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[IRDA]: irda-usb, unregister netdev when patch upload fails
[deliverable/linux.git] / drivers / net / irda / smsc-ircc2.c
CommitLineData
1da177e4
LT		 1/*********************************************************************
2 * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
3 *
4 * Description: Driver for the SMC Infrared Communications Controller
5 * Status: Experimental.
6 * Author: Daniele Peri (peri@csai.unipa.it)
527b6af4
DT		 7 * Created at:
8 * Modified at:
9 * Modified by:
10 *
1da177e4
LT		 11 * Copyright (c) 2002 Daniele Peri
12 * All Rights Reserved.
13 * Copyright (c) 2002 Jean Tourrilhes
c1e14a6e 14 * Copyright (c) 2006 Linus Walleij
1da177e4
LT		 15 *
16 *
17 * Based on smc-ircc.c:
18 *
19 * Copyright (c) 2001 Stefani Seibold
20 * Copyright (c) 1999-2001 Dag Brattli
527b6af4 21 * Copyright (c) 1998-1999 Thomas Davis,
1da177e4
LT		 22 *
23 * and irport.c:
24 *
25 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
26 *
527b6af4
DT		 27 *
28 * This program is free software; you can redistribute it and/or
29 * modify it under the terms of the GNU General Public License as
30 * published by the Free Software Foundation; either version 2 of
1da177e4 31 * the License, or (at your option) any later version.
527b6af4 32 *
1da177e4
LT		 33 * This program is distributed in the hope that it will be useful,
34 * but WITHOUT ANY WARRANTY; without even the implied warranty of
35 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36 * GNU General Public License for more details.
527b6af4
DT		 37 *
38 * You should have received a copy of the GNU General Public License
39 * along with this program; if not, write to the Free Software
40 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1da177e4
LT		 41 * MA 02111-1307 USA
42 *
43 ********************************************************************/
44
45#include <linux/module.h>
46#include <linux/kernel.h>
47#include <linux/types.h>
48#include <linux/skbuff.h>
49#include <linux/netdevice.h>
50#include <linux/ioport.h>
51#include <linux/delay.h>
52#include <linux/slab.h>
53#include <linux/init.h>
54#include <linux/rtnetlink.h>
55#include <linux/serial_reg.h>
56#include <linux/dma-mapping.h>
d052d1be 57#include <linux/platform_device.h>
1da177e4
LT		 58
59#include <asm/io.h>
60#include <asm/dma.h>
61#include <asm/byteorder.h>
62
63#include <linux/spinlock.h>
64#include <linux/pm.h>
c1e14a6e
LW		 65#ifdef CONFIG_PCI
66#include <linux/pci.h>
67#endif
1da177e4
LT		 68
69#include <net/irda/wrapper.h>
70#include <net/irda/irda.h>
71#include <net/irda/irda_device.h>
72
73#include "smsc-ircc2.h"
74#include "smsc-sio.h"
75
98b77773
DT		 76
77MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
78MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
79MODULE_LICENSE("GPL");
80
98b77773
DT		 81static int ircc_dma = 255;
82module_param(ircc_dma, int, 0);
83MODULE_PARM_DESC(ircc_dma, "DMA channel");
84
85static int ircc_irq = 255;
86module_param(ircc_irq, int, 0);
87MODULE_PARM_DESC(ircc_irq, "IRQ line");
88
89static int ircc_fir;
90module_param(ircc_fir, int, 0);
91MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
92
93static int ircc_sir;
94module_param(ircc_sir, int, 0);
95MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
96
97static int ircc_cfg;
98module_param(ircc_cfg, int, 0);
99MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
100
101static int ircc_transceiver;
102module_param(ircc_transceiver, int, 0);
103MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
104
1da177e4
LT		 105/* Types */
106
c1e14a6e
LW		 107#ifdef CONFIG_PCI
108struct smsc_ircc_subsystem_configuration {
109 unsigned short vendor; /* PCI vendor ID */
110 unsigned short device; /* PCI vendor ID */
111 unsigned short subvendor; /* PCI subsystem vendor ID */
112 unsigned short subdevice; /* PCI sybsystem device ID */
113 unsigned short sir_io; /* I/O port for SIR */
114 unsigned short fir_io; /* I/O port for FIR */
115 unsigned char fir_irq; /* FIR IRQ */
116 unsigned char fir_dma; /* FIR DMA */
117 unsigned short cfg_base; /* I/O port for chip configuration */
118 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
119 const char *name; /* name shown as info */
120};
121#endif
122
1da177e4
LT		 123struct smsc_transceiver {
124 char *name;
527b6af4 125 void (*set_for_speed)(int fir_base, u32 speed);
1da177e4
LT		 126 int (*probe)(int fir_base);
127};
1da177e4
LT		 128
129struct smsc_chip {
130 char *name;
131 #if 0
132 u8 type;
133 #endif
134 u16 flags;
135 u8 devid;
136 u8 rev;
137};
1da177e4
LT		 138
139struct smsc_chip_address {
140 unsigned int cfg_base;
141 unsigned int type;
142};
1da177e4
LT		 143
144/* Private data for each instance */
145struct smsc_ircc_cb {
146 struct net_device *netdev; /* Yes! we are some kind of netdevice */
147 struct net_device_stats stats;
148 struct irlap_cb *irlap; /* The link layer we are binded to */
527b6af4 149
1da177e4
LT		 150 chipio_t io; /* IrDA controller information */
151 iobuff_t tx_buff; /* Transmit buffer */
152 iobuff_t rx_buff; /* Receive buffer */
153 dma_addr_t tx_buff_dma;
154 dma_addr_t rx_buff_dma;
155
156 struct qos_info qos; /* QoS capabilities for this device */
157
158 spinlock_t lock; /* For serializing operations */
527b6af4 159
1da177e4
LT		 160 __u32 new_speed;
161 __u32 flags; /* Interface flags */
162
163 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
164 int tx_len; /* Number of frames in tx_buff */
165
166 int transceiver;
6bb3b2cd 167 struct platform_device *pldev;
1da177e4
LT		 168};
169
170/* Constants */
171
6bb3b2cd
DT		 172#define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
173
1da177e4
LT		 174#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
175#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
98b77773 176#define SMSC_IRCC2_C_NET_TIMEOUT 0
1da177e4
LT		 177#define SMSC_IRCC2_C_SIR_STOP 0
178
6bb3b2cd
DT		 179static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
180
1da177e4
LT		 181/* Prototypes */
182
183static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
184static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
185static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
186static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
187static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
188static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
80a90589
DT		 189static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
190static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
1da177e4
LT		 191static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
192static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
193static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
80a90589
DT		 194static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
195static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
0fa2f491
DT		 196static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
197static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
1da177e4
LT		 198static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs);
199static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
200static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
201#if SMSC_IRCC2_C_SIR_STOP
202static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
203#endif
204static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
205static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
206static int smsc_ircc_net_open(struct net_device *dev);
207static int smsc_ircc_net_close(struct net_device *dev);
208static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
209#if SMSC_IRCC2_C_NET_TIMEOUT
210static void smsc_ircc_timeout(struct net_device *dev);
211#endif
212static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
1da177e4
LT		 213static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
214static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
215static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
216static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
217
218/* Probing */
219static int __init smsc_ircc_look_for_chips(void);
b6158d23
DT		 220static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
221static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
222static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
1da177e4
LT		 223static int __init smsc_superio_fdc(unsigned short cfg_base);
224static int __init smsc_superio_lpc(unsigned short cfg_base);
c1e14a6e
LW		 225#ifdef CONFIG_PCI
226static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
227static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
228static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
229static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
230 unsigned short ircc_fir,
231 unsigned short ircc_sir,
232 unsigned char ircc_dma,
233 unsigned char ircc_irq);
234#endif
1da177e4
LT		 235
236/* Transceivers specific functions */
237
238static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
239static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
240static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
241static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
242static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
243static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
244
245/* Power Management */
246
3ae5eaec
RK		 247static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
248static int smsc_ircc_resume(struct platform_device *dev);
1da177e4 249
3ae5eaec 250static struct platform_driver smsc_ircc_driver = {
6bb3b2cd
DT		 251 .suspend = smsc_ircc_suspend,
252 .resume = smsc_ircc_resume,
3ae5eaec
RK		 253 .driver = {
254 .name = SMSC_IRCC2_DRIVER_NAME,
255 },
6bb3b2cd 256};
1da177e4
LT		 257
258/* Transceivers for SMSC-ircc */
259
b6158d23 260static struct smsc_transceiver smsc_transceivers[] =
1da177e4 261{
98b77773
DT		 262 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
263 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
264 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
265 { NULL, NULL }
1da177e4 266};
a956f4ca 267#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
1da177e4
LT		 268
269/* SMC SuperIO chipsets definitions */
270
271#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
272#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
273#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
274#define SIR 0 /* SuperIO Chip has only slow IRDA */
275#define FIR 4 /* SuperIO Chip has fast IRDA */
276#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
277
b6158d23 278static struct smsc_chip __initdata fdc_chips_flat[] =
1da177e4
LT		 279{
280 /* Base address 0x3f0 or 0x370 */
281 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
282 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
283 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
284 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
285 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
286 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
287 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
288 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
289 { NULL }
290};
291
b6158d23 292static struct smsc_chip __initdata fdc_chips_paged[] =
1da177e4
LT		 293{
294 /* Base address 0x3f0 or 0x370 */
295 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
296 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
297 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
298 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
299 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
300 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
301 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
302 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
303 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
304 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
305 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
306 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
307 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
308 { NULL }
309};
310
b6158d23 311static struct smsc_chip __initdata lpc_chips_flat[] =
1da177e4
LT		 312{
313 /* Base address 0x2E or 0x4E */
314 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
315 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
316 { NULL }
317};
318
b6158d23 319static struct smsc_chip __initdata lpc_chips_paged[] =
1da177e4
LT		 320{
321 /* Base address 0x2E or 0x4E */
322 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
323 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
324 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
325 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
326 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
327 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
328 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
329 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
330 { NULL }
331};
332
333#define SMSCSIO_TYPE_FDC 1
334#define SMSCSIO_TYPE_LPC 2
335#define SMSCSIO_TYPE_FLAT 4
336#define SMSCSIO_TYPE_PAGED 8
337
b6158d23 338static struct smsc_chip_address __initdata possible_addresses[] =
1da177e4 339{
98b77773
DT		 340 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
341 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
342 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
343 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
344 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
345 { 0, 0 }
1da177e4
LT		 346};
347
348/* Globals */
349
98b77773
DT		 350static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
351static unsigned short dev_count;
1da177e4
LT		 352
353static inline void register_bank(int iobase, int bank)
354{
98b77773
DT		 355 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
356 iobase + IRCC_MASTER);
1da177e4
LT		 357}
358
359
360/*******************************************************************************
361 *
362 *
363 * SMSC-ircc stuff
364 *
365 *
366 *******************************************************************************/
367
368/*
369 * Function smsc_ircc_init ()
370 *
371 * Initialize chip. Just try to find out how many chips we are dealing with
372 * and where they are
373 */
374static int __init smsc_ircc_init(void)
375{
6bb3b2cd 376 int ret;
1da177e4
LT		 377
378 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
379
3ae5eaec 380 ret = platform_driver_register(&smsc_ircc_driver);
6bb3b2cd
DT		 381 if (ret) {
382 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
383 return ret;
384 }
385
c1e14a6e
LW		 386#ifdef CONFIG_PCI
387 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
388 /* Ignore errors from preconfiguration */
389 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
390 }
391#endif
392
98b77773 393 dev_count = 0;
527b6af4 394
98b77773 395 if (ircc_fir > 0 && ircc_sir > 0) {
1da177e4
LT		 396 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
397 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
398
6bb3b2cd
DT		 399 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
400 ret = -ENODEV;
401 } else {
505db036 402 ret = -ENODEV;
1da177e4 403
6bb3b2cd
DT		 404 /* try user provided configuration register base address */
405 if (ircc_cfg > 0) {
406 IRDA_MESSAGE(" Overriding configuration address "
407 "0x%04x\n", ircc_cfg);
408 if (!smsc_superio_fdc(ircc_cfg))
409 ret = 0;
410 if (!smsc_superio_lpc(ircc_cfg))
411 ret = 0;
412 }
1da177e4 413
6bb3b2cd 414 if (smsc_ircc_look_for_chips() > 0)
1da177e4
LT		 415 ret = 0;
416 }
527b6af4 417
6bb3b2cd 418 if (ret)
3ae5eaec 419 platform_driver_unregister(&smsc_ircc_driver);
527b6af4 420
1da177e4
LT		 421 return ret;
422}
423
424/*
425 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
426 *
427 * Try to open driver instance
428 *
429 */
430static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
431{
432 struct smsc_ircc_cb *self;
433 struct net_device *dev;
434 int err;
527b6af4 435
1da177e4
LT		 436 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
437
438 err = smsc_ircc_present(fir_base, sir_base);
98b77773 439 if (err)
1da177e4 440 goto err_out;
527b6af4 441
1da177e4 442 err = -ENOMEM;
a956f4ca 443 if (dev_count >= ARRAY_SIZE(dev_self)) {
1da177e4
LT		 444 IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__);
445 goto err_out1;
446 }
447
448 /*
449 * Allocate new instance of the driver
450 */
451 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
452 if (!dev) {
453 IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__);
454 goto err_out1;
455 }
456
457 SET_MODULE_OWNER(dev);
458
459 dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
460#if SMSC_IRCC2_C_NET_TIMEOUT
461 dev->tx_timeout = smsc_ircc_timeout;
98b77773 462 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
1da177e4
LT		 463#endif
464 dev->open = smsc_ircc_net_open;
465 dev->stop = smsc_ircc_net_close;
466 dev->do_ioctl = smsc_ircc_net_ioctl;
467 dev->get_stats = smsc_ircc_net_get_stats;
527b6af4 468
da0841a0 469 self = netdev_priv(dev);
1da177e4
LT		 470 self->netdev = dev;
471
472 /* Make ifconfig display some details */
473 dev->base_addr = self->io.fir_base = fir_base;
474 dev->irq = self->io.irq = irq;
475
476 /* Need to store self somewhere */
6bb3b2cd 477 dev_self[dev_count] = self;
1da177e4
LT		 478 spin_lock_init(&self->lock);
479
527b6af4 480 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
1da177e4
LT		 481 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
482
483 self->rx_buff.head =
484 dma_alloc_coherent(NULL, self->rx_buff.truesize,
485 &self->rx_buff_dma, GFP_KERNEL);
486 if (self->rx_buff.head == NULL) {
487 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
488 driver_name);
489 goto err_out2;
490 }
491
492 self->tx_buff.head =
493 dma_alloc_coherent(NULL, self->tx_buff.truesize,
494 &self->tx_buff_dma, GFP_KERNEL);
495 if (self->tx_buff.head == NULL) {
496 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
497 driver_name);
498 goto err_out3;
499 }
500
501 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
502 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
503
504 self->rx_buff.in_frame = FALSE;
505 self->rx_buff.state = OUTSIDE_FRAME;
506 self->tx_buff.data = self->tx_buff.head;
507 self->rx_buff.data = self->rx_buff.head;
527b6af4 508
1da177e4 509 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
1da177e4 510 smsc_ircc_setup_qos(self);
1da177e4 511 smsc_ircc_init_chip(self);
527b6af4 512
98b77773
DT		 513 if (ircc_transceiver > 0 &&
514 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
1da177e4
LT		 515 self->transceiver = ircc_transceiver;
516 else
517 smsc_ircc_probe_transceiver(self);
518
519 err = register_netdev(self->netdev);
98b77773 520 if (err) {
1da177e4
LT		 521 IRDA_ERROR("%s, Network device registration failed!\n",
522 driver_name);
523 goto err_out4;
524 }
525
6bb3b2cd
DT		 526 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
527 dev_count, NULL, 0);
528 if (IS_ERR(self->pldev)) {
529 err = PTR_ERR(self->pldev);
530 goto err_out5;
531 }
3ae5eaec 532 platform_set_drvdata(self->pldev, self);
1da177e4
LT		 533
534 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
6bb3b2cd 535 dev_count++;
1da177e4
LT		 536
537 return 0;
98b77773 538
6bb3b2cd
DT		 539 err_out5:
540 unregister_netdev(self->netdev);
541
1da177e4
LT		 542 err_out4:
543 dma_free_coherent(NULL, self->tx_buff.truesize,
544 self->tx_buff.head, self->tx_buff_dma);
545 err_out3:
546 dma_free_coherent(NULL, self->rx_buff.truesize,
547 self->rx_buff.head, self->rx_buff_dma);
548 err_out2:
549 free_netdev(self->netdev);
6bb3b2cd 550 dev_self[dev_count] = NULL;
1da177e4
LT		 551 err_out1:
552 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
553 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
554 err_out:
555 return err;
556}
557
558/*
559 * Function smsc_ircc_present(fir_base, sir_base)
560 *
561 * Check the smsc-ircc chip presence
562 *
563 */
564static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
565{
566 unsigned char low, high, chip, config, dma, irq, version;
567
568 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
569 driver_name)) {
570 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
571 __FUNCTION__, fir_base);
572 goto out1;
573 }
574
575 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
576 driver_name)) {
577 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
578 __FUNCTION__, sir_base);
579 goto out2;
580 }
581
582 register_bank(fir_base, 3);
583
98b77773
DT		 584 high = inb(fir_base + IRCC_ID_HIGH);
585 low = inb(fir_base + IRCC_ID_LOW);
586 chip = inb(fir_base + IRCC_CHIP_ID);
587 version = inb(fir_base + IRCC_VERSION);
588 config = inb(fir_base + IRCC_INTERFACE);
1da177e4
LT		 589 dma = config & IRCC_INTERFACE_DMA_MASK;
590 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
591
527b6af4 592 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
98b77773 593 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
1da177e4
LT		 594 __FUNCTION__, fir_base);
595 goto out3;
596 }
597 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
598 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
599 chip & 0x0f, version, fir_base, sir_base, dma, irq);
600
601 return 0;
98b77773 602
1da177e4
LT		 603 out3:
604 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
605 out2:
606 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
607 out1:
608 return -ENODEV;
609}
610
611/*
612 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
613 *
614 * Setup I/O
615 *
616 */
527b6af4
DT		 617static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
618 unsigned int fir_base, unsigned int sir_base,
1da177e4
LT		 619 u8 dma, u8 irq)
620{
621 unsigned char config, chip_dma, chip_irq;
622
623 register_bank(fir_base, 3);
98b77773
DT		 624 config = inb(fir_base + IRCC_INTERFACE);
625 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
626 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
1da177e4
LT		 627
628 self->io.fir_base = fir_base;
629 self->io.sir_base = sir_base;
630 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
631 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
632 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
633 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
634
635 if (irq < 255) {
636 if (irq != chip_irq)
637 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
638 driver_name, chip_irq, irq);
639 self->io.irq = irq;
98b77773 640 } else
1da177e4 641 self->io.irq = chip_irq;
527b6af4 642
1da177e4
LT		 643 if (dma < 255) {
644 if (dma != chip_dma)
645 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
646 driver_name, chip_dma, dma);
647 self->io.dma = dma;
98b77773 648 } else
1da177e4
LT		 649 self->io.dma = chip_dma;
650
651}
652
653/*
654 * Function smsc_ircc_setup_qos(self)
655 *
656 * Setup qos
657 *
658 */
659static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
660{
661 /* Initialize QoS for this device */
662 irda_init_max_qos_capabilies(&self->qos);
527b6af4 663
1da177e4
LT		 664 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
665 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
666
667 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
668 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
669 irda_qos_bits_to_value(&self->qos);
670}
671
672/*
673 * Function smsc_ircc_init_chip(self)
674 *
675 * Init chip
676 *
677 */
678static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
679{
e812cb52 680 int iobase = self->io.fir_base;
1da177e4
LT		 681
682 register_bank(iobase, 0);
98b77773
DT		 683 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
684 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 685
686 register_bank(iobase, 1);
e812cb52 687 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
98b77773 688 iobase + IRCC_SCE_CFGA);
1da177e4
LT		 689
690#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 691 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
692 iobase + IRCC_SCE_CFGB);
527b6af4 693#else
98b77773
DT		 694 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
695 iobase + IRCC_SCE_CFGB);
527b6af4 696#endif
98b77773
DT		 697 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
698 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
527b6af4 699
1da177e4 700 register_bank(iobase, 4);
e812cb52 701 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
527b6af4 702
1da177e4 703 register_bank(iobase, 0);
e812cb52 704 outb(0, iobase + IRCC_LCR_A);
1da177e4
LT		 705
706 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
527b6af4 707
1da177e4 708 /* Power on device */
98b77773 709 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 710}
711
712/*
713 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
714 *
715 * Process IOCTL commands for this device
716 *
717 */
718static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
719{
720 struct if_irda_req *irq = (struct if_irda_req *) rq;
721 struct smsc_ircc_cb *self;
722 unsigned long flags;
723 int ret = 0;
724
725 IRDA_ASSERT(dev != NULL, return -1;);
726
da0841a0 727 self = netdev_priv(dev);
1da177e4
LT		 728
729 IRDA_ASSERT(self != NULL, return -1;);
730
731 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
527b6af4 732
1da177e4
LT		 733 switch (cmd) {
734 case SIOCSBANDWIDTH: /* Set bandwidth */
735 if (!capable(CAP_NET_ADMIN))
736 ret = -EPERM;
737 else {
738 /* Make sure we are the only one touching
739 * self->io.speed and the hardware - Jean II */
740 spin_lock_irqsave(&self->lock, flags);
741 smsc_ircc_change_speed(self, irq->ifr_baudrate);
742 spin_unlock_irqrestore(&self->lock, flags);
743 }
744 break;
745 case SIOCSMEDIABUSY: /* Set media busy */
746 if (!capable(CAP_NET_ADMIN)) {
747 ret = -EPERM;
748 break;
749 }
750
751 irda_device_set_media_busy(self->netdev, TRUE);
752 break;
753 case SIOCGRECEIVING: /* Check if we are receiving right now */
754 irq->ifr_receiving = smsc_ircc_is_receiving(self);
755 break;
756 #if 0
757 case SIOCSDTRRTS:
758 if (!capable(CAP_NET_ADMIN)) {
759 ret = -EPERM;
760 break;
761 }
762 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
763 break;
764 #endif
765 default:
766 ret = -EOPNOTSUPP;
767 }
527b6af4 768
1da177e4
LT		 769 return ret;
770}
771
772static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
773{
da0841a0 774 struct smsc_ircc_cb *self = netdev_priv(dev);
527b6af4 775
1da177e4
LT		 776 return &self->stats;
777}
778
779#if SMSC_IRCC2_C_NET_TIMEOUT
780/*
781 * Function smsc_ircc_timeout (struct net_device *dev)
782 *
783 * The networking timeout management.
784 *
785 */
786
787static void smsc_ircc_timeout(struct net_device *dev)
788{
da0841a0 789 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 790 unsigned long flags;
791
1da177e4
LT		 792 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
793 dev->name, self->io.speed);
794 spin_lock_irqsave(&self->lock, flags);
795 smsc_ircc_sir_start(self);
796 smsc_ircc_change_speed(self, self->io.speed);
797 dev->trans_start = jiffies;
798 netif_wake_queue(dev);
799 spin_unlock_irqrestore(&self->lock, flags);
800}
801#endif
802
803/*
804 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
805 *
806 * Transmits the current frame until FIFO is full, then
807 * waits until the next transmit interrupt, and continues until the
808 * frame is transmitted.
809 */
810int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
811{
812 struct smsc_ircc_cb *self;
813 unsigned long flags;
1da177e4
LT		 814 s32 speed;
815
816 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
817
818 IRDA_ASSERT(dev != NULL, return 0;);
527b6af4 819
da0841a0 820 self = netdev_priv(dev);
1da177e4
LT		 821 IRDA_ASSERT(self != NULL, return 0;);
822
1da177e4 823 netif_stop_queue(dev);
527b6af4 824
1da177e4
LT		 825 /* Make sure test of self->io.speed & speed change are atomic */
826 spin_lock_irqsave(&self->lock, flags);
827
828 /* Check if we need to change the speed */
829 speed = irda_get_next_speed(skb);
98b77773 830 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 831 /* Check for empty frame */
832 if (!skb->len) {
833 /*
834 * We send frames one by one in SIR mode (no
835 * pipelining), so at this point, if we were sending
836 * a previous frame, we just received the interrupt
837 * telling us it is finished (UART_IIR_THRI).
838 * Therefore, waiting for the transmitter to really
839 * finish draining the fifo won't take too long.
840 * And the interrupt handler is not expected to run.
841 * - Jean II */
842 smsc_ircc_sir_wait_hw_transmitter_finish(self);
843 smsc_ircc_change_speed(self, speed);
844 spin_unlock_irqrestore(&self->lock, flags);
845 dev_kfree_skb(skb);
846 return 0;
1da177e4 847 }
98b77773 848 self->new_speed = speed;
1da177e4
LT		 849 }
850
851 /* Init tx buffer */
852 self->tx_buff.data = self->tx_buff.head;
853
854 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
527b6af4 855 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
1da177e4 856 self->tx_buff.truesize);
527b6af4 857
1da177e4
LT		 858 self->stats.tx_bytes += self->tx_buff.len;
859
860 /* Turn on transmit finished interrupt. Will fire immediately! */
80a90589 861 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
1da177e4
LT		 862
863 spin_unlock_irqrestore(&self->lock, flags);
864
865 dev_kfree_skb(skb);
527b6af4 866
1da177e4
LT		 867 return 0;
868}
869
870/*
871 * Function smsc_ircc_set_fir_speed (self, baud)
872 *
873 * Change the speed of the device
874 *
875 */
876static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
877{
878 int fir_base, ir_mode, ctrl, fast;
879
880 IRDA_ASSERT(self != NULL, return;);
881 fir_base = self->io.fir_base;
882
883 self->io.speed = speed;
884
98b77773 885 switch (speed) {
1da177e4 886 default:
527b6af4 887 case 576000:
1da177e4
LT		 888 ir_mode = IRCC_CFGA_IRDA_HDLC;
889 ctrl = IRCC_CRC;
890 fast = 0;
891 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
892 break;
893 case 1152000:
894 ir_mode = IRCC_CFGA_IRDA_HDLC;
895 ctrl = IRCC_1152 | IRCC_CRC;
896 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
897 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
898 __FUNCTION__);
899 break;
900 case 4000000:
901 ir_mode = IRCC_CFGA_IRDA_4PPM;
902 ctrl = IRCC_CRC;
903 fast = IRCC_LCR_A_FAST;
904 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
905 __FUNCTION__);
906 break;
907 }
908 #if 0
909 Now in tranceiver!
910 /* This causes an interrupt */
911 register_bank(fir_base, 0);
98b77773 912 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
1da177e4 913 #endif
527b6af4 914
1da177e4 915 register_bank(fir_base, 1);
98b77773 916 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
527b6af4 917
1da177e4 918 register_bank(fir_base, 4);
98b77773 919 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
1da177e4
LT		 920}
921
922/*
923 * Function smsc_ircc_fir_start(self)
924 *
925 * Change the speed of the device
926 *
927 */
928static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
929{
930 struct net_device *dev;
931 int fir_base;
932
933 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
934
935 IRDA_ASSERT(self != NULL, return;);
936 dev = self->netdev;
937 IRDA_ASSERT(dev != NULL, return;);
938
939 fir_base = self->io.fir_base;
940
941 /* Reset everything */
942
943 /* Install FIR transmit handler */
527b6af4 944 dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
1da177e4
LT		 945
946 /* Clear FIFO */
98b77773 947 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1da177e4
LT		 948
949 /* Enable interrupt */
98b77773 950 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1da177e4
LT		 951
952 register_bank(fir_base, 1);
953
527b6af4 954 /* Select the TX/RX interface */
1da177e4 955#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 956 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
957 fir_base + IRCC_SCE_CFGB);
527b6af4 958#else
98b77773
DT		 959 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
960 fir_base + IRCC_SCE_CFGB);
527b6af4 961#endif
98b77773 962 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1da177e4
LT		 963
964 /* Enable SCE interrupts */
98b77773 965 outb(0, fir_base + IRCC_MASTER);
1da177e4 966 register_bank(fir_base, 0);
98b77773
DT		 967 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
968 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1da177e4
LT		 969}
970
971/*
972 * Function smsc_ircc_fir_stop(self, baud)
973 *
974 * Change the speed of the device
975 *
976 */
977static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
978{
979 int fir_base;
980
981 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 982
1da177e4
LT		 983 IRDA_ASSERT(self != NULL, return;);
984
985 fir_base = self->io.fir_base;
986 register_bank(fir_base, 0);
98b77773
DT		 987 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
988 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1da177e4
LT		 989}
990
991
992/*
993 * Function smsc_ircc_change_speed(self, baud)
994 *
995 * Change the speed of the device
996 *
997 * This function *must* be called with spinlock held, because it may
998 * be called from the irq handler. - Jean II
999 */
0fa2f491 1000static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1da177e4 1001{
1da177e4 1002 struct net_device *dev;
1da177e4 1003 int last_speed_was_sir;
527b6af4 1004
1da177e4
LT		 1005 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed);
1006
1007 IRDA_ASSERT(self != NULL, return;);
1008 dev = self->netdev;
1da177e4
LT		 1009
1010 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1011
1012 #if 0
1013 /* Temp Hack */
1014 speed= 1152000;
1015 self->io.speed = speed;
1016 last_speed_was_sir = 0;
527b6af4 1017 smsc_ircc_fir_start(self);
1da177e4 1018 #endif
527b6af4 1019
98b77773 1020 if (self->io.speed == 0)
1da177e4
LT		 1021 smsc_ircc_sir_start(self);
1022
1023 #if 0
98b77773 1024 if (!last_speed_was_sir) speed = self->io.speed;
1da177e4
LT		 1025 #endif
1026
98b77773
DT		 1027 if (self->io.speed != speed)
1028 smsc_ircc_set_transceiver_for_speed(self, speed);
1da177e4
LT		 1029
1030 self->io.speed = speed;
527b6af4 1031
98b77773
DT		 1032 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1033 if (!last_speed_was_sir) {
1da177e4
LT		 1034 smsc_ircc_fir_stop(self);
1035 smsc_ircc_sir_start(self);
1036 }
527b6af4 1037 smsc_ircc_set_sir_speed(self, speed);
98b77773
DT		 1038 } else {
1039 if (last_speed_was_sir) {
527b6af4 1040 #if SMSC_IRCC2_C_SIR_STOP
1da177e4
LT		 1041 smsc_ircc_sir_stop(self);
1042 #endif
1043 smsc_ircc_fir_start(self);
1044 }
1045 smsc_ircc_set_fir_speed(self, speed);
1046
1047 #if 0
1048 self->tx_buff.len = 10;
1049 self->tx_buff.data = self->tx_buff.head;
527b6af4 1050
80a90589 1051 smsc_ircc_dma_xmit(self, 4000);
1da177e4
LT		 1052 #endif
1053 /* Be ready for incoming frames */
80a90589 1054 smsc_ircc_dma_receive(self);
1da177e4 1055 }
527b6af4 1056
1da177e4
LT		 1057 netif_wake_queue(dev);
1058}
1059
1060/*
1061 * Function smsc_ircc_set_sir_speed (self, speed)
1062 *
1063 * Set speed of IrDA port to specified baudrate
1064 *
1065 */
0fa2f491 1066void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1da177e4 1067{
527b6af4 1068 int iobase;
1da177e4
LT		 1069 int fcr; /* FIFO control reg */
1070 int lcr; /* Line control reg */
1071 int divisor;
1072
1073 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed);
1074
1075 IRDA_ASSERT(self != NULL, return;);
1076 iobase = self->io.sir_base;
527b6af4 1077
1da177e4
LT		 1078 /* Update accounting for new speed */
1079 self->io.speed = speed;
1080
1081 /* Turn off interrupts */
98b77773 1082 outb(0, iobase + UART_IER);
1da177e4 1083
98b77773 1084 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
527b6af4 1085
1da177e4
LT		 1086 fcr = UART_FCR_ENABLE_FIFO;
1087
527b6af4 1088 /*
1da177e4
LT		 1089 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1090 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
527b6af4 1091 * about this timeout since it will always be fast enough.
1da177e4 1092 */
98b77773
DT		 1093 fcr |= self->io.speed < 38400 ?
1094 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
527b6af4 1095
1da177e4
LT		 1096 /* IrDA ports use 8N1 */
1097 lcr = UART_LCR_WLEN8;
527b6af4 1098
98b77773
DT		 1099 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1100 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1101 outb(divisor >> 8, iobase + UART_DLM);
1102 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1103 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1da177e4
LT		 1104
1105 /* Turn on interrups */
98b77773 1106 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1da177e4
LT		 1107
1108 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed);
1109}
1110
1111
1112/*
1113 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1114 *
1115 * Transmit the frame!
1116 *
1117 */
1118static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1119{
1120 struct smsc_ircc_cb *self;
1121 unsigned long flags;
1122 s32 speed;
1da177e4
LT		 1123 int mtt;
1124
1125 IRDA_ASSERT(dev != NULL, return 0;);
da0841a0 1126 self = netdev_priv(dev);
1da177e4
LT		 1127 IRDA_ASSERT(self != NULL, return 0;);
1128
1da177e4
LT		 1129 netif_stop_queue(dev);
1130
1131 /* Make sure test of self->io.speed & speed change are atomic */
1132 spin_lock_irqsave(&self->lock, flags);
1133
1134 /* Check if we need to change the speed after this frame */
1135 speed = irda_get_next_speed(skb);
98b77773 1136 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 1137 /* Check for empty frame */
1138 if (!skb->len) {
1139 /* Note : you should make sure that speed changes
1140 * are not going to corrupt any outgoing frame.
1141 * Look at nsc-ircc for the gory details - Jean II */
527b6af4 1142 smsc_ircc_change_speed(self, speed);
1da177e4
LT		 1143 spin_unlock_irqrestore(&self->lock, flags);
1144 dev_kfree_skb(skb);
1145 return 0;
98b77773
DT		 1146 }
1147
1148 self->new_speed = speed;
1da177e4 1149 }
527b6af4 1150
1da177e4
LT		 1151 memcpy(self->tx_buff.head, skb->data, skb->len);
1152
1153 self->tx_buff.len = skb->len;
1154 self->tx_buff.data = self->tx_buff.head;
527b6af4
DT		 1155
1156 mtt = irda_get_mtt(skb);
1da177e4
LT		 1157 if (mtt) {
1158 int bofs;
1159
527b6af4 1160 /*
1da177e4
LT		 1161 * Compute how many BOFs (STA or PA's) we need to waste the
1162 * min turn time given the speed of the link.
1163 */
1164 bofs = mtt * (self->io.speed / 1000) / 8000;
1165 if (bofs > 4095)
1166 bofs = 4095;
1167
80a90589 1168 smsc_ircc_dma_xmit(self, bofs);
1da177e4
LT		 1169 } else {
1170 /* Transmit frame */
80a90589 1171 smsc_ircc_dma_xmit(self, 0);
1da177e4 1172 }
98b77773 1173
1da177e4
LT		 1174 spin_unlock_irqrestore(&self->lock, flags);
1175 dev_kfree_skb(skb);
1176
1177 return 0;
1178}
1179
1180/*
80a90589 1181 * Function smsc_ircc_dma_xmit (self, bofs)
1da177e4
LT		 1182 *
1183 * Transmit data using DMA
1184 *
1185 */
80a90589 1186static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1da177e4 1187{
80a90589 1188 int iobase = self->io.fir_base;
1da177e4
LT		 1189 u8 ctrl;
1190
1191 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1192#if 1
1193 /* Disable Rx */
1194 register_bank(iobase, 0);
98b77773 1195 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1196#endif
1197 register_bank(iobase, 1);
98b77773
DT		 1198 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1199 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1200
1201 self->io.direction = IO_XMIT;
1202
1203 /* Set BOF additional count for generating the min turn time */
1204 register_bank(iobase, 4);
98b77773
DT		 1205 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1206 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1207 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1da177e4
LT		 1208
1209 /* Set max Tx frame size */
98b77773
DT		 1210 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1211 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1da177e4
LT		 1212
1213 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
527b6af4 1214
1da177e4
LT		 1215 /* Enable burst mode chip Tx DMA */
1216 register_bank(iobase, 1);
98b77773
DT		 1217 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1218 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1219
1220 /* Setup DMA controller (must be done after enabling chip DMA) */
1221 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1222 DMA_TX_MODE);
1223
1224 /* Enable interrupt */
1225
1226 register_bank(iobase, 0);
98b77773
DT		 1227 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1228 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
527b6af4 1229
1da177e4 1230 /* Enable transmit */
98b77773 1231 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1da177e4
LT		 1232}
1233
1234/*
1235 * Function smsc_ircc_dma_xmit_complete (self)
1236 *
527b6af4 1237 * The transfer of a frame in finished. This function will only be called
1da177e4
LT		 1238 * by the interrupt handler
1239 *
1240 */
80a90589 1241static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1da177e4 1242{
80a90589
DT		 1243 int iobase = self->io.fir_base;
1244
1da177e4
LT		 1245 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1246#if 0
1247 /* Disable Tx */
1248 register_bank(iobase, 0);
98b77773 1249 outb(0x00, iobase + IRCC_LCR_B);
1da177e4 1250#endif
80a90589
DT		 1251 register_bank(iobase, 1);
1252 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1253 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1254
1255 /* Check for underrun! */
1256 register_bank(iobase, 0);
98b77773 1257 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1da177e4
LT		 1258 self->stats.tx_errors++;
1259 self->stats.tx_fifo_errors++;
1260
1261 /* Reset error condition */
1262 register_bank(iobase, 0);
98b77773
DT		 1263 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1264 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 1265 } else {
1266 self->stats.tx_packets++;
98b77773 1267 self->stats.tx_bytes += self->tx_buff.len;
1da177e4
LT		 1268 }
1269
1270 /* Check if it's time to change the speed */
1271 if (self->new_speed) {
527b6af4 1272 smsc_ircc_change_speed(self, self->new_speed);
1da177e4
LT		 1273 self->new_speed = 0;
1274 }
1275
1276 netif_wake_queue(self->netdev);
1277}
1278
1279/*
1280 * Function smsc_ircc_dma_receive(self)
1281 *
1282 * Get ready for receiving a frame. The device will initiate a DMA
1283 * if it starts to receive a frame.
1284 *
1285 */
80a90589 1286static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1da177e4 1287{
80a90589 1288 int iobase = self->io.fir_base;
1da177e4
LT		 1289#if 0
1290 /* Turn off chip DMA */
1291 register_bank(iobase, 1);
98b77773
DT		 1292 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1293 iobase + IRCC_SCE_CFGB);
1da177e4 1294#endif
527b6af4 1295
1da177e4
LT		 1296 /* Disable Tx */
1297 register_bank(iobase, 0);
98b77773 1298 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1299
1300 /* Turn off chip DMA */
1301 register_bank(iobase, 1);
98b77773
DT		 1302 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1303 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1304
1305 self->io.direction = IO_RECV;
1306 self->rx_buff.data = self->rx_buff.head;
1307
1308 /* Set max Rx frame size */
1309 register_bank(iobase, 4);
98b77773
DT		 1310 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1311 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1da177e4
LT		 1312
1313 /* Setup DMA controller */
1314 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1315 DMA_RX_MODE);
1316
1317 /* Enable burst mode chip Rx DMA */
1318 register_bank(iobase, 1);
98b77773
DT		 1319 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1320 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1321
1322 /* Enable interrupt */
1323 register_bank(iobase, 0);
98b77773
DT		 1324 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1325 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1da177e4
LT		 1326
1327 /* Enable receiver */
1328 register_bank(iobase, 0);
527b6af4 1329 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
98b77773 1330 iobase + IRCC_LCR_B);
527b6af4 1331
1da177e4
LT		 1332 return 0;
1333}
1334
1335/*
80a90589 1336 * Function smsc_ircc_dma_receive_complete(self)
1da177e4
LT		 1337 *
1338 * Finished with receiving frames
1339 *
1340 */
80a90589 1341static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1da177e4
LT		 1342{
1343 struct sk_buff *skb;
1344 int len, msgcnt, lsr;
80a90589 1345 int iobase = self->io.fir_base;
527b6af4 1346
1da177e4 1347 register_bank(iobase, 0);
527b6af4 1348
1da177e4
LT		 1349 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1350#if 0
1351 /* Disable Rx */
1352 register_bank(iobase, 0);
98b77773 1353 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1354#endif
1355 register_bank(iobase, 0);
98b77773
DT		 1356 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1357 lsr= inb(iobase + IRCC_LSR);
1358 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1da177e4
LT		 1359
1360 IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__,
1361 get_dma_residue(self->io.dma));
1362
1363 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1364
98b77773
DT		 1365 /* Look for errors */
1366 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1da177e4 1367 self->stats.rx_errors++;
98b77773
DT		 1368 if (lsr & IRCC_LSR_FRAME_ERROR)
1369 self->stats.rx_frame_errors++;
1370 if (lsr & IRCC_LSR_CRC_ERROR)
1371 self->stats.rx_crc_errors++;
1372 if (lsr & IRCC_LSR_SIZE_ERROR)
1373 self->stats.rx_length_errors++;
1374 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1375 self->stats.rx_length_errors++;
1da177e4
LT		 1376 return;
1377 }
98b77773 1378
1da177e4 1379 /* Remove CRC */
98b77773 1380 len -= self->io.speed < 4000000 ? 2 : 4;
1da177e4 1381
98b77773 1382 if (len < 2 || len > 2050) {
1da177e4
LT		 1383 IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
1384 return;
1385 }
1386 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
1387
98b77773
DT		 1388 skb = dev_alloc_skb(len + 1);
1389 if (!skb) {
1da177e4
LT		 1390 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1391 __FUNCTION__);
1392 return;
527b6af4 1393 }
1da177e4 1394 /* Make sure IP header gets aligned */
527b6af4 1395 skb_reserve(skb, 1);
1da177e4
LT		 1396
1397 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1398 self->stats.rx_packets++;
1399 self->stats.rx_bytes += len;
1400
1401 skb->dev = self->netdev;
1402 skb->mac.raw = skb->data;
1403 skb->protocol = htons(ETH_P_IRDA);
1404 netif_rx(skb);
1405}
1406
1407/*
1408 * Function smsc_ircc_sir_receive (self)
1409 *
1410 * Receive one frame from the infrared port
1411 *
1412 */
527b6af4 1413static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1da177e4
LT		 1414{
1415 int boguscount = 0;
1416 int iobase;
1417
1418 IRDA_ASSERT(self != NULL, return;);
1419
1420 iobase = self->io.sir_base;
1421
527b6af4
DT		 1422 /*
1423 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1424 * async_unwrap_char will deliver all found frames
1da177e4
LT		 1425 */
1426 do {
527b6af4 1427 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
98b77773 1428 inb(iobase + UART_RX));
1da177e4
LT		 1429
1430 /* Make sure we don't stay here to long */
1431 if (boguscount++ > 32) {
1432 IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__);
1433 break;
1434 }
98b77773 1435 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1da177e4
LT		 1436}
1437
1438
1439/*
1440 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1441 *
1442 * An interrupt from the chip has arrived. Time to do some work
1443 *
1444 */
1445static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1446{
1447 struct net_device *dev = (struct net_device *) dev_id;
1448 struct smsc_ircc_cb *self;
1449 int iobase, iir, lcra, lsr;
1450 irqreturn_t ret = IRQ_NONE;
1451
1452 if (dev == NULL) {
527b6af4 1453 printk(KERN_WARNING "%s: irq %d for unknown device.\n",
1da177e4
LT		 1454 driver_name, irq);
1455 goto irq_ret;
1456 }
da0841a0
DT		 1457
1458 self = netdev_priv(dev);
1da177e4
LT		 1459 IRDA_ASSERT(self != NULL, return IRQ_NONE;);
1460
1461 /* Serialise the interrupt handler in various CPUs, stop Tx path */
527b6af4 1462 spin_lock(&self->lock);
1da177e4
LT		 1463
1464 /* Check if we should use the SIR interrupt handler */
98b77773 1465 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1da177e4
LT		 1466 ret = smsc_ircc_interrupt_sir(dev);
1467 goto irq_ret_unlock;
1468 }
1469
1470 iobase = self->io.fir_base;
1471
1472 register_bank(iobase, 0);
98b77773 1473 iir = inb(iobase + IRCC_IIR);
527b6af4 1474 if (iir == 0)
1da177e4
LT		 1475 goto irq_ret_unlock;
1476 ret = IRQ_HANDLED;
1477
1478 /* Disable interrupts */
98b77773
DT		 1479 outb(0, iobase + IRCC_IER);
1480 lcra = inb(iobase + IRCC_LCR_A);
1481 lsr = inb(iobase + IRCC_LSR);
527b6af4 1482
1da177e4
LT		 1483 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1484
1485 if (iir & IRCC_IIR_EOM) {
1486 if (self->io.direction == IO_RECV)
80a90589 1487 smsc_ircc_dma_receive_complete(self);
1da177e4 1488 else
80a90589 1489 smsc_ircc_dma_xmit_complete(self);
527b6af4 1490
80a90589 1491 smsc_ircc_dma_receive(self);
1da177e4
LT		 1492 }
1493
1494 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1495 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/
1496 }
1497
1498 /* Enable interrupts again */
1499
1500 register_bank(iobase, 0);
98b77773 1501 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1da177e4
LT		 1502
1503 irq_ret_unlock:
1504 spin_unlock(&self->lock);
1505 irq_ret:
1506 return ret;
1507}
1508
1509/*
1510 * Function irport_interrupt_sir (irq, dev_id, regs)
1511 *
1512 * Interrupt handler for SIR modes
1513 */
1514static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1515{
da0841a0 1516 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 1517 int boguscount = 0;
1518 int iobase;
1519 int iir, lsr;
1520
1521 /* Already locked comming here in smsc_ircc_interrupt() */
1522 /*spin_lock(&self->lock);*/
1523
1524 iobase = self->io.sir_base;
1525
98b77773 1526 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1527 if (iir == 0)
1528 return IRQ_NONE;
1529 while (iir) {
1530 /* Clear interrupt */
98b77773 1531 lsr = inb(iobase + UART_LSR);
1da177e4 1532
527b6af4 1533 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1da177e4
LT		 1534 __FUNCTION__, iir, lsr, iobase);
1535
1536 switch (iir) {
1537 case UART_IIR_RLSI:
1538 IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__);
1539 break;
1540 case UART_IIR_RDI:
1541 /* Receive interrupt */
1542 smsc_ircc_sir_receive(self);
1543 break;
1544 case UART_IIR_THRI:
1545 if (lsr & UART_LSR_THRE)
1546 /* Transmitter ready for data */
1547 smsc_ircc_sir_write_wakeup(self);
1548 break;
1549 default:
1550 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1551 __FUNCTION__, iir);
1552 break;
527b6af4
DT		 1553 }
1554
1da177e4
LT		 1555 /* Make sure we don't stay here to long */
1556 if (boguscount++ > 100)
1557 break;
1558
527b6af4 1559 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1560 }
1561 /*spin_unlock(&self->lock);*/
1562 return IRQ_HANDLED;
1563}
1564
1565
1566#if 0 /* unused */
1567/*
1568 * Function ircc_is_receiving (self)
1569 *
1570 * Return TRUE is we are currently receiving a frame
1571 *
1572 */
1573static int ircc_is_receiving(struct smsc_ircc_cb *self)
1574{
1575 int status = FALSE;
1576 /* int iobase; */
1577
1578 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1579
1580 IRDA_ASSERT(self != NULL, return FALSE;);
1581
1582 IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__,
1583 get_dma_residue(self->io.dma));
1584
1585 status = (self->rx_buff.state != OUTSIDE_FRAME);
527b6af4 1586
1da177e4
LT		 1587 return status;
1588}
1589#endif /* unused */
1590
e812cb52
DT		 1591static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1592{
1593 int error;
1594
1595 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1596 self->netdev->name, self->netdev);
1597 if (error)
1598 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
1599 __FUNCTION__, self->io.irq, error);
1600
1601 return error;
1602}
1603
1604static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1605{
1606 unsigned long flags;
1607
1608 spin_lock_irqsave(&self->lock, flags);
1609
1610 self->io.speed = 0;
1611 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1612
1613 spin_unlock_irqrestore(&self->lock, flags);
1614}
1615
1616static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1617{
1618 int iobase = self->io.fir_base;
1619 unsigned long flags;
1620
1621 spin_lock_irqsave(&self->lock, flags);
1622
1623 register_bank(iobase, 0);
1624 outb(0, iobase + IRCC_IER);
1625 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1626 outb(0x00, iobase + IRCC_MASTER);
1627
1628 spin_unlock_irqrestore(&self->lock, flags);
1629}
1630
1da177e4
LT		 1631
1632/*
1633 * Function smsc_ircc_net_open (dev)
1634 *
1635 * Start the device
1636 *
1637 */
1638static int smsc_ircc_net_open(struct net_device *dev)
1639{
1640 struct smsc_ircc_cb *self;
1da177e4 1641 char hwname[16];
1da177e4
LT		 1642
1643 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 1644
1da177e4 1645 IRDA_ASSERT(dev != NULL, return -1;);
da0841a0 1646 self = netdev_priv(dev);
1da177e4 1647 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1648
e812cb52
DT		 1649 if (self->io.suspended) {
1650 IRDA_DEBUG(0, "%s(), device is suspended\n", __FUNCTION__);
1651 return -EAGAIN;
1652 }
1653
527b6af4 1654 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1da177e4
LT		 1655 (void *) dev)) {
1656 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1657 __FUNCTION__, self->io.irq);
1658 return -EAGAIN;
1659 }
1660
e812cb52 1661 smsc_ircc_start_interrupts(self);
527b6af4 1662
1da177e4
LT		 1663 /* Give self a hardware name */
1664 /* It would be cool to offer the chip revision here - Jean II */
1665 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1666
527b6af4 1667 /*
1da177e4 1668 * Open new IrLAP layer instance, now that everything should be
527b6af4 1669 * initialized properly
1da177e4
LT		 1670 */
1671 self->irlap = irlap_open(dev, &self->qos, hwname);
1672
1673 /*
1674 * Always allocate the DMA channel after the IRQ,
1675 * and clean up on failure.
1676 */
1677 if (request_dma(self->io.dma, dev->name)) {
1678 smsc_ircc_net_close(dev);
1679
1680 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1681 __FUNCTION__, self->io.dma);
1682 return -EAGAIN;
1683 }
527b6af4 1684
1da177e4
LT		 1685 netif_start_queue(dev);
1686
1687 return 0;
1688}
1689
1690/*
1691 * Function smsc_ircc_net_close (dev)
1692 *
1693 * Stop the device
1694 *
1695 */
1696static int smsc_ircc_net_close(struct net_device *dev)
1697{
1698 struct smsc_ircc_cb *self;
1da177e4
LT		 1699
1700 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 1701
1da177e4 1702 IRDA_ASSERT(dev != NULL, return -1;);
da0841a0 1703 self = netdev_priv(dev);
1da177e4 1704 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1705
1da177e4
LT		 1706 /* Stop device */
1707 netif_stop_queue(dev);
527b6af4 1708
1da177e4
LT		 1709 /* Stop and remove instance of IrLAP */
1710 if (self->irlap)
1711 irlap_close(self->irlap);
1712 self->irlap = NULL;
1713
e812cb52
DT		 1714 smsc_ircc_stop_interrupts(self);
1715
1716 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1717 if (!self->io.suspended)
1718 free_irq(self->io.irq, dev);
1719
1da177e4 1720 disable_dma(self->io.dma);
1da177e4
LT		 1721 free_dma(self->io.dma);
1722
1723 return 0;
1724}
1725
3ae5eaec 1726static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1727{
3ae5eaec 1728 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
6bb3b2cd 1729
9480e307 1730 if (!self->io.suspended) {
e812cb52
DT		 1731 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1732
1733 rtnl_lock();
1734 if (netif_running(self->netdev)) {
1735 netif_device_detach(self->netdev);
1736 smsc_ircc_stop_interrupts(self);
1737 free_irq(self->io.irq, self->netdev);
1738 disable_dma(self->io.dma);
1739 }
98b77773 1740 self->io.suspended = 1;
e812cb52 1741 rtnl_unlock();
98b77773 1742 }
6bb3b2cd
DT		 1743
1744 return 0;
1da177e4
LT		 1745}
1746
3ae5eaec 1747static int smsc_ircc_resume(struct platform_device *dev)
1da177e4 1748{
3ae5eaec 1749 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1da177e4 1750
9480e307 1751 if (self->io.suspended) {
e812cb52
DT		 1752 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1753
1754 rtnl_lock();
1755 smsc_ircc_init_chip(self);
1756 if (netif_running(self->netdev)) {
1757 if (smsc_ircc_request_irq(self)) {
1758 /*
1759 * Don't fail resume process, just kill this
1760 * network interface
1761 */
1762 unregister_netdevice(self->netdev);
1763 } else {
1764 enable_dma(self->io.dma);
1765 smsc_ircc_start_interrupts(self);
1766 netif_device_attach(self->netdev);
1767 }
1768 }
6bb3b2cd 1769 self->io.suspended = 0;
e812cb52 1770 rtnl_unlock();
6bb3b2cd 1771 }
1da177e4
LT		 1772 return 0;
1773}
1774
1775/*
1776 * Function smsc_ircc_close (self)
1777 *
1778 * Close driver instance
1779 *
1780 */
1781static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1782{
1da177e4
LT		 1783 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1784
1785 IRDA_ASSERT(self != NULL, return -1;);
1786
6bb3b2cd 1787 platform_device_unregister(self->pldev);
1da177e4
LT		 1788
1789 /* Remove netdevice */
1790 unregister_netdev(self->netdev);
1791
e812cb52 1792 smsc_ircc_stop_interrupts(self);
1da177e4
LT		 1793
1794 /* Release the PORTS that this driver is using */
1795 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1796 self->io.fir_base);
1797
1798 release_region(self->io.fir_base, self->io.fir_ext);
1799
527b6af4 1800 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1da177e4
LT		 1801 self->io.sir_base);
1802
1803 release_region(self->io.sir_base, self->io.sir_ext);
1804
1805 if (self->tx_buff.head)
1806 dma_free_coherent(NULL, self->tx_buff.truesize,
1807 self->tx_buff.head, self->tx_buff_dma);
527b6af4 1808
1da177e4
LT		 1809 if (self->rx_buff.head)
1810 dma_free_coherent(NULL, self->rx_buff.truesize,
1811 self->rx_buff.head, self->rx_buff_dma);
1812
1813 free_netdev(self->netdev);
1814
1815 return 0;
1816}
1817
1818static void __exit smsc_ircc_cleanup(void)
1819{
1820 int i;
1821
1822 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1823
98b77773 1824 for (i = 0; i < 2; i++) {
1da177e4
LT		 1825 if (dev_self[i])
1826 smsc_ircc_close(dev_self[i]);
1827 }
6bb3b2cd 1828
3ae5eaec 1829 platform_driver_unregister(&smsc_ircc_driver);
1da177e4
LT		 1830}
1831
1832/*
1833 * Start SIR operations
1834 *
1835 * This function *must* be called with spinlock held, because it may
1836 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1837 */
1838void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1839{
1840 struct net_device *dev;
1841 int fir_base, sir_base;
1842
1843 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1844
527b6af4 1845 IRDA_ASSERT(self != NULL, return;);
98b77773 1846 dev = self->netdev;
527b6af4 1847 IRDA_ASSERT(dev != NULL, return;);
1da177e4
LT		 1848 dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1849
1850 fir_base = self->io.fir_base;
1851 sir_base = self->io.sir_base;
1852
1853 /* Reset everything */
98b77773 1854 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1da177e4
LT		 1855
1856 #if SMSC_IRCC2_C_SIR_STOP
1857 /*smsc_ircc_sir_stop(self);*/
1858 #endif
1859
1860 register_bank(fir_base, 1);
98b77773 1861 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1da177e4
LT		 1862
1863 /* Initialize UART */
98b77773
DT		 1864 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1865 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
527b6af4 1866
1da177e4 1867 /* Turn on interrups */
98b77773 1868 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1da177e4
LT		 1869
1870 IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__);
1871
98b77773 1872 outb(0x00, fir_base + IRCC_MASTER);
1da177e4
LT		 1873}
1874
1875#if SMSC_IRCC2_C_SIR_STOP
1876void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1877{
1878 int iobase;
1879
1880 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1881 iobase = self->io.sir_base;
1882
1883 /* Reset UART */
98b77773 1884 outb(0, iobase + UART_MCR);
527b6af4 1885
1da177e4 1886 /* Turn off interrupts */
98b77773 1887 outb(0, iobase + UART_IER);
1da177e4
LT		 1888}
1889#endif
1890
1891/*
1892 * Function smsc_sir_write_wakeup (self)
1893 *
1894 * Called by the SIR interrupt handler when there's room for more data.
1895 * If we have more packets to send, we send them here.
1896 *
1897 */
1898static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1899{
1900 int actual = 0;
1901 int iobase;
1902 int fcr;
1903
1904 IRDA_ASSERT(self != NULL, return;);
1905
1906 IRDA_DEBUG(4, "%s\n", __FUNCTION__);
1907
1908 iobase = self->io.sir_base;
1909
1910 /* Finished with frame? */
1911 if (self->tx_buff.len > 0) {
1912 /* Write data left in transmit buffer */
527b6af4 1913 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1da177e4
LT		 1914 self->tx_buff.data, self->tx_buff.len);
1915 self->tx_buff.data += actual;
1916 self->tx_buff.len -= actual;
1917 } else {
527b6af4 1918
1da177e4 1919 /*if (self->tx_buff.len ==0) {*/
527b6af4
DT		 1920
1921 /*
1922 * Now serial buffer is almost free & we can start
1da177e4
LT		 1923 * transmission of another packet. But first we must check
1924 * if we need to change the speed of the hardware
1925 */
1926 if (self->new_speed) {
1927 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1928 __FUNCTION__, self->new_speed);
1929 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1930 smsc_ircc_change_speed(self, self->new_speed);
1931 self->new_speed = 0;
1932 } else {
1933 /* Tell network layer that we want more frames */
1934 netif_wake_queue(self->netdev);
1935 }
1936 self->stats.tx_packets++;
1937
98b77773
DT		 1938 if (self->io.speed <= 115200) {
1939 /*
1940 * Reset Rx FIFO to make sure that all reflected transmit data
1941 * is discarded. This is needed for half duplex operation
1942 */
1943 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
1944 fcr |= self->io.speed < 38400 ?
1945 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1da177e4 1946
98b77773 1947 outb(fcr, iobase + UART_FCR);
1da177e4 1948
98b77773
DT		 1949 /* Turn on receive interrupts */
1950 outb(UART_IER_RDI, iobase + UART_IER);
1da177e4
LT		 1951 }
1952 }
1953}
1954
1955/*
1956 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
1957 *
1958 * Fill Tx FIFO with transmit data
1959 *
1960 */
1961static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1962{
1963 int actual = 0;
527b6af4 1964
1da177e4 1965 /* Tx FIFO should be empty! */
98b77773 1966 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
1da177e4
LT		 1967 IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__);
1968 return 0;
1969 }
527b6af4 1970
1da177e4 1971 /* Fill FIFO with current frame */
98b77773 1972 while (fifo_size-- > 0 && actual < len) {
1da177e4 1973 /* Transmit next byte */
98b77773 1974 outb(buf[actual], iobase + UART_TX);
1da177e4
LT		 1975 actual++;
1976 }
1977 return actual;
1978}
1979
1980/*
1981 * Function smsc_ircc_is_receiving (self)
1982 *
1983 * Returns true is we are currently receiving data
1984 *
1985 */
1986static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
1987{
1988 return (self->rx_buff.state != OUTSIDE_FRAME);
1989}
1990
1991
1992/*
1993 * Function smsc_ircc_probe_transceiver(self)
1994 *
1995 * Tries to find the used Transceiver
1996 *
1997 */
1998static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
1999{
2000 unsigned int i;
527b6af4 2001
1da177e4 2002 IRDA_ASSERT(self != NULL, return;);
527b6af4 2003
98b77773
DT		 2004 for (i = 0; smsc_transceivers[i].name != NULL; i++)
2005 if (smsc_transceivers[i].probe(self->io.fir_base)) {
1da177e4
LT		 2006 IRDA_MESSAGE(" %s transceiver found\n",
2007 smsc_transceivers[i].name);
98b77773 2008 self->transceiver= i + 1;
1da177e4
LT		 2009 return;
2010 }
98b77773 2011
1da177e4
LT		 2012 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2013 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
527b6af4 2014
98b77773 2015 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
1da177e4
LT		 2016}
2017
2018
2019/*
2020 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2021 *
2022 * Set the transceiver according to the speed
2023 *
2024 */
2025static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2026{
2027 unsigned int trx;
527b6af4 2028
1da177e4 2029 trx = self->transceiver;
98b77773
DT		 2030 if (trx > 0)
2031 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
1da177e4
LT		 2032}
2033
2034/*
2035 * Function smsc_ircc_wait_hw_transmitter_finish ()
2036 *
2037 * Wait for the real end of HW transmission
2038 *
2039 * The UART is a strict FIFO, and we get called only when we have finished
2040 * pushing data to the FIFO, so the maximum amount of time we must wait
2041 * is only for the FIFO to drain out.
2042 *
2043 * We use a simple calibrated loop. We may need to adjust the loop
2044 * delay (udelay) to balance I/O traffic and latency. And we also need to
2045 * adjust the maximum timeout.
2046 * It would probably be better to wait for the proper interrupt,
2047 * but it doesn't seem to be available.
2048 *
2049 * We can't use jiffies or kernel timers because :
2050 * 1) We are called from the interrupt handler, which disable softirqs,
2051 * so jiffies won't be increased
2052 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2053 * want to wait that long to detect stuck hardware.
2054 * Jean II
2055 */
2056
2057static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2058{
98b77773 2059 int iobase = self->io.sir_base;
1da177e4 2060 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
527b6af4 2061
1da177e4 2062 /* Calibrated busy loop */
98b77773 2063 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
1da177e4
LT		 2064 udelay(1);
2065
98b77773 2066 if (count == 0)
1da177e4
LT		 2067 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__);
2068}
2069
2070
2071/* PROBING
2072 *
2073 *
2074 */
2075
2076static int __init smsc_ircc_look_for_chips(void)
2077{
b6158d23 2078 struct smsc_chip_address *address;
98b77773 2079 char *type;
1da177e4 2080 unsigned int cfg_base, found;
527b6af4 2081
1da177e4
LT		 2082 found = 0;
2083 address = possible_addresses;
527b6af4 2084
98b77773 2085 while (address->cfg_base) {
1da177e4 2086 cfg_base = address->cfg_base;
527b6af4 2087
1da177e4 2088 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/
527b6af4 2089
98b77773 2090 if (address->type & SMSCSIO_TYPE_FDC) {
1da177e4 2091 type = "FDC";
98b77773
DT		 2092 if (address->type & SMSCSIO_TYPE_FLAT)
2093 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2094 found++;
2095
2096 if (address->type & SMSCSIO_TYPE_PAGED)
2097 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2098 found++;
1da177e4 2099 }
98b77773 2100 if (address->type & SMSCSIO_TYPE_LPC) {
1da177e4 2101 type = "LPC";
98b77773
DT		 2102 if (address->type & SMSCSIO_TYPE_FLAT)
2103 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2104 found++;
2105
2106 if (address->type & SMSCSIO_TYPE_PAGED)
2107 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2108 found++;
1da177e4
LT		 2109 }
2110 address++;
2111 }
2112 return found;
527b6af4 2113}
1da177e4
LT		 2114
2115/*
2116 * Function smsc_superio_flat (chip, base, type)
2117 *
2118 * Try to get configuration of a smc SuperIO chip with flat register model
2119 *
2120 */
b6158d23 2121static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
1da177e4
LT		 2122{
2123 unsigned short firbase, sirbase;
2124 u8 mode, dma, irq;
2125 int ret = -ENODEV;
2126
2127 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2128
98b77773 2129 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
1da177e4
LT		 2130 return ret;
2131
2132 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
98b77773 2133 mode = inb(cfgbase + 1);
527b6af4 2134
1da177e4 2135 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/
527b6af4 2136
98b77773 2137 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
1da177e4
LT		 2138 IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__);
2139
2140 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
98b77773 2141 sirbase = inb(cfgbase + 1) << 2;
1da177e4 2142
527b6af4 2143 /* FIR iobase */
1da177e4 2144 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
98b77773 2145 firbase = inb(cfgbase + 1) << 3;
1da177e4
LT		 2146
2147 /* DMA */
2148 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
98b77773 2149 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
527b6af4 2150
1da177e4
LT		 2151 /* IRQ */
2152 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
98b77773 2153 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
1da177e4
LT		 2154
2155 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode);
2156
98b77773
DT		 2157 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2158 ret = 0;
527b6af4 2159
1da177e4
LT		 2160 /* Exit configuration */
2161 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2162
2163 return ret;
2164}
2165
2166/*
2167 * Function smsc_superio_paged (chip, base, type)
2168 *
2169 * Try to get configuration of a smc SuperIO chip with paged register model
2170 *
2171 */
b6158d23 2172static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
1da177e4
LT		 2173{
2174 unsigned short fir_io, sir_io;
2175 int ret = -ENODEV;
527b6af4 2176
1da177e4
LT		 2177 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2178
98b77773 2179 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
1da177e4 2180 return ret;
527b6af4 2181
1da177e4
LT		 2182 /* Select logical device (UART2) */
2183 outb(0x07, cfg_base);
2184 outb(0x05, cfg_base + 1);
527b6af4 2185
1da177e4
LT		 2186 /* SIR iobase */
2187 outb(0x60, cfg_base);
98b77773 2188 sir_io = inb(cfg_base + 1) << 8;
1da177e4
LT		 2189 outb(0x61, cfg_base);
2190 sir_io |= inb(cfg_base + 1);
527b6af4 2191
1da177e4
LT		 2192 /* Read FIR base */
2193 outb(0x62, cfg_base);
2194 fir_io = inb(cfg_base + 1) << 8;
2195 outb(0x63, cfg_base);
2196 fir_io |= inb(cfg_base + 1);
2197 outb(0x2b, cfg_base); /* ??? */
2198
98b77773
DT		 2199 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2200 ret = 0;
527b6af4 2201
1da177e4
LT		 2202 /* Exit configuration */
2203 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2204
2205 return ret;
2206}
2207
2208
98b77773 2209static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
1da177e4
LT		 2210{
2211 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2212
2213 outb(reg, cfg_base);
98b77773 2214 return inb(cfg_base) != reg ? -1 : 0;
1da177e4
LT		 2215}
2216
b6158d23 2217static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
1da177e4 2218{
98b77773 2219 u8 devid, xdevid, rev;
1da177e4
LT		 2220
2221 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2222
2223 /* Leave configuration */
2224
2225 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2226
2227 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2228 return NULL;
2229
2230 outb(reg, cfg_base);
2231
98b77773 2232 xdevid = inb(cfg_base + 1);
1da177e4
LT		 2233
2234 /* Enter configuration */
2235
2236 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2237
2238 #if 0
2239 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2240 return NULL;
2241 #endif
527b6af4 2242
1da177e4
LT		 2243 /* probe device ID */
2244
98b77773 2245 if (smsc_access(cfg_base, reg))
1da177e4
LT		 2246 return NULL;
2247
98b77773 2248 devid = inb(cfg_base + 1);
527b6af4 2249
98b77773 2250 if (devid == 0 || devid == 0xff) /* typical values for unused port */
1da177e4
LT		 2251 return NULL;
2252
2253 /* probe revision ID */
2254
98b77773 2255 if (smsc_access(cfg_base, reg + 1))
1da177e4
LT		 2256 return NULL;
2257
98b77773 2258 rev = inb(cfg_base + 1);
1da177e4 2259
98b77773 2260 if (rev >= 128) /* i think this will make no sense */
1da177e4
LT		 2261 return NULL;
2262
98b77773 2263 if (devid == xdevid) /* protection against false positives */
1da177e4
LT		 2264 return NULL;
2265
2266 /* Check for expected device ID; are there others? */
2267
98b77773 2268 while (chip->devid != devid) {
1da177e4
LT		 2269
2270 chip++;
2271
98b77773 2272 if (chip->name == NULL)
1da177e4
LT		 2273 return NULL;
2274 }
2275
98b77773
DT		 2276 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2277 devid, rev, cfg_base, type, chip->name);
1da177e4 2278
98b77773 2279 if (chip->rev > rev) {
527b6af4 2280 IRDA_MESSAGE("Revision higher than expected\n");
1da177e4
LT		 2281 return NULL;
2282 }
527b6af4 2283
98b77773 2284 if (chip->flags & NoIRDA)
1da177e4
LT		 2285 IRDA_MESSAGE("chipset does not support IRDA\n");
2286
2287 return chip;
2288}
2289
2290static int __init smsc_superio_fdc(unsigned short cfg_base)
2291{
2292 int ret = -1;
2293
2294 if (!request_region(cfg_base, 2, driver_name)) {
2295 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2296 __FUNCTION__, cfg_base);
2297 } else {
98b77773
DT		 2298 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2299 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
1da177e4
LT		 2300 ret = 0;
2301
2302 release_region(cfg_base, 2);
2303 }
2304
2305 return ret;
2306}
2307
2308static int __init smsc_superio_lpc(unsigned short cfg_base)
2309{
2310 int ret = -1;
2311
2312 if (!request_region(cfg_base, 2, driver_name)) {
2313 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2314 __FUNCTION__, cfg_base);
2315 } else {
98b77773
DT		 2316 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2317 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
1da177e4 2318 ret = 0;
98b77773 2319
1da177e4
LT		 2320 release_region(cfg_base, 2);
2321 }
2322 return ret;
2323}
2324
c1e14a6e
LW		 2325/*
2326 * Look for some specific subsystem setups that need
2327 * pre-configuration not properly done by the BIOS (especially laptops)
2328 * This code is based in part on smcinit.c, tosh1800-smcinit.c
2329 * and tosh2450-smcinit.c. The table lists the device entries
2330 * for ISA bridges with an LPC (Local Peripheral Configurator)
2331 * that are in turn used to configure the SMSC device with default
2332 * SIR and FIR I/O ports, DMA and IRQ.
2333 */
2334#ifdef CONFIG_PCI
2335#define PCIID_VENDOR_INTEL 0x8086
2336#define PCIID_VENDOR_ALI 0x10b9
2337static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __devinitdata = {
2338 {
2339 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2340 .device = 0x24cc,
2341 .subvendor = 0x103c,
2342 .subdevice = 0x088c,
2343 .sir_io = 0x02f8, /* Quite certain these are the same for nc8000 as for nc6000 */
2344 .fir_io = 0x0130,
2345 .fir_irq = 0x09,
2346 .fir_dma = 0x03,
2347 .cfg_base = 0x004e,
2348 .preconfigure = preconfigure_through_82801,
2349 .name = "HP nc8000",
2350 },
2351 {
2352 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2353 .device = 0x24cc,
2354 .subvendor = 0x103c,
2355 .subdevice = 0x0890,
2356 .sir_io = 0x02f8,
2357 .fir_io = 0x0130,
2358 .fir_irq = 0x09,
2359 .fir_dma = 0x03,
2360 .cfg_base = 0x004e,
2361 .preconfigure = preconfigure_through_82801,
2362 .name = "HP nc6000",
2363 },
2364 {
2365 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2366 .device = 0x24c0,
2367 .subvendor = 0x1179,
2368 .subdevice = 0xffff, /* 0xffff is "any", Not sure, 0x0001 or 0x0002 */
2369 .sir_io = 0x03f8,
2370 .fir_io = 0x0130,
2371 .fir_irq = 0x07,
2372 .fir_dma = 0x01,
2373 .cfg_base = 0x002e,
2374 .preconfigure = preconfigure_through_82801,
2375 .name = "Toshiba Satellite 2450",
2376 },
2377 {
2378 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */
2379 .device = 0x248c, /* Some use 24cc? */
2380 .subvendor = 0x1179,
2381 .subdevice = 0xffff, /* 0xffff is "any", Not sure, 0x0001 or 0x0002 */
2382 .sir_io = 0x03f8,
2383 .fir_io = 0x0130,
2384 .fir_irq = 0x03,
2385 .fir_dma = 0x03,
2386 .cfg_base = 0x002e,
2387 .preconfigure = preconfigure_through_82801,
2388 .name = "Toshiba Satellite 5100/5200, Tecra 9100",
2389 },
2390 {
2391 .vendor = PCIID_VENDOR_ALI, /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2392 .device = 0x1533,
2393 .subvendor = 0x1179,
2394 .subdevice = 0xffff, /* 0xffff is "any", Not sure, 0x0001 or 0x0002 */
2395 .sir_io = 0x02e8,
2396 .fir_io = 0x02f8,
2397 .fir_irq = 0x07,
2398 .fir_dma = 0x03,
2399 .cfg_base = 0x002e,
2400 .preconfigure = preconfigure_through_ali,
2401 .name = "Toshiba Satellite 1800",
2402 },
2403 { } // Terminator
2404};
2405
2406
2407/*
2408 * This sets up the basic SMSC parameters (FIR port, SIR port, FIR DMA, FIR IRQ)
2409 * through the chip configuration port.
2410 */
2411static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf)
2412{
2413 unsigned short iobase = conf->cfg_base;
2414 unsigned char tmpbyte;
2415
2416 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2417 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2418 tmpbyte = inb(iobase +1); // Read device ID
2419 IRDA_DEBUG(0, "Detected Chip id: 0x%02x, setting up registers...\n",tmpbyte);
2420
2421 /* Disable UART1 and set up SIR I/O port */
2422 outb(0x24, iobase); // select CR24 - UART1 base addr
2423 outb(0x00, iobase + 1); // disable UART1
2424 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr
2425 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2426 tmpbyte = inb(iobase + 1);
2427 if (tmpbyte != (conf->sir_io >> 2) ) {
2428 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
2429 return -ENXIO;
2430 }
2431
2432 /* Set up FIR IRQ channel for UART2 */
2433 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2434 tmpbyte = inb(iobase + 1);
2435 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2436 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2437 outb(tmpbyte, iobase + 1);
2438 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2439 if (tmpbyte != conf->fir_irq) {
2440 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2441 return -ENXIO;
2442 }
2443
2444 /* Set up FIR I/O port */
2445 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr
2446 outb((conf->fir_io >> 3), iobase + 1);
2447 tmpbyte = inb(iobase + 1);
2448 if (tmpbyte != (conf->fir_io >> 3) ) {
2449 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2450 return -ENXIO;
2451 }
2452
2453 /* Set up FIR DMA channel */
2454 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select
2455 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2456 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2457 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2458 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2459 return -ENXIO;
2460 }
2461
2462 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode
2463 tmpbyte = inb(iobase + 1);
2464 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK | SMSCSIOFLAT_UART2MODE_VAL_IRDA;
2465 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2466
2467 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel
2468 tmpbyte = inb(iobase + 1);
2469 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2470
2471 /* This one was not part of tosh1800 */
2472 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux
2473 tmpbyte = inb(iobase + 1);
2474 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2475
2476 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power
2477 tmpbyte = inb(iobase + 1);
2478 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2479
2480 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle
2481 tmpbyte = inb(iobase + 1);
2482 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2483
2484 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration
2485
2486 return 0;
2487}
2488
2489/* 82801CAM registers */
2490#define VID 0x00
2491#define DID 0x02
2492#define PIRQA_ROUT 0x60
2493#define PCI_DMA_C 0x90
2494#define COM_DEC 0xe0
2495#define LPC_EN 0xe6
2496#define GEN2_DEC 0xec
2497/*
2498 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge or
2499 * Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge. They all work the same way!
2500 */
2501static int __init preconfigure_through_82801(struct pci_dev *dev,
2502 struct smsc_ircc_subsystem_configuration *conf)
2503{
2504 unsigned short tmpword;
2505 int ret;
2506
2507 IRDA_MESSAGE("Setting up the SMSC device via the 82801 controller.\n");
2508 pci_write_config_byte(dev, COM_DEC, 0x10);
2509
2510 /* Enable LPC */
2511 pci_read_config_word(dev, LPC_EN, &tmpword); /* LPC_EN register */
2512 tmpword &= 0xfffd; /* mask bit 1 */
2513 tmpword |= 0x0001; /* set bit 0 : COMA addr range enable */
2514 pci_write_config_word(dev, LPC_EN, tmpword);
2515
2516 /* Setup DMA */
2517 pci_write_config_word(dev, PCI_DMA_C, 0xc0c0); /* LPC I/F DMA on, channel 3 -- rtm (?? PCI DMA ?) */
2518 pci_write_config_word(dev, GEN2_DEC, 0x131); /* LPC I/F 2nd decode range */
2519
2520 /* Pre-configure chip */
2521 ret = preconfigure_smsc_chip(conf);
2522
2523 /* Disable LPC */
2524 pci_read_config_word(dev, LPC_EN, &tmpword); /* LPC_EN register */
2525 tmpword &= 0xfffc; /* mask bit 1 and bit 0, COMA addr range disable */
2526 pci_write_config_word(dev, LPC_EN, tmpword);
2527 return ret;
2528}
2529
2530static int __init preconfigure_through_ali(struct pci_dev *dev,
2531 struct smsc_ircc_subsystem_configuration *conf)
2532{
2533 /* TODO: put in ALi 1533 configuration here. */
2534 IRDA_MESSAGE("SORRY: %s has an unsupported bridge controller (ALi): not pre-configured.\n", conf->name);
2535 return -ENODEV;
2536}
2537
2538static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
2539 unsigned short ircc_fir,
2540 unsigned short ircc_sir,
2541 unsigned char ircc_dma,
2542 unsigned char ircc_irq)
2543{
2544 struct pci_dev *dev = NULL;
2545 unsigned short ss_vendor = 0x0000;
2546 unsigned short ss_device = 0x0000;
2547 int ret = 0;
2548
2549 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2550
2551 while (dev != NULL) {
2552 struct smsc_ircc_subsystem_configuration *conf;
2553
2554 /*
2555 * Cache the subsystem vendor/device: some manufacturers fail to set
2556 * this for all components, so we save it in case there is just
2557 * 0x0000 0x0000 on the device we want to check.
2558 */
2559 if (dev->subsystem_vendor != 0x0000U) {
2560 ss_vendor = dev->subsystem_vendor;
2561 ss_device = dev->subsystem_device;
2562 }
2563 conf = subsystem_configurations;
2564 for( ; conf->subvendor; conf++) {
2565 if(conf->vendor == dev->vendor &&
2566 conf->device == dev->device &&
2567 conf->subvendor == ss_vendor && /* Sometimes these are cached values */
2568 (conf->subdevice == ss_device || conf->subdevice == 0xffff)) {
2569 struct smsc_ircc_subsystem_configuration tmpconf;
2570
2571 memcpy(&tmpconf, conf, sizeof(struct smsc_ircc_subsystem_configuration));
2572
2573 /* Override the default values with anything passed in as parameter */
2574 if (ircc_cfg != 0)
2575 tmpconf.cfg_base = ircc_cfg;
2576 if (ircc_fir != 0)
2577 tmpconf.fir_io = ircc_fir;
2578 if (ircc_sir != 0)
2579 tmpconf.sir_io = ircc_sir;
2580 if (ircc_dma != 0xff)
2581 tmpconf.fir_dma = ircc_dma;
2582 if (ircc_irq != 0xff)
2583 tmpconf.fir_irq = ircc_irq;
2584
2585 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2586 if (conf->preconfigure)
2587 ret = conf->preconfigure(dev, &tmpconf);
2588 else
2589 ret = -ENODEV;
2590 }
2591 }
2592 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2593 }
2594
2595 return ret;
2596}
2597#endif // CONFIG_PCI
2598
1da177e4
LT		 2599/************************************************
2600 *
2601 * Transceivers specific functions
2602 *
2603 ************************************************/
2604
2605
2606/*
2607 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2608 *
2609 * Program transceiver through smsc-ircc ATC circuitry
2610 *
2611 */
2612
2613static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2614{
2615 unsigned long jiffies_now, jiffies_timeout;
98b77773 2616 u8 val;
527b6af4 2617
98b77773
DT		 2618 jiffies_now = jiffies;
2619 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
527b6af4 2620
1da177e4
LT		 2621 /* ATC */
2622 register_bank(fir_base, 4);
98b77773
DT		 2623 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2624 fir_base + IRCC_ATC);
2625
2626 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2627 !time_after(jiffies, jiffies_timeout))
2628 /* empty */;
2629
2630 if (val)
1da177e4 2631 IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__,
98b77773 2632 inb(fir_base + IRCC_ATC));
1da177e4
LT		 2633}
2634
2635/*
2636 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2637 *
2638 * Probe transceiver smsc-ircc ATC circuitry
2639 *
2640 */
2641
2642static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2643{
2644 return 0;
2645}
2646
2647/*
2648 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2649 *
527b6af4 2650 * Set transceiver
1da177e4
LT		 2651 *
2652 */
2653
2654static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2655{
98b77773 2656 u8 fast_mode;
527b6af4 2657
98b77773
DT		 2658 switch (speed) {
2659 default:
2660 case 576000 :
527b6af4 2661 fast_mode = 0;
1da177e4 2662 break;
98b77773
DT		 2663 case 1152000 :
2664 case 4000000 :
1da177e4
LT		 2665 fast_mode = IRCC_LCR_A_FAST;
2666 break;
1da177e4
LT		 2667 }
2668 register_bank(fir_base, 0);
98b77773 2669 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 2670}
2671
2672/*
2673 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2674 *
527b6af4 2675 * Probe transceiver
1da177e4
LT		 2676 *
2677 */
2678
2679static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2680{
2681 return 0;
2682}
2683
2684/*
2685 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2686 *
527b6af4 2687 * Set transceiver
1da177e4
LT		 2688 *
2689 */
2690
2691static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2692{
98b77773 2693 u8 fast_mode;
527b6af4 2694
98b77773
DT		 2695 switch (speed) {
2696 default:
2697 case 576000 :
527b6af4 2698 fast_mode = 0;
1da177e4 2699 break;
98b77773
DT		 2700 case 1152000 :
2701 case 4000000 :
1da177e4
LT		 2702 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
2703 break;
527b6af4 2704
1da177e4
LT		 2705 }
2706 /* This causes an interrupt */
2707 register_bank(fir_base, 0);
98b77773 2708 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 2709}
2710
2711/*
2712 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
2713 *
527b6af4 2714 * Probe transceiver
1da177e4
LT		 2715 *
2716 */
2717
2718static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
2719{
2720 return 0;
2721}
2722
2723
2724module_init(smsc_ircc_init);
2725module_exit(smsc_ircc_cleanup);
Linux kernel - Deliverables
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