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[PATCH] smsc-ircc2: formatting fixes
[deliverable/linux.git] / drivers / net / irda / smsc-ircc2.c
CommitLineData
1da177e4
LT		 1/*********************************************************************
2 * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
3 *
4 * Description: Driver for the SMC Infrared Communications Controller
5 * Status: Experimental.
6 * Author: Daniele Peri (peri@csai.unipa.it)
527b6af4
DT		 7 * Created at:
8 * Modified at:
9 * Modified by:
10 *
1da177e4
LT		 11 * Copyright (c) 2002 Daniele Peri
12 * All Rights Reserved.
13 * Copyright (c) 2002 Jean Tourrilhes
14 *
15 *
16 * Based on smc-ircc.c:
17 *
18 * Copyright (c) 2001 Stefani Seibold
19 * Copyright (c) 1999-2001 Dag Brattli
527b6af4 20 * Copyright (c) 1998-1999 Thomas Davis,
1da177e4
LT		 21 *
22 * and irport.c:
23 *
24 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
25 *
527b6af4
DT		 26 *
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License as
29 * published by the Free Software Foundation; either version 2 of
1da177e4 30 * the License, or (at your option) any later version.
527b6af4 31 *
1da177e4
LT		 32 * This program is distributed in the hope that it will be useful,
33 * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 * GNU General Public License for more details.
527b6af4
DT		 36 *
37 * You should have received a copy of the GNU General Public License
38 * along with this program; if not, write to the Free Software
39 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1da177e4
LT		 40 * MA 02111-1307 USA
41 *
42 ********************************************************************/
43
44#include <linux/module.h>
45#include <linux/kernel.h>
46#include <linux/types.h>
47#include <linux/skbuff.h>
48#include <linux/netdevice.h>
49#include <linux/ioport.h>
50#include <linux/delay.h>
51#include <linux/slab.h>
52#include <linux/init.h>
53#include <linux/rtnetlink.h>
54#include <linux/serial_reg.h>
55#include <linux/dma-mapping.h>
56
57#include <asm/io.h>
58#include <asm/dma.h>
59#include <asm/byteorder.h>
60
61#include <linux/spinlock.h>
62#include <linux/pm.h>
63
64#include <net/irda/wrapper.h>
65#include <net/irda/irda.h>
66#include <net/irda/irda_device.h>
67
68#include "smsc-ircc2.h"
69#include "smsc-sio.h"
70
98b77773
DT		 71
72MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
73MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
74MODULE_LICENSE("GPL");
75
76
77static int ircc_dma = 255;
78module_param(ircc_dma, int, 0);
79MODULE_PARM_DESC(ircc_dma, "DMA channel");
80
81static int ircc_irq = 255;
82module_param(ircc_irq, int, 0);
83MODULE_PARM_DESC(ircc_irq, "IRQ line");
84
85static int ircc_fir;
86module_param(ircc_fir, int, 0);
87MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
88
89static int ircc_sir;
90module_param(ircc_sir, int, 0);
91MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
92
93static int ircc_cfg;
94module_param(ircc_cfg, int, 0);
95MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
96
97static int ircc_transceiver;
98module_param(ircc_transceiver, int, 0);
99MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
100
1da177e4
LT		 101/* Types */
102
103struct smsc_transceiver {
104 char *name;
527b6af4 105 void (*set_for_speed)(int fir_base, u32 speed);
1da177e4
LT		 106 int (*probe)(int fir_base);
107};
108typedef struct smsc_transceiver smsc_transceiver_t;
109
110#if 0
111struct smc_chip {
112 char *name;
113 u16 flags;
114 u8 devid;
115 u8 rev;
116};
117typedef struct smc_chip smc_chip_t;
118#endif
119
120struct smsc_chip {
121 char *name;
122 #if 0
123 u8 type;
124 #endif
125 u16 flags;
126 u8 devid;
127 u8 rev;
128};
129typedef struct smsc_chip smsc_chip_t;
130
131struct smsc_chip_address {
132 unsigned int cfg_base;
133 unsigned int type;
134};
135typedef struct smsc_chip_address smsc_chip_address_t;
136
137/* Private data for each instance */
138struct smsc_ircc_cb {
139 struct net_device *netdev; /* Yes! we are some kind of netdevice */
140 struct net_device_stats stats;
141 struct irlap_cb *irlap; /* The link layer we are binded to */
527b6af4 142
1da177e4
LT		 143 chipio_t io; /* IrDA controller information */
144 iobuff_t tx_buff; /* Transmit buffer */
145 iobuff_t rx_buff; /* Receive buffer */
146 dma_addr_t tx_buff_dma;
147 dma_addr_t rx_buff_dma;
148
149 struct qos_info qos; /* QoS capabilities for this device */
150
151 spinlock_t lock; /* For serializing operations */
527b6af4 152
1da177e4
LT		 153 __u32 new_speed;
154 __u32 flags; /* Interface flags */
155
156 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
157 int tx_len; /* Number of frames in tx_buff */
158
159 int transceiver;
160 struct pm_dev *pmdev;
161};
162
163/* Constants */
164
165static const char *driver_name = "smsc-ircc2";
166#define DIM(x) (sizeof(x)/(sizeof(*(x))))
167#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
168#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
98b77773 169#define SMSC_IRCC2_C_NET_TIMEOUT 0
1da177e4
LT		 170#define SMSC_IRCC2_C_SIR_STOP 0
171
172/* Prototypes */
173
174static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
175static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
176static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
177static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
178static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
179static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
527b6af4 180static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self, int iobase);
1da177e4
LT		 181static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self, int iobase);
182static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
183static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
184static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
185static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int iobase, int bofs);
186static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self, int iobase);
187static void smsc_ircc_change_speed(void *priv, u32 speed);
188static void smsc_ircc_set_sir_speed(void *priv, u32 speed);
189static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs);
190static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
191static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
192#if SMSC_IRCC2_C_SIR_STOP
193static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
194#endif
195static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
196static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
197static int smsc_ircc_net_open(struct net_device *dev);
198static int smsc_ircc_net_close(struct net_device *dev);
199static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
200#if SMSC_IRCC2_C_NET_TIMEOUT
201static void smsc_ircc_timeout(struct net_device *dev);
202#endif
203static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
204static int smsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data);
205static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
206static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
207static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
208static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
209
210/* Probing */
211static int __init smsc_ircc_look_for_chips(void);
98b77773 212static const smsc_chip_t * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const smsc_chip_t *chip, char *type);
1da177e4
LT		 213static int __init smsc_superio_flat(const smsc_chip_t *chips, unsigned short cfg_base, char *type);
214static int __init smsc_superio_paged(const smsc_chip_t *chips, unsigned short cfg_base, char *type);
215static int __init smsc_superio_fdc(unsigned short cfg_base);
216static int __init smsc_superio_lpc(unsigned short cfg_base);
217
218/* Transceivers specific functions */
219
220static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
221static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
222static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
223static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
224static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
225static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
226
227/* Power Management */
228
229static void smsc_ircc_suspend(struct smsc_ircc_cb *self);
230static void smsc_ircc_wakeup(struct smsc_ircc_cb *self);
231static int smsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data);
232
233
234/* Transceivers for SMSC-ircc */
235
98b77773 236static smsc_transceiver_t smsc_transceivers[] =
1da177e4 237{
98b77773
DT		 238 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
239 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
240 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
241 { NULL, NULL }
1da177e4
LT		 242};
243#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (DIM(smsc_transceivers)-1)
244
245/* SMC SuperIO chipsets definitions */
246
247#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
248#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
249#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
250#define SIR 0 /* SuperIO Chip has only slow IRDA */
251#define FIR 4 /* SuperIO Chip has fast IRDA */
252#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
253
98b77773 254static smsc_chip_t __initdata fdc_chips_flat[] =
1da177e4
LT		 255{
256 /* Base address 0x3f0 or 0x370 */
257 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
258 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
259 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
260 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
261 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
262 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
263 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
264 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
265 { NULL }
266};
267
98b77773 268static smsc_chip_t __initdata fdc_chips_paged[] =
1da177e4
LT		 269{
270 /* Base address 0x3f0 or 0x370 */
271 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
272 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
273 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
274 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
275 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
276 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
277 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
278 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
279 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
280 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
281 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
282 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
283 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
284 { NULL }
285};
286
98b77773 287static smsc_chip_t __initdata lpc_chips_flat[] =
1da177e4
LT		 288{
289 /* Base address 0x2E or 0x4E */
290 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
291 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
292 { NULL }
293};
294
98b77773 295static smsc_chip_t __initdata lpc_chips_paged[] =
1da177e4
LT		 296{
297 /* Base address 0x2E or 0x4E */
298 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
299 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
300 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
301 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
302 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
303 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
304 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
305 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
306 { NULL }
307};
308
309#define SMSCSIO_TYPE_FDC 1
310#define SMSCSIO_TYPE_LPC 2
311#define SMSCSIO_TYPE_FLAT 4
312#define SMSCSIO_TYPE_PAGED 8
313
98b77773 314static smsc_chip_address_t __initdata possible_addresses[] =
1da177e4 315{
98b77773
DT		 316 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
317 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
318 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
319 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
320 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
321 { 0, 0 }
1da177e4
LT		 322};
323
324/* Globals */
325
98b77773
DT		 326static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
327static unsigned short dev_count;
1da177e4
LT		 328
329static inline void register_bank(int iobase, int bank)
330{
98b77773
DT		 331 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
332 iobase + IRCC_MASTER);
1da177e4
LT		 333}
334
335
336/*******************************************************************************
337 *
338 *
339 * SMSC-ircc stuff
340 *
341 *
342 *******************************************************************************/
343
344/*
345 * Function smsc_ircc_init ()
346 *
347 * Initialize chip. Just try to find out how many chips we are dealing with
348 * and where they are
349 */
350static int __init smsc_ircc_init(void)
351{
98b77773 352 int ret = -ENODEV;
1da177e4
LT		 353
354 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
355
98b77773 356 dev_count = 0;
527b6af4 357
98b77773 358 if (ircc_fir > 0 && ircc_sir > 0) {
1da177e4
LT		 359 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
360 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
361
362 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq) == 0)
363 return 0;
364
365 return -ENODEV;
366 }
367
368 /* try user provided configuration register base address */
98b77773 369 if (ircc_cfg > 0) {
1da177e4
LT		 370 IRDA_MESSAGE(" Overriding configuration address 0x%04x\n",
371 ircc_cfg);
372 if (!smsc_superio_fdc(ircc_cfg))
373 ret = 0;
374 if (!smsc_superio_lpc(ircc_cfg))
375 ret = 0;
376 }
527b6af4 377
98b77773
DT		 378 if (smsc_ircc_look_for_chips() > 0)
379 ret = 0;
527b6af4 380
1da177e4
LT		 381 return ret;
382}
383
384/*
385 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
386 *
387 * Try to open driver instance
388 *
389 */
390static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
391{
392 struct smsc_ircc_cb *self;
393 struct net_device *dev;
394 int err;
527b6af4 395
1da177e4
LT		 396 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
397
398 err = smsc_ircc_present(fir_base, sir_base);
98b77773 399 if (err)
1da177e4 400 goto err_out;
527b6af4 401
1da177e4
LT		 402 err = -ENOMEM;
403 if (dev_count > DIM(dev_self)) {
404 IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__);
405 goto err_out1;
406 }
407
408 /*
409 * Allocate new instance of the driver
410 */
411 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
412 if (!dev) {
413 IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__);
414 goto err_out1;
415 }
416
417 SET_MODULE_OWNER(dev);
418
419 dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
420#if SMSC_IRCC2_C_NET_TIMEOUT
421 dev->tx_timeout = smsc_ircc_timeout;
98b77773 422 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
1da177e4
LT		 423#endif
424 dev->open = smsc_ircc_net_open;
425 dev->stop = smsc_ircc_net_close;
426 dev->do_ioctl = smsc_ircc_net_ioctl;
427 dev->get_stats = smsc_ircc_net_get_stats;
527b6af4 428
1da177e4
LT		 429 self = dev->priv;
430 self->netdev = dev;
431
432 /* Make ifconfig display some details */
433 dev->base_addr = self->io.fir_base = fir_base;
434 dev->irq = self->io.irq = irq;
435
436 /* Need to store self somewhere */
437 dev_self[dev_count++] = self;
438 spin_lock_init(&self->lock);
439
527b6af4 440 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
1da177e4
LT		 441 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
442
443 self->rx_buff.head =
444 dma_alloc_coherent(NULL, self->rx_buff.truesize,
445 &self->rx_buff_dma, GFP_KERNEL);
446 if (self->rx_buff.head == NULL) {
447 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
448 driver_name);
449 goto err_out2;
450 }
451
452 self->tx_buff.head =
453 dma_alloc_coherent(NULL, self->tx_buff.truesize,
454 &self->tx_buff_dma, GFP_KERNEL);
455 if (self->tx_buff.head == NULL) {
456 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
457 driver_name);
458 goto err_out3;
459 }
460
461 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
462 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
463
464 self->rx_buff.in_frame = FALSE;
465 self->rx_buff.state = OUTSIDE_FRAME;
466 self->tx_buff.data = self->tx_buff.head;
467 self->rx_buff.data = self->rx_buff.head;
527b6af4 468
1da177e4 469 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
1da177e4 470 smsc_ircc_setup_qos(self);
1da177e4 471 smsc_ircc_init_chip(self);
527b6af4 472
98b77773
DT		 473 if (ircc_transceiver > 0 &&
474 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
1da177e4
LT		 475 self->transceiver = ircc_transceiver;
476 else
477 smsc_ircc_probe_transceiver(self);
478
479 err = register_netdev(self->netdev);
98b77773 480 if (err) {
1da177e4
LT		 481 IRDA_ERROR("%s, Network device registration failed!\n",
482 driver_name);
483 goto err_out4;
484 }
485
486 self->pmdev = pm_register(PM_SYS_DEV, PM_SYS_IRDA, smsc_ircc_pmproc);
487 if (self->pmdev)
488 self->pmdev->data = self;
489
490 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
491
492 return 0;
98b77773 493
1da177e4
LT		 494 err_out4:
495 dma_free_coherent(NULL, self->tx_buff.truesize,
496 self->tx_buff.head, self->tx_buff_dma);
497 err_out3:
498 dma_free_coherent(NULL, self->rx_buff.truesize,
499 self->rx_buff.head, self->rx_buff_dma);
500 err_out2:
501 free_netdev(self->netdev);
502 dev_self[--dev_count] = NULL;
503 err_out1:
504 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
505 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
506 err_out:
507 return err;
508}
509
510/*
511 * Function smsc_ircc_present(fir_base, sir_base)
512 *
513 * Check the smsc-ircc chip presence
514 *
515 */
516static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
517{
518 unsigned char low, high, chip, config, dma, irq, version;
519
520 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
521 driver_name)) {
522 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
523 __FUNCTION__, fir_base);
524 goto out1;
525 }
526
527 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
528 driver_name)) {
529 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
530 __FUNCTION__, sir_base);
531 goto out2;
532 }
533
534 register_bank(fir_base, 3);
535
98b77773
DT		 536 high = inb(fir_base + IRCC_ID_HIGH);
537 low = inb(fir_base + IRCC_ID_LOW);
538 chip = inb(fir_base + IRCC_CHIP_ID);
539 version = inb(fir_base + IRCC_VERSION);
540 config = inb(fir_base + IRCC_INTERFACE);
1da177e4
LT		 541 dma = config & IRCC_INTERFACE_DMA_MASK;
542 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
543
527b6af4 544 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
98b77773 545 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
1da177e4
LT		 546 __FUNCTION__, fir_base);
547 goto out3;
548 }
549 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
550 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
551 chip & 0x0f, version, fir_base, sir_base, dma, irq);
552
553 return 0;
98b77773 554
1da177e4
LT		 555 out3:
556 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
557 out2:
558 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
559 out1:
560 return -ENODEV;
561}
562
563/*
564 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
565 *
566 * Setup I/O
567 *
568 */
527b6af4
DT		 569static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
570 unsigned int fir_base, unsigned int sir_base,
1da177e4
LT		 571 u8 dma, u8 irq)
572{
573 unsigned char config, chip_dma, chip_irq;
574
575 register_bank(fir_base, 3);
98b77773
DT		 576 config = inb(fir_base + IRCC_INTERFACE);
577 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
578 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
1da177e4
LT		 579
580 self->io.fir_base = fir_base;
581 self->io.sir_base = sir_base;
582 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
583 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
584 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
585 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
586
587 if (irq < 255) {
588 if (irq != chip_irq)
589 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
590 driver_name, chip_irq, irq);
591 self->io.irq = irq;
98b77773 592 } else
1da177e4 593 self->io.irq = chip_irq;
527b6af4 594
1da177e4
LT		 595 if (dma < 255) {
596 if (dma != chip_dma)
597 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
598 driver_name, chip_dma, dma);
599 self->io.dma = dma;
98b77773 600 } else
1da177e4
LT		 601 self->io.dma = chip_dma;
602
603}
604
605/*
606 * Function smsc_ircc_setup_qos(self)
607 *
608 * Setup qos
609 *
610 */
611static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
612{
613 /* Initialize QoS for this device */
614 irda_init_max_qos_capabilies(&self->qos);
527b6af4 615
1da177e4
LT		 616 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
617 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
618
619 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
620 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
621 irda_qos_bits_to_value(&self->qos);
622}
623
624/*
625 * Function smsc_ircc_init_chip(self)
626 *
627 * Init chip
628 *
629 */
630static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
631{
527b6af4
DT		 632 int iobase, ir_mode, ctrl, fast;
633
98b77773 634 IRDA_ASSERT(self != NULL, return;);
1da177e4 635
98b77773 636 iobase = self->io.fir_base;
1da177e4
LT		 637 ir_mode = IRCC_CFGA_IRDA_SIR_A;
638 ctrl = 0;
639 fast = 0;
640
641 register_bank(iobase, 0);
98b77773
DT		 642 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
643 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 644
645 register_bank(iobase, 1);
98b77773
DT		 646 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | ir_mode),
647 iobase + IRCC_SCE_CFGA);
1da177e4
LT		 648
649#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 650 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
651 iobase + IRCC_SCE_CFGB);
527b6af4 652#else
98b77773
DT		 653 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
654 iobase + IRCC_SCE_CFGB);
527b6af4 655#endif
98b77773
DT		 656 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
657 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
527b6af4 658
1da177e4 659 register_bank(iobase, 4);
98b77773 660 outb((inb(iobase + IRCC_CONTROL) & 0x30) | ctrl, iobase + IRCC_CONTROL);
527b6af4 661
1da177e4 662 register_bank(iobase, 0);
98b77773 663 outb(fast, iobase + IRCC_LCR_A);
1da177e4
LT		 664
665 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
527b6af4 666
1da177e4 667 /* Power on device */
98b77773 668 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 669}
670
671/*
672 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
673 *
674 * Process IOCTL commands for this device
675 *
676 */
677static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
678{
679 struct if_irda_req *irq = (struct if_irda_req *) rq;
680 struct smsc_ircc_cb *self;
681 unsigned long flags;
682 int ret = 0;
683
684 IRDA_ASSERT(dev != NULL, return -1;);
685
686 self = dev->priv;
687
688 IRDA_ASSERT(self != NULL, return -1;);
689
690 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
527b6af4 691
1da177e4
LT		 692 switch (cmd) {
693 case SIOCSBANDWIDTH: /* Set bandwidth */
694 if (!capable(CAP_NET_ADMIN))
695 ret = -EPERM;
696 else {
697 /* Make sure we are the only one touching
698 * self->io.speed and the hardware - Jean II */
699 spin_lock_irqsave(&self->lock, flags);
700 smsc_ircc_change_speed(self, irq->ifr_baudrate);
701 spin_unlock_irqrestore(&self->lock, flags);
702 }
703 break;
704 case SIOCSMEDIABUSY: /* Set media busy */
705 if (!capable(CAP_NET_ADMIN)) {
706 ret = -EPERM;
707 break;
708 }
709
710 irda_device_set_media_busy(self->netdev, TRUE);
711 break;
712 case SIOCGRECEIVING: /* Check if we are receiving right now */
713 irq->ifr_receiving = smsc_ircc_is_receiving(self);
714 break;
715 #if 0
716 case SIOCSDTRRTS:
717 if (!capable(CAP_NET_ADMIN)) {
718 ret = -EPERM;
719 break;
720 }
721 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
722 break;
723 #endif
724 default:
725 ret = -EOPNOTSUPP;
726 }
527b6af4 727
1da177e4
LT		 728 return ret;
729}
730
731static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
732{
733 struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) dev->priv;
527b6af4 734
1da177e4
LT		 735 return &self->stats;
736}
737
738#if SMSC_IRCC2_C_NET_TIMEOUT
739/*
740 * Function smsc_ircc_timeout (struct net_device *dev)
741 *
742 * The networking timeout management.
743 *
744 */
745
746static void smsc_ircc_timeout(struct net_device *dev)
747{
748 struct smsc_ircc_cb *self;
749 unsigned long flags;
750
751 self = (struct smsc_ircc_cb *) dev->priv;
527b6af4 752
1da177e4
LT		 753 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
754 dev->name, self->io.speed);
755 spin_lock_irqsave(&self->lock, flags);
756 smsc_ircc_sir_start(self);
757 smsc_ircc_change_speed(self, self->io.speed);
758 dev->trans_start = jiffies;
759 netif_wake_queue(dev);
760 spin_unlock_irqrestore(&self->lock, flags);
761}
762#endif
763
764/*
765 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
766 *
767 * Transmits the current frame until FIFO is full, then
768 * waits until the next transmit interrupt, and continues until the
769 * frame is transmitted.
770 */
771int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
772{
773 struct smsc_ircc_cb *self;
774 unsigned long flags;
775 int iobase;
776 s32 speed;
777
778 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
779
780 IRDA_ASSERT(dev != NULL, return 0;);
527b6af4 781
1da177e4
LT		 782 self = (struct smsc_ircc_cb *) dev->priv;
783 IRDA_ASSERT(self != NULL, return 0;);
784
785 iobase = self->io.sir_base;
786
787 netif_stop_queue(dev);
527b6af4 788
1da177e4
LT		 789 /* Make sure test of self->io.speed & speed change are atomic */
790 spin_lock_irqsave(&self->lock, flags);
791
792 /* Check if we need to change the speed */
793 speed = irda_get_next_speed(skb);
98b77773 794 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 795 /* Check for empty frame */
796 if (!skb->len) {
797 /*
798 * We send frames one by one in SIR mode (no
799 * pipelining), so at this point, if we were sending
800 * a previous frame, we just received the interrupt
801 * telling us it is finished (UART_IIR_THRI).
802 * Therefore, waiting for the transmitter to really
803 * finish draining the fifo won't take too long.
804 * And the interrupt handler is not expected to run.
805 * - Jean II */
806 smsc_ircc_sir_wait_hw_transmitter_finish(self);
807 smsc_ircc_change_speed(self, speed);
808 spin_unlock_irqrestore(&self->lock, flags);
809 dev_kfree_skb(skb);
810 return 0;
1da177e4 811 }
98b77773 812 self->new_speed = speed;
1da177e4
LT		 813 }
814
815 /* Init tx buffer */
816 self->tx_buff.data = self->tx_buff.head;
817
818 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
527b6af4 819 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
1da177e4 820 self->tx_buff.truesize);
527b6af4 821
1da177e4
LT		 822 self->stats.tx_bytes += self->tx_buff.len;
823
824 /* Turn on transmit finished interrupt. Will fire immediately! */
98b77773 825 outb(UART_IER_THRI, iobase + UART_IER);
1da177e4
LT		 826
827 spin_unlock_irqrestore(&self->lock, flags);
828
829 dev_kfree_skb(skb);
527b6af4 830
1da177e4
LT		 831 return 0;
832}
833
834/*
835 * Function smsc_ircc_set_fir_speed (self, baud)
836 *
837 * Change the speed of the device
838 *
839 */
840static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
841{
842 int fir_base, ir_mode, ctrl, fast;
843
844 IRDA_ASSERT(self != NULL, return;);
845 fir_base = self->io.fir_base;
846
847 self->io.speed = speed;
848
98b77773 849 switch (speed) {
1da177e4 850 default:
527b6af4 851 case 576000:
1da177e4
LT		 852 ir_mode = IRCC_CFGA_IRDA_HDLC;
853 ctrl = IRCC_CRC;
854 fast = 0;
855 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
856 break;
857 case 1152000:
858 ir_mode = IRCC_CFGA_IRDA_HDLC;
859 ctrl = IRCC_1152 | IRCC_CRC;
860 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
861 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
862 __FUNCTION__);
863 break;
864 case 4000000:
865 ir_mode = IRCC_CFGA_IRDA_4PPM;
866 ctrl = IRCC_CRC;
867 fast = IRCC_LCR_A_FAST;
868 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
869 __FUNCTION__);
870 break;
871 }
872 #if 0
873 Now in tranceiver!
874 /* This causes an interrupt */
875 register_bank(fir_base, 0);
98b77773 876 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
1da177e4 877 #endif
527b6af4 878
1da177e4 879 register_bank(fir_base, 1);
98b77773 880 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
527b6af4 881
1da177e4 882 register_bank(fir_base, 4);
98b77773 883 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
1da177e4
LT		 884}
885
886/*
887 * Function smsc_ircc_fir_start(self)
888 *
889 * Change the speed of the device
890 *
891 */
892static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
893{
894 struct net_device *dev;
895 int fir_base;
896
897 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
898
899 IRDA_ASSERT(self != NULL, return;);
900 dev = self->netdev;
901 IRDA_ASSERT(dev != NULL, return;);
902
903 fir_base = self->io.fir_base;
904
905 /* Reset everything */
906
907 /* Install FIR transmit handler */
527b6af4 908 dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
1da177e4
LT		 909
910 /* Clear FIFO */
98b77773 911 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1da177e4
LT		 912
913 /* Enable interrupt */
98b77773 914 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1da177e4
LT		 915
916 register_bank(fir_base, 1);
917
527b6af4 918 /* Select the TX/RX interface */
1da177e4 919#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 920 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
921 fir_base + IRCC_SCE_CFGB);
527b6af4 922#else
98b77773
DT		 923 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
924 fir_base + IRCC_SCE_CFGB);
527b6af4 925#endif
98b77773 926 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1da177e4
LT		 927
928 /* Enable SCE interrupts */
98b77773 929 outb(0, fir_base + IRCC_MASTER);
1da177e4 930 register_bank(fir_base, 0);
98b77773
DT		 931 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
932 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1da177e4
LT		 933}
934
935/*
936 * Function smsc_ircc_fir_stop(self, baud)
937 *
938 * Change the speed of the device
939 *
940 */
941static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
942{
943 int fir_base;
944
945 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 946
1da177e4
LT		 947 IRDA_ASSERT(self != NULL, return;);
948
949 fir_base = self->io.fir_base;
950 register_bank(fir_base, 0);
98b77773
DT		 951 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
952 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1da177e4
LT		 953}
954
955
956/*
957 * Function smsc_ircc_change_speed(self, baud)
958 *
959 * Change the speed of the device
960 *
961 * This function *must* be called with spinlock held, because it may
962 * be called from the irq handler. - Jean II
963 */
964static void smsc_ircc_change_speed(void *priv, u32 speed)
965{
966 struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) priv;
967 struct net_device *dev;
968 int iobase;
969 int last_speed_was_sir;
527b6af4 970
1da177e4
LT		 971 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed);
972
973 IRDA_ASSERT(self != NULL, return;);
974 dev = self->netdev;
975 iobase = self->io.fir_base;
976
977 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
978
979 #if 0
980 /* Temp Hack */
981 speed= 1152000;
982 self->io.speed = speed;
983 last_speed_was_sir = 0;
527b6af4 984 smsc_ircc_fir_start(self);
1da177e4 985 #endif
527b6af4 986
98b77773 987 if (self->io.speed == 0)
1da177e4
LT		 988 smsc_ircc_sir_start(self);
989
990 #if 0
98b77773 991 if (!last_speed_was_sir) speed = self->io.speed;
1da177e4
LT		 992 #endif
993
98b77773
DT		 994 if (self->io.speed != speed)
995 smsc_ircc_set_transceiver_for_speed(self, speed);
1da177e4
LT		 996
997 self->io.speed = speed;
527b6af4 998
98b77773
DT		 999 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1000 if (!last_speed_was_sir) {
1da177e4
LT		 1001 smsc_ircc_fir_stop(self);
1002 smsc_ircc_sir_start(self);
1003 }
527b6af4 1004 smsc_ircc_set_sir_speed(self, speed);
98b77773
DT		 1005 } else {
1006 if (last_speed_was_sir) {
527b6af4 1007 #if SMSC_IRCC2_C_SIR_STOP
1da177e4
LT		 1008 smsc_ircc_sir_stop(self);
1009 #endif
1010 smsc_ircc_fir_start(self);
1011 }
1012 smsc_ircc_set_fir_speed(self, speed);
1013
1014 #if 0
1015 self->tx_buff.len = 10;
1016 self->tx_buff.data = self->tx_buff.head;
527b6af4 1017
1da177e4
LT		 1018 smsc_ircc_dma_xmit(self, iobase, 4000);
1019 #endif
1020 /* Be ready for incoming frames */
1021 smsc_ircc_dma_receive(self, iobase);
1022 }
527b6af4 1023
1da177e4
LT		 1024 netif_wake_queue(dev);
1025}
1026
1027/*
1028 * Function smsc_ircc_set_sir_speed (self, speed)
1029 *
1030 * Set speed of IrDA port to specified baudrate
1031 *
1032 */
1033void smsc_ircc_set_sir_speed(void *priv, __u32 speed)
1034{
1035 struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) priv;
527b6af4 1036 int iobase;
1da177e4
LT		 1037 int fcr; /* FIFO control reg */
1038 int lcr; /* Line control reg */
1039 int divisor;
1040
1041 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed);
1042
1043 IRDA_ASSERT(self != NULL, return;);
1044 iobase = self->io.sir_base;
527b6af4 1045
1da177e4
LT		 1046 /* Update accounting for new speed */
1047 self->io.speed = speed;
1048
1049 /* Turn off interrupts */
98b77773 1050 outb(0, iobase + UART_IER);
1da177e4 1051
98b77773 1052 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
527b6af4 1053
1da177e4
LT		 1054 fcr = UART_FCR_ENABLE_FIFO;
1055
527b6af4 1056 /*
1da177e4
LT		 1057 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1058 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
527b6af4 1059 * about this timeout since it will always be fast enough.
1da177e4 1060 */
98b77773
DT		 1061 fcr |= self->io.speed < 38400 ?
1062 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
527b6af4 1063
1da177e4
LT		 1064 /* IrDA ports use 8N1 */
1065 lcr = UART_LCR_WLEN8;
527b6af4 1066
98b77773
DT		 1067 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1068 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1069 outb(divisor >> 8, iobase + UART_DLM);
1070 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1071 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1da177e4
LT		 1072
1073 /* Turn on interrups */
98b77773 1074 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1da177e4
LT		 1075
1076 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed);
1077}
1078
1079
1080/*
1081 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1082 *
1083 * Transmit the frame!
1084 *
1085 */
1086static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1087{
1088 struct smsc_ircc_cb *self;
1089 unsigned long flags;
1090 s32 speed;
1091 int iobase;
1092 int mtt;
1093
1094 IRDA_ASSERT(dev != NULL, return 0;);
1095 self = (struct smsc_ircc_cb *) dev->priv;
1096 IRDA_ASSERT(self != NULL, return 0;);
1097
1098 iobase = self->io.fir_base;
1099
1100 netif_stop_queue(dev);
1101
1102 /* Make sure test of self->io.speed & speed change are atomic */
1103 spin_lock_irqsave(&self->lock, flags);
1104
1105 /* Check if we need to change the speed after this frame */
1106 speed = irda_get_next_speed(skb);
98b77773 1107 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 1108 /* Check for empty frame */
1109 if (!skb->len) {
1110 /* Note : you should make sure that speed changes
1111 * are not going to corrupt any outgoing frame.
1112 * Look at nsc-ircc for the gory details - Jean II */
527b6af4 1113 smsc_ircc_change_speed(self, speed);
1da177e4
LT		 1114 spin_unlock_irqrestore(&self->lock, flags);
1115 dev_kfree_skb(skb);
1116 return 0;
98b77773
DT		 1117 }
1118
1119 self->new_speed = speed;
1da177e4 1120 }
527b6af4 1121
1da177e4
LT		 1122 memcpy(self->tx_buff.head, skb->data, skb->len);
1123
1124 self->tx_buff.len = skb->len;
1125 self->tx_buff.data = self->tx_buff.head;
527b6af4
DT		 1126
1127 mtt = irda_get_mtt(skb);
1da177e4
LT		 1128 if (mtt) {
1129 int bofs;
1130
527b6af4 1131 /*
1da177e4
LT		 1132 * Compute how many BOFs (STA or PA's) we need to waste the
1133 * min turn time given the speed of the link.
1134 */
1135 bofs = mtt * (self->io.speed / 1000) / 8000;
1136 if (bofs > 4095)
1137 bofs = 4095;
1138
1139 smsc_ircc_dma_xmit(self, iobase, bofs);
1140 } else {
1141 /* Transmit frame */
1142 smsc_ircc_dma_xmit(self, iobase, 0);
1143 }
98b77773 1144
1da177e4
LT		 1145 spin_unlock_irqrestore(&self->lock, flags);
1146 dev_kfree_skb(skb);
1147
1148 return 0;
1149}
1150
1151/*
1152 * Function smsc_ircc_dma_xmit (self, iobase)
1153 *
1154 * Transmit data using DMA
1155 *
1156 */
1157static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int iobase, int bofs)
1158{
1159 u8 ctrl;
1160
1161 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1162#if 1
1163 /* Disable Rx */
1164 register_bank(iobase, 0);
98b77773 1165 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1166#endif
1167 register_bank(iobase, 1);
98b77773
DT		 1168 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1169 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1170
1171 self->io.direction = IO_XMIT;
1172
1173 /* Set BOF additional count for generating the min turn time */
1174 register_bank(iobase, 4);
98b77773
DT		 1175 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1176 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1177 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1da177e4
LT		 1178
1179 /* Set max Tx frame size */
98b77773
DT		 1180 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1181 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1da177e4
LT		 1182
1183 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
527b6af4 1184
1da177e4
LT		 1185 /* Enable burst mode chip Tx DMA */
1186 register_bank(iobase, 1);
98b77773
DT		 1187 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1188 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1189
1190 /* Setup DMA controller (must be done after enabling chip DMA) */
1191 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1192 DMA_TX_MODE);
1193
1194 /* Enable interrupt */
1195
1196 register_bank(iobase, 0);
98b77773
DT		 1197 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1198 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
527b6af4 1199
1da177e4 1200 /* Enable transmit */
98b77773 1201 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1da177e4
LT		 1202}
1203
1204/*
1205 * Function smsc_ircc_dma_xmit_complete (self)
1206 *
527b6af4 1207 * The transfer of a frame in finished. This function will only be called
1da177e4
LT		 1208 * by the interrupt handler
1209 *
1210 */
1211static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self, int iobase)
1212{
1213 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1214#if 0
1215 /* Disable Tx */
1216 register_bank(iobase, 0);
98b77773 1217 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1218#endif
1219 register_bank(self->io.fir_base, 1);
98b77773
DT		 1220 outb(inb(self->io.fir_base + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1221 self->io.fir_base + IRCC_SCE_CFGB);
1da177e4
LT		 1222
1223 /* Check for underrun! */
1224 register_bank(iobase, 0);
98b77773 1225 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1da177e4
LT		 1226 self->stats.tx_errors++;
1227 self->stats.tx_fifo_errors++;
1228
1229 /* Reset error condition */
1230 register_bank(iobase, 0);
98b77773
DT		 1231 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1232 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 1233 } else {
1234 self->stats.tx_packets++;
98b77773 1235 self->stats.tx_bytes += self->tx_buff.len;
1da177e4
LT		 1236 }
1237
1238 /* Check if it's time to change the speed */
1239 if (self->new_speed) {
527b6af4 1240 smsc_ircc_change_speed(self, self->new_speed);
1da177e4
LT		 1241 self->new_speed = 0;
1242 }
1243
1244 netif_wake_queue(self->netdev);
1245}
1246
1247/*
1248 * Function smsc_ircc_dma_receive(self)
1249 *
1250 * Get ready for receiving a frame. The device will initiate a DMA
1251 * if it starts to receive a frame.
1252 *
1253 */
527b6af4 1254static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self, int iobase)
1da177e4
LT		 1255{
1256#if 0
1257 /* Turn off chip DMA */
1258 register_bank(iobase, 1);
98b77773
DT		 1259 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1260 iobase + IRCC_SCE_CFGB);
1da177e4 1261#endif
527b6af4 1262
1da177e4
LT		 1263 /* Disable Tx */
1264 register_bank(iobase, 0);
98b77773 1265 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1266
1267 /* Turn off chip DMA */
1268 register_bank(iobase, 1);
98b77773
DT		 1269 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1270 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1271
1272 self->io.direction = IO_RECV;
1273 self->rx_buff.data = self->rx_buff.head;
1274
1275 /* Set max Rx frame size */
1276 register_bank(iobase, 4);
98b77773
DT		 1277 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1278 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1da177e4
LT		 1279
1280 /* Setup DMA controller */
1281 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1282 DMA_RX_MODE);
1283
1284 /* Enable burst mode chip Rx DMA */
1285 register_bank(iobase, 1);
98b77773
DT		 1286 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1287 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1288
1289 /* Enable interrupt */
1290 register_bank(iobase, 0);
98b77773
DT		 1291 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1292 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1da177e4
LT		 1293
1294 /* Enable receiver */
1295 register_bank(iobase, 0);
527b6af4 1296 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
98b77773 1297 iobase + IRCC_LCR_B);
527b6af4 1298
1da177e4
LT		 1299 return 0;
1300}
1301
1302/*
1303 * Function smsc_ircc_dma_receive_complete(self, iobase)
1304 *
1305 * Finished with receiving frames
1306 *
1307 */
1308static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self, int iobase)
1309{
1310 struct sk_buff *skb;
1311 int len, msgcnt, lsr;
527b6af4 1312
1da177e4 1313 register_bank(iobase, 0);
527b6af4 1314
1da177e4
LT		 1315 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1316#if 0
1317 /* Disable Rx */
1318 register_bank(iobase, 0);
98b77773 1319 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1320#endif
1321 register_bank(iobase, 0);
98b77773
DT		 1322 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1323 lsr= inb(iobase + IRCC_LSR);
1324 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1da177e4
LT		 1325
1326 IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__,
1327 get_dma_residue(self->io.dma));
1328
1329 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1330
98b77773
DT		 1331 /* Look for errors */
1332 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1da177e4 1333 self->stats.rx_errors++;
98b77773
DT		 1334 if (lsr & IRCC_LSR_FRAME_ERROR)
1335 self->stats.rx_frame_errors++;
1336 if (lsr & IRCC_LSR_CRC_ERROR)
1337 self->stats.rx_crc_errors++;
1338 if (lsr & IRCC_LSR_SIZE_ERROR)
1339 self->stats.rx_length_errors++;
1340 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1341 self->stats.rx_length_errors++;
1da177e4
LT		 1342 return;
1343 }
98b77773 1344
1da177e4 1345 /* Remove CRC */
98b77773 1346 len -= self->io.speed < 4000000 ? 2 : 4;
1da177e4 1347
98b77773 1348 if (len < 2 || len > 2050) {
1da177e4
LT		 1349 IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
1350 return;
1351 }
1352 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
1353
98b77773
DT		 1354 skb = dev_alloc_skb(len + 1);
1355 if (!skb) {
1da177e4
LT		 1356 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1357 __FUNCTION__);
1358 return;
527b6af4 1359 }
1da177e4 1360 /* Make sure IP header gets aligned */
527b6af4 1361 skb_reserve(skb, 1);
1da177e4
LT		 1362
1363 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1364 self->stats.rx_packets++;
1365 self->stats.rx_bytes += len;
1366
1367 skb->dev = self->netdev;
1368 skb->mac.raw = skb->data;
1369 skb->protocol = htons(ETH_P_IRDA);
1370 netif_rx(skb);
1371}
1372
1373/*
1374 * Function smsc_ircc_sir_receive (self)
1375 *
1376 * Receive one frame from the infrared port
1377 *
1378 */
527b6af4 1379static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1da177e4
LT		 1380{
1381 int boguscount = 0;
1382 int iobase;
1383
1384 IRDA_ASSERT(self != NULL, return;);
1385
1386 iobase = self->io.sir_base;
1387
527b6af4
DT		 1388 /*
1389 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1390 * async_unwrap_char will deliver all found frames
1da177e4
LT		 1391 */
1392 do {
527b6af4 1393 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
98b77773 1394 inb(iobase + UART_RX));
1da177e4
LT		 1395
1396 /* Make sure we don't stay here to long */
1397 if (boguscount++ > 32) {
1398 IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__);
1399 break;
1400 }
98b77773 1401 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1da177e4
LT		 1402}
1403
1404
1405/*
1406 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1407 *
1408 * An interrupt from the chip has arrived. Time to do some work
1409 *
1410 */
1411static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1412{
1413 struct net_device *dev = (struct net_device *) dev_id;
1414 struct smsc_ircc_cb *self;
1415 int iobase, iir, lcra, lsr;
1416 irqreturn_t ret = IRQ_NONE;
1417
1418 if (dev == NULL) {
527b6af4 1419 printk(KERN_WARNING "%s: irq %d for unknown device.\n",
1da177e4
LT		 1420 driver_name, irq);
1421 goto irq_ret;
1422 }
1423 self = (struct smsc_ircc_cb *) dev->priv;
1424 IRDA_ASSERT(self != NULL, return IRQ_NONE;);
1425
1426 /* Serialise the interrupt handler in various CPUs, stop Tx path */
527b6af4 1427 spin_lock(&self->lock);
1da177e4
LT		 1428
1429 /* Check if we should use the SIR interrupt handler */
98b77773 1430 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1da177e4
LT		 1431 ret = smsc_ircc_interrupt_sir(dev);
1432 goto irq_ret_unlock;
1433 }
1434
1435 iobase = self->io.fir_base;
1436
1437 register_bank(iobase, 0);
98b77773 1438 iir = inb(iobase + IRCC_IIR);
527b6af4 1439 if (iir == 0)
1da177e4
LT		 1440 goto irq_ret_unlock;
1441 ret = IRQ_HANDLED;
1442
1443 /* Disable interrupts */
98b77773
DT		 1444 outb(0, iobase + IRCC_IER);
1445 lcra = inb(iobase + IRCC_LCR_A);
1446 lsr = inb(iobase + IRCC_LSR);
527b6af4 1447
1da177e4
LT		 1448 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1449
1450 if (iir & IRCC_IIR_EOM) {
1451 if (self->io.direction == IO_RECV)
1452 smsc_ircc_dma_receive_complete(self, iobase);
1453 else
1454 smsc_ircc_dma_xmit_complete(self, iobase);
527b6af4 1455
1da177e4
LT		 1456 smsc_ircc_dma_receive(self, iobase);
1457 }
1458
1459 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1460 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/
1461 }
1462
1463 /* Enable interrupts again */
1464
1465 register_bank(iobase, 0);
98b77773 1466 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1da177e4
LT		 1467
1468 irq_ret_unlock:
1469 spin_unlock(&self->lock);
1470 irq_ret:
1471 return ret;
1472}
1473
1474/*
1475 * Function irport_interrupt_sir (irq, dev_id, regs)
1476 *
1477 * Interrupt handler for SIR modes
1478 */
1479static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1480{
1481 struct smsc_ircc_cb *self = dev->priv;
1482 int boguscount = 0;
1483 int iobase;
1484 int iir, lsr;
1485
1486 /* Already locked comming here in smsc_ircc_interrupt() */
1487 /*spin_lock(&self->lock);*/
1488
1489 iobase = self->io.sir_base;
1490
98b77773 1491 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1492 if (iir == 0)
1493 return IRQ_NONE;
1494 while (iir) {
1495 /* Clear interrupt */
98b77773 1496 lsr = inb(iobase + UART_LSR);
1da177e4 1497
527b6af4 1498 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1da177e4
LT		 1499 __FUNCTION__, iir, lsr, iobase);
1500
1501 switch (iir) {
1502 case UART_IIR_RLSI:
1503 IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__);
1504 break;
1505 case UART_IIR_RDI:
1506 /* Receive interrupt */
1507 smsc_ircc_sir_receive(self);
1508 break;
1509 case UART_IIR_THRI:
1510 if (lsr & UART_LSR_THRE)
1511 /* Transmitter ready for data */
1512 smsc_ircc_sir_write_wakeup(self);
1513 break;
1514 default:
1515 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1516 __FUNCTION__, iir);
1517 break;
527b6af4
DT		 1518 }
1519
1da177e4
LT		 1520 /* Make sure we don't stay here to long */
1521 if (boguscount++ > 100)
1522 break;
1523
527b6af4 1524 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1525 }
1526 /*spin_unlock(&self->lock);*/
1527 return IRQ_HANDLED;
1528}
1529
1530
1531#if 0 /* unused */
1532/*
1533 * Function ircc_is_receiving (self)
1534 *
1535 * Return TRUE is we are currently receiving a frame
1536 *
1537 */
1538static int ircc_is_receiving(struct smsc_ircc_cb *self)
1539{
1540 int status = FALSE;
1541 /* int iobase; */
1542
1543 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1544
1545 IRDA_ASSERT(self != NULL, return FALSE;);
1546
1547 IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__,
1548 get_dma_residue(self->io.dma));
1549
1550 status = (self->rx_buff.state != OUTSIDE_FRAME);
527b6af4 1551
1da177e4
LT		 1552 return status;
1553}
1554#endif /* unused */
1555
1556
1557/*
1558 * Function smsc_ircc_net_open (dev)
1559 *
1560 * Start the device
1561 *
1562 */
1563static int smsc_ircc_net_open(struct net_device *dev)
1564{
1565 struct smsc_ircc_cb *self;
1566 int iobase;
1567 char hwname[16];
1568 unsigned long flags;
1569
1570 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 1571
1da177e4
LT		 1572 IRDA_ASSERT(dev != NULL, return -1;);
1573 self = (struct smsc_ircc_cb *) dev->priv;
1574 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1575
1da177e4
LT		 1576 iobase = self->io.fir_base;
1577
527b6af4 1578 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1da177e4
LT		 1579 (void *) dev)) {
1580 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1581 __FUNCTION__, self->io.irq);
1582 return -EAGAIN;
1583 }
1584
1585 spin_lock_irqsave(&self->lock, flags);
1586 /*smsc_ircc_sir_start(self);*/
1587 self->io.speed = 0;
1588 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1589 spin_unlock_irqrestore(&self->lock, flags);
527b6af4 1590
1da177e4
LT		 1591 /* Give self a hardware name */
1592 /* It would be cool to offer the chip revision here - Jean II */
1593 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1594
527b6af4 1595 /*
1da177e4 1596 * Open new IrLAP layer instance, now that everything should be
527b6af4 1597 * initialized properly
1da177e4
LT		 1598 */
1599 self->irlap = irlap_open(dev, &self->qos, hwname);
1600
1601 /*
1602 * Always allocate the DMA channel after the IRQ,
1603 * and clean up on failure.
1604 */
1605 if (request_dma(self->io.dma, dev->name)) {
1606 smsc_ircc_net_close(dev);
1607
1608 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1609 __FUNCTION__, self->io.dma);
1610 return -EAGAIN;
1611 }
527b6af4 1612
1da177e4
LT		 1613 netif_start_queue(dev);
1614
1615 return 0;
1616}
1617
1618/*
1619 * Function smsc_ircc_net_close (dev)
1620 *
1621 * Stop the device
1622 *
1623 */
1624static int smsc_ircc_net_close(struct net_device *dev)
1625{
1626 struct smsc_ircc_cb *self;
1627 int iobase;
1628
1629 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 1630
1da177e4 1631 IRDA_ASSERT(dev != NULL, return -1;);
527b6af4 1632 self = (struct smsc_ircc_cb *) dev->priv;
1da177e4 1633 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1634
1da177e4
LT		 1635 iobase = self->io.fir_base;
1636
1637 /* Stop device */
1638 netif_stop_queue(dev);
527b6af4 1639
1da177e4
LT		 1640 /* Stop and remove instance of IrLAP */
1641 if (self->irlap)
1642 irlap_close(self->irlap);
1643 self->irlap = NULL;
1644
1645 free_irq(self->io.irq, dev);
1da177e4 1646 disable_dma(self->io.dma);
1da177e4
LT		 1647 free_dma(self->io.dma);
1648
1649 return 0;
1650}
1651
1652
1653static void smsc_ircc_suspend(struct smsc_ircc_cb *self)
1654{
1655 IRDA_MESSAGE("%s, Suspending\n", driver_name);
1656
98b77773
DT		 1657 if (!self->io.suspended) {
1658 smsc_ircc_net_close(self->netdev);
1659 self->io.suspended = 1;
1660 }
1da177e4
LT		 1661}
1662
1663static void smsc_ircc_wakeup(struct smsc_ircc_cb *self)
1664{
1665 if (!self->io.suspended)
1666 return;
1667
1668 /* The code was doing a "cli()" here, but this can't be right.
1669 * If you need protection, do it in net_open with a spinlock
1670 * or give a good reason. - Jean II */
1671
1672 smsc_ircc_net_open(self->netdev);
527b6af4 1673
1da177e4
LT		 1674 IRDA_MESSAGE("%s, Waking up\n", driver_name);
1675}
1676
1677static int smsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data)
1678{
1679 struct smsc_ircc_cb *self = (struct smsc_ircc_cb*) dev->data;
1680 if (self) {
1681 switch (rqst) {
1682 case PM_SUSPEND:
1683 smsc_ircc_suspend(self);
1684 break;
1685 case PM_RESUME:
1686 smsc_ircc_wakeup(self);
1687 break;
1688 }
1689 }
1690 return 0;
1691}
1692
1693/*
1694 * Function smsc_ircc_close (self)
1695 *
1696 * Close driver instance
1697 *
1698 */
1699static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1700{
1701 int iobase;
1702 unsigned long flags;
1703
1704 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1705
1706 IRDA_ASSERT(self != NULL, return -1;);
1707
1708 iobase = self->io.fir_base;
1709
1710 if (self->pmdev)
1711 pm_unregister(self->pmdev);
1712
1713 /* Remove netdevice */
1714 unregister_netdev(self->netdev);
1715
1716 /* Make sure the irq handler is not exectuting */
1717 spin_lock_irqsave(&self->lock, flags);
1718
1719 /* Stop interrupts */
1720 register_bank(iobase, 0);
98b77773
DT		 1721 outb(0, iobase + IRCC_IER);
1722 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1723 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 1724#if 0
1725 /* Reset to SIR mode */
1726 register_bank(iobase, 1);
98b77773
DT		 1727 outb(IRCC_CFGA_IRDA_SIR_A|IRCC_CFGA_TX_POLARITY, iobase + IRCC_SCE_CFGA);
1728 outb(IRCC_CFGB_IR, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1729#endif
1730 spin_unlock_irqrestore(&self->lock, flags);
1731
1732 /* Release the PORTS that this driver is using */
1733 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1734 self->io.fir_base);
1735
1736 release_region(self->io.fir_base, self->io.fir_ext);
1737
527b6af4 1738 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1da177e4
LT		 1739 self->io.sir_base);
1740
1741 release_region(self->io.sir_base, self->io.sir_ext);
1742
1743 if (self->tx_buff.head)
1744 dma_free_coherent(NULL, self->tx_buff.truesize,
1745 self->tx_buff.head, self->tx_buff_dma);
527b6af4 1746
1da177e4
LT		 1747 if (self->rx_buff.head)
1748 dma_free_coherent(NULL, self->rx_buff.truesize,
1749 self->rx_buff.head, self->rx_buff_dma);
1750
1751 free_netdev(self->netdev);
1752
1753 return 0;
1754}
1755
1756static void __exit smsc_ircc_cleanup(void)
1757{
1758 int i;
1759
1760 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1761
98b77773 1762 for (i = 0; i < 2; i++) {
1da177e4
LT		 1763 if (dev_self[i])
1764 smsc_ircc_close(dev_self[i]);
1765 }
1766}
1767
1768/*
1769 * Start SIR operations
1770 *
1771 * This function *must* be called with spinlock held, because it may
1772 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1773 */
1774void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1775{
1776 struct net_device *dev;
1777 int fir_base, sir_base;
1778
1779 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1780
527b6af4 1781 IRDA_ASSERT(self != NULL, return;);
98b77773 1782 dev = self->netdev;
527b6af4 1783 IRDA_ASSERT(dev != NULL, return;);
1da177e4
LT		 1784 dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1785
1786 fir_base = self->io.fir_base;
1787 sir_base = self->io.sir_base;
1788
1789 /* Reset everything */
98b77773 1790 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1da177e4
LT		 1791
1792 #if SMSC_IRCC2_C_SIR_STOP
1793 /*smsc_ircc_sir_stop(self);*/
1794 #endif
1795
1796 register_bank(fir_base, 1);
98b77773 1797 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1da177e4
LT		 1798
1799 /* Initialize UART */
98b77773
DT		 1800 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1801 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
527b6af4 1802
1da177e4 1803 /* Turn on interrups */
98b77773 1804 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1da177e4
LT		 1805
1806 IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__);
1807
98b77773 1808 outb(0x00, fir_base + IRCC_MASTER);
1da177e4
LT		 1809}
1810
1811#if SMSC_IRCC2_C_SIR_STOP
1812void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1813{
1814 int iobase;
1815
1816 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1817 iobase = self->io.sir_base;
1818
1819 /* Reset UART */
98b77773 1820 outb(0, iobase + UART_MCR);
527b6af4 1821
1da177e4 1822 /* Turn off interrupts */
98b77773 1823 outb(0, iobase + UART_IER);
1da177e4
LT		 1824}
1825#endif
1826
1827/*
1828 * Function smsc_sir_write_wakeup (self)
1829 *
1830 * Called by the SIR interrupt handler when there's room for more data.
1831 * If we have more packets to send, we send them here.
1832 *
1833 */
1834static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1835{
1836 int actual = 0;
1837 int iobase;
1838 int fcr;
1839
1840 IRDA_ASSERT(self != NULL, return;);
1841
1842 IRDA_DEBUG(4, "%s\n", __FUNCTION__);
1843
1844 iobase = self->io.sir_base;
1845
1846 /* Finished with frame? */
1847 if (self->tx_buff.len > 0) {
1848 /* Write data left in transmit buffer */
527b6af4 1849 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1da177e4
LT		 1850 self->tx_buff.data, self->tx_buff.len);
1851 self->tx_buff.data += actual;
1852 self->tx_buff.len -= actual;
1853 } else {
527b6af4 1854
1da177e4 1855 /*if (self->tx_buff.len ==0) {*/
527b6af4
DT		 1856
1857 /*
1858 * Now serial buffer is almost free & we can start
1da177e4
LT		 1859 * transmission of another packet. But first we must check
1860 * if we need to change the speed of the hardware
1861 */
1862 if (self->new_speed) {
1863 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1864 __FUNCTION__, self->new_speed);
1865 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1866 smsc_ircc_change_speed(self, self->new_speed);
1867 self->new_speed = 0;
1868 } else {
1869 /* Tell network layer that we want more frames */
1870 netif_wake_queue(self->netdev);
1871 }
1872 self->stats.tx_packets++;
1873
98b77773
DT		 1874 if (self->io.speed <= 115200) {
1875 /*
1876 * Reset Rx FIFO to make sure that all reflected transmit data
1877 * is discarded. This is needed for half duplex operation
1878 */
1879 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
1880 fcr |= self->io.speed < 38400 ?
1881 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1da177e4 1882
98b77773 1883 outb(fcr, iobase + UART_FCR);
1da177e4 1884
98b77773
DT		 1885 /* Turn on receive interrupts */
1886 outb(UART_IER_RDI, iobase + UART_IER);
1da177e4
LT		 1887 }
1888 }
1889}
1890
1891/*
1892 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
1893 *
1894 * Fill Tx FIFO with transmit data
1895 *
1896 */
1897static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1898{
1899 int actual = 0;
527b6af4 1900
1da177e4 1901 /* Tx FIFO should be empty! */
98b77773 1902 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
1da177e4
LT		 1903 IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__);
1904 return 0;
1905 }
527b6af4 1906
1da177e4 1907 /* Fill FIFO with current frame */
98b77773 1908 while (fifo_size-- > 0 && actual < len) {
1da177e4 1909 /* Transmit next byte */
98b77773 1910 outb(buf[actual], iobase + UART_TX);
1da177e4
LT		 1911 actual++;
1912 }
1913 return actual;
1914}
1915
1916/*
1917 * Function smsc_ircc_is_receiving (self)
1918 *
1919 * Returns true is we are currently receiving data
1920 *
1921 */
1922static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
1923{
1924 return (self->rx_buff.state != OUTSIDE_FRAME);
1925}
1926
1927
1928/*
1929 * Function smsc_ircc_probe_transceiver(self)
1930 *
1931 * Tries to find the used Transceiver
1932 *
1933 */
1934static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
1935{
1936 unsigned int i;
527b6af4 1937
1da177e4 1938 IRDA_ASSERT(self != NULL, return;);
527b6af4 1939
98b77773
DT		 1940 for (i = 0; smsc_transceivers[i].name != NULL; i++)
1941 if (smsc_transceivers[i].probe(self->io.fir_base)) {
1da177e4
LT		 1942 IRDA_MESSAGE(" %s transceiver found\n",
1943 smsc_transceivers[i].name);
98b77773 1944 self->transceiver= i + 1;
1da177e4
LT		 1945 return;
1946 }
98b77773 1947
1da177e4
LT		 1948 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
1949 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
527b6af4 1950
98b77773 1951 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
1da177e4
LT		 1952}
1953
1954
1955/*
1956 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
1957 *
1958 * Set the transceiver according to the speed
1959 *
1960 */
1961static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
1962{
1963 unsigned int trx;
527b6af4 1964
1da177e4 1965 trx = self->transceiver;
98b77773
DT		 1966 if (trx > 0)
1967 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
1da177e4
LT		 1968}
1969
1970/*
1971 * Function smsc_ircc_wait_hw_transmitter_finish ()
1972 *
1973 * Wait for the real end of HW transmission
1974 *
1975 * The UART is a strict FIFO, and we get called only when we have finished
1976 * pushing data to the FIFO, so the maximum amount of time we must wait
1977 * is only for the FIFO to drain out.
1978 *
1979 * We use a simple calibrated loop. We may need to adjust the loop
1980 * delay (udelay) to balance I/O traffic and latency. And we also need to
1981 * adjust the maximum timeout.
1982 * It would probably be better to wait for the proper interrupt,
1983 * but it doesn't seem to be available.
1984 *
1985 * We can't use jiffies or kernel timers because :
1986 * 1) We are called from the interrupt handler, which disable softirqs,
1987 * so jiffies won't be increased
1988 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
1989 * want to wait that long to detect stuck hardware.
1990 * Jean II
1991 */
1992
1993static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
1994{
98b77773 1995 int iobase = self->io.sir_base;
1da177e4 1996 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
527b6af4 1997
1da177e4 1998 /* Calibrated busy loop */
98b77773 1999 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
1da177e4
LT		 2000 udelay(1);
2001
98b77773 2002 if (count == 0)
1da177e4
LT		 2003 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__);
2004}
2005
2006
2007/* PROBING
2008 *
2009 *
2010 */
2011
2012static int __init smsc_ircc_look_for_chips(void)
2013{
2014 smsc_chip_address_t *address;
98b77773 2015 char *type;
1da177e4 2016 unsigned int cfg_base, found;
527b6af4 2017
1da177e4
LT		 2018 found = 0;
2019 address = possible_addresses;
527b6af4 2020
98b77773 2021 while (address->cfg_base) {
1da177e4 2022 cfg_base = address->cfg_base;
527b6af4 2023
1da177e4 2024 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/
527b6af4 2025
98b77773 2026 if (address->type & SMSCSIO_TYPE_FDC) {
1da177e4 2027 type = "FDC";
98b77773
DT		 2028 if (address->type & SMSCSIO_TYPE_FLAT)
2029 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2030 found++;
2031
2032 if (address->type & SMSCSIO_TYPE_PAGED)
2033 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2034 found++;
1da177e4 2035 }
98b77773 2036 if (address->type & SMSCSIO_TYPE_LPC) {
1da177e4 2037 type = "LPC";
98b77773
DT		 2038 if (address->type & SMSCSIO_TYPE_FLAT)
2039 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2040 found++;
2041
2042 if (address->type & SMSCSIO_TYPE_PAGED)
2043 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2044 found++;
1da177e4
LT		 2045 }
2046 address++;
2047 }
2048 return found;
527b6af4 2049}
1da177e4
LT		 2050
2051/*
2052 * Function smsc_superio_flat (chip, base, type)
2053 *
2054 * Try to get configuration of a smc SuperIO chip with flat register model
2055 *
2056 */
2057static int __init smsc_superio_flat(const smsc_chip_t *chips, unsigned short cfgbase, char *type)
2058{
2059 unsigned short firbase, sirbase;
2060 u8 mode, dma, irq;
2061 int ret = -ENODEV;
2062
2063 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2064
98b77773 2065 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
1da177e4
LT		 2066 return ret;
2067
2068 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
98b77773 2069 mode = inb(cfgbase + 1);
527b6af4 2070
1da177e4 2071 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/
527b6af4 2072
98b77773 2073 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
1da177e4
LT		 2074 IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__);
2075
2076 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
98b77773 2077 sirbase = inb(cfgbase + 1) << 2;
1da177e4 2078
527b6af4 2079 /* FIR iobase */
1da177e4 2080 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
98b77773 2081 firbase = inb(cfgbase + 1) << 3;
1da177e4
LT		 2082
2083 /* DMA */
2084 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
98b77773 2085 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
527b6af4 2086
1da177e4
LT		 2087 /* IRQ */
2088 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
98b77773 2089 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
1da177e4
LT		 2090
2091 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode);
2092
98b77773
DT		 2093 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2094 ret = 0;
527b6af4 2095
1da177e4
LT		 2096 /* Exit configuration */
2097 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2098
2099 return ret;
2100}
2101
2102/*
2103 * Function smsc_superio_paged (chip, base, type)
2104 *
2105 * Try to get configuration of a smc SuperIO chip with paged register model
2106 *
2107 */
2108static int __init smsc_superio_paged(const smsc_chip_t *chips, unsigned short cfg_base, char *type)
2109{
2110 unsigned short fir_io, sir_io;
2111 int ret = -ENODEV;
527b6af4 2112
1da177e4
LT		 2113 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2114
98b77773 2115 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
1da177e4 2116 return ret;
527b6af4 2117
1da177e4
LT		 2118 /* Select logical device (UART2) */
2119 outb(0x07, cfg_base);
2120 outb(0x05, cfg_base + 1);
527b6af4 2121
1da177e4
LT		 2122 /* SIR iobase */
2123 outb(0x60, cfg_base);
98b77773 2124 sir_io = inb(cfg_base + 1) << 8;
1da177e4
LT		 2125 outb(0x61, cfg_base);
2126 sir_io |= inb(cfg_base + 1);
527b6af4 2127
1da177e4
LT		 2128 /* Read FIR base */
2129 outb(0x62, cfg_base);
2130 fir_io = inb(cfg_base + 1) << 8;
2131 outb(0x63, cfg_base);
2132 fir_io |= inb(cfg_base + 1);
2133 outb(0x2b, cfg_base); /* ??? */
2134
98b77773
DT		 2135 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2136 ret = 0;
527b6af4 2137
1da177e4
LT		 2138 /* Exit configuration */
2139 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2140
2141 return ret;
2142}
2143
2144
98b77773 2145static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
1da177e4
LT		 2146{
2147 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2148
2149 outb(reg, cfg_base);
98b77773 2150 return inb(cfg_base) != reg ? -1 : 0;
1da177e4
LT		 2151}
2152
98b77773 2153static const smsc_chip_t * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const smsc_chip_t *chip, char *type)
1da177e4 2154{
98b77773 2155 u8 devid, xdevid, rev;
1da177e4
LT		 2156
2157 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2158
2159 /* Leave configuration */
2160
2161 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2162
2163 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2164 return NULL;
2165
2166 outb(reg, cfg_base);
2167
98b77773 2168 xdevid = inb(cfg_base + 1);
1da177e4
LT		 2169
2170 /* Enter configuration */
2171
2172 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2173
2174 #if 0
2175 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2176 return NULL;
2177 #endif
527b6af4 2178
1da177e4
LT		 2179 /* probe device ID */
2180
98b77773 2181 if (smsc_access(cfg_base, reg))
1da177e4
LT		 2182 return NULL;
2183
98b77773 2184 devid = inb(cfg_base + 1);
527b6af4 2185
98b77773 2186 if (devid == 0 || devid == 0xff) /* typical values for unused port */
1da177e4
LT		 2187 return NULL;
2188
2189 /* probe revision ID */
2190
98b77773 2191 if (smsc_access(cfg_base, reg + 1))
1da177e4
LT		 2192 return NULL;
2193
98b77773 2194 rev = inb(cfg_base + 1);
1da177e4 2195
98b77773 2196 if (rev >= 128) /* i think this will make no sense */
1da177e4
LT		 2197 return NULL;
2198
98b77773 2199 if (devid == xdevid) /* protection against false positives */
1da177e4
LT		 2200 return NULL;
2201
2202 /* Check for expected device ID; are there others? */
2203
98b77773 2204 while (chip->devid != devid) {
1da177e4
LT		 2205
2206 chip++;
2207
98b77773 2208 if (chip->name == NULL)
1da177e4
LT		 2209 return NULL;
2210 }
2211
98b77773
DT		 2212 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2213 devid, rev, cfg_base, type, chip->name);
1da177e4 2214
98b77773 2215 if (chip->rev > rev) {
527b6af4 2216 IRDA_MESSAGE("Revision higher than expected\n");
1da177e4
LT		 2217 return NULL;
2218 }
527b6af4 2219
98b77773 2220 if (chip->flags & NoIRDA)
1da177e4
LT		 2221 IRDA_MESSAGE("chipset does not support IRDA\n");
2222
2223 return chip;
2224}
2225
2226static int __init smsc_superio_fdc(unsigned short cfg_base)
2227{
2228 int ret = -1;
2229
2230 if (!request_region(cfg_base, 2, driver_name)) {
2231 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2232 __FUNCTION__, cfg_base);
2233 } else {
98b77773
DT		 2234 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2235 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
1da177e4
LT		 2236 ret = 0;
2237
2238 release_region(cfg_base, 2);
2239 }
2240
2241 return ret;
2242}
2243
2244static int __init smsc_superio_lpc(unsigned short cfg_base)
2245{
2246 int ret = -1;
2247
2248 if (!request_region(cfg_base, 2, driver_name)) {
2249 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2250 __FUNCTION__, cfg_base);
2251 } else {
98b77773
DT		 2252 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2253 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
1da177e4 2254 ret = 0;
98b77773 2255
1da177e4
LT		 2256 release_region(cfg_base, 2);
2257 }
2258 return ret;
2259}
2260
2261/************************************************
2262 *
2263 * Transceivers specific functions
2264 *
2265 ************************************************/
2266
2267
2268/*
2269 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2270 *
2271 * Program transceiver through smsc-ircc ATC circuitry
2272 *
2273 */
2274
2275static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2276{
2277 unsigned long jiffies_now, jiffies_timeout;
98b77773 2278 u8 val;
527b6af4 2279
98b77773
DT		 2280 jiffies_now = jiffies;
2281 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
527b6af4 2282
1da177e4
LT		 2283 /* ATC */
2284 register_bank(fir_base, 4);
98b77773
DT		 2285 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2286 fir_base + IRCC_ATC);
2287
2288 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2289 !time_after(jiffies, jiffies_timeout))
2290 /* empty */;
2291
2292 if (val)
1da177e4 2293 IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__,
98b77773 2294 inb(fir_base + IRCC_ATC));
1da177e4
LT		 2295}
2296
2297/*
2298 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2299 *
2300 * Probe transceiver smsc-ircc ATC circuitry
2301 *
2302 */
2303
2304static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2305{
2306 return 0;
2307}
2308
2309/*
2310 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2311 *
527b6af4 2312 * Set transceiver
1da177e4
LT		 2313 *
2314 */
2315
2316static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2317{
98b77773 2318 u8 fast_mode;
527b6af4 2319
98b77773
DT		 2320 switch (speed) {
2321 default:
2322 case 576000 :
527b6af4 2323 fast_mode = 0;
1da177e4 2324 break;
98b77773
DT		 2325 case 1152000 :
2326 case 4000000 :
1da177e4
LT		 2327 fast_mode = IRCC_LCR_A_FAST;
2328 break;
1da177e4
LT		 2329 }
2330 register_bank(fir_base, 0);
98b77773 2331 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 2332}
2333
2334/*
2335 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2336 *
527b6af4 2337 * Probe transceiver
1da177e4
LT		 2338 *
2339 */
2340
2341static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2342{
2343 return 0;
2344}
2345
2346/*
2347 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2348 *
527b6af4 2349 * Set transceiver
1da177e4
LT		 2350 *
2351 */
2352
2353static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2354{
98b77773 2355 u8 fast_mode;
527b6af4 2356
98b77773
DT		 2357 switch (speed) {
2358 default:
2359 case 576000 :
527b6af4 2360 fast_mode = 0;
1da177e4 2361 break;
98b77773
DT		 2362 case 1152000 :
2363 case 4000000 :
1da177e4
LT		 2364 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
2365 break;
527b6af4 2366
1da177e4
LT		 2367 }
2368 /* This causes an interrupt */
2369 register_bank(fir_base, 0);
98b77773 2370 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 2371}
2372
2373/*
2374 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
2375 *
527b6af4 2376 * Probe transceiver
1da177e4
LT		 2377 *
2378 */
2379
2380static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
2381{
2382 return 0;
2383}
2384
2385
2386module_init(smsc_ircc_init);
2387module_exit(smsc_ircc_cleanup);
Linux kernel - Deliverables
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