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[PATCH] smsc-ircc2: remove typedefs
[deliverable/linux.git] / drivers / net / irda / smsc-ircc2.c
CommitLineData
1da177e4
LT		 1/*********************************************************************
2 * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
3 *
4 * Description: Driver for the SMC Infrared Communications Controller
5 * Status: Experimental.
6 * Author: Daniele Peri (peri@csai.unipa.it)
527b6af4
DT		 7 * Created at:
8 * Modified at:
9 * Modified by:
10 *
1da177e4
LT		 11 * Copyright (c) 2002 Daniele Peri
12 * All Rights Reserved.
13 * Copyright (c) 2002 Jean Tourrilhes
14 *
15 *
16 * Based on smc-ircc.c:
17 *
18 * Copyright (c) 2001 Stefani Seibold
19 * Copyright (c) 1999-2001 Dag Brattli
527b6af4 20 * Copyright (c) 1998-1999 Thomas Davis,
1da177e4
LT		 21 *
22 * and irport.c:
23 *
24 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
25 *
527b6af4
DT		 26 *
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License as
29 * published by the Free Software Foundation; either version 2 of
1da177e4 30 * the License, or (at your option) any later version.
527b6af4 31 *
1da177e4
LT		 32 * This program is distributed in the hope that it will be useful,
33 * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 * GNU General Public License for more details.
527b6af4
DT		 36 *
37 * You should have received a copy of the GNU General Public License
38 * along with this program; if not, write to the Free Software
39 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1da177e4
LT		 40 * MA 02111-1307 USA
41 *
42 ********************************************************************/
43
44#include <linux/module.h>
45#include <linux/kernel.h>
46#include <linux/types.h>
47#include <linux/skbuff.h>
48#include <linux/netdevice.h>
49#include <linux/ioport.h>
50#include <linux/delay.h>
51#include <linux/slab.h>
52#include <linux/init.h>
53#include <linux/rtnetlink.h>
54#include <linux/serial_reg.h>
55#include <linux/dma-mapping.h>
56
57#include <asm/io.h>
58#include <asm/dma.h>
59#include <asm/byteorder.h>
60
61#include <linux/spinlock.h>
62#include <linux/pm.h>
63
64#include <net/irda/wrapper.h>
65#include <net/irda/irda.h>
66#include <net/irda/irda_device.h>
67
68#include "smsc-ircc2.h"
69#include "smsc-sio.h"
70
98b77773
DT		 71
72MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
73MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
74MODULE_LICENSE("GPL");
75
76
77static int ircc_dma = 255;
78module_param(ircc_dma, int, 0);
79MODULE_PARM_DESC(ircc_dma, "DMA channel");
80
81static int ircc_irq = 255;
82module_param(ircc_irq, int, 0);
83MODULE_PARM_DESC(ircc_irq, "IRQ line");
84
85static int ircc_fir;
86module_param(ircc_fir, int, 0);
87MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
88
89static int ircc_sir;
90module_param(ircc_sir, int, 0);
91MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
92
93static int ircc_cfg;
94module_param(ircc_cfg, int, 0);
95MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
96
97static int ircc_transceiver;
98module_param(ircc_transceiver, int, 0);
99MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
100
1da177e4
LT		 101/* Types */
102
103struct smsc_transceiver {
104 char *name;
527b6af4 105 void (*set_for_speed)(int fir_base, u32 speed);
1da177e4
LT		 106 int (*probe)(int fir_base);
107};
1da177e4
LT		 108
109struct smsc_chip {
110 char *name;
111 #if 0
112 u8 type;
113 #endif
114 u16 flags;
115 u8 devid;
116 u8 rev;
117};
1da177e4
LT		 118
119struct smsc_chip_address {
120 unsigned int cfg_base;
121 unsigned int type;
122};
1da177e4
LT		 123
124/* Private data for each instance */
125struct smsc_ircc_cb {
126 struct net_device *netdev; /* Yes! we are some kind of netdevice */
127 struct net_device_stats stats;
128 struct irlap_cb *irlap; /* The link layer we are binded to */
527b6af4 129
1da177e4
LT		 130 chipio_t io; /* IrDA controller information */
131 iobuff_t tx_buff; /* Transmit buffer */
132 iobuff_t rx_buff; /* Receive buffer */
133 dma_addr_t tx_buff_dma;
134 dma_addr_t rx_buff_dma;
135
136 struct qos_info qos; /* QoS capabilities for this device */
137
138 spinlock_t lock; /* For serializing operations */
527b6af4 139
1da177e4
LT		 140 __u32 new_speed;
141 __u32 flags; /* Interface flags */
142
143 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
144 int tx_len; /* Number of frames in tx_buff */
145
146 int transceiver;
147 struct pm_dev *pmdev;
148};
149
150/* Constants */
151
152static const char *driver_name = "smsc-ircc2";
1da177e4
LT		 153#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
154#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
98b77773 155#define SMSC_IRCC2_C_NET_TIMEOUT 0
1da177e4
LT		 156#define SMSC_IRCC2_C_SIR_STOP 0
157
158/* Prototypes */
159
160static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
161static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
162static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
163static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
164static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
165static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
527b6af4 166static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self, int iobase);
1da177e4
LT		 167static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self, int iobase);
168static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
169static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
170static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
171static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int iobase, int bofs);
172static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self, int iobase);
173static void smsc_ircc_change_speed(void *priv, u32 speed);
174static void smsc_ircc_set_sir_speed(void *priv, u32 speed);
175static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs);
176static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
177static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
178#if SMSC_IRCC2_C_SIR_STOP
179static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
180#endif
181static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
182static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
183static int smsc_ircc_net_open(struct net_device *dev);
184static int smsc_ircc_net_close(struct net_device *dev);
185static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
186#if SMSC_IRCC2_C_NET_TIMEOUT
187static void smsc_ircc_timeout(struct net_device *dev);
188#endif
189static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
190static int smsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data);
191static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
192static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
193static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
194static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
195
196/* Probing */
197static int __init smsc_ircc_look_for_chips(void);
b6158d23
DT		 198static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
199static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
200static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
1da177e4
LT		 201static int __init smsc_superio_fdc(unsigned short cfg_base);
202static int __init smsc_superio_lpc(unsigned short cfg_base);
203
204/* Transceivers specific functions */
205
206static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
207static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
208static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
209static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
210static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
211static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
212
213/* Power Management */
214
215static void smsc_ircc_suspend(struct smsc_ircc_cb *self);
216static void smsc_ircc_wakeup(struct smsc_ircc_cb *self);
217static int smsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data);
218
219
220/* Transceivers for SMSC-ircc */
221
b6158d23 222static struct smsc_transceiver smsc_transceivers[] =
1da177e4 223{
98b77773
DT		 224 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
225 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
226 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
227 { NULL, NULL }
1da177e4 228};
a956f4ca 229#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
1da177e4
LT		 230
231/* SMC SuperIO chipsets definitions */
232
233#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
234#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
235#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
236#define SIR 0 /* SuperIO Chip has only slow IRDA */
237#define FIR 4 /* SuperIO Chip has fast IRDA */
238#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
239
b6158d23 240static struct smsc_chip __initdata fdc_chips_flat[] =
1da177e4
LT		 241{
242 /* Base address 0x3f0 or 0x370 */
243 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
244 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
245 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
246 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
247 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
248 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
249 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
250 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
251 { NULL }
252};
253
b6158d23 254static struct smsc_chip __initdata fdc_chips_paged[] =
1da177e4
LT		 255{
256 /* Base address 0x3f0 or 0x370 */
257 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
258 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
259 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
260 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
261 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
262 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
263 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
264 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
265 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
266 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
267 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
268 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
269 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
270 { NULL }
271};
272
b6158d23 273static struct smsc_chip __initdata lpc_chips_flat[] =
1da177e4
LT		 274{
275 /* Base address 0x2E or 0x4E */
276 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
277 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
278 { NULL }
279};
280
b6158d23 281static struct smsc_chip __initdata lpc_chips_paged[] =
1da177e4
LT		 282{
283 /* Base address 0x2E or 0x4E */
284 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
285 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
286 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
287 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
288 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
289 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
290 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
291 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
292 { NULL }
293};
294
295#define SMSCSIO_TYPE_FDC 1
296#define SMSCSIO_TYPE_LPC 2
297#define SMSCSIO_TYPE_FLAT 4
298#define SMSCSIO_TYPE_PAGED 8
299
b6158d23 300static struct smsc_chip_address __initdata possible_addresses[] =
1da177e4 301{
98b77773
DT		 302 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
303 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
304 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
305 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
306 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
307 { 0, 0 }
1da177e4
LT		 308};
309
310/* Globals */
311
98b77773
DT		 312static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
313static unsigned short dev_count;
1da177e4
LT		 314
315static inline void register_bank(int iobase, int bank)
316{
98b77773
DT		 317 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
318 iobase + IRCC_MASTER);
1da177e4
LT		 319}
320
321
322/*******************************************************************************
323 *
324 *
325 * SMSC-ircc stuff
326 *
327 *
328 *******************************************************************************/
329
330/*
331 * Function smsc_ircc_init ()
332 *
333 * Initialize chip. Just try to find out how many chips we are dealing with
334 * and where they are
335 */
336static int __init smsc_ircc_init(void)
337{
98b77773 338 int ret = -ENODEV;
1da177e4
LT		 339
340 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
341
98b77773 342 dev_count = 0;
527b6af4 343
98b77773 344 if (ircc_fir > 0 && ircc_sir > 0) {
1da177e4
LT		 345 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
346 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
347
348 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq) == 0)
349 return 0;
350
351 return -ENODEV;
352 }
353
354 /* try user provided configuration register base address */
98b77773 355 if (ircc_cfg > 0) {
1da177e4
LT		 356 IRDA_MESSAGE(" Overriding configuration address 0x%04x\n",
357 ircc_cfg);
358 if (!smsc_superio_fdc(ircc_cfg))
359 ret = 0;
360 if (!smsc_superio_lpc(ircc_cfg))
361 ret = 0;
362 }
527b6af4 363
98b77773
DT		 364 if (smsc_ircc_look_for_chips() > 0)
365 ret = 0;
527b6af4 366
1da177e4
LT		 367 return ret;
368}
369
370/*
371 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
372 *
373 * Try to open driver instance
374 *
375 */
376static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
377{
378 struct smsc_ircc_cb *self;
379 struct net_device *dev;
380 int err;
527b6af4 381
1da177e4
LT		 382 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
383
384 err = smsc_ircc_present(fir_base, sir_base);
98b77773 385 if (err)
1da177e4 386 goto err_out;
527b6af4 387
1da177e4 388 err = -ENOMEM;
a956f4ca 389 if (dev_count >= ARRAY_SIZE(dev_self)) {
1da177e4
LT		 390 IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__);
391 goto err_out1;
392 }
393
394 /*
395 * Allocate new instance of the driver
396 */
397 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
398 if (!dev) {
399 IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__);
400 goto err_out1;
401 }
402
403 SET_MODULE_OWNER(dev);
404
405 dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
406#if SMSC_IRCC2_C_NET_TIMEOUT
407 dev->tx_timeout = smsc_ircc_timeout;
98b77773 408 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
1da177e4
LT		 409#endif
410 dev->open = smsc_ircc_net_open;
411 dev->stop = smsc_ircc_net_close;
412 dev->do_ioctl = smsc_ircc_net_ioctl;
413 dev->get_stats = smsc_ircc_net_get_stats;
527b6af4 414
1da177e4
LT		 415 self = dev->priv;
416 self->netdev = dev;
417
418 /* Make ifconfig display some details */
419 dev->base_addr = self->io.fir_base = fir_base;
420 dev->irq = self->io.irq = irq;
421
422 /* Need to store self somewhere */
423 dev_self[dev_count++] = self;
424 spin_lock_init(&self->lock);
425
527b6af4 426 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
1da177e4
LT		 427 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
428
429 self->rx_buff.head =
430 dma_alloc_coherent(NULL, self->rx_buff.truesize,
431 &self->rx_buff_dma, GFP_KERNEL);
432 if (self->rx_buff.head == NULL) {
433 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
434 driver_name);
435 goto err_out2;
436 }
437
438 self->tx_buff.head =
439 dma_alloc_coherent(NULL, self->tx_buff.truesize,
440 &self->tx_buff_dma, GFP_KERNEL);
441 if (self->tx_buff.head == NULL) {
442 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
443 driver_name);
444 goto err_out3;
445 }
446
447 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
448 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
449
450 self->rx_buff.in_frame = FALSE;
451 self->rx_buff.state = OUTSIDE_FRAME;
452 self->tx_buff.data = self->tx_buff.head;
453 self->rx_buff.data = self->rx_buff.head;
527b6af4 454
1da177e4 455 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
1da177e4 456 smsc_ircc_setup_qos(self);
1da177e4 457 smsc_ircc_init_chip(self);
527b6af4 458
98b77773
DT		 459 if (ircc_transceiver > 0 &&
460 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
1da177e4
LT		 461 self->transceiver = ircc_transceiver;
462 else
463 smsc_ircc_probe_transceiver(self);
464
465 err = register_netdev(self->netdev);
98b77773 466 if (err) {
1da177e4
LT		 467 IRDA_ERROR("%s, Network device registration failed!\n",
468 driver_name);
469 goto err_out4;
470 }
471
472 self->pmdev = pm_register(PM_SYS_DEV, PM_SYS_IRDA, smsc_ircc_pmproc);
473 if (self->pmdev)
474 self->pmdev->data = self;
475
476 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
477
478 return 0;
98b77773 479
1da177e4
LT		 480 err_out4:
481 dma_free_coherent(NULL, self->tx_buff.truesize,
482 self->tx_buff.head, self->tx_buff_dma);
483 err_out3:
484 dma_free_coherent(NULL, self->rx_buff.truesize,
485 self->rx_buff.head, self->rx_buff_dma);
486 err_out2:
487 free_netdev(self->netdev);
488 dev_self[--dev_count] = NULL;
489 err_out1:
490 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
491 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
492 err_out:
493 return err;
494}
495
496/*
497 * Function smsc_ircc_present(fir_base, sir_base)
498 *
499 * Check the smsc-ircc chip presence
500 *
501 */
502static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
503{
504 unsigned char low, high, chip, config, dma, irq, version;
505
506 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
507 driver_name)) {
508 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
509 __FUNCTION__, fir_base);
510 goto out1;
511 }
512
513 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
514 driver_name)) {
515 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
516 __FUNCTION__, sir_base);
517 goto out2;
518 }
519
520 register_bank(fir_base, 3);
521
98b77773
DT		 522 high = inb(fir_base + IRCC_ID_HIGH);
523 low = inb(fir_base + IRCC_ID_LOW);
524 chip = inb(fir_base + IRCC_CHIP_ID);
525 version = inb(fir_base + IRCC_VERSION);
526 config = inb(fir_base + IRCC_INTERFACE);
1da177e4
LT		 527 dma = config & IRCC_INTERFACE_DMA_MASK;
528 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
529
527b6af4 530 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
98b77773 531 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
1da177e4
LT		 532 __FUNCTION__, fir_base);
533 goto out3;
534 }
535 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
536 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
537 chip & 0x0f, version, fir_base, sir_base, dma, irq);
538
539 return 0;
98b77773 540
1da177e4
LT		 541 out3:
542 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
543 out2:
544 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
545 out1:
546 return -ENODEV;
547}
548
549/*
550 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
551 *
552 * Setup I/O
553 *
554 */
527b6af4
DT		 555static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
556 unsigned int fir_base, unsigned int sir_base,
1da177e4
LT		 557 u8 dma, u8 irq)
558{
559 unsigned char config, chip_dma, chip_irq;
560
561 register_bank(fir_base, 3);
98b77773
DT		 562 config = inb(fir_base + IRCC_INTERFACE);
563 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
564 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
1da177e4
LT		 565
566 self->io.fir_base = fir_base;
567 self->io.sir_base = sir_base;
568 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
569 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
570 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
571 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
572
573 if (irq < 255) {
574 if (irq != chip_irq)
575 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
576 driver_name, chip_irq, irq);
577 self->io.irq = irq;
98b77773 578 } else
1da177e4 579 self->io.irq = chip_irq;
527b6af4 580
1da177e4
LT		 581 if (dma < 255) {
582 if (dma != chip_dma)
583 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
584 driver_name, chip_dma, dma);
585 self->io.dma = dma;
98b77773 586 } else
1da177e4
LT		 587 self->io.dma = chip_dma;
588
589}
590
591/*
592 * Function smsc_ircc_setup_qos(self)
593 *
594 * Setup qos
595 *
596 */
597static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
598{
599 /* Initialize QoS for this device */
600 irda_init_max_qos_capabilies(&self->qos);
527b6af4 601
1da177e4
LT		 602 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
603 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
604
605 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
606 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
607 irda_qos_bits_to_value(&self->qos);
608}
609
610/*
611 * Function smsc_ircc_init_chip(self)
612 *
613 * Init chip
614 *
615 */
616static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
617{
527b6af4
DT		 618 int iobase, ir_mode, ctrl, fast;
619
98b77773 620 IRDA_ASSERT(self != NULL, return;);
1da177e4 621
98b77773 622 iobase = self->io.fir_base;
1da177e4
LT		 623 ir_mode = IRCC_CFGA_IRDA_SIR_A;
624 ctrl = 0;
625 fast = 0;
626
627 register_bank(iobase, 0);
98b77773
DT		 628 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
629 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 630
631 register_bank(iobase, 1);
98b77773
DT		 632 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | ir_mode),
633 iobase + IRCC_SCE_CFGA);
1da177e4
LT		 634
635#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 636 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
637 iobase + IRCC_SCE_CFGB);
527b6af4 638#else
98b77773
DT		 639 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
640 iobase + IRCC_SCE_CFGB);
527b6af4 641#endif
98b77773
DT		 642 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
643 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
527b6af4 644
1da177e4 645 register_bank(iobase, 4);
98b77773 646 outb((inb(iobase + IRCC_CONTROL) & 0x30) | ctrl, iobase + IRCC_CONTROL);
527b6af4 647
1da177e4 648 register_bank(iobase, 0);
98b77773 649 outb(fast, iobase + IRCC_LCR_A);
1da177e4
LT		 650
651 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
527b6af4 652
1da177e4 653 /* Power on device */
98b77773 654 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 655}
656
657/*
658 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
659 *
660 * Process IOCTL commands for this device
661 *
662 */
663static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
664{
665 struct if_irda_req *irq = (struct if_irda_req *) rq;
666 struct smsc_ircc_cb *self;
667 unsigned long flags;
668 int ret = 0;
669
670 IRDA_ASSERT(dev != NULL, return -1;);
671
672 self = dev->priv;
673
674 IRDA_ASSERT(self != NULL, return -1;);
675
676 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
527b6af4 677
1da177e4
LT		 678 switch (cmd) {
679 case SIOCSBANDWIDTH: /* Set bandwidth */
680 if (!capable(CAP_NET_ADMIN))
681 ret = -EPERM;
682 else {
683 /* Make sure we are the only one touching
684 * self->io.speed and the hardware - Jean II */
685 spin_lock_irqsave(&self->lock, flags);
686 smsc_ircc_change_speed(self, irq->ifr_baudrate);
687 spin_unlock_irqrestore(&self->lock, flags);
688 }
689 break;
690 case SIOCSMEDIABUSY: /* Set media busy */
691 if (!capable(CAP_NET_ADMIN)) {
692 ret = -EPERM;
693 break;
694 }
695
696 irda_device_set_media_busy(self->netdev, TRUE);
697 break;
698 case SIOCGRECEIVING: /* Check if we are receiving right now */
699 irq->ifr_receiving = smsc_ircc_is_receiving(self);
700 break;
701 #if 0
702 case SIOCSDTRRTS:
703 if (!capable(CAP_NET_ADMIN)) {
704 ret = -EPERM;
705 break;
706 }
707 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
708 break;
709 #endif
710 default:
711 ret = -EOPNOTSUPP;
712 }
527b6af4 713
1da177e4
LT		 714 return ret;
715}
716
717static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
718{
719 struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) dev->priv;
527b6af4 720
1da177e4
LT		 721 return &self->stats;
722}
723
724#if SMSC_IRCC2_C_NET_TIMEOUT
725/*
726 * Function smsc_ircc_timeout (struct net_device *dev)
727 *
728 * The networking timeout management.
729 *
730 */
731
732static void smsc_ircc_timeout(struct net_device *dev)
733{
734 struct smsc_ircc_cb *self;
735 unsigned long flags;
736
737 self = (struct smsc_ircc_cb *) dev->priv;
527b6af4 738
1da177e4
LT		 739 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
740 dev->name, self->io.speed);
741 spin_lock_irqsave(&self->lock, flags);
742 smsc_ircc_sir_start(self);
743 smsc_ircc_change_speed(self, self->io.speed);
744 dev->trans_start = jiffies;
745 netif_wake_queue(dev);
746 spin_unlock_irqrestore(&self->lock, flags);
747}
748#endif
749
750/*
751 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
752 *
753 * Transmits the current frame until FIFO is full, then
754 * waits until the next transmit interrupt, and continues until the
755 * frame is transmitted.
756 */
757int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
758{
759 struct smsc_ircc_cb *self;
760 unsigned long flags;
761 int iobase;
762 s32 speed;
763
764 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
765
766 IRDA_ASSERT(dev != NULL, return 0;);
527b6af4 767
1da177e4
LT		 768 self = (struct smsc_ircc_cb *) dev->priv;
769 IRDA_ASSERT(self != NULL, return 0;);
770
771 iobase = self->io.sir_base;
772
773 netif_stop_queue(dev);
527b6af4 774
1da177e4
LT		 775 /* Make sure test of self->io.speed & speed change are atomic */
776 spin_lock_irqsave(&self->lock, flags);
777
778 /* Check if we need to change the speed */
779 speed = irda_get_next_speed(skb);
98b77773 780 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 781 /* Check for empty frame */
782 if (!skb->len) {
783 /*
784 * We send frames one by one in SIR mode (no
785 * pipelining), so at this point, if we were sending
786 * a previous frame, we just received the interrupt
787 * telling us it is finished (UART_IIR_THRI).
788 * Therefore, waiting for the transmitter to really
789 * finish draining the fifo won't take too long.
790 * And the interrupt handler is not expected to run.
791 * - Jean II */
792 smsc_ircc_sir_wait_hw_transmitter_finish(self);
793 smsc_ircc_change_speed(self, speed);
794 spin_unlock_irqrestore(&self->lock, flags);
795 dev_kfree_skb(skb);
796 return 0;
1da177e4 797 }
98b77773 798 self->new_speed = speed;
1da177e4
LT		 799 }
800
801 /* Init tx buffer */
802 self->tx_buff.data = self->tx_buff.head;
803
804 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
527b6af4 805 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
1da177e4 806 self->tx_buff.truesize);
527b6af4 807
1da177e4
LT		 808 self->stats.tx_bytes += self->tx_buff.len;
809
810 /* Turn on transmit finished interrupt. Will fire immediately! */
98b77773 811 outb(UART_IER_THRI, iobase + UART_IER);
1da177e4
LT		 812
813 spin_unlock_irqrestore(&self->lock, flags);
814
815 dev_kfree_skb(skb);
527b6af4 816
1da177e4
LT		 817 return 0;
818}
819
820/*
821 * Function smsc_ircc_set_fir_speed (self, baud)
822 *
823 * Change the speed of the device
824 *
825 */
826static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
827{
828 int fir_base, ir_mode, ctrl, fast;
829
830 IRDA_ASSERT(self != NULL, return;);
831 fir_base = self->io.fir_base;
832
833 self->io.speed = speed;
834
98b77773 835 switch (speed) {
1da177e4 836 default:
527b6af4 837 case 576000:
1da177e4
LT		 838 ir_mode = IRCC_CFGA_IRDA_HDLC;
839 ctrl = IRCC_CRC;
840 fast = 0;
841 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
842 break;
843 case 1152000:
844 ir_mode = IRCC_CFGA_IRDA_HDLC;
845 ctrl = IRCC_1152 | IRCC_CRC;
846 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
847 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
848 __FUNCTION__);
849 break;
850 case 4000000:
851 ir_mode = IRCC_CFGA_IRDA_4PPM;
852 ctrl = IRCC_CRC;
853 fast = IRCC_LCR_A_FAST;
854 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
855 __FUNCTION__);
856 break;
857 }
858 #if 0
859 Now in tranceiver!
860 /* This causes an interrupt */
861 register_bank(fir_base, 0);
98b77773 862 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
1da177e4 863 #endif
527b6af4 864
1da177e4 865 register_bank(fir_base, 1);
98b77773 866 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
527b6af4 867
1da177e4 868 register_bank(fir_base, 4);
98b77773 869 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
1da177e4
LT		 870}
871
872/*
873 * Function smsc_ircc_fir_start(self)
874 *
875 * Change the speed of the device
876 *
877 */
878static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
879{
880 struct net_device *dev;
881 int fir_base;
882
883 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
884
885 IRDA_ASSERT(self != NULL, return;);
886 dev = self->netdev;
887 IRDA_ASSERT(dev != NULL, return;);
888
889 fir_base = self->io.fir_base;
890
891 /* Reset everything */
892
893 /* Install FIR transmit handler */
527b6af4 894 dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
1da177e4
LT		 895
896 /* Clear FIFO */
98b77773 897 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1da177e4
LT		 898
899 /* Enable interrupt */
98b77773 900 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1da177e4
LT		 901
902 register_bank(fir_base, 1);
903
527b6af4 904 /* Select the TX/RX interface */
1da177e4 905#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 906 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
907 fir_base + IRCC_SCE_CFGB);
527b6af4 908#else
98b77773
DT		 909 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
910 fir_base + IRCC_SCE_CFGB);
527b6af4 911#endif
98b77773 912 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1da177e4
LT		 913
914 /* Enable SCE interrupts */
98b77773 915 outb(0, fir_base + IRCC_MASTER);
1da177e4 916 register_bank(fir_base, 0);
98b77773
DT		 917 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
918 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1da177e4
LT		 919}
920
921/*
922 * Function smsc_ircc_fir_stop(self, baud)
923 *
924 * Change the speed of the device
925 *
926 */
927static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
928{
929 int fir_base;
930
931 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 932
1da177e4
LT		 933 IRDA_ASSERT(self != NULL, return;);
934
935 fir_base = self->io.fir_base;
936 register_bank(fir_base, 0);
98b77773
DT		 937 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
938 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1da177e4
LT		 939}
940
941
942/*
943 * Function smsc_ircc_change_speed(self, baud)
944 *
945 * Change the speed of the device
946 *
947 * This function *must* be called with spinlock held, because it may
948 * be called from the irq handler. - Jean II
949 */
950static void smsc_ircc_change_speed(void *priv, u32 speed)
951{
952 struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) priv;
953 struct net_device *dev;
954 int iobase;
955 int last_speed_was_sir;
527b6af4 956
1da177e4
LT		 957 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed);
958
959 IRDA_ASSERT(self != NULL, return;);
960 dev = self->netdev;
961 iobase = self->io.fir_base;
962
963 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
964
965 #if 0
966 /* Temp Hack */
967 speed= 1152000;
968 self->io.speed = speed;
969 last_speed_was_sir = 0;
527b6af4 970 smsc_ircc_fir_start(self);
1da177e4 971 #endif
527b6af4 972
98b77773 973 if (self->io.speed == 0)
1da177e4
LT		 974 smsc_ircc_sir_start(self);
975
976 #if 0
98b77773 977 if (!last_speed_was_sir) speed = self->io.speed;
1da177e4
LT		 978 #endif
979
98b77773
DT		 980 if (self->io.speed != speed)
981 smsc_ircc_set_transceiver_for_speed(self, speed);
1da177e4
LT		 982
983 self->io.speed = speed;
527b6af4 984
98b77773
DT		 985 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
986 if (!last_speed_was_sir) {
1da177e4
LT		 987 smsc_ircc_fir_stop(self);
988 smsc_ircc_sir_start(self);
989 }
527b6af4 990 smsc_ircc_set_sir_speed(self, speed);
98b77773
DT		 991 } else {
992 if (last_speed_was_sir) {
527b6af4 993 #if SMSC_IRCC2_C_SIR_STOP
1da177e4
LT		 994 smsc_ircc_sir_stop(self);
995 #endif
996 smsc_ircc_fir_start(self);
997 }
998 smsc_ircc_set_fir_speed(self, speed);
999
1000 #if 0
1001 self->tx_buff.len = 10;
1002 self->tx_buff.data = self->tx_buff.head;
527b6af4 1003
1da177e4
LT		 1004 smsc_ircc_dma_xmit(self, iobase, 4000);
1005 #endif
1006 /* Be ready for incoming frames */
1007 smsc_ircc_dma_receive(self, iobase);
1008 }
527b6af4 1009
1da177e4
LT		 1010 netif_wake_queue(dev);
1011}
1012
1013/*
1014 * Function smsc_ircc_set_sir_speed (self, speed)
1015 *
1016 * Set speed of IrDA port to specified baudrate
1017 *
1018 */
1019void smsc_ircc_set_sir_speed(void *priv, __u32 speed)
1020{
1021 struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) priv;
527b6af4 1022 int iobase;
1da177e4
LT		 1023 int fcr; /* FIFO control reg */
1024 int lcr; /* Line control reg */
1025 int divisor;
1026
1027 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed);
1028
1029 IRDA_ASSERT(self != NULL, return;);
1030 iobase = self->io.sir_base;
527b6af4 1031
1da177e4
LT		 1032 /* Update accounting for new speed */
1033 self->io.speed = speed;
1034
1035 /* Turn off interrupts */
98b77773 1036 outb(0, iobase + UART_IER);
1da177e4 1037
98b77773 1038 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
527b6af4 1039
1da177e4
LT		 1040 fcr = UART_FCR_ENABLE_FIFO;
1041
527b6af4 1042 /*
1da177e4
LT		 1043 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1044 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
527b6af4 1045 * about this timeout since it will always be fast enough.
1da177e4 1046 */
98b77773
DT		 1047 fcr |= self->io.speed < 38400 ?
1048 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
527b6af4 1049
1da177e4
LT		 1050 /* IrDA ports use 8N1 */
1051 lcr = UART_LCR_WLEN8;
527b6af4 1052
98b77773
DT		 1053 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1054 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1055 outb(divisor >> 8, iobase + UART_DLM);
1056 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1057 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1da177e4
LT		 1058
1059 /* Turn on interrups */
98b77773 1060 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1da177e4
LT		 1061
1062 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed);
1063}
1064
1065
1066/*
1067 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1068 *
1069 * Transmit the frame!
1070 *
1071 */
1072static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1073{
1074 struct smsc_ircc_cb *self;
1075 unsigned long flags;
1076 s32 speed;
1077 int iobase;
1078 int mtt;
1079
1080 IRDA_ASSERT(dev != NULL, return 0;);
1081 self = (struct smsc_ircc_cb *) dev->priv;
1082 IRDA_ASSERT(self != NULL, return 0;);
1083
1084 iobase = self->io.fir_base;
1085
1086 netif_stop_queue(dev);
1087
1088 /* Make sure test of self->io.speed & speed change are atomic */
1089 spin_lock_irqsave(&self->lock, flags);
1090
1091 /* Check if we need to change the speed after this frame */
1092 speed = irda_get_next_speed(skb);
98b77773 1093 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 1094 /* Check for empty frame */
1095 if (!skb->len) {
1096 /* Note : you should make sure that speed changes
1097 * are not going to corrupt any outgoing frame.
1098 * Look at nsc-ircc for the gory details - Jean II */
527b6af4 1099 smsc_ircc_change_speed(self, speed);
1da177e4
LT		 1100 spin_unlock_irqrestore(&self->lock, flags);
1101 dev_kfree_skb(skb);
1102 return 0;
98b77773
DT		 1103 }
1104
1105 self->new_speed = speed;
1da177e4 1106 }
527b6af4 1107
1da177e4
LT		 1108 memcpy(self->tx_buff.head, skb->data, skb->len);
1109
1110 self->tx_buff.len = skb->len;
1111 self->tx_buff.data = self->tx_buff.head;
527b6af4
DT		 1112
1113 mtt = irda_get_mtt(skb);
1da177e4
LT		 1114 if (mtt) {
1115 int bofs;
1116
527b6af4 1117 /*
1da177e4
LT		 1118 * Compute how many BOFs (STA or PA's) we need to waste the
1119 * min turn time given the speed of the link.
1120 */
1121 bofs = mtt * (self->io.speed / 1000) / 8000;
1122 if (bofs > 4095)
1123 bofs = 4095;
1124
1125 smsc_ircc_dma_xmit(self, iobase, bofs);
1126 } else {
1127 /* Transmit frame */
1128 smsc_ircc_dma_xmit(self, iobase, 0);
1129 }
98b77773 1130
1da177e4
LT		 1131 spin_unlock_irqrestore(&self->lock, flags);
1132 dev_kfree_skb(skb);
1133
1134 return 0;
1135}
1136
1137/*
1138 * Function smsc_ircc_dma_xmit (self, iobase)
1139 *
1140 * Transmit data using DMA
1141 *
1142 */
1143static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int iobase, int bofs)
1144{
1145 u8 ctrl;
1146
1147 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1148#if 1
1149 /* Disable Rx */
1150 register_bank(iobase, 0);
98b77773 1151 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1152#endif
1153 register_bank(iobase, 1);
98b77773
DT		 1154 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1155 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1156
1157 self->io.direction = IO_XMIT;
1158
1159 /* Set BOF additional count for generating the min turn time */
1160 register_bank(iobase, 4);
98b77773
DT		 1161 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1162 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1163 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1da177e4
LT		 1164
1165 /* Set max Tx frame size */
98b77773
DT		 1166 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1167 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1da177e4
LT		 1168
1169 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
527b6af4 1170
1da177e4
LT		 1171 /* Enable burst mode chip Tx DMA */
1172 register_bank(iobase, 1);
98b77773
DT		 1173 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1174 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1175
1176 /* Setup DMA controller (must be done after enabling chip DMA) */
1177 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1178 DMA_TX_MODE);
1179
1180 /* Enable interrupt */
1181
1182 register_bank(iobase, 0);
98b77773
DT		 1183 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1184 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
527b6af4 1185
1da177e4 1186 /* Enable transmit */
98b77773 1187 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1da177e4
LT		 1188}
1189
1190/*
1191 * Function smsc_ircc_dma_xmit_complete (self)
1192 *
527b6af4 1193 * The transfer of a frame in finished. This function will only be called
1da177e4
LT		 1194 * by the interrupt handler
1195 *
1196 */
1197static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self, int iobase)
1198{
1199 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1200#if 0
1201 /* Disable Tx */
1202 register_bank(iobase, 0);
98b77773 1203 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1204#endif
1205 register_bank(self->io.fir_base, 1);
98b77773
DT		 1206 outb(inb(self->io.fir_base + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1207 self->io.fir_base + IRCC_SCE_CFGB);
1da177e4
LT		 1208
1209 /* Check for underrun! */
1210 register_bank(iobase, 0);
98b77773 1211 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1da177e4
LT		 1212 self->stats.tx_errors++;
1213 self->stats.tx_fifo_errors++;
1214
1215 /* Reset error condition */
1216 register_bank(iobase, 0);
98b77773
DT		 1217 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1218 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 1219 } else {
1220 self->stats.tx_packets++;
98b77773 1221 self->stats.tx_bytes += self->tx_buff.len;
1da177e4
LT		 1222 }
1223
1224 /* Check if it's time to change the speed */
1225 if (self->new_speed) {
527b6af4 1226 smsc_ircc_change_speed(self, self->new_speed);
1da177e4
LT		 1227 self->new_speed = 0;
1228 }
1229
1230 netif_wake_queue(self->netdev);
1231}
1232
1233/*
1234 * Function smsc_ircc_dma_receive(self)
1235 *
1236 * Get ready for receiving a frame. The device will initiate a DMA
1237 * if it starts to receive a frame.
1238 *
1239 */
527b6af4 1240static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self, int iobase)
1da177e4
LT		 1241{
1242#if 0
1243 /* Turn off chip DMA */
1244 register_bank(iobase, 1);
98b77773
DT		 1245 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1246 iobase + IRCC_SCE_CFGB);
1da177e4 1247#endif
527b6af4 1248
1da177e4
LT		 1249 /* Disable Tx */
1250 register_bank(iobase, 0);
98b77773 1251 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1252
1253 /* Turn off chip DMA */
1254 register_bank(iobase, 1);
98b77773
DT		 1255 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1256 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1257
1258 self->io.direction = IO_RECV;
1259 self->rx_buff.data = self->rx_buff.head;
1260
1261 /* Set max Rx frame size */
1262 register_bank(iobase, 4);
98b77773
DT		 1263 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1264 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1da177e4
LT		 1265
1266 /* Setup DMA controller */
1267 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1268 DMA_RX_MODE);
1269
1270 /* Enable burst mode chip Rx DMA */
1271 register_bank(iobase, 1);
98b77773
DT		 1272 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1273 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1274
1275 /* Enable interrupt */
1276 register_bank(iobase, 0);
98b77773
DT		 1277 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1278 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1da177e4
LT		 1279
1280 /* Enable receiver */
1281 register_bank(iobase, 0);
527b6af4 1282 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
98b77773 1283 iobase + IRCC_LCR_B);
527b6af4 1284
1da177e4
LT		 1285 return 0;
1286}
1287
1288/*
1289 * Function smsc_ircc_dma_receive_complete(self, iobase)
1290 *
1291 * Finished with receiving frames
1292 *
1293 */
1294static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self, int iobase)
1295{
1296 struct sk_buff *skb;
1297 int len, msgcnt, lsr;
527b6af4 1298
1da177e4 1299 register_bank(iobase, 0);
527b6af4 1300
1da177e4
LT		 1301 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1302#if 0
1303 /* Disable Rx */
1304 register_bank(iobase, 0);
98b77773 1305 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1306#endif
1307 register_bank(iobase, 0);
98b77773
DT		 1308 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1309 lsr= inb(iobase + IRCC_LSR);
1310 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1da177e4
LT		 1311
1312 IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__,
1313 get_dma_residue(self->io.dma));
1314
1315 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1316
98b77773
DT		 1317 /* Look for errors */
1318 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1da177e4 1319 self->stats.rx_errors++;
98b77773
DT		 1320 if (lsr & IRCC_LSR_FRAME_ERROR)
1321 self->stats.rx_frame_errors++;
1322 if (lsr & IRCC_LSR_CRC_ERROR)
1323 self->stats.rx_crc_errors++;
1324 if (lsr & IRCC_LSR_SIZE_ERROR)
1325 self->stats.rx_length_errors++;
1326 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1327 self->stats.rx_length_errors++;
1da177e4
LT		 1328 return;
1329 }
98b77773 1330
1da177e4 1331 /* Remove CRC */
98b77773 1332 len -= self->io.speed < 4000000 ? 2 : 4;
1da177e4 1333
98b77773 1334 if (len < 2 || len > 2050) {
1da177e4
LT		 1335 IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
1336 return;
1337 }
1338 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
1339
98b77773
DT		 1340 skb = dev_alloc_skb(len + 1);
1341 if (!skb) {
1da177e4
LT		 1342 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1343 __FUNCTION__);
1344 return;
527b6af4 1345 }
1da177e4 1346 /* Make sure IP header gets aligned */
527b6af4 1347 skb_reserve(skb, 1);
1da177e4
LT		 1348
1349 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1350 self->stats.rx_packets++;
1351 self->stats.rx_bytes += len;
1352
1353 skb->dev = self->netdev;
1354 skb->mac.raw = skb->data;
1355 skb->protocol = htons(ETH_P_IRDA);
1356 netif_rx(skb);
1357}
1358
1359/*
1360 * Function smsc_ircc_sir_receive (self)
1361 *
1362 * Receive one frame from the infrared port
1363 *
1364 */
527b6af4 1365static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1da177e4
LT		 1366{
1367 int boguscount = 0;
1368 int iobase;
1369
1370 IRDA_ASSERT(self != NULL, return;);
1371
1372 iobase = self->io.sir_base;
1373
527b6af4
DT		 1374 /*
1375 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1376 * async_unwrap_char will deliver all found frames
1da177e4
LT		 1377 */
1378 do {
527b6af4 1379 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
98b77773 1380 inb(iobase + UART_RX));
1da177e4
LT		 1381
1382 /* Make sure we don't stay here to long */
1383 if (boguscount++ > 32) {
1384 IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__);
1385 break;
1386 }
98b77773 1387 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1da177e4
LT		 1388}
1389
1390
1391/*
1392 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1393 *
1394 * An interrupt from the chip has arrived. Time to do some work
1395 *
1396 */
1397static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1398{
1399 struct net_device *dev = (struct net_device *) dev_id;
1400 struct smsc_ircc_cb *self;
1401 int iobase, iir, lcra, lsr;
1402 irqreturn_t ret = IRQ_NONE;
1403
1404 if (dev == NULL) {
527b6af4 1405 printk(KERN_WARNING "%s: irq %d for unknown device.\n",
1da177e4
LT		 1406 driver_name, irq);
1407 goto irq_ret;
1408 }
1409 self = (struct smsc_ircc_cb *) dev->priv;
1410 IRDA_ASSERT(self != NULL, return IRQ_NONE;);
1411
1412 /* Serialise the interrupt handler in various CPUs, stop Tx path */
527b6af4 1413 spin_lock(&self->lock);
1da177e4
LT		 1414
1415 /* Check if we should use the SIR interrupt handler */
98b77773 1416 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1da177e4
LT		 1417 ret = smsc_ircc_interrupt_sir(dev);
1418 goto irq_ret_unlock;
1419 }
1420
1421 iobase = self->io.fir_base;
1422
1423 register_bank(iobase, 0);
98b77773 1424 iir = inb(iobase + IRCC_IIR);
527b6af4 1425 if (iir == 0)
1da177e4
LT		 1426 goto irq_ret_unlock;
1427 ret = IRQ_HANDLED;
1428
1429 /* Disable interrupts */
98b77773
DT		 1430 outb(0, iobase + IRCC_IER);
1431 lcra = inb(iobase + IRCC_LCR_A);
1432 lsr = inb(iobase + IRCC_LSR);
527b6af4 1433
1da177e4
LT		 1434 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1435
1436 if (iir & IRCC_IIR_EOM) {
1437 if (self->io.direction == IO_RECV)
1438 smsc_ircc_dma_receive_complete(self, iobase);
1439 else
1440 smsc_ircc_dma_xmit_complete(self, iobase);
527b6af4 1441
1da177e4
LT		 1442 smsc_ircc_dma_receive(self, iobase);
1443 }
1444
1445 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1446 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/
1447 }
1448
1449 /* Enable interrupts again */
1450
1451 register_bank(iobase, 0);
98b77773 1452 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1da177e4
LT		 1453
1454 irq_ret_unlock:
1455 spin_unlock(&self->lock);
1456 irq_ret:
1457 return ret;
1458}
1459
1460/*
1461 * Function irport_interrupt_sir (irq, dev_id, regs)
1462 *
1463 * Interrupt handler for SIR modes
1464 */
1465static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1466{
1467 struct smsc_ircc_cb *self = dev->priv;
1468 int boguscount = 0;
1469 int iobase;
1470 int iir, lsr;
1471
1472 /* Already locked comming here in smsc_ircc_interrupt() */
1473 /*spin_lock(&self->lock);*/
1474
1475 iobase = self->io.sir_base;
1476
98b77773 1477 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1478 if (iir == 0)
1479 return IRQ_NONE;
1480 while (iir) {
1481 /* Clear interrupt */
98b77773 1482 lsr = inb(iobase + UART_LSR);
1da177e4 1483
527b6af4 1484 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1da177e4
LT		 1485 __FUNCTION__, iir, lsr, iobase);
1486
1487 switch (iir) {
1488 case UART_IIR_RLSI:
1489 IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__);
1490 break;
1491 case UART_IIR_RDI:
1492 /* Receive interrupt */
1493 smsc_ircc_sir_receive(self);
1494 break;
1495 case UART_IIR_THRI:
1496 if (lsr & UART_LSR_THRE)
1497 /* Transmitter ready for data */
1498 smsc_ircc_sir_write_wakeup(self);
1499 break;
1500 default:
1501 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1502 __FUNCTION__, iir);
1503 break;
527b6af4
DT		 1504 }
1505
1da177e4
LT		 1506 /* Make sure we don't stay here to long */
1507 if (boguscount++ > 100)
1508 break;
1509
527b6af4 1510 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1511 }
1512 /*spin_unlock(&self->lock);*/
1513 return IRQ_HANDLED;
1514}
1515
1516
1517#if 0 /* unused */
1518/*
1519 * Function ircc_is_receiving (self)
1520 *
1521 * Return TRUE is we are currently receiving a frame
1522 *
1523 */
1524static int ircc_is_receiving(struct smsc_ircc_cb *self)
1525{
1526 int status = FALSE;
1527 /* int iobase; */
1528
1529 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1530
1531 IRDA_ASSERT(self != NULL, return FALSE;);
1532
1533 IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__,
1534 get_dma_residue(self->io.dma));
1535
1536 status = (self->rx_buff.state != OUTSIDE_FRAME);
527b6af4 1537
1da177e4
LT		 1538 return status;
1539}
1540#endif /* unused */
1541
1542
1543/*
1544 * Function smsc_ircc_net_open (dev)
1545 *
1546 * Start the device
1547 *
1548 */
1549static int smsc_ircc_net_open(struct net_device *dev)
1550{
1551 struct smsc_ircc_cb *self;
1552 int iobase;
1553 char hwname[16];
1554 unsigned long flags;
1555
1556 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 1557
1da177e4
LT		 1558 IRDA_ASSERT(dev != NULL, return -1;);
1559 self = (struct smsc_ircc_cb *) dev->priv;
1560 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1561
1da177e4
LT		 1562 iobase = self->io.fir_base;
1563
527b6af4 1564 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1da177e4
LT		 1565 (void *) dev)) {
1566 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1567 __FUNCTION__, self->io.irq);
1568 return -EAGAIN;
1569 }
1570
1571 spin_lock_irqsave(&self->lock, flags);
1572 /*smsc_ircc_sir_start(self);*/
1573 self->io.speed = 0;
1574 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1575 spin_unlock_irqrestore(&self->lock, flags);
527b6af4 1576
1da177e4
LT		 1577 /* Give self a hardware name */
1578 /* It would be cool to offer the chip revision here - Jean II */
1579 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1580
527b6af4 1581 /*
1da177e4 1582 * Open new IrLAP layer instance, now that everything should be
527b6af4 1583 * initialized properly
1da177e4
LT		 1584 */
1585 self->irlap = irlap_open(dev, &self->qos, hwname);
1586
1587 /*
1588 * Always allocate the DMA channel after the IRQ,
1589 * and clean up on failure.
1590 */
1591 if (request_dma(self->io.dma, dev->name)) {
1592 smsc_ircc_net_close(dev);
1593
1594 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1595 __FUNCTION__, self->io.dma);
1596 return -EAGAIN;
1597 }
527b6af4 1598
1da177e4
LT		 1599 netif_start_queue(dev);
1600
1601 return 0;
1602}
1603
1604/*
1605 * Function smsc_ircc_net_close (dev)
1606 *
1607 * Stop the device
1608 *
1609 */
1610static int smsc_ircc_net_close(struct net_device *dev)
1611{
1612 struct smsc_ircc_cb *self;
1613 int iobase;
1614
1615 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 1616
1da177e4 1617 IRDA_ASSERT(dev != NULL, return -1;);
527b6af4 1618 self = (struct smsc_ircc_cb *) dev->priv;
1da177e4 1619 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1620
1da177e4
LT		 1621 iobase = self->io.fir_base;
1622
1623 /* Stop device */
1624 netif_stop_queue(dev);
527b6af4 1625
1da177e4
LT		 1626 /* Stop and remove instance of IrLAP */
1627 if (self->irlap)
1628 irlap_close(self->irlap);
1629 self->irlap = NULL;
1630
1631 free_irq(self->io.irq, dev);
1da177e4 1632 disable_dma(self->io.dma);
1da177e4
LT		 1633 free_dma(self->io.dma);
1634
1635 return 0;
1636}
1637
1638
1639static void smsc_ircc_suspend(struct smsc_ircc_cb *self)
1640{
1641 IRDA_MESSAGE("%s, Suspending\n", driver_name);
1642
98b77773
DT		 1643 if (!self->io.suspended) {
1644 smsc_ircc_net_close(self->netdev);
1645 self->io.suspended = 1;
1646 }
1da177e4
LT		 1647}
1648
1649static void smsc_ircc_wakeup(struct smsc_ircc_cb *self)
1650{
1651 if (!self->io.suspended)
1652 return;
1653
1654 /* The code was doing a "cli()" here, but this can't be right.
1655 * If you need protection, do it in net_open with a spinlock
1656 * or give a good reason. - Jean II */
1657
1658 smsc_ircc_net_open(self->netdev);
527b6af4 1659
1da177e4
LT		 1660 IRDA_MESSAGE("%s, Waking up\n", driver_name);
1661}
1662
1663static int smsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data)
1664{
1665 struct smsc_ircc_cb *self = (struct smsc_ircc_cb*) dev->data;
1666 if (self) {
1667 switch (rqst) {
1668 case PM_SUSPEND:
1669 smsc_ircc_suspend(self);
1670 break;
1671 case PM_RESUME:
1672 smsc_ircc_wakeup(self);
1673 break;
1674 }
1675 }
1676 return 0;
1677}
1678
1679/*
1680 * Function smsc_ircc_close (self)
1681 *
1682 * Close driver instance
1683 *
1684 */
1685static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1686{
1687 int iobase;
1688 unsigned long flags;
1689
1690 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1691
1692 IRDA_ASSERT(self != NULL, return -1;);
1693
1694 iobase = self->io.fir_base;
1695
1696 if (self->pmdev)
1697 pm_unregister(self->pmdev);
1698
1699 /* Remove netdevice */
1700 unregister_netdev(self->netdev);
1701
1702 /* Make sure the irq handler is not exectuting */
1703 spin_lock_irqsave(&self->lock, flags);
1704
1705 /* Stop interrupts */
1706 register_bank(iobase, 0);
98b77773
DT		 1707 outb(0, iobase + IRCC_IER);
1708 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1709 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 1710#if 0
1711 /* Reset to SIR mode */
1712 register_bank(iobase, 1);
98b77773
DT		 1713 outb(IRCC_CFGA_IRDA_SIR_A|IRCC_CFGA_TX_POLARITY, iobase + IRCC_SCE_CFGA);
1714 outb(IRCC_CFGB_IR, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1715#endif
1716 spin_unlock_irqrestore(&self->lock, flags);
1717
1718 /* Release the PORTS that this driver is using */
1719 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1720 self->io.fir_base);
1721
1722 release_region(self->io.fir_base, self->io.fir_ext);
1723
527b6af4 1724 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1da177e4
LT		 1725 self->io.sir_base);
1726
1727 release_region(self->io.sir_base, self->io.sir_ext);
1728
1729 if (self->tx_buff.head)
1730 dma_free_coherent(NULL, self->tx_buff.truesize,
1731 self->tx_buff.head, self->tx_buff_dma);
527b6af4 1732
1da177e4
LT		 1733 if (self->rx_buff.head)
1734 dma_free_coherent(NULL, self->rx_buff.truesize,
1735 self->rx_buff.head, self->rx_buff_dma);
1736
1737 free_netdev(self->netdev);
1738
1739 return 0;
1740}
1741
1742static void __exit smsc_ircc_cleanup(void)
1743{
1744 int i;
1745
1746 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1747
98b77773 1748 for (i = 0; i < 2; i++) {
1da177e4
LT		 1749 if (dev_self[i])
1750 smsc_ircc_close(dev_self[i]);
1751 }
1752}
1753
1754/*
1755 * Start SIR operations
1756 *
1757 * This function *must* be called with spinlock held, because it may
1758 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1759 */
1760void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1761{
1762 struct net_device *dev;
1763 int fir_base, sir_base;
1764
1765 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1766
527b6af4 1767 IRDA_ASSERT(self != NULL, return;);
98b77773 1768 dev = self->netdev;
527b6af4 1769 IRDA_ASSERT(dev != NULL, return;);
1da177e4
LT		 1770 dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1771
1772 fir_base = self->io.fir_base;
1773 sir_base = self->io.sir_base;
1774
1775 /* Reset everything */
98b77773 1776 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1da177e4
LT		 1777
1778 #if SMSC_IRCC2_C_SIR_STOP
1779 /*smsc_ircc_sir_stop(self);*/
1780 #endif
1781
1782 register_bank(fir_base, 1);
98b77773 1783 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1da177e4
LT		 1784
1785 /* Initialize UART */
98b77773
DT		 1786 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1787 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
527b6af4 1788
1da177e4 1789 /* Turn on interrups */
98b77773 1790 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1da177e4
LT		 1791
1792 IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__);
1793
98b77773 1794 outb(0x00, fir_base + IRCC_MASTER);
1da177e4
LT		 1795}
1796
1797#if SMSC_IRCC2_C_SIR_STOP
1798void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1799{
1800 int iobase;
1801
1802 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1803 iobase = self->io.sir_base;
1804
1805 /* Reset UART */
98b77773 1806 outb(0, iobase + UART_MCR);
527b6af4 1807
1da177e4 1808 /* Turn off interrupts */
98b77773 1809 outb(0, iobase + UART_IER);
1da177e4
LT		 1810}
1811#endif
1812
1813/*
1814 * Function smsc_sir_write_wakeup (self)
1815 *
1816 * Called by the SIR interrupt handler when there's room for more data.
1817 * If we have more packets to send, we send them here.
1818 *
1819 */
1820static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1821{
1822 int actual = 0;
1823 int iobase;
1824 int fcr;
1825
1826 IRDA_ASSERT(self != NULL, return;);
1827
1828 IRDA_DEBUG(4, "%s\n", __FUNCTION__);
1829
1830 iobase = self->io.sir_base;
1831
1832 /* Finished with frame? */
1833 if (self->tx_buff.len > 0) {
1834 /* Write data left in transmit buffer */
527b6af4 1835 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1da177e4
LT		 1836 self->tx_buff.data, self->tx_buff.len);
1837 self->tx_buff.data += actual;
1838 self->tx_buff.len -= actual;
1839 } else {
527b6af4 1840
1da177e4 1841 /*if (self->tx_buff.len ==0) {*/
527b6af4
DT		 1842
1843 /*
1844 * Now serial buffer is almost free & we can start
1da177e4
LT		 1845 * transmission of another packet. But first we must check
1846 * if we need to change the speed of the hardware
1847 */
1848 if (self->new_speed) {
1849 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1850 __FUNCTION__, self->new_speed);
1851 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1852 smsc_ircc_change_speed(self, self->new_speed);
1853 self->new_speed = 0;
1854 } else {
1855 /* Tell network layer that we want more frames */
1856 netif_wake_queue(self->netdev);
1857 }
1858 self->stats.tx_packets++;
1859
98b77773
DT		 1860 if (self->io.speed <= 115200) {
1861 /*
1862 * Reset Rx FIFO to make sure that all reflected transmit data
1863 * is discarded. This is needed for half duplex operation
1864 */
1865 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
1866 fcr |= self->io.speed < 38400 ?
1867 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1da177e4 1868
98b77773 1869 outb(fcr, iobase + UART_FCR);
1da177e4 1870
98b77773
DT		 1871 /* Turn on receive interrupts */
1872 outb(UART_IER_RDI, iobase + UART_IER);
1da177e4
LT		 1873 }
1874 }
1875}
1876
1877/*
1878 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
1879 *
1880 * Fill Tx FIFO with transmit data
1881 *
1882 */
1883static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1884{
1885 int actual = 0;
527b6af4 1886
1da177e4 1887 /* Tx FIFO should be empty! */
98b77773 1888 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
1da177e4
LT		 1889 IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__);
1890 return 0;
1891 }
527b6af4 1892
1da177e4 1893 /* Fill FIFO with current frame */
98b77773 1894 while (fifo_size-- > 0 && actual < len) {
1da177e4 1895 /* Transmit next byte */
98b77773 1896 outb(buf[actual], iobase + UART_TX);
1da177e4
LT		 1897 actual++;
1898 }
1899 return actual;
1900}
1901
1902/*
1903 * Function smsc_ircc_is_receiving (self)
1904 *
1905 * Returns true is we are currently receiving data
1906 *
1907 */
1908static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
1909{
1910 return (self->rx_buff.state != OUTSIDE_FRAME);
1911}
1912
1913
1914/*
1915 * Function smsc_ircc_probe_transceiver(self)
1916 *
1917 * Tries to find the used Transceiver
1918 *
1919 */
1920static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
1921{
1922 unsigned int i;
527b6af4 1923
1da177e4 1924 IRDA_ASSERT(self != NULL, return;);
527b6af4 1925
98b77773
DT		 1926 for (i = 0; smsc_transceivers[i].name != NULL; i++)
1927 if (smsc_transceivers[i].probe(self->io.fir_base)) {
1da177e4
LT		 1928 IRDA_MESSAGE(" %s transceiver found\n",
1929 smsc_transceivers[i].name);
98b77773 1930 self->transceiver= i + 1;
1da177e4
LT		 1931 return;
1932 }
98b77773 1933
1da177e4
LT		 1934 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
1935 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
527b6af4 1936
98b77773 1937 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
1da177e4
LT		 1938}
1939
1940
1941/*
1942 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
1943 *
1944 * Set the transceiver according to the speed
1945 *
1946 */
1947static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
1948{
1949 unsigned int trx;
527b6af4 1950
1da177e4 1951 trx = self->transceiver;
98b77773
DT		 1952 if (trx > 0)
1953 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
1da177e4
LT		 1954}
1955
1956/*
1957 * Function smsc_ircc_wait_hw_transmitter_finish ()
1958 *
1959 * Wait for the real end of HW transmission
1960 *
1961 * The UART is a strict FIFO, and we get called only when we have finished
1962 * pushing data to the FIFO, so the maximum amount of time we must wait
1963 * is only for the FIFO to drain out.
1964 *
1965 * We use a simple calibrated loop. We may need to adjust the loop
1966 * delay (udelay) to balance I/O traffic and latency. And we also need to
1967 * adjust the maximum timeout.
1968 * It would probably be better to wait for the proper interrupt,
1969 * but it doesn't seem to be available.
1970 *
1971 * We can't use jiffies or kernel timers because :
1972 * 1) We are called from the interrupt handler, which disable softirqs,
1973 * so jiffies won't be increased
1974 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
1975 * want to wait that long to detect stuck hardware.
1976 * Jean II
1977 */
1978
1979static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
1980{
98b77773 1981 int iobase = self->io.sir_base;
1da177e4 1982 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
527b6af4 1983
1da177e4 1984 /* Calibrated busy loop */
98b77773 1985 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
1da177e4
LT		 1986 udelay(1);
1987
98b77773 1988 if (count == 0)
1da177e4
LT		 1989 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__);
1990}
1991
1992
1993/* PROBING
1994 *
1995 *
1996 */
1997
1998static int __init smsc_ircc_look_for_chips(void)
1999{
b6158d23 2000 struct smsc_chip_address *address;
98b77773 2001 char *type;
1da177e4 2002 unsigned int cfg_base, found;
527b6af4 2003
1da177e4
LT		 2004 found = 0;
2005 address = possible_addresses;
527b6af4 2006
98b77773 2007 while (address->cfg_base) {
1da177e4 2008 cfg_base = address->cfg_base;
527b6af4 2009
1da177e4 2010 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/
527b6af4 2011
98b77773 2012 if (address->type & SMSCSIO_TYPE_FDC) {
1da177e4 2013 type = "FDC";
98b77773
DT		 2014 if (address->type & SMSCSIO_TYPE_FLAT)
2015 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2016 found++;
2017
2018 if (address->type & SMSCSIO_TYPE_PAGED)
2019 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2020 found++;
1da177e4 2021 }
98b77773 2022 if (address->type & SMSCSIO_TYPE_LPC) {
1da177e4 2023 type = "LPC";
98b77773
DT		 2024 if (address->type & SMSCSIO_TYPE_FLAT)
2025 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2026 found++;
2027
2028 if (address->type & SMSCSIO_TYPE_PAGED)
2029 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2030 found++;
1da177e4
LT		 2031 }
2032 address++;
2033 }
2034 return found;
527b6af4 2035}
1da177e4
LT		 2036
2037/*
2038 * Function smsc_superio_flat (chip, base, type)
2039 *
2040 * Try to get configuration of a smc SuperIO chip with flat register model
2041 *
2042 */
b6158d23 2043static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
1da177e4
LT		 2044{
2045 unsigned short firbase, sirbase;
2046 u8 mode, dma, irq;
2047 int ret = -ENODEV;
2048
2049 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2050
98b77773 2051 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
1da177e4
LT		 2052 return ret;
2053
2054 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
98b77773 2055 mode = inb(cfgbase + 1);
527b6af4 2056
1da177e4 2057 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/
527b6af4 2058
98b77773 2059 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
1da177e4
LT		 2060 IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__);
2061
2062 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
98b77773 2063 sirbase = inb(cfgbase + 1) << 2;
1da177e4 2064
527b6af4 2065 /* FIR iobase */
1da177e4 2066 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
98b77773 2067 firbase = inb(cfgbase + 1) << 3;
1da177e4
LT		 2068
2069 /* DMA */
2070 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
98b77773 2071 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
527b6af4 2072
1da177e4
LT		 2073 /* IRQ */
2074 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
98b77773 2075 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
1da177e4
LT		 2076
2077 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode);
2078
98b77773
DT		 2079 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2080 ret = 0;
527b6af4 2081
1da177e4
LT		 2082 /* Exit configuration */
2083 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2084
2085 return ret;
2086}
2087
2088/*
2089 * Function smsc_superio_paged (chip, base, type)
2090 *
2091 * Try to get configuration of a smc SuperIO chip with paged register model
2092 *
2093 */
b6158d23 2094static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
1da177e4
LT		 2095{
2096 unsigned short fir_io, sir_io;
2097 int ret = -ENODEV;
527b6af4 2098
1da177e4
LT		 2099 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2100
98b77773 2101 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
1da177e4 2102 return ret;
527b6af4 2103
1da177e4
LT		 2104 /* Select logical device (UART2) */
2105 outb(0x07, cfg_base);
2106 outb(0x05, cfg_base + 1);
527b6af4 2107
1da177e4
LT		 2108 /* SIR iobase */
2109 outb(0x60, cfg_base);
98b77773 2110 sir_io = inb(cfg_base + 1) << 8;
1da177e4
LT		 2111 outb(0x61, cfg_base);
2112 sir_io |= inb(cfg_base + 1);
527b6af4 2113
1da177e4
LT		 2114 /* Read FIR base */
2115 outb(0x62, cfg_base);
2116 fir_io = inb(cfg_base + 1) << 8;
2117 outb(0x63, cfg_base);
2118 fir_io |= inb(cfg_base + 1);
2119 outb(0x2b, cfg_base); /* ??? */
2120
98b77773
DT		 2121 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2122 ret = 0;
527b6af4 2123
1da177e4
LT		 2124 /* Exit configuration */
2125 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2126
2127 return ret;
2128}
2129
2130
98b77773 2131static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
1da177e4
LT		 2132{
2133 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2134
2135 outb(reg, cfg_base);
98b77773 2136 return inb(cfg_base) != reg ? -1 : 0;
1da177e4
LT		 2137}
2138
b6158d23 2139static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
1da177e4 2140{
98b77773 2141 u8 devid, xdevid, rev;
1da177e4
LT		 2142
2143 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2144
2145 /* Leave configuration */
2146
2147 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2148
2149 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2150 return NULL;
2151
2152 outb(reg, cfg_base);
2153
98b77773 2154 xdevid = inb(cfg_base + 1);
1da177e4
LT		 2155
2156 /* Enter configuration */
2157
2158 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2159
2160 #if 0
2161 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2162 return NULL;
2163 #endif
527b6af4 2164
1da177e4
LT		 2165 /* probe device ID */
2166
98b77773 2167 if (smsc_access(cfg_base, reg))
1da177e4
LT		 2168 return NULL;
2169
98b77773 2170 devid = inb(cfg_base + 1);
527b6af4 2171
98b77773 2172 if (devid == 0 || devid == 0xff) /* typical values for unused port */
1da177e4
LT		 2173 return NULL;
2174
2175 /* probe revision ID */
2176
98b77773 2177 if (smsc_access(cfg_base, reg + 1))
1da177e4
LT		 2178 return NULL;
2179
98b77773 2180 rev = inb(cfg_base + 1);
1da177e4 2181
98b77773 2182 if (rev >= 128) /* i think this will make no sense */
1da177e4
LT		 2183 return NULL;
2184
98b77773 2185 if (devid == xdevid) /* protection against false positives */
1da177e4
LT		 2186 return NULL;
2187
2188 /* Check for expected device ID; are there others? */
2189
98b77773 2190 while (chip->devid != devid) {
1da177e4
LT		 2191
2192 chip++;
2193
98b77773 2194 if (chip->name == NULL)
1da177e4
LT		 2195 return NULL;
2196 }
2197
98b77773
DT		 2198 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2199 devid, rev, cfg_base, type, chip->name);
1da177e4 2200
98b77773 2201 if (chip->rev > rev) {
527b6af4 2202 IRDA_MESSAGE("Revision higher than expected\n");
1da177e4
LT		 2203 return NULL;
2204 }
527b6af4 2205
98b77773 2206 if (chip->flags & NoIRDA)
1da177e4
LT		 2207 IRDA_MESSAGE("chipset does not support IRDA\n");
2208
2209 return chip;
2210}
2211
2212static int __init smsc_superio_fdc(unsigned short cfg_base)
2213{
2214 int ret = -1;
2215
2216 if (!request_region(cfg_base, 2, driver_name)) {
2217 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2218 __FUNCTION__, cfg_base);
2219 } else {
98b77773
DT		 2220 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2221 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
1da177e4
LT		 2222 ret = 0;
2223
2224 release_region(cfg_base, 2);
2225 }
2226
2227 return ret;
2228}
2229
2230static int __init smsc_superio_lpc(unsigned short cfg_base)
2231{
2232 int ret = -1;
2233
2234 if (!request_region(cfg_base, 2, driver_name)) {
2235 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2236 __FUNCTION__, cfg_base);
2237 } else {
98b77773
DT		 2238 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2239 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
1da177e4 2240 ret = 0;
98b77773 2241
1da177e4
LT		 2242 release_region(cfg_base, 2);
2243 }
2244 return ret;
2245}
2246
2247/************************************************
2248 *
2249 * Transceivers specific functions
2250 *
2251 ************************************************/
2252
2253
2254/*
2255 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2256 *
2257 * Program transceiver through smsc-ircc ATC circuitry
2258 *
2259 */
2260
2261static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2262{
2263 unsigned long jiffies_now, jiffies_timeout;
98b77773 2264 u8 val;
527b6af4 2265
98b77773
DT		 2266 jiffies_now = jiffies;
2267 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
527b6af4 2268
1da177e4
LT		 2269 /* ATC */
2270 register_bank(fir_base, 4);
98b77773
DT		 2271 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2272 fir_base + IRCC_ATC);
2273
2274 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2275 !time_after(jiffies, jiffies_timeout))
2276 /* empty */;
2277
2278 if (val)
1da177e4 2279 IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__,
98b77773 2280 inb(fir_base + IRCC_ATC));
1da177e4
LT		 2281}
2282
2283/*
2284 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2285 *
2286 * Probe transceiver smsc-ircc ATC circuitry
2287 *
2288 */
2289
2290static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2291{
2292 return 0;
2293}
2294
2295/*
2296 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2297 *
527b6af4 2298 * Set transceiver
1da177e4
LT		 2299 *
2300 */
2301
2302static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2303{
98b77773 2304 u8 fast_mode;
527b6af4 2305
98b77773
DT		 2306 switch (speed) {
2307 default:
2308 case 576000 :
527b6af4 2309 fast_mode = 0;
1da177e4 2310 break;
98b77773
DT		 2311 case 1152000 :
2312 case 4000000 :
1da177e4
LT		 2313 fast_mode = IRCC_LCR_A_FAST;
2314 break;
1da177e4
LT		 2315 }
2316 register_bank(fir_base, 0);
98b77773 2317 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 2318}
2319
2320/*
2321 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2322 *
527b6af4 2323 * Probe transceiver
1da177e4
LT		 2324 *
2325 */
2326
2327static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2328{
2329 return 0;
2330}
2331
2332/*
2333 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2334 *
527b6af4 2335 * Set transceiver
1da177e4
LT		 2336 *
2337 */
2338
2339static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2340{
98b77773 2341 u8 fast_mode;
527b6af4 2342
98b77773
DT		 2343 switch (speed) {
2344 default:
2345 case 576000 :
527b6af4 2346 fast_mode = 0;
1da177e4 2347 break;
98b77773
DT		 2348 case 1152000 :
2349 case 4000000 :
1da177e4
LT		 2350 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
2351 break;
527b6af4 2352
1da177e4
LT		 2353 }
2354 /* This causes an interrupt */
2355 register_bank(fir_base, 0);
98b77773 2356 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 2357}
2358
2359/*
2360 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
2361 *
527b6af4 2362 * Probe transceiver
1da177e4
LT		 2363 *
2364 */
2365
2366static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
2367{
2368 return 0;
2369}
2370
2371
2372module_init(smsc_ircc_init);
2373module_exit(smsc_ircc_cleanup);
Linux kernel - Deliverables
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