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Create platform_device.h to contain all the platform device details.
[deliverable/linux.git] / drivers / net / irda / smsc-ircc2.c
CommitLineData
1da177e4
LT		 1/*********************************************************************
2 * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
3 *
4 * Description: Driver for the SMC Infrared Communications Controller
5 * Status: Experimental.
6 * Author: Daniele Peri (peri@csai.unipa.it)
527b6af4
DT		 7 * Created at:
8 * Modified at:
9 * Modified by:
10 *
1da177e4
LT		 11 * Copyright (c) 2002 Daniele Peri
12 * All Rights Reserved.
13 * Copyright (c) 2002 Jean Tourrilhes
14 *
15 *
16 * Based on smc-ircc.c:
17 *
18 * Copyright (c) 2001 Stefani Seibold
19 * Copyright (c) 1999-2001 Dag Brattli
527b6af4 20 * Copyright (c) 1998-1999 Thomas Davis,
1da177e4
LT		 21 *
22 * and irport.c:
23 *
24 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
25 *
527b6af4
DT		 26 *
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License as
29 * published by the Free Software Foundation; either version 2 of
1da177e4 30 * the License, or (at your option) any later version.
527b6af4 31 *
1da177e4
LT		 32 * This program is distributed in the hope that it will be useful,
33 * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 * GNU General Public License for more details.
527b6af4
DT		 36 *
37 * You should have received a copy of the GNU General Public License
38 * along with this program; if not, write to the Free Software
39 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1da177e4
LT		 40 * MA 02111-1307 USA
41 *
42 ********************************************************************/
43
44#include <linux/module.h>
45#include <linux/kernel.h>
46#include <linux/types.h>
47#include <linux/skbuff.h>
48#include <linux/netdevice.h>
49#include <linux/ioport.h>
50#include <linux/delay.h>
51#include <linux/slab.h>
52#include <linux/init.h>
53#include <linux/rtnetlink.h>
54#include <linux/serial_reg.h>
55#include <linux/dma-mapping.h>
d052d1be 56#include <linux/platform_device.h>
1da177e4
LT		 57
58#include <asm/io.h>
59#include <asm/dma.h>
60#include <asm/byteorder.h>
61
62#include <linux/spinlock.h>
63#include <linux/pm.h>
64
65#include <net/irda/wrapper.h>
66#include <net/irda/irda.h>
67#include <net/irda/irda_device.h>
68
69#include "smsc-ircc2.h"
70#include "smsc-sio.h"
71
98b77773
DT		 72
73MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
74MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
75MODULE_LICENSE("GPL");
76
98b77773
DT		 77static int ircc_dma = 255;
78module_param(ircc_dma, int, 0);
79MODULE_PARM_DESC(ircc_dma, "DMA channel");
80
81static int ircc_irq = 255;
82module_param(ircc_irq, int, 0);
83MODULE_PARM_DESC(ircc_irq, "IRQ line");
84
85static int ircc_fir;
86module_param(ircc_fir, int, 0);
87MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
88
89static int ircc_sir;
90module_param(ircc_sir, int, 0);
91MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
92
93static int ircc_cfg;
94module_param(ircc_cfg, int, 0);
95MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
96
97static int ircc_transceiver;
98module_param(ircc_transceiver, int, 0);
99MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
100
1da177e4
LT		 101/* Types */
102
103struct smsc_transceiver {
104 char *name;
527b6af4 105 void (*set_for_speed)(int fir_base, u32 speed);
1da177e4
LT		 106 int (*probe)(int fir_base);
107};
1da177e4
LT		 108
109struct smsc_chip {
110 char *name;
111 #if 0
112 u8 type;
113 #endif
114 u16 flags;
115 u8 devid;
116 u8 rev;
117};
1da177e4
LT		 118
119struct smsc_chip_address {
120 unsigned int cfg_base;
121 unsigned int type;
122};
1da177e4
LT		 123
124/* Private data for each instance */
125struct smsc_ircc_cb {
126 struct net_device *netdev; /* Yes! we are some kind of netdevice */
127 struct net_device_stats stats;
128 struct irlap_cb *irlap; /* The link layer we are binded to */
527b6af4 129
1da177e4
LT		 130 chipio_t io; /* IrDA controller information */
131 iobuff_t tx_buff; /* Transmit buffer */
132 iobuff_t rx_buff; /* Receive buffer */
133 dma_addr_t tx_buff_dma;
134 dma_addr_t rx_buff_dma;
135
136 struct qos_info qos; /* QoS capabilities for this device */
137
138 spinlock_t lock; /* For serializing operations */
527b6af4 139
1da177e4
LT		 140 __u32 new_speed;
141 __u32 flags; /* Interface flags */
142
143 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
144 int tx_len; /* Number of frames in tx_buff */
145
146 int transceiver;
6bb3b2cd 147 struct platform_device *pldev;
1da177e4
LT		 148};
149
150/* Constants */
151
6bb3b2cd
DT		 152#define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
153
1da177e4
LT		 154#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
155#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
98b77773 156#define SMSC_IRCC2_C_NET_TIMEOUT 0
1da177e4
LT		 157#define SMSC_IRCC2_C_SIR_STOP 0
158
6bb3b2cd
DT		 159static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
160
1da177e4
LT		 161/* Prototypes */
162
163static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
164static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
165static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
166static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
167static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
168static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
80a90589
DT		 169static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
170static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
1da177e4
LT		 171static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
172static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
173static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
80a90589
DT		 174static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
175static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
0fa2f491
DT		 176static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
177static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
1da177e4
LT		 178static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs);
179static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
180static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
181#if SMSC_IRCC2_C_SIR_STOP
182static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
183#endif
184static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
185static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
186static int smsc_ircc_net_open(struct net_device *dev);
187static int smsc_ircc_net_close(struct net_device *dev);
188static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
189#if SMSC_IRCC2_C_NET_TIMEOUT
190static void smsc_ircc_timeout(struct net_device *dev);
191#endif
192static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
1da177e4
LT		 193static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
194static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
195static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
196static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
197
198/* Probing */
199static int __init smsc_ircc_look_for_chips(void);
b6158d23
DT		 200static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
201static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
202static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
1da177e4
LT		 203static int __init smsc_superio_fdc(unsigned short cfg_base);
204static int __init smsc_superio_lpc(unsigned short cfg_base);
205
206/* Transceivers specific functions */
207
208static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
209static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
210static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
211static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
212static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
213static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
214
215/* Power Management */
216
9480e307
RK		 217static int smsc_ircc_suspend(struct device *dev, pm_message_t state);
218static int smsc_ircc_resume(struct device *dev);
1da177e4 219
6bb3b2cd
DT		 220static struct device_driver smsc_ircc_driver = {
221 .name = SMSC_IRCC2_DRIVER_NAME,
222 .bus = &platform_bus_type,
223 .suspend = smsc_ircc_suspend,
224 .resume = smsc_ircc_resume,
225};
1da177e4
LT		 226
227/* Transceivers for SMSC-ircc */
228
b6158d23 229static struct smsc_transceiver smsc_transceivers[] =
1da177e4 230{
98b77773
DT		 231 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
232 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
233 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
234 { NULL, NULL }
1da177e4 235};
a956f4ca 236#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
1da177e4
LT		 237
238/* SMC SuperIO chipsets definitions */
239
240#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
241#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
242#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
243#define SIR 0 /* SuperIO Chip has only slow IRDA */
244#define FIR 4 /* SuperIO Chip has fast IRDA */
245#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
246
b6158d23 247static struct smsc_chip __initdata fdc_chips_flat[] =
1da177e4
LT		 248{
249 /* Base address 0x3f0 or 0x370 */
250 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
251 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
252 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
253 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
254 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
255 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
256 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
257 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
258 { NULL }
259};
260
b6158d23 261static struct smsc_chip __initdata fdc_chips_paged[] =
1da177e4
LT		 262{
263 /* Base address 0x3f0 or 0x370 */
264 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
265 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
266 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
267 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
268 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
269 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
270 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
271 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
272 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
273 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
274 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
275 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
276 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
277 { NULL }
278};
279
b6158d23 280static struct smsc_chip __initdata lpc_chips_flat[] =
1da177e4
LT		 281{
282 /* Base address 0x2E or 0x4E */
283 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
284 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
285 { NULL }
286};
287
b6158d23 288static struct smsc_chip __initdata lpc_chips_paged[] =
1da177e4
LT		 289{
290 /* Base address 0x2E or 0x4E */
291 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
292 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
293 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
294 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
295 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
296 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
297 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
298 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
299 { NULL }
300};
301
302#define SMSCSIO_TYPE_FDC 1
303#define SMSCSIO_TYPE_LPC 2
304#define SMSCSIO_TYPE_FLAT 4
305#define SMSCSIO_TYPE_PAGED 8
306
b6158d23 307static struct smsc_chip_address __initdata possible_addresses[] =
1da177e4 308{
98b77773
DT		 309 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
310 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
311 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
312 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
313 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
314 { 0, 0 }
1da177e4
LT		 315};
316
317/* Globals */
318
98b77773
DT		 319static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
320static unsigned short dev_count;
1da177e4
LT		 321
322static inline void register_bank(int iobase, int bank)
323{
98b77773
DT		 324 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
325 iobase + IRCC_MASTER);
1da177e4
LT		 326}
327
328
329/*******************************************************************************
330 *
331 *
332 * SMSC-ircc stuff
333 *
334 *
335 *******************************************************************************/
336
337/*
338 * Function smsc_ircc_init ()
339 *
340 * Initialize chip. Just try to find out how many chips we are dealing with
341 * and where they are
342 */
343static int __init smsc_ircc_init(void)
344{
6bb3b2cd 345 int ret;
1da177e4
LT		 346
347 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
348
6bb3b2cd
DT		 349 ret = driver_register(&smsc_ircc_driver);
350 if (ret) {
351 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
352 return ret;
353 }
354
98b77773 355 dev_count = 0;
527b6af4 356
98b77773 357 if (ircc_fir > 0 && ircc_sir > 0) {
1da177e4
LT		 358 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
359 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
360
6bb3b2cd
DT		 361 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
362 ret = -ENODEV;
363 } else {
505db036 364 ret = -ENODEV;
1da177e4 365
6bb3b2cd
DT		 366 /* try user provided configuration register base address */
367 if (ircc_cfg > 0) {
368 IRDA_MESSAGE(" Overriding configuration address "
369 "0x%04x\n", ircc_cfg);
370 if (!smsc_superio_fdc(ircc_cfg))
371 ret = 0;
372 if (!smsc_superio_lpc(ircc_cfg))
373 ret = 0;
374 }
1da177e4 375
6bb3b2cd 376 if (smsc_ircc_look_for_chips() > 0)
1da177e4
LT		 377 ret = 0;
378 }
527b6af4 379
6bb3b2cd
DT		 380 if (ret)
381 driver_unregister(&smsc_ircc_driver);
527b6af4 382
1da177e4
LT		 383 return ret;
384}
385
386/*
387 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
388 *
389 * Try to open driver instance
390 *
391 */
392static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
393{
394 struct smsc_ircc_cb *self;
395 struct net_device *dev;
396 int err;
527b6af4 397
1da177e4
LT		 398 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
399
400 err = smsc_ircc_present(fir_base, sir_base);
98b77773 401 if (err)
1da177e4 402 goto err_out;
527b6af4 403
1da177e4 404 err = -ENOMEM;
a956f4ca 405 if (dev_count >= ARRAY_SIZE(dev_self)) {
1da177e4
LT		 406 IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__);
407 goto err_out1;
408 }
409
410 /*
411 * Allocate new instance of the driver
412 */
413 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
414 if (!dev) {
415 IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__);
416 goto err_out1;
417 }
418
419 SET_MODULE_OWNER(dev);
420
421 dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
422#if SMSC_IRCC2_C_NET_TIMEOUT
423 dev->tx_timeout = smsc_ircc_timeout;
98b77773 424 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
1da177e4
LT		 425#endif
426 dev->open = smsc_ircc_net_open;
427 dev->stop = smsc_ircc_net_close;
428 dev->do_ioctl = smsc_ircc_net_ioctl;
429 dev->get_stats = smsc_ircc_net_get_stats;
527b6af4 430
da0841a0 431 self = netdev_priv(dev);
1da177e4
LT		 432 self->netdev = dev;
433
434 /* Make ifconfig display some details */
435 dev->base_addr = self->io.fir_base = fir_base;
436 dev->irq = self->io.irq = irq;
437
438 /* Need to store self somewhere */
6bb3b2cd 439 dev_self[dev_count] = self;
1da177e4
LT		 440 spin_lock_init(&self->lock);
441
527b6af4 442 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
1da177e4
LT		 443 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
444
445 self->rx_buff.head =
446 dma_alloc_coherent(NULL, self->rx_buff.truesize,
447 &self->rx_buff_dma, GFP_KERNEL);
448 if (self->rx_buff.head == NULL) {
449 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
450 driver_name);
451 goto err_out2;
452 }
453
454 self->tx_buff.head =
455 dma_alloc_coherent(NULL, self->tx_buff.truesize,
456 &self->tx_buff_dma, GFP_KERNEL);
457 if (self->tx_buff.head == NULL) {
458 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
459 driver_name);
460 goto err_out3;
461 }
462
463 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
464 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
465
466 self->rx_buff.in_frame = FALSE;
467 self->rx_buff.state = OUTSIDE_FRAME;
468 self->tx_buff.data = self->tx_buff.head;
469 self->rx_buff.data = self->rx_buff.head;
527b6af4 470
1da177e4 471 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
1da177e4 472 smsc_ircc_setup_qos(self);
1da177e4 473 smsc_ircc_init_chip(self);
527b6af4 474
98b77773
DT		 475 if (ircc_transceiver > 0 &&
476 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
1da177e4
LT		 477 self->transceiver = ircc_transceiver;
478 else
479 smsc_ircc_probe_transceiver(self);
480
481 err = register_netdev(self->netdev);
98b77773 482 if (err) {
1da177e4
LT		 483 IRDA_ERROR("%s, Network device registration failed!\n",
484 driver_name);
485 goto err_out4;
486 }
487
6bb3b2cd
DT		 488 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
489 dev_count, NULL, 0);
490 if (IS_ERR(self->pldev)) {
491 err = PTR_ERR(self->pldev);
492 goto err_out5;
493 }
494 dev_set_drvdata(&self->pldev->dev, self);
1da177e4
LT		 495
496 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
6bb3b2cd 497 dev_count++;
1da177e4
LT		 498
499 return 0;
98b77773 500
6bb3b2cd
DT		 501 err_out5:
502 unregister_netdev(self->netdev);
503
1da177e4
LT		 504 err_out4:
505 dma_free_coherent(NULL, self->tx_buff.truesize,
506 self->tx_buff.head, self->tx_buff_dma);
507 err_out3:
508 dma_free_coherent(NULL, self->rx_buff.truesize,
509 self->rx_buff.head, self->rx_buff_dma);
510 err_out2:
511 free_netdev(self->netdev);
6bb3b2cd 512 dev_self[dev_count] = NULL;
1da177e4
LT		 513 err_out1:
514 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
515 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
516 err_out:
517 return err;
518}
519
520/*
521 * Function smsc_ircc_present(fir_base, sir_base)
522 *
523 * Check the smsc-ircc chip presence
524 *
525 */
526static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
527{
528 unsigned char low, high, chip, config, dma, irq, version;
529
530 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
531 driver_name)) {
532 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
533 __FUNCTION__, fir_base);
534 goto out1;
535 }
536
537 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
538 driver_name)) {
539 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
540 __FUNCTION__, sir_base);
541 goto out2;
542 }
543
544 register_bank(fir_base, 3);
545
98b77773
DT		 546 high = inb(fir_base + IRCC_ID_HIGH);
547 low = inb(fir_base + IRCC_ID_LOW);
548 chip = inb(fir_base + IRCC_CHIP_ID);
549 version = inb(fir_base + IRCC_VERSION);
550 config = inb(fir_base + IRCC_INTERFACE);
1da177e4
LT		 551 dma = config & IRCC_INTERFACE_DMA_MASK;
552 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
553
527b6af4 554 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
98b77773 555 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
1da177e4
LT		 556 __FUNCTION__, fir_base);
557 goto out3;
558 }
559 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
560 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
561 chip & 0x0f, version, fir_base, sir_base, dma, irq);
562
563 return 0;
98b77773 564
1da177e4
LT		 565 out3:
566 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
567 out2:
568 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
569 out1:
570 return -ENODEV;
571}
572
573/*
574 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
575 *
576 * Setup I/O
577 *
578 */
527b6af4
DT		 579static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
580 unsigned int fir_base, unsigned int sir_base,
1da177e4
LT		 581 u8 dma, u8 irq)
582{
583 unsigned char config, chip_dma, chip_irq;
584
585 register_bank(fir_base, 3);
98b77773
DT		 586 config = inb(fir_base + IRCC_INTERFACE);
587 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
588 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
1da177e4
LT		 589
590 self->io.fir_base = fir_base;
591 self->io.sir_base = sir_base;
592 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
593 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
594 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
595 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
596
597 if (irq < 255) {
598 if (irq != chip_irq)
599 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
600 driver_name, chip_irq, irq);
601 self->io.irq = irq;
98b77773 602 } else
1da177e4 603 self->io.irq = chip_irq;
527b6af4 604
1da177e4
LT		 605 if (dma < 255) {
606 if (dma != chip_dma)
607 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
608 driver_name, chip_dma, dma);
609 self->io.dma = dma;
98b77773 610 } else
1da177e4
LT		 611 self->io.dma = chip_dma;
612
613}
614
615/*
616 * Function smsc_ircc_setup_qos(self)
617 *
618 * Setup qos
619 *
620 */
621static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
622{
623 /* Initialize QoS for this device */
624 irda_init_max_qos_capabilies(&self->qos);
527b6af4 625
1da177e4
LT		 626 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
627 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
628
629 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
630 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
631 irda_qos_bits_to_value(&self->qos);
632}
633
634/*
635 * Function smsc_ircc_init_chip(self)
636 *
637 * Init chip
638 *
639 */
640static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
641{
527b6af4
DT		 642 int iobase, ir_mode, ctrl, fast;
643
98b77773 644 IRDA_ASSERT(self != NULL, return;);
1da177e4 645
98b77773 646 iobase = self->io.fir_base;
1da177e4
LT		 647 ir_mode = IRCC_CFGA_IRDA_SIR_A;
648 ctrl = 0;
649 fast = 0;
650
651 register_bank(iobase, 0);
98b77773
DT		 652 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
653 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 654
655 register_bank(iobase, 1);
98b77773
DT		 656 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | ir_mode),
657 iobase + IRCC_SCE_CFGA);
1da177e4
LT		 658
659#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 660 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
661 iobase + IRCC_SCE_CFGB);
527b6af4 662#else
98b77773
DT		 663 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
664 iobase + IRCC_SCE_CFGB);
527b6af4 665#endif
98b77773
DT		 666 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
667 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
527b6af4 668
1da177e4 669 register_bank(iobase, 4);
98b77773 670 outb((inb(iobase + IRCC_CONTROL) & 0x30) | ctrl, iobase + IRCC_CONTROL);
527b6af4 671
1da177e4 672 register_bank(iobase, 0);
98b77773 673 outb(fast, iobase + IRCC_LCR_A);
1da177e4
LT		 674
675 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
527b6af4 676
1da177e4 677 /* Power on device */
98b77773 678 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 679}
680
681/*
682 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
683 *
684 * Process IOCTL commands for this device
685 *
686 */
687static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
688{
689 struct if_irda_req *irq = (struct if_irda_req *) rq;
690 struct smsc_ircc_cb *self;
691 unsigned long flags;
692 int ret = 0;
693
694 IRDA_ASSERT(dev != NULL, return -1;);
695
da0841a0 696 self = netdev_priv(dev);
1da177e4
LT		 697
698 IRDA_ASSERT(self != NULL, return -1;);
699
700 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
527b6af4 701
1da177e4
LT		 702 switch (cmd) {
703 case SIOCSBANDWIDTH: /* Set bandwidth */
704 if (!capable(CAP_NET_ADMIN))
705 ret = -EPERM;
706 else {
707 /* Make sure we are the only one touching
708 * self->io.speed and the hardware - Jean II */
709 spin_lock_irqsave(&self->lock, flags);
710 smsc_ircc_change_speed(self, irq->ifr_baudrate);
711 spin_unlock_irqrestore(&self->lock, flags);
712 }
713 break;
714 case SIOCSMEDIABUSY: /* Set media busy */
715 if (!capable(CAP_NET_ADMIN)) {
716 ret = -EPERM;
717 break;
718 }
719
720 irda_device_set_media_busy(self->netdev, TRUE);
721 break;
722 case SIOCGRECEIVING: /* Check if we are receiving right now */
723 irq->ifr_receiving = smsc_ircc_is_receiving(self);
724 break;
725 #if 0
726 case SIOCSDTRRTS:
727 if (!capable(CAP_NET_ADMIN)) {
728 ret = -EPERM;
729 break;
730 }
731 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
732 break;
733 #endif
734 default:
735 ret = -EOPNOTSUPP;
736 }
527b6af4 737
1da177e4
LT		 738 return ret;
739}
740
741static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
742{
da0841a0 743 struct smsc_ircc_cb *self = netdev_priv(dev);
527b6af4 744
1da177e4
LT		 745 return &self->stats;
746}
747
748#if SMSC_IRCC2_C_NET_TIMEOUT
749/*
750 * Function smsc_ircc_timeout (struct net_device *dev)
751 *
752 * The networking timeout management.
753 *
754 */
755
756static void smsc_ircc_timeout(struct net_device *dev)
757{
da0841a0 758 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 759 unsigned long flags;
760
1da177e4
LT		 761 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
762 dev->name, self->io.speed);
763 spin_lock_irqsave(&self->lock, flags);
764 smsc_ircc_sir_start(self);
765 smsc_ircc_change_speed(self, self->io.speed);
766 dev->trans_start = jiffies;
767 netif_wake_queue(dev);
768 spin_unlock_irqrestore(&self->lock, flags);
769}
770#endif
771
772/*
773 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
774 *
775 * Transmits the current frame until FIFO is full, then
776 * waits until the next transmit interrupt, and continues until the
777 * frame is transmitted.
778 */
779int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
780{
781 struct smsc_ircc_cb *self;
782 unsigned long flags;
1da177e4
LT		 783 s32 speed;
784
785 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
786
787 IRDA_ASSERT(dev != NULL, return 0;);
527b6af4 788
da0841a0 789 self = netdev_priv(dev);
1da177e4
LT		 790 IRDA_ASSERT(self != NULL, return 0;);
791
1da177e4 792 netif_stop_queue(dev);
527b6af4 793
1da177e4
LT		 794 /* Make sure test of self->io.speed & speed change are atomic */
795 spin_lock_irqsave(&self->lock, flags);
796
797 /* Check if we need to change the speed */
798 speed = irda_get_next_speed(skb);
98b77773 799 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 800 /* Check for empty frame */
801 if (!skb->len) {
802 /*
803 * We send frames one by one in SIR mode (no
804 * pipelining), so at this point, if we were sending
805 * a previous frame, we just received the interrupt
806 * telling us it is finished (UART_IIR_THRI).
807 * Therefore, waiting for the transmitter to really
808 * finish draining the fifo won't take too long.
809 * And the interrupt handler is not expected to run.
810 * - Jean II */
811 smsc_ircc_sir_wait_hw_transmitter_finish(self);
812 smsc_ircc_change_speed(self, speed);
813 spin_unlock_irqrestore(&self->lock, flags);
814 dev_kfree_skb(skb);
815 return 0;
1da177e4 816 }
98b77773 817 self->new_speed = speed;
1da177e4
LT		 818 }
819
820 /* Init tx buffer */
821 self->tx_buff.data = self->tx_buff.head;
822
823 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
527b6af4 824 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
1da177e4 825 self->tx_buff.truesize);
527b6af4 826
1da177e4
LT		 827 self->stats.tx_bytes += self->tx_buff.len;
828
829 /* Turn on transmit finished interrupt. Will fire immediately! */
80a90589 830 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
1da177e4
LT		 831
832 spin_unlock_irqrestore(&self->lock, flags);
833
834 dev_kfree_skb(skb);
527b6af4 835
1da177e4
LT		 836 return 0;
837}
838
839/*
840 * Function smsc_ircc_set_fir_speed (self, baud)
841 *
842 * Change the speed of the device
843 *
844 */
845static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
846{
847 int fir_base, ir_mode, ctrl, fast;
848
849 IRDA_ASSERT(self != NULL, return;);
850 fir_base = self->io.fir_base;
851
852 self->io.speed = speed;
853
98b77773 854 switch (speed) {
1da177e4 855 default:
527b6af4 856 case 576000:
1da177e4
LT		 857 ir_mode = IRCC_CFGA_IRDA_HDLC;
858 ctrl = IRCC_CRC;
859 fast = 0;
860 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
861 break;
862 case 1152000:
863 ir_mode = IRCC_CFGA_IRDA_HDLC;
864 ctrl = IRCC_1152 | IRCC_CRC;
865 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
866 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
867 __FUNCTION__);
868 break;
869 case 4000000:
870 ir_mode = IRCC_CFGA_IRDA_4PPM;
871 ctrl = IRCC_CRC;
872 fast = IRCC_LCR_A_FAST;
873 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
874 __FUNCTION__);
875 break;
876 }
877 #if 0
878 Now in tranceiver!
879 /* This causes an interrupt */
880 register_bank(fir_base, 0);
98b77773 881 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
1da177e4 882 #endif
527b6af4 883
1da177e4 884 register_bank(fir_base, 1);
98b77773 885 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
527b6af4 886
1da177e4 887 register_bank(fir_base, 4);
98b77773 888 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
1da177e4
LT		 889}
890
891/*
892 * Function smsc_ircc_fir_start(self)
893 *
894 * Change the speed of the device
895 *
896 */
897static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
898{
899 struct net_device *dev;
900 int fir_base;
901
902 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
903
904 IRDA_ASSERT(self != NULL, return;);
905 dev = self->netdev;
906 IRDA_ASSERT(dev != NULL, return;);
907
908 fir_base = self->io.fir_base;
909
910 /* Reset everything */
911
912 /* Install FIR transmit handler */
527b6af4 913 dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
1da177e4
LT		 914
915 /* Clear FIFO */
98b77773 916 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1da177e4
LT		 917
918 /* Enable interrupt */
98b77773 919 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1da177e4
LT		 920
921 register_bank(fir_base, 1);
922
527b6af4 923 /* Select the TX/RX interface */
1da177e4 924#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 925 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
926 fir_base + IRCC_SCE_CFGB);
527b6af4 927#else
98b77773
DT		 928 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
929 fir_base + IRCC_SCE_CFGB);
527b6af4 930#endif
98b77773 931 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1da177e4
LT		 932
933 /* Enable SCE interrupts */
98b77773 934 outb(0, fir_base + IRCC_MASTER);
1da177e4 935 register_bank(fir_base, 0);
98b77773
DT		 936 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
937 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1da177e4
LT		 938}
939
940/*
941 * Function smsc_ircc_fir_stop(self, baud)
942 *
943 * Change the speed of the device
944 *
945 */
946static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
947{
948 int fir_base;
949
950 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 951
1da177e4
LT		 952 IRDA_ASSERT(self != NULL, return;);
953
954 fir_base = self->io.fir_base;
955 register_bank(fir_base, 0);
98b77773
DT		 956 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
957 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1da177e4
LT		 958}
959
960
961/*
962 * Function smsc_ircc_change_speed(self, baud)
963 *
964 * Change the speed of the device
965 *
966 * This function *must* be called with spinlock held, because it may
967 * be called from the irq handler. - Jean II
968 */
0fa2f491 969static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1da177e4 970{
1da177e4 971 struct net_device *dev;
1da177e4 972 int last_speed_was_sir;
527b6af4 973
1da177e4
LT		 974 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed);
975
976 IRDA_ASSERT(self != NULL, return;);
977 dev = self->netdev;
1da177e4
LT		 978
979 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
980
981 #if 0
982 /* Temp Hack */
983 speed= 1152000;
984 self->io.speed = speed;
985 last_speed_was_sir = 0;
527b6af4 986 smsc_ircc_fir_start(self);
1da177e4 987 #endif
527b6af4 988
98b77773 989 if (self->io.speed == 0)
1da177e4
LT		 990 smsc_ircc_sir_start(self);
991
992 #if 0
98b77773 993 if (!last_speed_was_sir) speed = self->io.speed;
1da177e4
LT		 994 #endif
995
98b77773
DT		 996 if (self->io.speed != speed)
997 smsc_ircc_set_transceiver_for_speed(self, speed);
1da177e4
LT		 998
999 self->io.speed = speed;
527b6af4 1000
98b77773
DT		 1001 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1002 if (!last_speed_was_sir) {
1da177e4
LT		 1003 smsc_ircc_fir_stop(self);
1004 smsc_ircc_sir_start(self);
1005 }
527b6af4 1006 smsc_ircc_set_sir_speed(self, speed);
98b77773
DT		 1007 } else {
1008 if (last_speed_was_sir) {
527b6af4 1009 #if SMSC_IRCC2_C_SIR_STOP
1da177e4
LT		 1010 smsc_ircc_sir_stop(self);
1011 #endif
1012 smsc_ircc_fir_start(self);
1013 }
1014 smsc_ircc_set_fir_speed(self, speed);
1015
1016 #if 0
1017 self->tx_buff.len = 10;
1018 self->tx_buff.data = self->tx_buff.head;
527b6af4 1019
80a90589 1020 smsc_ircc_dma_xmit(self, 4000);
1da177e4
LT		 1021 #endif
1022 /* Be ready for incoming frames */
80a90589 1023 smsc_ircc_dma_receive(self);
1da177e4 1024 }
527b6af4 1025
1da177e4
LT		 1026 netif_wake_queue(dev);
1027}
1028
1029/*
1030 * Function smsc_ircc_set_sir_speed (self, speed)
1031 *
1032 * Set speed of IrDA port to specified baudrate
1033 *
1034 */
0fa2f491 1035void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1da177e4 1036{
527b6af4 1037 int iobase;
1da177e4
LT		 1038 int fcr; /* FIFO control reg */
1039 int lcr; /* Line control reg */
1040 int divisor;
1041
1042 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed);
1043
1044 IRDA_ASSERT(self != NULL, return;);
1045 iobase = self->io.sir_base;
527b6af4 1046
1da177e4
LT		 1047 /* Update accounting for new speed */
1048 self->io.speed = speed;
1049
1050 /* Turn off interrupts */
98b77773 1051 outb(0, iobase + UART_IER);
1da177e4 1052
98b77773 1053 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
527b6af4 1054
1da177e4
LT		 1055 fcr = UART_FCR_ENABLE_FIFO;
1056
527b6af4 1057 /*
1da177e4
LT		 1058 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1059 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
527b6af4 1060 * about this timeout since it will always be fast enough.
1da177e4 1061 */
98b77773
DT		 1062 fcr |= self->io.speed < 38400 ?
1063 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
527b6af4 1064
1da177e4
LT		 1065 /* IrDA ports use 8N1 */
1066 lcr = UART_LCR_WLEN8;
527b6af4 1067
98b77773
DT		 1068 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1069 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1070 outb(divisor >> 8, iobase + UART_DLM);
1071 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1072 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1da177e4
LT		 1073
1074 /* Turn on interrups */
98b77773 1075 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1da177e4
LT		 1076
1077 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed);
1078}
1079
1080
1081/*
1082 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1083 *
1084 * Transmit the frame!
1085 *
1086 */
1087static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1088{
1089 struct smsc_ircc_cb *self;
1090 unsigned long flags;
1091 s32 speed;
1da177e4
LT		 1092 int mtt;
1093
1094 IRDA_ASSERT(dev != NULL, return 0;);
da0841a0 1095 self = netdev_priv(dev);
1da177e4
LT		 1096 IRDA_ASSERT(self != NULL, return 0;);
1097
1da177e4
LT		 1098 netif_stop_queue(dev);
1099
1100 /* Make sure test of self->io.speed & speed change are atomic */
1101 spin_lock_irqsave(&self->lock, flags);
1102
1103 /* Check if we need to change the speed after this frame */
1104 speed = irda_get_next_speed(skb);
98b77773 1105 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 1106 /* Check for empty frame */
1107 if (!skb->len) {
1108 /* Note : you should make sure that speed changes
1109 * are not going to corrupt any outgoing frame.
1110 * Look at nsc-ircc for the gory details - Jean II */
527b6af4 1111 smsc_ircc_change_speed(self, speed);
1da177e4
LT		 1112 spin_unlock_irqrestore(&self->lock, flags);
1113 dev_kfree_skb(skb);
1114 return 0;
98b77773
DT		 1115 }
1116
1117 self->new_speed = speed;
1da177e4 1118 }
527b6af4 1119
1da177e4
LT		 1120 memcpy(self->tx_buff.head, skb->data, skb->len);
1121
1122 self->tx_buff.len = skb->len;
1123 self->tx_buff.data = self->tx_buff.head;
527b6af4
DT		 1124
1125 mtt = irda_get_mtt(skb);
1da177e4
LT		 1126 if (mtt) {
1127 int bofs;
1128
527b6af4 1129 /*
1da177e4
LT		 1130 * Compute how many BOFs (STA or PA's) we need to waste the
1131 * min turn time given the speed of the link.
1132 */
1133 bofs = mtt * (self->io.speed / 1000) / 8000;
1134 if (bofs > 4095)
1135 bofs = 4095;
1136
80a90589 1137 smsc_ircc_dma_xmit(self, bofs);
1da177e4
LT		 1138 } else {
1139 /* Transmit frame */
80a90589 1140 smsc_ircc_dma_xmit(self, 0);
1da177e4 1141 }
98b77773 1142
1da177e4
LT		 1143 spin_unlock_irqrestore(&self->lock, flags);
1144 dev_kfree_skb(skb);
1145
1146 return 0;
1147}
1148
1149/*
80a90589 1150 * Function smsc_ircc_dma_xmit (self, bofs)
1da177e4
LT		 1151 *
1152 * Transmit data using DMA
1153 *
1154 */
80a90589 1155static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1da177e4 1156{
80a90589 1157 int iobase = self->io.fir_base;
1da177e4
LT		 1158 u8 ctrl;
1159
1160 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1161#if 1
1162 /* Disable Rx */
1163 register_bank(iobase, 0);
98b77773 1164 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1165#endif
1166 register_bank(iobase, 1);
98b77773
DT		 1167 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1168 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1169
1170 self->io.direction = IO_XMIT;
1171
1172 /* Set BOF additional count for generating the min turn time */
1173 register_bank(iobase, 4);
98b77773
DT		 1174 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1175 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1176 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1da177e4
LT		 1177
1178 /* Set max Tx frame size */
98b77773
DT		 1179 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1180 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1da177e4
LT		 1181
1182 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
527b6af4 1183
1da177e4
LT		 1184 /* Enable burst mode chip Tx DMA */
1185 register_bank(iobase, 1);
98b77773
DT		 1186 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1187 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1188
1189 /* Setup DMA controller (must be done after enabling chip DMA) */
1190 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1191 DMA_TX_MODE);
1192
1193 /* Enable interrupt */
1194
1195 register_bank(iobase, 0);
98b77773
DT		 1196 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1197 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
527b6af4 1198
1da177e4 1199 /* Enable transmit */
98b77773 1200 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1da177e4
LT		 1201}
1202
1203/*
1204 * Function smsc_ircc_dma_xmit_complete (self)
1205 *
527b6af4 1206 * The transfer of a frame in finished. This function will only be called
1da177e4
LT		 1207 * by the interrupt handler
1208 *
1209 */
80a90589 1210static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1da177e4 1211{
80a90589
DT		 1212 int iobase = self->io.fir_base;
1213
1da177e4
LT		 1214 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1215#if 0
1216 /* Disable Tx */
1217 register_bank(iobase, 0);
98b77773 1218 outb(0x00, iobase + IRCC_LCR_B);
1da177e4 1219#endif
80a90589
DT		 1220 register_bank(iobase, 1);
1221 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1222 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1223
1224 /* Check for underrun! */
1225 register_bank(iobase, 0);
98b77773 1226 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1da177e4
LT		 1227 self->stats.tx_errors++;
1228 self->stats.tx_fifo_errors++;
1229
1230 /* Reset error condition */
1231 register_bank(iobase, 0);
98b77773
DT		 1232 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1233 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 1234 } else {
1235 self->stats.tx_packets++;
98b77773 1236 self->stats.tx_bytes += self->tx_buff.len;
1da177e4
LT		 1237 }
1238
1239 /* Check if it's time to change the speed */
1240 if (self->new_speed) {
527b6af4 1241 smsc_ircc_change_speed(self, self->new_speed);
1da177e4
LT		 1242 self->new_speed = 0;
1243 }
1244
1245 netif_wake_queue(self->netdev);
1246}
1247
1248/*
1249 * Function smsc_ircc_dma_receive(self)
1250 *
1251 * Get ready for receiving a frame. The device will initiate a DMA
1252 * if it starts to receive a frame.
1253 *
1254 */
80a90589 1255static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1da177e4 1256{
80a90589 1257 int iobase = self->io.fir_base;
1da177e4
LT		 1258#if 0
1259 /* Turn off chip DMA */
1260 register_bank(iobase, 1);
98b77773
DT		 1261 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1262 iobase + IRCC_SCE_CFGB);
1da177e4 1263#endif
527b6af4 1264
1da177e4
LT		 1265 /* Disable Tx */
1266 register_bank(iobase, 0);
98b77773 1267 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1268
1269 /* Turn off chip DMA */
1270 register_bank(iobase, 1);
98b77773
DT		 1271 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1272 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1273
1274 self->io.direction = IO_RECV;
1275 self->rx_buff.data = self->rx_buff.head;
1276
1277 /* Set max Rx frame size */
1278 register_bank(iobase, 4);
98b77773
DT		 1279 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1280 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1da177e4
LT		 1281
1282 /* Setup DMA controller */
1283 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1284 DMA_RX_MODE);
1285
1286 /* Enable burst mode chip Rx DMA */
1287 register_bank(iobase, 1);
98b77773
DT		 1288 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1289 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1290
1291 /* Enable interrupt */
1292 register_bank(iobase, 0);
98b77773
DT		 1293 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1294 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1da177e4
LT		 1295
1296 /* Enable receiver */
1297 register_bank(iobase, 0);
527b6af4 1298 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
98b77773 1299 iobase + IRCC_LCR_B);
527b6af4 1300
1da177e4
LT		 1301 return 0;
1302}
1303
1304/*
80a90589 1305 * Function smsc_ircc_dma_receive_complete(self)
1da177e4
LT		 1306 *
1307 * Finished with receiving frames
1308 *
1309 */
80a90589 1310static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1da177e4
LT		 1311{
1312 struct sk_buff *skb;
1313 int len, msgcnt, lsr;
80a90589 1314 int iobase = self->io.fir_base;
527b6af4 1315
1da177e4 1316 register_bank(iobase, 0);
527b6af4 1317
1da177e4
LT		 1318 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1319#if 0
1320 /* Disable Rx */
1321 register_bank(iobase, 0);
98b77773 1322 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1323#endif
1324 register_bank(iobase, 0);
98b77773
DT		 1325 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1326 lsr= inb(iobase + IRCC_LSR);
1327 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1da177e4
LT		 1328
1329 IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__,
1330 get_dma_residue(self->io.dma));
1331
1332 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1333
98b77773
DT		 1334 /* Look for errors */
1335 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1da177e4 1336 self->stats.rx_errors++;
98b77773
DT		 1337 if (lsr & IRCC_LSR_FRAME_ERROR)
1338 self->stats.rx_frame_errors++;
1339 if (lsr & IRCC_LSR_CRC_ERROR)
1340 self->stats.rx_crc_errors++;
1341 if (lsr & IRCC_LSR_SIZE_ERROR)
1342 self->stats.rx_length_errors++;
1343 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1344 self->stats.rx_length_errors++;
1da177e4
LT		 1345 return;
1346 }
98b77773 1347
1da177e4 1348 /* Remove CRC */
98b77773 1349 len -= self->io.speed < 4000000 ? 2 : 4;
1da177e4 1350
98b77773 1351 if (len < 2 || len > 2050) {
1da177e4
LT		 1352 IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
1353 return;
1354 }
1355 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
1356
98b77773
DT		 1357 skb = dev_alloc_skb(len + 1);
1358 if (!skb) {
1da177e4
LT		 1359 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1360 __FUNCTION__);
1361 return;
527b6af4 1362 }
1da177e4 1363 /* Make sure IP header gets aligned */
527b6af4 1364 skb_reserve(skb, 1);
1da177e4
LT		 1365
1366 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1367 self->stats.rx_packets++;
1368 self->stats.rx_bytes += len;
1369
1370 skb->dev = self->netdev;
1371 skb->mac.raw = skb->data;
1372 skb->protocol = htons(ETH_P_IRDA);
1373 netif_rx(skb);
1374}
1375
1376/*
1377 * Function smsc_ircc_sir_receive (self)
1378 *
1379 * Receive one frame from the infrared port
1380 *
1381 */
527b6af4 1382static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1da177e4
LT		 1383{
1384 int boguscount = 0;
1385 int iobase;
1386
1387 IRDA_ASSERT(self != NULL, return;);
1388
1389 iobase = self->io.sir_base;
1390
527b6af4
DT		 1391 /*
1392 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1393 * async_unwrap_char will deliver all found frames
1da177e4
LT		 1394 */
1395 do {
527b6af4 1396 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
98b77773 1397 inb(iobase + UART_RX));
1da177e4
LT		 1398
1399 /* Make sure we don't stay here to long */
1400 if (boguscount++ > 32) {
1401 IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__);
1402 break;
1403 }
98b77773 1404 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1da177e4
LT		 1405}
1406
1407
1408/*
1409 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1410 *
1411 * An interrupt from the chip has arrived. Time to do some work
1412 *
1413 */
1414static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1415{
1416 struct net_device *dev = (struct net_device *) dev_id;
1417 struct smsc_ircc_cb *self;
1418 int iobase, iir, lcra, lsr;
1419 irqreturn_t ret = IRQ_NONE;
1420
1421 if (dev == NULL) {
527b6af4 1422 printk(KERN_WARNING "%s: irq %d for unknown device.\n",
1da177e4
LT		 1423 driver_name, irq);
1424 goto irq_ret;
1425 }
da0841a0
DT		 1426
1427 self = netdev_priv(dev);
1da177e4
LT		 1428 IRDA_ASSERT(self != NULL, return IRQ_NONE;);
1429
1430 /* Serialise the interrupt handler in various CPUs, stop Tx path */
527b6af4 1431 spin_lock(&self->lock);
1da177e4
LT		 1432
1433 /* Check if we should use the SIR interrupt handler */
98b77773 1434 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1da177e4
LT		 1435 ret = smsc_ircc_interrupt_sir(dev);
1436 goto irq_ret_unlock;
1437 }
1438
1439 iobase = self->io.fir_base;
1440
1441 register_bank(iobase, 0);
98b77773 1442 iir = inb(iobase + IRCC_IIR);
527b6af4 1443 if (iir == 0)
1da177e4
LT		 1444 goto irq_ret_unlock;
1445 ret = IRQ_HANDLED;
1446
1447 /* Disable interrupts */
98b77773
DT		 1448 outb(0, iobase + IRCC_IER);
1449 lcra = inb(iobase + IRCC_LCR_A);
1450 lsr = inb(iobase + IRCC_LSR);
527b6af4 1451
1da177e4
LT		 1452 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1453
1454 if (iir & IRCC_IIR_EOM) {
1455 if (self->io.direction == IO_RECV)
80a90589 1456 smsc_ircc_dma_receive_complete(self);
1da177e4 1457 else
80a90589 1458 smsc_ircc_dma_xmit_complete(self);
527b6af4 1459
80a90589 1460 smsc_ircc_dma_receive(self);
1da177e4
LT		 1461 }
1462
1463 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1464 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/
1465 }
1466
1467 /* Enable interrupts again */
1468
1469 register_bank(iobase, 0);
98b77773 1470 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1da177e4
LT		 1471
1472 irq_ret_unlock:
1473 spin_unlock(&self->lock);
1474 irq_ret:
1475 return ret;
1476}
1477
1478/*
1479 * Function irport_interrupt_sir (irq, dev_id, regs)
1480 *
1481 * Interrupt handler for SIR modes
1482 */
1483static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1484{
da0841a0 1485 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 1486 int boguscount = 0;
1487 int iobase;
1488 int iir, lsr;
1489
1490 /* Already locked comming here in smsc_ircc_interrupt() */
1491 /*spin_lock(&self->lock);*/
1492
1493 iobase = self->io.sir_base;
1494
98b77773 1495 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1496 if (iir == 0)
1497 return IRQ_NONE;
1498 while (iir) {
1499 /* Clear interrupt */
98b77773 1500 lsr = inb(iobase + UART_LSR);
1da177e4 1501
527b6af4 1502 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1da177e4
LT		 1503 __FUNCTION__, iir, lsr, iobase);
1504
1505 switch (iir) {
1506 case UART_IIR_RLSI:
1507 IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__);
1508 break;
1509 case UART_IIR_RDI:
1510 /* Receive interrupt */
1511 smsc_ircc_sir_receive(self);
1512 break;
1513 case UART_IIR_THRI:
1514 if (lsr & UART_LSR_THRE)
1515 /* Transmitter ready for data */
1516 smsc_ircc_sir_write_wakeup(self);
1517 break;
1518 default:
1519 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1520 __FUNCTION__, iir);
1521 break;
527b6af4
DT		 1522 }
1523
1da177e4
LT		 1524 /* Make sure we don't stay here to long */
1525 if (boguscount++ > 100)
1526 break;
1527
527b6af4 1528 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1529 }
1530 /*spin_unlock(&self->lock);*/
1531 return IRQ_HANDLED;
1532}
1533
1534
1535#if 0 /* unused */
1536/*
1537 * Function ircc_is_receiving (self)
1538 *
1539 * Return TRUE is we are currently receiving a frame
1540 *
1541 */
1542static int ircc_is_receiving(struct smsc_ircc_cb *self)
1543{
1544 int status = FALSE;
1545 /* int iobase; */
1546
1547 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1548
1549 IRDA_ASSERT(self != NULL, return FALSE;);
1550
1551 IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__,
1552 get_dma_residue(self->io.dma));
1553
1554 status = (self->rx_buff.state != OUTSIDE_FRAME);
527b6af4 1555
1da177e4
LT		 1556 return status;
1557}
1558#endif /* unused */
1559
1560
1561/*
1562 * Function smsc_ircc_net_open (dev)
1563 *
1564 * Start the device
1565 *
1566 */
1567static int smsc_ircc_net_open(struct net_device *dev)
1568{
1569 struct smsc_ircc_cb *self;
1da177e4
LT		 1570 char hwname[16];
1571 unsigned long flags;
1572
1573 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 1574
1da177e4 1575 IRDA_ASSERT(dev != NULL, return -1;);
da0841a0 1576 self = netdev_priv(dev);
1da177e4 1577 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1578
527b6af4 1579 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1da177e4
LT		 1580 (void *) dev)) {
1581 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1582 __FUNCTION__, self->io.irq);
1583 return -EAGAIN;
1584 }
1585
1586 spin_lock_irqsave(&self->lock, flags);
1587 /*smsc_ircc_sir_start(self);*/
1588 self->io.speed = 0;
1589 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1590 spin_unlock_irqrestore(&self->lock, flags);
527b6af4 1591
1da177e4
LT		 1592 /* Give self a hardware name */
1593 /* It would be cool to offer the chip revision here - Jean II */
1594 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1595
527b6af4 1596 /*
1da177e4 1597 * Open new IrLAP layer instance, now that everything should be
527b6af4 1598 * initialized properly
1da177e4
LT		 1599 */
1600 self->irlap = irlap_open(dev, &self->qos, hwname);
1601
1602 /*
1603 * Always allocate the DMA channel after the IRQ,
1604 * and clean up on failure.
1605 */
1606 if (request_dma(self->io.dma, dev->name)) {
1607 smsc_ircc_net_close(dev);
1608
1609 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1610 __FUNCTION__, self->io.dma);
1611 return -EAGAIN;
1612 }
527b6af4 1613
1da177e4
LT		 1614 netif_start_queue(dev);
1615
1616 return 0;
1617}
1618
1619/*
1620 * Function smsc_ircc_net_close (dev)
1621 *
1622 * Stop the device
1623 *
1624 */
1625static int smsc_ircc_net_close(struct net_device *dev)
1626{
1627 struct smsc_ircc_cb *self;
1da177e4
LT		 1628
1629 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 1630
1da177e4 1631 IRDA_ASSERT(dev != NULL, return -1;);
da0841a0 1632 self = netdev_priv(dev);
1da177e4 1633 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1634
1da177e4
LT		 1635 /* Stop device */
1636 netif_stop_queue(dev);
527b6af4 1637
1da177e4
LT		 1638 /* Stop and remove instance of IrLAP */
1639 if (self->irlap)
1640 irlap_close(self->irlap);
1641 self->irlap = NULL;
1642
1643 free_irq(self->io.irq, dev);
1da177e4 1644 disable_dma(self->io.dma);
1da177e4
LT		 1645 free_dma(self->io.dma);
1646
1647 return 0;
1648}
1649
9480e307 1650static int smsc_ircc_suspend(struct device *dev, pm_message_t state)
1da177e4 1651{
6bb3b2cd
DT		 1652 struct smsc_ircc_cb *self = dev_get_drvdata(dev);
1653
1da177e4
LT		 1654 IRDA_MESSAGE("%s, Suspending\n", driver_name);
1655
9480e307 1656 if (!self->io.suspended) {
98b77773
DT		 1657 smsc_ircc_net_close(self->netdev);
1658 self->io.suspended = 1;
1659 }
6bb3b2cd
DT		 1660
1661 return 0;
1da177e4
LT		 1662}
1663
9480e307 1664static int smsc_ircc_resume(struct device *dev)
1da177e4 1665{
6bb3b2cd 1666 struct smsc_ircc_cb *self = dev_get_drvdata(dev);
1da177e4 1667
9480e307 1668 if (self->io.suspended) {
527b6af4 1669
6bb3b2cd
DT		 1670 smsc_ircc_net_open(self->netdev);
1671 self->io.suspended = 0;
1da177e4 1672
6bb3b2cd
DT		 1673 IRDA_MESSAGE("%s, Waking up\n", driver_name);
1674 }
1da177e4
LT		 1675 return 0;
1676}
1677
1678/*
1679 * Function smsc_ircc_close (self)
1680 *
1681 * Close driver instance
1682 *
1683 */
1684static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1685{
1686 int iobase;
1687 unsigned long flags;
1688
1689 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1690
1691 IRDA_ASSERT(self != NULL, return -1;);
1692
6bb3b2cd 1693 platform_device_unregister(self->pldev);
1da177e4
LT		 1694
1695 /* Remove netdevice */
1696 unregister_netdev(self->netdev);
1697
1698 /* Make sure the irq handler is not exectuting */
1699 spin_lock_irqsave(&self->lock, flags);
1700
1701 /* Stop interrupts */
6bb3b2cd 1702 iobase = self->io.fir_base;
1da177e4 1703 register_bank(iobase, 0);
98b77773
DT		 1704 outb(0, iobase + IRCC_IER);
1705 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1706 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 1707#if 0
1708 /* Reset to SIR mode */
1709 register_bank(iobase, 1);
98b77773
DT		 1710 outb(IRCC_CFGA_IRDA_SIR_A|IRCC_CFGA_TX_POLARITY, iobase + IRCC_SCE_CFGA);
1711 outb(IRCC_CFGB_IR, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1712#endif
1713 spin_unlock_irqrestore(&self->lock, flags);
1714
1715 /* Release the PORTS that this driver is using */
1716 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1717 self->io.fir_base);
1718
1719 release_region(self->io.fir_base, self->io.fir_ext);
1720
527b6af4 1721 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1da177e4
LT		 1722 self->io.sir_base);
1723
1724 release_region(self->io.sir_base, self->io.sir_ext);
1725
1726 if (self->tx_buff.head)
1727 dma_free_coherent(NULL, self->tx_buff.truesize,
1728 self->tx_buff.head, self->tx_buff_dma);
527b6af4 1729
1da177e4
LT		 1730 if (self->rx_buff.head)
1731 dma_free_coherent(NULL, self->rx_buff.truesize,
1732 self->rx_buff.head, self->rx_buff_dma);
1733
1734 free_netdev(self->netdev);
1735
1736 return 0;
1737}
1738
1739static void __exit smsc_ircc_cleanup(void)
1740{
1741 int i;
1742
1743 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1744
98b77773 1745 for (i = 0; i < 2; i++) {
1da177e4
LT		 1746 if (dev_self[i])
1747 smsc_ircc_close(dev_self[i]);
1748 }
6bb3b2cd
DT		 1749
1750 driver_unregister(&smsc_ircc_driver);
1da177e4
LT		 1751}
1752
1753/*
1754 * Start SIR operations
1755 *
1756 * This function *must* be called with spinlock held, because it may
1757 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1758 */
1759void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1760{
1761 struct net_device *dev;
1762 int fir_base, sir_base;
1763
1764 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1765
527b6af4 1766 IRDA_ASSERT(self != NULL, return;);
98b77773 1767 dev = self->netdev;
527b6af4 1768 IRDA_ASSERT(dev != NULL, return;);
1da177e4
LT		 1769 dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1770
1771 fir_base = self->io.fir_base;
1772 sir_base = self->io.sir_base;
1773
1774 /* Reset everything */
98b77773 1775 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1da177e4
LT		 1776
1777 #if SMSC_IRCC2_C_SIR_STOP
1778 /*smsc_ircc_sir_stop(self);*/
1779 #endif
1780
1781 register_bank(fir_base, 1);
98b77773 1782 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1da177e4
LT		 1783
1784 /* Initialize UART */
98b77773
DT		 1785 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1786 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
527b6af4 1787
1da177e4 1788 /* Turn on interrups */
98b77773 1789 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1da177e4
LT		 1790
1791 IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__);
1792
98b77773 1793 outb(0x00, fir_base + IRCC_MASTER);
1da177e4
LT		 1794}
1795
1796#if SMSC_IRCC2_C_SIR_STOP
1797void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1798{
1799 int iobase;
1800
1801 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1802 iobase = self->io.sir_base;
1803
1804 /* Reset UART */
98b77773 1805 outb(0, iobase + UART_MCR);
527b6af4 1806
1da177e4 1807 /* Turn off interrupts */
98b77773 1808 outb(0, iobase + UART_IER);
1da177e4
LT		 1809}
1810#endif
1811
1812/*
1813 * Function smsc_sir_write_wakeup (self)
1814 *
1815 * Called by the SIR interrupt handler when there's room for more data.
1816 * If we have more packets to send, we send them here.
1817 *
1818 */
1819static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1820{
1821 int actual = 0;
1822 int iobase;
1823 int fcr;
1824
1825 IRDA_ASSERT(self != NULL, return;);
1826
1827 IRDA_DEBUG(4, "%s\n", __FUNCTION__);
1828
1829 iobase = self->io.sir_base;
1830
1831 /* Finished with frame? */
1832 if (self->tx_buff.len > 0) {
1833 /* Write data left in transmit buffer */
527b6af4 1834 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1da177e4
LT		 1835 self->tx_buff.data, self->tx_buff.len);
1836 self->tx_buff.data += actual;
1837 self->tx_buff.len -= actual;
1838 } else {
527b6af4 1839
1da177e4 1840 /*if (self->tx_buff.len ==0) {*/
527b6af4
DT		 1841
1842 /*
1843 * Now serial buffer is almost free & we can start
1da177e4
LT		 1844 * transmission of another packet. But first we must check
1845 * if we need to change the speed of the hardware
1846 */
1847 if (self->new_speed) {
1848 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1849 __FUNCTION__, self->new_speed);
1850 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1851 smsc_ircc_change_speed(self, self->new_speed);
1852 self->new_speed = 0;
1853 } else {
1854 /* Tell network layer that we want more frames */
1855 netif_wake_queue(self->netdev);
1856 }
1857 self->stats.tx_packets++;
1858
98b77773
DT		 1859 if (self->io.speed <= 115200) {
1860 /*
1861 * Reset Rx FIFO to make sure that all reflected transmit data
1862 * is discarded. This is needed for half duplex operation
1863 */
1864 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
1865 fcr |= self->io.speed < 38400 ?
1866 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1da177e4 1867
98b77773 1868 outb(fcr, iobase + UART_FCR);
1da177e4 1869
98b77773
DT		 1870 /* Turn on receive interrupts */
1871 outb(UART_IER_RDI, iobase + UART_IER);
1da177e4
LT		 1872 }
1873 }
1874}
1875
1876/*
1877 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
1878 *
1879 * Fill Tx FIFO with transmit data
1880 *
1881 */
1882static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1883{
1884 int actual = 0;
527b6af4 1885
1da177e4 1886 /* Tx FIFO should be empty! */
98b77773 1887 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
1da177e4
LT		 1888 IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__);
1889 return 0;
1890 }
527b6af4 1891
1da177e4 1892 /* Fill FIFO with current frame */
98b77773 1893 while (fifo_size-- > 0 && actual < len) {
1da177e4 1894 /* Transmit next byte */
98b77773 1895 outb(buf[actual], iobase + UART_TX);
1da177e4
LT		 1896 actual++;
1897 }
1898 return actual;
1899}
1900
1901/*
1902 * Function smsc_ircc_is_receiving (self)
1903 *
1904 * Returns true is we are currently receiving data
1905 *
1906 */
1907static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
1908{
1909 return (self->rx_buff.state != OUTSIDE_FRAME);
1910}
1911
1912
1913/*
1914 * Function smsc_ircc_probe_transceiver(self)
1915 *
1916 * Tries to find the used Transceiver
1917 *
1918 */
1919static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
1920{
1921 unsigned int i;
527b6af4 1922
1da177e4 1923 IRDA_ASSERT(self != NULL, return;);
527b6af4 1924
98b77773
DT		 1925 for (i = 0; smsc_transceivers[i].name != NULL; i++)
1926 if (smsc_transceivers[i].probe(self->io.fir_base)) {
1da177e4
LT		 1927 IRDA_MESSAGE(" %s transceiver found\n",
1928 smsc_transceivers[i].name);
98b77773 1929 self->transceiver= i + 1;
1da177e4
LT		 1930 return;
1931 }
98b77773 1932
1da177e4
LT		 1933 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
1934 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
527b6af4 1935
98b77773 1936 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
1da177e4
LT		 1937}
1938
1939
1940/*
1941 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
1942 *
1943 * Set the transceiver according to the speed
1944 *
1945 */
1946static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
1947{
1948 unsigned int trx;
527b6af4 1949
1da177e4 1950 trx = self->transceiver;
98b77773
DT		 1951 if (trx > 0)
1952 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
1da177e4
LT		 1953}
1954
1955/*
1956 * Function smsc_ircc_wait_hw_transmitter_finish ()
1957 *
1958 * Wait for the real end of HW transmission
1959 *
1960 * The UART is a strict FIFO, and we get called only when we have finished
1961 * pushing data to the FIFO, so the maximum amount of time we must wait
1962 * is only for the FIFO to drain out.
1963 *
1964 * We use a simple calibrated loop. We may need to adjust the loop
1965 * delay (udelay) to balance I/O traffic and latency. And we also need to
1966 * adjust the maximum timeout.
1967 * It would probably be better to wait for the proper interrupt,
1968 * but it doesn't seem to be available.
1969 *
1970 * We can't use jiffies or kernel timers because :
1971 * 1) We are called from the interrupt handler, which disable softirqs,
1972 * so jiffies won't be increased
1973 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
1974 * want to wait that long to detect stuck hardware.
1975 * Jean II
1976 */
1977
1978static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
1979{
98b77773 1980 int iobase = self->io.sir_base;
1da177e4 1981 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
527b6af4 1982
1da177e4 1983 /* Calibrated busy loop */
98b77773 1984 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
1da177e4
LT		 1985 udelay(1);
1986
98b77773 1987 if (count == 0)
1da177e4
LT		 1988 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__);
1989}
1990
1991
1992/* PROBING
1993 *
1994 *
1995 */
1996
1997static int __init smsc_ircc_look_for_chips(void)
1998{
b6158d23 1999 struct smsc_chip_address *address;
98b77773 2000 char *type;
1da177e4 2001 unsigned int cfg_base, found;
527b6af4 2002
1da177e4
LT		 2003 found = 0;
2004 address = possible_addresses;
527b6af4 2005
98b77773 2006 while (address->cfg_base) {
1da177e4 2007 cfg_base = address->cfg_base;
527b6af4 2008
1da177e4 2009 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/
527b6af4 2010
98b77773 2011 if (address->type & SMSCSIO_TYPE_FDC) {
1da177e4 2012 type = "FDC";
98b77773
DT		 2013 if (address->type & SMSCSIO_TYPE_FLAT)
2014 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2015 found++;
2016
2017 if (address->type & SMSCSIO_TYPE_PAGED)
2018 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2019 found++;
1da177e4 2020 }
98b77773 2021 if (address->type & SMSCSIO_TYPE_LPC) {
1da177e4 2022 type = "LPC";
98b77773
DT		 2023 if (address->type & SMSCSIO_TYPE_FLAT)
2024 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2025 found++;
2026
2027 if (address->type & SMSCSIO_TYPE_PAGED)
2028 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2029 found++;
1da177e4
LT		 2030 }
2031 address++;
2032 }
2033 return found;
527b6af4 2034}
1da177e4
LT		 2035
2036/*
2037 * Function smsc_superio_flat (chip, base, type)
2038 *
2039 * Try to get configuration of a smc SuperIO chip with flat register model
2040 *
2041 */
b6158d23 2042static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
1da177e4
LT		 2043{
2044 unsigned short firbase, sirbase;
2045 u8 mode, dma, irq;
2046 int ret = -ENODEV;
2047
2048 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2049
98b77773 2050 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
1da177e4
LT		 2051 return ret;
2052
2053 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
98b77773 2054 mode = inb(cfgbase + 1);
527b6af4 2055
1da177e4 2056 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/
527b6af4 2057
98b77773 2058 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
1da177e4
LT		 2059 IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__);
2060
2061 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
98b77773 2062 sirbase = inb(cfgbase + 1) << 2;
1da177e4 2063
527b6af4 2064 /* FIR iobase */
1da177e4 2065 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
98b77773 2066 firbase = inb(cfgbase + 1) << 3;
1da177e4
LT		 2067
2068 /* DMA */
2069 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
98b77773 2070 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
527b6af4 2071
1da177e4
LT		 2072 /* IRQ */
2073 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
98b77773 2074 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
1da177e4
LT		 2075
2076 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode);
2077
98b77773
DT		 2078 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2079 ret = 0;
527b6af4 2080
1da177e4
LT		 2081 /* Exit configuration */
2082 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2083
2084 return ret;
2085}
2086
2087/*
2088 * Function smsc_superio_paged (chip, base, type)
2089 *
2090 * Try to get configuration of a smc SuperIO chip with paged register model
2091 *
2092 */
b6158d23 2093static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
1da177e4
LT		 2094{
2095 unsigned short fir_io, sir_io;
2096 int ret = -ENODEV;
527b6af4 2097
1da177e4
LT		 2098 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2099
98b77773 2100 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
1da177e4 2101 return ret;
527b6af4 2102
1da177e4
LT		 2103 /* Select logical device (UART2) */
2104 outb(0x07, cfg_base);
2105 outb(0x05, cfg_base + 1);
527b6af4 2106
1da177e4
LT		 2107 /* SIR iobase */
2108 outb(0x60, cfg_base);
98b77773 2109 sir_io = inb(cfg_base + 1) << 8;
1da177e4
LT		 2110 outb(0x61, cfg_base);
2111 sir_io |= inb(cfg_base + 1);
527b6af4 2112
1da177e4
LT		 2113 /* Read FIR base */
2114 outb(0x62, cfg_base);
2115 fir_io = inb(cfg_base + 1) << 8;
2116 outb(0x63, cfg_base);
2117 fir_io |= inb(cfg_base + 1);
2118 outb(0x2b, cfg_base); /* ??? */
2119
98b77773
DT		 2120 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2121 ret = 0;
527b6af4 2122
1da177e4
LT		 2123 /* Exit configuration */
2124 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2125
2126 return ret;
2127}
2128
2129
98b77773 2130static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
1da177e4
LT		 2131{
2132 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2133
2134 outb(reg, cfg_base);
98b77773 2135 return inb(cfg_base) != reg ? -1 : 0;
1da177e4
LT		 2136}
2137
b6158d23 2138static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
1da177e4 2139{
98b77773 2140 u8 devid, xdevid, rev;
1da177e4
LT		 2141
2142 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2143
2144 /* Leave configuration */
2145
2146 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2147
2148 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2149 return NULL;
2150
2151 outb(reg, cfg_base);
2152
98b77773 2153 xdevid = inb(cfg_base + 1);
1da177e4
LT		 2154
2155 /* Enter configuration */
2156
2157 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2158
2159 #if 0
2160 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2161 return NULL;
2162 #endif
527b6af4 2163
1da177e4
LT		 2164 /* probe device ID */
2165
98b77773 2166 if (smsc_access(cfg_base, reg))
1da177e4
LT		 2167 return NULL;
2168
98b77773 2169 devid = inb(cfg_base + 1);
527b6af4 2170
98b77773 2171 if (devid == 0 || devid == 0xff) /* typical values for unused port */
1da177e4
LT		 2172 return NULL;
2173
2174 /* probe revision ID */
2175
98b77773 2176 if (smsc_access(cfg_base, reg + 1))
1da177e4
LT		 2177 return NULL;
2178
98b77773 2179 rev = inb(cfg_base + 1);
1da177e4 2180
98b77773 2181 if (rev >= 128) /* i think this will make no sense */
1da177e4
LT		 2182 return NULL;
2183
98b77773 2184 if (devid == xdevid) /* protection against false positives */
1da177e4
LT		 2185 return NULL;
2186
2187 /* Check for expected device ID; are there others? */
2188
98b77773 2189 while (chip->devid != devid) {
1da177e4
LT		 2190
2191 chip++;
2192
98b77773 2193 if (chip->name == NULL)
1da177e4
LT		 2194 return NULL;
2195 }
2196
98b77773
DT		 2197 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2198 devid, rev, cfg_base, type, chip->name);
1da177e4 2199
98b77773 2200 if (chip->rev > rev) {
527b6af4 2201 IRDA_MESSAGE("Revision higher than expected\n");
1da177e4
LT		 2202 return NULL;
2203 }
527b6af4 2204
98b77773 2205 if (chip->flags & NoIRDA)
1da177e4
LT		 2206 IRDA_MESSAGE("chipset does not support IRDA\n");
2207
2208 return chip;
2209}
2210
2211static int __init smsc_superio_fdc(unsigned short cfg_base)
2212{
2213 int ret = -1;
2214
2215 if (!request_region(cfg_base, 2, driver_name)) {
2216 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2217 __FUNCTION__, cfg_base);
2218 } else {
98b77773
DT		 2219 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2220 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
1da177e4
LT		 2221 ret = 0;
2222
2223 release_region(cfg_base, 2);
2224 }
2225
2226 return ret;
2227}
2228
2229static int __init smsc_superio_lpc(unsigned short cfg_base)
2230{
2231 int ret = -1;
2232
2233 if (!request_region(cfg_base, 2, driver_name)) {
2234 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2235 __FUNCTION__, cfg_base);
2236 } else {
98b77773
DT		 2237 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2238 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
1da177e4 2239 ret = 0;
98b77773 2240
1da177e4
LT		 2241 release_region(cfg_base, 2);
2242 }
2243 return ret;
2244}
2245
2246/************************************************
2247 *
2248 * Transceivers specific functions
2249 *
2250 ************************************************/
2251
2252
2253/*
2254 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2255 *
2256 * Program transceiver through smsc-ircc ATC circuitry
2257 *
2258 */
2259
2260static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2261{
2262 unsigned long jiffies_now, jiffies_timeout;
98b77773 2263 u8 val;
527b6af4 2264
98b77773
DT		 2265 jiffies_now = jiffies;
2266 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
527b6af4 2267
1da177e4
LT		 2268 /* ATC */
2269 register_bank(fir_base, 4);
98b77773
DT		 2270 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2271 fir_base + IRCC_ATC);
2272
2273 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2274 !time_after(jiffies, jiffies_timeout))
2275 /* empty */;
2276
2277 if (val)
1da177e4 2278 IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__,
98b77773 2279 inb(fir_base + IRCC_ATC));
1da177e4
LT		 2280}
2281
2282/*
2283 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2284 *
2285 * Probe transceiver smsc-ircc ATC circuitry
2286 *
2287 */
2288
2289static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2290{
2291 return 0;
2292}
2293
2294/*
2295 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2296 *
527b6af4 2297 * Set transceiver
1da177e4
LT		 2298 *
2299 */
2300
2301static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2302{
98b77773 2303 u8 fast_mode;
527b6af4 2304
98b77773
DT		 2305 switch (speed) {
2306 default:
2307 case 576000 :
527b6af4 2308 fast_mode = 0;
1da177e4 2309 break;
98b77773
DT		 2310 case 1152000 :
2311 case 4000000 :
1da177e4
LT		 2312 fast_mode = IRCC_LCR_A_FAST;
2313 break;
1da177e4
LT		 2314 }
2315 register_bank(fir_base, 0);
98b77773 2316 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 2317}
2318
2319/*
2320 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2321 *
527b6af4 2322 * Probe transceiver
1da177e4
LT		 2323 *
2324 */
2325
2326static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2327{
2328 return 0;
2329}
2330
2331/*
2332 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2333 *
527b6af4 2334 * Set transceiver
1da177e4
LT		 2335 *
2336 */
2337
2338static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2339{
98b77773 2340 u8 fast_mode;
527b6af4 2341
98b77773
DT		 2342 switch (speed) {
2343 default:
2344 case 576000 :
527b6af4 2345 fast_mode = 0;
1da177e4 2346 break;
98b77773
DT		 2347 case 1152000 :
2348 case 4000000 :
1da177e4
LT		 2349 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
2350 break;
527b6af4 2351
1da177e4
LT		 2352 }
2353 /* This causes an interrupt */
2354 register_bank(fir_base, 0);
98b77773 2355 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 2356}
2357
2358/*
2359 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
2360 *
527b6af4 2361 * Probe transceiver
1da177e4
LT		 2362 *
2363 */
2364
2365static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
2366{
2367 return 0;
2368}
2369
2370
2371module_init(smsc_ircc_init);
2372module_exit(smsc_ircc_cleanup);
Linux kernel - Deliverables
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