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1da177e4 LT |
1 | /********************************************************************* |
2 | * | |
3 | * Filename: w83977af_ir.c | |
4 | * Version: 1.0 | |
5 | * Description: FIR driver for the Winbond W83977AF Super I/O chip | |
6 | * Status: Experimental. | |
7 | * Author: Paul VanderSpek | |
8 | * Created at: Wed Nov 4 11:46:16 1998 | |
9 | * Modified at: Fri Jan 28 12:10:59 2000 | |
10 | * Modified by: Dag Brattli <dagb@cs.uit.no> | |
11 | * | |
12 | * Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no> | |
13 | * Copyright (c) 1998-1999 Rebel.com | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of | |
18 | * the License, or (at your option) any later version. | |
19 | * | |
20 | * Neither Paul VanderSpek nor Rebel.com admit liability nor provide | |
21 | * warranty for any of this software. This material is provided "AS-IS" | |
22 | * and at no charge. | |
23 | * | |
24 | * If you find bugs in this file, its very likely that the same bug | |
25 | * will also be in pc87108.c since the implementations are quite | |
26 | * similar. | |
27 | * | |
28 | * Notice that all functions that needs to access the chip in _any_ | |
29 | * way, must save BSR register on entry, and restore it on exit. | |
30 | * It is _very_ important to follow this policy! | |
31 | * | |
32 | * __u8 bank; | |
33 | * | |
34 | * bank = inb( iobase+BSR); | |
35 | * | |
36 | * do_your_stuff_here(); | |
37 | * | |
38 | * outb( bank, iobase+BSR); | |
39 | * | |
40 | ********************************************************************/ | |
41 | ||
42 | #include <linux/module.h> | |
1da177e4 LT |
43 | #include <linux/kernel.h> |
44 | #include <linux/types.h> | |
45 | #include <linux/skbuff.h> | |
46 | #include <linux/netdevice.h> | |
47 | #include <linux/ioport.h> | |
48 | #include <linux/delay.h> | |
49 | #include <linux/slab.h> | |
50 | #include <linux/init.h> | |
51 | #include <linux/rtnetlink.h> | |
52 | #include <linux/dma-mapping.h> | |
53 | ||
54 | #include <asm/io.h> | |
55 | #include <asm/dma.h> | |
56 | #include <asm/byteorder.h> | |
57 | ||
58 | #include <net/irda/irda.h> | |
59 | #include <net/irda/wrapper.h> | |
60 | #include <net/irda/irda_device.h> | |
61 | #include "w83977af.h" | |
62 | #include "w83977af_ir.h" | |
63 | ||
64 | #ifdef CONFIG_ARCH_NETWINDER /* Adjust to NetWinder differences */ | |
65 | #undef CONFIG_NETWINDER_TX_DMA_PROBLEMS /* Not needed */ | |
66 | #define CONFIG_NETWINDER_RX_DMA_PROBLEMS /* Must have this one! */ | |
67 | #endif | |
68 | #undef CONFIG_USE_INTERNAL_TIMER /* Just cannot make that timer work */ | |
69 | #define CONFIG_USE_W977_PNP /* Currently needed */ | |
70 | #define PIO_MAX_SPEED 115200 | |
71 | ||
72 | static char *driver_name = "w83977af_ir"; | |
73 | static int qos_mtt_bits = 0x07; /* 1 ms or more */ | |
74 | ||
75 | #define CHIP_IO_EXTENT 8 | |
76 | ||
77 | static unsigned int io[] = { 0x180, ~0, ~0, ~0 }; | |
78 | #ifdef CONFIG_ARCH_NETWINDER /* Adjust to NetWinder differences */ | |
79 | static unsigned int irq[] = { 6, 0, 0, 0 }; | |
80 | #else | |
81 | static unsigned int irq[] = { 11, 0, 0, 0 }; | |
82 | #endif | |
83 | static unsigned int dma[] = { 1, 0, 0, 0 }; | |
84 | static unsigned int efbase[] = { W977_EFIO_BASE, W977_EFIO2_BASE }; | |
85 | static unsigned int efio = W977_EFIO_BASE; | |
86 | ||
87 | static struct w83977af_ir *dev_self[] = { NULL, NULL, NULL, NULL}; | |
88 | ||
89 | /* Some prototypes */ | |
90 | static int w83977af_open(int i, unsigned int iobase, unsigned int irq, | |
91 | unsigned int dma); | |
92 | static int w83977af_close(struct w83977af_ir *self); | |
93 | static int w83977af_probe(int iobase, int irq, int dma); | |
94 | static int w83977af_dma_receive(struct w83977af_ir *self); | |
95 | static int w83977af_dma_receive_complete(struct w83977af_ir *self); | |
96 | static int w83977af_hard_xmit(struct sk_buff *skb, struct net_device *dev); | |
97 | static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size); | |
98 | static void w83977af_dma_write(struct w83977af_ir *self, int iobase); | |
99 | static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed); | |
100 | static int w83977af_is_receiving(struct w83977af_ir *self); | |
101 | ||
102 | static int w83977af_net_open(struct net_device *dev); | |
103 | static int w83977af_net_close(struct net_device *dev); | |
104 | static int w83977af_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
1da177e4 LT |
105 | |
106 | /* | |
107 | * Function w83977af_init () | |
108 | * | |
109 | * Initialize chip. Just try to find out how many chips we are dealing with | |
110 | * and where they are | |
111 | */ | |
112 | static int __init w83977af_init(void) | |
113 | { | |
114 | int i; | |
115 | ||
a97a6f10 | 116 | IRDA_DEBUG(0, "%s()\n", __func__ ); |
1da177e4 | 117 | |
9c3bd683 | 118 | for (i=0; (io[i] < 2000) && (i < ARRAY_SIZE(dev_self)); i++) { |
1da177e4 LT |
119 | if (w83977af_open(i, io[i], irq[i], dma[i]) == 0) |
120 | return 0; | |
121 | } | |
122 | return -ENODEV; | |
123 | } | |
124 | ||
125 | /* | |
126 | * Function w83977af_cleanup () | |
127 | * | |
128 | * Close all configured chips | |
129 | * | |
130 | */ | |
131 | static void __exit w83977af_cleanup(void) | |
132 | { | |
133 | int i; | |
134 | ||
a97a6f10 | 135 | IRDA_DEBUG(4, "%s()\n", __func__ ); |
1da177e4 | 136 | |
9c3bd683 | 137 | for (i=0; i < ARRAY_SIZE(dev_self); i++) { |
1da177e4 LT |
138 | if (dev_self[i]) |
139 | w83977af_close(dev_self[i]); | |
140 | } | |
141 | } | |
142 | ||
4113a1a6 SH |
143 | static const struct net_device_ops w83977_netdev_ops = { |
144 | .ndo_open = w83977af_net_open, | |
145 | .ndo_stop = w83977af_net_close, | |
146 | .ndo_start_xmit = w83977af_hard_xmit, | |
147 | .ndo_do_ioctl = w83977af_net_ioctl, | |
148 | }; | |
149 | ||
1da177e4 LT |
150 | /* |
151 | * Function w83977af_open (iobase, irq) | |
152 | * | |
153 | * Open driver instance | |
154 | * | |
155 | */ | |
0e49e645 HE |
156 | static int w83977af_open(int i, unsigned int iobase, unsigned int irq, |
157 | unsigned int dma) | |
1da177e4 LT |
158 | { |
159 | struct net_device *dev; | |
160 | struct w83977af_ir *self; | |
161 | int err; | |
162 | ||
a97a6f10 | 163 | IRDA_DEBUG(0, "%s()\n", __func__ ); |
1da177e4 LT |
164 | |
165 | /* Lock the port that we need */ | |
166 | if (!request_region(iobase, CHIP_IO_EXTENT, driver_name)) { | |
167 | IRDA_DEBUG(0, "%s(), can't get iobase of 0x%03x\n", | |
a97a6f10 | 168 | __func__ , iobase); |
1da177e4 LT |
169 | return -ENODEV; |
170 | } | |
171 | ||
172 | if (w83977af_probe(iobase, irq, dma) == -1) { | |
173 | err = -1; | |
174 | goto err_out; | |
175 | } | |
176 | /* | |
177 | * Allocate new instance of the driver | |
178 | */ | |
179 | dev = alloc_irdadev(sizeof(struct w83977af_ir)); | |
180 | if (dev == NULL) { | |
181 | printk( KERN_ERR "IrDA: Can't allocate memory for " | |
182 | "IrDA control block!\n"); | |
183 | err = -ENOMEM; | |
184 | goto err_out; | |
185 | } | |
186 | ||
4cf1653a | 187 | self = netdev_priv(dev); |
1da177e4 LT |
188 | spin_lock_init(&self->lock); |
189 | ||
190 | ||
191 | /* Initialize IO */ | |
192 | self->io.fir_base = iobase; | |
193 | self->io.irq = irq; | |
194 | self->io.fir_ext = CHIP_IO_EXTENT; | |
195 | self->io.dma = dma; | |
196 | self->io.fifo_size = 32; | |
197 | ||
198 | /* Initialize QoS for this device */ | |
199 | irda_init_max_qos_capabilies(&self->qos); | |
200 | ||
201 | /* The only value we must override it the baudrate */ | |
202 | ||
203 | /* FIXME: The HP HDLS-1100 does not support 1152000! */ | |
204 | self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600| | |
205 | IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8); | |
206 | ||
207 | /* The HP HDLS-1100 needs 1 ms according to the specs */ | |
208 | self->qos.min_turn_time.bits = qos_mtt_bits; | |
209 | irda_qos_bits_to_value(&self->qos); | |
210 | ||
211 | /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */ | |
212 | self->rx_buff.truesize = 14384; | |
213 | self->tx_buff.truesize = 4000; | |
214 | ||
215 | /* Allocate memory if needed */ | |
216 | self->rx_buff.head = | |
217 | dma_alloc_coherent(NULL, self->rx_buff.truesize, | |
218 | &self->rx_buff_dma, GFP_KERNEL); | |
219 | if (self->rx_buff.head == NULL) { | |
220 | err = -ENOMEM; | |
221 | goto err_out1; | |
222 | } | |
223 | ||
224 | memset(self->rx_buff.head, 0, self->rx_buff.truesize); | |
225 | ||
226 | self->tx_buff.head = | |
227 | dma_alloc_coherent(NULL, self->tx_buff.truesize, | |
228 | &self->tx_buff_dma, GFP_KERNEL); | |
229 | if (self->tx_buff.head == NULL) { | |
230 | err = -ENOMEM; | |
231 | goto err_out2; | |
232 | } | |
233 | memset(self->tx_buff.head, 0, self->tx_buff.truesize); | |
234 | ||
235 | self->rx_buff.in_frame = FALSE; | |
236 | self->rx_buff.state = OUTSIDE_FRAME; | |
237 | self->tx_buff.data = self->tx_buff.head; | |
238 | self->rx_buff.data = self->rx_buff.head; | |
239 | self->netdev = dev; | |
240 | ||
4113a1a6 | 241 | dev->netdev_ops = &w83977_netdev_ops; |
1da177e4 LT |
242 | |
243 | err = register_netdev(dev); | |
244 | if (err) { | |
a97a6f10 | 245 | IRDA_ERROR("%s(), register_netdevice() failed!\n", __func__); |
1da177e4 LT |
246 | goto err_out3; |
247 | } | |
248 | IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name); | |
249 | ||
250 | /* Need to store self somewhere */ | |
251 | dev_self[i] = self; | |
252 | ||
253 | return 0; | |
254 | err_out3: | |
255 | dma_free_coherent(NULL, self->tx_buff.truesize, | |
256 | self->tx_buff.head, self->tx_buff_dma); | |
257 | err_out2: | |
258 | dma_free_coherent(NULL, self->rx_buff.truesize, | |
259 | self->rx_buff.head, self->rx_buff_dma); | |
260 | err_out1: | |
261 | free_netdev(dev); | |
262 | err_out: | |
263 | release_region(iobase, CHIP_IO_EXTENT); | |
264 | return err; | |
265 | } | |
266 | ||
267 | /* | |
268 | * Function w83977af_close (self) | |
269 | * | |
270 | * Close driver instance | |
271 | * | |
272 | */ | |
273 | static int w83977af_close(struct w83977af_ir *self) | |
274 | { | |
275 | int iobase; | |
276 | ||
a97a6f10 | 277 | IRDA_DEBUG(0, "%s()\n", __func__ ); |
1da177e4 LT |
278 | |
279 | iobase = self->io.fir_base; | |
280 | ||
281 | #ifdef CONFIG_USE_W977_PNP | |
282 | /* enter PnP configuration mode */ | |
283 | w977_efm_enter(efio); | |
284 | ||
285 | w977_select_device(W977_DEVICE_IR, efio); | |
286 | ||
287 | /* Deactivate device */ | |
288 | w977_write_reg(0x30, 0x00, efio); | |
289 | ||
290 | w977_efm_exit(efio); | |
291 | #endif /* CONFIG_USE_W977_PNP */ | |
292 | ||
293 | /* Remove netdevice */ | |
294 | unregister_netdev(self->netdev); | |
295 | ||
296 | /* Release the PORT that this driver is using */ | |
297 | IRDA_DEBUG(0 , "%s(), Releasing Region %03x\n", | |
a97a6f10 | 298 | __func__ , self->io.fir_base); |
1da177e4 LT |
299 | release_region(self->io.fir_base, self->io.fir_ext); |
300 | ||
301 | if (self->tx_buff.head) | |
302 | dma_free_coherent(NULL, self->tx_buff.truesize, | |
303 | self->tx_buff.head, self->tx_buff_dma); | |
304 | ||
305 | if (self->rx_buff.head) | |
306 | dma_free_coherent(NULL, self->rx_buff.truesize, | |
307 | self->rx_buff.head, self->rx_buff_dma); | |
308 | ||
309 | free_netdev(self->netdev); | |
310 | ||
311 | return 0; | |
312 | } | |
313 | ||
0e49e645 | 314 | static int w83977af_probe(int iobase, int irq, int dma) |
1da177e4 LT |
315 | { |
316 | int version; | |
317 | int i; | |
318 | ||
319 | for (i=0; i < 2; i++) { | |
a97a6f10 | 320 | IRDA_DEBUG( 0, "%s()\n", __func__ ); |
1da177e4 LT |
321 | #ifdef CONFIG_USE_W977_PNP |
322 | /* Enter PnP configuration mode */ | |
323 | w977_efm_enter(efbase[i]); | |
324 | ||
325 | w977_select_device(W977_DEVICE_IR, efbase[i]); | |
326 | ||
327 | /* Configure PnP port, IRQ, and DMA channel */ | |
328 | w977_write_reg(0x60, (iobase >> 8) & 0xff, efbase[i]); | |
329 | w977_write_reg(0x61, (iobase) & 0xff, efbase[i]); | |
330 | ||
331 | w977_write_reg(0x70, irq, efbase[i]); | |
332 | #ifdef CONFIG_ARCH_NETWINDER | |
333 | /* Netwinder uses 1 higher than Linux */ | |
334 | w977_write_reg(0x74, dma+1, efbase[i]); | |
335 | #else | |
336 | w977_write_reg(0x74, dma, efbase[i]); | |
337 | #endif /*CONFIG_ARCH_NETWINDER */ | |
338 | w977_write_reg(0x75, 0x04, efbase[i]); /* Disable Tx DMA */ | |
339 | ||
340 | /* Set append hardware CRC, enable IR bank selection */ | |
341 | w977_write_reg(0xf0, APEDCRC|ENBNKSEL, efbase[i]); | |
342 | ||
343 | /* Activate device */ | |
344 | w977_write_reg(0x30, 0x01, efbase[i]); | |
345 | ||
346 | w977_efm_exit(efbase[i]); | |
347 | #endif /* CONFIG_USE_W977_PNP */ | |
348 | /* Disable Advanced mode */ | |
349 | switch_bank(iobase, SET2); | |
350 | outb(iobase+2, 0x00); | |
351 | ||
352 | /* Turn on UART (global) interrupts */ | |
353 | switch_bank(iobase, SET0); | |
354 | outb(HCR_EN_IRQ, iobase+HCR); | |
355 | ||
356 | /* Switch to advanced mode */ | |
357 | switch_bank(iobase, SET2); | |
358 | outb(inb(iobase+ADCR1) | ADCR1_ADV_SL, iobase+ADCR1); | |
359 | ||
360 | /* Set default IR-mode */ | |
361 | switch_bank(iobase, SET0); | |
362 | outb(HCR_SIR, iobase+HCR); | |
363 | ||
364 | /* Read the Advanced IR ID */ | |
365 | switch_bank(iobase, SET3); | |
366 | version = inb(iobase+AUID); | |
367 | ||
368 | /* Should be 0x1? */ | |
369 | if (0x10 == (version & 0xf0)) { | |
370 | efio = efbase[i]; | |
371 | ||
372 | /* Set FIFO size to 32 */ | |
373 | switch_bank(iobase, SET2); | |
374 | outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2); | |
375 | ||
376 | /* Set FIFO threshold to TX17, RX16 */ | |
377 | switch_bank(iobase, SET0); | |
378 | outb(UFR_RXTL|UFR_TXTL|UFR_TXF_RST|UFR_RXF_RST| | |
379 | UFR_EN_FIFO,iobase+UFR); | |
380 | ||
381 | /* Receiver frame length */ | |
382 | switch_bank(iobase, SET4); | |
383 | outb(2048 & 0xff, iobase+6); | |
384 | outb((2048 >> 8) & 0x1f, iobase+7); | |
385 | ||
386 | /* | |
387 | * Init HP HSDL-1100 transceiver. | |
388 | * | |
389 | * Set IRX_MSL since we have 2 * receive paths IRRX, | |
390 | * and IRRXH. Clear IRSL0D since we want IRSL0 * to | |
391 | * be a input pin used for IRRXH | |
392 | * | |
393 | * IRRX pin 37 connected to receiver | |
394 | * IRTX pin 38 connected to transmitter | |
395 | * FIRRX pin 39 connected to receiver (IRSL0) | |
396 | * CIRRX pin 40 connected to pin 37 | |
397 | */ | |
398 | switch_bank(iobase, SET7); | |
399 | outb(0x40, iobase+7); | |
400 | ||
401 | IRDA_MESSAGE("W83977AF (IR) driver loaded. " | |
402 | "Version: 0x%02x\n", version); | |
403 | ||
404 | return 0; | |
405 | } else { | |
406 | /* Try next extented function register address */ | |
a97a6f10 | 407 | IRDA_DEBUG( 0, "%s(), Wrong chip version", __func__ ); |
1da177e4 LT |
408 | } |
409 | } | |
410 | return -1; | |
411 | } | |
412 | ||
0e49e645 | 413 | static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed) |
1da177e4 LT |
414 | { |
415 | int ir_mode = HCR_SIR; | |
416 | int iobase; | |
417 | __u8 set; | |
418 | ||
419 | iobase = self->io.fir_base; | |
420 | ||
421 | /* Update accounting for new speed */ | |
422 | self->io.speed = speed; | |
423 | ||
424 | /* Save current bank */ | |
425 | set = inb(iobase+SSR); | |
426 | ||
427 | /* Disable interrupts */ | |
428 | switch_bank(iobase, SET0); | |
429 | outb(0, iobase+ICR); | |
430 | ||
431 | /* Select Set 2 */ | |
432 | switch_bank(iobase, SET2); | |
433 | outb(0x00, iobase+ABHL); | |
434 | ||
435 | switch (speed) { | |
436 | case 9600: outb(0x0c, iobase+ABLL); break; | |
437 | case 19200: outb(0x06, iobase+ABLL); break; | |
438 | case 38400: outb(0x03, iobase+ABLL); break; | |
439 | case 57600: outb(0x02, iobase+ABLL); break; | |
440 | case 115200: outb(0x01, iobase+ABLL); break; | |
441 | case 576000: | |
442 | ir_mode = HCR_MIR_576; | |
a97a6f10 | 443 | IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__ ); |
1da177e4 LT |
444 | break; |
445 | case 1152000: | |
446 | ir_mode = HCR_MIR_1152; | |
a97a6f10 | 447 | IRDA_DEBUG(0, "%s(), handling baud of 1152000\n", __func__ ); |
1da177e4 LT |
448 | break; |
449 | case 4000000: | |
450 | ir_mode = HCR_FIR; | |
a97a6f10 | 451 | IRDA_DEBUG(0, "%s(), handling baud of 4000000\n", __func__ ); |
1da177e4 LT |
452 | break; |
453 | default: | |
454 | ir_mode = HCR_FIR; | |
a97a6f10 | 455 | IRDA_DEBUG(0, "%s(), unknown baud rate of %d\n", __func__ , speed); |
1da177e4 LT |
456 | break; |
457 | } | |
458 | ||
459 | /* Set speed mode */ | |
460 | switch_bank(iobase, SET0); | |
461 | outb(ir_mode, iobase+HCR); | |
462 | ||
463 | /* set FIFO size to 32 */ | |
464 | switch_bank(iobase, SET2); | |
465 | outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2); | |
466 | ||
467 | /* set FIFO threshold to TX17, RX16 */ | |
468 | switch_bank(iobase, SET0); | |
469 | outb(0x00, iobase+UFR); /* Reset */ | |
470 | outb(UFR_EN_FIFO, iobase+UFR); /* First we must enable FIFO */ | |
471 | outb(0xa7, iobase+UFR); | |
472 | ||
473 | netif_wake_queue(self->netdev); | |
474 | ||
475 | /* Enable some interrupts so we can receive frames */ | |
476 | switch_bank(iobase, SET0); | |
477 | if (speed > PIO_MAX_SPEED) { | |
478 | outb(ICR_EFSFI, iobase+ICR); | |
479 | w83977af_dma_receive(self); | |
480 | } else | |
481 | outb(ICR_ERBRI, iobase+ICR); | |
482 | ||
483 | /* Restore SSR */ | |
484 | outb(set, iobase+SSR); | |
485 | } | |
486 | ||
487 | /* | |
488 | * Function w83977af_hard_xmit (skb, dev) | |
489 | * | |
490 | * Sets up a DMA transfer to send the current frame. | |
491 | * | |
492 | */ | |
0e49e645 | 493 | static int w83977af_hard_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 LT |
494 | { |
495 | struct w83977af_ir *self; | |
496 | __s32 speed; | |
497 | int iobase; | |
498 | __u8 set; | |
499 | int mtt; | |
500 | ||
4cf1653a | 501 | self = netdev_priv(dev); |
1da177e4 LT |
502 | |
503 | iobase = self->io.fir_base; | |
504 | ||
a97a6f10 | 505 | IRDA_DEBUG(4, "%s(%ld), skb->len=%d\n", __func__ , jiffies, |
1da177e4 LT |
506 | (int) skb->len); |
507 | ||
508 | /* Lock transmit buffer */ | |
509 | netif_stop_queue(dev); | |
510 | ||
511 | /* Check if we need to change the speed */ | |
512 | speed = irda_get_next_speed(skb); | |
513 | if ((speed != self->io.speed) && (speed != -1)) { | |
514 | /* Check for empty frame */ | |
515 | if (!skb->len) { | |
516 | w83977af_change_speed(self, speed); | |
517 | dev->trans_start = jiffies; | |
518 | dev_kfree_skb(skb); | |
519 | return 0; | |
520 | } else | |
521 | self->new_speed = speed; | |
522 | } | |
523 | ||
524 | /* Save current set */ | |
525 | set = inb(iobase+SSR); | |
526 | ||
527 | /* Decide if we should use PIO or DMA transfer */ | |
528 | if (self->io.speed > PIO_MAX_SPEED) { | |
529 | self->tx_buff.data = self->tx_buff.head; | |
d626f62b | 530 | skb_copy_from_linear_data(skb, self->tx_buff.data, skb->len); |
1da177e4 LT |
531 | self->tx_buff.len = skb->len; |
532 | ||
533 | mtt = irda_get_mtt(skb); | |
534 | #ifdef CONFIG_USE_INTERNAL_TIMER | |
535 | if (mtt > 50) { | |
536 | /* Adjust for timer resolution */ | |
537 | mtt /= 1000+1; | |
538 | ||
539 | /* Setup timer */ | |
540 | switch_bank(iobase, SET4); | |
541 | outb(mtt & 0xff, iobase+TMRL); | |
542 | outb((mtt >> 8) & 0x0f, iobase+TMRH); | |
543 | ||
544 | /* Start timer */ | |
545 | outb(IR_MSL_EN_TMR, iobase+IR_MSL); | |
546 | self->io.direction = IO_XMIT; | |
547 | ||
548 | /* Enable timer interrupt */ | |
549 | switch_bank(iobase, SET0); | |
550 | outb(ICR_ETMRI, iobase+ICR); | |
551 | } else { | |
552 | #endif | |
a97a6f10 | 553 | IRDA_DEBUG(4, "%s(%ld), mtt=%d\n", __func__ , jiffies, mtt); |
1da177e4 LT |
554 | if (mtt) |
555 | udelay(mtt); | |
556 | ||
557 | /* Enable DMA interrupt */ | |
558 | switch_bank(iobase, SET0); | |
559 | outb(ICR_EDMAI, iobase+ICR); | |
560 | w83977af_dma_write(self, iobase); | |
561 | #ifdef CONFIG_USE_INTERNAL_TIMER | |
562 | } | |
563 | #endif | |
564 | } else { | |
565 | self->tx_buff.data = self->tx_buff.head; | |
566 | self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data, | |
567 | self->tx_buff.truesize); | |
568 | ||
569 | /* Add interrupt on tx low level (will fire immediately) */ | |
570 | switch_bank(iobase, SET0); | |
571 | outb(ICR_ETXTHI, iobase+ICR); | |
572 | } | |
573 | dev->trans_start = jiffies; | |
574 | dev_kfree_skb(skb); | |
575 | ||
576 | /* Restore set register */ | |
577 | outb(set, iobase+SSR); | |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
582 | /* | |
583 | * Function w83977af_dma_write (self, iobase) | |
584 | * | |
585 | * Send frame using DMA | |
586 | * | |
587 | */ | |
588 | static void w83977af_dma_write(struct w83977af_ir *self, int iobase) | |
589 | { | |
590 | __u8 set; | |
591 | #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS | |
592 | unsigned long flags; | |
593 | __u8 hcr; | |
594 | #endif | |
a97a6f10 | 595 | IRDA_DEBUG(4, "%s(), len=%d\n", __func__ , self->tx_buff.len); |
1da177e4 LT |
596 | |
597 | /* Save current set */ | |
598 | set = inb(iobase+SSR); | |
599 | ||
600 | /* Disable DMA */ | |
601 | switch_bank(iobase, SET0); | |
602 | outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); | |
603 | ||
604 | /* Choose transmit DMA channel */ | |
605 | switch_bank(iobase, SET2); | |
606 | outb(ADCR1_D_CHSW|/*ADCR1_DMA_F|*/ADCR1_ADV_SL, iobase+ADCR1); | |
607 | #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS | |
608 | spin_lock_irqsave(&self->lock, flags); | |
609 | ||
610 | disable_dma(self->io.dma); | |
611 | clear_dma_ff(self->io.dma); | |
612 | set_dma_mode(self->io.dma, DMA_MODE_READ); | |
613 | set_dma_addr(self->io.dma, self->tx_buff_dma); | |
614 | set_dma_count(self->io.dma, self->tx_buff.len); | |
615 | #else | |
616 | irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len, | |
617 | DMA_MODE_WRITE); | |
618 | #endif | |
619 | self->io.direction = IO_XMIT; | |
620 | ||
621 | /* Enable DMA */ | |
622 | switch_bank(iobase, SET0); | |
623 | #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS | |
624 | hcr = inb(iobase+HCR); | |
625 | outb(hcr | HCR_EN_DMA, iobase+HCR); | |
626 | enable_dma(self->io.dma); | |
627 | spin_unlock_irqrestore(&self->lock, flags); | |
628 | #else | |
629 | outb(inb(iobase+HCR) | HCR_EN_DMA | HCR_TX_WT, iobase+HCR); | |
630 | #endif | |
631 | ||
632 | /* Restore set register */ | |
633 | outb(set, iobase+SSR); | |
634 | } | |
635 | ||
636 | /* | |
637 | * Function w83977af_pio_write (iobase, buf, len, fifo_size) | |
638 | * | |
639 | * | |
640 | * | |
641 | */ | |
642 | static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size) | |
643 | { | |
644 | int actual = 0; | |
645 | __u8 set; | |
646 | ||
a97a6f10 | 647 | IRDA_DEBUG(4, "%s()\n", __func__ ); |
1da177e4 LT |
648 | |
649 | /* Save current bank */ | |
650 | set = inb(iobase+SSR); | |
651 | ||
652 | switch_bank(iobase, SET0); | |
653 | if (!(inb_p(iobase+USR) & USR_TSRE)) { | |
654 | IRDA_DEBUG(4, | |
a97a6f10 | 655 | "%s(), warning, FIFO not empty yet!\n", __func__ ); |
1da177e4 LT |
656 | |
657 | fifo_size -= 17; | |
658 | IRDA_DEBUG(4, "%s(), %d bytes left in tx fifo\n", | |
a97a6f10 | 659 | __func__ , fifo_size); |
1da177e4 LT |
660 | } |
661 | ||
662 | /* Fill FIFO with current frame */ | |
663 | while ((fifo_size-- > 0) && (actual < len)) { | |
664 | /* Transmit next byte */ | |
665 | outb(buf[actual++], iobase+TBR); | |
666 | } | |
667 | ||
668 | IRDA_DEBUG(4, "%s(), fifo_size %d ; %d sent of %d\n", | |
a97a6f10 | 669 | __func__ , fifo_size, actual, len); |
1da177e4 LT |
670 | |
671 | /* Restore bank */ | |
672 | outb(set, iobase+SSR); | |
673 | ||
674 | return actual; | |
675 | } | |
676 | ||
677 | /* | |
678 | * Function w83977af_dma_xmit_complete (self) | |
679 | * | |
680 | * The transfer of a frame in finished. So do the necessary things | |
681 | * | |
682 | * | |
683 | */ | |
684 | static void w83977af_dma_xmit_complete(struct w83977af_ir *self) | |
685 | { | |
686 | int iobase; | |
687 | __u8 set; | |
688 | ||
a97a6f10 | 689 | IRDA_DEBUG(4, "%s(%ld)\n", __func__ , jiffies); |
1da177e4 LT |
690 | |
691 | IRDA_ASSERT(self != NULL, return;); | |
692 | ||
693 | iobase = self->io.fir_base; | |
694 | ||
695 | /* Save current set */ | |
696 | set = inb(iobase+SSR); | |
697 | ||
698 | /* Disable DMA */ | |
699 | switch_bank(iobase, SET0); | |
700 | outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); | |
701 | ||
702 | /* Check for underrrun! */ | |
703 | if (inb(iobase+AUDR) & AUDR_UNDR) { | |
a97a6f10 | 704 | IRDA_DEBUG(0, "%s(), Transmit underrun!\n", __func__ ); |
1da177e4 | 705 | |
af049081 SH |
706 | self->netdev->stats.tx_errors++; |
707 | self->netdev->stats.tx_fifo_errors++; | |
1da177e4 LT |
708 | |
709 | /* Clear bit, by writing 1 to it */ | |
710 | outb(AUDR_UNDR, iobase+AUDR); | |
711 | } else | |
af049081 | 712 | self->netdev->stats.tx_packets++; |
1da177e4 LT |
713 | |
714 | ||
715 | if (self->new_speed) { | |
716 | w83977af_change_speed(self, self->new_speed); | |
717 | self->new_speed = 0; | |
718 | } | |
719 | ||
720 | /* Unlock tx_buff and request another frame */ | |
721 | /* Tell the network layer, that we want more frames */ | |
722 | netif_wake_queue(self->netdev); | |
723 | ||
724 | /* Restore set */ | |
725 | outb(set, iobase+SSR); | |
726 | } | |
727 | ||
728 | /* | |
729 | * Function w83977af_dma_receive (self) | |
730 | * | |
731 | * Get ready for receiving a frame. The device will initiate a DMA | |
732 | * if it starts to receive a frame. | |
733 | * | |
734 | */ | |
0e49e645 | 735 | static int w83977af_dma_receive(struct w83977af_ir *self) |
1da177e4 LT |
736 | { |
737 | int iobase; | |
738 | __u8 set; | |
739 | #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS | |
740 | unsigned long flags; | |
741 | __u8 hcr; | |
742 | #endif | |
743 | IRDA_ASSERT(self != NULL, return -1;); | |
744 | ||
a97a6f10 | 745 | IRDA_DEBUG(4, "%s\n", __func__ ); |
1da177e4 LT |
746 | |
747 | iobase= self->io.fir_base; | |
748 | ||
749 | /* Save current set */ | |
750 | set = inb(iobase+SSR); | |
751 | ||
752 | /* Disable DMA */ | |
753 | switch_bank(iobase, SET0); | |
754 | outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); | |
755 | ||
756 | /* Choose DMA Rx, DMA Fairness, and Advanced mode */ | |
757 | switch_bank(iobase, SET2); | |
758 | outb((inb(iobase+ADCR1) & ~ADCR1_D_CHSW)/*|ADCR1_DMA_F*/|ADCR1_ADV_SL, | |
759 | iobase+ADCR1); | |
760 | ||
761 | self->io.direction = IO_RECV; | |
762 | self->rx_buff.data = self->rx_buff.head; | |
763 | ||
764 | #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS | |
765 | spin_lock_irqsave(&self->lock, flags); | |
766 | ||
767 | disable_dma(self->io.dma); | |
768 | clear_dma_ff(self->io.dma); | |
769 | set_dma_mode(self->io.dma, DMA_MODE_READ); | |
770 | set_dma_addr(self->io.dma, self->rx_buff_dma); | |
771 | set_dma_count(self->io.dma, self->rx_buff.truesize); | |
772 | #else | |
773 | irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize, | |
774 | DMA_MODE_READ); | |
775 | #endif | |
776 | /* | |
777 | * Reset Rx FIFO. This will also flush the ST_FIFO, it's very | |
778 | * important that we don't reset the Tx FIFO since it might not | |
779 | * be finished transmitting yet | |
780 | */ | |
781 | switch_bank(iobase, SET0); | |
782 | outb(UFR_RXTL|UFR_TXTL|UFR_RXF_RST|UFR_EN_FIFO, iobase+UFR); | |
783 | self->st_fifo.len = self->st_fifo.tail = self->st_fifo.head = 0; | |
784 | ||
785 | /* Enable DMA */ | |
786 | switch_bank(iobase, SET0); | |
787 | #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS | |
788 | hcr = inb(iobase+HCR); | |
789 | outb(hcr | HCR_EN_DMA, iobase+HCR); | |
790 | enable_dma(self->io.dma); | |
791 | spin_unlock_irqrestore(&self->lock, flags); | |
792 | #else | |
793 | outb(inb(iobase+HCR) | HCR_EN_DMA, iobase+HCR); | |
794 | #endif | |
795 | /* Restore set */ | |
796 | outb(set, iobase+SSR); | |
797 | ||
798 | return 0; | |
799 | } | |
800 | ||
801 | /* | |
802 | * Function w83977af_receive_complete (self) | |
803 | * | |
804 | * Finished with receiving a frame | |
805 | * | |
806 | */ | |
0e49e645 | 807 | static int w83977af_dma_receive_complete(struct w83977af_ir *self) |
1da177e4 LT |
808 | { |
809 | struct sk_buff *skb; | |
810 | struct st_fifo *st_fifo; | |
811 | int len; | |
812 | int iobase; | |
813 | __u8 set; | |
814 | __u8 status; | |
815 | ||
a97a6f10 | 816 | IRDA_DEBUG(4, "%s\n", __func__ ); |
1da177e4 LT |
817 | |
818 | st_fifo = &self->st_fifo; | |
819 | ||
820 | iobase = self->io.fir_base; | |
821 | ||
822 | /* Save current set */ | |
823 | set = inb(iobase+SSR); | |
824 | ||
825 | iobase = self->io.fir_base; | |
826 | ||
827 | /* Read status FIFO */ | |
828 | switch_bank(iobase, SET5); | |
829 | while ((status = inb(iobase+FS_FO)) & FS_FO_FSFDR) { | |
830 | st_fifo->entries[st_fifo->tail].status = status; | |
831 | ||
832 | st_fifo->entries[st_fifo->tail].len = inb(iobase+RFLFL); | |
833 | st_fifo->entries[st_fifo->tail].len |= inb(iobase+RFLFH) << 8; | |
834 | ||
835 | st_fifo->tail++; | |
836 | st_fifo->len++; | |
837 | } | |
838 | ||
839 | while (st_fifo->len) { | |
840 | /* Get first entry */ | |
841 | status = st_fifo->entries[st_fifo->head].status; | |
842 | len = st_fifo->entries[st_fifo->head].len; | |
843 | st_fifo->head++; | |
844 | st_fifo->len--; | |
845 | ||
846 | /* Check for errors */ | |
847 | if (status & FS_FO_ERR_MSK) { | |
848 | if (status & FS_FO_LST_FR) { | |
849 | /* Add number of lost frames to stats */ | |
af049081 | 850 | self->netdev->stats.rx_errors += len; |
1da177e4 LT |
851 | } else { |
852 | /* Skip frame */ | |
af049081 | 853 | self->netdev->stats.rx_errors++; |
1da177e4 LT |
854 | |
855 | self->rx_buff.data += len; | |
856 | ||
857 | if (status & FS_FO_MX_LEX) | |
af049081 | 858 | self->netdev->stats.rx_length_errors++; |
1da177e4 LT |
859 | |
860 | if (status & FS_FO_PHY_ERR) | |
af049081 | 861 | self->netdev->stats.rx_frame_errors++; |
1da177e4 LT |
862 | |
863 | if (status & FS_FO_CRC_ERR) | |
af049081 | 864 | self->netdev->stats.rx_crc_errors++; |
1da177e4 LT |
865 | } |
866 | /* The errors below can be reported in both cases */ | |
867 | if (status & FS_FO_RX_OV) | |
af049081 | 868 | self->netdev->stats.rx_fifo_errors++; |
1da177e4 LT |
869 | |
870 | if (status & FS_FO_FSF_OV) | |
af049081 | 871 | self->netdev->stats.rx_fifo_errors++; |
1da177e4 LT |
872 | |
873 | } else { | |
874 | /* Check if we have transferred all data to memory */ | |
875 | switch_bank(iobase, SET0); | |
876 | if (inb(iobase+USR) & USR_RDR) { | |
877 | #ifdef CONFIG_USE_INTERNAL_TIMER | |
878 | /* Put this entry back in fifo */ | |
879 | st_fifo->head--; | |
880 | st_fifo->len++; | |
881 | st_fifo->entries[st_fifo->head].status = status; | |
882 | st_fifo->entries[st_fifo->head].len = len; | |
883 | ||
884 | /* Restore set register */ | |
885 | outb(set, iobase+SSR); | |
886 | ||
887 | return FALSE; /* I'll be back! */ | |
888 | #else | |
889 | udelay(80); /* Should be enough!? */ | |
890 | #endif | |
891 | } | |
892 | ||
893 | skb = dev_alloc_skb(len+1); | |
894 | if (skb == NULL) { | |
895 | printk(KERN_INFO | |
a97a6f10 | 896 | "%s(), memory squeeze, dropping frame.\n", __func__); |
1da177e4 LT |
897 | /* Restore set register */ |
898 | outb(set, iobase+SSR); | |
899 | ||
900 | return FALSE; | |
901 | } | |
902 | ||
903 | /* Align to 20 bytes */ | |
904 | skb_reserve(skb, 1); | |
905 | ||
906 | /* Copy frame without CRC */ | |
907 | if (self->io.speed < 4000000) { | |
908 | skb_put(skb, len-2); | |
27d7ff46 ACM |
909 | skb_copy_to_linear_data(skb, |
910 | self->rx_buff.data, | |
911 | len - 2); | |
1da177e4 LT |
912 | } else { |
913 | skb_put(skb, len-4); | |
27d7ff46 ACM |
914 | skb_copy_to_linear_data(skb, |
915 | self->rx_buff.data, | |
916 | len - 4); | |
1da177e4 LT |
917 | } |
918 | ||
919 | /* Move to next frame */ | |
920 | self->rx_buff.data += len; | |
af049081 | 921 | self->netdev->stats.rx_packets++; |
1da177e4 LT |
922 | |
923 | skb->dev = self->netdev; | |
459a98ed | 924 | skb_reset_mac_header(skb); |
1da177e4 LT |
925 | skb->protocol = htons(ETH_P_IRDA); |
926 | netif_rx(skb); | |
1da177e4 LT |
927 | } |
928 | } | |
929 | /* Restore set register */ | |
930 | outb(set, iobase+SSR); | |
931 | ||
932 | return TRUE; | |
933 | } | |
934 | ||
935 | /* | |
936 | * Function pc87108_pio_receive (self) | |
937 | * | |
938 | * Receive all data in receiver FIFO | |
939 | * | |
940 | */ | |
941 | static void w83977af_pio_receive(struct w83977af_ir *self) | |
942 | { | |
943 | __u8 byte = 0x00; | |
944 | int iobase; | |
945 | ||
a97a6f10 | 946 | IRDA_DEBUG(4, "%s()\n", __func__ ); |
1da177e4 LT |
947 | |
948 | IRDA_ASSERT(self != NULL, return;); | |
949 | ||
950 | iobase = self->io.fir_base; | |
951 | ||
952 | /* Receive all characters in Rx FIFO */ | |
953 | do { | |
954 | byte = inb(iobase+RBR); | |
af049081 | 955 | async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff, |
1da177e4 LT |
956 | byte); |
957 | } while (inb(iobase+USR) & USR_RDR); /* Data available */ | |
958 | } | |
959 | ||
960 | /* | |
961 | * Function w83977af_sir_interrupt (self, eir) | |
962 | * | |
963 | * Handle SIR interrupt | |
964 | * | |
965 | */ | |
966 | static __u8 w83977af_sir_interrupt(struct w83977af_ir *self, int isr) | |
967 | { | |
968 | int actual; | |
969 | __u8 new_icr = 0; | |
970 | __u8 set; | |
971 | int iobase; | |
972 | ||
a97a6f10 | 973 | IRDA_DEBUG(4, "%s(), isr=%#x\n", __func__ , isr); |
1da177e4 LT |
974 | |
975 | iobase = self->io.fir_base; | |
976 | /* Transmit FIFO low on data */ | |
977 | if (isr & ISR_TXTH_I) { | |
978 | /* Write data left in transmit buffer */ | |
979 | actual = w83977af_pio_write(self->io.fir_base, | |
980 | self->tx_buff.data, | |
981 | self->tx_buff.len, | |
982 | self->io.fifo_size); | |
983 | ||
984 | self->tx_buff.data += actual; | |
985 | self->tx_buff.len -= actual; | |
986 | ||
987 | self->io.direction = IO_XMIT; | |
988 | ||
989 | /* Check if finished */ | |
990 | if (self->tx_buff.len > 0) { | |
991 | new_icr |= ICR_ETXTHI; | |
992 | } else { | |
993 | set = inb(iobase+SSR); | |
994 | switch_bank(iobase, SET0); | |
995 | outb(AUDR_SFEND, iobase+AUDR); | |
996 | outb(set, iobase+SSR); | |
997 | ||
af049081 | 998 | self->netdev->stats.tx_packets++; |
1da177e4 LT |
999 | |
1000 | /* Feed me more packets */ | |
1001 | netif_wake_queue(self->netdev); | |
1002 | new_icr |= ICR_ETBREI; | |
1003 | } | |
1004 | } | |
1005 | /* Check if transmission has completed */ | |
1006 | if (isr & ISR_TXEMP_I) { | |
1007 | /* Check if we need to change the speed? */ | |
1008 | if (self->new_speed) { | |
1009 | IRDA_DEBUG(2, | |
a97a6f10 | 1010 | "%s(), Changing speed!\n", __func__ ); |
1da177e4 LT |
1011 | w83977af_change_speed(self, self->new_speed); |
1012 | self->new_speed = 0; | |
1013 | } | |
1014 | ||
1015 | /* Turn around and get ready to receive some data */ | |
1016 | self->io.direction = IO_RECV; | |
1017 | new_icr |= ICR_ERBRI; | |
1018 | } | |
1019 | ||
1020 | /* Rx FIFO threshold or timeout */ | |
1021 | if (isr & ISR_RXTH_I) { | |
1022 | w83977af_pio_receive(self); | |
1023 | ||
1024 | /* Keep receiving */ | |
1025 | new_icr |= ICR_ERBRI; | |
1026 | } | |
1027 | return new_icr; | |
1028 | } | |
1029 | ||
1030 | /* | |
1031 | * Function pc87108_fir_interrupt (self, eir) | |
1032 | * | |
1033 | * Handle MIR/FIR interrupt | |
1034 | * | |
1035 | */ | |
1036 | static __u8 w83977af_fir_interrupt(struct w83977af_ir *self, int isr) | |
1037 | { | |
1038 | __u8 new_icr = 0; | |
1039 | __u8 set; | |
1040 | int iobase; | |
1041 | ||
1042 | iobase = self->io.fir_base; | |
1043 | set = inb(iobase+SSR); | |
1044 | ||
1045 | /* End of frame detected in FIFO */ | |
1046 | if (isr & (ISR_FEND_I|ISR_FSF_I)) { | |
1047 | if (w83977af_dma_receive_complete(self)) { | |
1048 | ||
1049 | /* Wait for next status FIFO interrupt */ | |
1050 | new_icr |= ICR_EFSFI; | |
1051 | } else { | |
1052 | /* DMA not finished yet */ | |
1053 | ||
1054 | /* Set timer value, resolution 1 ms */ | |
1055 | switch_bank(iobase, SET4); | |
1056 | outb(0x01, iobase+TMRL); /* 1 ms */ | |
1057 | outb(0x00, iobase+TMRH); | |
1058 | ||
1059 | /* Start timer */ | |
1060 | outb(IR_MSL_EN_TMR, iobase+IR_MSL); | |
1061 | ||
1062 | new_icr |= ICR_ETMRI; | |
1063 | } | |
1064 | } | |
1065 | /* Timer finished */ | |
1066 | if (isr & ISR_TMR_I) { | |
1067 | /* Disable timer */ | |
1068 | switch_bank(iobase, SET4); | |
1069 | outb(0, iobase+IR_MSL); | |
1070 | ||
1071 | /* Clear timer event */ | |
1072 | /* switch_bank(iobase, SET0); */ | |
1073 | /* outb(ASCR_CTE, iobase+ASCR); */ | |
1074 | ||
1075 | /* Check if this is a TX timer interrupt */ | |
1076 | if (self->io.direction == IO_XMIT) { | |
1077 | w83977af_dma_write(self, iobase); | |
1078 | ||
1079 | new_icr |= ICR_EDMAI; | |
1080 | } else { | |
1081 | /* Check if DMA has now finished */ | |
1082 | w83977af_dma_receive_complete(self); | |
1083 | ||
1084 | new_icr |= ICR_EFSFI; | |
1085 | } | |
1086 | } | |
1087 | /* Finished with DMA */ | |
1088 | if (isr & ISR_DMA_I) { | |
1089 | w83977af_dma_xmit_complete(self); | |
1090 | ||
1091 | /* Check if there are more frames to be transmitted */ | |
1092 | /* if (irda_device_txqueue_empty(self)) { */ | |
1093 | ||
1094 | /* Prepare for receive | |
1095 | * | |
1096 | * ** Netwinder Tx DMA likes that we do this anyway ** | |
1097 | */ | |
1098 | w83977af_dma_receive(self); | |
1099 | new_icr = ICR_EFSFI; | |
1100 | /* } */ | |
1101 | } | |
1102 | ||
1103 | /* Restore set */ | |
1104 | outb(set, iobase+SSR); | |
1105 | ||
1106 | return new_icr; | |
1107 | } | |
1108 | ||
1109 | /* | |
1110 | * Function w83977af_interrupt (irq, dev_id, regs) | |
1111 | * | |
1112 | * An interrupt from the chip has arrived. Time to do some work | |
1113 | * | |
1114 | */ | |
7d12e780 | 1115 | static irqreturn_t w83977af_interrupt(int irq, void *dev_id) |
1da177e4 | 1116 | { |
c31f28e7 | 1117 | struct net_device *dev = dev_id; |
1da177e4 LT |
1118 | struct w83977af_ir *self; |
1119 | __u8 set, icr, isr; | |
1120 | int iobase; | |
1121 | ||
4cf1653a | 1122 | self = netdev_priv(dev); |
1da177e4 LT |
1123 | |
1124 | iobase = self->io.fir_base; | |
1125 | ||
1126 | /* Save current bank */ | |
1127 | set = inb(iobase+SSR); | |
1128 | switch_bank(iobase, SET0); | |
1129 | ||
1130 | icr = inb(iobase+ICR); | |
1131 | isr = inb(iobase+ISR) & icr; /* Mask out the interesting ones */ | |
1132 | ||
1133 | outb(0, iobase+ICR); /* Disable interrupts */ | |
1134 | ||
1135 | if (isr) { | |
1136 | /* Dispatch interrupt handler for the current speed */ | |
1137 | if (self->io.speed > PIO_MAX_SPEED ) | |
1138 | icr = w83977af_fir_interrupt(self, isr); | |
1139 | else | |
1140 | icr = w83977af_sir_interrupt(self, isr); | |
1141 | } | |
1142 | ||
1143 | outb(icr, iobase+ICR); /* Restore (new) interrupts */ | |
1144 | outb(set, iobase+SSR); /* Restore bank register */ | |
1145 | return IRQ_RETVAL(isr); | |
1146 | } | |
1147 | ||
1148 | /* | |
1149 | * Function w83977af_is_receiving (self) | |
1150 | * | |
1151 | * Return TRUE is we are currently receiving a frame | |
1152 | * | |
1153 | */ | |
1154 | static int w83977af_is_receiving(struct w83977af_ir *self) | |
1155 | { | |
1156 | int status = FALSE; | |
1157 | int iobase; | |
1158 | __u8 set; | |
1159 | ||
1160 | IRDA_ASSERT(self != NULL, return FALSE;); | |
1161 | ||
1162 | if (self->io.speed > 115200) { | |
1163 | iobase = self->io.fir_base; | |
1164 | ||
1165 | /* Check if rx FIFO is not empty */ | |
1166 | set = inb(iobase+SSR); | |
1167 | switch_bank(iobase, SET2); | |
1168 | if ((inb(iobase+RXFDTH) & 0x3f) != 0) { | |
1169 | /* We are receiving something */ | |
1170 | status = TRUE; | |
1171 | } | |
1172 | outb(set, iobase+SSR); | |
1173 | } else | |
1174 | status = (self->rx_buff.state != OUTSIDE_FRAME); | |
1175 | ||
1176 | return status; | |
1177 | } | |
1178 | ||
1179 | /* | |
1180 | * Function w83977af_net_open (dev) | |
1181 | * | |
1182 | * Start the device | |
1183 | * | |
1184 | */ | |
1185 | static int w83977af_net_open(struct net_device *dev) | |
1186 | { | |
1187 | struct w83977af_ir *self; | |
1188 | int iobase; | |
1189 | char hwname[32]; | |
1190 | __u8 set; | |
1191 | ||
a97a6f10 | 1192 | IRDA_DEBUG(0, "%s()\n", __func__ ); |
1da177e4 LT |
1193 | |
1194 | IRDA_ASSERT(dev != NULL, return -1;); | |
4cf1653a | 1195 | self = netdev_priv(dev); |
1da177e4 LT |
1196 | |
1197 | IRDA_ASSERT(self != NULL, return 0;); | |
1198 | ||
1199 | iobase = self->io.fir_base; | |
1200 | ||
1201 | if (request_irq(self->io.irq, w83977af_interrupt, 0, dev->name, | |
1202 | (void *) dev)) { | |
1203 | return -EAGAIN; | |
1204 | } | |
1205 | /* | |
1206 | * Always allocate the DMA channel after the IRQ, | |
1207 | * and clean up on failure. | |
1208 | */ | |
1209 | if (request_dma(self->io.dma, dev->name)) { | |
1210 | free_irq(self->io.irq, self); | |
1211 | return -EAGAIN; | |
1212 | } | |
1213 | ||
1214 | /* Save current set */ | |
1215 | set = inb(iobase+SSR); | |
1216 | ||
1217 | /* Enable some interrupts so we can receive frames again */ | |
1218 | switch_bank(iobase, SET0); | |
1219 | if (self->io.speed > 115200) { | |
1220 | outb(ICR_EFSFI, iobase+ICR); | |
1221 | w83977af_dma_receive(self); | |
1222 | } else | |
1223 | outb(ICR_ERBRI, iobase+ICR); | |
1224 | ||
1225 | /* Restore bank register */ | |
1226 | outb(set, iobase+SSR); | |
1227 | ||
1228 | /* Ready to play! */ | |
1229 | netif_start_queue(dev); | |
1230 | ||
1231 | /* Give self a hardware name */ | |
1232 | sprintf(hwname, "w83977af @ 0x%03x", self->io.fir_base); | |
1233 | ||
1234 | /* | |
1235 | * Open new IrLAP layer instance, now that everything should be | |
1236 | * initialized properly | |
1237 | */ | |
1238 | self->irlap = irlap_open(dev, &self->qos, hwname); | |
1239 | ||
1240 | return 0; | |
1241 | } | |
1242 | ||
1243 | /* | |
1244 | * Function w83977af_net_close (dev) | |
1245 | * | |
1246 | * Stop the device | |
1247 | * | |
1248 | */ | |
1249 | static int w83977af_net_close(struct net_device *dev) | |
1250 | { | |
1251 | struct w83977af_ir *self; | |
1252 | int iobase; | |
1253 | __u8 set; | |
1254 | ||
a97a6f10 | 1255 | IRDA_DEBUG(0, "%s()\n", __func__ ); |
1da177e4 LT |
1256 | |
1257 | IRDA_ASSERT(dev != NULL, return -1;); | |
1258 | ||
4cf1653a | 1259 | self = netdev_priv(dev); |
1da177e4 LT |
1260 | |
1261 | IRDA_ASSERT(self != NULL, return 0;); | |
1262 | ||
1263 | iobase = self->io.fir_base; | |
1264 | ||
1265 | /* Stop device */ | |
1266 | netif_stop_queue(dev); | |
1267 | ||
1268 | /* Stop and remove instance of IrLAP */ | |
1269 | if (self->irlap) | |
1270 | irlap_close(self->irlap); | |
1271 | self->irlap = NULL; | |
1272 | ||
1273 | disable_dma(self->io.dma); | |
1274 | ||
1275 | /* Save current set */ | |
1276 | set = inb(iobase+SSR); | |
1277 | ||
1278 | /* Disable interrupts */ | |
1279 | switch_bank(iobase, SET0); | |
1280 | outb(0, iobase+ICR); | |
1281 | ||
1282 | free_irq(self->io.irq, dev); | |
1283 | free_dma(self->io.dma); | |
1284 | ||
1285 | /* Restore bank register */ | |
1286 | outb(set, iobase+SSR); | |
1287 | ||
1288 | return 0; | |
1289 | } | |
1290 | ||
1291 | /* | |
1292 | * Function w83977af_net_ioctl (dev, rq, cmd) | |
1293 | * | |
1294 | * Process IOCTL commands for this device | |
1295 | * | |
1296 | */ | |
1297 | static int w83977af_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1298 | { | |
1299 | struct if_irda_req *irq = (struct if_irda_req *) rq; | |
1300 | struct w83977af_ir *self; | |
1301 | unsigned long flags; | |
1302 | int ret = 0; | |
1303 | ||
1304 | IRDA_ASSERT(dev != NULL, return -1;); | |
1305 | ||
4cf1653a | 1306 | self = netdev_priv(dev); |
1da177e4 LT |
1307 | |
1308 | IRDA_ASSERT(self != NULL, return -1;); | |
1309 | ||
a97a6f10 | 1310 | IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__ , dev->name, cmd); |
1da177e4 LT |
1311 | |
1312 | spin_lock_irqsave(&self->lock, flags); | |
1313 | ||
1314 | switch (cmd) { | |
1315 | case SIOCSBANDWIDTH: /* Set bandwidth */ | |
1316 | if (!capable(CAP_NET_ADMIN)) { | |
1317 | ret = -EPERM; | |
1318 | goto out; | |
1319 | } | |
1320 | w83977af_change_speed(self, irq->ifr_baudrate); | |
1321 | break; | |
1322 | case SIOCSMEDIABUSY: /* Set media busy */ | |
1323 | if (!capable(CAP_NET_ADMIN)) { | |
1324 | ret = -EPERM; | |
1325 | goto out; | |
1326 | } | |
1327 | irda_device_set_media_busy(self->netdev, TRUE); | |
1328 | break; | |
1329 | case SIOCGRECEIVING: /* Check if we are receiving right now */ | |
1330 | irq->ifr_receiving = w83977af_is_receiving(self); | |
1331 | break; | |
1332 | default: | |
1333 | ret = -EOPNOTSUPP; | |
1334 | } | |
1335 | out: | |
1336 | spin_unlock_irqrestore(&self->lock, flags); | |
1337 | return ret; | |
1338 | } | |
1339 | ||
1da177e4 LT |
1340 | MODULE_AUTHOR("Dag Brattli <dagb@cs.uit.no>"); |
1341 | MODULE_DESCRIPTION("Winbond W83977AF IrDA Device Driver"); | |
1342 | MODULE_LICENSE("GPL"); | |
1343 | ||
1344 | ||
1345 | module_param(qos_mtt_bits, int, 0); | |
1346 | MODULE_PARM_DESC(qos_mtt_bits, "Mimimum Turn Time"); | |
1347 | module_param_array(io, int, NULL, 0); | |
1348 | MODULE_PARM_DESC(io, "Base I/O addresses"); | |
1349 | module_param_array(irq, int, NULL, 0); | |
1350 | MODULE_PARM_DESC(irq, "IRQ lines"); | |
1351 | ||
1352 | /* | |
1353 | * Function init_module (void) | |
1354 | * | |
1355 | * | |
1356 | * | |
1357 | */ | |
1358 | module_init(w83977af_init); | |
1359 | ||
1360 | /* | |
1361 | * Function cleanup_module (void) | |
1362 | * | |
1363 | * | |
1364 | * | |
1365 | */ | |
1366 | module_exit(w83977af_cleanup); |