Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /******************************************************************************* |
2 | ||
3 | ||
4 | Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms of the GNU General Public License as published by the Free | |
8 | Software Foundation; either version 2 of the License, or (at your option) | |
9 | any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., 59 | |
18 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in the | |
21 | file called LICENSE. | |
22 | ||
23 | Contact Information: | |
24 | Linux NICS <linux.nics@intel.com> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #ifndef _IXGB_HW_H_ | |
30 | #define _IXGB_HW_H_ | |
31 | ||
32 | #include "ixgb_osdep.h" | |
33 | ||
34 | /* Enums */ | |
35 | typedef enum { | |
36 | ixgb_mac_unknown = 0, | |
37 | ixgb_82597, | |
38 | ixgb_num_macs | |
39 | } ixgb_mac_type; | |
40 | ||
41 | /* Types of physical layer modules */ | |
42 | typedef enum { | |
43 | ixgb_phy_type_unknown = 0, | |
44 | ixgb_phy_type_g6005, /* 850nm, MM fiber, XPAK transceiver */ | |
45 | ixgb_phy_type_g6104, /* 1310nm, SM fiber, XPAK transceiver */ | |
46 | ixgb_phy_type_txn17201, /* 850nm, MM fiber, XPAK transceiver */ | |
47 | ixgb_phy_type_txn17401 /* 1310nm, SM fiber, XENPAK transceiver */ | |
48 | } ixgb_phy_type; | |
49 | ||
50 | /* XPAK transceiver vendors, for the SR adapters */ | |
51 | typedef enum { | |
52 | ixgb_xpak_vendor_intel, | |
53 | ixgb_xpak_vendor_infineon | |
54 | } ixgb_xpak_vendor; | |
55 | ||
56 | /* Media Types */ | |
57 | typedef enum { | |
58 | ixgb_media_type_unknown = 0, | |
59 | ixgb_media_type_fiber = 1, | |
60 | ixgb_num_media_types | |
61 | } ixgb_media_type; | |
62 | ||
63 | /* Flow Control Settings */ | |
64 | typedef enum { | |
65 | ixgb_fc_none = 0, | |
66 | ixgb_fc_rx_pause = 1, | |
67 | ixgb_fc_tx_pause = 2, | |
68 | ixgb_fc_full = 3, | |
69 | ixgb_fc_default = 0xFF | |
70 | } ixgb_fc_type; | |
71 | ||
72 | /* PCI bus types */ | |
73 | typedef enum { | |
74 | ixgb_bus_type_unknown = 0, | |
75 | ixgb_bus_type_pci, | |
76 | ixgb_bus_type_pcix | |
77 | } ixgb_bus_type; | |
78 | ||
79 | /* PCI bus speeds */ | |
80 | typedef enum { | |
81 | ixgb_bus_speed_unknown = 0, | |
82 | ixgb_bus_speed_33, | |
83 | ixgb_bus_speed_66, | |
84 | ixgb_bus_speed_100, | |
85 | ixgb_bus_speed_133, | |
86 | ixgb_bus_speed_reserved | |
87 | } ixgb_bus_speed; | |
88 | ||
89 | /* PCI bus widths */ | |
90 | typedef enum { | |
91 | ixgb_bus_width_unknown = 0, | |
92 | ixgb_bus_width_32, | |
93 | ixgb_bus_width_64 | |
94 | } ixgb_bus_width; | |
95 | ||
96 | #define IXGB_ETH_LENGTH_OF_ADDRESS 6 | |
97 | ||
98 | #define IXGB_EEPROM_SIZE 64 /* Size in words */ | |
99 | ||
100 | #define SPEED_10000 10000 | |
101 | #define FULL_DUPLEX 2 | |
102 | ||
103 | #define MIN_NUMBER_OF_DESCRIPTORS 8 | |
104 | #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 /* 13 bits in RDLEN/TDLEN, 128B aligned */ | |
105 | ||
106 | #define IXGB_DELAY_BEFORE_RESET 10 /* allow 10ms after idling rx/tx units */ | |
107 | #define IXGB_DELAY_AFTER_RESET 1 /* allow 1ms after the reset */ | |
108 | #define IXGB_DELAY_AFTER_EE_RESET 10 /* allow 10ms after the EEPROM reset */ | |
109 | ||
110 | #define IXGB_DELAY_USECS_AFTER_LINK_RESET 13 /* allow 13 microseconds after the reset */ | |
111 | /* NOTE: this is MICROSECONDS */ | |
112 | #define MAX_RESET_ITERATIONS 8 /* number of iterations to get things right */ | |
113 | ||
114 | /* General Registers */ | |
115 | #define IXGB_CTRL0 0x00000 /* Device Control Register 0 - RW */ | |
116 | #define IXGB_CTRL1 0x00008 /* Device Control Register 1 - RW */ | |
117 | #define IXGB_STATUS 0x00010 /* Device Status Register - RO */ | |
118 | #define IXGB_EECD 0x00018 /* EEPROM/Flash Control/Data Register - RW */ | |
119 | #define IXGB_MFS 0x00020 /* Maximum Frame Size - RW */ | |
120 | ||
121 | /* Interrupt */ | |
122 | #define IXGB_ICR 0x00080 /* Interrupt Cause Read - R/clr */ | |
123 | #define IXGB_ICS 0x00088 /* Interrupt Cause Set - RW */ | |
124 | #define IXGB_IMS 0x00090 /* Interrupt Mask Set/Read - RW */ | |
125 | #define IXGB_IMC 0x00098 /* Interrupt Mask Clear - WO */ | |
126 | ||
127 | /* Receive */ | |
128 | #define IXGB_RCTL 0x00100 /* RX Control - RW */ | |
129 | #define IXGB_FCRTL 0x00108 /* Flow Control Receive Threshold Low - RW */ | |
130 | #define IXGB_FCRTH 0x00110 /* Flow Control Receive Threshold High - RW */ | |
131 | #define IXGB_RDBAL 0x00118 /* RX Descriptor Base Low - RW */ | |
132 | #define IXGB_RDBAH 0x0011C /* RX Descriptor Base High - RW */ | |
133 | #define IXGB_RDLEN 0x00120 /* RX Descriptor Length - RW */ | |
134 | #define IXGB_RDH 0x00128 /* RX Descriptor Head - RW */ | |
135 | #define IXGB_RDT 0x00130 /* RX Descriptor Tail - RW */ | |
136 | #define IXGB_RDTR 0x00138 /* RX Delay Timer Ring - RW */ | |
137 | #define IXGB_RXDCTL 0x00140 /* Receive Descriptor Control - RW */ | |
138 | #define IXGB_RAIDC 0x00148 /* Receive Adaptive Interrupt Delay Control - RW */ | |
139 | #define IXGB_RXCSUM 0x00158 /* Receive Checksum Control - RW */ | |
140 | #define IXGB_RA 0x00180 /* Receive Address Array Base - RW */ | |
141 | #define IXGB_RAL 0x00180 /* Receive Address Low [0:15] - RW */ | |
142 | #define IXGB_RAH 0x00184 /* Receive Address High [0:15] - RW */ | |
143 | #define IXGB_MTA 0x00200 /* Multicast Table Array [0:127] - RW */ | |
144 | #define IXGB_VFTA 0x00400 /* VLAN Filter Table Array [0:127] - RW */ | |
145 | #define IXGB_REQ_RX_DESCRIPTOR_MULTIPLE 8 | |
146 | ||
147 | /* Transmit */ | |
148 | #define IXGB_TCTL 0x00600 /* TX Control - RW */ | |
149 | #define IXGB_TDBAL 0x00608 /* TX Descriptor Base Low - RW */ | |
150 | #define IXGB_TDBAH 0x0060C /* TX Descriptor Base High - RW */ | |
151 | #define IXGB_TDLEN 0x00610 /* TX Descriptor Length - RW */ | |
152 | #define IXGB_TDH 0x00618 /* TX Descriptor Head - RW */ | |
153 | #define IXGB_TDT 0x00620 /* TX Descriptor Tail - RW */ | |
154 | #define IXGB_TIDV 0x00628 /* TX Interrupt Delay Value - RW */ | |
155 | #define IXGB_TXDCTL 0x00630 /* Transmit Descriptor Control - RW */ | |
156 | #define IXGB_TSPMT 0x00638 /* TCP Segmentation PAD & Min Threshold - RW */ | |
157 | #define IXGB_PAP 0x00640 /* Pause and Pace - RW */ | |
158 | #define IXGB_REQ_TX_DESCRIPTOR_MULTIPLE 8 | |
159 | ||
160 | /* Physical */ | |
161 | #define IXGB_PCSC1 0x00700 /* PCS Control 1 - RW */ | |
162 | #define IXGB_PCSC2 0x00708 /* PCS Control 2 - RW */ | |
163 | #define IXGB_PCSS1 0x00710 /* PCS Status 1 - RO */ | |
164 | #define IXGB_PCSS2 0x00718 /* PCS Status 2 - RO */ | |
165 | #define IXGB_XPCSS 0x00720 /* 10GBASE-X PCS Status (or XGXS Lane Status) - RO */ | |
166 | #define IXGB_UCCR 0x00728 /* Unilink Circuit Control Register */ | |
167 | #define IXGB_XPCSTC 0x00730 /* 10GBASE-X PCS Test Control */ | |
168 | #define IXGB_MACA 0x00738 /* MDI Autoscan Command and Address - RW */ | |
169 | #define IXGB_APAE 0x00740 /* Autoscan PHY Address Enable - RW */ | |
170 | #define IXGB_ARD 0x00748 /* Autoscan Read Data - RO */ | |
171 | #define IXGB_AIS 0x00750 /* Autoscan Interrupt Status - RO */ | |
172 | #define IXGB_MSCA 0x00758 /* MDI Single Command and Address - RW */ | |
173 | #define IXGB_MSRWD 0x00760 /* MDI Single Read and Write Data - RW, RO */ | |
174 | ||
175 | /* Wake-up */ | |
176 | #define IXGB_WUFC 0x00808 /* Wake Up Filter Control - RW */ | |
177 | #define IXGB_WUS 0x00810 /* Wake Up Status - RO */ | |
178 | #define IXGB_FFLT 0x01000 /* Flexible Filter Length Table - RW */ | |
179 | #define IXGB_FFMT 0x01020 /* Flexible Filter Mask Table - RW */ | |
180 | #define IXGB_FTVT 0x01420 /* Flexible Filter Value Table - RW */ | |
181 | ||
182 | /* Statistics */ | |
183 | #define IXGB_TPRL 0x02000 /* Total Packets Received (Low) */ | |
184 | #define IXGB_TPRH 0x02004 /* Total Packets Received (High) */ | |
185 | #define IXGB_GPRCL 0x02008 /* Good Packets Received Count (Low) */ | |
186 | #define IXGB_GPRCH 0x0200C /* Good Packets Received Count (High) */ | |
187 | #define IXGB_BPRCL 0x02010 /* Broadcast Packets Received Count (Low) */ | |
188 | #define IXGB_BPRCH 0x02014 /* Broadcast Packets Received Count (High) */ | |
189 | #define IXGB_MPRCL 0x02018 /* Multicast Packets Received Count (Low) */ | |
190 | #define IXGB_MPRCH 0x0201C /* Multicast Packets Received Count (High) */ | |
191 | #define IXGB_UPRCL 0x02020 /* Unicast Packets Received Count (Low) */ | |
192 | #define IXGB_UPRCH 0x02024 /* Unicast Packets Received Count (High) */ | |
193 | #define IXGB_VPRCL 0x02028 /* VLAN Packets Received Count (Low) */ | |
194 | #define IXGB_VPRCH 0x0202C /* VLAN Packets Received Count (High) */ | |
195 | #define IXGB_JPRCL 0x02030 /* Jumbo Packets Received Count (Low) */ | |
196 | #define IXGB_JPRCH 0x02034 /* Jumbo Packets Received Count (High) */ | |
197 | #define IXGB_GORCL 0x02038 /* Good Octets Received Count (Low) */ | |
198 | #define IXGB_GORCH 0x0203C /* Good Octets Received Count (High) */ | |
199 | #define IXGB_TORL 0x02040 /* Total Octets Received (Low) */ | |
200 | #define IXGB_TORH 0x02044 /* Total Octets Received (High) */ | |
201 | #define IXGB_RNBC 0x02048 /* Receive No Buffers Count */ | |
202 | #define IXGB_RUC 0x02050 /* Receive Undersize Count */ | |
203 | #define IXGB_ROC 0x02058 /* Receive Oversize Count */ | |
204 | #define IXGB_RLEC 0x02060 /* Receive Length Error Count */ | |
205 | #define IXGB_CRCERRS 0x02068 /* CRC Error Count */ | |
206 | #define IXGB_ICBC 0x02070 /* Illegal control byte in mid-packet Count */ | |
207 | #define IXGB_ECBC 0x02078 /* Error Control byte in mid-packet Count */ | |
208 | #define IXGB_MPC 0x02080 /* Missed Packets Count */ | |
209 | #define IXGB_TPTL 0x02100 /* Total Packets Transmitted (Low) */ | |
210 | #define IXGB_TPTH 0x02104 /* Total Packets Transmitted (High) */ | |
211 | #define IXGB_GPTCL 0x02108 /* Good Packets Transmitted Count (Low) */ | |
212 | #define IXGB_GPTCH 0x0210C /* Good Packets Transmitted Count (High) */ | |
213 | #define IXGB_BPTCL 0x02110 /* Broadcast Packets Transmitted Count (Low) */ | |
214 | #define IXGB_BPTCH 0x02114 /* Broadcast Packets Transmitted Count (High) */ | |
215 | #define IXGB_MPTCL 0x02118 /* Multicast Packets Transmitted Count (Low) */ | |
216 | #define IXGB_MPTCH 0x0211C /* Multicast Packets Transmitted Count (High) */ | |
217 | #define IXGB_UPTCL 0x02120 /* Unicast Packets Transmitted Count (Low) */ | |
218 | #define IXGB_UPTCH 0x02124 /* Unicast Packets Transmitted Count (High) */ | |
219 | #define IXGB_VPTCL 0x02128 /* VLAN Packets Transmitted Count (Low) */ | |
220 | #define IXGB_VPTCH 0x0212C /* VLAN Packets Transmitted Count (High) */ | |
221 | #define IXGB_JPTCL 0x02130 /* Jumbo Packets Transmitted Count (Low) */ | |
222 | #define IXGB_JPTCH 0x02134 /* Jumbo Packets Transmitted Count (High) */ | |
223 | #define IXGB_GOTCL 0x02138 /* Good Octets Transmitted Count (Low) */ | |
224 | #define IXGB_GOTCH 0x0213C /* Good Octets Transmitted Count (High) */ | |
225 | #define IXGB_TOTL 0x02140 /* Total Octets Transmitted Count (Low) */ | |
226 | #define IXGB_TOTH 0x02144 /* Total Octets Transmitted Count (High) */ | |
227 | #define IXGB_DC 0x02148 /* Defer Count */ | |
228 | #define IXGB_PLT64C 0x02150 /* Packet Transmitted was less than 64 bytes Count */ | |
229 | #define IXGB_TSCTC 0x02170 /* TCP Segmentation Context Transmitted Count */ | |
230 | #define IXGB_TSCTFC 0x02178 /* TCP Segmentation Context Tx Fail Count */ | |
231 | #define IXGB_IBIC 0x02180 /* Illegal byte during Idle stream count */ | |
232 | #define IXGB_RFC 0x02188 /* Remote Fault Count */ | |
233 | #define IXGB_LFC 0x02190 /* Local Fault Count */ | |
234 | #define IXGB_PFRC 0x02198 /* Pause Frame Receive Count */ | |
235 | #define IXGB_PFTC 0x021A0 /* Pause Frame Transmit Count */ | |
236 | #define IXGB_MCFRC 0x021A8 /* MAC Control Frames (non-Pause) Received Count */ | |
237 | #define IXGB_MCFTC 0x021B0 /* MAC Control Frames (non-Pause) Transmitted Count */ | |
238 | #define IXGB_XONRXC 0x021B8 /* XON Received Count */ | |
239 | #define IXGB_XONTXC 0x021C0 /* XON Transmitted Count */ | |
240 | #define IXGB_XOFFRXC 0x021C8 /* XOFF Received Count */ | |
241 | #define IXGB_XOFFTXC 0x021D0 /* XOFF Transmitted Count */ | |
242 | #define IXGB_RJC 0x021D8 /* Receive Jabber Count */ | |
243 | ||
244 | /* CTRL0 Bit Masks */ | |
245 | #define IXGB_CTRL0_LRST 0x00000008 | |
246 | #define IXGB_CTRL0_JFE 0x00000010 | |
247 | #define IXGB_CTRL0_XLE 0x00000020 | |
248 | #define IXGB_CTRL0_MDCS 0x00000040 | |
249 | #define IXGB_CTRL0_CMDC 0x00000080 | |
250 | #define IXGB_CTRL0_SDP0 0x00040000 | |
251 | #define IXGB_CTRL0_SDP1 0x00080000 | |
252 | #define IXGB_CTRL0_SDP2 0x00100000 | |
253 | #define IXGB_CTRL0_SDP3 0x00200000 | |
254 | #define IXGB_CTRL0_SDP0_DIR 0x00400000 | |
255 | #define IXGB_CTRL0_SDP1_DIR 0x00800000 | |
256 | #define IXGB_CTRL0_SDP2_DIR 0x01000000 | |
257 | #define IXGB_CTRL0_SDP3_DIR 0x02000000 | |
258 | #define IXGB_CTRL0_RST 0x04000000 | |
259 | #define IXGB_CTRL0_RPE 0x08000000 | |
260 | #define IXGB_CTRL0_TPE 0x10000000 | |
261 | #define IXGB_CTRL0_VME 0x40000000 | |
262 | ||
263 | /* CTRL1 Bit Masks */ | |
264 | #define IXGB_CTRL1_GPI0_EN 0x00000001 | |
265 | #define IXGB_CTRL1_GPI1_EN 0x00000002 | |
266 | #define IXGB_CTRL1_GPI2_EN 0x00000004 | |
267 | #define IXGB_CTRL1_GPI3_EN 0x00000008 | |
268 | #define IXGB_CTRL1_SDP4 0x00000010 | |
269 | #define IXGB_CTRL1_SDP5 0x00000020 | |
270 | #define IXGB_CTRL1_SDP6 0x00000040 | |
271 | #define IXGB_CTRL1_SDP7 0x00000080 | |
272 | #define IXGB_CTRL1_SDP4_DIR 0x00000100 | |
273 | #define IXGB_CTRL1_SDP5_DIR 0x00000200 | |
274 | #define IXGB_CTRL1_SDP6_DIR 0x00000400 | |
275 | #define IXGB_CTRL1_SDP7_DIR 0x00000800 | |
276 | #define IXGB_CTRL1_EE_RST 0x00002000 | |
277 | #define IXGB_CTRL1_RO_DIS 0x00020000 | |
278 | #define IXGB_CTRL1_PCIXHM_MASK 0x00C00000 | |
279 | #define IXGB_CTRL1_PCIXHM_1_2 0x00000000 | |
280 | #define IXGB_CTRL1_PCIXHM_5_8 0x00400000 | |
281 | #define IXGB_CTRL1_PCIXHM_3_4 0x00800000 | |
282 | #define IXGB_CTRL1_PCIXHM_7_8 0x00C00000 | |
283 | ||
284 | /* STATUS Bit Masks */ | |
285 | #define IXGB_STATUS_LU 0x00000002 | |
286 | #define IXGB_STATUS_AIP 0x00000004 | |
287 | #define IXGB_STATUS_TXOFF 0x00000010 | |
288 | #define IXGB_STATUS_XAUIME 0x00000020 | |
289 | #define IXGB_STATUS_RES 0x00000040 | |
290 | #define IXGB_STATUS_RIS 0x00000080 | |
291 | #define IXGB_STATUS_RIE 0x00000100 | |
292 | #define IXGB_STATUS_RLF 0x00000200 | |
293 | #define IXGB_STATUS_RRF 0x00000400 | |
294 | #define IXGB_STATUS_PCI_SPD 0x00000800 | |
295 | #define IXGB_STATUS_BUS64 0x00001000 | |
296 | #define IXGB_STATUS_PCIX_MODE 0x00002000 | |
297 | #define IXGB_STATUS_PCIX_SPD_MASK 0x0000C000 | |
298 | #define IXGB_STATUS_PCIX_SPD_66 0x00000000 | |
299 | #define IXGB_STATUS_PCIX_SPD_100 0x00004000 | |
300 | #define IXGB_STATUS_PCIX_SPD_133 0x00008000 | |
301 | #define IXGB_STATUS_REV_ID_MASK 0x000F0000 | |
302 | #define IXGB_STATUS_REV_ID_SHIFT 16 | |
303 | ||
304 | /* EECD Bit Masks */ | |
305 | #define IXGB_EECD_SK 0x00000001 | |
306 | #define IXGB_EECD_CS 0x00000002 | |
307 | #define IXGB_EECD_DI 0x00000004 | |
308 | #define IXGB_EECD_DO 0x00000008 | |
309 | #define IXGB_EECD_FWE_MASK 0x00000030 | |
310 | #define IXGB_EECD_FWE_DIS 0x00000010 | |
311 | #define IXGB_EECD_FWE_EN 0x00000020 | |
312 | ||
313 | /* MFS */ | |
314 | #define IXGB_MFS_SHIFT 16 | |
315 | ||
316 | /* Interrupt Register Bit Masks (used for ICR, ICS, IMS, and IMC) */ | |
317 | #define IXGB_INT_TXDW 0x00000001 | |
318 | #define IXGB_INT_TXQE 0x00000002 | |
319 | #define IXGB_INT_LSC 0x00000004 | |
320 | #define IXGB_INT_RXSEQ 0x00000008 | |
321 | #define IXGB_INT_RXDMT0 0x00000010 | |
322 | #define IXGB_INT_RXO 0x00000040 | |
323 | #define IXGB_INT_RXT0 0x00000080 | |
324 | #define IXGB_INT_AUTOSCAN 0x00000200 | |
325 | #define IXGB_INT_GPI0 0x00000800 | |
326 | #define IXGB_INT_GPI1 0x00001000 | |
327 | #define IXGB_INT_GPI2 0x00002000 | |
328 | #define IXGB_INT_GPI3 0x00004000 | |
329 | ||
330 | /* RCTL Bit Masks */ | |
331 | #define IXGB_RCTL_RXEN 0x00000002 | |
332 | #define IXGB_RCTL_SBP 0x00000004 | |
333 | #define IXGB_RCTL_UPE 0x00000008 | |
334 | #define IXGB_RCTL_MPE 0x00000010 | |
335 | #define IXGB_RCTL_RDMTS_MASK 0x00000300 | |
336 | #define IXGB_RCTL_RDMTS_1_2 0x00000000 | |
337 | #define IXGB_RCTL_RDMTS_1_4 0x00000100 | |
338 | #define IXGB_RCTL_RDMTS_1_8 0x00000200 | |
339 | #define IXGB_RCTL_MO_MASK 0x00003000 | |
340 | #define IXGB_RCTL_MO_47_36 0x00000000 | |
341 | #define IXGB_RCTL_MO_46_35 0x00001000 | |
342 | #define IXGB_RCTL_MO_45_34 0x00002000 | |
343 | #define IXGB_RCTL_MO_43_32 0x00003000 | |
344 | #define IXGB_RCTL_MO_SHIFT 12 | |
345 | #define IXGB_RCTL_BAM 0x00008000 | |
346 | #define IXGB_RCTL_BSIZE_MASK 0x00030000 | |
347 | #define IXGB_RCTL_BSIZE_2048 0x00000000 | |
348 | #define IXGB_RCTL_BSIZE_4096 0x00010000 | |
349 | #define IXGB_RCTL_BSIZE_8192 0x00020000 | |
350 | #define IXGB_RCTL_BSIZE_16384 0x00030000 | |
351 | #define IXGB_RCTL_VFE 0x00040000 | |
352 | #define IXGB_RCTL_CFIEN 0x00080000 | |
353 | #define IXGB_RCTL_CFI 0x00100000 | |
354 | #define IXGB_RCTL_RPDA_MASK 0x00600000 | |
355 | #define IXGB_RCTL_RPDA_MC_MAC 0x00000000 | |
356 | #define IXGB_RCTL_MC_ONLY 0x00400000 | |
357 | #define IXGB_RCTL_CFF 0x00800000 | |
358 | #define IXGB_RCTL_SECRC 0x04000000 | |
359 | #define IXGB_RDT_FPDB 0x80000000 | |
360 | ||
361 | #define IXGB_RCTL_IDLE_RX_UNIT 0 | |
362 | ||
363 | /* FCRTL Bit Masks */ | |
364 | #define IXGB_FCRTL_XONE 0x80000000 | |
365 | ||
366 | /* RXDCTL Bit Masks */ | |
367 | #define IXGB_RXDCTL_PTHRESH_MASK 0x000001FF | |
368 | #define IXGB_RXDCTL_PTHRESH_SHIFT 0 | |
369 | #define IXGB_RXDCTL_HTHRESH_MASK 0x0003FE00 | |
370 | #define IXGB_RXDCTL_HTHRESH_SHIFT 9 | |
371 | #define IXGB_RXDCTL_WTHRESH_MASK 0x07FC0000 | |
372 | #define IXGB_RXDCTL_WTHRESH_SHIFT 18 | |
373 | ||
374 | /* RAIDC Bit Masks */ | |
375 | #define IXGB_RAIDC_HIGHTHRS_MASK 0x0000003F | |
376 | #define IXGB_RAIDC_DELAY_MASK 0x000FF800 | |
377 | #define IXGB_RAIDC_DELAY_SHIFT 11 | |
378 | #define IXGB_RAIDC_POLL_MASK 0x1FF00000 | |
379 | #define IXGB_RAIDC_POLL_SHIFT 20 | |
380 | #define IXGB_RAIDC_RXT_GATE 0x40000000 | |
381 | #define IXGB_RAIDC_EN 0x80000000 | |
382 | ||
383 | #define IXGB_RAIDC_POLL_1000_INTERRUPTS_PER_SECOND 1220 | |
384 | #define IXGB_RAIDC_POLL_5000_INTERRUPTS_PER_SECOND 244 | |
385 | #define IXGB_RAIDC_POLL_10000_INTERRUPTS_PER_SECOND 122 | |
386 | #define IXGB_RAIDC_POLL_20000_INTERRUPTS_PER_SECOND 61 | |
387 | ||
388 | /* RXCSUM Bit Masks */ | |
389 | #define IXGB_RXCSUM_IPOFL 0x00000100 | |
390 | #define IXGB_RXCSUM_TUOFL 0x00000200 | |
391 | ||
392 | /* RAH Bit Masks */ | |
393 | #define IXGB_RAH_ASEL_MASK 0x00030000 | |
394 | #define IXGB_RAH_ASEL_DEST 0x00000000 | |
395 | #define IXGB_RAH_ASEL_SRC 0x00010000 | |
396 | #define IXGB_RAH_AV 0x80000000 | |
397 | ||
398 | /* TCTL Bit Masks */ | |
399 | #define IXGB_TCTL_TCE 0x00000001 | |
400 | #define IXGB_TCTL_TXEN 0x00000002 | |
401 | #define IXGB_TCTL_TPDE 0x00000004 | |
402 | ||
403 | #define IXGB_TCTL_IDLE_TX_UNIT 0 | |
404 | ||
405 | /* TXDCTL Bit Masks */ | |
406 | #define IXGB_TXDCTL_PTHRESH_MASK 0x0000007F | |
407 | #define IXGB_TXDCTL_HTHRESH_MASK 0x00007F00 | |
408 | #define IXGB_TXDCTL_HTHRESH_SHIFT 8 | |
409 | #define IXGB_TXDCTL_WTHRESH_MASK 0x007F0000 | |
410 | #define IXGB_TXDCTL_WTHRESH_SHIFT 16 | |
411 | ||
412 | /* TSPMT Bit Masks */ | |
413 | #define IXGB_TSPMT_TSMT_MASK 0x0000FFFF | |
414 | #define IXGB_TSPMT_TSPBP_MASK 0xFFFF0000 | |
415 | #define IXGB_TSPMT_TSPBP_SHIFT 16 | |
416 | ||
417 | /* PAP Bit Masks */ | |
418 | #define IXGB_PAP_TXPC_MASK 0x0000FFFF | |
419 | #define IXGB_PAP_TXPV_MASK 0x000F0000 | |
420 | #define IXGB_PAP_TXPV_10G 0x00000000 | |
421 | #define IXGB_PAP_TXPV_1G 0x00010000 | |
422 | #define IXGB_PAP_TXPV_2G 0x00020000 | |
423 | #define IXGB_PAP_TXPV_3G 0x00030000 | |
424 | #define IXGB_PAP_TXPV_4G 0x00040000 | |
425 | #define IXGB_PAP_TXPV_5G 0x00050000 | |
426 | #define IXGB_PAP_TXPV_6G 0x00060000 | |
427 | #define IXGB_PAP_TXPV_7G 0x00070000 | |
428 | #define IXGB_PAP_TXPV_8G 0x00080000 | |
429 | #define IXGB_PAP_TXPV_9G 0x00090000 | |
430 | #define IXGB_PAP_TXPV_WAN 0x000F0000 | |
431 | ||
432 | /* PCSC1 Bit Masks */ | |
433 | #define IXGB_PCSC1_LOOPBACK 0x00004000 | |
434 | ||
435 | /* PCSC2 Bit Masks */ | |
436 | #define IXGB_PCSC2_PCS_TYPE_MASK 0x00000003 | |
437 | #define IXGB_PCSC2_PCS_TYPE_10GBX 0x00000001 | |
438 | ||
439 | /* PCSS1 Bit Masks */ | |
440 | #define IXGB_PCSS1_LOCAL_FAULT 0x00000080 | |
441 | #define IXGB_PCSS1_RX_LINK_STATUS 0x00000004 | |
442 | ||
443 | /* PCSS2 Bit Masks */ | |
444 | #define IXGB_PCSS2_DEV_PRES_MASK 0x0000C000 | |
445 | #define IXGB_PCSS2_DEV_PRES 0x00004000 | |
446 | #define IXGB_PCSS2_TX_LF 0x00000800 | |
447 | #define IXGB_PCSS2_RX_LF 0x00000400 | |
448 | #define IXGB_PCSS2_10GBW 0x00000004 | |
449 | #define IXGB_PCSS2_10GBX 0x00000002 | |
450 | #define IXGB_PCSS2_10GBR 0x00000001 | |
451 | ||
452 | /* XPCSS Bit Masks */ | |
453 | #define IXGB_XPCSS_ALIGN_STATUS 0x00001000 | |
454 | #define IXGB_XPCSS_PATTERN_TEST 0x00000800 | |
455 | #define IXGB_XPCSS_LANE_3_SYNC 0x00000008 | |
456 | #define IXGB_XPCSS_LANE_2_SYNC 0x00000004 | |
457 | #define IXGB_XPCSS_LANE_1_SYNC 0x00000002 | |
458 | #define IXGB_XPCSS_LANE_0_SYNC 0x00000001 | |
459 | ||
460 | /* XPCSTC Bit Masks */ | |
461 | #define IXGB_XPCSTC_BERT_TRIG 0x00200000 | |
462 | #define IXGB_XPCSTC_BERT_SST 0x00100000 | |
463 | #define IXGB_XPCSTC_BERT_PSZ_MASK 0x000C0000 | |
464 | #define IXGB_XPCSTC_BERT_PSZ_SHIFT 17 | |
465 | #define IXGB_XPCSTC_BERT_PSZ_INF 0x00000003 | |
466 | #define IXGB_XPCSTC_BERT_PSZ_68 0x00000001 | |
467 | #define IXGB_XPCSTC_BERT_PSZ_1028 0x00000000 | |
468 | ||
469 | /* MSCA bit Masks */ | |
470 | /* New Protocol Address */ | |
471 | #define IXGB_MSCA_NP_ADDR_MASK 0x0000FFFF | |
472 | #define IXGB_MSCA_NP_ADDR_SHIFT 0 | |
473 | /* Either Device Type or Register Address,depending on ST_CODE */ | |
474 | #define IXGB_MSCA_DEV_TYPE_MASK 0x001F0000 | |
475 | #define IXGB_MSCA_DEV_TYPE_SHIFT 16 | |
476 | #define IXGB_MSCA_PHY_ADDR_MASK 0x03E00000 | |
477 | #define IXGB_MSCA_PHY_ADDR_SHIFT 21 | |
478 | #define IXGB_MSCA_OP_CODE_MASK 0x0C000000 | |
479 | /* OP_CODE == 00, Address cycle, New Protocol */ | |
480 | /* OP_CODE == 01, Write operation */ | |
481 | /* OP_CODE == 10, Read operation */ | |
482 | /* OP_CODE == 11, Read, auto increment, New Protocol */ | |
483 | #define IXGB_MSCA_ADDR_CYCLE 0x00000000 | |
484 | #define IXGB_MSCA_WRITE 0x04000000 | |
485 | #define IXGB_MSCA_READ 0x08000000 | |
486 | #define IXGB_MSCA_READ_AUTOINC 0x0C000000 | |
487 | #define IXGB_MSCA_OP_CODE_SHIFT 26 | |
488 | #define IXGB_MSCA_ST_CODE_MASK 0x30000000 | |
489 | /* ST_CODE == 00, New Protocol */ | |
490 | /* ST_CODE == 01, Old Protocol */ | |
491 | #define IXGB_MSCA_NEW_PROTOCOL 0x00000000 | |
492 | #define IXGB_MSCA_OLD_PROTOCOL 0x10000000 | |
493 | #define IXGB_MSCA_ST_CODE_SHIFT 28 | |
494 | /* Initiate command, self-clearing when command completes */ | |
495 | #define IXGB_MSCA_MDI_COMMAND 0x40000000 | |
496 | /*MDI In Progress Enable. */ | |
497 | #define IXGB_MSCA_MDI_IN_PROG_EN 0x80000000 | |
498 | ||
499 | /* MSRWD bit masks */ | |
500 | #define IXGB_MSRWD_WRITE_DATA_MASK 0x0000FFFF | |
501 | #define IXGB_MSRWD_WRITE_DATA_SHIFT 0 | |
502 | #define IXGB_MSRWD_READ_DATA_MASK 0xFFFF0000 | |
503 | #define IXGB_MSRWD_READ_DATA_SHIFT 16 | |
504 | ||
505 | /* Definitions for the optics devices on the MDIO bus. */ | |
506 | #define IXGB_PHY_ADDRESS 0x0 /* Single PHY, multiple "Devices" */ | |
507 | ||
508 | /* Standard five-bit Device IDs. See IEEE 802.3ae, clause 45 */ | |
509 | #define MDIO_PMA_PMD_DID 0x01 | |
510 | #define MDIO_WIS_DID 0x02 | |
511 | #define MDIO_PCS_DID 0x03 | |
512 | #define MDIO_XGXS_DID 0x04 | |
513 | ||
514 | /* Standard PMA/PMD registers and bit definitions. */ | |
515 | /* Note: This is a very limited set of definitions, */ | |
516 | /* only implemented features are defined. */ | |
517 | #define MDIO_PMA_PMD_CR1 0x0000 | |
518 | #define MDIO_PMA_PMD_CR1_RESET 0x8000 | |
519 | ||
520 | #define MDIO_PMA_PMD_XPAK_VENDOR_NAME 0x803A /* XPAK/XENPAK devices only */ | |
521 | ||
522 | /* Vendor-specific MDIO registers */ | |
523 | #define G6XXX_PMA_PMD_VS1 0xC001 /* Vendor-specific register */ | |
524 | #define G6XXX_XGXS_XAUI_VS2 0x18 /* Vendor-specific register */ | |
525 | ||
526 | #define G6XXX_PMA_PMD_VS1_PLL_RESET 0x80 | |
527 | #define G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET 0x00 | |
528 | #define G6XXX_XGXS_XAUI_VS2_INPUT_MASK 0x0F /* XAUI lanes synchronized */ | |
529 | ||
530 | /* Layout of a single receive descriptor. The controller assumes that this | |
531 | * structure is packed into 16 bytes, which is a safe assumption with most | |
532 | * compilers. However, some compilers may insert padding between the fields, | |
533 | * in which case the structure must be packed in some compiler-specific | |
534 | * manner. */ | |
535 | struct ixgb_rx_desc { | |
536 | uint64_t buff_addr; | |
537 | uint16_t length; | |
538 | uint16_t reserved; | |
539 | uint8_t status; | |
540 | uint8_t errors; | |
541 | uint16_t special; | |
542 | }; | |
543 | ||
544 | #define IXGB_RX_DESC_STATUS_DD 0x01 | |
545 | #define IXGB_RX_DESC_STATUS_EOP 0x02 | |
546 | #define IXGB_RX_DESC_STATUS_IXSM 0x04 | |
547 | #define IXGB_RX_DESC_STATUS_VP 0x08 | |
548 | #define IXGB_RX_DESC_STATUS_TCPCS 0x20 | |
549 | #define IXGB_RX_DESC_STATUS_IPCS 0x40 | |
550 | #define IXGB_RX_DESC_STATUS_PIF 0x80 | |
551 | ||
552 | #define IXGB_RX_DESC_ERRORS_CE 0x01 | |
553 | #define IXGB_RX_DESC_ERRORS_SE 0x02 | |
554 | #define IXGB_RX_DESC_ERRORS_P 0x08 | |
555 | #define IXGB_RX_DESC_ERRORS_TCPE 0x20 | |
556 | #define IXGB_RX_DESC_ERRORS_IPE 0x40 | |
557 | #define IXGB_RX_DESC_ERRORS_RXE 0x80 | |
558 | ||
559 | #define IXGB_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ | |
560 | #define IXGB_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ | |
561 | #define IXGB_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ | |
562 | ||
563 | /* Layout of a single transmit descriptor. The controller assumes that this | |
564 | * structure is packed into 16 bytes, which is a safe assumption with most | |
565 | * compilers. However, some compilers may insert padding between the fields, | |
566 | * in which case the structure must be packed in some compiler-specific | |
567 | * manner. */ | |
568 | struct ixgb_tx_desc { | |
569 | uint64_t buff_addr; | |
570 | uint32_t cmd_type_len; | |
571 | uint8_t status; | |
572 | uint8_t popts; | |
573 | uint16_t vlan; | |
574 | }; | |
575 | ||
576 | #define IXGB_TX_DESC_LENGTH_MASK 0x000FFFFF | |
577 | #define IXGB_TX_DESC_TYPE_MASK 0x00F00000 | |
578 | #define IXGB_TX_DESC_TYPE_SHIFT 20 | |
579 | #define IXGB_TX_DESC_CMD_MASK 0xFF000000 | |
580 | #define IXGB_TX_DESC_CMD_SHIFT 24 | |
581 | #define IXGB_TX_DESC_CMD_EOP 0x01000000 | |
582 | #define IXGB_TX_DESC_CMD_TSE 0x04000000 | |
583 | #define IXGB_TX_DESC_CMD_RS 0x08000000 | |
584 | #define IXGB_TX_DESC_CMD_VLE 0x40000000 | |
585 | #define IXGB_TX_DESC_CMD_IDE 0x80000000 | |
586 | ||
587 | #define IXGB_TX_DESC_TYPE 0x00100000 | |
588 | ||
589 | #define IXGB_TX_DESC_STATUS_DD 0x01 | |
590 | ||
591 | #define IXGB_TX_DESC_POPTS_IXSM 0x01 | |
592 | #define IXGB_TX_DESC_POPTS_TXSM 0x02 | |
593 | #define IXGB_TX_DESC_SPECIAL_PRI_SHIFT IXGB_RX_DESC_SPECIAL_PRI_SHIFT /* Priority is in upper 3 of 16 */ | |
594 | ||
595 | struct ixgb_context_desc { | |
596 | uint8_t ipcss; | |
597 | uint8_t ipcso; | |
598 | uint16_t ipcse; | |
599 | uint8_t tucss; | |
600 | uint8_t tucso; | |
601 | uint16_t tucse; | |
602 | uint32_t cmd_type_len; | |
603 | uint8_t status; | |
604 | uint8_t hdr_len; | |
605 | uint16_t mss; | |
606 | }; | |
607 | ||
608 | #define IXGB_CONTEXT_DESC_CMD_TCP 0x01000000 | |
609 | #define IXGB_CONTEXT_DESC_CMD_IP 0x02000000 | |
610 | #define IXGB_CONTEXT_DESC_CMD_TSE 0x04000000 | |
611 | #define IXGB_CONTEXT_DESC_CMD_RS 0x08000000 | |
612 | #define IXGB_CONTEXT_DESC_CMD_IDE 0x80000000 | |
613 | ||
614 | #define IXGB_CONTEXT_DESC_TYPE 0x00000000 | |
615 | ||
616 | #define IXGB_CONTEXT_DESC_STATUS_DD 0x01 | |
617 | ||
618 | /* Filters */ | |
619 | #define IXGB_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ | |
620 | #define IXGB_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ | |
621 | #define IXGB_RAR_ENTRIES 3 /* Number of entries in Rx Address array */ | |
622 | ||
623 | #define IXGB_MEMORY_REGISTER_BASE_ADDRESS 0 | |
624 | #define ENET_HEADER_SIZE 14 | |
625 | #define ENET_FCS_LENGTH 4 | |
626 | #define IXGB_MAX_NUM_MULTICAST_ADDRESSES 128 | |
627 | #define IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS 60 | |
628 | #define IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS 1514 | |
629 | #define IXGB_MAX_JUMBO_FRAME_SIZE 0x3F00 | |
630 | ||
631 | /* Phy Addresses */ | |
632 | #define IXGB_OPTICAL_PHY_ADDR 0x0 /* Optical Module phy address */ | |
633 | #define IXGB_XAUII_PHY_ADDR 0x1 /* Xauii transceiver phy address */ | |
634 | #define IXGB_DIAG_PHY_ADDR 0x1F /* Diagnostic Device phy address */ | |
635 | ||
636 | /* This structure takes a 64k flash and maps it for identification commands */ | |
637 | struct ixgb_flash_buffer { | |
638 | uint8_t manufacturer_id; | |
639 | uint8_t device_id; | |
640 | uint8_t filler1[0x2AA8]; | |
641 | uint8_t cmd2; | |
642 | uint8_t filler2[0x2AAA]; | |
643 | uint8_t cmd1; | |
644 | uint8_t filler3[0xAAAA]; | |
645 | }; | |
646 | ||
647 | /* | |
648 | * This is a little-endian specific check. | |
649 | */ | |
650 | #define IS_MULTICAST(Address) \ | |
651 | (boolean_t)(((uint8_t *)(Address))[0] & ((uint8_t)0x01)) | |
652 | ||
653 | /* | |
654 | * Check whether an address is broadcast. | |
655 | */ | |
656 | #define IS_BROADCAST(Address) \ | |
657 | ((((uint8_t *)(Address))[0] == ((uint8_t)0xff)) && (((uint8_t *)(Address))[1] == ((uint8_t)0xff))) | |
658 | ||
659 | /* Flow control parameters */ | |
660 | struct ixgb_fc { | |
661 | uint32_t high_water; /* Flow Control High-water */ | |
662 | uint32_t low_water; /* Flow Control Low-water */ | |
663 | uint16_t pause_time; /* Flow Control Pause timer */ | |
664 | boolean_t send_xon; /* Flow control send XON */ | |
665 | ixgb_fc_type type; /* Type of flow control */ | |
666 | }; | |
667 | ||
668 | /* The historical defaults for the flow control values are given below. */ | |
669 | #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ | |
670 | #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ | |
671 | #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ | |
672 | ||
673 | /* Phy definitions */ | |
674 | #define IXGB_MAX_PHY_REG_ADDRESS 0xFFFF | |
675 | #define IXGB_MAX_PHY_ADDRESS 31 | |
676 | #define IXGB_MAX_PHY_DEV_TYPE 31 | |
677 | ||
678 | /* Bus parameters */ | |
679 | struct ixgb_bus { | |
680 | ixgb_bus_speed speed; | |
681 | ixgb_bus_width width; | |
682 | ixgb_bus_type type; | |
683 | }; | |
684 | ||
685 | struct ixgb_hw { | |
686 | uint8_t __iomem *hw_addr;/* Base Address of the hardware */ | |
687 | void *back; /* Pointer to OS-dependent struct */ | |
688 | struct ixgb_fc fc; /* Flow control parameters */ | |
689 | struct ixgb_bus bus; /* Bus parameters */ | |
690 | uint32_t phy_id; /* Phy Identifier */ | |
691 | uint32_t phy_addr; /* XGMII address of Phy */ | |
692 | ixgb_mac_type mac_type; /* Identifier for MAC controller */ | |
693 | ixgb_phy_type phy_type; /* Transceiver/phy identifier */ | |
694 | uint32_t max_frame_size; /* Maximum frame size supported */ | |
695 | uint32_t mc_filter_type; /* Multicast filter hash type */ | |
696 | uint32_t num_mc_addrs; /* Number of current Multicast addrs */ | |
697 | uint8_t curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS]; /* Individual address currently programmed in MAC */ | |
698 | uint32_t num_tx_desc; /* Number of Transmit descriptors */ | |
699 | uint32_t num_rx_desc; /* Number of Receive descriptors */ | |
700 | uint32_t rx_buffer_size; /* Size of Receive buffer */ | |
701 | boolean_t link_up; /* TRUE if link is valid */ | |
702 | boolean_t adapter_stopped; /* State of adapter */ | |
703 | uint16_t device_id; /* device id from PCI configuration space */ | |
704 | uint16_t vendor_id; /* vendor id from PCI configuration space */ | |
705 | uint8_t revision_id; /* revision id from PCI configuration space */ | |
706 | uint16_t subsystem_vendor_id; /* subsystem vendor id from PCI configuration space */ | |
707 | uint16_t subsystem_id; /* subsystem id from PCI configuration space */ | |
708 | uint32_t bar0; /* Base Address registers */ | |
709 | uint32_t bar1; | |
710 | uint32_t bar2; | |
711 | uint32_t bar3; | |
712 | uint16_t pci_cmd_word; /* PCI command register id from PCI configuration space */ | |
713 | uint16_t eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init time */ | |
714 | unsigned long io_base; /* Our I/O mapped location */ | |
715 | uint32_t lastLFC; | |
716 | uint32_t lastRFC; | |
717 | }; | |
718 | ||
719 | /* Statistics reported by the hardware */ | |
720 | struct ixgb_hw_stats { | |
721 | uint64_t tprl; | |
722 | uint64_t tprh; | |
723 | uint64_t gprcl; | |
724 | uint64_t gprch; | |
725 | uint64_t bprcl; | |
726 | uint64_t bprch; | |
727 | uint64_t mprcl; | |
728 | uint64_t mprch; | |
729 | uint64_t uprcl; | |
730 | uint64_t uprch; | |
731 | uint64_t vprcl; | |
732 | uint64_t vprch; | |
733 | uint64_t jprcl; | |
734 | uint64_t jprch; | |
735 | uint64_t gorcl; | |
736 | uint64_t gorch; | |
737 | uint64_t torl; | |
738 | uint64_t torh; | |
739 | uint64_t rnbc; | |
740 | uint64_t ruc; | |
741 | uint64_t roc; | |
742 | uint64_t rlec; | |
743 | uint64_t crcerrs; | |
744 | uint64_t icbc; | |
745 | uint64_t ecbc; | |
746 | uint64_t mpc; | |
747 | uint64_t tptl; | |
748 | uint64_t tpth; | |
749 | uint64_t gptcl; | |
750 | uint64_t gptch; | |
751 | uint64_t bptcl; | |
752 | uint64_t bptch; | |
753 | uint64_t mptcl; | |
754 | uint64_t mptch; | |
755 | uint64_t uptcl; | |
756 | uint64_t uptch; | |
757 | uint64_t vptcl; | |
758 | uint64_t vptch; | |
759 | uint64_t jptcl; | |
760 | uint64_t jptch; | |
761 | uint64_t gotcl; | |
762 | uint64_t gotch; | |
763 | uint64_t totl; | |
764 | uint64_t toth; | |
765 | uint64_t dc; | |
766 | uint64_t plt64c; | |
767 | uint64_t tsctc; | |
768 | uint64_t tsctfc; | |
769 | uint64_t ibic; | |
770 | uint64_t rfc; | |
771 | uint64_t lfc; | |
772 | uint64_t pfrc; | |
773 | uint64_t pftc; | |
774 | uint64_t mcfrc; | |
775 | uint64_t mcftc; | |
776 | uint64_t xonrxc; | |
777 | uint64_t xontxc; | |
778 | uint64_t xoffrxc; | |
779 | uint64_t xofftxc; | |
780 | uint64_t rjc; | |
781 | }; | |
782 | ||
783 | /* Function Prototypes */ | |
784 | extern boolean_t ixgb_adapter_stop(struct ixgb_hw *hw); | |
785 | extern boolean_t ixgb_init_hw(struct ixgb_hw *hw); | |
786 | extern boolean_t ixgb_adapter_start(struct ixgb_hw *hw); | |
1da177e4 LT |
787 | extern void ixgb_check_for_link(struct ixgb_hw *hw); |
788 | extern boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw); | |
1da177e4 LT |
789 | |
790 | extern void ixgb_rar_set(struct ixgb_hw *hw, | |
791 | uint8_t *addr, | |
792 | uint32_t index); | |
793 | ||
794 | ||
795 | /* Filters (multicast, vlan, receive) */ | |
796 | extern void ixgb_mc_addr_list_update(struct ixgb_hw *hw, | |
797 | uint8_t *mc_addr_list, | |
798 | uint32_t mc_addr_count, | |
799 | uint32_t pad); | |
800 | ||
801 | /* Vfta functions */ | |
802 | extern void ixgb_write_vfta(struct ixgb_hw *hw, | |
803 | uint32_t offset, | |
804 | uint32_t value); | |
805 | ||
1da177e4 LT |
806 | /* Access functions to eeprom data */ |
807 | void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t *mac_addr); | |
1da177e4 | 808 | uint32_t ixgb_get_ee_pba_number(struct ixgb_hw *hw); |
1da177e4 | 809 | uint16_t ixgb_get_ee_device_id(struct ixgb_hw *hw); |
1da177e4 LT |
810 | boolean_t ixgb_get_eeprom_data(struct ixgb_hw *hw); |
811 | uint16_t ixgb_get_eeprom_word(struct ixgb_hw *hw, uint16_t index); | |
812 | ||
813 | /* Everything else */ | |
814 | void ixgb_led_on(struct ixgb_hw *hw); | |
815 | void ixgb_led_off(struct ixgb_hw *hw); | |
816 | void ixgb_write_pci_cfg(struct ixgb_hw *hw, | |
817 | uint32_t reg, | |
818 | uint16_t * value); | |
819 | ||
820 | ||
821 | #endif /* _IXGB_HW_H_ */ |