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ixgbe: DCB, set minimum bandwidth per traffic class
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
f62bbb5e 31#include <linux/bitops.h>
9a799d71
AK		 32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
b25ebfd2 35#include <linux/cpumask.h>
6fabd715 36#include <linux/aer.h>
f62bbb5e 37#include <linux/if_vlan.h>
9a799d71
AK		 38
39#include "ixgbe_type.h"
40#include "ixgbe_common.h"
2f90b865 41#include "ixgbe_dcb.h"
eacd73f7
YZ		 42#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
43#define IXGBE_FCOE
44#include "ixgbe_fcoe.h"
45#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332 46#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 47#include <linux/dca.h>
48#endif
9a799d71 49
849c4542
ET		 50/* common prefix used by pr_<> macros */
51#undef pr_fmt
52#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9a799d71
AK		 53
54/* TX/RX descriptor defines */
6bacb300 55#define IXGBE_DEFAULT_TXD 512
9a799d71
AK		 56#define IXGBE_MAX_TXD 4096
57#define IXGBE_MIN_TXD 64
58
6bacb300 59#define IXGBE_DEFAULT_RXD 512
9a799d71
AK		 60#define IXGBE_MAX_RXD 4096
61#define IXGBE_MIN_RXD 64
62
9a799d71 63/* flow control */
2b9ade93 64#define IXGBE_MIN_FCRTL 0x40
9a799d71 65#define IXGBE_MAX_FCRTL 0x7FF80
2b9ade93 66#define IXGBE_MIN_FCRTH 0x600
9a799d71 67#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93 68#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71
AK		 69#define IXGBE_MIN_FCPAUSE 0
70#define IXGBE_MAX_FCPAUSE 0xFFFF
71
72/* Supported Rx Buffer Sizes */
13958070 73#define IXGBE_RXBUFFER_512 512 /* Used for packet split */
9a799d71 74#define IXGBE_RXBUFFER_2048 2048
e76678dd
AD		 75#define IXGBE_RXBUFFER_4096 4096
76#define IXGBE_RXBUFFER_8192 8192
32344a39 77#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71 78
13958070
AD		 79/*
80 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
81 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
82 * this adds up to 512 bytes of extra data meaning the smallest allocation
83 * we could have is 1K.
84 * i.e. RXBUFFER_512 --> size-1024 slab
85 */
86#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
9a799d71
AK		 87
88#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
89
9a799d71
AK		 90/* How many Rx Buffers do we bundle into one write to the hardware ? */
91#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
92
93#define IXGBE_TX_FLAGS_CSUM (u32)(1)
94#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
95#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
96#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
eacd73f7
YZ		 97#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
98#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
9a799d71 99#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
2f90b865 100#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
9a799d71
AK		 101#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
102
0a924578
PWJ		 103#define IXGBE_MAX_RSC_INT_RATE 162760
104
7f870475
GR		 105#define IXGBE_MAX_VF_MC_ENTRIES 30
106#define IXGBE_MAX_VF_FUNCTIONS 64
107#define IXGBE_MAX_VFTA_ENTRIES 128
108#define MAX_EMULATION_MAC_ADDRS 16
109#define VMDQ_P(p) ((p) + adapter->num_vfs)
110
111struct vf_data_storage {
112 unsigned char vf_mac_addresses[ETH_ALEN];
113 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
114 u16 num_vf_mc_hashes;
115 u16 default_vf_vlan_id;
116 u16 vlans_enabled;
7f870475 117 bool clear_to_send;
7f01648a 118 bool pf_set_mac;
7f01648a
GR		 119 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
120 u16 pf_qos;
7f870475
GR		 121};
122
9a799d71
AK		 123/* wrapper around a pointer to a socket buffer,
124 * so a DMA handle can be stored along with the buffer */
125struct ixgbe_tx_buffer {
126 struct sk_buff *skb;
127 dma_addr_t dma;
128 unsigned long time_stamp;
129 u16 length;
130 u16 next_to_watch;
8ad494b0
AD		 131 unsigned int bytecount;
132 u16 gso_segs;
133 u8 mapped_as_page;
9a799d71
AK		 134};
135
136struct ixgbe_rx_buffer {
137 struct sk_buff *skb;
138 dma_addr_t dma;
139 struct page *page;
140 dma_addr_t page_dma;
762f4c57 141 unsigned int page_offset;
9a799d71
AK		 142};
143
144struct ixgbe_queue_stats {
145 u64 packets;
146 u64 bytes;
147};
148
5b7da515
AD		 149struct ixgbe_tx_queue_stats {
150 u64 restart_queue;
151 u64 tx_busy;
c84d324c
JF		 152 u64 completed;
153 u64 tx_done_old;
5b7da515
AD		 154};
155
156struct ixgbe_rx_queue_stats {
157 u64 rsc_count;
158 u64 rsc_flush;
159 u64 non_eop_descs;
160 u64 alloc_rx_page_failed;
161 u64 alloc_rx_buff_failed;
162};
163
7d637bcc
AD		 164enum ixbge_ring_state_t {
165 __IXGBE_TX_FDIR_INIT_DONE,
166 __IXGBE_TX_DETECT_HANG,
c84d324c 167 __IXGBE_HANG_CHECK_ARMED,
7d637bcc
AD		 168 __IXGBE_RX_PS_ENABLED,
169 __IXGBE_RX_RSC_ENABLED,
170};
171
172#define ring_is_ps_enabled(ring) \
173 test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
174#define set_ring_ps_enabled(ring) \
175 set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
176#define clear_ring_ps_enabled(ring) \
177 clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
178#define check_for_tx_hang(ring) \
179 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
180#define set_check_for_tx_hang(ring) \
181 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
182#define clear_check_for_tx_hang(ring) \
183 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
184#define ring_is_rsc_enabled(ring) \
185 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
186#define set_ring_rsc_enabled(ring) \
187 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
188#define clear_ring_rsc_enabled(ring) \
189 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
9a799d71 190struct ixgbe_ring {
9a799d71 191 void *desc; /* descriptor ring memory */
b6ec895e 192 struct device *dev; /* device for DMA mapping */
fc77dc3c 193 struct net_device *netdev; /* netdev ring belongs to */
9a799d71
AK		 194 union {
195 struct ixgbe_tx_buffer *tx_buffer_info;
196 struct ixgbe_rx_buffer *rx_buffer_info;
197 };
7d637bcc 198 unsigned long state;
ae540af1
JB		 199 u8 atr_sample_rate;
200 u8 atr_count;
201 u16 count; /* amount of descriptors */
202 u16 rx_buf_len;
203 u16 next_to_use;
204 u16 next_to_clean;
205
206 u8 queue_index; /* needed for multiqueue queue management */
7d637bcc
AD		 207 u8 reg_idx; /* holds the special value that gets
208 * the hardware register offset
209 * associated with this ring, which is
210 * different for DCB and RSS modes
211 */
e5b64635 212 u8 dcb_tc;
7d637bcc
AD		 213
214 u16 work_limit; /* max work per interrupt */
9a799d71 215
84ea2591 216 u8 __iomem *tail;
9a799d71 217
f494e8fa
AV		 218 unsigned int total_bytes;
219 unsigned int total_packets;
9a799d71
AK		 220
221 struct ixgbe_queue_stats stats;
de1036b1 222 struct u64_stats_sync syncp;
5b7da515
AD		 223 union {
224 struct ixgbe_tx_queue_stats tx_stats;
225 struct ixgbe_rx_queue_stats rx_stats;
226 };
5b7da515 227 int numa_node;
ae540af1
JB		 228 unsigned int size; /* length in bytes */
229 dma_addr_t dma; /* phys. address of descriptor ring */
1a51502b 230 struct rcu_head rcu;
33cf09c9 231 struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
7ca3bc58 232} ____cacheline_internodealigned_in_smp;
9a799d71 233
c7e4358a
SN		 234enum ixgbe_ring_f_enum {
235 RING_F_NONE = 0,
236 RING_F_DCB,
7f870475 237 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
c7e4358a 238 RING_F_RSS,
c4cf55e5 239 RING_F_FDIR,
0331a832
YZ		 240#ifdef IXGBE_FCOE
241 RING_F_FCOE,
242#endif /* IXGBE_FCOE */
c7e4358a
SN		 243
244 RING_F_ARRAY_SIZE /* must be last in enum set */
245};
246
e5b64635 247#define IXGBE_MAX_DCB_INDICES 64
021230d4 248#define IXGBE_MAX_RSS_INDICES 16
7f870475 249#define IXGBE_MAX_VMDQ_INDICES 64
c4cf55e5 250#define IXGBE_MAX_FDIR_INDICES 64
0331a832
YZ		 251#ifdef IXGBE_FCOE
252#define IXGBE_MAX_FCOE_INDICES 8
e0fce695
JF		 253#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
254#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
255#else
256#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
257#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
0331a832 258#endif /* IXGBE_FCOE */
021230d4
AV		 259struct ixgbe_ring_feature {
260 int indices;
261 int mask;
7ca3bc58 262} ____cacheline_internodealigned_in_smp;
021230d4 263
021230d4 264
2f90b865
AD		 265#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
266 ? 8 : 1)
267#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
268
021230d4
AV		 269/* MAX_MSIX_Q_VECTORS of these are allocated,
270 * but we only use one per queue-specific vector.
271 */
272struct ixgbe_q_vector {
273 struct ixgbe_adapter *adapter;
fe49f04a
AD		 274 unsigned int v_idx; /* index of q_vector within array, also used for
275 * finding the bit in EICR and friends that
276 * represents the vector for this ring */
33cf09c9
AD		 277#ifdef CONFIG_IXGBE_DCA
278 int cpu; /* CPU for DCA */
279#endif
021230d4
AV		 280 struct napi_struct napi;
281 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
282 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
283 u8 rxr_count; /* Rx ring count assigned to this vector */
284 u8 txr_count; /* Tx ring count assigned to this vector */
30efa5a3
JB		 285 u8 tx_itr;
286 u8 rx_itr;
021230d4 287 u32 eitr;
b25ebfd2 288 cpumask_var_t affinity_mask;
d0759ebb 289 char name[IFNAMSIZ + 9];
021230d4
AV		 290};
291
9a799d71 292/* Helper macros to switch between ints/sec and what the register uses.
509ee935
JB		 293 * And yes, it's the same math going both ways. The lowest value
294 * supported by all of the ixgbe hardware is 8.
9a799d71
AK		 295 */
296#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
509ee935 297 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
9a799d71
AK		 298#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
299
300#define IXGBE_DESC_UNUSED(R) \
301 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
302 (R)->next_to_clean - (R)->next_to_use - 1)
303
304#define IXGBE_RX_DESC_ADV(R, i) \
31f05a2d 305 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
9a799d71 306#define IXGBE_TX_DESC_ADV(R, i) \
31f05a2d 307 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
9a799d71 308#define IXGBE_TX_CTXTDESC_ADV(R, i) \
31f05a2d 309 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
9a799d71
AK		 310
311#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
63f39bd1
YZ		 312#ifdef IXGBE_FCOE
313/* Use 3K as the baby jumbo frame size for FCoE */
314#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
315#endif /* IXGBE_FCOE */
9a799d71 316
021230d4
AV		 317#define OTHER_VECTOR 1
318#define NON_Q_VECTORS (OTHER_VECTOR)
319
e8e26350
PW		 320#define MAX_MSIX_VECTORS_82599 64
321#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c
PWJ		 322#define MAX_MSIX_VECTORS_82598 18
323#define MAX_MSIX_Q_VECTORS_82598 16
324
e8e26350
PW		 325#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
326#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c 327
021230d4 328#define MIN_MSIX_Q_VECTORS 2
021230d4
AV		 329#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
330
9a799d71
AK		 331/* board specific private data structure */
332struct ixgbe_adapter {
333 struct timer_list watchdog_timer;
f62bbb5e 334 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
9a799d71 335 u16 bd_number;
9a799d71 336 struct work_struct reset_task;
7a921c93 337 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
d033d526
JF		 338
339 /* DCB parameters */
340 struct ieee_pfc *ixgbe_ieee_pfc;
341 struct ieee_ets *ixgbe_ieee_ets;
2f90b865
AD		 342 struct ixgbe_dcb_config dcb_cfg;
343 struct ixgbe_dcb_config temp_dcb_cfg;
344 u8 dcb_set_bitmap;
3032309b 345 u8 dcbx_cap;
264857b8 346 enum ixgbe_fc_mode last_lfc_mode;
9a799d71 347
f494e8fa 348 /* Interrupt Throttle Rate */
f7554a2b
NS		 349 u32 rx_itr_setting;
350 u32 tx_itr_setting;
f494e8fa
AV		 351 u16 eitr_low;
352 u16 eitr_high;
353
9a799d71 354 /* TX */
4a0b9ca0 355 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 356 int num_tx_queues;
9a799d71
AK		 357 u32 tx_timeout_count;
358 bool detect_tx_hung;
359
7ca3bc58
JB		 360 u64 restart_queue;
361 u64 lsc_int;
362
9a799d71 363 /* RX */
4a0b9ca0 364 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 365 int num_rx_queues;
7f870475
GR		 366 int num_rx_pools; /* == num_rx_queues in 82598 */
367 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
9a799d71 368 u64 hw_csum_rx_error;
e8e26350 369 u64 hw_rx_no_dma_resources;
9a799d71 370 u64 non_eop_descs;
021230d4 371 int num_msix_vectors;
eb7f139c 372 int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a 373 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
9a799d71
AK		 374 struct msix_entry *msix_entries;
375
9a799d71
AK		 376 u32 alloc_rx_page_failed;
377 u32 alloc_rx_buff_failed;
378
021230d4
AV		 379 /* Some features need tri-state capability,
380 * thus the additional *_CAPABLE flags.
381 */
9a799d71 382 u32 flags;
96b0e0f6
JB		 383#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
384#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
385#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
386#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
387#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
388#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
389#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
390#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
391#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
392#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
393#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
394#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
395#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
e8e26350 396#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
96b0e0f6
JB		 397#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
398#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
399#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
400#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
0befdb3e 401#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
96b0e0f6 402#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
10eec955
JF		 403#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 23)
404#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 24)
405#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 25)
406#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 26)
407#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 27)
408#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 28)
409#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 29)
410#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 30)
96b0e0f6 411
df647b5c
PWJ		 412 u32 flags2;
413#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
414#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
119fc60a 415#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
96b0e0f6
JB		 416/* default to trying for four seconds */
417#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71
AK		 418
419 /* OS defined structs */
420 struct net_device *netdev;
421 struct pci_dev *pdev;
9a799d71 422
da4dd0f7
PWJ		 423 u32 test_icr;
424 struct ixgbe_ring test_tx_ring;
425 struct ixgbe_ring test_rx_ring;
426
9a799d71
AK		 427 /* structs defined in ixgbe_hw.h */
428 struct ixgbe_hw hw;
429 u16 msg_enable;
430 struct ixgbe_hw_stats stats;
021230d4
AV		 431
432 /* Interrupt Throttle Rate */
f7554a2b
NS		 433 u32 rx_eitr_param;
434 u32 tx_eitr_param;
9a799d71
AK		 435
436 unsigned long state;
437 u64 tx_busy;
30efa5a3
JB		 438 unsigned int tx_ring_count;
439 unsigned int rx_ring_count;
cf8280ee
JB		 440
441 u32 link_speed;
442 bool link_up;
443 unsigned long link_check_timeout;
444
445 struct work_struct watchdog_task;
c4900be0
DS		 446 struct work_struct sfp_task;
447 struct timer_list sfp_timer;
e8e26350
PW		 448 struct work_struct multispeed_fiber_task;
449 struct work_struct sfp_config_module_task;
c4cf55e5
PWJ		 450 u32 fdir_pballoc;
451 u32 atr_sample_rate;
452 spinlock_t fdir_perfect_lock;
453 struct work_struct fdir_reinit_task;
d0ed8937
YZ		 454#ifdef IXGBE_FCOE
455 struct ixgbe_fcoe fcoe;
456#endif /* IXGBE_FCOE */
94b982b2
MC		 457 u64 rsc_total_count;
458 u64 rsc_total_flush;
e8e26350 459 u32 wol;
34b0368c 460 u16 eeprom_version;
7f870475 461
1a6c14a2 462 int node;
119fc60a
MC		 463 struct work_struct check_overtemp_task;
464 u32 interrupt_event;
d0759ebb 465 char lsc_int_name[IFNAMSIZ + 9];
1a6c14a2 466
7f870475
GR		 467 /* SR-IOV */
468 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
469 unsigned int num_vfs;
470 struct vf_data_storage *vfinfo;
9a799d71
AK		 471};
472
473enum ixbge_state_t {
474 __IXGBE_TESTING,
475 __IXGBE_RESETTING,
c4900be0
DS		 476 __IXGBE_DOWN,
477 __IXGBE_SFP_MODULE_NOT_FOUND
9a799d71
AK		 478};
479
aa80175a
AD		 480struct ixgbe_rsc_cb {
481 dma_addr_t dma;
482 u16 skb_cnt;
483 bool delay_unmap;
484};
485#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
486
9a799d71 487enum ixgbe_boards {
3957d63d 488 board_82598,
e8e26350 489 board_82599,
fe15e8e1 490 board_X540,
9a799d71
AK		 491};
492
3957d63d 493extern struct ixgbe_info ixgbe_82598_info;
e8e26350 494extern struct ixgbe_info ixgbe_82599_info;
fe15e8e1 495extern struct ixgbe_info ixgbe_X540_info;
7a6b6f51 496#ifdef CONFIG_IXGBE_DCB
32953543 497extern const struct dcbnl_rtnl_ops dcbnl_ops;
2f90b865
AD		 498extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
499 struct ixgbe_dcb_config *dst_dcb_cfg,
500 int tc_max);
501#endif
9a799d71
AK		 502
503extern char ixgbe_driver_name[];
9c8eb720 504extern const char ixgbe_driver_version[];
9a799d71
AK		 505
506extern int ixgbe_up(struct ixgbe_adapter *adapter);
507extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882 508extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 509extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71 510extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b6ec895e
AD		 511extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
512extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
513extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
514extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
84418e3b
AD		 515extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
516extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
2d39d576
YZ		 517extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
518 struct ixgbe_ring *);
b4617240 519extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 520extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
7a921c93 521extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
84418e3b 522extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
84418e3b
AD		 523 struct ixgbe_adapter *,
524 struct ixgbe_ring *);
b6ec895e 525extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
84418e3b 526 struct ixgbe_tx_buffer *);
fc77dc3c 527extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
fe49f04a
AD		 528extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
529extern int ethtool_ioctl(struct ifreq *ifr);
ffff4772
PWJ		 530extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
531extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
532extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
533extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
69830529
AD		 534 union ixgbe_atr_hash_dword input,
535 union ixgbe_atr_hash_dword common,
ffff4772 536 u8 queue);
9a713e7c 537extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
905e4a41 538 union ixgbe_atr_input *input,
9a713e7c
PW		 539 struct ixgbe_atr_input_masks *input_masks,
540 u16 soft_id, u8 queue);
b93a2226
DS		 541extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
542 struct ixgbe_ring *ring);
543extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
544 struct ixgbe_ring *ring);
7f870475 545extern void ixgbe_set_rx_mode(struct net_device *netdev);
e5b64635 546extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
eacd73f7
YZ		 547#ifdef IXGBE_FCOE
548extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
549extern int ixgbe_fso(struct ixgbe_adapter *adapter,
550 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
551 u32 tx_flags, u8 *hdr_len);
332d4a7d
YZ		 552extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
553extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
554 union ixgbe_adv_rx_desc *rx_desc,
555 struct sk_buff *skb);
556extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
557 struct scatterlist *sgl, unsigned int sgc);
68a683cf
YZ		 558extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
559 struct scatterlist *sgl, unsigned int sgc);
332d4a7d 560extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
8450ff8c
YZ		 561extern int ixgbe_fcoe_enable(struct net_device *netdev);
562extern int ixgbe_fcoe_disable(struct net_device *netdev);
6ee16520
YZ		 563#ifdef CONFIG_IXGBE_DCB
564extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
565extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
566#endif /* CONFIG_IXGBE_DCB */
61a1fa10 567extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
eacd73f7 568#endif /* IXGBE_FCOE */
9a799d71
AK		 569
570#endif /* _IXGBE_H_ */
Linux kernel - Deliverables
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