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Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelv...
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
31#include <linux/types.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
6fabd715 34#include <linux/aer.h>
9a799d71
AK		 35
36#include "ixgbe_type.h"
37#include "ixgbe_common.h"
2f90b865 38#include "ixgbe_dcb.h"
eacd73f7
YZ		 39#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
40#define IXGBE_FCOE
41#include "ixgbe_fcoe.h"
42#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332 43#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 44#include <linux/dca.h>
45#endif
9a799d71 46
9a799d71
AK		 47#define PFX "ixgbe: "
48#define DPRINTK(nlevel, klevel, fmt, args...) \
49 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
50 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
b39d66a8 51 __func__ , ## args)))
9a799d71
AK		 52
53/* TX/RX descriptor defines */
54#define IXGBE_DEFAULT_TXD 1024
55#define IXGBE_MAX_TXD 4096
56#define IXGBE_MIN_TXD 64
57
58#define IXGBE_DEFAULT_RXD 1024
59#define IXGBE_MAX_RXD 4096
60#define IXGBE_MIN_RXD 64
61
9a799d71
AK		 62/* flow control */
63#define IXGBE_DEFAULT_FCRTL 0x10000
2b9ade93 64#define IXGBE_MIN_FCRTL 0x40
9a799d71
AK		 65#define IXGBE_MAX_FCRTL 0x7FF80
66#define IXGBE_DEFAULT_FCRTH 0x20000
2b9ade93 67#define IXGBE_MIN_FCRTH 0x600
9a799d71 68#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93 69#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71
AK		 70#define IXGBE_MIN_FCPAUSE 0
71#define IXGBE_MAX_FCPAUSE 0xFFFF
72
73/* Supported Rx Buffer Sizes */
74#define IXGBE_RXBUFFER_64 64 /* Used for packet split */
75#define IXGBE_RXBUFFER_128 128 /* Used for packet split */
76#define IXGBE_RXBUFFER_256 256 /* Used for packet split */
77#define IXGBE_RXBUFFER_2048 2048
e76678dd
AD		 78#define IXGBE_RXBUFFER_4096 4096
79#define IXGBE_RXBUFFER_8192 8192
32344a39 80#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71
AK		 81
82#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
83
84#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
85
9a799d71
AK		 86/* How many Rx Buffers do we bundle into one write to the hardware ? */
87#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
88
89#define IXGBE_TX_FLAGS_CSUM (u32)(1)
90#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
91#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
92#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
eacd73f7
YZ		 93#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
94#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
9a799d71 95#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
2f90b865 96#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
9a799d71
AK		 97#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
98
99/* wrapper around a pointer to a socket buffer,
100 * so a DMA handle can be stored along with the buffer */
101struct ixgbe_tx_buffer {
102 struct sk_buff *skb;
103 dma_addr_t dma;
104 unsigned long time_stamp;
105 u16 length;
106 u16 next_to_watch;
107};
108
109struct ixgbe_rx_buffer {
110 struct sk_buff *skb;
111 dma_addr_t dma;
112 struct page *page;
113 dma_addr_t page_dma;
762f4c57 114 unsigned int page_offset;
9a799d71
AK		 115};
116
117struct ixgbe_queue_stats {
118 u64 packets;
119 u64 bytes;
120};
121
122struct ixgbe_ring {
9a799d71 123 void *desc; /* descriptor ring memory */
9a799d71
AK		 124 union {
125 struct ixgbe_tx_buffer *tx_buffer_info;
126 struct ixgbe_rx_buffer *rx_buffer_info;
127 };
ae540af1
JB		 128 u8 atr_sample_rate;
129 u8 atr_count;
130 u16 count; /* amount of descriptors */
131 u16 rx_buf_len;
132 u16 next_to_use;
133 u16 next_to_clean;
134
135 u8 queue_index; /* needed for multiqueue queue management */
9a799d71
AK		 136
137 u16 head;
138 u16 tail;
139
f494e8fa
AV		 140 unsigned int total_bytes;
141 unsigned int total_packets;
9a799d71 142
5dd2d332 143#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 144 /* cpu for tx queue */
145 int cpu;
146#endif
ae540af1
JB		 147
148 u16 work_limit; /* max work per interrupt */
149 u16 reg_idx; /* holds the special value that gets
150 * the hardware register offset
151 * associated with this ring, which is
152 * different for DCB and RSS modes
153 */
154
9a799d71 155 struct ixgbe_queue_stats stats;
c4cf55e5 156 unsigned long reinit_state;
ae540af1 157 u64 rsc_count; /* stat for coalesced packets */
9a799d71 158
ae540af1
JB		 159 unsigned int size; /* length in bytes */
160 dma_addr_t dma; /* phys. address of descriptor ring */
9a799d71
AK		 161};
162
c7e4358a
SN		 163enum ixgbe_ring_f_enum {
164 RING_F_NONE = 0,
165 RING_F_DCB,
166 RING_F_VMDQ,
167 RING_F_RSS,
c4cf55e5 168 RING_F_FDIR,
0331a832
YZ		 169#ifdef IXGBE_FCOE
170 RING_F_FCOE,
171#endif /* IXGBE_FCOE */
c7e4358a
SN		 172
173 RING_F_ARRAY_SIZE /* must be last in enum set */
174};
175
2f90b865 176#define IXGBE_MAX_DCB_INDICES 8
021230d4
AV		 177#define IXGBE_MAX_RSS_INDICES 16
178#define IXGBE_MAX_VMDQ_INDICES 16
c4cf55e5 179#define IXGBE_MAX_FDIR_INDICES 64
0331a832
YZ		 180#ifdef IXGBE_FCOE
181#define IXGBE_MAX_FCOE_INDICES 8
182#endif /* IXGBE_FCOE */
021230d4
AV		 183struct ixgbe_ring_feature {
184 int indices;
185 int mask;
186};
187
e8e26350
PW		 188#define MAX_RX_QUEUES 128
189#define MAX_TX_QUEUES 128
021230d4 190
2f90b865
AD		 191#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
192 ? 8 : 1)
193#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
194
021230d4
AV		 195/* MAX_MSIX_Q_VECTORS of these are allocated,
196 * but we only use one per queue-specific vector.
197 */
198struct ixgbe_q_vector {
199 struct ixgbe_adapter *adapter;
fe49f04a
AD		 200 unsigned int v_idx; /* index of q_vector within array, also used for
201 * finding the bit in EICR and friends that
202 * represents the vector for this ring */
021230d4
AV		 203 struct napi_struct napi;
204 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
205 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
206 u8 rxr_count; /* Rx ring count assigned to this vector */
207 u8 txr_count; /* Tx ring count assigned to this vector */
30efa5a3
JB		 208 u8 tx_itr;
209 u8 rx_itr;
021230d4
AV		 210 u32 eitr;
211};
212
9a799d71 213/* Helper macros to switch between ints/sec and what the register uses.
509ee935
JB		 214 * And yes, it's the same math going both ways. The lowest value
215 * supported by all of the ixgbe hardware is 8.
9a799d71
AK		 216 */
217#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
509ee935 218 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
9a799d71
AK		 219#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
220
221#define IXGBE_DESC_UNUSED(R) \
222 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
223 (R)->next_to_clean - (R)->next_to_use - 1)
224
225#define IXGBE_RX_DESC_ADV(R, i) \
226 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
227#define IXGBE_TX_DESC_ADV(R, i) \
228 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
229#define IXGBE_TX_CTXTDESC_ADV(R, i) \
230 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
231
da4dd0f7
PWJ		 232#define IXGBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
233#define IXGBE_TX_DESC(R, i) IXGBE_GET_DESC(R, i, ixgbe_legacy_tx_desc)
234#define IXGBE_RX_DESC(R, i) IXGBE_GET_DESC(R, i, ixgbe_legacy_rx_desc)
235
9a799d71 236#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
63f39bd1
YZ		 237#ifdef IXGBE_FCOE
238/* Use 3K as the baby jumbo frame size for FCoE */
239#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
240#endif /* IXGBE_FCOE */
9a799d71 241
021230d4
AV		 242#define OTHER_VECTOR 1
243#define NON_Q_VECTORS (OTHER_VECTOR)
244
e8e26350
PW		 245#define MAX_MSIX_VECTORS_82599 64
246#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c
PWJ		 247#define MAX_MSIX_VECTORS_82598 18
248#define MAX_MSIX_Q_VECTORS_82598 16
249
e8e26350
PW		 250#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
251#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c 252
021230d4 253#define MIN_MSIX_Q_VECTORS 2
021230d4
AV		 254#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
255
9a799d71
AK		 256/* board specific private data structure */
257struct ixgbe_adapter {
258 struct timer_list watchdog_timer;
259 struct vlan_group *vlgrp;
260 u16 bd_number;
9a799d71 261 struct work_struct reset_task;
7a921c93 262 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
e8e26350 263 char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
2f90b865
AD		 264 struct ixgbe_dcb_config dcb_cfg;
265 struct ixgbe_dcb_config temp_dcb_cfg;
266 u8 dcb_set_bitmap;
264857b8 267 enum ixgbe_fc_mode last_lfc_mode;
9a799d71 268
f494e8fa
AV		 269 /* Interrupt Throttle Rate */
270 u32 itr_setting;
271 u16 eitr_low;
272 u16 eitr_high;
273
9a799d71
AK		 274 /* TX */
275 struct ixgbe_ring *tx_ring; /* One per active queue */
30efa5a3 276 int num_tx_queues;
9a799d71 277 u64 restart_queue;
30efa5a3 278 u64 hw_csum_tx_good;
9a799d71
AK		 279 u64 lsc_int;
280 u64 hw_tso_ctxt;
281 u64 hw_tso6_ctxt;
282 u32 tx_timeout_count;
283 bool detect_tx_hung;
284
285 /* RX */
286 struct ixgbe_ring *rx_ring; /* One per active queue */
30efa5a3 287 int num_rx_queues;
9a799d71 288 u64 hw_csum_rx_error;
e8e26350 289 u64 hw_rx_no_dma_resources;
9a799d71
AK		 290 u64 hw_csum_rx_good;
291 u64 non_eop_descs;
021230d4 292 int num_msix_vectors;
eb7f139c 293 int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a 294 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
9a799d71
AK		 295 struct msix_entry *msix_entries;
296
297 u64 rx_hdr_split;
298 u32 alloc_rx_page_failed;
299 u32 alloc_rx_buff_failed;
300
021230d4
AV		 301 /* Some features need tri-state capability,
302 * thus the additional *_CAPABLE flags.
303 */
9a799d71 304 u32 flags;
96b0e0f6
JB		 305#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
306#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
307#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
308#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
309#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
310#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
311#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
312#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
313#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
314#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
315#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
316#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
317#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
e8e26350 318#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
96b0e0f6
JB		 319#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
320#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
321#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
322#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
0befdb3e 323#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
96b0e0f6
JB		 324#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
325#define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23)
e8e26350
PW		 326#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 24)
327#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 25)
c4cf55e5
PWJ		 328#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 26)
329#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 27)
eacd73f7 330#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 29)
96b0e0f6 331
df647b5c
PWJ		 332 u32 flags2;
333#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
334#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
96b0e0f6
JB		 335/* default to trying for four seconds */
336#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71
AK		 337
338 /* OS defined structs */
339 struct net_device *netdev;
340 struct pci_dev *pdev;
341 struct net_device_stats net_stats;
342
da4dd0f7
PWJ		 343 u32 test_icr;
344 struct ixgbe_ring test_tx_ring;
345 struct ixgbe_ring test_rx_ring;
346
9a799d71
AK		 347 /* structs defined in ixgbe_hw.h */
348 struct ixgbe_hw hw;
349 u16 msg_enable;
350 struct ixgbe_hw_stats stats;
021230d4
AV		 351
352 /* Interrupt Throttle Rate */
30efa5a3 353 u32 eitr_param;
9a799d71
AK		 354
355 unsigned long state;
356 u64 tx_busy;
30efa5a3
JB		 357 unsigned int tx_ring_count;
358 unsigned int rx_ring_count;
cf8280ee
JB		 359
360 u32 link_speed;
361 bool link_up;
362 unsigned long link_check_timeout;
363
364 struct work_struct watchdog_task;
c4900be0
DS		 365 struct work_struct sfp_task;
366 struct timer_list sfp_timer;
e8e26350
PW		 367 struct work_struct multispeed_fiber_task;
368 struct work_struct sfp_config_module_task;
c4cf55e5
PWJ		 369 u32 fdir_pballoc;
370 u32 atr_sample_rate;
371 spinlock_t fdir_perfect_lock;
372 struct work_struct fdir_reinit_task;
d0ed8937
YZ		 373#ifdef IXGBE_FCOE
374 struct ixgbe_fcoe fcoe;
375#endif /* IXGBE_FCOE */
f8212f97 376 u64 rsc_count;
e8e26350 377 u32 wol;
34b0368c 378 u16 eeprom_version;
9a799d71
AK		 379};
380
381enum ixbge_state_t {
382 __IXGBE_TESTING,
383 __IXGBE_RESETTING,
c4900be0 384 __IXGBE_DOWN,
c4cf55e5 385 __IXGBE_FDIR_INIT_DONE,
c4900be0 386 __IXGBE_SFP_MODULE_NOT_FOUND
9a799d71
AK		 387};
388
389enum ixgbe_boards {
3957d63d 390 board_82598,
e8e26350 391 board_82599,
9a799d71
AK		 392};
393
3957d63d 394extern struct ixgbe_info ixgbe_82598_info;
e8e26350 395extern struct ixgbe_info ixgbe_82599_info;
7a6b6f51 396#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 397extern struct dcbnl_rtnl_ops dcbnl_ops;
398extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
399 struct ixgbe_dcb_config *dst_dcb_cfg,
400 int tc_max);
401#endif
9a799d71
AK		 402
403extern char ixgbe_driver_name[];
9c8eb720 404extern const char ixgbe_driver_version[];
9a799d71
AK		 405
406extern int ixgbe_up(struct ixgbe_adapter *adapter);
407extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882 408extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 409extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71 410extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b4617240
PW		 411extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
412extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
413extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
414extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
415extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 416extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
7a921c93 417extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
fe49f04a
AD		 418extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
419extern int ethtool_ioctl(struct ifreq *ifr);
ffff4772
PWJ		 420extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
421extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
422extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
423extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
424 struct ixgbe_atr_input *input,
425 u8 queue);
426extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
427 struct ixgbe_atr_input *input,
428 u16 soft_id,
429 u8 queue);
430extern u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *input, u32 key);
431extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
432 u16 vlan_id);
433extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
434 u32 src_addr);
435extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
436 u32 dst_addr);
437extern s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
438 u32 src_addr_1, u32 src_addr_2,
439 u32 src_addr_3, u32 src_addr_4);
440extern s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
441 u32 dst_addr_1, u32 dst_addr_2,
442 u32 dst_addr_3, u32 dst_addr_4);
443extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
444 u16 src_port);
445extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
446 u16 dst_port);
447extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
448 u16 flex_byte);
449extern s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
450 u8 vm_pool);
451extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
452 u8 l4type);
453extern s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input,
454 u16 *vlan_id);
455extern s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
456 u32 *src_addr);
457extern s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
458 u32 *dst_addr);
459extern s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
460 u32 *src_addr_1, u32 *src_addr_2,
461 u32 *src_addr_3, u32 *src_addr_4);
462extern s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
463 u32 *dst_addr_1, u32 *dst_addr_2,
464 u32 *dst_addr_3, u32 *dst_addr_4);
465extern s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
466 u16 *src_port);
467extern s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
468 u16 *dst_port);
469extern s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
470 u16 *flex_byte);
471extern s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
472 u8 *vm_pool);
473extern s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
474 u8 *l4type);
eacd73f7
YZ		 475#ifdef IXGBE_FCOE
476extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
477extern int ixgbe_fso(struct ixgbe_adapter *adapter,
478 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
479 u32 tx_flags, u8 *hdr_len);
332d4a7d
YZ		 480extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
481extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
482 union ixgbe_adv_rx_desc *rx_desc,
483 struct sk_buff *skb);
484extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
485 struct scatterlist *sgl, unsigned int sgc);
486extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
eacd73f7 487#endif /* IXGBE_FCOE */
9a799d71
AK		 488
489#endif /* _IXGBE_H_ */
Linux kernel - Deliverables
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