projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgbe: Add FCoE Storage MAC Address support
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
34
35#define IXGBE_82599_MAX_TX_QUEUES 128
36#define IXGBE_82599_MAX_RX_QUEUES 128
37#define IXGBE_82599_RAR_ENTRIES 128
38#define IXGBE_82599_MC_TBL_SIZE 128
39#define IXGBE_82599_VFT_TBL_SIZE 128
40
41s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
45s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
46s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed, bool autoneg,
48 bool autoneg_wait_to_complete);
49s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
50s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
51 ixgbe_link_speed *speed,
52 bool *link_up, bool link_up_wait_to_complete);
53s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
54 ixgbe_link_speed speed,
55 bool autoneg,
56 bool autoneg_wait_to_complete);
57static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
58 ixgbe_link_speed *speed,
59 bool *autoneg);
60static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
61static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
62 ixgbe_link_speed speed,
63 bool autoneg,
64 bool autoneg_wait_to_complete);
65s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
66s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
67s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
68s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan,
69 u32 vind, bool vlan_on);
70s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw);
11afc1b1
PW		 71s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw);
72s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
73s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
74s32 ixgbe_start_hw_rev_0_82599(struct ixgbe_hw *hw);
75s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
76s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
77u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
78
79void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
80{
81 struct ixgbe_mac_info *mac = &hw->mac;
82 if (hw->phy.multispeed_fiber) {
83 /* Set up dual speed SFP+ support */
84 mac->ops.setup_link =
85 &ixgbe_setup_mac_link_multispeed_fiber;
86 mac->ops.setup_link_speed =
87 &ixgbe_setup_mac_link_speed_multispeed_fiber;
88 } else {
89 mac->ops.setup_link =
90 &ixgbe_setup_mac_link_82599;
91 mac->ops.setup_link_speed =
92 &ixgbe_setup_mac_link_speed_82599;
93 }
94}
95
96s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
97{
98 s32 ret_val = 0;
99 u16 list_offset, data_offset, data_value;
100
101 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
102 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 103
104 hw->phy.ops.reset = NULL;
105
11afc1b1
PW		 106 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
107 &data_offset);
108
109 if (ret_val != 0)
110 goto setup_sfp_out;
111
112 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
113 while (data_value != 0xffff) {
114 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
115 IXGBE_WRITE_FLUSH(hw);
116 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
117 }
118 /* Now restart DSP */
119 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000102);
120 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000b1d);
121 IXGBE_WRITE_FLUSH(hw);
122 }
123
124setup_sfp_out:
125 return ret_val;
126}
127
128/**
129 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
130 * @hw: pointer to hardware structure
131 *
132 * Read PCIe configuration space, and get the MSI-X vector count from
133 * the capabilities table.
134 **/
135u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
136{
137 struct ixgbe_adapter *adapter = hw->back;
138 u16 msix_count;
139 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
140 &msix_count);
141 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
142
143 /* MSI-X count is zero-based in HW, so increment to give proper value */
144 msix_count++;
145
146 return msix_count;
147}
148
149static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
150{
151 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 152
04f165ef 153 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 154
04f165ef
PW		 155 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
156 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
157 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
158 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
159 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
160 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
11afc1b1 161
04f165ef
PW		 162 return 0;
163}
11afc1b1 164
04f165ef
PW		 165/**
166 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
167 * @hw: pointer to hardware structure
168 *
169 * Initialize any function pointers that were not able to be
170 * set during get_invariants because the PHY/SFP type was
171 * not known. Perform the SFP init if necessary.
172 *
173 **/
174s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
175{
176 struct ixgbe_mac_info *mac = &hw->mac;
177 struct ixgbe_phy_info *phy = &hw->phy;
178 s32 ret_val = 0;
11afc1b1 179
04f165ef
PW		 180 /* Identify the PHY or SFP module */
181 ret_val = phy->ops.identify(hw);
182
183 /* Setup function pointers based on detected SFP module and speeds */
184 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 185
186 /* If copper media, overwrite with copper function pointers */
187 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
188 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
189 mac->ops.setup_link_speed =
04f165ef 190 &ixgbe_setup_copper_link_speed_82599;
11afc1b1
PW		 191 mac->ops.get_link_capabilities =
192 &ixgbe_get_copper_link_capabilities_82599;
193 }
194
04f165ef 195 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 196 switch (hw->phy.type) {
197 case ixgbe_phy_tn:
198 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
199 phy->ops.get_firmware_version =
04f165ef 200 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 201 break;
202 default:
203 break;
204 }
205
11afc1b1
PW		 206 return ret_val;
207}
208
209/**
210 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
211 * @hw: pointer to hardware structure
212 * @speed: pointer to link speed
213 * @negotiation: true when autoneg or autotry is enabled
214 *
215 * Determines the link capabilities by reading the AUTOC register.
216 **/
217s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
218 ixgbe_link_speed *speed,
219 bool *negotiation)
220{
221 s32 status = 0;
1eb99d5a 222 u32 autoc = 0;
11afc1b1 223
1eb99d5a
PW		 224 /*
225 * Determine link capabilities based on the stored value of AUTOC,
226 * which represents EEPROM defaults. If AUTOC value has not been
227 * stored, use the current register value.
228 */
229 if (hw->mac.orig_link_settings_stored)
230 autoc = hw->mac.orig_autoc;
231 else
232 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
233
234 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 235 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
236 *speed = IXGBE_LINK_SPEED_1GB_FULL;
237 *negotiation = false;
238 break;
239
240 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
241 *speed = IXGBE_LINK_SPEED_10GB_FULL;
242 *negotiation = false;
243 break;
244
245 case IXGBE_AUTOC_LMS_1G_AN:
246 *speed = IXGBE_LINK_SPEED_1GB_FULL;
247 *negotiation = true;
248 break;
249
250 case IXGBE_AUTOC_LMS_10G_SERIAL:
251 *speed = IXGBE_LINK_SPEED_10GB_FULL;
252 *negotiation = false;
253 break;
254
255 case IXGBE_AUTOC_LMS_KX4_KX_KR:
256 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
257 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 258 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 259 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 260 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 261 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 262 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 263 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
264 *negotiation = true;
265 break;
266
267 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
268 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 269 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 270 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 271 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 272 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 273 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 274 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
275 *negotiation = true;
276 break;
277
278 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
279 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
280 *negotiation = false;
281 break;
282
283 default:
284 status = IXGBE_ERR_LINK_SETUP;
285 goto out;
286 break;
287 }
288
289 if (hw->phy.multispeed_fiber) {
290 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
291 IXGBE_LINK_SPEED_1GB_FULL;
292 *negotiation = true;
293 }
294
295out:
296 return status;
297}
298
299/**
300 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
301 * @hw: pointer to hardware structure
302 * @speed: pointer to link speed
303 * @autoneg: boolean auto-negotiation value
304 *
305 * Determines the link capabilities by reading the AUTOC register.
306 **/
307static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
308 ixgbe_link_speed *speed,
309 bool *autoneg)
310{
311 s32 status = IXGBE_ERR_LINK_SETUP;
312 u16 speed_ability;
313
314 *speed = 0;
315 *autoneg = true;
316
6b73e10d 317 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
11afc1b1
PW		 318 &speed_ability);
319
320 if (status == 0) {
6b73e10d 321 if (speed_ability & MDIO_SPEED_10G)
11afc1b1 322 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
6b73e10d 323 if (speed_ability & MDIO_PMA_SPEED_1000)
11afc1b1
PW		 324 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
325 }
326
327 return status;
328}
329
330/**
331 * ixgbe_get_media_type_82599 - Get media type
332 * @hw: pointer to hardware structure
333 *
334 * Returns the media type (fiber, copper, backplane)
335 **/
336enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
337{
338 enum ixgbe_media_type media_type;
339
340 /* Detect if there is a copper PHY attached. */
341 if (hw->phy.type == ixgbe_phy_cu_unknown ||
342 hw->phy.type == ixgbe_phy_tn) {
343 media_type = ixgbe_media_type_copper;
344 goto out;
345 }
346
347 switch (hw->device_id) {
348 case IXGBE_DEV_ID_82599:
349 case IXGBE_DEV_ID_82599_KX4:
350 /* Default device ID is mezzanine card KX/KX4 */
351 media_type = ixgbe_media_type_backplane;
352 break;
353 case IXGBE_DEV_ID_82599_SFP:
354 media_type = ixgbe_media_type_fiber;
355 break;
356 default:
357 media_type = ixgbe_media_type_unknown;
358 break;
359 }
360out:
361 return media_type;
362}
363
364/**
365 * ixgbe_setup_mac_link_82599 - Setup MAC link settings
366 * @hw: pointer to hardware structure
367 *
368 * Configures link settings based on values in the ixgbe_hw struct.
369 * Restarts the link. Performs autonegotiation if needed.
370 **/
371s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
372{
373 u32 autoc_reg;
374 u32 links_reg;
375 u32 i;
376 s32 status = 0;
377
378 /* Restart link */
379 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
380 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
381 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
382
383 /* Only poll for autoneg to complete if specified to do so */
384 if (hw->phy.autoneg_wait_to_complete) {
385 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
386 IXGBE_AUTOC_LMS_KX4_KX_KR ||
387 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
388 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
389 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
390 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
391 links_reg = 0; /* Just in case Autoneg time = 0 */
392 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
393 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
394 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
395 break;
396 msleep(100);
397 }
398 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
399 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
400 hw_dbg(hw, "Autoneg did not complete.\n");
401 }
402 }
403 }
404
405 /* Set up flow control */
406 status = ixgbe_setup_fc_generic(hw, 0);
407
408 /* Add delay to filter out noises during initial link setup */
409 msleep(50);
410
411 return status;
412}
413
414/**
415 * ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
416 * @hw: pointer to hardware structure
417 *
418 * Configures link settings based on values in the ixgbe_hw struct.
419 * Restarts the link for multi-speed fiber at 1G speed, if link
420 * fails at 10G.
421 * Performs autonegotiation if needed.
422 **/
423s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
424{
425 s32 status = 0;
426 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
4df10466 427 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, link_speed,
11afc1b1
PW		 428 true, true);
429 return status;
430}
431
432/**
433 * ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
434 * @hw: pointer to hardware structure
435 * @speed: new link speed
436 * @autoneg: true if autonegotiation enabled
437 * @autoneg_wait_to_complete: true when waiting for completion is needed
438 *
439 * Set the link speed in the AUTOC register and restarts link.
440 **/
441s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
442 ixgbe_link_speed speed,
443 bool autoneg,
444 bool autoneg_wait_to_complete)
445{
446 s32 status = 0;
447 ixgbe_link_speed phy_link_speed;
448 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
449 u32 speedcnt = 0;
450 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
451 bool link_up = false;
452 bool negotiation;
453
454 /* Mask off requested but non-supported speeds */
455 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
456 speed &= phy_link_speed;
457
458 /*
459 * Try each speed one by one, highest priority first. We do this in
460 * software because 10gb fiber doesn't support speed autonegotiation.
461 */
462 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
463 speedcnt++;
464 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
465
466 /* Set hardware SDP's */
467 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
468 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
469
470 ixgbe_setup_mac_link_speed_82599(hw,
471 IXGBE_LINK_SPEED_10GB_FULL,
472 autoneg,
473 autoneg_wait_to_complete);
474
475 msleep(50);
476
477 /* If we have link, just jump out */
478 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
479 if (link_up)
480 goto out;
481 }
482
483 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
484 speedcnt++;
485 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
486 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
487
488 /* Set hardware SDP's */
489 esdp_reg &= ~IXGBE_ESDP_SDP5;
490 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
491 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
492
493 ixgbe_setup_mac_link_speed_82599(
494 hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg,
495 autoneg_wait_to_complete);
496
497 msleep(50);
498
499 /* If we have link, just jump out */
500 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
501 if (link_up)
502 goto out;
503 }
504
505 /*
506 * We didn't get link. Configure back to the highest speed we tried,
507 * (if there was more than one). We call ourselves back with just the
508 * single highest speed that the user requested.
509 */
510 if (speedcnt > 1)
511 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
512 highest_link_speed,
513 autoneg,
514 autoneg_wait_to_complete);
515
516out:
517 return status;
518}
519
520/**
521 * ixgbe_check_mac_link_82599 - Determine link and speed status
522 * @hw: pointer to hardware structure
523 * @speed: pointer to link speed
524 * @link_up: true when link is up
525 * @link_up_wait_to_complete: bool used to wait for link up or not
526 *
527 * Reads the links register to determine if link is up and the current speed
528 **/
529s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
530 bool *link_up, bool link_up_wait_to_complete)
531{
532 u32 links_reg;
533 u32 i;
534
535 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
536 if (link_up_wait_to_complete) {
537 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
538 if (links_reg & IXGBE_LINKS_UP) {
539 *link_up = true;
540 break;
541 } else {
542 *link_up = false;
543 }
544 msleep(100);
545 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
546 }
547 } else {
548 if (links_reg & IXGBE_LINKS_UP)
549 *link_up = true;
550 else
551 *link_up = false;
552 }
553
554 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
555 IXGBE_LINKS_SPEED_10G_82599)
556 *speed = IXGBE_LINK_SPEED_10GB_FULL;
557 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
558 IXGBE_LINKS_SPEED_1G_82599)
559 *speed = IXGBE_LINK_SPEED_1GB_FULL;
560 else
561 *speed = IXGBE_LINK_SPEED_100_FULL;
562
563
564 return 0;
565}
566
567/**
568 * ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
569 * @hw: pointer to hardware structure
570 * @speed: new link speed
571 * @autoneg: true if autonegotiation enabled
572 * @autoneg_wait_to_complete: true when waiting for completion is needed
573 *
574 * Set the link speed in the AUTOC register and restarts link.
575 **/
576s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
577 ixgbe_link_speed speed, bool autoneg,
578 bool autoneg_wait_to_complete)
579{
580 s32 status = 0;
581 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
582 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1eb99d5a 583 u32 orig_autoc = 0;
11afc1b1
PW		 584 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
585 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
586 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
587 u32 links_reg;
588 u32 i;
589 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
590
591 /* Check to see if speed passed in is supported. */
592 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
593 speed &= link_capabilities;
594
1eb99d5a
PW		 595 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
596 if (hw->mac.orig_link_settings_stored)
597 orig_autoc = hw->mac.orig_autoc;
598 else
599 orig_autoc = autoc;
600
601
11afc1b1
PW		 602 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
603 status = IXGBE_ERR_LINK_SETUP;
604 } else if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
605 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
606 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
607 /* Set KX4/KX/KR support according to speed requested */
608 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
609 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 610 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 611 autoc |= IXGBE_AUTOC_KX4_SUPP;
1eb99d5a 612 if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1
PW		 613 autoc |= IXGBE_AUTOC_KR_SUPP;
614 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
615 autoc |= IXGBE_AUTOC_KX_SUPP;
616 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
617 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
618 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
619 /* Switch from 1G SFI to 10G SFI if requested */
620 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
621 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
622 autoc &= ~IXGBE_AUTOC_LMS_MASK;
623 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
624 }
625 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
626 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
627 /* Switch from 10G SFI to 1G SFI if requested */
628 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
629 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
630 autoc &= ~IXGBE_AUTOC_LMS_MASK;
631 if (autoneg)
632 autoc |= IXGBE_AUTOC_LMS_1G_AN;
633 else
634 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
635 }
636 }
637
638 if (status == 0) {
639 /* Restart link */
640 autoc |= IXGBE_AUTOC_AN_RESTART;
641 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
642
643 /* Only poll for autoneg to complete if specified to do so */
644 if (autoneg_wait_to_complete) {
645 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
646 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
647 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
648 links_reg = 0; /*Just in case Autoneg time=0*/
649 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
650 links_reg =
651 IXGBE_READ_REG(hw, IXGBE_LINKS);
652 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
653 break;
654 msleep(100);
655 }
656 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
657 status =
658 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
659 hw_dbg(hw, "Autoneg did not "
660 "complete.\n");
661 }
662 }
663 }
664
665 /* Set up flow control */
666 status = ixgbe_setup_fc_generic(hw, 0);
667
668 /* Add delay to filter out noises during initial link setup */
669 msleep(50);
670 }
671
672 return status;
673}
674
675/**
676 * ixgbe_setup_copper_link_82599 - Setup copper link settings
677 * @hw: pointer to hardware structure
678 *
679 * Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
680 **/
681static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
682{
683 s32 status;
684
685 /* Restart autonegotiation on PHY */
686 status = hw->phy.ops.setup_link(hw);
687
688 /* Set up MAC */
689 ixgbe_setup_mac_link_82599(hw);
690
691 return status;
692}
693
694/**
695 * ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
696 * @hw: pointer to hardware structure
697 * @speed: new link speed
698 * @autoneg: true if autonegotiation enabled
699 * @autoneg_wait_to_complete: true if waiting is needed to complete
700 *
701 * Restarts link on PHY and MAC based on settings passed in.
702 **/
703static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
704 ixgbe_link_speed speed,
705 bool autoneg,
706 bool autoneg_wait_to_complete)
707{
708 s32 status;
709
710 /* Setup the PHY according to input speed */
711 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
712 autoneg_wait_to_complete);
713 /* Set up MAC */
714 ixgbe_setup_mac_link_82599(hw);
715
716 return status;
717}
718
719/**
720 * ixgbe_reset_hw_82599 - Perform hardware reset
721 * @hw: pointer to hardware structure
722 *
723 * Resets the hardware by resetting the transmit and receive units, masks
724 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
725 * reset.
726 **/
727s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
728{
729 s32 status = 0;
730 u32 ctrl, ctrl_ext;
731 u32 i;
732 u32 autoc;
733 u32 autoc2;
734
735 /* Call adapter stop to disable tx/rx and clear interrupts */
736 hw->mac.ops.stop_adapter(hw);
737
553b4497 738 /* PHY ops must be identified and initialized prior to reset */
04f165ef 739
553b4497
PW		 740 /* Init PHY and function pointers, perform SFP setup */
741 status = hw->phy.ops.init(hw);
04f165ef 742
553b4497
PW		 743 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
744 goto reset_hw_out;
04f165ef 745
553b4497
PW		 746 /* Setup SFP module if there is one present. */
747 if (hw->phy.sfp_setup_needed) {
748 status = hw->mac.ops.setup_sfp(hw);
749 hw->phy.sfp_setup_needed = false;
04f165ef 750 }
11afc1b1 751
553b4497
PW		 752 /* Reset PHY */
753 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
754 hw->phy.ops.reset(hw);
755
11afc1b1
PW		 756 /*
757 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
758 * access and verify no pending requests before reset
759 */
04f165ef
PW		 760 status = ixgbe_disable_pcie_master(hw);
761 if (status != 0) {
11afc1b1
PW		 762 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
763 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
764 }
765
766 /*
767 * Issue global reset to the MAC. This needs to be a SW reset.
768 * If link reset is used, it might reset the MAC when mng is using it
769 */
770 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
771 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
772 IXGBE_WRITE_FLUSH(hw);
773
774 /* Poll for reset bit to self-clear indicating reset is complete */
775 for (i = 0; i < 10; i++) {
776 udelay(1);
777 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
778 if (!(ctrl & IXGBE_CTRL_RST))
779 break;
780 }
781 if (ctrl & IXGBE_CTRL_RST) {
782 status = IXGBE_ERR_RESET_FAILED;
783 hw_dbg(hw, "Reset polling failed to complete.\n");
784 }
785 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
786 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
787 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
788 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
789
790 msleep(50);
791
792
793
794 /*
795 * Store the original AUTOC/AUTOC2 values if they have not been
796 * stored off yet. Otherwise restore the stored original
797 * values since the reset operation sets back to defaults.
798 */
799 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
800 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
801 if (hw->mac.orig_link_settings_stored == false) {
802 hw->mac.orig_autoc = autoc;
803 hw->mac.orig_autoc2 = autoc2;
804 hw->mac.orig_link_settings_stored = true;
4df10466 805 } else {
11afc1b1
PW		 806 if (autoc != hw->mac.orig_autoc)
807 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
808 IXGBE_AUTOC_AN_RESTART));
809
810 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
811 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
812 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
813 autoc2 |= (hw->mac.orig_autoc2 &
814 IXGBE_AUTOC2_UPPER_MASK);
815 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
816 }
817 }
818
819 /* Store the permanent mac address */
820 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
821
0365e6e4
PW		 822 /* Store the permanent SAN mac address */
823 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
824
04f165ef 825reset_hw_out:
11afc1b1
PW		 826 return status;
827}
828
829/**
830 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
831 * @hw: pointer to hardware struct
832 * @rar: receive address register index to disassociate
833 * @vmdq: VMDq pool index to remove from the rar
834 **/
835s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
836{
837 u32 mpsar_lo, mpsar_hi;
838 u32 rar_entries = hw->mac.num_rar_entries;
839
840 if (rar < rar_entries) {
841 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
842 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
843
844 if (!mpsar_lo && !mpsar_hi)
845 goto done;
846
847 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
848 if (mpsar_lo) {
849 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
850 mpsar_lo = 0;
851 }
852 if (mpsar_hi) {
853 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
854 mpsar_hi = 0;
855 }
856 } else if (vmdq < 32) {
857 mpsar_lo &= ~(1 << vmdq);
858 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
859 } else {
860 mpsar_hi &= ~(1 << (vmdq - 32));
861 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
862 }
863
864 /* was that the last pool using this rar? */
865 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
866 hw->mac.ops.clear_rar(hw, rar);
867 } else {
868 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
869 }
870
871done:
872 return 0;
873}
874
875/**
876 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
877 * @hw: pointer to hardware struct
878 * @rar: receive address register index to associate with a VMDq index
879 * @vmdq: VMDq pool index
880 **/
881s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
882{
883 u32 mpsar;
884 u32 rar_entries = hw->mac.num_rar_entries;
885
886 if (rar < rar_entries) {
887 if (vmdq < 32) {
888 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
889 mpsar |= 1 << vmdq;
890 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
891 } else {
892 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
893 mpsar |= 1 << (vmdq - 32);
894 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
895 }
896 } else {
897 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
898 }
899 return 0;
900}
901
902/**
903 * ixgbe_set_vfta_82599 - Set VLAN filter table
904 * @hw: pointer to hardware structure
905 * @vlan: VLAN id to write to VLAN filter
906 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
907 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
908 *
909 * Turn on/off specified VLAN in the VLAN filter table.
910 **/
911s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
912 bool vlan_on)
913{
914 u32 regindex;
915 u32 bitindex;
916 u32 bits;
917 u32 first_empty_slot;
918
919 if (vlan > 4095)
920 return IXGBE_ERR_PARAM;
921
922 /*
923 * this is a 2 part operation - first the VFTA, then the
924 * VLVF and VLVFB if vind is set
925 */
926
927 /* Part 1
928 * The VFTA is a bitstring made up of 128 32-bit registers
929 * that enable the particular VLAN id, much like the MTA:
930 * bits[11-5]: which register
931 * bits[4-0]: which bit in the register
932 */
933 regindex = (vlan >> 5) & 0x7F;
934 bitindex = vlan & 0x1F;
935 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
936 if (vlan_on)
937 bits |= (1 << bitindex);
938 else
939 bits &= ~(1 << bitindex);
940 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
941
942
943 /* Part 2
944 * If the vind is set
945 * Either vlan_on
946 * make sure the vlan is in VLVF
947 * set the vind bit in the matching VLVFB
948 * Or !vlan_on
949 * clear the pool bit and possibly the vind
950 */
951 if (vind) {
952 /* find the vlanid or the first empty slot */
953 first_empty_slot = 0;
954
955 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
956 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
957 if (!bits && !first_empty_slot)
958 first_empty_slot = regindex;
959 else if ((bits & 0x0FFF) == vlan)
960 break;
961 }
962
963 if (regindex >= IXGBE_VLVF_ENTRIES) {
964 if (first_empty_slot)
965 regindex = first_empty_slot;
966 else {
967 hw_dbg(hw, "No space in VLVF.\n");
968 goto out;
969 }
970 }
971
972 if (vlan_on) {
973 /* set the pool bit */
974 if (vind < 32) {
975 bits = IXGBE_READ_REG(hw,
976 IXGBE_VLVFB(regindex * 2));
977 bits |= (1 << vind);
978 IXGBE_WRITE_REG(hw,
979 IXGBE_VLVFB(regindex * 2), bits);
980 } else {
981 bits = IXGBE_READ_REG(hw,
982 IXGBE_VLVFB((regindex * 2) + 1));
983 bits |= (1 << vind);
984 IXGBE_WRITE_REG(hw,
985 IXGBE_VLVFB((regindex * 2) + 1), bits);
986 }
987 } else {
988 /* clear the pool bit */
989 if (vind < 32) {
990 bits = IXGBE_READ_REG(hw,
991 IXGBE_VLVFB(regindex * 2));
992 bits &= ~(1 << vind);
993 IXGBE_WRITE_REG(hw,
994 IXGBE_VLVFB(regindex * 2), bits);
995 bits |= IXGBE_READ_REG(hw,
996 IXGBE_VLVFB((regindex * 2) + 1));
997 } else {
998 bits = IXGBE_READ_REG(hw,
999 IXGBE_VLVFB((regindex * 2) + 1));
1000 bits &= ~(1 << vind);
1001 IXGBE_WRITE_REG(hw,
1002 IXGBE_VLVFB((regindex * 2) + 1), bits);
1003 bits |= IXGBE_READ_REG(hw,
1004 IXGBE_VLVFB(regindex * 2));
1005 }
1006 }
1007
1008 if (bits)
1009 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1010 (IXGBE_VLVF_VIEN | vlan));
1011 else
1012 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1013 }
1014
1015out:
1016 return 0;
1017}
1018
1019/**
1020 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1021 * @hw: pointer to hardware structure
1022 *
1023 * Clears the VLAN filer table, and the VMDq index associated with the filter
1024 **/
1025s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1026{
1027 u32 offset;
1028
1029 for (offset = 0; offset < hw->mac.vft_size; offset++)
1030 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1031
1032 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1033 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1034 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1035 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1036 }
1037
1038 return 0;
1039}
1040
11afc1b1
PW		 1041/**
1042 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1043 * @hw: pointer to hardware structure
1044 **/
1045s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1046{
1047 int i;
1048 hw_dbg(hw, " Clearing UTA\n");
1049
1050 for (i = 0; i < 128; i++)
1051 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1052
1053 return 0;
1054}
1055
1056/**
1057 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1058 * @hw: pointer to hardware structure
1059 * @reg: analog register to read
1060 * @val: read value
1061 *
1062 * Performs read operation to Omer analog register specified.
1063 **/
1064s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1065{
1066 u32 core_ctl;
1067
1068 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1069 (reg << 8));
1070 IXGBE_WRITE_FLUSH(hw);
1071 udelay(10);
1072 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1073 *val = (u8)core_ctl;
1074
1075 return 0;
1076}
1077
1078/**
1079 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1080 * @hw: pointer to hardware structure
1081 * @reg: atlas register to write
1082 * @val: value to write
1083 *
1084 * Performs write operation to Omer analog register specified.
1085 **/
1086s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1087{
1088 u32 core_ctl;
1089
1090 core_ctl = (reg << 8) | val;
1091 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1092 IXGBE_WRITE_FLUSH(hw);
1093 udelay(10);
1094
1095 return 0;
1096}
1097
1098/**
1099 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1100 * @hw: pointer to hardware structure
1101 *
1102 * Starts the hardware using the generic start_hw function.
1103 * Then performs device-specific:
1104 * Clears the rate limiter registers.
1105 **/
1106s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1107{
1108 u32 q_num;
1109
1110 ixgbe_start_hw_generic(hw);
1111
1112 /* Clear the rate limiters */
1113 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1114 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1115 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1116 }
1117 IXGBE_WRITE_FLUSH(hw);
1118
1119 return 0;
1120}
1121
1122/**
1123 * ixgbe_identify_phy_82599 - Get physical layer module
1124 * @hw: pointer to hardware structure
1125 *
1126 * Determines the physical layer module found on the current adapter.
1127 **/
1128s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1129{
1130 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1131 status = ixgbe_identify_phy_generic(hw);
1132 if (status != 0)
1133 status = ixgbe_identify_sfp_module_generic(hw);
1134 return status;
1135}
1136
1137/**
1138 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1139 * @hw: pointer to hardware structure
1140 *
1141 * Determines physical layer capabilities of the current configuration.
1142 **/
1143u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1144{
1145 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 1146 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1147 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1148 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1149 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1150 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1151 u16 ext_ability = 0;
1339b9e9 1152 u8 comp_codes_10g = 0;
11afc1b1 1153
04193058
PWJ		 1154 hw->phy.ops.identify(hw);
1155
1156 if (hw->phy.type == ixgbe_phy_tn ||
1157 hw->phy.type == ixgbe_phy_cu_unknown) {
6b73e10d
BH		 1158 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1159 &ext_ability);
1160 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 1161 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 1162 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 1163 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 1164 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 1165 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1166 goto out;
1167 }
1168
1169 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1170 case IXGBE_AUTOC_LMS_1G_AN:
1171 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1172 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1173 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1174 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1175 goto out;
1176 } else
1177 /* SFI mode so read SFP module */
1178 goto sfp_check;
11afc1b1 1179 break;
04193058
PWJ		 1180 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1181 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1182 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1183 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1184 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1185 goto out;
1186 break;
1187 case IXGBE_AUTOC_LMS_10G_SERIAL:
1188 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1189 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1190 goto out;
1191 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1192 goto sfp_check;
1193 break;
1194 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1195 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1196 if (autoc & IXGBE_AUTOC_KX_SUPP)
1197 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1198 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1199 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1200 if (autoc & IXGBE_AUTOC_KR_SUPP)
1201 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1202 goto out;
1203 break;
1204 default:
1205 goto out;
1206 break;
1207 }
11afc1b1 1208
04193058
PWJ		 1209sfp_check:
1210 /* SFP check must be done last since DA modules are sometimes used to
1211 * test KR mode - we need to id KR mode correctly before SFP module.
1212 * Call identify_sfp because the pluggable module may have changed */
1213 hw->phy.ops.identify_sfp(hw);
1214 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1215 goto out;
1216
1217 switch (hw->phy.type) {
1218 case ixgbe_phy_tw_tyco:
1219 case ixgbe_phy_tw_unknown:
1220 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1221 break;
1222 case ixgbe_phy_sfp_avago:
1223 case ixgbe_phy_sfp_ftl:
1224 case ixgbe_phy_sfp_intel:
1225 case ixgbe_phy_sfp_unknown:
1226 hw->phy.ops.read_i2c_eeprom(hw,
1227 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1228 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 1229 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 1230 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 1231 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
11afc1b1
PW		 1232 break;
1233 default:
11afc1b1
PW		 1234 break;
1235 }
1236
04193058 1237out:
11afc1b1
PW		 1238 return physical_layer;
1239}
1240
1241/**
1242 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1243 * @hw: pointer to hardware structure
1244 * @regval: register value to write to RXCTRL
1245 *
1246 * Enables the Rx DMA unit for 82599
1247 **/
1248s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1249{
1250#define IXGBE_MAX_SECRX_POLL 30
1251 int i;
1252 int secrxreg;
1253
1254 /*
1255 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1256 * If traffic is incoming before we enable the Rx unit, it could hang
1257 * the Rx DMA unit. Therefore, make sure the security engine is
1258 * completely disabled prior to enabling the Rx unit.
1259 */
1260 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1261 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1262 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1263 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1264 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1265 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1266 break;
1267 else
1268 udelay(10);
1269 }
1270
1271 /* For informational purposes only */
1272 if (i >= IXGBE_MAX_SECRX_POLL)
1273 hw_dbg(hw, "Rx unit being enabled before security "
1274 "path fully disabled. Continuing with init.\n");
1275
1276 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1277 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1278 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1279 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1280 IXGBE_WRITE_FLUSH(hw);
1281
1282 return 0;
1283}
1284
04193058
PWJ		 1285/**
1286 * ixgbe_get_device_caps_82599 - Get additional device capabilities
1287 * @hw: pointer to hardware structure
1288 * @device_caps: the EEPROM word with the extra device capabilities
1289 *
1290 * This function will read the EEPROM location for the device capabilities,
1291 * and return the word through device_caps.
1292 **/
1293s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
1294{
1295 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
1296
1297 return 0;
1298}
1299
0365e6e4
PW		 1300/**
1301 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
1302 * @hw: pointer to hardware structure
1303 * @san_mac_offset: SAN MAC address offset
1304 *
1305 * This function will read the EEPROM location for the SAN MAC address
1306 * pointer, and returns the value at that location. This is used in both
1307 * get and set mac_addr routines.
1308 **/
1309s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
1310 u16 *san_mac_offset)
1311{
1312 /*
1313 * First read the EEPROM pointer to see if the MAC addresses are
1314 * available.
1315 */
1316 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
1317
1318 return 0;
1319}
1320
1321/**
1322 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
1323 * @hw: pointer to hardware structure
1324 * @san_mac_addr: SAN MAC address
1325 *
1326 * Reads the SAN MAC address from the EEPROM, if it's available. This is
1327 * per-port, so set_lan_id() must be called before reading the addresses.
1328 * set_lan_id() is called by identify_sfp(), but this cannot be relied
1329 * upon for non-SFP connections, so we must call it here.
1330 **/
1331s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
1332{
1333 u16 san_mac_data, san_mac_offset;
1334 u8 i;
1335
1336 /*
1337 * First read the EEPROM pointer to see if the MAC addresses are
1338 * available. If they're not, no point in calling set_lan_id() here.
1339 */
1340 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
1341
1342 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
1343 /*
1344 * No addresses available in this EEPROM. It's not an
1345 * error though, so just wipe the local address and return.
1346 */
1347 for (i = 0; i < 6; i++)
1348 san_mac_addr[i] = 0xFF;
1349
1350 goto san_mac_addr_out;
1351 }
1352
1353 /* make sure we know which port we need to program */
1354 hw->mac.ops.set_lan_id(hw);
1355 /* apply the port offset to the address offset */
1356 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1357 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1358 for (i = 0; i < 3; i++) {
1359 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
1360 san_mac_addr[i * 2] = (u8)(san_mac_data);
1361 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
1362 san_mac_offset++;
1363 }
1364
1365san_mac_addr_out:
1366 return 0;
1367}
1368
11afc1b1
PW		 1369static struct ixgbe_mac_operations mac_ops_82599 = {
1370 .init_hw = &ixgbe_init_hw_generic,
1371 .reset_hw = &ixgbe_reset_hw_82599,
1372 .start_hw = &ixgbe_start_hw_82599,
1373 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1374 .get_media_type = &ixgbe_get_media_type_82599,
1375 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1376 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
1377 .get_mac_addr = &ixgbe_get_mac_addr_generic,
0365e6e4 1378 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
04193058 1379 .get_device_caps = &ixgbe_get_device_caps_82599,
11afc1b1
PW		 1380 .stop_adapter = &ixgbe_stop_adapter_generic,
1381 .get_bus_info = &ixgbe_get_bus_info_generic,
1382 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
1383 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
1384 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
1385 .setup_link = &ixgbe_setup_mac_link_82599,
1386 .setup_link_speed = &ixgbe_setup_mac_link_speed_82599,
1387 .check_link = &ixgbe_check_mac_link_82599,
1388 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
1389 .led_on = &ixgbe_led_on_generic,
1390 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 1391 .blink_led_start = &ixgbe_blink_led_start_generic,
1392 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 1393 .set_rar = &ixgbe_set_rar_generic,
1394 .clear_rar = &ixgbe_clear_rar_generic,
1395 .set_vmdq = &ixgbe_set_vmdq_82599,
1396 .clear_vmdq = &ixgbe_clear_vmdq_82599,
1397 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1398 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1399 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1400 .enable_mc = &ixgbe_enable_mc_generic,
1401 .disable_mc = &ixgbe_disable_mc_generic,
1402 .clear_vfta = &ixgbe_clear_vfta_82599,
1403 .set_vfta = &ixgbe_set_vfta_82599,
1404 .setup_fc = &ixgbe_setup_fc_generic,
1405 .init_uta_tables = &ixgbe_init_uta_tables_82599,
1406 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
1407};
1408
1409static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
1410 .init_params = &ixgbe_init_eeprom_params_generic,
1411 .read = &ixgbe_read_eeprom_generic,
1412 .write = &ixgbe_write_eeprom_generic,
1413 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1414 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1415};
1416
1417static struct ixgbe_phy_operations phy_ops_82599 = {
1418 .identify = &ixgbe_identify_phy_82599,
1419 .identify_sfp = &ixgbe_identify_sfp_module_generic,
04f165ef 1420 .init = &ixgbe_init_phy_ops_82599,
11afc1b1
PW		 1421 .reset = &ixgbe_reset_phy_generic,
1422 .read_reg = &ixgbe_read_phy_reg_generic,
1423 .write_reg = &ixgbe_write_phy_reg_generic,
1424 .setup_link = &ixgbe_setup_phy_link_generic,
1425 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1426 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
1427 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
1428 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
1429 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
1430};
1431
1432struct ixgbe_info ixgbe_82599_info = {
1433 .mac = ixgbe_mac_82599EB,
1434 .get_invariants = &ixgbe_get_invariants_82599,
1435 .mac_ops = &mac_ops_82599,
1436 .eeprom_ops = &eeprom_ops_82599,
1437 .phy_ops = &phy_ops_82599,
1438};
Linux kernel - Deliverables
This page took 0.118583 seconds and 5 git commands to generate.