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ixgbe: add support for 64k EEPROM for 82599
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
11afc1b1
PW		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
096a58fd 34#include "ixgbe_mbx.h"
11afc1b1
PW		 35
36#define IXGBE_82599_MAX_TX_QUEUES 128
37#define IXGBE_82599_MAX_RX_QUEUES 128
38#define IXGBE_82599_RAR_ENTRIES 128
39#define IXGBE_82599_MC_TBL_SIZE 128
40#define IXGBE_82599_VFT_TBL_SIZE 128
e09ad236 41#define IXGBE_82599_RX_PB_SIZE 512
11afc1b1 42
5d5b7c39
ET		 43static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
48 bool autoneg,
49 bool autoneg_wait_to_complete);
cd7e1f0b
DS		 50static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed,
52 bool autoneg,
53 bool autoneg_wait_to_complete);
5d5b7c39
ET		 54static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
55 bool autoneg_wait_to_complete);
56static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
8620a103
MC		 57 ixgbe_link_speed speed,
58 bool autoneg,
59 bool autoneg_wait_to_complete);
8620a103
MC		 60static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
61 ixgbe_link_speed speed,
62 bool autoneg,
63 bool autoneg_wait_to_complete);
794caeb2 64static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
0fa6d832 65static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
11afc1b1 66
7b25cdba 67static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 68{
69 struct ixgbe_mac_info *mac = &hw->mac;
c6ecf39a
DS		 70
71 /* enable the laser control functions for SFP+ fiber */
72 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
61fac744
PW		 73 mac->ops.disable_tx_laser =
74 &ixgbe_disable_tx_laser_multispeed_fiber;
75 mac->ops.enable_tx_laser =
76 &ixgbe_enable_tx_laser_multispeed_fiber;
1097cd17 77 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
11afc1b1 78 } else {
61fac744
PW		 79 mac->ops.disable_tx_laser = NULL;
80 mac->ops.enable_tx_laser = NULL;
1097cd17 81 mac->ops.flap_tx_laser = NULL;
c6ecf39a
DS		 82 }
83
84 if (hw->phy.multispeed_fiber) {
85 /* Set up dual speed SFP+ support */
86 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
87 } else {
cd7e1f0b
DS		 88 if ((mac->ops.get_media_type(hw) ==
89 ixgbe_media_type_backplane) &&
90 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
0fa6d832
ET		 91 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
92 !ixgbe_verify_lesm_fw_enabled_82599(hw))
cd7e1f0b
DS		 93 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
94 else
95 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
11afc1b1
PW		 96 }
97}
98
7b25cdba 99static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 100{
101 s32 ret_val = 0;
a7f5a5fc
DS		 102 u32 reg_anlp1 = 0;
103 u32 i = 0;
11afc1b1
PW		 104 u16 list_offset, data_offset, data_value;
105
106 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
107 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 108
109 hw->phy.ops.reset = NULL;
110
11afc1b1
PW		 111 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
112 &data_offset);
113
114 if (ret_val != 0)
115 goto setup_sfp_out;
116
aa5aec88 117 /* PHY config will finish before releasing the semaphore */
5e655105
DS		 118 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
119 IXGBE_GSSR_MAC_CSR_SM);
aa5aec88
PWJ		 120 if (ret_val != 0) {
121 ret_val = IXGBE_ERR_SWFW_SYNC;
122 goto setup_sfp_out;
123 }
124
11afc1b1
PW		 125 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
126 while (data_value != 0xffff) {
127 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
128 IXGBE_WRITE_FLUSH(hw);
129 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
130 }
aa5aec88
PWJ		 131
132 /* Release the semaphore */
133 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
032b4325
DS		 134 /*
135 * Delay obtaining semaphore again to allow FW access,
136 * semaphore_delay is in ms usleep_range needs us.
137 */
138 usleep_range(hw->eeprom.semaphore_delay * 1000,
139 hw->eeprom.semaphore_delay * 2000);
a7f5a5fc
DS		 140
141 /* Now restart DSP by setting Restart_AN and clearing LMS */
142 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
143 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
144 IXGBE_AUTOC_AN_RESTART));
145
146 /* Wait for AN to leave state 0 */
147 for (i = 0; i < 10; i++) {
032b4325 148 usleep_range(4000, 8000);
a7f5a5fc
DS		 149 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
150 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
151 break;
152 }
153 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
154 hw_dbg(hw, "sfp module setup not complete\n");
155 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
156 goto setup_sfp_out;
157 }
158
159 /* Restart DSP by setting Restart_AN and return to SFI mode */
160 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
161 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
162 IXGBE_AUTOC_AN_RESTART));
11afc1b1
PW		 163 }
164
165setup_sfp_out:
166 return ret_val;
167}
168
11afc1b1
PW		 169static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
170{
171 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 172
04f165ef 173 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 174
04f165ef
PW		 175 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
176 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
177 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
178 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
179 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
21ce849b 180 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
11afc1b1 181
04f165ef
PW		 182 return 0;
183}
11afc1b1 184
04f165ef
PW		 185/**
186 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
187 * @hw: pointer to hardware structure
188 *
189 * Initialize any function pointers that were not able to be
190 * set during get_invariants because the PHY/SFP type was
191 * not known. Perform the SFP init if necessary.
192 *
193 **/
7b25cdba 194static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
04f165ef
PW		 195{
196 struct ixgbe_mac_info *mac = &hw->mac;
197 struct ixgbe_phy_info *phy = &hw->phy;
198 s32 ret_val = 0;
11afc1b1 199
04f165ef
PW		 200 /* Identify the PHY or SFP module */
201 ret_val = phy->ops.identify(hw);
202
203 /* Setup function pointers based on detected SFP module and speeds */
204 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 205
206 /* If copper media, overwrite with copper function pointers */
207 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
208 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
11afc1b1 209 mac->ops.get_link_capabilities =
a391f1d5 210 &ixgbe_get_copper_link_capabilities_generic;
11afc1b1
PW		 211 }
212
04f165ef 213 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 214 switch (hw->phy.type) {
215 case ixgbe_phy_tn:
216 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
217 phy->ops.get_firmware_version =
04f165ef 218 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1 219 break;
fe15e8e1
DS		 220 case ixgbe_phy_aq:
221 phy->ops.get_firmware_version =
222 &ixgbe_get_phy_firmware_version_generic;
223 break;
11afc1b1
PW		 224 default:
225 break;
226 }
227
11afc1b1
PW		 228 return ret_val;
229}
230
231/**
232 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
233 * @hw: pointer to hardware structure
234 * @speed: pointer to link speed
235 * @negotiation: true when autoneg or autotry is enabled
236 *
237 * Determines the link capabilities by reading the AUTOC register.
238 **/
7b25cdba
DS		 239static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
240 ixgbe_link_speed *speed,
241 bool *negotiation)
11afc1b1
PW		 242{
243 s32 status = 0;
1eb99d5a 244 u32 autoc = 0;
11afc1b1 245
cb836a97
DS		 246 /* Determine 1G link capabilities off of SFP+ type */
247 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
248 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
249 *speed = IXGBE_LINK_SPEED_1GB_FULL;
250 *negotiation = true;
251 goto out;
252 }
253
1eb99d5a
PW		 254 /*
255 * Determine link capabilities based on the stored value of AUTOC,
256 * which represents EEPROM defaults. If AUTOC value has not been
257 * stored, use the current register value.
258 */
259 if (hw->mac.orig_link_settings_stored)
260 autoc = hw->mac.orig_autoc;
261 else
262 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
263
264 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 265 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
266 *speed = IXGBE_LINK_SPEED_1GB_FULL;
267 *negotiation = false;
268 break;
269
270 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
271 *speed = IXGBE_LINK_SPEED_10GB_FULL;
272 *negotiation = false;
273 break;
274
275 case IXGBE_AUTOC_LMS_1G_AN:
276 *speed = IXGBE_LINK_SPEED_1GB_FULL;
277 *negotiation = true;
278 break;
279
280 case IXGBE_AUTOC_LMS_10G_SERIAL:
281 *speed = IXGBE_LINK_SPEED_10GB_FULL;
282 *negotiation = false;
283 break;
284
285 case IXGBE_AUTOC_LMS_KX4_KX_KR:
286 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
287 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 288 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 289 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 290 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 291 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 292 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 293 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
294 *negotiation = true;
295 break;
296
297 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
298 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 299 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 300 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 301 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 302 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 303 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 304 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
305 *negotiation = true;
306 break;
307
308 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
309 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
310 *negotiation = false;
311 break;
312
313 default:
314 status = IXGBE_ERR_LINK_SETUP;
315 goto out;
316 break;
317 }
318
319 if (hw->phy.multispeed_fiber) {
320 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
321 IXGBE_LINK_SPEED_1GB_FULL;
322 *negotiation = true;
323 }
324
325out:
326 return status;
327}
328
11afc1b1
PW		 329/**
330 * ixgbe_get_media_type_82599 - Get media type
331 * @hw: pointer to hardware structure
332 *
333 * Returns the media type (fiber, copper, backplane)
334 **/
7b25cdba 335static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 336{
337 enum ixgbe_media_type media_type;
338
339 /* Detect if there is a copper PHY attached. */
21cc5b4f
ET		 340 switch (hw->phy.type) {
341 case ixgbe_phy_cu_unknown:
342 case ixgbe_phy_tn:
343 case ixgbe_phy_aq:
11afc1b1
PW		 344 media_type = ixgbe_media_type_copper;
345 goto out;
21cc5b4f
ET		 346 default:
347 break;
11afc1b1
PW		 348 }
349
350 switch (hw->device_id) {
11afc1b1 351 case IXGBE_DEV_ID_82599_KX4:
dbfec662 352 case IXGBE_DEV_ID_82599_KX4_MEZZ:
312eb931 353 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
74757d49 354 case IXGBE_DEV_ID_82599_KR:
dbffcb21 355 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
1fcf03e6 356 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 357 /* Default device ID is mezzanine card KX/KX4 */
358 media_type = ixgbe_media_type_backplane;
359 break;
360 case IXGBE_DEV_ID_82599_SFP:
dbffcb21 361 case IXGBE_DEV_ID_82599_SFP_FCOE:
38ad1c8e 362 case IXGBE_DEV_ID_82599_SFP_EM:
4c40ef02 363 case IXGBE_DEV_ID_82599_SFP_SF2:
11afc1b1
PW		 364 media_type = ixgbe_media_type_fiber;
365 break;
8911184f 366 case IXGBE_DEV_ID_82599_CX4:
6b1be199 367 media_type = ixgbe_media_type_cx4;
8911184f 368 break;
21cc5b4f
ET		 369 case IXGBE_DEV_ID_82599_T3_LOM:
370 media_type = ixgbe_media_type_copper;
371 break;
11afc1b1
PW		 372 default:
373 media_type = ixgbe_media_type_unknown;
374 break;
375 }
376out:
377 return media_type;
378}
379
380/**
8620a103 381 * ixgbe_start_mac_link_82599 - Setup MAC link settings
11afc1b1 382 * @hw: pointer to hardware structure
8620a103 383 * @autoneg_wait_to_complete: true when waiting for completion is needed
11afc1b1
PW		 384 *
385 * Configures link settings based on values in the ixgbe_hw struct.
386 * Restarts the link. Performs autonegotiation if needed.
387 **/
5d5b7c39 388static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
8620a103 389 bool autoneg_wait_to_complete)
11afc1b1
PW		 390{
391 u32 autoc_reg;
392 u32 links_reg;
393 u32 i;
394 s32 status = 0;
395
396 /* Restart link */
397 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
398 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
399 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
400
401 /* Only poll for autoneg to complete if specified to do so */
8620a103 402 if (autoneg_wait_to_complete) {
11afc1b1
PW		 403 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
404 IXGBE_AUTOC_LMS_KX4_KX_KR ||
405 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
406 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
407 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
408 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
409 links_reg = 0; /* Just in case Autoneg time = 0 */
410 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
411 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
412 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
413 break;
414 msleep(100);
415 }
416 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
417 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
418 hw_dbg(hw, "Autoneg did not complete.\n");
419 }
420 }
421 }
422
11afc1b1
PW		 423 /* Add delay to filter out noises during initial link setup */
424 msleep(50);
425
426 return status;
427}
428
8c7bea32
ET		 429/**
430 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
431 * @hw: pointer to hardware structure
432 *
433 * The base drivers may require better control over SFP+ module
434 * PHY states. This includes selectively shutting down the Tx
435 * laser on the PHY, effectively halting physical link.
436 **/
5d5b7c39 437static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
61fac744
PW		 438{
439 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
440
441 /* Disable tx laser; allow 100us to go dark per spec */
442 esdp_reg |= IXGBE_ESDP_SDP3;
443 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
444 IXGBE_WRITE_FLUSH(hw);
445 udelay(100);
446}
447
448/**
449 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
450 * @hw: pointer to hardware structure
451 *
452 * The base drivers may require better control over SFP+ module
453 * PHY states. This includes selectively turning on the Tx
454 * laser on the PHY, effectively starting physical link.
455 **/
5d5b7c39 456static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
61fac744
PW		 457{
458 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
459
460 /* Enable tx laser; allow 100ms to light up */
461 esdp_reg &= ~IXGBE_ESDP_SDP3;
462 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
463 IXGBE_WRITE_FLUSH(hw);
464 msleep(100);
465}
466
1097cd17
MC		 467/**
468 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
469 * @hw: pointer to hardware structure
470 *
471 * When the driver changes the link speeds that it can support,
472 * it sets autotry_restart to true to indicate that we need to
473 * initiate a new autotry session with the link partner. To do
474 * so, we set the speed then disable and re-enable the tx laser, to
475 * alert the link partner that it also needs to restart autotry on its
476 * end. This is consistent with true clause 37 autoneg, which also
477 * involves a loss of signal.
478 **/
5d5b7c39 479static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
1097cd17 480{
1097cd17 481 if (hw->mac.autotry_restart) {
61fac744
PW		 482 ixgbe_disable_tx_laser_multispeed_fiber(hw);
483 ixgbe_enable_tx_laser_multispeed_fiber(hw);
1097cd17
MC		 484 hw->mac.autotry_restart = false;
485 }
486}
487
11afc1b1 488/**
8620a103 489 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
11afc1b1
PW		 490 * @hw: pointer to hardware structure
491 * @speed: new link speed
492 * @autoneg: true if autonegotiation enabled
493 * @autoneg_wait_to_complete: true when waiting for completion is needed
494 *
495 * Set the link speed in the AUTOC register and restarts link.
496 **/
8620a103
MC		 497s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
498 ixgbe_link_speed speed,
499 bool autoneg,
500 bool autoneg_wait_to_complete)
11afc1b1
PW		 501{
502 s32 status = 0;
037c6d0a 503 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
11afc1b1
PW		 504 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
505 u32 speedcnt = 0;
506 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
037c6d0a 507 u32 i = 0;
11afc1b1
PW		 508 bool link_up = false;
509 bool negotiation;
510
511 /* Mask off requested but non-supported speeds */
037c6d0a
ET		 512 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
513 &negotiation);
514 if (status != 0)
515 return status;
516
517 speed &= link_speed;
11afc1b1
PW		 518
519 /*
520 * Try each speed one by one, highest priority first. We do this in
521 * software because 10gb fiber doesn't support speed autonegotiation.
522 */
523 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
524 speedcnt++;
525 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
526
50ac58ba 527 /* If we already have link at this speed, just jump out */
037c6d0a
ET		 528 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
529 false);
530 if (status != 0)
531 return status;
50ac58ba 532
037c6d0a 533 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
50ac58ba
PWJ		 534 goto out;
535
536 /* Set the module link speed */
11afc1b1
PW		 537 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
538 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
1097cd17 539 IXGBE_WRITE_FLUSH(hw);
11afc1b1 540
50ac58ba
PWJ		 541 /* Allow module to change analog characteristics (1G->10G) */
542 msleep(40);
11afc1b1 543
8620a103 544 status = ixgbe_setup_mac_link_82599(hw,
037c6d0a
ET		 545 IXGBE_LINK_SPEED_10GB_FULL,
546 autoneg,
547 autoneg_wait_to_complete);
50ac58ba 548 if (status != 0)
c3c74327 549 return status;
50ac58ba
PWJ		 550
551 /* Flap the tx laser if it has not already been done */
1097cd17 552 hw->mac.ops.flap_tx_laser(hw);
50ac58ba 553
cd7e1f0b
DS		 554 /*
555 * Wait for the controller to acquire link. Per IEEE 802.3ap,
556 * Section 73.10.2, we may have to wait up to 500ms if KR is
557 * attempted. 82599 uses the same timing for 10g SFI.
558 */
50ac58ba
PWJ		 559 for (i = 0; i < 5; i++) {
560 /* Wait for the link partner to also set speed */
561 msleep(100);
562
563 /* If we have link, just jump out */
037c6d0a
ET		 564 status = hw->mac.ops.check_link(hw, &link_speed,
565 &link_up, false);
566 if (status != 0)
567 return status;
568
50ac58ba
PWJ		 569 if (link_up)
570 goto out;
571 }
11afc1b1
PW		 572 }
573
574 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
575 speedcnt++;
576 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
577 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
578
50ac58ba 579 /* If we already have link at this speed, just jump out */
037c6d0a
ET		 580 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
581 false);
582 if (status != 0)
583 return status;
50ac58ba 584
037c6d0a 585 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
50ac58ba
PWJ		 586 goto out;
587
588 /* Set the module link speed */
11afc1b1
PW		 589 esdp_reg &= ~IXGBE_ESDP_SDP5;
590 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
591 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
1097cd17 592 IXGBE_WRITE_FLUSH(hw);
11afc1b1 593
50ac58ba
PWJ		 594 /* Allow module to change analog characteristics (10G->1G) */
595 msleep(40);
11afc1b1 596
8620a103 597 status = ixgbe_setup_mac_link_82599(hw,
037c6d0a
ET		 598 IXGBE_LINK_SPEED_1GB_FULL,
599 autoneg,
600 autoneg_wait_to_complete);
50ac58ba 601 if (status != 0)
c3c74327 602 return status;
50ac58ba
PWJ		 603
604 /* Flap the tx laser if it has not already been done */
1097cd17 605 hw->mac.ops.flap_tx_laser(hw);
50ac58ba
PWJ		 606
607 /* Wait for the link partner to also set speed */
608 msleep(100);
11afc1b1
PW		 609
610 /* If we have link, just jump out */
037c6d0a
ET		 611 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
612 false);
613 if (status != 0)
614 return status;
615
11afc1b1
PW		 616 if (link_up)
617 goto out;
618 }
619
620 /*
621 * We didn't get link. Configure back to the highest speed we tried,
622 * (if there was more than one). We call ourselves back with just the
623 * single highest speed that the user requested.
624 */
625 if (speedcnt > 1)
8620a103
MC		 626 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
627 highest_link_speed,
628 autoneg,
629 autoneg_wait_to_complete);
11afc1b1
PW		 630
631out:
c3c74327
MC		 632 /* Set autoneg_advertised value based on input link speed */
633 hw->phy.autoneg_advertised = 0;
634
635 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
636 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
637
638 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
639 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
640
11afc1b1
PW		 641 return status;
642}
643
cd7e1f0b
DS		 644/**
645 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
646 * @hw: pointer to hardware structure
647 * @speed: new link speed
648 * @autoneg: true if autonegotiation enabled
649 * @autoneg_wait_to_complete: true when waiting for completion is needed
650 *
651 * Implements the Intel SmartSpeed algorithm.
652 **/
653static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
654 ixgbe_link_speed speed, bool autoneg,
655 bool autoneg_wait_to_complete)
656{
657 s32 status = 0;
037c6d0a 658 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
cd7e1f0b
DS		 659 s32 i, j;
660 bool link_up = false;
661 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
cd7e1f0b
DS		 662
663 /* Set autoneg_advertised value based on input link speed */
664 hw->phy.autoneg_advertised = 0;
665
666 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
667 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
668
669 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
670 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
671
672 if (speed & IXGBE_LINK_SPEED_100_FULL)
673 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
674
675 /*
676 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
677 * autoneg advertisement if link is unable to be established at the
678 * highest negotiated rate. This can sometimes happen due to integrity
679 * issues with the physical media connection.
680 */
681
682 /* First, try to get link with full advertisement */
683 hw->phy.smart_speed_active = false;
684 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
685 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
686 autoneg_wait_to_complete);
037c6d0a 687 if (status != 0)
cd7e1f0b
DS		 688 goto out;
689
690 /*
691 * Wait for the controller to acquire link. Per IEEE 802.3ap,
692 * Section 73.10.2, we may have to wait up to 500ms if KR is
693 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
694 * Table 9 in the AN MAS.
695 */
696 for (i = 0; i < 5; i++) {
697 mdelay(100);
698
699 /* If we have link, just jump out */
037c6d0a
ET		 700 status = hw->mac.ops.check_link(hw, &link_speed,
701 &link_up, false);
702 if (status != 0)
703 goto out;
704
cd7e1f0b
DS		 705 if (link_up)
706 goto out;
707 }
708 }
709
710 /*
711 * We didn't get link. If we advertised KR plus one of KX4/KX
712 * (or BX4/BX), then disable KR and try again.
713 */
714 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
715 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
716 goto out;
717
718 /* Turn SmartSpeed on to disable KR support */
719 hw->phy.smart_speed_active = true;
720 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
721 autoneg_wait_to_complete);
037c6d0a 722 if (status != 0)
cd7e1f0b
DS		 723 goto out;
724
725 /*
726 * Wait for the controller to acquire link. 600ms will allow for
727 * the AN link_fail_inhibit_timer as well for multiple cycles of
728 * parallel detect, both 10g and 1g. This allows for the maximum
729 * connect attempts as defined in the AN MAS table 73-7.
730 */
731 for (i = 0; i < 6; i++) {
732 mdelay(100);
733
734 /* If we have link, just jump out */
037c6d0a
ET		 735 status = hw->mac.ops.check_link(hw, &link_speed,
736 &link_up, false);
737 if (status != 0)
738 goto out;
739
cd7e1f0b
DS		 740 if (link_up)
741 goto out;
742 }
743
744 /* We didn't get link. Turn SmartSpeed back off. */
745 hw->phy.smart_speed_active = false;
746 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
747 autoneg_wait_to_complete);
748
749out:
c4ee6a53 750 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
037c6d0a 751 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
849c4542 752 "the maximum advertised\n");
cd7e1f0b
DS		 753 return status;
754}
755
11afc1b1 756/**
8620a103 757 * ixgbe_setup_mac_link_82599 - Set MAC link speed
11afc1b1
PW		 758 * @hw: pointer to hardware structure
759 * @speed: new link speed
760 * @autoneg: true if autonegotiation enabled
761 * @autoneg_wait_to_complete: true when waiting for completion is needed
762 *
763 * Set the link speed in the AUTOC register and restarts link.
764 **/
5d5b7c39 765static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
8620a103
MC		 766 ixgbe_link_speed speed, bool autoneg,
767 bool autoneg_wait_to_complete)
11afc1b1
PW		 768{
769 s32 status = 0;
770 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
771 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
50ac58ba 772 u32 start_autoc = autoc;
1eb99d5a 773 u32 orig_autoc = 0;
11afc1b1
PW		 774 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
775 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
776 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
777 u32 links_reg;
778 u32 i;
779 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
780
781 /* Check to see if speed passed in is supported. */
782 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
0b0c2b31
ET		 783 if (status != 0)
784 goto out;
785
11afc1b1
PW		 786 speed &= link_capabilities;
787
50ac58ba
PWJ		 788 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
789 status = IXGBE_ERR_LINK_SETUP;
790 goto out;
791 }
792
1eb99d5a
PW		 793 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
794 if (hw->mac.orig_link_settings_stored)
795 orig_autoc = hw->mac.orig_autoc;
796 else
797 orig_autoc = autoc;
798
50ac58ba
PWJ		 799 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
800 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
801 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
11afc1b1
PW		 802 /* Set KX4/KX/KR support according to speed requested */
803 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
804 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 805 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 806 autoc |= IXGBE_AUTOC_KX4_SUPP;
cd7e1f0b
DS		 807 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
808 (hw->phy.smart_speed_active == false))
11afc1b1
PW		 809 autoc |= IXGBE_AUTOC_KR_SUPP;
810 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
811 autoc |= IXGBE_AUTOC_KX_SUPP;
812 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
813 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
814 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
815 /* Switch from 1G SFI to 10G SFI if requested */
816 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
817 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
818 autoc &= ~IXGBE_AUTOC_LMS_MASK;
819 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
820 }
821 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
822 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
823 /* Switch from 10G SFI to 1G SFI if requested */
824 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
825 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
826 autoc &= ~IXGBE_AUTOC_LMS_MASK;
827 if (autoneg)
828 autoc |= IXGBE_AUTOC_LMS_1G_AN;
829 else
830 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
831 }
832 }
833
50ac58ba 834 if (autoc != start_autoc) {
11afc1b1
PW		 835 /* Restart link */
836 autoc |= IXGBE_AUTOC_AN_RESTART;
837 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
838
839 /* Only poll for autoneg to complete if specified to do so */
840 if (autoneg_wait_to_complete) {
841 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
842 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
843 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
844 links_reg = 0; /*Just in case Autoneg time=0*/
845 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
846 links_reg =
847 IXGBE_READ_REG(hw, IXGBE_LINKS);
848 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
849 break;
850 msleep(100);
851 }
852 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
853 status =
854 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
855 hw_dbg(hw, "Autoneg did not "
856 "complete.\n");
857 }
858 }
859 }
860
11afc1b1
PW		 861 /* Add delay to filter out noises during initial link setup */
862 msleep(50);
863 }
864
50ac58ba 865out:
11afc1b1
PW		 866 return status;
867}
868
869/**
8620a103 870 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
11afc1b1
PW		 871 * @hw: pointer to hardware structure
872 * @speed: new link speed
873 * @autoneg: true if autonegotiation enabled
874 * @autoneg_wait_to_complete: true if waiting is needed to complete
875 *
876 * Restarts link on PHY and MAC based on settings passed in.
877 **/
8620a103
MC		 878static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
879 ixgbe_link_speed speed,
880 bool autoneg,
881 bool autoneg_wait_to_complete)
11afc1b1
PW		 882{
883 s32 status;
884
885 /* Setup the PHY according to input speed */
886 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
887 autoneg_wait_to_complete);
888 /* Set up MAC */
8620a103 889 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
11afc1b1
PW		 890
891 return status;
892}
893
894/**
895 * ixgbe_reset_hw_82599 - Perform hardware reset
896 * @hw: pointer to hardware structure
897 *
898 * Resets the hardware by resetting the transmit and receive units, masks
899 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
900 * reset.
901 **/
7b25cdba 902static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 903{
904 s32 status = 0;
c9205697 905 u32 ctrl;
11afc1b1
PW		 906 u32 i;
907 u32 autoc;
908 u32 autoc2;
909
910 /* Call adapter stop to disable tx/rx and clear interrupts */
911 hw->mac.ops.stop_adapter(hw);
912
553b4497 913 /* PHY ops must be identified and initialized prior to reset */
04f165ef 914
037c6d0a 915 /* Identify PHY and related function pointers */
553b4497 916 status = hw->phy.ops.init(hw);
04f165ef 917
553b4497
PW		 918 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
919 goto reset_hw_out;
04f165ef 920
553b4497
PW		 921 /* Setup SFP module if there is one present. */
922 if (hw->phy.sfp_setup_needed) {
923 status = hw->mac.ops.setup_sfp(hw);
924 hw->phy.sfp_setup_needed = false;
04f165ef 925 }
11afc1b1 926
037c6d0a
ET		 927 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
928 goto reset_hw_out;
929
553b4497
PW		 930 /* Reset PHY */
931 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
932 hw->phy.ops.reset(hw);
933
11afc1b1
PW		 934 /*
935 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
936 * access and verify no pending requests before reset
937 */
a4297dc2 938 ixgbe_disable_pcie_master(hw);
11afc1b1 939
a4297dc2 940mac_reset_top:
11afc1b1
PW		 941 /*
942 * Issue global reset to the MAC. This needs to be a SW reset.
943 * If link reset is used, it might reset the MAC when mng is using it
944 */
945 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
946 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
947 IXGBE_WRITE_FLUSH(hw);
948
949 /* Poll for reset bit to self-clear indicating reset is complete */
950 for (i = 0; i < 10; i++) {
951 udelay(1);
952 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
953 if (!(ctrl & IXGBE_CTRL_RST))
954 break;
955 }
956 if (ctrl & IXGBE_CTRL_RST) {
957 status = IXGBE_ERR_RESET_FAILED;
958 hw_dbg(hw, "Reset polling failed to complete.\n");
959 }
11afc1b1 960
a4297dc2
ET		 961 /*
962 * Double resets are required for recovery from certain error
963 * conditions. Between resets, it is necessary to stall to allow time
964 * for any pending HW events to complete. We use 1usec since that is
965 * what is needed for ixgbe_disable_pcie_master(). The second reset
966 * then clears out any effects of those events.
967 */
968 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
969 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
970 udelay(1);
971 goto mac_reset_top;
972 }
973
11afc1b1
PW		 974 msleep(50);
975
11afc1b1
PW		 976 /*
977 * Store the original AUTOC/AUTOC2 values if they have not been
978 * stored off yet. Otherwise restore the stored original
979 * values since the reset operation sets back to defaults.
980 */
981 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
982 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
983 if (hw->mac.orig_link_settings_stored == false) {
984 hw->mac.orig_autoc = autoc;
985 hw->mac.orig_autoc2 = autoc2;
986 hw->mac.orig_link_settings_stored = true;
4df10466 987 } else {
11afc1b1
PW		 988 if (autoc != hw->mac.orig_autoc)
989 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
990 IXGBE_AUTOC_AN_RESTART));
991
992 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
993 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
994 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
995 autoc2 |= (hw->mac.orig_autoc2 &
996 IXGBE_AUTOC2_UPPER_MASK);
997 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
998 }
999 }
1000
278675d8
ET		 1001 /* Store the permanent mac address */
1002 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1003
aca6bee7
WJP		 1004 /*
1005 * Store MAC address from RAR0, clear receive address registers, and
1006 * clear the multicast table. Also reset num_rar_entries to 128,
1007 * since we modify this value when programming the SAN MAC address.
1008 */
1009 hw->mac.num_rar_entries = 128;
1010 hw->mac.ops.init_rx_addrs(hw);
1011
0365e6e4
PW		 1012 /* Store the permanent SAN mac address */
1013 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1014
aca6bee7
WJP		 1015 /* Add the SAN MAC address to the RAR only if it's a valid address */
1016 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1017 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1018 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1019
1020 /* Reserve the last RAR for the SAN MAC address */
1021 hw->mac.num_rar_entries--;
1022 }
1023
383ff34b
YZ		 1024 /* Store the alternative WWNN/WWPN prefix */
1025 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1026 &hw->mac.wwpn_prefix);
1027
04f165ef 1028reset_hw_out:
11afc1b1
PW		 1029 return status;
1030}
1031
ffff4772
PWJ		 1032/**
1033 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1034 * @hw: pointer to hardware structure
1035 **/
1036s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1037{
1038 int i;
1039 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1040 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1041
1042 /*
1043 * Before starting reinitialization process,
1044 * FDIRCMD.CMD must be zero.
1045 */
1046 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1047 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1048 IXGBE_FDIRCMD_CMD_MASK))
1049 break;
1050 udelay(10);
1051 }
1052 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
905e4a41 1053 hw_dbg(hw, "Flow Director previous command isn't complete, "
d6dbee86 1054 "aborting table re-initialization.\n");
ffff4772
PWJ		 1055 return IXGBE_ERR_FDIR_REINIT_FAILED;
1056 }
1057
1058 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1059 IXGBE_WRITE_FLUSH(hw);
1060 /*
1061 * 82599 adapters flow director init flow cannot be restarted,
1062 * Workaround 82599 silicon errata by performing the following steps
1063 * before re-writing the FDIRCTRL control register with the same value.
1064 * - write 1 to bit 8 of FDIRCMD register &
1065 * - write 0 to bit 8 of FDIRCMD register
1066 */
1067 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1068 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1069 IXGBE_FDIRCMD_CLEARHT));
1070 IXGBE_WRITE_FLUSH(hw);
1071 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1072 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1073 ~IXGBE_FDIRCMD_CLEARHT));
1074 IXGBE_WRITE_FLUSH(hw);
1075 /*
1076 * Clear FDIR Hash register to clear any leftover hashes
1077 * waiting to be programmed.
1078 */
1079 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1080 IXGBE_WRITE_FLUSH(hw);
1081
1082 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1083 IXGBE_WRITE_FLUSH(hw);
1084
1085 /* Poll init-done after we write FDIRCTRL register */
1086 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1087 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1088 IXGBE_FDIRCTRL_INIT_DONE)
1089 break;
1090 udelay(10);
1091 }
1092 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1093 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1094 return IXGBE_ERR_FDIR_REINIT_FAILED;
1095 }
1096
1097 /* Clear FDIR statistics registers (read to clear) */
1098 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1099 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1100 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1101 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1102 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1103
1104 return 0;
1105}
1106
1107/**
1108 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1109 * @hw: pointer to hardware structure
1110 * @pballoc: which mode to allocate filters with
1111 **/
1112s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1113{
1114 u32 fdirctrl = 0;
1115 u32 pbsize;
1116 int i;
1117
1118 /*
1119 * Before enabling Flow Director, the Rx Packet Buffer size
1120 * must be reduced. The new value is the current size minus
1121 * flow director memory usage size.
1122 */
1123 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1124 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1125 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1126
1127 /*
1128 * The defaults in the HW for RX PB 1-7 are not zero and so should be
b595076a 1129 * initialized to zero for non DCB mode otherwise actual total RX PB
ffff4772
PWJ		 1130 * would be bigger than programmed and filter space would run into
1131 * the PB 0 region.
1132 */
1133 for (i = 1; i < 8; i++)
1134 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1135
1136 /* Send interrupt when 64 filters are left */
1137 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1138
1139 /* Set the maximum length per hash bucket to 0xA filters */
1140 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1141
1142 switch (pballoc) {
1143 case IXGBE_FDIR_PBALLOC_64K:
1144 /* 8k - 1 signature filters */
1145 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1146 break;
1147 case IXGBE_FDIR_PBALLOC_128K:
1148 /* 16k - 1 signature filters */
1149 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1150 break;
1151 case IXGBE_FDIR_PBALLOC_256K:
1152 /* 32k - 1 signature filters */
1153 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1154 break;
1155 default:
1156 /* bad value */
1157 return IXGBE_ERR_CONFIG;
1158 };
1159
1160 /* Move the flexible bytes to use the ethertype - shift 6 words */
1161 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1162
ffff4772
PWJ		 1163
1164 /* Prime the keys for hashing */
905e4a41
AD		 1165 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1166 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
ffff4772
PWJ		 1167
1168 /*
1169 * Poll init-done after we write the register. Estimated times:
1170 * 10G: PBALLOC = 11b, timing is 60us
1171 * 1G: PBALLOC = 11b, timing is 600us
1172 * 100M: PBALLOC = 11b, timing is 6ms
1173 *
1174 * Multiple these timings by 4 if under full Rx load
1175 *
1176 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1177 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1178 * this might not finish in our poll time, but we can live with that
1179 * for now.
1180 */
1181 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1182 IXGBE_WRITE_FLUSH(hw);
1183 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1184 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1185 IXGBE_FDIRCTRL_INIT_DONE)
1186 break;
032b4325 1187 usleep_range(1000, 2000);
ffff4772
PWJ		 1188 }
1189 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1190 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1191
1192 return 0;
1193}
1194
1195/**
1196 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1197 * @hw: pointer to hardware structure
1198 * @pballoc: which mode to allocate filters with
1199 **/
1200s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1201{
1202 u32 fdirctrl = 0;
1203 u32 pbsize;
1204 int i;
1205
1206 /*
1207 * Before enabling Flow Director, the Rx Packet Buffer size
1208 * must be reduced. The new value is the current size minus
1209 * flow director memory usage size.
1210 */
1211 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1212 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1213 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1214
1215 /*
1216 * The defaults in the HW for RX PB 1-7 are not zero and so should be
b595076a 1217 * initialized to zero for non DCB mode otherwise actual total RX PB
ffff4772
PWJ		 1218 * would be bigger than programmed and filter space would run into
1219 * the PB 0 region.
1220 */
1221 for (i = 1; i < 8; i++)
1222 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1223
1224 /* Send interrupt when 64 filters are left */
1225 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1226
9a713e7c
PW		 1227 /* Initialize the drop queue to Rx queue 127 */
1228 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1229
ffff4772
PWJ		 1230 switch (pballoc) {
1231 case IXGBE_FDIR_PBALLOC_64K:
1232 /* 2k - 1 perfect filters */
1233 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1234 break;
1235 case IXGBE_FDIR_PBALLOC_128K:
1236 /* 4k - 1 perfect filters */
1237 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1238 break;
1239 case IXGBE_FDIR_PBALLOC_256K:
1240 /* 8k - 1 perfect filters */
1241 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1242 break;
1243 default:
1244 /* bad value */
1245 return IXGBE_ERR_CONFIG;
1246 };
1247
1248 /* Turn perfect match filtering on */
1249 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1250 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1251
1252 /* Move the flexible bytes to use the ethertype - shift 6 words */
1253 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1254
1255 /* Prime the keys for hashing */
905e4a41
AD		 1256 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1257 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
ffff4772
PWJ		 1258
1259 /*
1260 * Poll init-done after we write the register. Estimated times:
1261 * 10G: PBALLOC = 11b, timing is 60us
1262 * 1G: PBALLOC = 11b, timing is 600us
1263 * 100M: PBALLOC = 11b, timing is 6ms
1264 *
1265 * Multiple these timings by 4 if under full Rx load
1266 *
1267 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1268 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1269 * this might not finish in our poll time, but we can live with that
1270 * for now.
1271 */
1272
1273 /* Set the maximum length per hash bucket to 0xA filters */
1274 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1275
1276 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1277 IXGBE_WRITE_FLUSH(hw);
1278 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1279 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1280 IXGBE_FDIRCTRL_INIT_DONE)
1281 break;
032b4325 1282 usleep_range(1000, 2000);
ffff4772
PWJ		 1283 }
1284 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1285 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1286
1287 return 0;
1288}
1289
1290
1291/**
1292 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1293 * @stream: input bitstream to compute the hash on
1294 * @key: 32-bit hash key
1295 **/
905e4a41
AD		 1296static u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
1297 u32 key)
ffff4772
PWJ		 1298{
1299 /*
1300 * The algorithm is as follows:
1301 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1302 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1303 * and A[n] x B[n] is bitwise AND between same length strings
1304 *
1305 * K[n] is 16 bits, defined as:
1306 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1307 * for n modulo 32 < 15, K[n] =
1308 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1309 *
1310 * S[n] is 16 bits, defined as:
1311 * for n >= 15, S[n] = S[n:n - 15]
1312 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1313 *
1314 * To simplify for programming, the algorithm is implemented
1315 * in software this way:
1316 *
905e4a41
AD		 1317 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
1318 *
1319 * for (i = 0; i < 352; i+=32)
1320 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
1321 *
1322 * lo_hash_dword[15:0] ^= Stream[15:0];
1323 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
1324 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
ffff4772 1325 *
905e4a41 1326 * hi_hash_dword[31:0] ^= Stream[351:320];
ffff4772 1327 *
905e4a41
AD		 1328 * if(key[0])
1329 * hash[15:0] ^= Stream[15:0];
1330 *
1331 * for (i = 0; i < 16; i++) {
1332 * if (key[i])
1333 * hash[15:0] ^= lo_hash_dword[(i+15):i];
1334 * if (key[i + 16])
1335 * hash[15:0] ^= hi_hash_dword[(i+15):i];
ffff4772 1336 * }
905e4a41 1337 *
ffff4772 1338 */
905e4a41
AD		 1339 __be32 common_hash_dword = 0;
1340 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1341 u32 hash_result = 0;
1342 u8 i;
ffff4772 1343
905e4a41
AD		 1344 /* record the flow_vm_vlan bits as they are a key part to the hash */
1345 flow_vm_vlan = ntohl(atr_input->dword_stream[0]);
ffff4772 1346
905e4a41
AD		 1347 /* generate common hash dword */
1348 for (i = 10; i; i -= 2)
1349 common_hash_dword ^= atr_input->dword_stream[i] ^
1350 atr_input->dword_stream[i - 1];
ffff4772 1351
905e4a41 1352 hi_hash_dword = ntohl(common_hash_dword);
ffff4772 1353
905e4a41
AD		 1354 /* low dword is word swapped version of common */
1355 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
ffff4772 1356
905e4a41
AD		 1357 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1358 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
ffff4772 1359
905e4a41
AD		 1360 /* Process bits 0 and 16 */
1361 if (key & 0x0001) hash_result ^= lo_hash_dword;
1362 if (key & 0x00010000) hash_result ^= hi_hash_dword;
ffff4772
PWJ		 1363
1364 /*
905e4a41
AD		 1365 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1366 * delay this because bit 0 of the stream should not be processed
1367 * so we do not add the vlan until after bit 0 was processed
ffff4772 1368 */
905e4a41 1369 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
ffff4772 1370
905e4a41
AD		 1371
1372 /* process the remaining 30 bits in the key 2 bits at a time */
1373 for (i = 15; i; i-- ) {
1374 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
1375 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
ffff4772
PWJ		 1376 }
1377
905e4a41 1378 return hash_result & IXGBE_ATR_HASH_MASK;
ffff4772
PWJ		 1379}
1380
69830529
AD		 1381/*
1382 * These defines allow us to quickly generate all of the necessary instructions
1383 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1384 * for values 0 through 15
1385 */
1386#define IXGBE_ATR_COMMON_HASH_KEY \
1387 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1388#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1389do { \
1390 u32 n = (_n); \
1391 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1392 common_hash ^= lo_hash_dword >> n; \
1393 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1394 bucket_hash ^= lo_hash_dword >> n; \
1395 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1396 sig_hash ^= lo_hash_dword << (16 - n); \
1397 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1398 common_hash ^= hi_hash_dword >> n; \
1399 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1400 bucket_hash ^= hi_hash_dword >> n; \
1401 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1402 sig_hash ^= hi_hash_dword << (16 - n); \
1403} while (0);
1404
1405/**
1406 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1407 * @stream: input bitstream to compute the hash on
1408 *
1409 * This function is almost identical to the function above but contains
1410 * several optomizations such as unwinding all of the loops, letting the
1411 * compiler work out all of the conditional ifs since the keys are static
1412 * defines, and computing two keys at once since the hashed dword stream
1413 * will be the same for both keys.
1414 **/
1415static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1416 union ixgbe_atr_hash_dword common)
1417{
1418 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1419 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1420
1421 /* record the flow_vm_vlan bits as they are a key part to the hash */
1422 flow_vm_vlan = ntohl(input.dword);
1423
1424 /* generate common hash dword */
1425 hi_hash_dword = ntohl(common.dword);
1426
1427 /* low dword is word swapped version of common */
1428 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1429
1430 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1431 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1432
1433 /* Process bits 0 and 16 */
1434 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1435
1436 /*
1437 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1438 * delay this because bit 0 of the stream should not be processed
1439 * so we do not add the vlan until after bit 0 was processed
1440 */
1441 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1442
1443 /* Process remaining 30 bit of the key */
1444 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1445 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1446 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1447 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1448 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1449 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1450 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1451 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1452 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1453 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1454 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1455 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1456 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1457 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1458 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1459
1460 /* combine common_hash result with signature and bucket hashes */
1461 bucket_hash ^= common_hash;
1462 bucket_hash &= IXGBE_ATR_HASH_MASK;
1463
1464 sig_hash ^= common_hash << 16;
1465 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1466
1467 /* return completed signature hash */
1468 return sig_hash ^ bucket_hash;
1469}
1470
ffff4772
PWJ		 1471/**
1472 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1473 * @hw: pointer to hardware structure
69830529
AD		 1474 * @input: unique input dword
1475 * @common: compressed common input dword
ffff4772
PWJ		 1476 * @queue: queue index to direct traffic to
1477 **/
1478s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
69830529
AD		 1479 union ixgbe_atr_hash_dword input,
1480 union ixgbe_atr_hash_dword common,
ffff4772
PWJ		 1481 u8 queue)
1482{
1483 u64 fdirhashcmd;
905e4a41 1484 u32 fdircmd;
ffff4772
PWJ		 1485
1486 /*
905e4a41
AD		 1487 * Get the flow_type in order to program FDIRCMD properly
1488 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
ffff4772 1489 */
69830529 1490 switch (input.formatted.flow_type) {
905e4a41
AD		 1491 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1492 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1493 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1494 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1495 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1496 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
ffff4772
PWJ		 1497 break;
1498 default:
905e4a41 1499 hw_dbg(hw, " Error on flow type input\n");
ffff4772
PWJ		 1500 return IXGBE_ERR_CONFIG;
1501 }
1502
905e4a41
AD		 1503 /* configure FDIRCMD register */
1504 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1505 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
69830529 1506 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
905e4a41
AD		 1507 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1508
1509 /*
1510 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1511 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1512 */
1513 fdirhashcmd = (u64)fdircmd << 32;
69830529 1514 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
ffff4772
PWJ		 1515
1516 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1517
69830529
AD		 1518 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1519
ffff4772
PWJ		 1520 return 0;
1521}
1522
45b9f509
AD		 1523/**
1524 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1525 * @input_mask: mask to be bit swapped
1526 *
1527 * The source and destination port masks for flow director are bit swapped
1528 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1529 * generate a correctly swapped value we need to bit swap the mask and that
1530 * is what is accomplished by this function.
1531 **/
1532static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks)
1533{
1534 u32 mask = ntohs(input_masks->dst_port_mask);
1535 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1536 mask |= ntohs(input_masks->src_port_mask);
1537 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1538 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1539 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1540 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1541}
1542
1543/*
1544 * These two macros are meant to address the fact that we have registers
1545 * that are either all or in part big-endian. As a result on big-endian
1546 * systems we will end up byte swapping the value to little-endian before
1547 * it is byte swapped again and written to the hardware in the original
1548 * big-endian format.
1549 */
1550#define IXGBE_STORE_AS_BE32(_value) \
1551 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1552 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1553
1554#define IXGBE_WRITE_REG_BE32(a, reg, value) \
1555 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1556
1557#define IXGBE_STORE_AS_BE16(_value) \
1558 (((u16)(_value) >> 8) | ((u16)(_value) << 8))
1559
ffff4772
PWJ		 1560/**
1561 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1562 * @hw: pointer to hardware structure
1563 * @input: input bitstream
9a713e7c
PW		 1564 * @input_masks: bitwise masks for relevant fields
1565 * @soft_id: software index into the silicon hash tables for filter storage
ffff4772
PWJ		 1566 * @queue: queue index to direct traffic to
1567 *
1568 * Note that the caller to this function must lock before calling, since the
1569 * hardware writes must be protected from one another.
1570 **/
1571s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
905e4a41 1572 union ixgbe_atr_input *input,
9a713e7c
PW		 1573 struct ixgbe_atr_input_masks *input_masks,
1574 u16 soft_id, u8 queue)
ffff4772 1575{
ffff4772 1576 u32 fdirhash;
45b9f509
AD		 1577 u32 fdircmd;
1578 u32 fdirport, fdirtcpm;
1579 u32 fdirvlan;
1580 /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
1581 u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX |
1582 IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
ffff4772
PWJ		 1583
1584 /*
45b9f509 1585 * Check flow_type formatting, and bail out before we touch the hardware
ffff4772
PWJ		 1586 * if there's a configuration issue
1587 */
45b9f509
AD		 1588 switch (input->formatted.flow_type) {
1589 case IXGBE_ATR_FLOW_TYPE_IPV4:
1590 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
1591 fdirm |= IXGBE_FDIRM_L4P;
1592 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1593 if (input_masks->dst_port_mask || input_masks->src_port_mask) {
1594 hw_dbg(hw, " Error on src/dst port mask\n");
1595 return IXGBE_ERR_CONFIG;
1596 }
1597 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1598 case IXGBE_ATR_FLOW_TYPE_UDPV4:
ffff4772
PWJ		 1599 break;
1600 default:
45b9f509 1601 hw_dbg(hw, " Error on flow type input\n");
ffff4772
PWJ		 1602 return IXGBE_ERR_CONFIG;
1603 }
1604
9a713e7c 1605 /*
45b9f509
AD		 1606 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1607 * are zero, then assume a full mask for that field. Also assume that
1608 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1609 * cannot be masked out in this implementation.
9a713e7c
PW		 1610 *
1611 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1612 * point in time.
1613 */
45b9f509
AD		 1614
1615 /* Program FDIRM */
1616 switch (ntohs(input_masks->vlan_id_mask) & 0xEFFF) {
1617 case 0xEFFF:
1618 /* Unmask VLAN ID - bit 0 and fall through to unmask prio */
1619 fdirm &= ~IXGBE_FDIRM_VLANID;
1620 case 0xE000:
1621 /* Unmask VLAN prio - bit 1 */
1622 fdirm &= ~IXGBE_FDIRM_VLANP;
9a713e7c 1623 break;
45b9f509
AD		 1624 case 0x0FFF:
1625 /* Unmask VLAN ID - bit 0 */
1626 fdirm &= ~IXGBE_FDIRM_VLANID;
9a713e7c 1627 break;
45b9f509
AD		 1628 case 0x0000:
1629 /* do nothing, vlans already masked */
9a713e7c 1630 break;
45b9f509
AD		 1631 default:
1632 hw_dbg(hw, " Error on VLAN mask\n");
1633 return IXGBE_ERR_CONFIG;
9a713e7c
PW		 1634 }
1635
45b9f509
AD		 1636 if (input_masks->flex_mask & 0xFFFF) {
1637 if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) {
1638 hw_dbg(hw, " Error on flexible byte mask\n");
1639 return IXGBE_ERR_CONFIG;
1640 }
1641 /* Unmask Flex Bytes - bit 4 */
1642 fdirm &= ~IXGBE_FDIRM_FLEX;
1643 }
9a713e7c
PW		 1644
1645 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
9a713e7c 1646 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
ffff4772 1647
45b9f509
AD		 1648 /* store the TCP/UDP port masks, bit reversed from port layout */
1649 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks);
1650
1651 /* write both the same so that UDP and TCP use the same mask */
1652 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1653 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1654
1655 /* store source and destination IP masks (big-enian) */
1656 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1657 ~input_masks->src_ip_mask[0]);
1658 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1659 ~input_masks->dst_ip_mask[0]);
1660
1661 /* Apply masks to input data */
1662 input->formatted.vlan_id &= input_masks->vlan_id_mask;
1663 input->formatted.flex_bytes &= input_masks->flex_mask;
1664 input->formatted.src_port &= input_masks->src_port_mask;
1665 input->formatted.dst_port &= input_masks->dst_port_mask;
1666 input->formatted.src_ip[0] &= input_masks->src_ip_mask[0];
1667 input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0];
1668
1669 /* record vlan (little-endian) and flex_bytes(big-endian) */
1670 fdirvlan =
1671 IXGBE_STORE_AS_BE16(ntohs(input->formatted.flex_bytes));
1672 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1673 fdirvlan |= ntohs(input->formatted.vlan_id);
1674 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1675
1676 /* record source and destination port (little-endian)*/
1677 fdirport = ntohs(input->formatted.dst_port);
1678 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1679 fdirport |= ntohs(input->formatted.src_port);
1680 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1681
1682 /* record the first 32 bits of the destination address (big-endian) */
1683 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1684
1685 /* record the source address (big-endian) */
1686 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1687
1688 /* configure FDIRCMD register */
1689 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1690 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1691 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1692 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1693
1694 /* we only want the bucket hash so drop the upper 16 bits */
1695 fdirhash = ixgbe_atr_compute_hash_82599(input,
1696 IXGBE_ATR_BUCKET_HASH_KEY);
1697 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
ffff4772
PWJ		 1698
1699 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1700 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1701
1702 return 0;
1703}
45b9f509 1704
11afc1b1
PW		 1705/**
1706 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1707 * @hw: pointer to hardware structure
1708 * @reg: analog register to read
1709 * @val: read value
1710 *
1711 * Performs read operation to Omer analog register specified.
1712 **/
7b25cdba 1713static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
11afc1b1
PW		 1714{
1715 u32 core_ctl;
1716
1717 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1718 (reg << 8));
1719 IXGBE_WRITE_FLUSH(hw);
1720 udelay(10);
1721 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1722 *val = (u8)core_ctl;
1723
1724 return 0;
1725}
1726
1727/**
1728 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1729 * @hw: pointer to hardware structure
1730 * @reg: atlas register to write
1731 * @val: value to write
1732 *
1733 * Performs write operation to Omer analog register specified.
1734 **/
7b25cdba 1735static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
11afc1b1
PW		 1736{
1737 u32 core_ctl;
1738
1739 core_ctl = (reg << 8) | val;
1740 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1741 IXGBE_WRITE_FLUSH(hw);
1742 udelay(10);
1743
1744 return 0;
1745}
1746
1747/**
1748 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1749 * @hw: pointer to hardware structure
1750 *
7184b7cf
ET		 1751 * Starts the hardware using the generic start_hw function
1752 * and the generation start_hw function.
1753 * Then performs revision-specific operations, if any.
11afc1b1 1754 **/
7b25cdba 1755static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
11afc1b1 1756{
7184b7cf 1757 s32 ret_val = 0;
11afc1b1 1758
794caeb2 1759 ret_val = ixgbe_start_hw_generic(hw);
7184b7cf
ET		 1760 if (ret_val != 0)
1761 goto out;
11afc1b1 1762
7184b7cf
ET		 1763 ret_val = ixgbe_start_hw_gen2(hw);
1764 if (ret_val != 0)
1765 goto out;
11afc1b1 1766
50ac58ba
PWJ		 1767 /* We need to run link autotry after the driver loads */
1768 hw->mac.autotry_restart = true;
e09ad236 1769 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
50ac58ba 1770
794caeb2
PWJ		 1771 if (ret_val == 0)
1772 ret_val = ixgbe_verify_fw_version_82599(hw);
7184b7cf 1773out:
794caeb2 1774 return ret_val;
11afc1b1
PW		 1775}
1776
1777/**
1778 * ixgbe_identify_phy_82599 - Get physical layer module
1779 * @hw: pointer to hardware structure
1780 *
1781 * Determines the physical layer module found on the current adapter.
21cc5b4f
ET		 1782 * If PHY already detected, maintains current PHY type in hw struct,
1783 * otherwise executes the PHY detection routine.
11afc1b1 1784 **/
d6cd8e0e 1785static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1786{
1787 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
21cc5b4f
ET		 1788
1789 /* Detect PHY if not unknown - returns success if already detected. */
11afc1b1 1790 status = ixgbe_identify_phy_generic(hw);
21cc5b4f
ET		 1791 if (status != 0) {
1792 /* 82599 10GBASE-T requires an external PHY */
1793 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1794 goto out;
1795 else
1796 status = ixgbe_identify_sfp_module_generic(hw);
1797 }
1798
1799 /* Set PHY type none if no PHY detected */
1800 if (hw->phy.type == ixgbe_phy_unknown) {
1801 hw->phy.type = ixgbe_phy_none;
1802 status = 0;
1803 }
1804
1805 /* Return error if SFP module has been detected but is not supported */
1806 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1807 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1808
1809out:
11afc1b1
PW		 1810 return status;
1811}
1812
1813/**
1814 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1815 * @hw: pointer to hardware structure
1816 *
1817 * Determines physical layer capabilities of the current configuration.
1818 **/
7b25cdba 1819static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1820{
1821 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 1822 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1823 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1824 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1825 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1826 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1827 u16 ext_ability = 0;
1339b9e9 1828 u8 comp_codes_10g = 0;
cb836a97 1829 u8 comp_codes_1g = 0;
11afc1b1 1830
04193058
PWJ		 1831 hw->phy.ops.identify(hw);
1832
21cc5b4f
ET		 1833 switch (hw->phy.type) {
1834 case ixgbe_phy_tn:
1835 case ixgbe_phy_aq:
1836 case ixgbe_phy_cu_unknown:
6b73e10d 1837 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
21cc5b4f 1838 &ext_ability);
6b73e10d 1839 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 1840 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 1841 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 1842 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 1843 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 1844 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1845 goto out;
21cc5b4f
ET		 1846 default:
1847 break;
04193058
PWJ		 1848 }
1849
1850 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1851 case IXGBE_AUTOC_LMS_1G_AN:
1852 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1853 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1854 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1855 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1856 goto out;
1857 } else
1858 /* SFI mode so read SFP module */
1859 goto sfp_check;
11afc1b1 1860 break;
04193058
PWJ		 1861 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1862 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1863 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1864 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1865 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 1866 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1867 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 1868 goto out;
1869 break;
1870 case IXGBE_AUTOC_LMS_10G_SERIAL:
1871 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1872 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1873 goto out;
1874 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1875 goto sfp_check;
1876 break;
1877 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1878 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1879 if (autoc & IXGBE_AUTOC_KX_SUPP)
1880 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1881 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1882 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1883 if (autoc & IXGBE_AUTOC_KR_SUPP)
1884 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1885 goto out;
1886 break;
1887 default:
1888 goto out;
1889 break;
1890 }
11afc1b1 1891
04193058
PWJ		 1892sfp_check:
1893 /* SFP check must be done last since DA modules are sometimes used to
1894 * test KR mode - we need to id KR mode correctly before SFP module.
1895 * Call identify_sfp because the pluggable module may have changed */
1896 hw->phy.ops.identify_sfp(hw);
1897 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1898 goto out;
1899
1900 switch (hw->phy.type) {
ea0a04df
DS		 1901 case ixgbe_phy_sfp_passive_tyco:
1902 case ixgbe_phy_sfp_passive_unknown:
04193058
PWJ		 1903 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1904 break;
ea0a04df
DS		 1905 case ixgbe_phy_sfp_ftl_active:
1906 case ixgbe_phy_sfp_active_unknown:
1907 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1908 break;
04193058
PWJ		 1909 case ixgbe_phy_sfp_avago:
1910 case ixgbe_phy_sfp_ftl:
1911 case ixgbe_phy_sfp_intel:
1912 case ixgbe_phy_sfp_unknown:
cb836a97
DS		 1913 hw->phy.ops.read_i2c_eeprom(hw,
1914 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
04193058
PWJ		 1915 hw->phy.ops.read_i2c_eeprom(hw,
1916 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1917 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 1918 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 1919 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 1920 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
cb836a97
DS		 1921 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1922 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
11afc1b1
PW		 1923 break;
1924 default:
11afc1b1
PW		 1925 break;
1926 }
1927
04193058 1928out:
11afc1b1
PW		 1929 return physical_layer;
1930}
1931
1932/**
1933 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1934 * @hw: pointer to hardware structure
1935 * @regval: register value to write to RXCTRL
1936 *
1937 * Enables the Rx DMA unit for 82599
1938 **/
7b25cdba 1939static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
11afc1b1
PW		 1940{
1941#define IXGBE_MAX_SECRX_POLL 30
1942 int i;
1943 int secrxreg;
1944
1945 /*
1946 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1947 * If traffic is incoming before we enable the Rx unit, it could hang
1948 * the Rx DMA unit. Therefore, make sure the security engine is
1949 * completely disabled prior to enabling the Rx unit.
1950 */
1951 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1952 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1953 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1954 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1955 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1956 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1957 break;
1958 else
8c7bea32 1959 /* Use interrupt-safe sleep just in case */
11afc1b1
PW		 1960 udelay(10);
1961 }
1962
1963 /* For informational purposes only */
1964 if (i >= IXGBE_MAX_SECRX_POLL)
1965 hw_dbg(hw, "Rx unit being enabled before security "
1966 "path fully disabled. Continuing with init.\n");
1967
1968 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1969 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1970 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1971 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1972 IXGBE_WRITE_FLUSH(hw);
1973
1974 return 0;
1975}
1976
794caeb2
PWJ		 1977/**
1978 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1979 * @hw: pointer to hardware structure
1980 *
1981 * Verifies that installed the firmware version is 0.6 or higher
1982 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1983 *
1984 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1985 * if the FW version is not supported.
1986 **/
1987static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
1988{
1989 s32 status = IXGBE_ERR_EEPROM_VERSION;
1990 u16 fw_offset, fw_ptp_cfg_offset;
1991 u16 fw_version = 0;
1992
1993 /* firmware check is only necessary for SFI devices */
1994 if (hw->phy.media_type != ixgbe_media_type_fiber) {
1995 status = 0;
1996 goto fw_version_out;
1997 }
1998
1999 /* get the offset to the Firmware Module block */
2000 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2001
2002 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2003 goto fw_version_out;
2004
2005 /* get the offset to the Pass Through Patch Configuration block */
2006 hw->eeprom.ops.read(hw, (fw_offset +
2007 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2008 &fw_ptp_cfg_offset);
2009
2010 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2011 goto fw_version_out;
2012
2013 /* get the firmware version */
2014 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2015 IXGBE_FW_PATCH_VERSION_4),
2016 &fw_version);
2017
2018 if (fw_version > 0x5)
2019 status = 0;
2020
2021fw_version_out:
2022 return status;
2023}
2024
0fa6d832
ET		 2025/**
2026 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2027 * @hw: pointer to hardware structure
2028 *
2029 * Returns true if the LESM FW module is present and enabled. Otherwise
2030 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2031 **/
2032static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2033{
2034 bool lesm_enabled = false;
2035 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2036 s32 status;
2037
2038 /* get the offset to the Firmware Module block */
2039 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2040
2041 if ((status != 0) ||
2042 (fw_offset == 0) || (fw_offset == 0xFFFF))
2043 goto out;
2044
2045 /* get the offset to the LESM Parameters block */
2046 status = hw->eeprom.ops.read(hw, (fw_offset +
2047 IXGBE_FW_LESM_PARAMETERS_PTR),
2048 &fw_lesm_param_offset);
2049
2050 if ((status != 0) ||
2051 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2052 goto out;
2053
2054 /* get the lesm state word */
2055 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2056 IXGBE_FW_LESM_STATE_1),
2057 &fw_lesm_state);
2058
2059 if ((status == 0) &&
2060 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2061 lesm_enabled = true;
2062
2063out:
2064 return lesm_enabled;
2065}
2066
0665b09f
ET		 2067/**
2068 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2069 * fastest available method
2070 *
2071 * @hw: pointer to hardware structure
2072 * @offset: offset of word in the EEPROM to read
2073 * @data: word read from the EEPROM
2074 *
2075 * Reads a 16 bit word from the EEPROM
2076 **/
2077static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2078 u16 offset, u16 *data)
2079{
2080 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2081 s32 ret_val = IXGBE_ERR_CONFIG;
2082
2083 /*
2084 * If EEPROM is detected and can be addressed using 14 bits,
2085 * use EERD otherwise use bit bang
2086 */
2087 if ((eeprom->type == ixgbe_eeprom_spi) &&
2088 (offset <= IXGBE_EERD_MAX_ADDR))
2089 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2090 else
2091 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2092
2093 return ret_val;
2094}
2095
11afc1b1
PW		 2096static struct ixgbe_mac_operations mac_ops_82599 = {
2097 .init_hw = &ixgbe_init_hw_generic,
2098 .reset_hw = &ixgbe_reset_hw_82599,
2099 .start_hw = &ixgbe_start_hw_82599,
2100 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2101 .get_media_type = &ixgbe_get_media_type_82599,
2102 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2103 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2104 .get_mac_addr = &ixgbe_get_mac_addr_generic,
21ce849b 2105 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
b776d104 2106 .get_device_caps = &ixgbe_get_device_caps_generic,
a391f1d5 2107 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
11afc1b1
PW		 2108 .stop_adapter = &ixgbe_stop_adapter_generic,
2109 .get_bus_info = &ixgbe_get_bus_info_generic,
2110 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2111 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2112 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2113 .setup_link = &ixgbe_setup_mac_link_82599,
21ce849b 2114 .check_link = &ixgbe_check_mac_link_generic,
11afc1b1
PW		 2115 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2116 .led_on = &ixgbe_led_on_generic,
2117 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 2118 .blink_led_start = &ixgbe_blink_led_start_generic,
2119 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 2120 .set_rar = &ixgbe_set_rar_generic,
2121 .clear_rar = &ixgbe_clear_rar_generic,
21ce849b
MC		 2122 .set_vmdq = &ixgbe_set_vmdq_generic,
2123 .clear_vmdq = &ixgbe_clear_vmdq_generic,
11afc1b1 2124 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
11afc1b1
PW		 2125 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2126 .enable_mc = &ixgbe_enable_mc_generic,
2127 .disable_mc = &ixgbe_disable_mc_generic,
21ce849b
MC		 2128 .clear_vfta = &ixgbe_clear_vfta_generic,
2129 .set_vfta = &ixgbe_set_vfta_generic,
2130 .fc_enable = &ixgbe_fc_enable_generic,
2131 .init_uta_tables = &ixgbe_init_uta_tables_generic,
11afc1b1 2132 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
a985b6c3
GR		 2133 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2134 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
5e655105
DS		 2135 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2136 .release_swfw_sync = &ixgbe_release_swfw_sync,
2137
11afc1b1
PW		 2138};
2139
2140static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
037c6d0a 2141 .init_params = &ixgbe_init_eeprom_params_generic,
0665b09f 2142 .read = &ixgbe_read_eeprom_82599,
037c6d0a
ET		 2143 .write = &ixgbe_write_eeprom_generic,
2144 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2145 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2146 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
11afc1b1
PW		 2147};
2148
2149static struct ixgbe_phy_operations phy_ops_82599 = {
037c6d0a
ET		 2150 .identify = &ixgbe_identify_phy_82599,
2151 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2152 .init = &ixgbe_init_phy_ops_82599,
2153 .reset = &ixgbe_reset_phy_generic,
2154 .read_reg = &ixgbe_read_phy_reg_generic,
2155 .write_reg = &ixgbe_write_phy_reg_generic,
2156 .setup_link = &ixgbe_setup_phy_link_generic,
2157 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2158 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2159 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2160 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2161 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2162 .check_overtemp = &ixgbe_tn_check_overtemp,
11afc1b1
PW		 2163};
2164
2165struct ixgbe_info ixgbe_82599_info = {
2166 .mac = ixgbe_mac_82599EB,
2167 .get_invariants = &ixgbe_get_invariants_82599,
2168 .mac_ops = &mac_ops_82599,
2169 .eeprom_ops = &eeprom_ops_82599,
2170 .phy_ops = &phy_ops_82599,
a391f1d5 2171 .mbx_ops = &mbx_ops_generic,
11afc1b1 2172};
Linux kernel - Deliverables
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