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ixgbe: Properly disable packet split per-ring when globally disabled
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
34
35#define IXGBE_82599_MAX_TX_QUEUES 128
36#define IXGBE_82599_MAX_RX_QUEUES 128
37#define IXGBE_82599_RAR_ENTRIES 128
38#define IXGBE_82599_MC_TBL_SIZE 128
39#define IXGBE_82599_VFT_TBL_SIZE 128
40
8620a103
MC		 41s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
42 ixgbe_link_speed speed,
43 bool autoneg,
44 bool autoneg_wait_to_complete);
45s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
46 bool autoneg_wait_to_complete);
47s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
48 ixgbe_link_speed speed,
49 bool autoneg,
50 bool autoneg_wait_to_complete);
11afc1b1
PW		 51static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
52 ixgbe_link_speed *speed,
53 bool *autoneg);
8620a103
MC		 54static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
55 ixgbe_link_speed speed,
56 bool autoneg,
57 bool autoneg_wait_to_complete);
794caeb2 58static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
11afc1b1 59
7b25cdba 60static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 61{
62 struct ixgbe_mac_info *mac = &hw->mac;
63 if (hw->phy.multispeed_fiber) {
64 /* Set up dual speed SFP+ support */
8620a103 65 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
11afc1b1 66 } else {
8620a103 67 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
11afc1b1
PW		 68 }
69}
70
7b25cdba 71static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 72{
73 s32 ret_val = 0;
74 u16 list_offset, data_offset, data_value;
75
76 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
77 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 78
79 hw->phy.ops.reset = NULL;
80
11afc1b1
PW		 81 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
82 &data_offset);
83
84 if (ret_val != 0)
85 goto setup_sfp_out;
86
aa5aec88
PWJ		 87 /* PHY config will finish before releasing the semaphore */
88 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
89 if (ret_val != 0) {
90 ret_val = IXGBE_ERR_SWFW_SYNC;
91 goto setup_sfp_out;
92 }
93
11afc1b1
PW		 94 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
95 while (data_value != 0xffff) {
96 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
97 IXGBE_WRITE_FLUSH(hw);
98 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
99 }
1479ad4f
PWJ		 100 /* Now restart DSP by setting Restart_AN */
101 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
102 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
aa5aec88
PWJ		 103
104 /* Release the semaphore */
105 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
106 /* Delay obtaining semaphore again to allow FW access */
107 msleep(hw->eeprom.semaphore_delay);
11afc1b1
PW		 108 }
109
110setup_sfp_out:
111 return ret_val;
112}
113
114/**
115 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
116 * @hw: pointer to hardware structure
117 *
118 * Read PCIe configuration space, and get the MSI-X vector count from
119 * the capabilities table.
120 **/
7b25cdba 121static u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 122{
123 struct ixgbe_adapter *adapter = hw->back;
124 u16 msix_count;
125 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
126 &msix_count);
127 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
128
129 /* MSI-X count is zero-based in HW, so increment to give proper value */
130 msix_count++;
131
132 return msix_count;
133}
134
135static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
136{
137 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 138
04f165ef 139 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 140
04f165ef
PW		 141 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
142 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
143 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
144 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
145 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
146 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
11afc1b1 147
04f165ef
PW		 148 return 0;
149}
11afc1b1 150
04f165ef
PW		 151/**
152 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
153 * @hw: pointer to hardware structure
154 *
155 * Initialize any function pointers that were not able to be
156 * set during get_invariants because the PHY/SFP type was
157 * not known. Perform the SFP init if necessary.
158 *
159 **/
7b25cdba 160static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
04f165ef
PW		 161{
162 struct ixgbe_mac_info *mac = &hw->mac;
163 struct ixgbe_phy_info *phy = &hw->phy;
164 s32 ret_val = 0;
11afc1b1 165
04f165ef
PW		 166 /* Identify the PHY or SFP module */
167 ret_val = phy->ops.identify(hw);
168
169 /* Setup function pointers based on detected SFP module and speeds */
170 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 171
172 /* If copper media, overwrite with copper function pointers */
173 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
174 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
11afc1b1
PW		 175 mac->ops.get_link_capabilities =
176 &ixgbe_get_copper_link_capabilities_82599;
177 }
178
04f165ef 179 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 180 switch (hw->phy.type) {
181 case ixgbe_phy_tn:
182 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
183 phy->ops.get_firmware_version =
04f165ef 184 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 185 break;
186 default:
187 break;
188 }
189
11afc1b1
PW		 190 return ret_val;
191}
192
193/**
194 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
195 * @hw: pointer to hardware structure
196 * @speed: pointer to link speed
197 * @negotiation: true when autoneg or autotry is enabled
198 *
199 * Determines the link capabilities by reading the AUTOC register.
200 **/
7b25cdba
DS		 201static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
202 ixgbe_link_speed *speed,
203 bool *negotiation)
11afc1b1
PW		 204{
205 s32 status = 0;
1eb99d5a 206 u32 autoc = 0;
11afc1b1 207
1eb99d5a
PW		 208 /*
209 * Determine link capabilities based on the stored value of AUTOC,
210 * which represents EEPROM defaults. If AUTOC value has not been
211 * stored, use the current register value.
212 */
213 if (hw->mac.orig_link_settings_stored)
214 autoc = hw->mac.orig_autoc;
215 else
216 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
217
218 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 219 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
220 *speed = IXGBE_LINK_SPEED_1GB_FULL;
221 *negotiation = false;
222 break;
223
224 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
225 *speed = IXGBE_LINK_SPEED_10GB_FULL;
226 *negotiation = false;
227 break;
228
229 case IXGBE_AUTOC_LMS_1G_AN:
230 *speed = IXGBE_LINK_SPEED_1GB_FULL;
231 *negotiation = true;
232 break;
233
234 case IXGBE_AUTOC_LMS_10G_SERIAL:
235 *speed = IXGBE_LINK_SPEED_10GB_FULL;
236 *negotiation = false;
237 break;
238
239 case IXGBE_AUTOC_LMS_KX4_KX_KR:
240 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
241 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 242 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 243 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 244 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 245 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 246 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 247 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
248 *negotiation = true;
249 break;
250
251 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
252 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 253 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 254 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 255 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 256 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 257 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 258 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
259 *negotiation = true;
260 break;
261
262 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
263 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
264 *negotiation = false;
265 break;
266
267 default:
268 status = IXGBE_ERR_LINK_SETUP;
269 goto out;
270 break;
271 }
272
273 if (hw->phy.multispeed_fiber) {
274 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
275 IXGBE_LINK_SPEED_1GB_FULL;
276 *negotiation = true;
277 }
278
279out:
280 return status;
281}
282
283/**
284 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
285 * @hw: pointer to hardware structure
286 * @speed: pointer to link speed
287 * @autoneg: boolean auto-negotiation value
288 *
289 * Determines the link capabilities by reading the AUTOC register.
290 **/
291static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
292 ixgbe_link_speed *speed,
293 bool *autoneg)
294{
295 s32 status = IXGBE_ERR_LINK_SETUP;
296 u16 speed_ability;
297
298 *speed = 0;
299 *autoneg = true;
300
6b73e10d 301 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
11afc1b1
PW		 302 &speed_ability);
303
304 if (status == 0) {
6b73e10d 305 if (speed_ability & MDIO_SPEED_10G)
11afc1b1 306 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
6b73e10d 307 if (speed_ability & MDIO_PMA_SPEED_1000)
11afc1b1
PW		 308 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
309 }
310
311 return status;
312}
313
314/**
315 * ixgbe_get_media_type_82599 - Get media type
316 * @hw: pointer to hardware structure
317 *
318 * Returns the media type (fiber, copper, backplane)
319 **/
7b25cdba 320static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 321{
322 enum ixgbe_media_type media_type;
323
324 /* Detect if there is a copper PHY attached. */
325 if (hw->phy.type == ixgbe_phy_cu_unknown ||
326 hw->phy.type == ixgbe_phy_tn) {
327 media_type = ixgbe_media_type_copper;
328 goto out;
329 }
330
331 switch (hw->device_id) {
11afc1b1 332 case IXGBE_DEV_ID_82599_KX4:
1fcf03e6 333 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 334 /* Default device ID is mezzanine card KX/KX4 */
335 media_type = ixgbe_media_type_backplane;
336 break;
337 case IXGBE_DEV_ID_82599_SFP:
338 media_type = ixgbe_media_type_fiber;
339 break;
340 default:
341 media_type = ixgbe_media_type_unknown;
342 break;
343 }
344out:
345 return media_type;
346}
347
348/**
8620a103 349 * ixgbe_start_mac_link_82599 - Setup MAC link settings
11afc1b1 350 * @hw: pointer to hardware structure
8620a103 351 * @autoneg_wait_to_complete: true when waiting for completion is needed
11afc1b1
PW		 352 *
353 * Configures link settings based on values in the ixgbe_hw struct.
354 * Restarts the link. Performs autonegotiation if needed.
355 **/
8620a103
MC		 356s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
357 bool autoneg_wait_to_complete)
11afc1b1
PW		 358{
359 u32 autoc_reg;
360 u32 links_reg;
361 u32 i;
362 s32 status = 0;
363
364 /* Restart link */
365 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
366 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
367 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
368
369 /* Only poll for autoneg to complete if specified to do so */
8620a103 370 if (autoneg_wait_to_complete) {
11afc1b1
PW		 371 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
372 IXGBE_AUTOC_LMS_KX4_KX_KR ||
373 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
374 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
375 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
376 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
377 links_reg = 0; /* Just in case Autoneg time = 0 */
378 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
379 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
380 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
381 break;
382 msleep(100);
383 }
384 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
385 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
386 hw_dbg(hw, "Autoneg did not complete.\n");
387 }
388 }
389 }
390
11afc1b1
PW		 391 /* Add delay to filter out noises during initial link setup */
392 msleep(50);
393
394 return status;
395}
396
397/**
8620a103 398 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
11afc1b1
PW		 399 * @hw: pointer to hardware structure
400 * @speed: new link speed
401 * @autoneg: true if autonegotiation enabled
402 * @autoneg_wait_to_complete: true when waiting for completion is needed
403 *
404 * Set the link speed in the AUTOC register and restarts link.
405 **/
8620a103
MC		 406s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
407 ixgbe_link_speed speed,
408 bool autoneg,
409 bool autoneg_wait_to_complete)
11afc1b1
PW		 410{
411 s32 status = 0;
412 ixgbe_link_speed phy_link_speed;
413 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
414 u32 speedcnt = 0;
415 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
416 bool link_up = false;
417 bool negotiation;
50ac58ba 418 int i;
11afc1b1
PW		 419
420 /* Mask off requested but non-supported speeds */
421 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
422 speed &= phy_link_speed;
423
50ac58ba
PWJ		 424 /*
425 * When the driver changes the link speeds that it can support,
426 * it sets autotry_restart to true to indicate that we need to
427 * initiate a new autotry session with the link partner. To do
428 * so, we set the speed then disable and re-enable the tx laser, to
429 * alert the link partner that it also needs to restart autotry on its
430 * end. This is consistent with true clause 37 autoneg, which also
431 * involves a loss of signal.
432 */
433
11afc1b1
PW		 434 /*
435 * Try each speed one by one, highest priority first. We do this in
436 * software because 10gb fiber doesn't support speed autonegotiation.
437 */
438 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
439 speedcnt++;
440 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
441
50ac58ba
PWJ		 442 /* If we already have link at this speed, just jump out */
443 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
444
445 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
446 goto out;
447
448 /* Set the module link speed */
11afc1b1
PW		 449 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
450 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
451
50ac58ba
PWJ		 452 /* Allow module to change analog characteristics (1G->10G) */
453 msleep(40);
11afc1b1 454
8620a103
MC		 455 status = ixgbe_setup_mac_link_82599(hw,
456 IXGBE_LINK_SPEED_10GB_FULL,
457 autoneg,
458 autoneg_wait_to_complete);
50ac58ba 459 if (status != 0)
c3c74327 460 return status;
50ac58ba
PWJ		 461
462 /* Flap the tx laser if it has not already been done */
463 if (hw->mac.autotry_restart) {
464 /* Disable tx laser; allow 100us to go dark per spec */
465 esdp_reg |= IXGBE_ESDP_SDP3;
466 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
467 udelay(100);
468
469 /* Enable tx laser; allow 2ms to light up per spec */
470 esdp_reg &= ~IXGBE_ESDP_SDP3;
471 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
472 msleep(2);
473
474 hw->mac.autotry_restart = false;
475 }
476
477 /* The controller may take up to 500ms at 10g to acquire link */
478 for (i = 0; i < 5; i++) {
479 /* Wait for the link partner to also set speed */
480 msleep(100);
481
482 /* If we have link, just jump out */
483 hw->mac.ops.check_link(hw, &phy_link_speed,
484 &link_up, false);
485 if (link_up)
486 goto out;
487 }
11afc1b1
PW		 488 }
489
490 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
491 speedcnt++;
492 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
493 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
494
50ac58ba
PWJ		 495 /* If we already have link at this speed, just jump out */
496 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
497
498 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
499 goto out;
500
501 /* Set the module link speed */
11afc1b1
PW		 502 esdp_reg &= ~IXGBE_ESDP_SDP5;
503 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
504 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
505
50ac58ba
PWJ		 506 /* Allow module to change analog characteristics (10G->1G) */
507 msleep(40);
11afc1b1 508
8620a103 509 status = ixgbe_setup_mac_link_82599(hw,
50ac58ba
PWJ		 510 IXGBE_LINK_SPEED_1GB_FULL,
511 autoneg,
512 autoneg_wait_to_complete);
513 if (status != 0)
c3c74327 514 return status;
50ac58ba
PWJ		 515
516 /* Flap the tx laser if it has not already been done */
517 if (hw->mac.autotry_restart) {
518 /* Disable tx laser; allow 100us to go dark per spec */
519 esdp_reg |= IXGBE_ESDP_SDP3;
520 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
521 udelay(100);
522
523 /* Enable tx laser; allow 2ms to light up per spec */
524 esdp_reg &= ~IXGBE_ESDP_SDP3;
525 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
526 msleep(2);
527
528 hw->mac.autotry_restart = false;
529 }
530
531 /* Wait for the link partner to also set speed */
532 msleep(100);
11afc1b1
PW		 533
534 /* If we have link, just jump out */
535 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
536 if (link_up)
537 goto out;
538 }
539
540 /*
541 * We didn't get link. Configure back to the highest speed we tried,
542 * (if there was more than one). We call ourselves back with just the
543 * single highest speed that the user requested.
544 */
545 if (speedcnt > 1)
8620a103
MC		 546 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
547 highest_link_speed,
548 autoneg,
549 autoneg_wait_to_complete);
11afc1b1
PW		 550
551out:
c3c74327
MC		 552 /* Set autoneg_advertised value based on input link speed */
553 hw->phy.autoneg_advertised = 0;
554
555 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
556 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
557
558 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
559 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
560
11afc1b1
PW		 561 return status;
562}
563
564/**
565 * ixgbe_check_mac_link_82599 - Determine link and speed status
566 * @hw: pointer to hardware structure
567 * @speed: pointer to link speed
568 * @link_up: true when link is up
569 * @link_up_wait_to_complete: bool used to wait for link up or not
570 *
571 * Reads the links register to determine if link is up and the current speed
572 **/
7b25cdba
DS		 573static s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
574 ixgbe_link_speed *speed,
575 bool *link_up,
576 bool link_up_wait_to_complete)
11afc1b1
PW		 577{
578 u32 links_reg;
579 u32 i;
580
581 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
582 if (link_up_wait_to_complete) {
583 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
584 if (links_reg & IXGBE_LINKS_UP) {
585 *link_up = true;
586 break;
587 } else {
588 *link_up = false;
589 }
590 msleep(100);
591 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
592 }
593 } else {
594 if (links_reg & IXGBE_LINKS_UP)
595 *link_up = true;
596 else
597 *link_up = false;
598 }
599
600 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
601 IXGBE_LINKS_SPEED_10G_82599)
602 *speed = IXGBE_LINK_SPEED_10GB_FULL;
603 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
604 IXGBE_LINKS_SPEED_1G_82599)
605 *speed = IXGBE_LINK_SPEED_1GB_FULL;
606 else
607 *speed = IXGBE_LINK_SPEED_100_FULL;
608
620fa036
MC		 609 /* if link is down, zero out the current_mode */
610 if (*link_up == false) {
611 hw->fc.current_mode = ixgbe_fc_none;
612 hw->fc.fc_was_autonegged = false;
613 }
11afc1b1
PW		 614
615 return 0;
616}
617
618/**
8620a103 619 * ixgbe_setup_mac_link_82599 - Set MAC link speed
11afc1b1
PW		 620 * @hw: pointer to hardware structure
621 * @speed: new link speed
622 * @autoneg: true if autonegotiation enabled
623 * @autoneg_wait_to_complete: true when waiting for completion is needed
624 *
625 * Set the link speed in the AUTOC register and restarts link.
626 **/
8620a103
MC		 627s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
628 ixgbe_link_speed speed, bool autoneg,
629 bool autoneg_wait_to_complete)
11afc1b1
PW		 630{
631 s32 status = 0;
632 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
633 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
50ac58ba 634 u32 start_autoc = autoc;
1eb99d5a 635 u32 orig_autoc = 0;
11afc1b1
PW		 636 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
637 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
638 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
639 u32 links_reg;
640 u32 i;
641 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
642
643 /* Check to see if speed passed in is supported. */
644 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
645 speed &= link_capabilities;
646
50ac58ba
PWJ		 647 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
648 status = IXGBE_ERR_LINK_SETUP;
649 goto out;
650 }
651
1eb99d5a
PW		 652 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
653 if (hw->mac.orig_link_settings_stored)
654 orig_autoc = hw->mac.orig_autoc;
655 else
656 orig_autoc = autoc;
657
658
50ac58ba
PWJ		 659 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
660 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
661 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
11afc1b1
PW		 662 /* Set KX4/KX/KR support according to speed requested */
663 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
664 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 665 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 666 autoc |= IXGBE_AUTOC_KX4_SUPP;
1eb99d5a 667 if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1
PW		 668 autoc |= IXGBE_AUTOC_KR_SUPP;
669 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
670 autoc |= IXGBE_AUTOC_KX_SUPP;
671 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
672 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
673 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
674 /* Switch from 1G SFI to 10G SFI if requested */
675 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
676 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
677 autoc &= ~IXGBE_AUTOC_LMS_MASK;
678 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
679 }
680 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
681 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
682 /* Switch from 10G SFI to 1G SFI if requested */
683 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
684 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
685 autoc &= ~IXGBE_AUTOC_LMS_MASK;
686 if (autoneg)
687 autoc |= IXGBE_AUTOC_LMS_1G_AN;
688 else
689 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
690 }
691 }
692
50ac58ba 693 if (autoc != start_autoc) {
11afc1b1
PW		 694 /* Restart link */
695 autoc |= IXGBE_AUTOC_AN_RESTART;
696 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
697
698 /* Only poll for autoneg to complete if specified to do so */
699 if (autoneg_wait_to_complete) {
700 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
701 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
702 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
703 links_reg = 0; /*Just in case Autoneg time=0*/
704 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
705 links_reg =
706 IXGBE_READ_REG(hw, IXGBE_LINKS);
707 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
708 break;
709 msleep(100);
710 }
711 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
712 status =
713 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
714 hw_dbg(hw, "Autoneg did not "
715 "complete.\n");
716 }
717 }
718 }
719
11afc1b1
PW		 720 /* Add delay to filter out noises during initial link setup */
721 msleep(50);
722 }
723
50ac58ba 724out:
11afc1b1
PW		 725 return status;
726}
727
728/**
8620a103 729 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
11afc1b1
PW		 730 * @hw: pointer to hardware structure
731 * @speed: new link speed
732 * @autoneg: true if autonegotiation enabled
733 * @autoneg_wait_to_complete: true if waiting is needed to complete
734 *
735 * Restarts link on PHY and MAC based on settings passed in.
736 **/
8620a103
MC		 737static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
738 ixgbe_link_speed speed,
739 bool autoneg,
740 bool autoneg_wait_to_complete)
11afc1b1
PW		 741{
742 s32 status;
743
744 /* Setup the PHY according to input speed */
745 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
746 autoneg_wait_to_complete);
747 /* Set up MAC */
8620a103 748 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
11afc1b1
PW		 749
750 return status;
751}
752
753/**
754 * ixgbe_reset_hw_82599 - Perform hardware reset
755 * @hw: pointer to hardware structure
756 *
757 * Resets the hardware by resetting the transmit and receive units, masks
758 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
759 * reset.
760 **/
7b25cdba 761static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 762{
763 s32 status = 0;
764 u32 ctrl, ctrl_ext;
765 u32 i;
766 u32 autoc;
767 u32 autoc2;
768
769 /* Call adapter stop to disable tx/rx and clear interrupts */
770 hw->mac.ops.stop_adapter(hw);
771
553b4497 772 /* PHY ops must be identified and initialized prior to reset */
04f165ef 773
553b4497
PW		 774 /* Init PHY and function pointers, perform SFP setup */
775 status = hw->phy.ops.init(hw);
04f165ef 776
553b4497
PW		 777 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
778 goto reset_hw_out;
04f165ef 779
553b4497
PW		 780 /* Setup SFP module if there is one present. */
781 if (hw->phy.sfp_setup_needed) {
782 status = hw->mac.ops.setup_sfp(hw);
783 hw->phy.sfp_setup_needed = false;
04f165ef 784 }
11afc1b1 785
553b4497
PW		 786 /* Reset PHY */
787 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
788 hw->phy.ops.reset(hw);
789
11afc1b1
PW		 790 /*
791 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
792 * access and verify no pending requests before reset
793 */
04f165ef
PW		 794 status = ixgbe_disable_pcie_master(hw);
795 if (status != 0) {
11afc1b1
PW		 796 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
797 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
798 }
799
800 /*
801 * Issue global reset to the MAC. This needs to be a SW reset.
802 * If link reset is used, it might reset the MAC when mng is using it
803 */
804 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
805 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
806 IXGBE_WRITE_FLUSH(hw);
807
808 /* Poll for reset bit to self-clear indicating reset is complete */
809 for (i = 0; i < 10; i++) {
810 udelay(1);
811 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
812 if (!(ctrl & IXGBE_CTRL_RST))
813 break;
814 }
815 if (ctrl & IXGBE_CTRL_RST) {
816 status = IXGBE_ERR_RESET_FAILED;
817 hw_dbg(hw, "Reset polling failed to complete.\n");
818 }
819 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
820 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
821 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
822 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
823
824 msleep(50);
825
826
827
828 /*
829 * Store the original AUTOC/AUTOC2 values if they have not been
830 * stored off yet. Otherwise restore the stored original
831 * values since the reset operation sets back to defaults.
832 */
833 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
834 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
835 if (hw->mac.orig_link_settings_stored == false) {
836 hw->mac.orig_autoc = autoc;
837 hw->mac.orig_autoc2 = autoc2;
838 hw->mac.orig_link_settings_stored = true;
4df10466 839 } else {
11afc1b1
PW		 840 if (autoc != hw->mac.orig_autoc)
841 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
842 IXGBE_AUTOC_AN_RESTART));
843
844 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
845 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
846 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
847 autoc2 |= (hw->mac.orig_autoc2 &
848 IXGBE_AUTOC2_UPPER_MASK);
849 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
850 }
851 }
852
aca6bee7
WJP		 853 /*
854 * Store MAC address from RAR0, clear receive address registers, and
855 * clear the multicast table. Also reset num_rar_entries to 128,
856 * since we modify this value when programming the SAN MAC address.
857 */
858 hw->mac.num_rar_entries = 128;
859 hw->mac.ops.init_rx_addrs(hw);
860
11afc1b1
PW		 861 /* Store the permanent mac address */
862 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
863
0365e6e4
PW		 864 /* Store the permanent SAN mac address */
865 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
866
aca6bee7
WJP		 867 /* Add the SAN MAC address to the RAR only if it's a valid address */
868 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
869 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
870 hw->mac.san_addr, 0, IXGBE_RAH_AV);
871
872 /* Reserve the last RAR for the SAN MAC address */
873 hw->mac.num_rar_entries--;
874 }
875
04f165ef 876reset_hw_out:
11afc1b1
PW		 877 return status;
878}
879
880/**
881 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
882 * @hw: pointer to hardware struct
883 * @rar: receive address register index to disassociate
884 * @vmdq: VMDq pool index to remove from the rar
885 **/
7b25cdba 886static s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
11afc1b1
PW		 887{
888 u32 mpsar_lo, mpsar_hi;
889 u32 rar_entries = hw->mac.num_rar_entries;
890
891 if (rar < rar_entries) {
892 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
893 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
894
895 if (!mpsar_lo && !mpsar_hi)
896 goto done;
897
898 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
899 if (mpsar_lo) {
900 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
901 mpsar_lo = 0;
902 }
903 if (mpsar_hi) {
904 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
905 mpsar_hi = 0;
906 }
907 } else if (vmdq < 32) {
908 mpsar_lo &= ~(1 << vmdq);
909 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
910 } else {
911 mpsar_hi &= ~(1 << (vmdq - 32));
912 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
913 }
914
915 /* was that the last pool using this rar? */
916 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
917 hw->mac.ops.clear_rar(hw, rar);
918 } else {
919 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
920 }
921
922done:
923 return 0;
924}
925
926/**
927 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
928 * @hw: pointer to hardware struct
929 * @rar: receive address register index to associate with a VMDq index
930 * @vmdq: VMDq pool index
931 **/
7b25cdba 932static s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
11afc1b1
PW		 933{
934 u32 mpsar;
935 u32 rar_entries = hw->mac.num_rar_entries;
936
937 if (rar < rar_entries) {
938 if (vmdq < 32) {
939 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
940 mpsar |= 1 << vmdq;
941 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
942 } else {
943 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
944 mpsar |= 1 << (vmdq - 32);
945 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
946 }
947 } else {
948 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
949 }
950 return 0;
951}
952
953/**
954 * ixgbe_set_vfta_82599 - Set VLAN filter table
955 * @hw: pointer to hardware structure
956 * @vlan: VLAN id to write to VLAN filter
957 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
958 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
959 *
960 * Turn on/off specified VLAN in the VLAN filter table.
961 **/
7b25cdba
DS		 962static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
963 bool vlan_on)
11afc1b1
PW		 964{
965 u32 regindex;
966 u32 bitindex;
967 u32 bits;
968 u32 first_empty_slot;
969
970 if (vlan > 4095)
971 return IXGBE_ERR_PARAM;
972
973 /*
974 * this is a 2 part operation - first the VFTA, then the
975 * VLVF and VLVFB if vind is set
976 */
977
978 /* Part 1
979 * The VFTA is a bitstring made up of 128 32-bit registers
980 * that enable the particular VLAN id, much like the MTA:
981 * bits[11-5]: which register
982 * bits[4-0]: which bit in the register
983 */
984 regindex = (vlan >> 5) & 0x7F;
985 bitindex = vlan & 0x1F;
986 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
987 if (vlan_on)
988 bits |= (1 << bitindex);
989 else
990 bits &= ~(1 << bitindex);
991 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
992
993
994 /* Part 2
995 * If the vind is set
996 * Either vlan_on
997 * make sure the vlan is in VLVF
998 * set the vind bit in the matching VLVFB
999 * Or !vlan_on
1000 * clear the pool bit and possibly the vind
1001 */
1002 if (vind) {
1003 /* find the vlanid or the first empty slot */
1004 first_empty_slot = 0;
1005
1006 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
1007 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
1008 if (!bits && !first_empty_slot)
1009 first_empty_slot = regindex;
1010 else if ((bits & 0x0FFF) == vlan)
1011 break;
1012 }
1013
1014 if (regindex >= IXGBE_VLVF_ENTRIES) {
1015 if (first_empty_slot)
1016 regindex = first_empty_slot;
1017 else {
1018 hw_dbg(hw, "No space in VLVF.\n");
1019 goto out;
1020 }
1021 }
1022
1023 if (vlan_on) {
1024 /* set the pool bit */
1025 if (vind < 32) {
1026 bits = IXGBE_READ_REG(hw,
1027 IXGBE_VLVFB(regindex * 2));
1028 bits |= (1 << vind);
1029 IXGBE_WRITE_REG(hw,
1030 IXGBE_VLVFB(regindex * 2), bits);
1031 } else {
1032 bits = IXGBE_READ_REG(hw,
1033 IXGBE_VLVFB((regindex * 2) + 1));
1034 bits |= (1 << vind);
1035 IXGBE_WRITE_REG(hw,
1036 IXGBE_VLVFB((regindex * 2) + 1), bits);
1037 }
1038 } else {
1039 /* clear the pool bit */
1040 if (vind < 32) {
1041 bits = IXGBE_READ_REG(hw,
1042 IXGBE_VLVFB(regindex * 2));
1043 bits &= ~(1 << vind);
1044 IXGBE_WRITE_REG(hw,
1045 IXGBE_VLVFB(regindex * 2), bits);
1046 bits |= IXGBE_READ_REG(hw,
1047 IXGBE_VLVFB((regindex * 2) + 1));
1048 } else {
1049 bits = IXGBE_READ_REG(hw,
1050 IXGBE_VLVFB((regindex * 2) + 1));
1051 bits &= ~(1 << vind);
1052 IXGBE_WRITE_REG(hw,
1053 IXGBE_VLVFB((regindex * 2) + 1), bits);
1054 bits |= IXGBE_READ_REG(hw,
1055 IXGBE_VLVFB(regindex * 2));
1056 }
1057 }
1058
1059 if (bits)
1060 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1061 (IXGBE_VLVF_VIEN | vlan));
1062 else
1063 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1064 }
1065
1066out:
1067 return 0;
1068}
1069
1070/**
1071 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1072 * @hw: pointer to hardware structure
1073 *
1074 * Clears the VLAN filer table, and the VMDq index associated with the filter
1075 **/
7b25cdba 1076static s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1077{
1078 u32 offset;
1079
1080 for (offset = 0; offset < hw->mac.vft_size; offset++)
1081 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1082
1083 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1084 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1085 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1086 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1087 }
1088
1089 return 0;
1090}
1091
11afc1b1
PW		 1092/**
1093 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1094 * @hw: pointer to hardware structure
1095 **/
7b25cdba 1096static s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1097{
1098 int i;
1099 hw_dbg(hw, " Clearing UTA\n");
1100
1101 for (i = 0; i < 128; i++)
1102 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1103
1104 return 0;
1105}
1106
ffff4772
PWJ		 1107/**
1108 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1109 * @hw: pointer to hardware structure
1110 **/
1111s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1112{
1113 int i;
1114 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1115 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1116
1117 /*
1118 * Before starting reinitialization process,
1119 * FDIRCMD.CMD must be zero.
1120 */
1121 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1122 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1123 IXGBE_FDIRCMD_CMD_MASK))
1124 break;
1125 udelay(10);
1126 }
1127 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1128 hw_dbg(hw ,"Flow Director previous command isn't complete, "
1129 "aborting table re-initialization. \n");
1130 return IXGBE_ERR_FDIR_REINIT_FAILED;
1131 }
1132
1133 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1134 IXGBE_WRITE_FLUSH(hw);
1135 /*
1136 * 82599 adapters flow director init flow cannot be restarted,
1137 * Workaround 82599 silicon errata by performing the following steps
1138 * before re-writing the FDIRCTRL control register with the same value.
1139 * - write 1 to bit 8 of FDIRCMD register &
1140 * - write 0 to bit 8 of FDIRCMD register
1141 */
1142 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1143 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1144 IXGBE_FDIRCMD_CLEARHT));
1145 IXGBE_WRITE_FLUSH(hw);
1146 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1147 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1148 ~IXGBE_FDIRCMD_CLEARHT));
1149 IXGBE_WRITE_FLUSH(hw);
1150 /*
1151 * Clear FDIR Hash register to clear any leftover hashes
1152 * waiting to be programmed.
1153 */
1154 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1155 IXGBE_WRITE_FLUSH(hw);
1156
1157 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1158 IXGBE_WRITE_FLUSH(hw);
1159
1160 /* Poll init-done after we write FDIRCTRL register */
1161 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1162 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1163 IXGBE_FDIRCTRL_INIT_DONE)
1164 break;
1165 udelay(10);
1166 }
1167 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1168 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1169 return IXGBE_ERR_FDIR_REINIT_FAILED;
1170 }
1171
1172 /* Clear FDIR statistics registers (read to clear) */
1173 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1174 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1175 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1176 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1177 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1178
1179 return 0;
1180}
1181
1182/**
1183 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1184 * @hw: pointer to hardware structure
1185 * @pballoc: which mode to allocate filters with
1186 **/
1187s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1188{
1189 u32 fdirctrl = 0;
1190 u32 pbsize;
1191 int i;
1192
1193 /*
1194 * Before enabling Flow Director, the Rx Packet Buffer size
1195 * must be reduced. The new value is the current size minus
1196 * flow director memory usage size.
1197 */
1198 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1199 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1200 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1201
1202 /*
1203 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1204 * intialized to zero for non DCB mode otherwise actual total RX PB
1205 * would be bigger than programmed and filter space would run into
1206 * the PB 0 region.
1207 */
1208 for (i = 1; i < 8; i++)
1209 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1210
1211 /* Send interrupt when 64 filters are left */
1212 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1213
1214 /* Set the maximum length per hash bucket to 0xA filters */
1215 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1216
1217 switch (pballoc) {
1218 case IXGBE_FDIR_PBALLOC_64K:
1219 /* 8k - 1 signature filters */
1220 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1221 break;
1222 case IXGBE_FDIR_PBALLOC_128K:
1223 /* 16k - 1 signature filters */
1224 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1225 break;
1226 case IXGBE_FDIR_PBALLOC_256K:
1227 /* 32k - 1 signature filters */
1228 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1229 break;
1230 default:
1231 /* bad value */
1232 return IXGBE_ERR_CONFIG;
1233 };
1234
1235 /* Move the flexible bytes to use the ethertype - shift 6 words */
1236 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1237
1238 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1239
1240 /* Prime the keys for hashing */
1241 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1242 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1243 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1244 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1245
1246 /*
1247 * Poll init-done after we write the register. Estimated times:
1248 * 10G: PBALLOC = 11b, timing is 60us
1249 * 1G: PBALLOC = 11b, timing is 600us
1250 * 100M: PBALLOC = 11b, timing is 6ms
1251 *
1252 * Multiple these timings by 4 if under full Rx load
1253 *
1254 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1255 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1256 * this might not finish in our poll time, but we can live with that
1257 * for now.
1258 */
1259 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1260 IXGBE_WRITE_FLUSH(hw);
1261 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1262 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1263 IXGBE_FDIRCTRL_INIT_DONE)
1264 break;
1265 msleep(1);
1266 }
1267 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1268 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1269
1270 return 0;
1271}
1272
1273/**
1274 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1275 * @hw: pointer to hardware structure
1276 * @pballoc: which mode to allocate filters with
1277 **/
1278s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1279{
1280 u32 fdirctrl = 0;
1281 u32 pbsize;
1282 int i;
1283
1284 /*
1285 * Before enabling Flow Director, the Rx Packet Buffer size
1286 * must be reduced. The new value is the current size minus
1287 * flow director memory usage size.
1288 */
1289 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1290 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1291 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1292
1293 /*
1294 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1295 * intialized to zero for non DCB mode otherwise actual total RX PB
1296 * would be bigger than programmed and filter space would run into
1297 * the PB 0 region.
1298 */
1299 for (i = 1; i < 8; i++)
1300 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1301
1302 /* Send interrupt when 64 filters are left */
1303 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1304
1305 switch (pballoc) {
1306 case IXGBE_FDIR_PBALLOC_64K:
1307 /* 2k - 1 perfect filters */
1308 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1309 break;
1310 case IXGBE_FDIR_PBALLOC_128K:
1311 /* 4k - 1 perfect filters */
1312 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1313 break;
1314 case IXGBE_FDIR_PBALLOC_256K:
1315 /* 8k - 1 perfect filters */
1316 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1317 break;
1318 default:
1319 /* bad value */
1320 return IXGBE_ERR_CONFIG;
1321 };
1322
1323 /* Turn perfect match filtering on */
1324 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1325 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1326
1327 /* Move the flexible bytes to use the ethertype - shift 6 words */
1328 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1329
1330 /* Prime the keys for hashing */
1331 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1332 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1333 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1334 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1335
1336 /*
1337 * Poll init-done after we write the register. Estimated times:
1338 * 10G: PBALLOC = 11b, timing is 60us
1339 * 1G: PBALLOC = 11b, timing is 600us
1340 * 100M: PBALLOC = 11b, timing is 6ms
1341 *
1342 * Multiple these timings by 4 if under full Rx load
1343 *
1344 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1345 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1346 * this might not finish in our poll time, but we can live with that
1347 * for now.
1348 */
1349
1350 /* Set the maximum length per hash bucket to 0xA filters */
1351 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1352
1353 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1354 IXGBE_WRITE_FLUSH(hw);
1355 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1356 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1357 IXGBE_FDIRCTRL_INIT_DONE)
1358 break;
1359 msleep(1);
1360 }
1361 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1362 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1363
1364 return 0;
1365}
1366
1367
1368/**
1369 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1370 * @stream: input bitstream to compute the hash on
1371 * @key: 32-bit hash key
1372 **/
7b25cdba
DS		 1373static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1374 u32 key)
ffff4772
PWJ		 1375{
1376 /*
1377 * The algorithm is as follows:
1378 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1379 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1380 * and A[n] x B[n] is bitwise AND between same length strings
1381 *
1382 * K[n] is 16 bits, defined as:
1383 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1384 * for n modulo 32 < 15, K[n] =
1385 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1386 *
1387 * S[n] is 16 bits, defined as:
1388 * for n >= 15, S[n] = S[n:n - 15]
1389 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1390 *
1391 * To simplify for programming, the algorithm is implemented
1392 * in software this way:
1393 *
1394 * Key[31:0], Stream[335:0]
1395 *
1396 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1397 * int_key[350:0] = tmp_key[351:1]
1398 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1399 *
1400 * hash[15:0] = 0;
1401 * for (i = 0; i < 351; i++) {
1402 * if (int_key[i])
1403 * hash ^= int_stream[(i + 15):i];
1404 * }
1405 */
1406
1407 union {
1408 u64 fill[6];
1409 u32 key[11];
1410 u8 key_stream[44];
1411 } tmp_key;
1412
1413 u8 *stream = (u8 *)atr_input;
1414 u8 int_key[44]; /* upper-most bit unused */
1415 u8 hash_str[46]; /* upper-most 2 bits unused */
1416 u16 hash_result = 0;
1417 int i, j, k, h;
1418
1419 /*
1420 * Initialize the fill member to prevent warnings
1421 * on some compilers
1422 */
1423 tmp_key.fill[0] = 0;
1424
1425 /* First load the temporary key stream */
1426 for (i = 0; i < 6; i++) {
1427 u64 fillkey = ((u64)key << 32) | key;
1428 tmp_key.fill[i] = fillkey;
1429 }
1430
1431 /*
1432 * Set the interim key for the hashing. Bit 352 is unused, so we must
1433 * shift and compensate when building the key.
1434 */
1435
1436 int_key[0] = tmp_key.key_stream[0] >> 1;
1437 for (i = 1, j = 0; i < 44; i++) {
1438 unsigned int this_key = tmp_key.key_stream[j] << 7;
1439 j++;
1440 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1441 }
1442
1443 /*
1444 * Set the interim bit string for the hashing. Bits 368 and 367 are
1445 * unused, so shift and compensate when building the string.
1446 */
1447 hash_str[0] = (stream[40] & 0x7f) >> 1;
1448 for (i = 1, j = 40; i < 46; i++) {
1449 unsigned int this_str = stream[j] << 7;
1450 j++;
1451 if (j > 41)
1452 j = 0;
1453 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1454 }
1455
1456 /*
1457 * Now compute the hash. i is the index into hash_str, j is into our
1458 * key stream, k is counting the number of bits, and h interates within
1459 * each byte.
1460 */
1461 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1462 for (h = 0; h < 8 && k < 351; h++, k++) {
1463 if (int_key[j] & (1 << h)) {
1464 /*
1465 * Key bit is set, XOR in the current 16-bit
1466 * string. Example of processing:
1467 * h = 0,
1468 * tmp = (hash_str[i - 2] & 0 << 16) |
1469 * (hash_str[i - 1] & 0xff << 8) |
1470 * (hash_str[i] & 0xff >> 0)
1471 * So tmp = hash_str[15 + k:k], since the
1472 * i + 2 clause rolls off the 16-bit value
1473 * h = 7,
1474 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1475 * (hash_str[i - 1] & 0xff << 1) |
1476 * (hash_str[i] & 0x80 >> 7)
1477 */
1478 int tmp = (hash_str[i] >> h);
1479 tmp |= (hash_str[i - 1] << (8 - h));
1480 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1481 << (16 - h);
1482 hash_result ^= (u16)tmp;
1483 }
1484 }
1485 }
1486
1487 return hash_result;
1488}
1489
1490/**
1491 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1492 * @input: input stream to modify
1493 * @vlan: the VLAN id to load
1494 **/
1495s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1496{
1497 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1498 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1499
1500 return 0;
1501}
1502
1503/**
1504 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1505 * @input: input stream to modify
1506 * @src_addr: the IP address to load
1507 **/
1508s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1509{
1510 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1511 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1512 (src_addr >> 16) & 0xff;
1513 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1514 (src_addr >> 8) & 0xff;
1515 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1516
1517 return 0;
1518}
1519
1520/**
1521 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1522 * @input: input stream to modify
1523 * @dst_addr: the IP address to load
1524 **/
1525s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1526{
1527 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1528 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1529 (dst_addr >> 16) & 0xff;
1530 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1531 (dst_addr >> 8) & 0xff;
1532 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1533
1534 return 0;
1535}
1536
1537/**
1538 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1539 * @input: input stream to modify
1540 * @src_addr_1: the first 4 bytes of the IP address to load
1541 * @src_addr_2: the second 4 bytes of the IP address to load
1542 * @src_addr_3: the third 4 bytes of the IP address to load
1543 * @src_addr_4: the fourth 4 bytes of the IP address to load
1544 **/
1545s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1546 u32 src_addr_1, u32 src_addr_2,
1547 u32 src_addr_3, u32 src_addr_4)
ffff4772
PWJ		 1548{
1549 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1550 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1551 (src_addr_4 >> 8) & 0xff;
1552 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1553 (src_addr_4 >> 16) & 0xff;
1554 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1555
1556 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1557 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1558 (src_addr_3 >> 8) & 0xff;
1559 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1560 (src_addr_3 >> 16) & 0xff;
1561 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1562
1563 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1564 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1565 (src_addr_2 >> 8) & 0xff;
1566 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1567 (src_addr_2 >> 16) & 0xff;
1568 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1569
1570 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1571 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1572 (src_addr_1 >> 8) & 0xff;
1573 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1574 (src_addr_1 >> 16) & 0xff;
1575 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1576
1577 return 0;
1578}
1579
1580/**
1581 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1582 * @input: input stream to modify
1583 * @dst_addr_1: the first 4 bytes of the IP address to load
1584 * @dst_addr_2: the second 4 bytes of the IP address to load
1585 * @dst_addr_3: the third 4 bytes of the IP address to load
1586 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1587 **/
1588s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1589 u32 dst_addr_1, u32 dst_addr_2,
1590 u32 dst_addr_3, u32 dst_addr_4)
ffff4772
PWJ		 1591{
1592 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1593 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1594 (dst_addr_4 >> 8) & 0xff;
1595 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1596 (dst_addr_4 >> 16) & 0xff;
1597 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1598
1599 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1600 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1601 (dst_addr_3 >> 8) & 0xff;
1602 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1603 (dst_addr_3 >> 16) & 0xff;
1604 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1605
1606 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1607 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1608 (dst_addr_2 >> 8) & 0xff;
1609 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1610 (dst_addr_2 >> 16) & 0xff;
1611 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1612
1613 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1614 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1615 (dst_addr_1 >> 8) & 0xff;
1616 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1617 (dst_addr_1 >> 16) & 0xff;
1618 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1619
1620 return 0;
1621}
1622
1623/**
1624 * ixgbe_atr_set_src_port_82599 - Sets the source port
1625 * @input: input stream to modify
1626 * @src_port: the source port to load
1627 **/
1628s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1629{
1630 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1631 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1632
1633 return 0;
1634}
1635
1636/**
1637 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1638 * @input: input stream to modify
1639 * @dst_port: the destination port to load
1640 **/
1641s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1642{
1643 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1644 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1645
1646 return 0;
1647}
1648
1649/**
1650 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1651 * @input: input stream to modify
1652 * @flex_bytes: the flexible bytes to load
1653 **/
1654s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1655{
1656 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1657 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1658
1659 return 0;
1660}
1661
1662/**
1663 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1664 * @input: input stream to modify
1665 * @vm_pool: the Virtual Machine pool to load
1666 **/
7b25cdba
DS		 1667s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
1668 u8 vm_pool)
ffff4772
PWJ		 1669{
1670 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1671
1672 return 0;
1673}
1674
1675/**
1676 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1677 * @input: input stream to modify
1678 * @l4type: the layer 4 type value to load
1679 **/
1680s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1681{
1682 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1683
1684 return 0;
1685}
1686
1687/**
1688 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1689 * @input: input stream to search
1690 * @vlan: the VLAN id to load
1691 **/
7b25cdba
DS		 1692static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input,
1693 u16 *vlan)
ffff4772
PWJ		 1694{
1695 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1696 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1697
1698 return 0;
1699}
1700
1701/**
1702 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1703 * @input: input stream to search
1704 * @src_addr: the IP address to load
1705 **/
7b25cdba
DS		 1706static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1707 u32 *src_addr)
ffff4772
PWJ		 1708{
1709 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1710 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1711 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1712 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1713
1714 return 0;
1715}
1716
1717/**
1718 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1719 * @input: input stream to search
1720 * @dst_addr: the IP address to load
1721 **/
7b25cdba
DS		 1722static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1723 u32 *dst_addr)
ffff4772
PWJ		 1724{
1725 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1726 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1727 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1728 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1729
1730 return 0;
1731}
1732
1733/**
1734 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1735 * @input: input stream to search
1736 * @src_addr_1: the first 4 bytes of the IP address to load
1737 * @src_addr_2: the second 4 bytes of the IP address to load
1738 * @src_addr_3: the third 4 bytes of the IP address to load
1739 * @src_addr_4: the fourth 4 bytes of the IP address to load
1740 **/
7b25cdba
DS		 1741static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1742 u32 *src_addr_1, u32 *src_addr_2,
1743 u32 *src_addr_3, u32 *src_addr_4)
ffff4772
PWJ		 1744{
1745 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1746 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1747 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1748 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1749
1750 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1751 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1752 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1753 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1754
1755 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1756 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1757 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1758 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1759
1760 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1761 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1762 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1763 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1764
1765 return 0;
1766}
1767
1768/**
1769 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1770 * @input: input stream to search
1771 * @dst_addr_1: the first 4 bytes of the IP address to load
1772 * @dst_addr_2: the second 4 bytes of the IP address to load
1773 * @dst_addr_3: the third 4 bytes of the IP address to load
1774 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1775 **/
1776s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1777 u32 *dst_addr_1, u32 *dst_addr_2,
1778 u32 *dst_addr_3, u32 *dst_addr_4)
ffff4772
PWJ		 1779{
1780 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1781 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1782 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1783 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1784
1785 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1786 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1787 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1788 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1789
1790 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1791 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1792 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1793 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1794
1795 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1796 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1797 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1798 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1799
1800 return 0;
1801}
1802
1803/**
1804 * ixgbe_atr_get_src_port_82599 - Gets the source port
1805 * @input: input stream to modify
1806 * @src_port: the source port to load
1807 *
1808 * Even though the input is given in big-endian, the FDIRPORT registers
1809 * expect the ports to be programmed in little-endian. Hence the need to swap
1810 * endianness when retrieving the data. This can be confusing since the
1811 * internal hash engine expects it to be big-endian.
1812 **/
7b25cdba
DS		 1813static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1814 u16 *src_port)
ffff4772
PWJ		 1815{
1816 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1817 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1818
1819 return 0;
1820}
1821
1822/**
1823 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1824 * @input: input stream to modify
1825 * @dst_port: the destination port to load
1826 *
1827 * Even though the input is given in big-endian, the FDIRPORT registers
1828 * expect the ports to be programmed in little-endian. Hence the need to swap
1829 * endianness when retrieving the data. This can be confusing since the
1830 * internal hash engine expects it to be big-endian.
1831 **/
7b25cdba
DS		 1832static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1833 u16 *dst_port)
ffff4772
PWJ		 1834{
1835 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1836 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1837
1838 return 0;
1839}
1840
1841/**
1842 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1843 * @input: input stream to modify
1844 * @flex_bytes: the flexible bytes to load
1845 **/
7b25cdba
DS		 1846static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1847 u16 *flex_byte)
ffff4772
PWJ		 1848{
1849 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1850 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1851
1852 return 0;
1853}
1854
1855/**
1856 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
1857 * @input: input stream to modify
1858 * @vm_pool: the Virtual Machine pool to load
1859 **/
7b25cdba
DS		 1860s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
1861 u8 *vm_pool)
ffff4772
PWJ		 1862{
1863 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
1864
1865 return 0;
1866}
1867
1868/**
1869 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1870 * @input: input stream to modify
1871 * @l4type: the layer 4 type value to load
1872 **/
7b25cdba
DS		 1873static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
1874 u8 *l4type)
ffff4772
PWJ		 1875{
1876 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
1877
1878 return 0;
1879}
1880
1881/**
1882 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1883 * @hw: pointer to hardware structure
1884 * @stream: input bitstream
1885 * @queue: queue index to direct traffic to
1886 **/
1887s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1888 struct ixgbe_atr_input *input,
1889 u8 queue)
1890{
1891 u64 fdirhashcmd;
1892 u64 fdircmd;
1893 u32 fdirhash;
1894 u16 bucket_hash, sig_hash;
1895 u8 l4type;
1896
1897 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1898 IXGBE_ATR_BUCKET_HASH_KEY);
1899
1900 /* bucket_hash is only 15 bits */
1901 bucket_hash &= IXGBE_ATR_HASH_MASK;
1902
1903 sig_hash = ixgbe_atr_compute_hash_82599(input,
1904 IXGBE_ATR_SIGNATURE_HASH_KEY);
1905
1906 /* Get the l4type in order to program FDIRCMD properly */
1907 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1908 ixgbe_atr_get_l4type_82599(input, &l4type);
1909
1910 /*
1911 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1912 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1913 */
1914 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1915
1916 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1917 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
1918
1919 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1920 case IXGBE_ATR_L4TYPE_TCP:
1921 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1922 break;
1923 case IXGBE_ATR_L4TYPE_UDP:
1924 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1925 break;
1926 case IXGBE_ATR_L4TYPE_SCTP:
1927 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1928 break;
1929 default:
1930 hw_dbg(hw, "Error on l4type input\n");
1931 return IXGBE_ERR_CONFIG;
1932 }
1933
1934 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
1935 fdircmd |= IXGBE_FDIRCMD_IPV6;
1936
1937 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
1938 fdirhashcmd = ((fdircmd << 32) | fdirhash);
1939
1940 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1941
1942 return 0;
1943}
1944
1945/**
1946 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1947 * @hw: pointer to hardware structure
1948 * @input: input bitstream
1949 * @queue: queue index to direct traffic to
1950 *
1951 * Note that the caller to this function must lock before calling, since the
1952 * hardware writes must be protected from one another.
1953 **/
1954s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
7b25cdba
DS		 1955 struct ixgbe_atr_input *input,
1956 u16 soft_id,
1957 u8 queue)
ffff4772
PWJ		 1958{
1959 u32 fdircmd = 0;
1960 u32 fdirhash;
1961 u32 src_ipv4, dst_ipv4;
1962 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
1963 u16 src_port, dst_port, vlan_id, flex_bytes;
1964 u16 bucket_hash;
1965 u8 l4type;
1966
1967 /* Get our input values */
1968 ixgbe_atr_get_l4type_82599(input, &l4type);
1969
1970 /*
1971 * Check l4type formatting, and bail out before we touch the hardware
1972 * if there's a configuration issue
1973 */
1974 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1975 case IXGBE_ATR_L4TYPE_TCP:
1976 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1977 break;
1978 case IXGBE_ATR_L4TYPE_UDP:
1979 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1980 break;
1981 case IXGBE_ATR_L4TYPE_SCTP:
1982 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1983 break;
1984 default:
1985 hw_dbg(hw, "Error on l4type input\n");
1986 return IXGBE_ERR_CONFIG;
1987 }
1988
1989 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1990 IXGBE_ATR_BUCKET_HASH_KEY);
1991
1992 /* bucket_hash is only 15 bits */
1993 bucket_hash &= IXGBE_ATR_HASH_MASK;
1994
1995 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
1996 ixgbe_atr_get_src_port_82599(input, &src_port);
1997 ixgbe_atr_get_dst_port_82599(input, &dst_port);
1998 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
1999
2000 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2001
2002 /* Now figure out if we're IPv4 or IPv6 */
2003 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
2004 /* IPv6 */
2005 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
2006 &src_ipv6_3, &src_ipv6_4);
2007
2008 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
2009 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
2010 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
2011 /* The last 4 bytes is the same register as IPv4 */
2012 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
2013
2014 fdircmd |= IXGBE_FDIRCMD_IPV6;
2015 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
2016 } else {
2017 /* IPv4 */
2018 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
2019 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
2020
2021 }
2022
2023 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
2024 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
2025
2026 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
2027 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
2028 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
2029 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
2030
2031 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
2032 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
2033 fdircmd |= IXGBE_FDIRCMD_LAST;
2034 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
2035 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
2036
2037 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2038 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
2039
2040 return 0;
2041}
11afc1b1
PW		 2042/**
2043 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2044 * @hw: pointer to hardware structure
2045 * @reg: analog register to read
2046 * @val: read value
2047 *
2048 * Performs read operation to Omer analog register specified.
2049 **/
7b25cdba 2050static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
11afc1b1
PW		 2051{
2052 u32 core_ctl;
2053
2054 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2055 (reg << 8));
2056 IXGBE_WRITE_FLUSH(hw);
2057 udelay(10);
2058 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2059 *val = (u8)core_ctl;
2060
2061 return 0;
2062}
2063
2064/**
2065 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2066 * @hw: pointer to hardware structure
2067 * @reg: atlas register to write
2068 * @val: value to write
2069 *
2070 * Performs write operation to Omer analog register specified.
2071 **/
7b25cdba 2072static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
11afc1b1
PW		 2073{
2074 u32 core_ctl;
2075
2076 core_ctl = (reg << 8) | val;
2077 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2078 IXGBE_WRITE_FLUSH(hw);
2079 udelay(10);
2080
2081 return 0;
2082}
2083
2084/**
2085 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2086 * @hw: pointer to hardware structure
2087 *
2088 * Starts the hardware using the generic start_hw function.
2089 * Then performs device-specific:
2090 * Clears the rate limiter registers.
2091 **/
7b25cdba 2092static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2093{
2094 u32 q_num;
794caeb2 2095 s32 ret_val;
11afc1b1 2096
794caeb2 2097 ret_val = ixgbe_start_hw_generic(hw);
11afc1b1
PW		 2098
2099 /* Clear the rate limiters */
2100 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2101 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2102 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2103 }
2104 IXGBE_WRITE_FLUSH(hw);
2105
50ac58ba
PWJ		 2106 /* We need to run link autotry after the driver loads */
2107 hw->mac.autotry_restart = true;
2108
794caeb2
PWJ		 2109 if (ret_val == 0)
2110 ret_val = ixgbe_verify_fw_version_82599(hw);
2111
2112 return ret_val;
11afc1b1
PW		 2113}
2114
2115/**
2116 * ixgbe_identify_phy_82599 - Get physical layer module
2117 * @hw: pointer to hardware structure
2118 *
2119 * Determines the physical layer module found on the current adapter.
2120 **/
7b25cdba 2121static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2122{
2123 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2124 status = ixgbe_identify_phy_generic(hw);
2125 if (status != 0)
2126 status = ixgbe_identify_sfp_module_generic(hw);
2127 return status;
2128}
2129
2130/**
2131 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2132 * @hw: pointer to hardware structure
2133 *
2134 * Determines physical layer capabilities of the current configuration.
2135 **/
7b25cdba 2136static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2137{
2138 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 2139 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2140 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2141 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2142 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2143 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2144 u16 ext_ability = 0;
1339b9e9 2145 u8 comp_codes_10g = 0;
11afc1b1 2146
04193058
PWJ		 2147 hw->phy.ops.identify(hw);
2148
2149 if (hw->phy.type == ixgbe_phy_tn ||
2150 hw->phy.type == ixgbe_phy_cu_unknown) {
6b73e10d
BH		 2151 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2152 &ext_ability);
2153 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 2154 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 2155 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 2156 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 2157 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 2158 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2159 goto out;
2160 }
2161
2162 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2163 case IXGBE_AUTOC_LMS_1G_AN:
2164 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2165 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2166 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2167 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2168 goto out;
2169 } else
2170 /* SFI mode so read SFP module */
2171 goto sfp_check;
11afc1b1 2172 break;
04193058
PWJ		 2173 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2174 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2175 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2176 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2177 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 2178 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2179 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 2180 goto out;
2181 break;
2182 case IXGBE_AUTOC_LMS_10G_SERIAL:
2183 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2184 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2185 goto out;
2186 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2187 goto sfp_check;
2188 break;
2189 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2190 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2191 if (autoc & IXGBE_AUTOC_KX_SUPP)
2192 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2193 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2194 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2195 if (autoc & IXGBE_AUTOC_KR_SUPP)
2196 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2197 goto out;
2198 break;
2199 default:
2200 goto out;
2201 break;
2202 }
11afc1b1 2203
04193058
PWJ		 2204sfp_check:
2205 /* SFP check must be done last since DA modules are sometimes used to
2206 * test KR mode - we need to id KR mode correctly before SFP module.
2207 * Call identify_sfp because the pluggable module may have changed */
2208 hw->phy.ops.identify_sfp(hw);
2209 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2210 goto out;
2211
2212 switch (hw->phy.type) {
2213 case ixgbe_phy_tw_tyco:
2214 case ixgbe_phy_tw_unknown:
2215 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2216 break;
2217 case ixgbe_phy_sfp_avago:
2218 case ixgbe_phy_sfp_ftl:
2219 case ixgbe_phy_sfp_intel:
2220 case ixgbe_phy_sfp_unknown:
2221 hw->phy.ops.read_i2c_eeprom(hw,
2222 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2223 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 2224 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 2225 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 2226 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
11afc1b1
PW		 2227 break;
2228 default:
11afc1b1
PW		 2229 break;
2230 }
2231
04193058 2232out:
11afc1b1
PW		 2233 return physical_layer;
2234}
2235
2236/**
2237 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2238 * @hw: pointer to hardware structure
2239 * @regval: register value to write to RXCTRL
2240 *
2241 * Enables the Rx DMA unit for 82599
2242 **/
7b25cdba 2243static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
11afc1b1
PW		 2244{
2245#define IXGBE_MAX_SECRX_POLL 30
2246 int i;
2247 int secrxreg;
2248
2249 /*
2250 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2251 * If traffic is incoming before we enable the Rx unit, it could hang
2252 * the Rx DMA unit. Therefore, make sure the security engine is
2253 * completely disabled prior to enabling the Rx unit.
2254 */
2255 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2256 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2257 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2258 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2259 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2260 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2261 break;
2262 else
2263 udelay(10);
2264 }
2265
2266 /* For informational purposes only */
2267 if (i >= IXGBE_MAX_SECRX_POLL)
2268 hw_dbg(hw, "Rx unit being enabled before security "
2269 "path fully disabled. Continuing with init.\n");
2270
2271 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2272 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2273 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2274 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2275 IXGBE_WRITE_FLUSH(hw);
2276
2277 return 0;
2278}
2279
04193058
PWJ		 2280/**
2281 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2282 * @hw: pointer to hardware structure
2283 * @device_caps: the EEPROM word with the extra device capabilities
2284 *
2285 * This function will read the EEPROM location for the device capabilities,
2286 * and return the word through device_caps.
2287 **/
7b25cdba 2288static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
04193058
PWJ		 2289{
2290 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2291
2292 return 0;
2293}
2294
0365e6e4
PW		 2295/**
2296 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2297 * @hw: pointer to hardware structure
2298 * @san_mac_offset: SAN MAC address offset
2299 *
2300 * This function will read the EEPROM location for the SAN MAC address
2301 * pointer, and returns the value at that location. This is used in both
2302 * get and set mac_addr routines.
2303 **/
7b25cdba
DS		 2304static s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
2305 u16 *san_mac_offset)
0365e6e4
PW		 2306{
2307 /*
2308 * First read the EEPROM pointer to see if the MAC addresses are
2309 * available.
2310 */
2311 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2312
2313 return 0;
2314}
2315
2316/**
2317 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2318 * @hw: pointer to hardware structure
2319 * @san_mac_addr: SAN MAC address
2320 *
2321 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2322 * per-port, so set_lan_id() must be called before reading the addresses.
2323 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2324 * upon for non-SFP connections, so we must call it here.
2325 **/
7b25cdba 2326static s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
0365e6e4
PW		 2327{
2328 u16 san_mac_data, san_mac_offset;
2329 u8 i;
2330
2331 /*
2332 * First read the EEPROM pointer to see if the MAC addresses are
2333 * available. If they're not, no point in calling set_lan_id() here.
2334 */
2335 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2336
2337 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2338 /*
2339 * No addresses available in this EEPROM. It's not an
2340 * error though, so just wipe the local address and return.
2341 */
2342 for (i = 0; i < 6; i++)
2343 san_mac_addr[i] = 0xFF;
2344
2345 goto san_mac_addr_out;
2346 }
2347
2348 /* make sure we know which port we need to program */
2349 hw->mac.ops.set_lan_id(hw);
2350 /* apply the port offset to the address offset */
2351 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2352 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2353 for (i = 0; i < 3; i++) {
2354 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2355 san_mac_addr[i * 2] = (u8)(san_mac_data);
2356 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2357 san_mac_offset++;
2358 }
2359
2360san_mac_addr_out:
2361 return 0;
2362}
2363
794caeb2
PWJ		 2364/**
2365 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2366 * @hw: pointer to hardware structure
2367 *
2368 * Verifies that installed the firmware version is 0.6 or higher
2369 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2370 *
2371 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2372 * if the FW version is not supported.
2373 **/
2374static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2375{
2376 s32 status = IXGBE_ERR_EEPROM_VERSION;
2377 u16 fw_offset, fw_ptp_cfg_offset;
2378 u16 fw_version = 0;
2379
2380 /* firmware check is only necessary for SFI devices */
2381 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2382 status = 0;
2383 goto fw_version_out;
2384 }
2385
2386 /* get the offset to the Firmware Module block */
2387 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2388
2389 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2390 goto fw_version_out;
2391
2392 /* get the offset to the Pass Through Patch Configuration block */
2393 hw->eeprom.ops.read(hw, (fw_offset +
2394 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2395 &fw_ptp_cfg_offset);
2396
2397 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2398 goto fw_version_out;
2399
2400 /* get the firmware version */
2401 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2402 IXGBE_FW_PATCH_VERSION_4),
2403 &fw_version);
2404
2405 if (fw_version > 0x5)
2406 status = 0;
2407
2408fw_version_out:
2409 return status;
2410}
2411
11afc1b1
PW		 2412static struct ixgbe_mac_operations mac_ops_82599 = {
2413 .init_hw = &ixgbe_init_hw_generic,
2414 .reset_hw = &ixgbe_reset_hw_82599,
2415 .start_hw = &ixgbe_start_hw_82599,
2416 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2417 .get_media_type = &ixgbe_get_media_type_82599,
2418 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2419 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2420 .get_mac_addr = &ixgbe_get_mac_addr_generic,
0365e6e4 2421 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
04193058 2422 .get_device_caps = &ixgbe_get_device_caps_82599,
11afc1b1
PW		 2423 .stop_adapter = &ixgbe_stop_adapter_generic,
2424 .get_bus_info = &ixgbe_get_bus_info_generic,
2425 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2426 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2427 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2428 .setup_link = &ixgbe_setup_mac_link_82599,
11afc1b1
PW		 2429 .check_link = &ixgbe_check_mac_link_82599,
2430 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2431 .led_on = &ixgbe_led_on_generic,
2432 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 2433 .blink_led_start = &ixgbe_blink_led_start_generic,
2434 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 2435 .set_rar = &ixgbe_set_rar_generic,
2436 .clear_rar = &ixgbe_clear_rar_generic,
2437 .set_vmdq = &ixgbe_set_vmdq_82599,
2438 .clear_vmdq = &ixgbe_clear_vmdq_82599,
2439 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2440 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2441 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2442 .enable_mc = &ixgbe_enable_mc_generic,
2443 .disable_mc = &ixgbe_disable_mc_generic,
2444 .clear_vfta = &ixgbe_clear_vfta_82599,
2445 .set_vfta = &ixgbe_set_vfta_82599,
620fa036 2446 .fc_enable = &ixgbe_fc_enable_generic,
11afc1b1
PW		 2447 .init_uta_tables = &ixgbe_init_uta_tables_82599,
2448 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2449};
2450
2451static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2452 .init_params = &ixgbe_init_eeprom_params_generic,
2453 .read = &ixgbe_read_eeprom_generic,
2454 .write = &ixgbe_write_eeprom_generic,
2455 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2456 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2457};
2458
2459static struct ixgbe_phy_operations phy_ops_82599 = {
2460 .identify = &ixgbe_identify_phy_82599,
2461 .identify_sfp = &ixgbe_identify_sfp_module_generic,
04f165ef 2462 .init = &ixgbe_init_phy_ops_82599,
11afc1b1
PW		 2463 .reset = &ixgbe_reset_phy_generic,
2464 .read_reg = &ixgbe_read_phy_reg_generic,
2465 .write_reg = &ixgbe_write_phy_reg_generic,
2466 .setup_link = &ixgbe_setup_phy_link_generic,
2467 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2468 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2469 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2470 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2471 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2472};
2473
2474struct ixgbe_info ixgbe_82599_info = {
2475 .mac = ixgbe_mac_82599EB,
2476 .get_invariants = &ixgbe_get_invariants_82599,
2477 .mac_ops = &mac_ops_82599,
2478 .eeprom_ops = &eeprom_ops_82599,
2479 .phy_ops = &phy_ops_82599,
2480};
Linux kernel - Deliverables
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