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ixgbe: add support for 82599 Combined Backplane
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
34
35#define IXGBE_82599_MAX_TX_QUEUES 128
36#define IXGBE_82599_MAX_RX_QUEUES 128
37#define IXGBE_82599_RAR_ENTRIES 128
38#define IXGBE_82599_MC_TBL_SIZE 128
39#define IXGBE_82599_VFT_TBL_SIZE 128
40
8620a103
MC		 41s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
42 ixgbe_link_speed speed,
43 bool autoneg,
44 bool autoneg_wait_to_complete);
45s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
46 bool autoneg_wait_to_complete);
47s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
48 ixgbe_link_speed speed,
49 bool autoneg,
50 bool autoneg_wait_to_complete);
11afc1b1
PW		 51static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
52 ixgbe_link_speed *speed,
53 bool *autoneg);
8620a103
MC		 54static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
55 ixgbe_link_speed speed,
56 bool autoneg,
57 bool autoneg_wait_to_complete);
794caeb2 58static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
11afc1b1 59
7b25cdba 60static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 61{
62 struct ixgbe_mac_info *mac = &hw->mac;
63 if (hw->phy.multispeed_fiber) {
64 /* Set up dual speed SFP+ support */
8620a103 65 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
11afc1b1 66 } else {
8620a103 67 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
11afc1b1
PW		 68 }
69}
70
7b25cdba 71static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 72{
73 s32 ret_val = 0;
74 u16 list_offset, data_offset, data_value;
75
76 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
77 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 78
79 hw->phy.ops.reset = NULL;
80
11afc1b1
PW		 81 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
82 &data_offset);
83
84 if (ret_val != 0)
85 goto setup_sfp_out;
86
aa5aec88
PWJ		 87 /* PHY config will finish before releasing the semaphore */
88 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
89 if (ret_val != 0) {
90 ret_val = IXGBE_ERR_SWFW_SYNC;
91 goto setup_sfp_out;
92 }
93
11afc1b1
PW		 94 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
95 while (data_value != 0xffff) {
96 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
97 IXGBE_WRITE_FLUSH(hw);
98 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
99 }
1479ad4f
PWJ		 100 /* Now restart DSP by setting Restart_AN */
101 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
102 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
aa5aec88
PWJ		 103
104 /* Release the semaphore */
105 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
106 /* Delay obtaining semaphore again to allow FW access */
107 msleep(hw->eeprom.semaphore_delay);
11afc1b1
PW		 108 }
109
110setup_sfp_out:
111 return ret_val;
112}
113
114/**
115 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
116 * @hw: pointer to hardware structure
117 *
118 * Read PCIe configuration space, and get the MSI-X vector count from
119 * the capabilities table.
120 **/
7b25cdba 121static u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 122{
123 struct ixgbe_adapter *adapter = hw->back;
124 u16 msix_count;
125 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
126 &msix_count);
127 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
128
129 /* MSI-X count is zero-based in HW, so increment to give proper value */
130 msix_count++;
131
132 return msix_count;
133}
134
135static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
136{
137 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 138
04f165ef 139 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 140
04f165ef
PW		 141 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
142 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
143 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
144 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
145 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
146 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
11afc1b1 147
04f165ef
PW		 148 return 0;
149}
11afc1b1 150
04f165ef
PW		 151/**
152 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
153 * @hw: pointer to hardware structure
154 *
155 * Initialize any function pointers that were not able to be
156 * set during get_invariants because the PHY/SFP type was
157 * not known. Perform the SFP init if necessary.
158 *
159 **/
7b25cdba 160static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
04f165ef
PW		 161{
162 struct ixgbe_mac_info *mac = &hw->mac;
163 struct ixgbe_phy_info *phy = &hw->phy;
164 s32 ret_val = 0;
11afc1b1 165
04f165ef
PW		 166 /* Identify the PHY or SFP module */
167 ret_val = phy->ops.identify(hw);
168
169 /* Setup function pointers based on detected SFP module and speeds */
170 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 171
172 /* If copper media, overwrite with copper function pointers */
173 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
174 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
11afc1b1
PW		 175 mac->ops.get_link_capabilities =
176 &ixgbe_get_copper_link_capabilities_82599;
177 }
178
04f165ef 179 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 180 switch (hw->phy.type) {
181 case ixgbe_phy_tn:
182 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
183 phy->ops.get_firmware_version =
04f165ef 184 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 185 break;
186 default:
187 break;
188 }
189
11afc1b1
PW		 190 return ret_val;
191}
192
193/**
194 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
195 * @hw: pointer to hardware structure
196 * @speed: pointer to link speed
197 * @negotiation: true when autoneg or autotry is enabled
198 *
199 * Determines the link capabilities by reading the AUTOC register.
200 **/
7b25cdba
DS		 201static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
202 ixgbe_link_speed *speed,
203 bool *negotiation)
11afc1b1
PW		 204{
205 s32 status = 0;
1eb99d5a 206 u32 autoc = 0;
11afc1b1 207
1eb99d5a
PW		 208 /*
209 * Determine link capabilities based on the stored value of AUTOC,
210 * which represents EEPROM defaults. If AUTOC value has not been
211 * stored, use the current register value.
212 */
213 if (hw->mac.orig_link_settings_stored)
214 autoc = hw->mac.orig_autoc;
215 else
216 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
217
218 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 219 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
220 *speed = IXGBE_LINK_SPEED_1GB_FULL;
221 *negotiation = false;
222 break;
223
224 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
225 *speed = IXGBE_LINK_SPEED_10GB_FULL;
226 *negotiation = false;
227 break;
228
229 case IXGBE_AUTOC_LMS_1G_AN:
230 *speed = IXGBE_LINK_SPEED_1GB_FULL;
231 *negotiation = true;
232 break;
233
234 case IXGBE_AUTOC_LMS_10G_SERIAL:
235 *speed = IXGBE_LINK_SPEED_10GB_FULL;
236 *negotiation = false;
237 break;
238
239 case IXGBE_AUTOC_LMS_KX4_KX_KR:
240 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
241 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 242 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 243 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 244 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 245 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 246 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 247 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
248 *negotiation = true;
249 break;
250
251 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
252 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 253 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 254 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 255 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 256 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 257 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 258 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
259 *negotiation = true;
260 break;
261
262 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
263 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
264 *negotiation = false;
265 break;
266
267 default:
268 status = IXGBE_ERR_LINK_SETUP;
269 goto out;
270 break;
271 }
272
273 if (hw->phy.multispeed_fiber) {
274 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
275 IXGBE_LINK_SPEED_1GB_FULL;
276 *negotiation = true;
277 }
278
279out:
280 return status;
281}
282
283/**
284 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
285 * @hw: pointer to hardware structure
286 * @speed: pointer to link speed
287 * @autoneg: boolean auto-negotiation value
288 *
289 * Determines the link capabilities by reading the AUTOC register.
290 **/
291static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
292 ixgbe_link_speed *speed,
293 bool *autoneg)
294{
295 s32 status = IXGBE_ERR_LINK_SETUP;
296 u16 speed_ability;
297
298 *speed = 0;
299 *autoneg = true;
300
6b73e10d 301 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
11afc1b1
PW		 302 &speed_ability);
303
304 if (status == 0) {
6b73e10d 305 if (speed_ability & MDIO_SPEED_10G)
11afc1b1 306 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
6b73e10d 307 if (speed_ability & MDIO_PMA_SPEED_1000)
11afc1b1
PW		 308 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
309 }
310
311 return status;
312}
313
314/**
315 * ixgbe_get_media_type_82599 - Get media type
316 * @hw: pointer to hardware structure
317 *
318 * Returns the media type (fiber, copper, backplane)
319 **/
7b25cdba 320static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 321{
322 enum ixgbe_media_type media_type;
323
324 /* Detect if there is a copper PHY attached. */
325 if (hw->phy.type == ixgbe_phy_cu_unknown ||
326 hw->phy.type == ixgbe_phy_tn) {
327 media_type = ixgbe_media_type_copper;
328 goto out;
329 }
330
331 switch (hw->device_id) {
11afc1b1 332 case IXGBE_DEV_ID_82599_KX4:
312eb931 333 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
1fcf03e6 334 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 335 /* Default device ID is mezzanine card KX/KX4 */
336 media_type = ixgbe_media_type_backplane;
337 break;
338 case IXGBE_DEV_ID_82599_SFP:
339 media_type = ixgbe_media_type_fiber;
340 break;
8911184f 341 case IXGBE_DEV_ID_82599_CX4:
6b1be199 342 media_type = ixgbe_media_type_cx4;
8911184f 343 break;
11afc1b1
PW		 344 default:
345 media_type = ixgbe_media_type_unknown;
346 break;
347 }
348out:
349 return media_type;
350}
351
352/**
8620a103 353 * ixgbe_start_mac_link_82599 - Setup MAC link settings
11afc1b1 354 * @hw: pointer to hardware structure
8620a103 355 * @autoneg_wait_to_complete: true when waiting for completion is needed
11afc1b1
PW		 356 *
357 * Configures link settings based on values in the ixgbe_hw struct.
358 * Restarts the link. Performs autonegotiation if needed.
359 **/
8620a103
MC		 360s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
361 bool autoneg_wait_to_complete)
11afc1b1
PW		 362{
363 u32 autoc_reg;
364 u32 links_reg;
365 u32 i;
366 s32 status = 0;
367
368 /* Restart link */
369 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
370 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
371 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
372
373 /* Only poll for autoneg to complete if specified to do so */
8620a103 374 if (autoneg_wait_to_complete) {
11afc1b1
PW		 375 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
376 IXGBE_AUTOC_LMS_KX4_KX_KR ||
377 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
378 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
379 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
380 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
381 links_reg = 0; /* Just in case Autoneg time = 0 */
382 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
383 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
384 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
385 break;
386 msleep(100);
387 }
388 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
389 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
390 hw_dbg(hw, "Autoneg did not complete.\n");
391 }
392 }
393 }
394
11afc1b1
PW		 395 /* Add delay to filter out noises during initial link setup */
396 msleep(50);
397
398 return status;
399}
400
401/**
8620a103 402 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
11afc1b1
PW		 403 * @hw: pointer to hardware structure
404 * @speed: new link speed
405 * @autoneg: true if autonegotiation enabled
406 * @autoneg_wait_to_complete: true when waiting for completion is needed
407 *
408 * Set the link speed in the AUTOC register and restarts link.
409 **/
8620a103
MC		 410s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
411 ixgbe_link_speed speed,
412 bool autoneg,
413 bool autoneg_wait_to_complete)
11afc1b1
PW		 414{
415 s32 status = 0;
416 ixgbe_link_speed phy_link_speed;
417 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
418 u32 speedcnt = 0;
419 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
420 bool link_up = false;
421 bool negotiation;
50ac58ba 422 int i;
11afc1b1
PW		 423
424 /* Mask off requested but non-supported speeds */
425 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
426 speed &= phy_link_speed;
427
50ac58ba
PWJ		 428 /*
429 * When the driver changes the link speeds that it can support,
430 * it sets autotry_restart to true to indicate that we need to
431 * initiate a new autotry session with the link partner. To do
432 * so, we set the speed then disable and re-enable the tx laser, to
433 * alert the link partner that it also needs to restart autotry on its
434 * end. This is consistent with true clause 37 autoneg, which also
435 * involves a loss of signal.
436 */
437
11afc1b1
PW		 438 /*
439 * Try each speed one by one, highest priority first. We do this in
440 * software because 10gb fiber doesn't support speed autonegotiation.
441 */
442 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
443 speedcnt++;
444 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
445
50ac58ba
PWJ		 446 /* If we already have link at this speed, just jump out */
447 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
448
449 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
450 goto out;
451
452 /* Set the module link speed */
11afc1b1
PW		 453 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
454 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
455
50ac58ba
PWJ		 456 /* Allow module to change analog characteristics (1G->10G) */
457 msleep(40);
11afc1b1 458
8620a103
MC		 459 status = ixgbe_setup_mac_link_82599(hw,
460 IXGBE_LINK_SPEED_10GB_FULL,
461 autoneg,
462 autoneg_wait_to_complete);
50ac58ba 463 if (status != 0)
c3c74327 464 return status;
50ac58ba
PWJ		 465
466 /* Flap the tx laser if it has not already been done */
467 if (hw->mac.autotry_restart) {
468 /* Disable tx laser; allow 100us to go dark per spec */
469 esdp_reg |= IXGBE_ESDP_SDP3;
470 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
471 udelay(100);
472
473 /* Enable tx laser; allow 2ms to light up per spec */
474 esdp_reg &= ~IXGBE_ESDP_SDP3;
475 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
476 msleep(2);
477
478 hw->mac.autotry_restart = false;
479 }
480
481 /* The controller may take up to 500ms at 10g to acquire link */
482 for (i = 0; i < 5; i++) {
483 /* Wait for the link partner to also set speed */
484 msleep(100);
485
486 /* If we have link, just jump out */
487 hw->mac.ops.check_link(hw, &phy_link_speed,
488 &link_up, false);
489 if (link_up)
490 goto out;
491 }
11afc1b1
PW		 492 }
493
494 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
495 speedcnt++;
496 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
497 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
498
50ac58ba
PWJ		 499 /* If we already have link at this speed, just jump out */
500 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
501
502 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
503 goto out;
504
505 /* Set the module link speed */
11afc1b1
PW		 506 esdp_reg &= ~IXGBE_ESDP_SDP5;
507 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
508 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
509
50ac58ba
PWJ		 510 /* Allow module to change analog characteristics (10G->1G) */
511 msleep(40);
11afc1b1 512
8620a103 513 status = ixgbe_setup_mac_link_82599(hw,
50ac58ba
PWJ		 514 IXGBE_LINK_SPEED_1GB_FULL,
515 autoneg,
516 autoneg_wait_to_complete);
517 if (status != 0)
c3c74327 518 return status;
50ac58ba
PWJ		 519
520 /* Flap the tx laser if it has not already been done */
521 if (hw->mac.autotry_restart) {
522 /* Disable tx laser; allow 100us to go dark per spec */
523 esdp_reg |= IXGBE_ESDP_SDP3;
524 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
525 udelay(100);
526
527 /* Enable tx laser; allow 2ms to light up per spec */
528 esdp_reg &= ~IXGBE_ESDP_SDP3;
529 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
530 msleep(2);
531
532 hw->mac.autotry_restart = false;
533 }
534
535 /* Wait for the link partner to also set speed */
536 msleep(100);
11afc1b1
PW		 537
538 /* If we have link, just jump out */
539 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
540 if (link_up)
541 goto out;
542 }
543
544 /*
545 * We didn't get link. Configure back to the highest speed we tried,
546 * (if there was more than one). We call ourselves back with just the
547 * single highest speed that the user requested.
548 */
549 if (speedcnt > 1)
8620a103
MC		 550 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
551 highest_link_speed,
552 autoneg,
553 autoneg_wait_to_complete);
11afc1b1
PW		 554
555out:
c3c74327
MC		 556 /* Set autoneg_advertised value based on input link speed */
557 hw->phy.autoneg_advertised = 0;
558
559 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
560 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
561
562 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
563 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
564
11afc1b1
PW		 565 return status;
566}
567
568/**
569 * ixgbe_check_mac_link_82599 - Determine link and speed status
570 * @hw: pointer to hardware structure
571 * @speed: pointer to link speed
572 * @link_up: true when link is up
573 * @link_up_wait_to_complete: bool used to wait for link up or not
574 *
575 * Reads the links register to determine if link is up and the current speed
576 **/
7b25cdba
DS		 577static s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
578 ixgbe_link_speed *speed,
579 bool *link_up,
580 bool link_up_wait_to_complete)
11afc1b1
PW		 581{
582 u32 links_reg;
583 u32 i;
584
585 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
586 if (link_up_wait_to_complete) {
587 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
588 if (links_reg & IXGBE_LINKS_UP) {
589 *link_up = true;
590 break;
591 } else {
592 *link_up = false;
593 }
594 msleep(100);
595 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
596 }
597 } else {
598 if (links_reg & IXGBE_LINKS_UP)
599 *link_up = true;
600 else
601 *link_up = false;
602 }
603
604 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
605 IXGBE_LINKS_SPEED_10G_82599)
606 *speed = IXGBE_LINK_SPEED_10GB_FULL;
607 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
608 IXGBE_LINKS_SPEED_1G_82599)
609 *speed = IXGBE_LINK_SPEED_1GB_FULL;
610 else
611 *speed = IXGBE_LINK_SPEED_100_FULL;
612
620fa036
MC		 613 /* if link is down, zero out the current_mode */
614 if (*link_up == false) {
615 hw->fc.current_mode = ixgbe_fc_none;
616 hw->fc.fc_was_autonegged = false;
617 }
11afc1b1
PW		 618
619 return 0;
620}
621
622/**
8620a103 623 * ixgbe_setup_mac_link_82599 - Set MAC link speed
11afc1b1
PW		 624 * @hw: pointer to hardware structure
625 * @speed: new link speed
626 * @autoneg: true if autonegotiation enabled
627 * @autoneg_wait_to_complete: true when waiting for completion is needed
628 *
629 * Set the link speed in the AUTOC register and restarts link.
630 **/
8620a103
MC		 631s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
632 ixgbe_link_speed speed, bool autoneg,
633 bool autoneg_wait_to_complete)
11afc1b1
PW		 634{
635 s32 status = 0;
636 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
637 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
50ac58ba 638 u32 start_autoc = autoc;
1eb99d5a 639 u32 orig_autoc = 0;
11afc1b1
PW		 640 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
641 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
642 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
643 u32 links_reg;
644 u32 i;
645 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
646
647 /* Check to see if speed passed in is supported. */
648 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
649 speed &= link_capabilities;
650
50ac58ba
PWJ		 651 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
652 status = IXGBE_ERR_LINK_SETUP;
653 goto out;
654 }
655
1eb99d5a
PW		 656 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
657 if (hw->mac.orig_link_settings_stored)
658 orig_autoc = hw->mac.orig_autoc;
659 else
660 orig_autoc = autoc;
661
662
50ac58ba
PWJ		 663 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
664 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
665 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
11afc1b1
PW		 666 /* Set KX4/KX/KR support according to speed requested */
667 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
668 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 669 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 670 autoc |= IXGBE_AUTOC_KX4_SUPP;
1eb99d5a 671 if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1
PW		 672 autoc |= IXGBE_AUTOC_KR_SUPP;
673 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
674 autoc |= IXGBE_AUTOC_KX_SUPP;
675 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
676 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
677 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
678 /* Switch from 1G SFI to 10G SFI if requested */
679 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
680 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
681 autoc &= ~IXGBE_AUTOC_LMS_MASK;
682 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
683 }
684 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
685 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
686 /* Switch from 10G SFI to 1G SFI if requested */
687 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
688 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
689 autoc &= ~IXGBE_AUTOC_LMS_MASK;
690 if (autoneg)
691 autoc |= IXGBE_AUTOC_LMS_1G_AN;
692 else
693 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
694 }
695 }
696
50ac58ba 697 if (autoc != start_autoc) {
11afc1b1
PW		 698 /* Restart link */
699 autoc |= IXGBE_AUTOC_AN_RESTART;
700 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
701
702 /* Only poll for autoneg to complete if specified to do so */
703 if (autoneg_wait_to_complete) {
704 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
705 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
706 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
707 links_reg = 0; /*Just in case Autoneg time=0*/
708 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
709 links_reg =
710 IXGBE_READ_REG(hw, IXGBE_LINKS);
711 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
712 break;
713 msleep(100);
714 }
715 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
716 status =
717 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
718 hw_dbg(hw, "Autoneg did not "
719 "complete.\n");
720 }
721 }
722 }
723
11afc1b1
PW		 724 /* Add delay to filter out noises during initial link setup */
725 msleep(50);
726 }
727
50ac58ba 728out:
11afc1b1
PW		 729 return status;
730}
731
732/**
8620a103 733 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
11afc1b1
PW		 734 * @hw: pointer to hardware structure
735 * @speed: new link speed
736 * @autoneg: true if autonegotiation enabled
737 * @autoneg_wait_to_complete: true if waiting is needed to complete
738 *
739 * Restarts link on PHY and MAC based on settings passed in.
740 **/
8620a103
MC		 741static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
742 ixgbe_link_speed speed,
743 bool autoneg,
744 bool autoneg_wait_to_complete)
11afc1b1
PW		 745{
746 s32 status;
747
748 /* Setup the PHY according to input speed */
749 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
750 autoneg_wait_to_complete);
751 /* Set up MAC */
8620a103 752 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
11afc1b1
PW		 753
754 return status;
755}
756
757/**
758 * ixgbe_reset_hw_82599 - Perform hardware reset
759 * @hw: pointer to hardware structure
760 *
761 * Resets the hardware by resetting the transmit and receive units, masks
762 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
763 * reset.
764 **/
7b25cdba 765static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 766{
767 s32 status = 0;
768 u32 ctrl, ctrl_ext;
769 u32 i;
770 u32 autoc;
771 u32 autoc2;
772
773 /* Call adapter stop to disable tx/rx and clear interrupts */
774 hw->mac.ops.stop_adapter(hw);
775
553b4497 776 /* PHY ops must be identified and initialized prior to reset */
04f165ef 777
553b4497
PW		 778 /* Init PHY and function pointers, perform SFP setup */
779 status = hw->phy.ops.init(hw);
04f165ef 780
553b4497
PW		 781 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
782 goto reset_hw_out;
04f165ef 783
553b4497
PW		 784 /* Setup SFP module if there is one present. */
785 if (hw->phy.sfp_setup_needed) {
786 status = hw->mac.ops.setup_sfp(hw);
787 hw->phy.sfp_setup_needed = false;
04f165ef 788 }
11afc1b1 789
553b4497
PW		 790 /* Reset PHY */
791 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
792 hw->phy.ops.reset(hw);
793
11afc1b1
PW		 794 /*
795 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
796 * access and verify no pending requests before reset
797 */
04f165ef
PW		 798 status = ixgbe_disable_pcie_master(hw);
799 if (status != 0) {
11afc1b1
PW		 800 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
801 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
802 }
803
804 /*
805 * Issue global reset to the MAC. This needs to be a SW reset.
806 * If link reset is used, it might reset the MAC when mng is using it
807 */
808 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
809 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
810 IXGBE_WRITE_FLUSH(hw);
811
812 /* Poll for reset bit to self-clear indicating reset is complete */
813 for (i = 0; i < 10; i++) {
814 udelay(1);
815 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
816 if (!(ctrl & IXGBE_CTRL_RST))
817 break;
818 }
819 if (ctrl & IXGBE_CTRL_RST) {
820 status = IXGBE_ERR_RESET_FAILED;
821 hw_dbg(hw, "Reset polling failed to complete.\n");
822 }
823 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
824 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
825 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
826 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
827
828 msleep(50);
829
830
831
832 /*
833 * Store the original AUTOC/AUTOC2 values if they have not been
834 * stored off yet. Otherwise restore the stored original
835 * values since the reset operation sets back to defaults.
836 */
837 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
838 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
839 if (hw->mac.orig_link_settings_stored == false) {
840 hw->mac.orig_autoc = autoc;
841 hw->mac.orig_autoc2 = autoc2;
842 hw->mac.orig_link_settings_stored = true;
4df10466 843 } else {
11afc1b1
PW		 844 if (autoc != hw->mac.orig_autoc)
845 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
846 IXGBE_AUTOC_AN_RESTART));
847
848 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
849 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
850 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
851 autoc2 |= (hw->mac.orig_autoc2 &
852 IXGBE_AUTOC2_UPPER_MASK);
853 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
854 }
855 }
856
aca6bee7
WJP		 857 /*
858 * Store MAC address from RAR0, clear receive address registers, and
859 * clear the multicast table. Also reset num_rar_entries to 128,
860 * since we modify this value when programming the SAN MAC address.
861 */
862 hw->mac.num_rar_entries = 128;
863 hw->mac.ops.init_rx_addrs(hw);
864
11afc1b1
PW		 865 /* Store the permanent mac address */
866 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
867
0365e6e4
PW		 868 /* Store the permanent SAN mac address */
869 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
870
aca6bee7
WJP		 871 /* Add the SAN MAC address to the RAR only if it's a valid address */
872 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
873 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
874 hw->mac.san_addr, 0, IXGBE_RAH_AV);
875
876 /* Reserve the last RAR for the SAN MAC address */
877 hw->mac.num_rar_entries--;
878 }
879
04f165ef 880reset_hw_out:
11afc1b1
PW		 881 return status;
882}
883
884/**
885 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
886 * @hw: pointer to hardware struct
887 * @rar: receive address register index to disassociate
888 * @vmdq: VMDq pool index to remove from the rar
889 **/
7b25cdba 890static s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
11afc1b1
PW		 891{
892 u32 mpsar_lo, mpsar_hi;
893 u32 rar_entries = hw->mac.num_rar_entries;
894
895 if (rar < rar_entries) {
896 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
897 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
898
899 if (!mpsar_lo && !mpsar_hi)
900 goto done;
901
902 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
903 if (mpsar_lo) {
904 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
905 mpsar_lo = 0;
906 }
907 if (mpsar_hi) {
908 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
909 mpsar_hi = 0;
910 }
911 } else if (vmdq < 32) {
912 mpsar_lo &= ~(1 << vmdq);
913 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
914 } else {
915 mpsar_hi &= ~(1 << (vmdq - 32));
916 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
917 }
918
919 /* was that the last pool using this rar? */
920 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
921 hw->mac.ops.clear_rar(hw, rar);
922 } else {
923 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
924 }
925
926done:
927 return 0;
928}
929
930/**
931 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
932 * @hw: pointer to hardware struct
933 * @rar: receive address register index to associate with a VMDq index
934 * @vmdq: VMDq pool index
935 **/
7b25cdba 936static s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
11afc1b1
PW		 937{
938 u32 mpsar;
939 u32 rar_entries = hw->mac.num_rar_entries;
940
941 if (rar < rar_entries) {
942 if (vmdq < 32) {
943 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
944 mpsar |= 1 << vmdq;
945 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
946 } else {
947 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
948 mpsar |= 1 << (vmdq - 32);
949 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
950 }
951 } else {
952 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
953 }
954 return 0;
955}
956
957/**
958 * ixgbe_set_vfta_82599 - Set VLAN filter table
959 * @hw: pointer to hardware structure
960 * @vlan: VLAN id to write to VLAN filter
961 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
962 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
963 *
964 * Turn on/off specified VLAN in the VLAN filter table.
965 **/
7b25cdba
DS		 966static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
967 bool vlan_on)
11afc1b1
PW		 968{
969 u32 regindex;
970 u32 bitindex;
971 u32 bits;
972 u32 first_empty_slot;
973
974 if (vlan > 4095)
975 return IXGBE_ERR_PARAM;
976
977 /*
978 * this is a 2 part operation - first the VFTA, then the
979 * VLVF and VLVFB if vind is set
980 */
981
982 /* Part 1
983 * The VFTA is a bitstring made up of 128 32-bit registers
984 * that enable the particular VLAN id, much like the MTA:
985 * bits[11-5]: which register
986 * bits[4-0]: which bit in the register
987 */
988 regindex = (vlan >> 5) & 0x7F;
989 bitindex = vlan & 0x1F;
990 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
991 if (vlan_on)
992 bits |= (1 << bitindex);
993 else
994 bits &= ~(1 << bitindex);
995 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
996
997
998 /* Part 2
999 * If the vind is set
1000 * Either vlan_on
1001 * make sure the vlan is in VLVF
1002 * set the vind bit in the matching VLVFB
1003 * Or !vlan_on
1004 * clear the pool bit and possibly the vind
1005 */
1006 if (vind) {
1007 /* find the vlanid or the first empty slot */
1008 first_empty_slot = 0;
1009
1010 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
1011 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
1012 if (!bits && !first_empty_slot)
1013 first_empty_slot = regindex;
1014 else if ((bits & 0x0FFF) == vlan)
1015 break;
1016 }
1017
1018 if (regindex >= IXGBE_VLVF_ENTRIES) {
1019 if (first_empty_slot)
1020 regindex = first_empty_slot;
1021 else {
1022 hw_dbg(hw, "No space in VLVF.\n");
1023 goto out;
1024 }
1025 }
1026
1027 if (vlan_on) {
1028 /* set the pool bit */
1029 if (vind < 32) {
1030 bits = IXGBE_READ_REG(hw,
1031 IXGBE_VLVFB(regindex * 2));
1032 bits |= (1 << vind);
1033 IXGBE_WRITE_REG(hw,
1034 IXGBE_VLVFB(regindex * 2), bits);
1035 } else {
1036 bits = IXGBE_READ_REG(hw,
1037 IXGBE_VLVFB((regindex * 2) + 1));
1038 bits |= (1 << vind);
1039 IXGBE_WRITE_REG(hw,
1040 IXGBE_VLVFB((regindex * 2) + 1), bits);
1041 }
1042 } else {
1043 /* clear the pool bit */
1044 if (vind < 32) {
1045 bits = IXGBE_READ_REG(hw,
1046 IXGBE_VLVFB(regindex * 2));
1047 bits &= ~(1 << vind);
1048 IXGBE_WRITE_REG(hw,
1049 IXGBE_VLVFB(regindex * 2), bits);
1050 bits |= IXGBE_READ_REG(hw,
1051 IXGBE_VLVFB((regindex * 2) + 1));
1052 } else {
1053 bits = IXGBE_READ_REG(hw,
1054 IXGBE_VLVFB((regindex * 2) + 1));
1055 bits &= ~(1 << vind);
1056 IXGBE_WRITE_REG(hw,
1057 IXGBE_VLVFB((regindex * 2) + 1), bits);
1058 bits |= IXGBE_READ_REG(hw,
1059 IXGBE_VLVFB(regindex * 2));
1060 }
1061 }
1062
1063 if (bits)
1064 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1065 (IXGBE_VLVF_VIEN | vlan));
1066 else
1067 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1068 }
1069
1070out:
1071 return 0;
1072}
1073
1074/**
1075 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1076 * @hw: pointer to hardware structure
1077 *
1078 * Clears the VLAN filer table, and the VMDq index associated with the filter
1079 **/
7b25cdba 1080static s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1081{
1082 u32 offset;
1083
1084 for (offset = 0; offset < hw->mac.vft_size; offset++)
1085 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1086
1087 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1088 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1089 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1090 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1091 }
1092
1093 return 0;
1094}
1095
11afc1b1
PW		 1096/**
1097 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1098 * @hw: pointer to hardware structure
1099 **/
7b25cdba 1100static s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1101{
1102 int i;
1103 hw_dbg(hw, " Clearing UTA\n");
1104
1105 for (i = 0; i < 128; i++)
1106 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1107
1108 return 0;
1109}
1110
ffff4772
PWJ		 1111/**
1112 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1113 * @hw: pointer to hardware structure
1114 **/
1115s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1116{
1117 int i;
1118 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1119 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1120
1121 /*
1122 * Before starting reinitialization process,
1123 * FDIRCMD.CMD must be zero.
1124 */
1125 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1126 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1127 IXGBE_FDIRCMD_CMD_MASK))
1128 break;
1129 udelay(10);
1130 }
1131 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1132 hw_dbg(hw ,"Flow Director previous command isn't complete, "
1133 "aborting table re-initialization. \n");
1134 return IXGBE_ERR_FDIR_REINIT_FAILED;
1135 }
1136
1137 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1138 IXGBE_WRITE_FLUSH(hw);
1139 /*
1140 * 82599 adapters flow director init flow cannot be restarted,
1141 * Workaround 82599 silicon errata by performing the following steps
1142 * before re-writing the FDIRCTRL control register with the same value.
1143 * - write 1 to bit 8 of FDIRCMD register &
1144 * - write 0 to bit 8 of FDIRCMD register
1145 */
1146 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1147 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1148 IXGBE_FDIRCMD_CLEARHT));
1149 IXGBE_WRITE_FLUSH(hw);
1150 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1151 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1152 ~IXGBE_FDIRCMD_CLEARHT));
1153 IXGBE_WRITE_FLUSH(hw);
1154 /*
1155 * Clear FDIR Hash register to clear any leftover hashes
1156 * waiting to be programmed.
1157 */
1158 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1159 IXGBE_WRITE_FLUSH(hw);
1160
1161 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1162 IXGBE_WRITE_FLUSH(hw);
1163
1164 /* Poll init-done after we write FDIRCTRL register */
1165 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1166 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1167 IXGBE_FDIRCTRL_INIT_DONE)
1168 break;
1169 udelay(10);
1170 }
1171 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1172 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1173 return IXGBE_ERR_FDIR_REINIT_FAILED;
1174 }
1175
1176 /* Clear FDIR statistics registers (read to clear) */
1177 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1178 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1179 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1180 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1181 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1182
1183 return 0;
1184}
1185
1186/**
1187 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1188 * @hw: pointer to hardware structure
1189 * @pballoc: which mode to allocate filters with
1190 **/
1191s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1192{
1193 u32 fdirctrl = 0;
1194 u32 pbsize;
1195 int i;
1196
1197 /*
1198 * Before enabling Flow Director, the Rx Packet Buffer size
1199 * must be reduced. The new value is the current size minus
1200 * flow director memory usage size.
1201 */
1202 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1203 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1204 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1205
1206 /*
1207 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1208 * intialized to zero for non DCB mode otherwise actual total RX PB
1209 * would be bigger than programmed and filter space would run into
1210 * the PB 0 region.
1211 */
1212 for (i = 1; i < 8; i++)
1213 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1214
1215 /* Send interrupt when 64 filters are left */
1216 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1217
1218 /* Set the maximum length per hash bucket to 0xA filters */
1219 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1220
1221 switch (pballoc) {
1222 case IXGBE_FDIR_PBALLOC_64K:
1223 /* 8k - 1 signature filters */
1224 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1225 break;
1226 case IXGBE_FDIR_PBALLOC_128K:
1227 /* 16k - 1 signature filters */
1228 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1229 break;
1230 case IXGBE_FDIR_PBALLOC_256K:
1231 /* 32k - 1 signature filters */
1232 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1233 break;
1234 default:
1235 /* bad value */
1236 return IXGBE_ERR_CONFIG;
1237 };
1238
1239 /* Move the flexible bytes to use the ethertype - shift 6 words */
1240 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1241
1242 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1243
1244 /* Prime the keys for hashing */
1245 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1246 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1247 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1248 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1249
1250 /*
1251 * Poll init-done after we write the register. Estimated times:
1252 * 10G: PBALLOC = 11b, timing is 60us
1253 * 1G: PBALLOC = 11b, timing is 600us
1254 * 100M: PBALLOC = 11b, timing is 6ms
1255 *
1256 * Multiple these timings by 4 if under full Rx load
1257 *
1258 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1259 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1260 * this might not finish in our poll time, but we can live with that
1261 * for now.
1262 */
1263 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1264 IXGBE_WRITE_FLUSH(hw);
1265 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1266 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1267 IXGBE_FDIRCTRL_INIT_DONE)
1268 break;
1269 msleep(1);
1270 }
1271 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1272 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1273
1274 return 0;
1275}
1276
1277/**
1278 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1279 * @hw: pointer to hardware structure
1280 * @pballoc: which mode to allocate filters with
1281 **/
1282s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1283{
1284 u32 fdirctrl = 0;
1285 u32 pbsize;
1286 int i;
1287
1288 /*
1289 * Before enabling Flow Director, the Rx Packet Buffer size
1290 * must be reduced. The new value is the current size minus
1291 * flow director memory usage size.
1292 */
1293 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1294 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1295 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1296
1297 /*
1298 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1299 * intialized to zero for non DCB mode otherwise actual total RX PB
1300 * would be bigger than programmed and filter space would run into
1301 * the PB 0 region.
1302 */
1303 for (i = 1; i < 8; i++)
1304 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1305
1306 /* Send interrupt when 64 filters are left */
1307 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1308
1309 switch (pballoc) {
1310 case IXGBE_FDIR_PBALLOC_64K:
1311 /* 2k - 1 perfect filters */
1312 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1313 break;
1314 case IXGBE_FDIR_PBALLOC_128K:
1315 /* 4k - 1 perfect filters */
1316 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1317 break;
1318 case IXGBE_FDIR_PBALLOC_256K:
1319 /* 8k - 1 perfect filters */
1320 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1321 break;
1322 default:
1323 /* bad value */
1324 return IXGBE_ERR_CONFIG;
1325 };
1326
1327 /* Turn perfect match filtering on */
1328 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1329 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1330
1331 /* Move the flexible bytes to use the ethertype - shift 6 words */
1332 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1333
1334 /* Prime the keys for hashing */
1335 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1336 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1337 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1338 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1339
1340 /*
1341 * Poll init-done after we write the register. Estimated times:
1342 * 10G: PBALLOC = 11b, timing is 60us
1343 * 1G: PBALLOC = 11b, timing is 600us
1344 * 100M: PBALLOC = 11b, timing is 6ms
1345 *
1346 * Multiple these timings by 4 if under full Rx load
1347 *
1348 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1349 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1350 * this might not finish in our poll time, but we can live with that
1351 * for now.
1352 */
1353
1354 /* Set the maximum length per hash bucket to 0xA filters */
1355 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1356
1357 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1358 IXGBE_WRITE_FLUSH(hw);
1359 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1360 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1361 IXGBE_FDIRCTRL_INIT_DONE)
1362 break;
1363 msleep(1);
1364 }
1365 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1366 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1367
1368 return 0;
1369}
1370
1371
1372/**
1373 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1374 * @stream: input bitstream to compute the hash on
1375 * @key: 32-bit hash key
1376 **/
7b25cdba
DS		 1377static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1378 u32 key)
ffff4772
PWJ		 1379{
1380 /*
1381 * The algorithm is as follows:
1382 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1383 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1384 * and A[n] x B[n] is bitwise AND between same length strings
1385 *
1386 * K[n] is 16 bits, defined as:
1387 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1388 * for n modulo 32 < 15, K[n] =
1389 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1390 *
1391 * S[n] is 16 bits, defined as:
1392 * for n >= 15, S[n] = S[n:n - 15]
1393 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1394 *
1395 * To simplify for programming, the algorithm is implemented
1396 * in software this way:
1397 *
1398 * Key[31:0], Stream[335:0]
1399 *
1400 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1401 * int_key[350:0] = tmp_key[351:1]
1402 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1403 *
1404 * hash[15:0] = 0;
1405 * for (i = 0; i < 351; i++) {
1406 * if (int_key[i])
1407 * hash ^= int_stream[(i + 15):i];
1408 * }
1409 */
1410
1411 union {
1412 u64 fill[6];
1413 u32 key[11];
1414 u8 key_stream[44];
1415 } tmp_key;
1416
1417 u8 *stream = (u8 *)atr_input;
1418 u8 int_key[44]; /* upper-most bit unused */
1419 u8 hash_str[46]; /* upper-most 2 bits unused */
1420 u16 hash_result = 0;
1421 int i, j, k, h;
1422
1423 /*
1424 * Initialize the fill member to prevent warnings
1425 * on some compilers
1426 */
1427 tmp_key.fill[0] = 0;
1428
1429 /* First load the temporary key stream */
1430 for (i = 0; i < 6; i++) {
1431 u64 fillkey = ((u64)key << 32) | key;
1432 tmp_key.fill[i] = fillkey;
1433 }
1434
1435 /*
1436 * Set the interim key for the hashing. Bit 352 is unused, so we must
1437 * shift and compensate when building the key.
1438 */
1439
1440 int_key[0] = tmp_key.key_stream[0] >> 1;
1441 for (i = 1, j = 0; i < 44; i++) {
1442 unsigned int this_key = tmp_key.key_stream[j] << 7;
1443 j++;
1444 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1445 }
1446
1447 /*
1448 * Set the interim bit string for the hashing. Bits 368 and 367 are
1449 * unused, so shift and compensate when building the string.
1450 */
1451 hash_str[0] = (stream[40] & 0x7f) >> 1;
1452 for (i = 1, j = 40; i < 46; i++) {
1453 unsigned int this_str = stream[j] << 7;
1454 j++;
1455 if (j > 41)
1456 j = 0;
1457 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1458 }
1459
1460 /*
1461 * Now compute the hash. i is the index into hash_str, j is into our
1462 * key stream, k is counting the number of bits, and h interates within
1463 * each byte.
1464 */
1465 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1466 for (h = 0; h < 8 && k < 351; h++, k++) {
1467 if (int_key[j] & (1 << h)) {
1468 /*
1469 * Key bit is set, XOR in the current 16-bit
1470 * string. Example of processing:
1471 * h = 0,
1472 * tmp = (hash_str[i - 2] & 0 << 16) |
1473 * (hash_str[i - 1] & 0xff << 8) |
1474 * (hash_str[i] & 0xff >> 0)
1475 * So tmp = hash_str[15 + k:k], since the
1476 * i + 2 clause rolls off the 16-bit value
1477 * h = 7,
1478 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1479 * (hash_str[i - 1] & 0xff << 1) |
1480 * (hash_str[i] & 0x80 >> 7)
1481 */
1482 int tmp = (hash_str[i] >> h);
1483 tmp |= (hash_str[i - 1] << (8 - h));
1484 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1485 << (16 - h);
1486 hash_result ^= (u16)tmp;
1487 }
1488 }
1489 }
1490
1491 return hash_result;
1492}
1493
1494/**
1495 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1496 * @input: input stream to modify
1497 * @vlan: the VLAN id to load
1498 **/
1499s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1500{
1501 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1502 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1503
1504 return 0;
1505}
1506
1507/**
1508 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1509 * @input: input stream to modify
1510 * @src_addr: the IP address to load
1511 **/
1512s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1513{
1514 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1515 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1516 (src_addr >> 16) & 0xff;
1517 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1518 (src_addr >> 8) & 0xff;
1519 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1520
1521 return 0;
1522}
1523
1524/**
1525 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1526 * @input: input stream to modify
1527 * @dst_addr: the IP address to load
1528 **/
1529s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1530{
1531 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1532 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1533 (dst_addr >> 16) & 0xff;
1534 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1535 (dst_addr >> 8) & 0xff;
1536 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1537
1538 return 0;
1539}
1540
1541/**
1542 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1543 * @input: input stream to modify
1544 * @src_addr_1: the first 4 bytes of the IP address to load
1545 * @src_addr_2: the second 4 bytes of the IP address to load
1546 * @src_addr_3: the third 4 bytes of the IP address to load
1547 * @src_addr_4: the fourth 4 bytes of the IP address to load
1548 **/
1549s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1550 u32 src_addr_1, u32 src_addr_2,
1551 u32 src_addr_3, u32 src_addr_4)
ffff4772
PWJ		 1552{
1553 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1554 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1555 (src_addr_4 >> 8) & 0xff;
1556 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1557 (src_addr_4 >> 16) & 0xff;
1558 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1559
1560 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1561 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1562 (src_addr_3 >> 8) & 0xff;
1563 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1564 (src_addr_3 >> 16) & 0xff;
1565 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1566
1567 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1568 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1569 (src_addr_2 >> 8) & 0xff;
1570 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1571 (src_addr_2 >> 16) & 0xff;
1572 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1573
1574 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1575 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1576 (src_addr_1 >> 8) & 0xff;
1577 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1578 (src_addr_1 >> 16) & 0xff;
1579 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1580
1581 return 0;
1582}
1583
1584/**
1585 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1586 * @input: input stream to modify
1587 * @dst_addr_1: the first 4 bytes of the IP address to load
1588 * @dst_addr_2: the second 4 bytes of the IP address to load
1589 * @dst_addr_3: the third 4 bytes of the IP address to load
1590 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1591 **/
1592s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1593 u32 dst_addr_1, u32 dst_addr_2,
1594 u32 dst_addr_3, u32 dst_addr_4)
ffff4772
PWJ		 1595{
1596 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1597 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1598 (dst_addr_4 >> 8) & 0xff;
1599 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1600 (dst_addr_4 >> 16) & 0xff;
1601 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1602
1603 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1604 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1605 (dst_addr_3 >> 8) & 0xff;
1606 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1607 (dst_addr_3 >> 16) & 0xff;
1608 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1609
1610 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1611 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1612 (dst_addr_2 >> 8) & 0xff;
1613 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1614 (dst_addr_2 >> 16) & 0xff;
1615 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1616
1617 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1618 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1619 (dst_addr_1 >> 8) & 0xff;
1620 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1621 (dst_addr_1 >> 16) & 0xff;
1622 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1623
1624 return 0;
1625}
1626
1627/**
1628 * ixgbe_atr_set_src_port_82599 - Sets the source port
1629 * @input: input stream to modify
1630 * @src_port: the source port to load
1631 **/
1632s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1633{
1634 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1635 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1636
1637 return 0;
1638}
1639
1640/**
1641 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1642 * @input: input stream to modify
1643 * @dst_port: the destination port to load
1644 **/
1645s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1646{
1647 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1648 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1649
1650 return 0;
1651}
1652
1653/**
1654 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1655 * @input: input stream to modify
1656 * @flex_bytes: the flexible bytes to load
1657 **/
1658s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1659{
1660 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1661 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1662
1663 return 0;
1664}
1665
1666/**
1667 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1668 * @input: input stream to modify
1669 * @vm_pool: the Virtual Machine pool to load
1670 **/
7b25cdba
DS		 1671s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
1672 u8 vm_pool)
ffff4772
PWJ		 1673{
1674 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1675
1676 return 0;
1677}
1678
1679/**
1680 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1681 * @input: input stream to modify
1682 * @l4type: the layer 4 type value to load
1683 **/
1684s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1685{
1686 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1687
1688 return 0;
1689}
1690
1691/**
1692 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1693 * @input: input stream to search
1694 * @vlan: the VLAN id to load
1695 **/
7b25cdba
DS		 1696static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input,
1697 u16 *vlan)
ffff4772
PWJ		 1698{
1699 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1700 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1701
1702 return 0;
1703}
1704
1705/**
1706 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1707 * @input: input stream to search
1708 * @src_addr: the IP address to load
1709 **/
7b25cdba
DS		 1710static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1711 u32 *src_addr)
ffff4772
PWJ		 1712{
1713 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1714 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1715 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1716 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1717
1718 return 0;
1719}
1720
1721/**
1722 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1723 * @input: input stream to search
1724 * @dst_addr: the IP address to load
1725 **/
7b25cdba
DS		 1726static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1727 u32 *dst_addr)
ffff4772
PWJ		 1728{
1729 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1730 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1731 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1732 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1733
1734 return 0;
1735}
1736
1737/**
1738 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1739 * @input: input stream to search
1740 * @src_addr_1: the first 4 bytes of the IP address to load
1741 * @src_addr_2: the second 4 bytes of the IP address to load
1742 * @src_addr_3: the third 4 bytes of the IP address to load
1743 * @src_addr_4: the fourth 4 bytes of the IP address to load
1744 **/
7b25cdba
DS		 1745static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1746 u32 *src_addr_1, u32 *src_addr_2,
1747 u32 *src_addr_3, u32 *src_addr_4)
ffff4772
PWJ		 1748{
1749 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1750 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1751 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1752 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1753
1754 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1755 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1756 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1757 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1758
1759 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1760 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1761 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1762 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1763
1764 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1765 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1766 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1767 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1768
1769 return 0;
1770}
1771
1772/**
1773 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1774 * @input: input stream to search
1775 * @dst_addr_1: the first 4 bytes of the IP address to load
1776 * @dst_addr_2: the second 4 bytes of the IP address to load
1777 * @dst_addr_3: the third 4 bytes of the IP address to load
1778 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1779 **/
1780s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1781 u32 *dst_addr_1, u32 *dst_addr_2,
1782 u32 *dst_addr_3, u32 *dst_addr_4)
ffff4772
PWJ		 1783{
1784 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1785 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1786 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1787 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1788
1789 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1790 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1791 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1792 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1793
1794 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1795 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1796 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1797 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1798
1799 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1800 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1801 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1802 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1803
1804 return 0;
1805}
1806
1807/**
1808 * ixgbe_atr_get_src_port_82599 - Gets the source port
1809 * @input: input stream to modify
1810 * @src_port: the source port to load
1811 *
1812 * Even though the input is given in big-endian, the FDIRPORT registers
1813 * expect the ports to be programmed in little-endian. Hence the need to swap
1814 * endianness when retrieving the data. This can be confusing since the
1815 * internal hash engine expects it to be big-endian.
1816 **/
7b25cdba
DS		 1817static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1818 u16 *src_port)
ffff4772
PWJ		 1819{
1820 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1821 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1822
1823 return 0;
1824}
1825
1826/**
1827 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1828 * @input: input stream to modify
1829 * @dst_port: the destination port to load
1830 *
1831 * Even though the input is given in big-endian, the FDIRPORT registers
1832 * expect the ports to be programmed in little-endian. Hence the need to swap
1833 * endianness when retrieving the data. This can be confusing since the
1834 * internal hash engine expects it to be big-endian.
1835 **/
7b25cdba
DS		 1836static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1837 u16 *dst_port)
ffff4772
PWJ		 1838{
1839 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1840 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1841
1842 return 0;
1843}
1844
1845/**
1846 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1847 * @input: input stream to modify
1848 * @flex_bytes: the flexible bytes to load
1849 **/
7b25cdba
DS		 1850static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1851 u16 *flex_byte)
ffff4772
PWJ		 1852{
1853 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1854 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1855
1856 return 0;
1857}
1858
1859/**
1860 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
1861 * @input: input stream to modify
1862 * @vm_pool: the Virtual Machine pool to load
1863 **/
7b25cdba
DS		 1864s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
1865 u8 *vm_pool)
ffff4772
PWJ		 1866{
1867 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
1868
1869 return 0;
1870}
1871
1872/**
1873 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1874 * @input: input stream to modify
1875 * @l4type: the layer 4 type value to load
1876 **/
7b25cdba
DS		 1877static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
1878 u8 *l4type)
ffff4772
PWJ		 1879{
1880 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
1881
1882 return 0;
1883}
1884
1885/**
1886 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1887 * @hw: pointer to hardware structure
1888 * @stream: input bitstream
1889 * @queue: queue index to direct traffic to
1890 **/
1891s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1892 struct ixgbe_atr_input *input,
1893 u8 queue)
1894{
1895 u64 fdirhashcmd;
1896 u64 fdircmd;
1897 u32 fdirhash;
1898 u16 bucket_hash, sig_hash;
1899 u8 l4type;
1900
1901 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1902 IXGBE_ATR_BUCKET_HASH_KEY);
1903
1904 /* bucket_hash is only 15 bits */
1905 bucket_hash &= IXGBE_ATR_HASH_MASK;
1906
1907 sig_hash = ixgbe_atr_compute_hash_82599(input,
1908 IXGBE_ATR_SIGNATURE_HASH_KEY);
1909
1910 /* Get the l4type in order to program FDIRCMD properly */
1911 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1912 ixgbe_atr_get_l4type_82599(input, &l4type);
1913
1914 /*
1915 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1916 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1917 */
1918 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1919
1920 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1921 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
1922
1923 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1924 case IXGBE_ATR_L4TYPE_TCP:
1925 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1926 break;
1927 case IXGBE_ATR_L4TYPE_UDP:
1928 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1929 break;
1930 case IXGBE_ATR_L4TYPE_SCTP:
1931 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1932 break;
1933 default:
1934 hw_dbg(hw, "Error on l4type input\n");
1935 return IXGBE_ERR_CONFIG;
1936 }
1937
1938 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
1939 fdircmd |= IXGBE_FDIRCMD_IPV6;
1940
1941 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
1942 fdirhashcmd = ((fdircmd << 32) | fdirhash);
1943
1944 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1945
1946 return 0;
1947}
1948
1949/**
1950 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1951 * @hw: pointer to hardware structure
1952 * @input: input bitstream
1953 * @queue: queue index to direct traffic to
1954 *
1955 * Note that the caller to this function must lock before calling, since the
1956 * hardware writes must be protected from one another.
1957 **/
1958s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
7b25cdba
DS		 1959 struct ixgbe_atr_input *input,
1960 u16 soft_id,
1961 u8 queue)
ffff4772
PWJ		 1962{
1963 u32 fdircmd = 0;
1964 u32 fdirhash;
1965 u32 src_ipv4, dst_ipv4;
1966 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
1967 u16 src_port, dst_port, vlan_id, flex_bytes;
1968 u16 bucket_hash;
1969 u8 l4type;
1970
1971 /* Get our input values */
1972 ixgbe_atr_get_l4type_82599(input, &l4type);
1973
1974 /*
1975 * Check l4type formatting, and bail out before we touch the hardware
1976 * if there's a configuration issue
1977 */
1978 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1979 case IXGBE_ATR_L4TYPE_TCP:
1980 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1981 break;
1982 case IXGBE_ATR_L4TYPE_UDP:
1983 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1984 break;
1985 case IXGBE_ATR_L4TYPE_SCTP:
1986 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1987 break;
1988 default:
1989 hw_dbg(hw, "Error on l4type input\n");
1990 return IXGBE_ERR_CONFIG;
1991 }
1992
1993 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1994 IXGBE_ATR_BUCKET_HASH_KEY);
1995
1996 /* bucket_hash is only 15 bits */
1997 bucket_hash &= IXGBE_ATR_HASH_MASK;
1998
1999 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
2000 ixgbe_atr_get_src_port_82599(input, &src_port);
2001 ixgbe_atr_get_dst_port_82599(input, &dst_port);
2002 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
2003
2004 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2005
2006 /* Now figure out if we're IPv4 or IPv6 */
2007 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
2008 /* IPv6 */
2009 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
2010 &src_ipv6_3, &src_ipv6_4);
2011
2012 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
2013 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
2014 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
2015 /* The last 4 bytes is the same register as IPv4 */
2016 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
2017
2018 fdircmd |= IXGBE_FDIRCMD_IPV6;
2019 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
2020 } else {
2021 /* IPv4 */
2022 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
2023 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
2024
2025 }
2026
2027 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
2028 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
2029
2030 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
2031 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
2032 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
2033 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
2034
2035 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
2036 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
2037 fdircmd |= IXGBE_FDIRCMD_LAST;
2038 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
2039 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
2040
2041 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2042 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
2043
2044 return 0;
2045}
11afc1b1
PW		 2046/**
2047 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2048 * @hw: pointer to hardware structure
2049 * @reg: analog register to read
2050 * @val: read value
2051 *
2052 * Performs read operation to Omer analog register specified.
2053 **/
7b25cdba 2054static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
11afc1b1
PW		 2055{
2056 u32 core_ctl;
2057
2058 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2059 (reg << 8));
2060 IXGBE_WRITE_FLUSH(hw);
2061 udelay(10);
2062 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2063 *val = (u8)core_ctl;
2064
2065 return 0;
2066}
2067
2068/**
2069 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2070 * @hw: pointer to hardware structure
2071 * @reg: atlas register to write
2072 * @val: value to write
2073 *
2074 * Performs write operation to Omer analog register specified.
2075 **/
7b25cdba 2076static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
11afc1b1
PW		 2077{
2078 u32 core_ctl;
2079
2080 core_ctl = (reg << 8) | val;
2081 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2082 IXGBE_WRITE_FLUSH(hw);
2083 udelay(10);
2084
2085 return 0;
2086}
2087
2088/**
2089 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2090 * @hw: pointer to hardware structure
2091 *
2092 * Starts the hardware using the generic start_hw function.
2093 * Then performs device-specific:
2094 * Clears the rate limiter registers.
2095 **/
7b25cdba 2096static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2097{
2098 u32 q_num;
794caeb2 2099 s32 ret_val;
11afc1b1 2100
794caeb2 2101 ret_val = ixgbe_start_hw_generic(hw);
11afc1b1
PW		 2102
2103 /* Clear the rate limiters */
2104 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2105 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2106 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2107 }
2108 IXGBE_WRITE_FLUSH(hw);
2109
50ac58ba
PWJ		 2110 /* We need to run link autotry after the driver loads */
2111 hw->mac.autotry_restart = true;
2112
794caeb2
PWJ		 2113 if (ret_val == 0)
2114 ret_val = ixgbe_verify_fw_version_82599(hw);
2115
2116 return ret_val;
11afc1b1
PW		 2117}
2118
2119/**
2120 * ixgbe_identify_phy_82599 - Get physical layer module
2121 * @hw: pointer to hardware structure
2122 *
2123 * Determines the physical layer module found on the current adapter.
2124 **/
7b25cdba 2125static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2126{
2127 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2128 status = ixgbe_identify_phy_generic(hw);
2129 if (status != 0)
2130 status = ixgbe_identify_sfp_module_generic(hw);
2131 return status;
2132}
2133
2134/**
2135 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2136 * @hw: pointer to hardware structure
2137 *
2138 * Determines physical layer capabilities of the current configuration.
2139 **/
7b25cdba 2140static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2141{
2142 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 2143 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2144 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2145 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2146 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2147 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2148 u16 ext_ability = 0;
1339b9e9 2149 u8 comp_codes_10g = 0;
11afc1b1 2150
04193058
PWJ		 2151 hw->phy.ops.identify(hw);
2152
2153 if (hw->phy.type == ixgbe_phy_tn ||
2154 hw->phy.type == ixgbe_phy_cu_unknown) {
6b73e10d
BH		 2155 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2156 &ext_ability);
2157 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 2158 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 2159 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 2160 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 2161 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 2162 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2163 goto out;
2164 }
2165
2166 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2167 case IXGBE_AUTOC_LMS_1G_AN:
2168 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2169 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2170 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2171 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2172 goto out;
2173 } else
2174 /* SFI mode so read SFP module */
2175 goto sfp_check;
11afc1b1 2176 break;
04193058
PWJ		 2177 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2178 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2179 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2180 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2181 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 2182 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2183 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 2184 goto out;
2185 break;
2186 case IXGBE_AUTOC_LMS_10G_SERIAL:
2187 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2188 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2189 goto out;
2190 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2191 goto sfp_check;
2192 break;
2193 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2194 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2195 if (autoc & IXGBE_AUTOC_KX_SUPP)
2196 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2197 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2198 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2199 if (autoc & IXGBE_AUTOC_KR_SUPP)
2200 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2201 goto out;
2202 break;
2203 default:
2204 goto out;
2205 break;
2206 }
11afc1b1 2207
04193058
PWJ		 2208sfp_check:
2209 /* SFP check must be done last since DA modules are sometimes used to
2210 * test KR mode - we need to id KR mode correctly before SFP module.
2211 * Call identify_sfp because the pluggable module may have changed */
2212 hw->phy.ops.identify_sfp(hw);
2213 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2214 goto out;
2215
2216 switch (hw->phy.type) {
2217 case ixgbe_phy_tw_tyco:
2218 case ixgbe_phy_tw_unknown:
2219 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2220 break;
2221 case ixgbe_phy_sfp_avago:
2222 case ixgbe_phy_sfp_ftl:
2223 case ixgbe_phy_sfp_intel:
2224 case ixgbe_phy_sfp_unknown:
2225 hw->phy.ops.read_i2c_eeprom(hw,
2226 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2227 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 2228 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 2229 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 2230 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
11afc1b1
PW		 2231 break;
2232 default:
11afc1b1
PW		 2233 break;
2234 }
2235
04193058 2236out:
11afc1b1
PW		 2237 return physical_layer;
2238}
2239
2240/**
2241 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2242 * @hw: pointer to hardware structure
2243 * @regval: register value to write to RXCTRL
2244 *
2245 * Enables the Rx DMA unit for 82599
2246 **/
7b25cdba 2247static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
11afc1b1
PW		 2248{
2249#define IXGBE_MAX_SECRX_POLL 30
2250 int i;
2251 int secrxreg;
2252
2253 /*
2254 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2255 * If traffic is incoming before we enable the Rx unit, it could hang
2256 * the Rx DMA unit. Therefore, make sure the security engine is
2257 * completely disabled prior to enabling the Rx unit.
2258 */
2259 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2260 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2261 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2262 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2263 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2264 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2265 break;
2266 else
2267 udelay(10);
2268 }
2269
2270 /* For informational purposes only */
2271 if (i >= IXGBE_MAX_SECRX_POLL)
2272 hw_dbg(hw, "Rx unit being enabled before security "
2273 "path fully disabled. Continuing with init.\n");
2274
2275 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2276 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2277 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2278 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2279 IXGBE_WRITE_FLUSH(hw);
2280
2281 return 0;
2282}
2283
04193058
PWJ		 2284/**
2285 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2286 * @hw: pointer to hardware structure
2287 * @device_caps: the EEPROM word with the extra device capabilities
2288 *
2289 * This function will read the EEPROM location for the device capabilities,
2290 * and return the word through device_caps.
2291 **/
7b25cdba 2292static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
04193058
PWJ		 2293{
2294 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2295
2296 return 0;
2297}
2298
0365e6e4
PW		 2299/**
2300 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2301 * @hw: pointer to hardware structure
2302 * @san_mac_offset: SAN MAC address offset
2303 *
2304 * This function will read the EEPROM location for the SAN MAC address
2305 * pointer, and returns the value at that location. This is used in both
2306 * get and set mac_addr routines.
2307 **/
7b25cdba
DS		 2308static s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
2309 u16 *san_mac_offset)
0365e6e4
PW		 2310{
2311 /*
2312 * First read the EEPROM pointer to see if the MAC addresses are
2313 * available.
2314 */
2315 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2316
2317 return 0;
2318}
2319
2320/**
2321 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2322 * @hw: pointer to hardware structure
2323 * @san_mac_addr: SAN MAC address
2324 *
2325 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2326 * per-port, so set_lan_id() must be called before reading the addresses.
2327 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2328 * upon for non-SFP connections, so we must call it here.
2329 **/
7b25cdba 2330static s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
0365e6e4
PW		 2331{
2332 u16 san_mac_data, san_mac_offset;
2333 u8 i;
2334
2335 /*
2336 * First read the EEPROM pointer to see if the MAC addresses are
2337 * available. If they're not, no point in calling set_lan_id() here.
2338 */
2339 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2340
2341 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2342 /*
2343 * No addresses available in this EEPROM. It's not an
2344 * error though, so just wipe the local address and return.
2345 */
2346 for (i = 0; i < 6; i++)
2347 san_mac_addr[i] = 0xFF;
2348
2349 goto san_mac_addr_out;
2350 }
2351
2352 /* make sure we know which port we need to program */
2353 hw->mac.ops.set_lan_id(hw);
2354 /* apply the port offset to the address offset */
2355 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2356 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2357 for (i = 0; i < 3; i++) {
2358 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2359 san_mac_addr[i * 2] = (u8)(san_mac_data);
2360 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2361 san_mac_offset++;
2362 }
2363
2364san_mac_addr_out:
2365 return 0;
2366}
2367
794caeb2
PWJ		 2368/**
2369 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2370 * @hw: pointer to hardware structure
2371 *
2372 * Verifies that installed the firmware version is 0.6 or higher
2373 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2374 *
2375 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2376 * if the FW version is not supported.
2377 **/
2378static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2379{
2380 s32 status = IXGBE_ERR_EEPROM_VERSION;
2381 u16 fw_offset, fw_ptp_cfg_offset;
2382 u16 fw_version = 0;
2383
2384 /* firmware check is only necessary for SFI devices */
2385 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2386 status = 0;
2387 goto fw_version_out;
2388 }
2389
2390 /* get the offset to the Firmware Module block */
2391 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2392
2393 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2394 goto fw_version_out;
2395
2396 /* get the offset to the Pass Through Patch Configuration block */
2397 hw->eeprom.ops.read(hw, (fw_offset +
2398 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2399 &fw_ptp_cfg_offset);
2400
2401 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2402 goto fw_version_out;
2403
2404 /* get the firmware version */
2405 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2406 IXGBE_FW_PATCH_VERSION_4),
2407 &fw_version);
2408
2409 if (fw_version > 0x5)
2410 status = 0;
2411
2412fw_version_out:
2413 return status;
2414}
2415
11afc1b1
PW		 2416static struct ixgbe_mac_operations mac_ops_82599 = {
2417 .init_hw = &ixgbe_init_hw_generic,
2418 .reset_hw = &ixgbe_reset_hw_82599,
2419 .start_hw = &ixgbe_start_hw_82599,
2420 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2421 .get_media_type = &ixgbe_get_media_type_82599,
2422 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2423 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2424 .get_mac_addr = &ixgbe_get_mac_addr_generic,
0365e6e4 2425 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
04193058 2426 .get_device_caps = &ixgbe_get_device_caps_82599,
11afc1b1
PW		 2427 .stop_adapter = &ixgbe_stop_adapter_generic,
2428 .get_bus_info = &ixgbe_get_bus_info_generic,
2429 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2430 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2431 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2432 .setup_link = &ixgbe_setup_mac_link_82599,
11afc1b1
PW		 2433 .check_link = &ixgbe_check_mac_link_82599,
2434 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2435 .led_on = &ixgbe_led_on_generic,
2436 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 2437 .blink_led_start = &ixgbe_blink_led_start_generic,
2438 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 2439 .set_rar = &ixgbe_set_rar_generic,
2440 .clear_rar = &ixgbe_clear_rar_generic,
2441 .set_vmdq = &ixgbe_set_vmdq_82599,
2442 .clear_vmdq = &ixgbe_clear_vmdq_82599,
2443 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2444 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2445 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2446 .enable_mc = &ixgbe_enable_mc_generic,
2447 .disable_mc = &ixgbe_disable_mc_generic,
2448 .clear_vfta = &ixgbe_clear_vfta_82599,
2449 .set_vfta = &ixgbe_set_vfta_82599,
620fa036 2450 .fc_enable = &ixgbe_fc_enable_generic,
11afc1b1
PW		 2451 .init_uta_tables = &ixgbe_init_uta_tables_82599,
2452 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2453};
2454
2455static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2456 .init_params = &ixgbe_init_eeprom_params_generic,
2457 .read = &ixgbe_read_eeprom_generic,
2458 .write = &ixgbe_write_eeprom_generic,
2459 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2460 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2461};
2462
2463static struct ixgbe_phy_operations phy_ops_82599 = {
2464 .identify = &ixgbe_identify_phy_82599,
2465 .identify_sfp = &ixgbe_identify_sfp_module_generic,
04f165ef 2466 .init = &ixgbe_init_phy_ops_82599,
11afc1b1
PW		 2467 .reset = &ixgbe_reset_phy_generic,
2468 .read_reg = &ixgbe_read_phy_reg_generic,
2469 .write_reg = &ixgbe_write_phy_reg_generic,
2470 .setup_link = &ixgbe_setup_phy_link_generic,
2471 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2472 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2473 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2474 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2475 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2476};
2477
2478struct ixgbe_info ixgbe_82599_info = {
2479 .mac = ixgbe_mac_82599EB,
2480 .get_invariants = &ixgbe_get_invariants_82599,
2481 .mac_ops = &mac_ops_82599,
2482 .eeprom_ops = &eeprom_ops_82599,
2483 .phy_ops = &phy_ops_82599,
2484};
Linux kernel - Deliverables
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