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ixgbe: dcb, do not tag tc_prio_control frames
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
11afc1b1
PW		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
096a58fd 34#include "ixgbe_mbx.h"
11afc1b1
PW		 35
36#define IXGBE_82599_MAX_TX_QUEUES 128
37#define IXGBE_82599_MAX_RX_QUEUES 128
38#define IXGBE_82599_RAR_ENTRIES 128
39#define IXGBE_82599_MC_TBL_SIZE 128
40#define IXGBE_82599_VFT_TBL_SIZE 128
41
61fac744
PW		 42void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
43void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
1097cd17 44void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
8620a103
MC		 45s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
cd7e1f0b
DS		 49static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg,
52 bool autoneg_wait_to_complete);
8620a103
MC		 53s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed speed,
57 bool autoneg,
58 bool autoneg_wait_to_complete);
11afc1b1
PW		 59static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed *speed,
61 bool *autoneg);
8620a103
MC		 62static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
63 ixgbe_link_speed speed,
64 bool autoneg,
65 bool autoneg_wait_to_complete);
794caeb2 66static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
11afc1b1 67
7b25cdba 68static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 69{
70 struct ixgbe_mac_info *mac = &hw->mac;
71 if (hw->phy.multispeed_fiber) {
72 /* Set up dual speed SFP+ support */
8620a103 73 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
61fac744
PW		 74 mac->ops.disable_tx_laser =
75 &ixgbe_disable_tx_laser_multispeed_fiber;
76 mac->ops.enable_tx_laser =
77 &ixgbe_enable_tx_laser_multispeed_fiber;
1097cd17 78 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
11afc1b1 79 } else {
61fac744
PW		 80 mac->ops.disable_tx_laser = NULL;
81 mac->ops.enable_tx_laser = NULL;
1097cd17 82 mac->ops.flap_tx_laser = NULL;
cd7e1f0b
DS		 83 if ((mac->ops.get_media_type(hw) ==
84 ixgbe_media_type_backplane) &&
85 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
86 hw->phy.smart_speed == ixgbe_smart_speed_on))
87 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
88 else
89 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
11afc1b1
PW		 90 }
91}
92
7b25cdba 93static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 94{
95 s32 ret_val = 0;
96 u16 list_offset, data_offset, data_value;
97
98 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
99 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 100
101 hw->phy.ops.reset = NULL;
102
11afc1b1
PW		 103 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
104 &data_offset);
105
106 if (ret_val != 0)
107 goto setup_sfp_out;
108
aa5aec88
PWJ		 109 /* PHY config will finish before releasing the semaphore */
110 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
111 if (ret_val != 0) {
112 ret_val = IXGBE_ERR_SWFW_SYNC;
113 goto setup_sfp_out;
114 }
115
11afc1b1
PW		 116 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
117 while (data_value != 0xffff) {
118 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
119 IXGBE_WRITE_FLUSH(hw);
120 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
121 }
1479ad4f
PWJ		 122 /* Now restart DSP by setting Restart_AN */
123 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
124 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
aa5aec88
PWJ		 125
126 /* Release the semaphore */
127 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
128 /* Delay obtaining semaphore again to allow FW access */
129 msleep(hw->eeprom.semaphore_delay);
11afc1b1
PW		 130 }
131
132setup_sfp_out:
133 return ret_val;
134}
135
11afc1b1
PW		 136static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
137{
138 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 139
04f165ef 140 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 141
04f165ef
PW		 142 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
143 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
144 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
145 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
146 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
21ce849b 147 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
11afc1b1 148
04f165ef
PW		 149 return 0;
150}
11afc1b1 151
04f165ef
PW		 152/**
153 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
154 * @hw: pointer to hardware structure
155 *
156 * Initialize any function pointers that were not able to be
157 * set during get_invariants because the PHY/SFP type was
158 * not known. Perform the SFP init if necessary.
159 *
160 **/
7b25cdba 161static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
04f165ef
PW		 162{
163 struct ixgbe_mac_info *mac = &hw->mac;
164 struct ixgbe_phy_info *phy = &hw->phy;
165 s32 ret_val = 0;
11afc1b1 166
04f165ef
PW		 167 /* Identify the PHY or SFP module */
168 ret_val = phy->ops.identify(hw);
169
170 /* Setup function pointers based on detected SFP module and speeds */
171 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 172
173 /* If copper media, overwrite with copper function pointers */
174 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
175 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
11afc1b1
PW		 176 mac->ops.get_link_capabilities =
177 &ixgbe_get_copper_link_capabilities_82599;
178 }
179
04f165ef 180 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 181 switch (hw->phy.type) {
182 case ixgbe_phy_tn:
183 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
184 phy->ops.get_firmware_version =
04f165ef 185 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 186 break;
187 default:
188 break;
189 }
190
11afc1b1
PW		 191 return ret_val;
192}
193
194/**
195 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
196 * @hw: pointer to hardware structure
197 * @speed: pointer to link speed
198 * @negotiation: true when autoneg or autotry is enabled
199 *
200 * Determines the link capabilities by reading the AUTOC register.
201 **/
7b25cdba
DS		 202static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
203 ixgbe_link_speed *speed,
204 bool *negotiation)
11afc1b1
PW		 205{
206 s32 status = 0;
1eb99d5a 207 u32 autoc = 0;
11afc1b1 208
1eb99d5a
PW		 209 /*
210 * Determine link capabilities based on the stored value of AUTOC,
211 * which represents EEPROM defaults. If AUTOC value has not been
212 * stored, use the current register value.
213 */
214 if (hw->mac.orig_link_settings_stored)
215 autoc = hw->mac.orig_autoc;
216 else
217 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
218
219 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 220 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
221 *speed = IXGBE_LINK_SPEED_1GB_FULL;
222 *negotiation = false;
223 break;
224
225 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
226 *speed = IXGBE_LINK_SPEED_10GB_FULL;
227 *negotiation = false;
228 break;
229
230 case IXGBE_AUTOC_LMS_1G_AN:
231 *speed = IXGBE_LINK_SPEED_1GB_FULL;
232 *negotiation = true;
233 break;
234
235 case IXGBE_AUTOC_LMS_10G_SERIAL:
236 *speed = IXGBE_LINK_SPEED_10GB_FULL;
237 *negotiation = false;
238 break;
239
240 case IXGBE_AUTOC_LMS_KX4_KX_KR:
241 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
242 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 243 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 244 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 245 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 246 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 247 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 248 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
249 *negotiation = true;
250 break;
251
252 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
253 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 254 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 255 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 256 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 257 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 258 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 259 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
260 *negotiation = true;
261 break;
262
263 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
264 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
265 *negotiation = false;
266 break;
267
268 default:
269 status = IXGBE_ERR_LINK_SETUP;
270 goto out;
271 break;
272 }
273
274 if (hw->phy.multispeed_fiber) {
275 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
276 IXGBE_LINK_SPEED_1GB_FULL;
277 *negotiation = true;
278 }
279
280out:
281 return status;
282}
283
284/**
285 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
286 * @hw: pointer to hardware structure
287 * @speed: pointer to link speed
288 * @autoneg: boolean auto-negotiation value
289 *
290 * Determines the link capabilities by reading the AUTOC register.
291 **/
292static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
293 ixgbe_link_speed *speed,
294 bool *autoneg)
295{
296 s32 status = IXGBE_ERR_LINK_SETUP;
297 u16 speed_ability;
298
299 *speed = 0;
300 *autoneg = true;
301
6b73e10d 302 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
11afc1b1
PW		 303 &speed_ability);
304
305 if (status == 0) {
6b73e10d 306 if (speed_ability & MDIO_SPEED_10G)
11afc1b1 307 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
6b73e10d 308 if (speed_ability & MDIO_PMA_SPEED_1000)
11afc1b1
PW		 309 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
310 }
311
312 return status;
313}
314
315/**
316 * ixgbe_get_media_type_82599 - Get media type
317 * @hw: pointer to hardware structure
318 *
319 * Returns the media type (fiber, copper, backplane)
320 **/
7b25cdba 321static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 322{
323 enum ixgbe_media_type media_type;
324
325 /* Detect if there is a copper PHY attached. */
326 if (hw->phy.type == ixgbe_phy_cu_unknown ||
327 hw->phy.type == ixgbe_phy_tn) {
328 media_type = ixgbe_media_type_copper;
329 goto out;
330 }
331
332 switch (hw->device_id) {
11afc1b1 333 case IXGBE_DEV_ID_82599_KX4:
dbfec662 334 case IXGBE_DEV_ID_82599_KX4_MEZZ:
312eb931 335 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
74757d49 336 case IXGBE_DEV_ID_82599_KR:
1fcf03e6 337 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 338 /* Default device ID is mezzanine card KX/KX4 */
339 media_type = ixgbe_media_type_backplane;
340 break;
341 case IXGBE_DEV_ID_82599_SFP:
38ad1c8e 342 case IXGBE_DEV_ID_82599_SFP_EM:
11afc1b1
PW		 343 media_type = ixgbe_media_type_fiber;
344 break;
8911184f 345 case IXGBE_DEV_ID_82599_CX4:
6b1be199 346 media_type = ixgbe_media_type_cx4;
8911184f 347 break;
11afc1b1
PW		 348 default:
349 media_type = ixgbe_media_type_unknown;
350 break;
351 }
352out:
353 return media_type;
354}
355
356/**
8620a103 357 * ixgbe_start_mac_link_82599 - Setup MAC link settings
11afc1b1 358 * @hw: pointer to hardware structure
8620a103 359 * @autoneg_wait_to_complete: true when waiting for completion is needed
11afc1b1
PW		 360 *
361 * Configures link settings based on values in the ixgbe_hw struct.
362 * Restarts the link. Performs autonegotiation if needed.
363 **/
8620a103
MC		 364s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
365 bool autoneg_wait_to_complete)
11afc1b1
PW		 366{
367 u32 autoc_reg;
368 u32 links_reg;
369 u32 i;
370 s32 status = 0;
371
372 /* Restart link */
373 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
374 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
375 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
376
377 /* Only poll for autoneg to complete if specified to do so */
8620a103 378 if (autoneg_wait_to_complete) {
11afc1b1
PW		 379 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
380 IXGBE_AUTOC_LMS_KX4_KX_KR ||
381 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
382 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
383 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
384 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
385 links_reg = 0; /* Just in case Autoneg time = 0 */
386 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
387 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
388 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
389 break;
390 msleep(100);
391 }
392 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
393 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
394 hw_dbg(hw, "Autoneg did not complete.\n");
395 }
396 }
397 }
398
11afc1b1
PW		 399 /* Add delay to filter out noises during initial link setup */
400 msleep(50);
401
402 return status;
403}
404
61fac744
PW		 405 /**
406 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
407 * @hw: pointer to hardware structure
408 *
409 * The base drivers may require better control over SFP+ module
410 * PHY states. This includes selectively shutting down the Tx
411 * laser on the PHY, effectively halting physical link.
412 **/
413void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
414{
415 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
416
417 /* Disable tx laser; allow 100us to go dark per spec */
418 esdp_reg |= IXGBE_ESDP_SDP3;
419 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
420 IXGBE_WRITE_FLUSH(hw);
421 udelay(100);
422}
423
424/**
425 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
426 * @hw: pointer to hardware structure
427 *
428 * The base drivers may require better control over SFP+ module
429 * PHY states. This includes selectively turning on the Tx
430 * laser on the PHY, effectively starting physical link.
431 **/
432void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
433{
434 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
435
436 /* Enable tx laser; allow 100ms to light up */
437 esdp_reg &= ~IXGBE_ESDP_SDP3;
438 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
439 IXGBE_WRITE_FLUSH(hw);
440 msleep(100);
441}
442
1097cd17
MC		 443/**
444 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
445 * @hw: pointer to hardware structure
446 *
447 * When the driver changes the link speeds that it can support,
448 * it sets autotry_restart to true to indicate that we need to
449 * initiate a new autotry session with the link partner. To do
450 * so, we set the speed then disable and re-enable the tx laser, to
451 * alert the link partner that it also needs to restart autotry on its
452 * end. This is consistent with true clause 37 autoneg, which also
453 * involves a loss of signal.
454 **/
455void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
456{
1097cd17
MC		 457 hw_dbg(hw, "ixgbe_flap_tx_laser_multispeed_fiber\n");
458
459 if (hw->mac.autotry_restart) {
61fac744
PW		 460 ixgbe_disable_tx_laser_multispeed_fiber(hw);
461 ixgbe_enable_tx_laser_multispeed_fiber(hw);
1097cd17
MC		 462 hw->mac.autotry_restart = false;
463 }
464}
465
11afc1b1 466/**
8620a103 467 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
11afc1b1
PW		 468 * @hw: pointer to hardware structure
469 * @speed: new link speed
470 * @autoneg: true if autonegotiation enabled
471 * @autoneg_wait_to_complete: true when waiting for completion is needed
472 *
473 * Set the link speed in the AUTOC register and restarts link.
474 **/
8620a103
MC		 475s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
476 ixgbe_link_speed speed,
477 bool autoneg,
478 bool autoneg_wait_to_complete)
11afc1b1
PW		 479{
480 s32 status = 0;
481 ixgbe_link_speed phy_link_speed;
482 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
483 u32 speedcnt = 0;
484 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
485 bool link_up = false;
486 bool negotiation;
50ac58ba 487 int i;
11afc1b1
PW		 488
489 /* Mask off requested but non-supported speeds */
490 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
491 speed &= phy_link_speed;
492
493 /*
494 * Try each speed one by one, highest priority first. We do this in
495 * software because 10gb fiber doesn't support speed autonegotiation.
496 */
497 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
498 speedcnt++;
499 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
500
50ac58ba
PWJ		 501 /* If we already have link at this speed, just jump out */
502 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
503
504 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
505 goto out;
506
507 /* Set the module link speed */
11afc1b1
PW		 508 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
509 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
1097cd17 510 IXGBE_WRITE_FLUSH(hw);
11afc1b1 511
50ac58ba
PWJ		 512 /* Allow module to change analog characteristics (1G->10G) */
513 msleep(40);
11afc1b1 514
8620a103
MC		 515 status = ixgbe_setup_mac_link_82599(hw,
516 IXGBE_LINK_SPEED_10GB_FULL,
517 autoneg,
518 autoneg_wait_to_complete);
50ac58ba 519 if (status != 0)
c3c74327 520 return status;
50ac58ba
PWJ		 521
522 /* Flap the tx laser if it has not already been done */
1097cd17 523 hw->mac.ops.flap_tx_laser(hw);
50ac58ba 524
cd7e1f0b
DS		 525 /*
526 * Wait for the controller to acquire link. Per IEEE 802.3ap,
527 * Section 73.10.2, we may have to wait up to 500ms if KR is
528 * attempted. 82599 uses the same timing for 10g SFI.
529 */
530
50ac58ba
PWJ		 531 for (i = 0; i < 5; i++) {
532 /* Wait for the link partner to also set speed */
533 msleep(100);
534
535 /* If we have link, just jump out */
536 hw->mac.ops.check_link(hw, &phy_link_speed,
537 &link_up, false);
538 if (link_up)
539 goto out;
540 }
11afc1b1
PW		 541 }
542
543 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
544 speedcnt++;
545 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
546 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
547
50ac58ba
PWJ		 548 /* If we already have link at this speed, just jump out */
549 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
550
551 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
552 goto out;
553
554 /* Set the module link speed */
11afc1b1
PW		 555 esdp_reg &= ~IXGBE_ESDP_SDP5;
556 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
557 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
1097cd17 558 IXGBE_WRITE_FLUSH(hw);
11afc1b1 559
50ac58ba
PWJ		 560 /* Allow module to change analog characteristics (10G->1G) */
561 msleep(40);
11afc1b1 562
8620a103 563 status = ixgbe_setup_mac_link_82599(hw,
50ac58ba
PWJ		 564 IXGBE_LINK_SPEED_1GB_FULL,
565 autoneg,
566 autoneg_wait_to_complete);
567 if (status != 0)
c3c74327 568 return status;
50ac58ba
PWJ		 569
570 /* Flap the tx laser if it has not already been done */
1097cd17 571 hw->mac.ops.flap_tx_laser(hw);
50ac58ba
PWJ		 572
573 /* Wait for the link partner to also set speed */
574 msleep(100);
11afc1b1
PW		 575
576 /* If we have link, just jump out */
577 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
578 if (link_up)
579 goto out;
580 }
581
582 /*
583 * We didn't get link. Configure back to the highest speed we tried,
584 * (if there was more than one). We call ourselves back with just the
585 * single highest speed that the user requested.
586 */
587 if (speedcnt > 1)
8620a103
MC		 588 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
589 highest_link_speed,
590 autoneg,
591 autoneg_wait_to_complete);
11afc1b1
PW		 592
593out:
c3c74327
MC		 594 /* Set autoneg_advertised value based on input link speed */
595 hw->phy.autoneg_advertised = 0;
596
597 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
598 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
599
600 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
601 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
602
11afc1b1
PW		 603 return status;
604}
605
cd7e1f0b
DS		 606/**
607 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
608 * @hw: pointer to hardware structure
609 * @speed: new link speed
610 * @autoneg: true if autonegotiation enabled
611 * @autoneg_wait_to_complete: true when waiting for completion is needed
612 *
613 * Implements the Intel SmartSpeed algorithm.
614 **/
615static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
616 ixgbe_link_speed speed, bool autoneg,
617 bool autoneg_wait_to_complete)
618{
619 s32 status = 0;
620 ixgbe_link_speed link_speed;
621 s32 i, j;
622 bool link_up = false;
623 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
c4ee6a53 624 struct ixgbe_adapter *adapter = hw->back;
cd7e1f0b
DS		 625
626 hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n");
627
628 /* Set autoneg_advertised value based on input link speed */
629 hw->phy.autoneg_advertised = 0;
630
631 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
632 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
633
634 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
635 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
636
637 if (speed & IXGBE_LINK_SPEED_100_FULL)
638 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
639
640 /*
641 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
642 * autoneg advertisement if link is unable to be established at the
643 * highest negotiated rate. This can sometimes happen due to integrity
644 * issues with the physical media connection.
645 */
646
647 /* First, try to get link with full advertisement */
648 hw->phy.smart_speed_active = false;
649 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
650 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
651 autoneg_wait_to_complete);
652 if (status)
653 goto out;
654
655 /*
656 * Wait for the controller to acquire link. Per IEEE 802.3ap,
657 * Section 73.10.2, we may have to wait up to 500ms if KR is
658 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
659 * Table 9 in the AN MAS.
660 */
661 for (i = 0; i < 5; i++) {
662 mdelay(100);
663
664 /* If we have link, just jump out */
665 hw->mac.ops.check_link(hw, &link_speed,
666 &link_up, false);
667 if (link_up)
668 goto out;
669 }
670 }
671
672 /*
673 * We didn't get link. If we advertised KR plus one of KX4/KX
674 * (or BX4/BX), then disable KR and try again.
675 */
676 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
677 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
678 goto out;
679
680 /* Turn SmartSpeed on to disable KR support */
681 hw->phy.smart_speed_active = true;
682 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
683 autoneg_wait_to_complete);
684 if (status)
685 goto out;
686
687 /*
688 * Wait for the controller to acquire link. 600ms will allow for
689 * the AN link_fail_inhibit_timer as well for multiple cycles of
690 * parallel detect, both 10g and 1g. This allows for the maximum
691 * connect attempts as defined in the AN MAS table 73-7.
692 */
693 for (i = 0; i < 6; i++) {
694 mdelay(100);
695
696 /* If we have link, just jump out */
697 hw->mac.ops.check_link(hw, &link_speed,
698 &link_up, false);
699 if (link_up)
700 goto out;
701 }
702
703 /* We didn't get link. Turn SmartSpeed back off. */
704 hw->phy.smart_speed_active = false;
705 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
706 autoneg_wait_to_complete);
707
708out:
c4ee6a53
AS		 709 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
710 netif_info(adapter, hw, adapter->netdev, "Smartspeed has"
711 " downgraded the link speed from the maximum"
712 " advertised\n");
cd7e1f0b
DS		 713 return status;
714}
715
11afc1b1 716/**
8620a103 717 * ixgbe_setup_mac_link_82599 - Set MAC link speed
11afc1b1
PW		 718 * @hw: pointer to hardware structure
719 * @speed: new link speed
720 * @autoneg: true if autonegotiation enabled
721 * @autoneg_wait_to_complete: true when waiting for completion is needed
722 *
723 * Set the link speed in the AUTOC register and restarts link.
724 **/
8620a103
MC		 725s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
726 ixgbe_link_speed speed, bool autoneg,
727 bool autoneg_wait_to_complete)
11afc1b1
PW		 728{
729 s32 status = 0;
730 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
731 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
50ac58ba 732 u32 start_autoc = autoc;
1eb99d5a 733 u32 orig_autoc = 0;
11afc1b1
PW		 734 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
735 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
736 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
737 u32 links_reg;
738 u32 i;
739 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
740
741 /* Check to see if speed passed in is supported. */
742 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
743 speed &= link_capabilities;
744
50ac58ba
PWJ		 745 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
746 status = IXGBE_ERR_LINK_SETUP;
747 goto out;
748 }
749
1eb99d5a
PW		 750 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
751 if (hw->mac.orig_link_settings_stored)
752 orig_autoc = hw->mac.orig_autoc;
753 else
754 orig_autoc = autoc;
755
756
50ac58ba
PWJ		 757 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
758 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
759 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
11afc1b1
PW		 760 /* Set KX4/KX/KR support according to speed requested */
761 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
762 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 763 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 764 autoc |= IXGBE_AUTOC_KX4_SUPP;
cd7e1f0b
DS		 765 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
766 (hw->phy.smart_speed_active == false))
11afc1b1
PW		 767 autoc |= IXGBE_AUTOC_KR_SUPP;
768 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
769 autoc |= IXGBE_AUTOC_KX_SUPP;
770 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
771 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
772 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
773 /* Switch from 1G SFI to 10G SFI if requested */
774 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
775 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
776 autoc &= ~IXGBE_AUTOC_LMS_MASK;
777 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
778 }
779 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
780 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
781 /* Switch from 10G SFI to 1G SFI if requested */
782 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
783 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
784 autoc &= ~IXGBE_AUTOC_LMS_MASK;
785 if (autoneg)
786 autoc |= IXGBE_AUTOC_LMS_1G_AN;
787 else
788 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
789 }
790 }
791
50ac58ba 792 if (autoc != start_autoc) {
11afc1b1
PW		 793 /* Restart link */
794 autoc |= IXGBE_AUTOC_AN_RESTART;
795 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
796
797 /* Only poll for autoneg to complete if specified to do so */
798 if (autoneg_wait_to_complete) {
799 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
800 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
801 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
802 links_reg = 0; /*Just in case Autoneg time=0*/
803 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
804 links_reg =
805 IXGBE_READ_REG(hw, IXGBE_LINKS);
806 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
807 break;
808 msleep(100);
809 }
810 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
811 status =
812 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
813 hw_dbg(hw, "Autoneg did not "
814 "complete.\n");
815 }
816 }
817 }
818
11afc1b1
PW		 819 /* Add delay to filter out noises during initial link setup */
820 msleep(50);
821 }
822
50ac58ba 823out:
11afc1b1
PW		 824 return status;
825}
826
827/**
8620a103 828 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
11afc1b1
PW		 829 * @hw: pointer to hardware structure
830 * @speed: new link speed
831 * @autoneg: true if autonegotiation enabled
832 * @autoneg_wait_to_complete: true if waiting is needed to complete
833 *
834 * Restarts link on PHY and MAC based on settings passed in.
835 **/
8620a103
MC		 836static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
837 ixgbe_link_speed speed,
838 bool autoneg,
839 bool autoneg_wait_to_complete)
11afc1b1
PW		 840{
841 s32 status;
842
843 /* Setup the PHY according to input speed */
844 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
845 autoneg_wait_to_complete);
846 /* Set up MAC */
8620a103 847 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
11afc1b1
PW		 848
849 return status;
850}
851
852/**
853 * ixgbe_reset_hw_82599 - Perform hardware reset
854 * @hw: pointer to hardware structure
855 *
856 * Resets the hardware by resetting the transmit and receive units, masks
857 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
858 * reset.
859 **/
7b25cdba 860static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 861{
862 s32 status = 0;
c9205697 863 u32 ctrl;
11afc1b1
PW		 864 u32 i;
865 u32 autoc;
866 u32 autoc2;
867
868 /* Call adapter stop to disable tx/rx and clear interrupts */
869 hw->mac.ops.stop_adapter(hw);
870
553b4497 871 /* PHY ops must be identified and initialized prior to reset */
04f165ef 872
553b4497
PW		 873 /* Init PHY and function pointers, perform SFP setup */
874 status = hw->phy.ops.init(hw);
04f165ef 875
553b4497
PW		 876 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
877 goto reset_hw_out;
04f165ef 878
553b4497
PW		 879 /* Setup SFP module if there is one present. */
880 if (hw->phy.sfp_setup_needed) {
881 status = hw->mac.ops.setup_sfp(hw);
882 hw->phy.sfp_setup_needed = false;
04f165ef 883 }
11afc1b1 884
553b4497
PW		 885 /* Reset PHY */
886 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
887 hw->phy.ops.reset(hw);
888
11afc1b1
PW		 889 /*
890 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
891 * access and verify no pending requests before reset
892 */
04f165ef
PW		 893 status = ixgbe_disable_pcie_master(hw);
894 if (status != 0) {
11afc1b1
PW		 895 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
896 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
897 }
898
899 /*
900 * Issue global reset to the MAC. This needs to be a SW reset.
901 * If link reset is used, it might reset the MAC when mng is using it
902 */
903 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
904 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
905 IXGBE_WRITE_FLUSH(hw);
906
907 /* Poll for reset bit to self-clear indicating reset is complete */
908 for (i = 0; i < 10; i++) {
909 udelay(1);
910 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
911 if (!(ctrl & IXGBE_CTRL_RST))
912 break;
913 }
914 if (ctrl & IXGBE_CTRL_RST) {
915 status = IXGBE_ERR_RESET_FAILED;
916 hw_dbg(hw, "Reset polling failed to complete.\n");
917 }
11afc1b1
PW		 918
919 msleep(50);
920
11afc1b1
PW		 921 /*
922 * Store the original AUTOC/AUTOC2 values if they have not been
923 * stored off yet. Otherwise restore the stored original
924 * values since the reset operation sets back to defaults.
925 */
926 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
927 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
928 if (hw->mac.orig_link_settings_stored == false) {
929 hw->mac.orig_autoc = autoc;
930 hw->mac.orig_autoc2 = autoc2;
931 hw->mac.orig_link_settings_stored = true;
4df10466 932 } else {
11afc1b1
PW		 933 if (autoc != hw->mac.orig_autoc)
934 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
935 IXGBE_AUTOC_AN_RESTART));
936
937 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
938 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
939 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
940 autoc2 |= (hw->mac.orig_autoc2 &
941 IXGBE_AUTOC2_UPPER_MASK);
942 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
943 }
944 }
945
aca6bee7
WJP		 946 /*
947 * Store MAC address from RAR0, clear receive address registers, and
948 * clear the multicast table. Also reset num_rar_entries to 128,
949 * since we modify this value when programming the SAN MAC address.
950 */
951 hw->mac.num_rar_entries = 128;
952 hw->mac.ops.init_rx_addrs(hw);
953
11afc1b1
PW		 954 /* Store the permanent mac address */
955 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
956
0365e6e4
PW		 957 /* Store the permanent SAN mac address */
958 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
959
aca6bee7
WJP		 960 /* Add the SAN MAC address to the RAR only if it's a valid address */
961 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
962 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
963 hw->mac.san_addr, 0, IXGBE_RAH_AV);
964
965 /* Reserve the last RAR for the SAN MAC address */
966 hw->mac.num_rar_entries--;
967 }
968
383ff34b
YZ		 969 /* Store the alternative WWNN/WWPN prefix */
970 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
971 &hw->mac.wwpn_prefix);
972
04f165ef 973reset_hw_out:
11afc1b1
PW		 974 return status;
975}
976
ffff4772
PWJ		 977/**
978 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
979 * @hw: pointer to hardware structure
980 **/
981s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
982{
983 int i;
984 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
985 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
986
987 /*
988 * Before starting reinitialization process,
989 * FDIRCMD.CMD must be zero.
990 */
991 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
992 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
993 IXGBE_FDIRCMD_CMD_MASK))
994 break;
995 udelay(10);
996 }
997 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
998 hw_dbg(hw ,"Flow Director previous command isn't complete, "
d6dbee86 999 "aborting table re-initialization.\n");
ffff4772
PWJ		 1000 return IXGBE_ERR_FDIR_REINIT_FAILED;
1001 }
1002
1003 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1004 IXGBE_WRITE_FLUSH(hw);
1005 /*
1006 * 82599 adapters flow director init flow cannot be restarted,
1007 * Workaround 82599 silicon errata by performing the following steps
1008 * before re-writing the FDIRCTRL control register with the same value.
1009 * - write 1 to bit 8 of FDIRCMD register &
1010 * - write 0 to bit 8 of FDIRCMD register
1011 */
1012 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1013 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1014 IXGBE_FDIRCMD_CLEARHT));
1015 IXGBE_WRITE_FLUSH(hw);
1016 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1017 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1018 ~IXGBE_FDIRCMD_CLEARHT));
1019 IXGBE_WRITE_FLUSH(hw);
1020 /*
1021 * Clear FDIR Hash register to clear any leftover hashes
1022 * waiting to be programmed.
1023 */
1024 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1025 IXGBE_WRITE_FLUSH(hw);
1026
1027 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1028 IXGBE_WRITE_FLUSH(hw);
1029
1030 /* Poll init-done after we write FDIRCTRL register */
1031 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1032 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1033 IXGBE_FDIRCTRL_INIT_DONE)
1034 break;
1035 udelay(10);
1036 }
1037 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1038 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1039 return IXGBE_ERR_FDIR_REINIT_FAILED;
1040 }
1041
1042 /* Clear FDIR statistics registers (read to clear) */
1043 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1044 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1045 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1046 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1047 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1048
1049 return 0;
1050}
1051
1052/**
1053 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1054 * @hw: pointer to hardware structure
1055 * @pballoc: which mode to allocate filters with
1056 **/
1057s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1058{
1059 u32 fdirctrl = 0;
1060 u32 pbsize;
1061 int i;
1062
1063 /*
1064 * Before enabling Flow Director, the Rx Packet Buffer size
1065 * must be reduced. The new value is the current size minus
1066 * flow director memory usage size.
1067 */
1068 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1069 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1070 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1071
1072 /*
1073 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1074 * intialized to zero for non DCB mode otherwise actual total RX PB
1075 * would be bigger than programmed and filter space would run into
1076 * the PB 0 region.
1077 */
1078 for (i = 1; i < 8; i++)
1079 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1080
1081 /* Send interrupt when 64 filters are left */
1082 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1083
1084 /* Set the maximum length per hash bucket to 0xA filters */
1085 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1086
1087 switch (pballoc) {
1088 case IXGBE_FDIR_PBALLOC_64K:
1089 /* 8k - 1 signature filters */
1090 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1091 break;
1092 case IXGBE_FDIR_PBALLOC_128K:
1093 /* 16k - 1 signature filters */
1094 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1095 break;
1096 case IXGBE_FDIR_PBALLOC_256K:
1097 /* 32k - 1 signature filters */
1098 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1099 break;
1100 default:
1101 /* bad value */
1102 return IXGBE_ERR_CONFIG;
1103 };
1104
1105 /* Move the flexible bytes to use the ethertype - shift 6 words */
1106 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1107
1108 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1109
1110 /* Prime the keys for hashing */
1111 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1112 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1113 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1114 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1115
1116 /*
1117 * Poll init-done after we write the register. Estimated times:
1118 * 10G: PBALLOC = 11b, timing is 60us
1119 * 1G: PBALLOC = 11b, timing is 600us
1120 * 100M: PBALLOC = 11b, timing is 6ms
1121 *
1122 * Multiple these timings by 4 if under full Rx load
1123 *
1124 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1125 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1126 * this might not finish in our poll time, but we can live with that
1127 * for now.
1128 */
1129 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1130 IXGBE_WRITE_FLUSH(hw);
1131 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1132 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1133 IXGBE_FDIRCTRL_INIT_DONE)
1134 break;
1135 msleep(1);
1136 }
1137 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1138 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1139
1140 return 0;
1141}
1142
1143/**
1144 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1145 * @hw: pointer to hardware structure
1146 * @pballoc: which mode to allocate filters with
1147 **/
1148s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1149{
1150 u32 fdirctrl = 0;
1151 u32 pbsize;
1152 int i;
1153
1154 /*
1155 * Before enabling Flow Director, the Rx Packet Buffer size
1156 * must be reduced. The new value is the current size minus
1157 * flow director memory usage size.
1158 */
1159 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1160 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1161 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1162
1163 /*
1164 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1165 * intialized to zero for non DCB mode otherwise actual total RX PB
1166 * would be bigger than programmed and filter space would run into
1167 * the PB 0 region.
1168 */
1169 for (i = 1; i < 8; i++)
1170 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1171
1172 /* Send interrupt when 64 filters are left */
1173 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1174
9a713e7c
PW		 1175 /* Initialize the drop queue to Rx queue 127 */
1176 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1177
ffff4772
PWJ		 1178 switch (pballoc) {
1179 case IXGBE_FDIR_PBALLOC_64K:
1180 /* 2k - 1 perfect filters */
1181 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1182 break;
1183 case IXGBE_FDIR_PBALLOC_128K:
1184 /* 4k - 1 perfect filters */
1185 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1186 break;
1187 case IXGBE_FDIR_PBALLOC_256K:
1188 /* 8k - 1 perfect filters */
1189 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1190 break;
1191 default:
1192 /* bad value */
1193 return IXGBE_ERR_CONFIG;
1194 };
1195
1196 /* Turn perfect match filtering on */
1197 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1198 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1199
1200 /* Move the flexible bytes to use the ethertype - shift 6 words */
1201 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1202
1203 /* Prime the keys for hashing */
1204 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1205 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1206 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1207 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1208
1209 /*
1210 * Poll init-done after we write the register. Estimated times:
1211 * 10G: PBALLOC = 11b, timing is 60us
1212 * 1G: PBALLOC = 11b, timing is 600us
1213 * 100M: PBALLOC = 11b, timing is 6ms
1214 *
1215 * Multiple these timings by 4 if under full Rx load
1216 *
1217 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1218 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1219 * this might not finish in our poll time, but we can live with that
1220 * for now.
1221 */
1222
1223 /* Set the maximum length per hash bucket to 0xA filters */
1224 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1225
1226 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1227 IXGBE_WRITE_FLUSH(hw);
1228 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1229 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1230 IXGBE_FDIRCTRL_INIT_DONE)
1231 break;
1232 msleep(1);
1233 }
1234 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1235 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1236
1237 return 0;
1238}
1239
1240
1241/**
1242 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1243 * @stream: input bitstream to compute the hash on
1244 * @key: 32-bit hash key
1245 **/
7b25cdba
DS		 1246static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1247 u32 key)
ffff4772
PWJ		 1248{
1249 /*
1250 * The algorithm is as follows:
1251 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1252 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1253 * and A[n] x B[n] is bitwise AND between same length strings
1254 *
1255 * K[n] is 16 bits, defined as:
1256 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1257 * for n modulo 32 < 15, K[n] =
1258 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1259 *
1260 * S[n] is 16 bits, defined as:
1261 * for n >= 15, S[n] = S[n:n - 15]
1262 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1263 *
1264 * To simplify for programming, the algorithm is implemented
1265 * in software this way:
1266 *
1267 * Key[31:0], Stream[335:0]
1268 *
1269 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1270 * int_key[350:0] = tmp_key[351:1]
1271 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1272 *
1273 * hash[15:0] = 0;
1274 * for (i = 0; i < 351; i++) {
1275 * if (int_key[i])
1276 * hash ^= int_stream[(i + 15):i];
1277 * }
1278 */
1279
1280 union {
1281 u64 fill[6];
1282 u32 key[11];
1283 u8 key_stream[44];
1284 } tmp_key;
1285
1286 u8 *stream = (u8 *)atr_input;
1287 u8 int_key[44]; /* upper-most bit unused */
1288 u8 hash_str[46]; /* upper-most 2 bits unused */
1289 u16 hash_result = 0;
1290 int i, j, k, h;
1291
1292 /*
1293 * Initialize the fill member to prevent warnings
1294 * on some compilers
1295 */
1296 tmp_key.fill[0] = 0;
1297
1298 /* First load the temporary key stream */
1299 for (i = 0; i < 6; i++) {
1300 u64 fillkey = ((u64)key << 32) | key;
1301 tmp_key.fill[i] = fillkey;
1302 }
1303
1304 /*
1305 * Set the interim key for the hashing. Bit 352 is unused, so we must
1306 * shift and compensate when building the key.
1307 */
1308
1309 int_key[0] = tmp_key.key_stream[0] >> 1;
1310 for (i = 1, j = 0; i < 44; i++) {
1311 unsigned int this_key = tmp_key.key_stream[j] << 7;
1312 j++;
1313 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1314 }
1315
1316 /*
1317 * Set the interim bit string for the hashing. Bits 368 and 367 are
1318 * unused, so shift and compensate when building the string.
1319 */
1320 hash_str[0] = (stream[40] & 0x7f) >> 1;
1321 for (i = 1, j = 40; i < 46; i++) {
1322 unsigned int this_str = stream[j] << 7;
1323 j++;
1324 if (j > 41)
1325 j = 0;
1326 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1327 }
1328
1329 /*
1330 * Now compute the hash. i is the index into hash_str, j is into our
1331 * key stream, k is counting the number of bits, and h interates within
1332 * each byte.
1333 */
1334 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1335 for (h = 0; h < 8 && k < 351; h++, k++) {
1336 if (int_key[j] & (1 << h)) {
1337 /*
1338 * Key bit is set, XOR in the current 16-bit
1339 * string. Example of processing:
1340 * h = 0,
1341 * tmp = (hash_str[i - 2] & 0 << 16) |
1342 * (hash_str[i - 1] & 0xff << 8) |
1343 * (hash_str[i] & 0xff >> 0)
1344 * So tmp = hash_str[15 + k:k], since the
1345 * i + 2 clause rolls off the 16-bit value
1346 * h = 7,
1347 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1348 * (hash_str[i - 1] & 0xff << 1) |
1349 * (hash_str[i] & 0x80 >> 7)
1350 */
1351 int tmp = (hash_str[i] >> h);
1352 tmp |= (hash_str[i - 1] << (8 - h));
1353 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1354 << (16 - h);
1355 hash_result ^= (u16)tmp;
1356 }
1357 }
1358 }
1359
1360 return hash_result;
1361}
1362
1363/**
1364 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1365 * @input: input stream to modify
1366 * @vlan: the VLAN id to load
1367 **/
1368s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1369{
1370 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1371 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1372
1373 return 0;
1374}
1375
1376/**
1377 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1378 * @input: input stream to modify
1379 * @src_addr: the IP address to load
1380 **/
1381s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1382{
1383 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1384 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1385 (src_addr >> 16) & 0xff;
1386 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1387 (src_addr >> 8) & 0xff;
1388 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1389
1390 return 0;
1391}
1392
1393/**
1394 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1395 * @input: input stream to modify
1396 * @dst_addr: the IP address to load
1397 **/
1398s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1399{
1400 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1401 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1402 (dst_addr >> 16) & 0xff;
1403 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1404 (dst_addr >> 8) & 0xff;
1405 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1406
1407 return 0;
1408}
1409
1410/**
1411 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1412 * @input: input stream to modify
1413 * @src_addr_1: the first 4 bytes of the IP address to load
1414 * @src_addr_2: the second 4 bytes of the IP address to load
1415 * @src_addr_3: the third 4 bytes of the IP address to load
1416 * @src_addr_4: the fourth 4 bytes of the IP address to load
1417 **/
1418s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
9a713e7c
PW		 1419 u32 src_addr_1, u32 src_addr_2,
1420 u32 src_addr_3, u32 src_addr_4)
ffff4772
PWJ		 1421{
1422 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1423 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1424 (src_addr_4 >> 8) & 0xff;
1425 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1426 (src_addr_4 >> 16) & 0xff;
1427 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1428
1429 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1430 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1431 (src_addr_3 >> 8) & 0xff;
1432 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1433 (src_addr_3 >> 16) & 0xff;
1434 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1435
1436 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1437 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1438 (src_addr_2 >> 8) & 0xff;
1439 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1440 (src_addr_2 >> 16) & 0xff;
1441 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1442
1443 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1444 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1445 (src_addr_1 >> 8) & 0xff;
1446 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1447 (src_addr_1 >> 16) & 0xff;
1448 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1449
1450 return 0;
1451}
1452
1453/**
1454 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1455 * @input: input stream to modify
1456 * @dst_addr_1: the first 4 bytes of the IP address to load
1457 * @dst_addr_2: the second 4 bytes of the IP address to load
1458 * @dst_addr_3: the third 4 bytes of the IP address to load
1459 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1460 **/
1461s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
9a713e7c
PW		 1462 u32 dst_addr_1, u32 dst_addr_2,
1463 u32 dst_addr_3, u32 dst_addr_4)
ffff4772
PWJ		 1464{
1465 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1466 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1467 (dst_addr_4 >> 8) & 0xff;
1468 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1469 (dst_addr_4 >> 16) & 0xff;
1470 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1471
1472 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1473 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1474 (dst_addr_3 >> 8) & 0xff;
1475 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1476 (dst_addr_3 >> 16) & 0xff;
1477 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1478
1479 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1480 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1481 (dst_addr_2 >> 8) & 0xff;
1482 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1483 (dst_addr_2 >> 16) & 0xff;
1484 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1485
1486 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1487 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1488 (dst_addr_1 >> 8) & 0xff;
1489 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1490 (dst_addr_1 >> 16) & 0xff;
1491 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1492
1493 return 0;
1494}
1495
1496/**
1497 * ixgbe_atr_set_src_port_82599 - Sets the source port
1498 * @input: input stream to modify
1499 * @src_port: the source port to load
1500 **/
1501s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1502{
1503 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1504 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1505
1506 return 0;
1507}
1508
1509/**
1510 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1511 * @input: input stream to modify
1512 * @dst_port: the destination port to load
1513 **/
1514s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1515{
1516 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1517 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1518
1519 return 0;
1520}
1521
1522/**
1523 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1524 * @input: input stream to modify
1525 * @flex_bytes: the flexible bytes to load
1526 **/
1527s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1528{
1529 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1530 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1531
1532 return 0;
1533}
1534
1535/**
1536 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1537 * @input: input stream to modify
1538 * @vm_pool: the Virtual Machine pool to load
1539 **/
7b25cdba 1540s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
9a713e7c 1541 u8 vm_pool)
ffff4772
PWJ		 1542{
1543 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1544
1545 return 0;
1546}
1547
1548/**
1549 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1550 * @input: input stream to modify
1551 * @l4type: the layer 4 type value to load
1552 **/
1553s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1554{
1555 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1556
1557 return 0;
1558}
1559
1560/**
1561 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1562 * @input: input stream to search
1563 * @vlan: the VLAN id to load
1564 **/
9a713e7c 1565static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
ffff4772
PWJ		 1566{
1567 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1568 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1569
1570 return 0;
1571}
1572
1573/**
1574 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1575 * @input: input stream to search
1576 * @src_addr: the IP address to load
1577 **/
7b25cdba
DS		 1578static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1579 u32 *src_addr)
ffff4772
PWJ		 1580{
1581 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1582 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1583 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1584 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1585
1586 return 0;
1587}
1588
1589/**
1590 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1591 * @input: input stream to search
1592 * @dst_addr: the IP address to load
1593 **/
7b25cdba
DS		 1594static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1595 u32 *dst_addr)
ffff4772
PWJ		 1596{
1597 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1598 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1599 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1600 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1601
1602 return 0;
1603}
1604
1605/**
1606 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1607 * @input: input stream to search
1608 * @src_addr_1: the first 4 bytes of the IP address to load
1609 * @src_addr_2: the second 4 bytes of the IP address to load
1610 * @src_addr_3: the third 4 bytes of the IP address to load
1611 * @src_addr_4: the fourth 4 bytes of the IP address to load
1612 **/
7b25cdba
DS		 1613static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1614 u32 *src_addr_1, u32 *src_addr_2,
1615 u32 *src_addr_3, u32 *src_addr_4)
ffff4772
PWJ		 1616{
1617 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1618 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1619 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1620 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1621
1622 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1623 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1624 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1625 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1626
1627 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1628 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1629 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1630 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1631
1632 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1633 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1634 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1635 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1636
1637 return 0;
1638}
1639
1640/**
1641 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1642 * @input: input stream to search
1643 * @dst_addr_1: the first 4 bytes of the IP address to load
1644 * @dst_addr_2: the second 4 bytes of the IP address to load
1645 * @dst_addr_3: the third 4 bytes of the IP address to load
1646 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1647 **/
1648s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1649 u32 *dst_addr_1, u32 *dst_addr_2,
1650 u32 *dst_addr_3, u32 *dst_addr_4)
ffff4772
PWJ		 1651{
1652 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1653 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1654 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1655 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1656
1657 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1658 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1659 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1660 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1661
1662 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1663 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1664 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1665 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1666
1667 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1668 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1669 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1670 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1671
1672 return 0;
1673}
1674
1675/**
1676 * ixgbe_atr_get_src_port_82599 - Gets the source port
1677 * @input: input stream to modify
1678 * @src_port: the source port to load
1679 *
1680 * Even though the input is given in big-endian, the FDIRPORT registers
1681 * expect the ports to be programmed in little-endian. Hence the need to swap
1682 * endianness when retrieving the data. This can be confusing since the
1683 * internal hash engine expects it to be big-endian.
1684 **/
7b25cdba
DS		 1685static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1686 u16 *src_port)
ffff4772
PWJ		 1687{
1688 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1689 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1690
1691 return 0;
1692}
1693
1694/**
1695 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1696 * @input: input stream to modify
1697 * @dst_port: the destination port to load
1698 *
1699 * Even though the input is given in big-endian, the FDIRPORT registers
1700 * expect the ports to be programmed in little-endian. Hence the need to swap
1701 * endianness when retrieving the data. This can be confusing since the
1702 * internal hash engine expects it to be big-endian.
1703 **/
7b25cdba
DS		 1704static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1705 u16 *dst_port)
ffff4772
PWJ		 1706{
1707 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1708 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1709
1710 return 0;
1711}
1712
1713/**
1714 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1715 * @input: input stream to modify
1716 * @flex_bytes: the flexible bytes to load
1717 **/
7b25cdba
DS		 1718static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1719 u16 *flex_byte)
ffff4772
PWJ		 1720{
1721 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1722 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1723
1724 return 0;
1725}
1726
1727/**
1728 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
1729 * @input: input stream to modify
1730 * @vm_pool: the Virtual Machine pool to load
1731 **/
7b25cdba
DS		 1732s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
1733 u8 *vm_pool)
ffff4772
PWJ		 1734{
1735 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
1736
1737 return 0;
1738}
1739
1740/**
1741 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1742 * @input: input stream to modify
1743 * @l4type: the layer 4 type value to load
1744 **/
7b25cdba
DS		 1745static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
1746 u8 *l4type)
ffff4772
PWJ		 1747{
1748 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
1749
1750 return 0;
1751}
1752
1753/**
1754 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1755 * @hw: pointer to hardware structure
1756 * @stream: input bitstream
1757 * @queue: queue index to direct traffic to
1758 **/
1759s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1760 struct ixgbe_atr_input *input,
1761 u8 queue)
1762{
1763 u64 fdirhashcmd;
1764 u64 fdircmd;
1765 u32 fdirhash;
1766 u16 bucket_hash, sig_hash;
1767 u8 l4type;
1768
1769 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1770 IXGBE_ATR_BUCKET_HASH_KEY);
1771
1772 /* bucket_hash is only 15 bits */
1773 bucket_hash &= IXGBE_ATR_HASH_MASK;
1774
1775 sig_hash = ixgbe_atr_compute_hash_82599(input,
1776 IXGBE_ATR_SIGNATURE_HASH_KEY);
1777
1778 /* Get the l4type in order to program FDIRCMD properly */
1779 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1780 ixgbe_atr_get_l4type_82599(input, &l4type);
1781
1782 /*
1783 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1784 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1785 */
1786 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1787
1788 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1789 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
1790
1791 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1792 case IXGBE_ATR_L4TYPE_TCP:
1793 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1794 break;
1795 case IXGBE_ATR_L4TYPE_UDP:
1796 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1797 break;
1798 case IXGBE_ATR_L4TYPE_SCTP:
1799 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1800 break;
1801 default:
1802 hw_dbg(hw, "Error on l4type input\n");
1803 return IXGBE_ERR_CONFIG;
1804 }
1805
1806 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
1807 fdircmd |= IXGBE_FDIRCMD_IPV6;
1808
1809 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
1810 fdirhashcmd = ((fdircmd << 32) | fdirhash);
1811
1812 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1813
1814 return 0;
1815}
1816
1817/**
1818 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1819 * @hw: pointer to hardware structure
1820 * @input: input bitstream
9a713e7c
PW		 1821 * @input_masks: bitwise masks for relevant fields
1822 * @soft_id: software index into the silicon hash tables for filter storage
ffff4772
PWJ		 1823 * @queue: queue index to direct traffic to
1824 *
1825 * Note that the caller to this function must lock before calling, since the
1826 * hardware writes must be protected from one another.
1827 **/
1828s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
9a713e7c
PW		 1829 struct ixgbe_atr_input *input,
1830 struct ixgbe_atr_input_masks *input_masks,
1831 u16 soft_id, u8 queue)
ffff4772
PWJ		 1832{
1833 u32 fdircmd = 0;
1834 u32 fdirhash;
9a713e7c 1835 u32 src_ipv4 = 0, dst_ipv4 = 0;
ffff4772
PWJ		 1836 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
1837 u16 src_port, dst_port, vlan_id, flex_bytes;
1838 u16 bucket_hash;
1839 u8 l4type;
9a713e7c 1840 u8 fdirm = 0;
ffff4772
PWJ		 1841
1842 /* Get our input values */
1843 ixgbe_atr_get_l4type_82599(input, &l4type);
1844
1845 /*
1846 * Check l4type formatting, and bail out before we touch the hardware
1847 * if there's a configuration issue
1848 */
1849 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1850 case IXGBE_ATR_L4TYPE_TCP:
1851 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1852 break;
1853 case IXGBE_ATR_L4TYPE_UDP:
1854 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1855 break;
1856 case IXGBE_ATR_L4TYPE_SCTP:
1857 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1858 break;
1859 default:
1860 hw_dbg(hw, "Error on l4type input\n");
1861 return IXGBE_ERR_CONFIG;
1862 }
1863
1864 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1865 IXGBE_ATR_BUCKET_HASH_KEY);
1866
1867 /* bucket_hash is only 15 bits */
1868 bucket_hash &= IXGBE_ATR_HASH_MASK;
1869
1870 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
1871 ixgbe_atr_get_src_port_82599(input, &src_port);
1872 ixgbe_atr_get_dst_port_82599(input, &dst_port);
1873 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
1874
1875 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1876
1877 /* Now figure out if we're IPv4 or IPv6 */
1878 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
1879 /* IPv6 */
1880 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
1881 &src_ipv6_3, &src_ipv6_4);
1882
1883 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
1884 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
1885 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
1886 /* The last 4 bytes is the same register as IPv4 */
1887 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
1888
1889 fdircmd |= IXGBE_FDIRCMD_IPV6;
1890 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
1891 } else {
1892 /* IPv4 */
1893 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
1894 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
ffff4772
PWJ		 1895 }
1896
1897 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
1898 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
1899
1900 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
1901 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
1902 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
9a713e7c
PW		 1903 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
1904
1905 /*
1906 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1907 * are zero, then assume a full mask for that field. Also assume that
1908 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1909 * cannot be masked out in this implementation.
1910 *
1911 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1912 * point in time.
1913 */
1914 if (src_ipv4 == 0)
1915 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xffffffff);
1916 else
1917 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
1918
1919 if (dst_ipv4 == 0)
1920 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xffffffff);
1921 else
1922 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
1923
1924 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1925 case IXGBE_ATR_L4TYPE_TCP:
1926 if (src_port == 0)
1927 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xffff);
1928 else
1929 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1930 input_masks->src_port_mask);
1931
1932 if (dst_port == 0)
1933 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1934 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
1935 (0xffff << 16)));
1936 else
1937 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1938 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
1939 (input_masks->dst_port_mask << 16)));
1940 break;
1941 case IXGBE_ATR_L4TYPE_UDP:
1942 if (src_port == 0)
1943 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xffff);
1944 else
1945 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1946 input_masks->src_port_mask);
1947
1948 if (dst_port == 0)
1949 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1950 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
1951 (0xffff << 16)));
1952 else
1953 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1954 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
1955 (input_masks->src_port_mask << 16)));
1956 break;
1957 default:
1958 /* this already would have failed above */
1959 break;
1960 }
1961
1962 /* Program the last mask register, FDIRM */
1963 if (input_masks->vlan_id_mask || !vlan_id)
1964 /* Mask both VLAN and VLANP - bits 0 and 1 */
1965 fdirm |= 0x3;
1966
1967 if (input_masks->data_mask || !flex_bytes)
1968 /* Flex bytes need masking, so mask the whole thing - bit 4 */
1969 fdirm |= 0x10;
1970
1971 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1972 fdirm |= 0x24;
1973
1974 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
ffff4772
PWJ		 1975
1976 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
1977 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
1978 fdircmd |= IXGBE_FDIRCMD_LAST;
1979 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
1980 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1981
1982 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1983 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1984
1985 return 0;
1986}
11afc1b1
PW		 1987/**
1988 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1989 * @hw: pointer to hardware structure
1990 * @reg: analog register to read
1991 * @val: read value
1992 *
1993 * Performs read operation to Omer analog register specified.
1994 **/
7b25cdba 1995static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
11afc1b1
PW		 1996{
1997 u32 core_ctl;
1998
1999 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2000 (reg << 8));
2001 IXGBE_WRITE_FLUSH(hw);
2002 udelay(10);
2003 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2004 *val = (u8)core_ctl;
2005
2006 return 0;
2007}
2008
2009/**
2010 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2011 * @hw: pointer to hardware structure
2012 * @reg: atlas register to write
2013 * @val: value to write
2014 *
2015 * Performs write operation to Omer analog register specified.
2016 **/
7b25cdba 2017static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
11afc1b1
PW		 2018{
2019 u32 core_ctl;
2020
2021 core_ctl = (reg << 8) | val;
2022 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2023 IXGBE_WRITE_FLUSH(hw);
2024 udelay(10);
2025
2026 return 0;
2027}
2028
2029/**
2030 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2031 * @hw: pointer to hardware structure
2032 *
2033 * Starts the hardware using the generic start_hw function.
2034 * Then performs device-specific:
2035 * Clears the rate limiter registers.
2036 **/
7b25cdba 2037static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2038{
2039 u32 q_num;
794caeb2 2040 s32 ret_val;
11afc1b1 2041
794caeb2 2042 ret_val = ixgbe_start_hw_generic(hw);
11afc1b1
PW		 2043
2044 /* Clear the rate limiters */
2045 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2046 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2047 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2048 }
2049 IXGBE_WRITE_FLUSH(hw);
2050
50ac58ba
PWJ		 2051 /* We need to run link autotry after the driver loads */
2052 hw->mac.autotry_restart = true;
2053
794caeb2
PWJ		 2054 if (ret_val == 0)
2055 ret_val = ixgbe_verify_fw_version_82599(hw);
2056
2057 return ret_val;
11afc1b1
PW		 2058}
2059
2060/**
2061 * ixgbe_identify_phy_82599 - Get physical layer module
2062 * @hw: pointer to hardware structure
2063 *
2064 * Determines the physical layer module found on the current adapter.
2065 **/
7b25cdba 2066static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2067{
2068 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2069 status = ixgbe_identify_phy_generic(hw);
2070 if (status != 0)
2071 status = ixgbe_identify_sfp_module_generic(hw);
2072 return status;
2073}
2074
2075/**
2076 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2077 * @hw: pointer to hardware structure
2078 *
2079 * Determines physical layer capabilities of the current configuration.
2080 **/
7b25cdba 2081static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2082{
2083 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 2084 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2085 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2086 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2087 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2088 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2089 u16 ext_ability = 0;
1339b9e9 2090 u8 comp_codes_10g = 0;
11afc1b1 2091
04193058
PWJ		 2092 hw->phy.ops.identify(hw);
2093
2094 if (hw->phy.type == ixgbe_phy_tn ||
2095 hw->phy.type == ixgbe_phy_cu_unknown) {
6b73e10d
BH		 2096 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2097 &ext_ability);
2098 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 2099 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 2100 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 2101 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 2102 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 2103 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2104 goto out;
2105 }
2106
2107 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2108 case IXGBE_AUTOC_LMS_1G_AN:
2109 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2110 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2111 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2112 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2113 goto out;
2114 } else
2115 /* SFI mode so read SFP module */
2116 goto sfp_check;
11afc1b1 2117 break;
04193058
PWJ		 2118 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2119 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2120 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2121 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2122 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 2123 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2124 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 2125 goto out;
2126 break;
2127 case IXGBE_AUTOC_LMS_10G_SERIAL:
2128 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2129 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2130 goto out;
2131 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2132 goto sfp_check;
2133 break;
2134 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2135 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2136 if (autoc & IXGBE_AUTOC_KX_SUPP)
2137 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2138 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2139 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2140 if (autoc & IXGBE_AUTOC_KR_SUPP)
2141 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2142 goto out;
2143 break;
2144 default:
2145 goto out;
2146 break;
2147 }
11afc1b1 2148
04193058
PWJ		 2149sfp_check:
2150 /* SFP check must be done last since DA modules are sometimes used to
2151 * test KR mode - we need to id KR mode correctly before SFP module.
2152 * Call identify_sfp because the pluggable module may have changed */
2153 hw->phy.ops.identify_sfp(hw);
2154 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2155 goto out;
2156
2157 switch (hw->phy.type) {
2158 case ixgbe_phy_tw_tyco:
2159 case ixgbe_phy_tw_unknown:
2160 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2161 break;
2162 case ixgbe_phy_sfp_avago:
2163 case ixgbe_phy_sfp_ftl:
2164 case ixgbe_phy_sfp_intel:
2165 case ixgbe_phy_sfp_unknown:
2166 hw->phy.ops.read_i2c_eeprom(hw,
2167 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2168 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 2169 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 2170 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 2171 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
11afc1b1
PW		 2172 break;
2173 default:
11afc1b1
PW		 2174 break;
2175 }
2176
04193058 2177out:
11afc1b1
PW		 2178 return physical_layer;
2179}
2180
2181/**
2182 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2183 * @hw: pointer to hardware structure
2184 * @regval: register value to write to RXCTRL
2185 *
2186 * Enables the Rx DMA unit for 82599
2187 **/
7b25cdba 2188static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
11afc1b1
PW		 2189{
2190#define IXGBE_MAX_SECRX_POLL 30
2191 int i;
2192 int secrxreg;
2193
2194 /*
2195 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2196 * If traffic is incoming before we enable the Rx unit, it could hang
2197 * the Rx DMA unit. Therefore, make sure the security engine is
2198 * completely disabled prior to enabling the Rx unit.
2199 */
2200 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2201 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2202 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2203 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2204 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2205 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2206 break;
2207 else
2208 udelay(10);
2209 }
2210
2211 /* For informational purposes only */
2212 if (i >= IXGBE_MAX_SECRX_POLL)
2213 hw_dbg(hw, "Rx unit being enabled before security "
2214 "path fully disabled. Continuing with init.\n");
2215
2216 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2217 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2218 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2219 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2220 IXGBE_WRITE_FLUSH(hw);
2221
2222 return 0;
2223}
2224
04193058
PWJ		 2225/**
2226 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2227 * @hw: pointer to hardware structure
2228 * @device_caps: the EEPROM word with the extra device capabilities
2229 *
2230 * This function will read the EEPROM location for the device capabilities,
2231 * and return the word through device_caps.
2232 **/
7b25cdba 2233static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
04193058
PWJ		 2234{
2235 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2236
2237 return 0;
2238}
2239
794caeb2
PWJ		 2240/**
2241 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2242 * @hw: pointer to hardware structure
2243 *
2244 * Verifies that installed the firmware version is 0.6 or higher
2245 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2246 *
2247 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2248 * if the FW version is not supported.
2249 **/
2250static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2251{
2252 s32 status = IXGBE_ERR_EEPROM_VERSION;
2253 u16 fw_offset, fw_ptp_cfg_offset;
2254 u16 fw_version = 0;
2255
2256 /* firmware check is only necessary for SFI devices */
2257 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2258 status = 0;
2259 goto fw_version_out;
2260 }
2261
2262 /* get the offset to the Firmware Module block */
2263 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2264
2265 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2266 goto fw_version_out;
2267
2268 /* get the offset to the Pass Through Patch Configuration block */
2269 hw->eeprom.ops.read(hw, (fw_offset +
2270 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2271 &fw_ptp_cfg_offset);
2272
2273 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2274 goto fw_version_out;
2275
2276 /* get the firmware version */
2277 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2278 IXGBE_FW_PATCH_VERSION_4),
2279 &fw_version);
2280
2281 if (fw_version > 0x5)
2282 status = 0;
2283
2284fw_version_out:
2285 return status;
2286}
2287
383ff34b
YZ		 2288/**
2289 * ixgbe_get_wwn_prefix_82599 - Get alternative WWNN/WWPN prefix from
2290 * the EEPROM
2291 * @hw: pointer to hardware structure
2292 * @wwnn_prefix: the alternative WWNN prefix
2293 * @wwpn_prefix: the alternative WWPN prefix
2294 *
2295 * This function will read the EEPROM from the alternative SAN MAC address
2296 * block to check the support for the alternative WWNN/WWPN prefix support.
2297 **/
2298static s32 ixgbe_get_wwn_prefix_82599(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2299 u16 *wwpn_prefix)
2300{
2301 u16 offset, caps;
2302 u16 alt_san_mac_blk_offset;
2303
2304 /* clear output first */
2305 *wwnn_prefix = 0xFFFF;
2306 *wwpn_prefix = 0xFFFF;
2307
2308 /* check if alternative SAN MAC is supported */
2309 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2310 &alt_san_mac_blk_offset);
2311
2312 if ((alt_san_mac_blk_offset == 0) ||
2313 (alt_san_mac_blk_offset == 0xFFFF))
2314 goto wwn_prefix_out;
2315
2316 /* check capability in alternative san mac address block */
2317 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2318 hw->eeprom.ops.read(hw, offset, &caps);
2319 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2320 goto wwn_prefix_out;
2321
2322 /* get the corresponding prefix for WWNN/WWPN */
2323 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2324 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2325
2326 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2327 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2328
2329wwn_prefix_out:
2330 return 0;
2331}
2332
11afc1b1
PW		 2333static struct ixgbe_mac_operations mac_ops_82599 = {
2334 .init_hw = &ixgbe_init_hw_generic,
2335 .reset_hw = &ixgbe_reset_hw_82599,
2336 .start_hw = &ixgbe_start_hw_82599,
2337 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2338 .get_media_type = &ixgbe_get_media_type_82599,
2339 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2340 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2341 .get_mac_addr = &ixgbe_get_mac_addr_generic,
21ce849b 2342 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
04193058 2343 .get_device_caps = &ixgbe_get_device_caps_82599,
383ff34b 2344 .get_wwn_prefix = &ixgbe_get_wwn_prefix_82599,
11afc1b1
PW		 2345 .stop_adapter = &ixgbe_stop_adapter_generic,
2346 .get_bus_info = &ixgbe_get_bus_info_generic,
2347 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2348 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2349 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2350 .setup_link = &ixgbe_setup_mac_link_82599,
21ce849b 2351 .check_link = &ixgbe_check_mac_link_generic,
11afc1b1
PW		 2352 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2353 .led_on = &ixgbe_led_on_generic,
2354 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 2355 .blink_led_start = &ixgbe_blink_led_start_generic,
2356 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 2357 .set_rar = &ixgbe_set_rar_generic,
2358 .clear_rar = &ixgbe_clear_rar_generic,
21ce849b
MC		 2359 .set_vmdq = &ixgbe_set_vmdq_generic,
2360 .clear_vmdq = &ixgbe_clear_vmdq_generic,
11afc1b1
PW		 2361 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2362 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2363 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2364 .enable_mc = &ixgbe_enable_mc_generic,
2365 .disable_mc = &ixgbe_disable_mc_generic,
21ce849b
MC		 2366 .clear_vfta = &ixgbe_clear_vfta_generic,
2367 .set_vfta = &ixgbe_set_vfta_generic,
2368 .fc_enable = &ixgbe_fc_enable_generic,
2369 .init_uta_tables = &ixgbe_init_uta_tables_generic,
11afc1b1
PW		 2370 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2371};
2372
2373static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2374 .init_params = &ixgbe_init_eeprom_params_generic,
21ce849b 2375 .read = &ixgbe_read_eerd_generic,
11afc1b1
PW		 2376 .write = &ixgbe_write_eeprom_generic,
2377 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2378 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2379};
2380
2381static struct ixgbe_phy_operations phy_ops_82599 = {
2382 .identify = &ixgbe_identify_phy_82599,
2383 .identify_sfp = &ixgbe_identify_sfp_module_generic,
21ce849b 2384 .init = &ixgbe_init_phy_ops_82599,
11afc1b1
PW		 2385 .reset = &ixgbe_reset_phy_generic,
2386 .read_reg = &ixgbe_read_phy_reg_generic,
2387 .write_reg = &ixgbe_write_phy_reg_generic,
2388 .setup_link = &ixgbe_setup_phy_link_generic,
2389 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2390 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2391 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2392 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2393 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2394};
2395
2396struct ixgbe_info ixgbe_82599_info = {
2397 .mac = ixgbe_mac_82599EB,
2398 .get_invariants = &ixgbe_get_invariants_82599,
2399 .mac_ops = &mac_ops_82599,
2400 .eeprom_ops = &eeprom_ops_82599,
2401 .phy_ops = &phy_ops_82599,
096a58fd 2402 .mbx_ops = &mbx_ops_82599,
11afc1b1 2403};
Linux kernel - Deliverables
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