projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgbe: Enable ACPI WoL capabilities for 82599
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
34
35#define IXGBE_82599_MAX_TX_QUEUES 128
36#define IXGBE_82599_MAX_RX_QUEUES 128
37#define IXGBE_82599_RAR_ENTRIES 128
38#define IXGBE_82599_MC_TBL_SIZE 128
39#define IXGBE_82599_VFT_TBL_SIZE 128
40
41s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
45s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
46s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed, bool autoneg,
48 bool autoneg_wait_to_complete);
49s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
50s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
51 ixgbe_link_speed *speed,
52 bool *link_up, bool link_up_wait_to_complete);
53s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
54 ixgbe_link_speed speed,
55 bool autoneg,
56 bool autoneg_wait_to_complete);
57static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
58 ixgbe_link_speed *speed,
59 bool *autoneg);
60static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
61static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
62 ixgbe_link_speed speed,
63 bool autoneg,
64 bool autoneg_wait_to_complete);
65s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
66s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
67s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
68s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan,
69 u32 vind, bool vlan_on);
70s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw);
11afc1b1
PW		 71s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw);
72s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
73s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
74s32 ixgbe_start_hw_rev_0_82599(struct ixgbe_hw *hw);
75s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
76s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
77u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
78
79void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
80{
81 struct ixgbe_mac_info *mac = &hw->mac;
82 if (hw->phy.multispeed_fiber) {
83 /* Set up dual speed SFP+ support */
84 mac->ops.setup_link =
85 &ixgbe_setup_mac_link_multispeed_fiber;
86 mac->ops.setup_link_speed =
87 &ixgbe_setup_mac_link_speed_multispeed_fiber;
88 } else {
89 mac->ops.setup_link =
90 &ixgbe_setup_mac_link_82599;
91 mac->ops.setup_link_speed =
92 &ixgbe_setup_mac_link_speed_82599;
93 }
94}
95
96s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
97{
98 s32 ret_val = 0;
99 u16 list_offset, data_offset, data_value;
100
101 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
102 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 103
104 hw->phy.ops.reset = NULL;
105
11afc1b1
PW		 106 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
107 &data_offset);
108
109 if (ret_val != 0)
110 goto setup_sfp_out;
111
aa5aec88
PWJ		 112 /* PHY config will finish before releasing the semaphore */
113 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
114 if (ret_val != 0) {
115 ret_val = IXGBE_ERR_SWFW_SYNC;
116 goto setup_sfp_out;
117 }
118
11afc1b1
PW		 119 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
120 while (data_value != 0xffff) {
121 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
122 IXGBE_WRITE_FLUSH(hw);
123 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
124 }
125 /* Now restart DSP */
126 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000102);
127 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000b1d);
128 IXGBE_WRITE_FLUSH(hw);
aa5aec88
PWJ		 129
130 /* Release the semaphore */
131 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
132 /* Delay obtaining semaphore again to allow FW access */
133 msleep(hw->eeprom.semaphore_delay);
11afc1b1
PW		 134 }
135
136setup_sfp_out:
137 return ret_val;
138}
139
140/**
141 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
142 * @hw: pointer to hardware structure
143 *
144 * Read PCIe configuration space, and get the MSI-X vector count from
145 * the capabilities table.
146 **/
147u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
148{
149 struct ixgbe_adapter *adapter = hw->back;
150 u16 msix_count;
151 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
152 &msix_count);
153 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
154
155 /* MSI-X count is zero-based in HW, so increment to give proper value */
156 msix_count++;
157
158 return msix_count;
159}
160
161static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
162{
163 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 164
04f165ef 165 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 166
04f165ef
PW		 167 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
168 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
169 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
170 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
171 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
172 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
11afc1b1 173
04f165ef
PW		 174 return 0;
175}
11afc1b1 176
04f165ef
PW		 177/**
178 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
179 * @hw: pointer to hardware structure
180 *
181 * Initialize any function pointers that were not able to be
182 * set during get_invariants because the PHY/SFP type was
183 * not known. Perform the SFP init if necessary.
184 *
185 **/
186s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
187{
188 struct ixgbe_mac_info *mac = &hw->mac;
189 struct ixgbe_phy_info *phy = &hw->phy;
190 s32 ret_val = 0;
11afc1b1 191
04f165ef
PW		 192 /* Identify the PHY or SFP module */
193 ret_val = phy->ops.identify(hw);
194
195 /* Setup function pointers based on detected SFP module and speeds */
196 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 197
198 /* If copper media, overwrite with copper function pointers */
199 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
200 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
201 mac->ops.setup_link_speed =
04f165ef 202 &ixgbe_setup_copper_link_speed_82599;
11afc1b1
PW		 203 mac->ops.get_link_capabilities =
204 &ixgbe_get_copper_link_capabilities_82599;
205 }
206
04f165ef 207 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 208 switch (hw->phy.type) {
209 case ixgbe_phy_tn:
210 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
211 phy->ops.get_firmware_version =
04f165ef 212 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 213 break;
214 default:
215 break;
216 }
217
11afc1b1
PW		 218 return ret_val;
219}
220
221/**
222 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
223 * @hw: pointer to hardware structure
224 * @speed: pointer to link speed
225 * @negotiation: true when autoneg or autotry is enabled
226 *
227 * Determines the link capabilities by reading the AUTOC register.
228 **/
229s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
230 ixgbe_link_speed *speed,
231 bool *negotiation)
232{
233 s32 status = 0;
1eb99d5a 234 u32 autoc = 0;
11afc1b1 235
1eb99d5a
PW		 236 /*
237 * Determine link capabilities based on the stored value of AUTOC,
238 * which represents EEPROM defaults. If AUTOC value has not been
239 * stored, use the current register value.
240 */
241 if (hw->mac.orig_link_settings_stored)
242 autoc = hw->mac.orig_autoc;
243 else
244 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
245
246 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 247 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
248 *speed = IXGBE_LINK_SPEED_1GB_FULL;
249 *negotiation = false;
250 break;
251
252 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
253 *speed = IXGBE_LINK_SPEED_10GB_FULL;
254 *negotiation = false;
255 break;
256
257 case IXGBE_AUTOC_LMS_1G_AN:
258 *speed = IXGBE_LINK_SPEED_1GB_FULL;
259 *negotiation = true;
260 break;
261
262 case IXGBE_AUTOC_LMS_10G_SERIAL:
263 *speed = IXGBE_LINK_SPEED_10GB_FULL;
264 *negotiation = false;
265 break;
266
267 case IXGBE_AUTOC_LMS_KX4_KX_KR:
268 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
269 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 270 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 271 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 272 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 273 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 274 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 275 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
276 *negotiation = true;
277 break;
278
279 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
280 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 281 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 282 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 283 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 284 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 285 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 286 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
287 *negotiation = true;
288 break;
289
290 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
291 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
292 *negotiation = false;
293 break;
294
295 default:
296 status = IXGBE_ERR_LINK_SETUP;
297 goto out;
298 break;
299 }
300
301 if (hw->phy.multispeed_fiber) {
302 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
303 IXGBE_LINK_SPEED_1GB_FULL;
304 *negotiation = true;
305 }
306
307out:
308 return status;
309}
310
311/**
312 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
313 * @hw: pointer to hardware structure
314 * @speed: pointer to link speed
315 * @autoneg: boolean auto-negotiation value
316 *
317 * Determines the link capabilities by reading the AUTOC register.
318 **/
319static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
320 ixgbe_link_speed *speed,
321 bool *autoneg)
322{
323 s32 status = IXGBE_ERR_LINK_SETUP;
324 u16 speed_ability;
325
326 *speed = 0;
327 *autoneg = true;
328
6b73e10d 329 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
11afc1b1
PW		 330 &speed_ability);
331
332 if (status == 0) {
6b73e10d 333 if (speed_ability & MDIO_SPEED_10G)
11afc1b1 334 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
6b73e10d 335 if (speed_ability & MDIO_PMA_SPEED_1000)
11afc1b1
PW		 336 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
337 }
338
339 return status;
340}
341
342/**
343 * ixgbe_get_media_type_82599 - Get media type
344 * @hw: pointer to hardware structure
345 *
346 * Returns the media type (fiber, copper, backplane)
347 **/
348enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
349{
350 enum ixgbe_media_type media_type;
351
352 /* Detect if there is a copper PHY attached. */
353 if (hw->phy.type == ixgbe_phy_cu_unknown ||
354 hw->phy.type == ixgbe_phy_tn) {
355 media_type = ixgbe_media_type_copper;
356 goto out;
357 }
358
359 switch (hw->device_id) {
11afc1b1 360 case IXGBE_DEV_ID_82599_KX4:
1fcf03e6 361 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 362 /* Default device ID is mezzanine card KX/KX4 */
363 media_type = ixgbe_media_type_backplane;
364 break;
365 case IXGBE_DEV_ID_82599_SFP:
366 media_type = ixgbe_media_type_fiber;
367 break;
368 default:
369 media_type = ixgbe_media_type_unknown;
370 break;
371 }
372out:
373 return media_type;
374}
375
376/**
377 * ixgbe_setup_mac_link_82599 - Setup MAC link settings
378 * @hw: pointer to hardware structure
379 *
380 * Configures link settings based on values in the ixgbe_hw struct.
381 * Restarts the link. Performs autonegotiation if needed.
382 **/
383s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
384{
385 u32 autoc_reg;
386 u32 links_reg;
387 u32 i;
388 s32 status = 0;
389
390 /* Restart link */
391 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
392 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
393 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
394
395 /* Only poll for autoneg to complete if specified to do so */
396 if (hw->phy.autoneg_wait_to_complete) {
397 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
398 IXGBE_AUTOC_LMS_KX4_KX_KR ||
399 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
400 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
401 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
402 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
403 links_reg = 0; /* Just in case Autoneg time = 0 */
404 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
405 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
406 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
407 break;
408 msleep(100);
409 }
410 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
411 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
412 hw_dbg(hw, "Autoneg did not complete.\n");
413 }
414 }
415 }
416
417 /* Set up flow control */
418 status = ixgbe_setup_fc_generic(hw, 0);
419
420 /* Add delay to filter out noises during initial link setup */
421 msleep(50);
422
423 return status;
424}
425
426/**
427 * ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
428 * @hw: pointer to hardware structure
429 *
430 * Configures link settings based on values in the ixgbe_hw struct.
431 * Restarts the link for multi-speed fiber at 1G speed, if link
432 * fails at 10G.
433 * Performs autonegotiation if needed.
434 **/
435s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
436{
437 s32 status = 0;
438 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
4df10466 439 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, link_speed,
11afc1b1
PW		 440 true, true);
441 return status;
442}
443
444/**
445 * ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
446 * @hw: pointer to hardware structure
447 * @speed: new link speed
448 * @autoneg: true if autonegotiation enabled
449 * @autoneg_wait_to_complete: true when waiting for completion is needed
450 *
451 * Set the link speed in the AUTOC register and restarts link.
452 **/
453s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
454 ixgbe_link_speed speed,
455 bool autoneg,
456 bool autoneg_wait_to_complete)
457{
458 s32 status = 0;
459 ixgbe_link_speed phy_link_speed;
460 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
461 u32 speedcnt = 0;
462 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
463 bool link_up = false;
464 bool negotiation;
465
466 /* Mask off requested but non-supported speeds */
467 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
468 speed &= phy_link_speed;
469
470 /*
471 * Try each speed one by one, highest priority first. We do this in
472 * software because 10gb fiber doesn't support speed autonegotiation.
473 */
474 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
475 speedcnt++;
476 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
477
478 /* Set hardware SDP's */
479 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
480 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
481
482 ixgbe_setup_mac_link_speed_82599(hw,
483 IXGBE_LINK_SPEED_10GB_FULL,
484 autoneg,
485 autoneg_wait_to_complete);
486
487 msleep(50);
488
489 /* If we have link, just jump out */
490 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
491 if (link_up)
492 goto out;
493 }
494
495 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
496 speedcnt++;
497 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
498 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
499
500 /* Set hardware SDP's */
501 esdp_reg &= ~IXGBE_ESDP_SDP5;
502 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
503 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
504
505 ixgbe_setup_mac_link_speed_82599(
506 hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg,
507 autoneg_wait_to_complete);
508
509 msleep(50);
510
511 /* If we have link, just jump out */
512 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
513 if (link_up)
514 goto out;
515 }
516
517 /*
518 * We didn't get link. Configure back to the highest speed we tried,
519 * (if there was more than one). We call ourselves back with just the
520 * single highest speed that the user requested.
521 */
522 if (speedcnt > 1)
523 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
524 highest_link_speed,
525 autoneg,
526 autoneg_wait_to_complete);
527
528out:
529 return status;
530}
531
532/**
533 * ixgbe_check_mac_link_82599 - Determine link and speed status
534 * @hw: pointer to hardware structure
535 * @speed: pointer to link speed
536 * @link_up: true when link is up
537 * @link_up_wait_to_complete: bool used to wait for link up or not
538 *
539 * Reads the links register to determine if link is up and the current speed
540 **/
541s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
542 bool *link_up, bool link_up_wait_to_complete)
543{
544 u32 links_reg;
545 u32 i;
546
547 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
548 if (link_up_wait_to_complete) {
549 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
550 if (links_reg & IXGBE_LINKS_UP) {
551 *link_up = true;
552 break;
553 } else {
554 *link_up = false;
555 }
556 msleep(100);
557 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
558 }
559 } else {
560 if (links_reg & IXGBE_LINKS_UP)
561 *link_up = true;
562 else
563 *link_up = false;
564 }
565
566 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
567 IXGBE_LINKS_SPEED_10G_82599)
568 *speed = IXGBE_LINK_SPEED_10GB_FULL;
569 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
570 IXGBE_LINKS_SPEED_1G_82599)
571 *speed = IXGBE_LINK_SPEED_1GB_FULL;
572 else
573 *speed = IXGBE_LINK_SPEED_100_FULL;
574
575
576 return 0;
577}
578
579/**
580 * ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
581 * @hw: pointer to hardware structure
582 * @speed: new link speed
583 * @autoneg: true if autonegotiation enabled
584 * @autoneg_wait_to_complete: true when waiting for completion is needed
585 *
586 * Set the link speed in the AUTOC register and restarts link.
587 **/
588s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
589 ixgbe_link_speed speed, bool autoneg,
590 bool autoneg_wait_to_complete)
591{
592 s32 status = 0;
593 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
594 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1eb99d5a 595 u32 orig_autoc = 0;
11afc1b1
PW		 596 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
597 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
598 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
599 u32 links_reg;
600 u32 i;
601 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
602
603 /* Check to see if speed passed in is supported. */
604 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
605 speed &= link_capabilities;
606
1eb99d5a
PW		 607 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
608 if (hw->mac.orig_link_settings_stored)
609 orig_autoc = hw->mac.orig_autoc;
610 else
611 orig_autoc = autoc;
612
613
11afc1b1
PW		 614 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
615 status = IXGBE_ERR_LINK_SETUP;
616 } else if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
617 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
618 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
619 /* Set KX4/KX/KR support according to speed requested */
620 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
621 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 622 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 623 autoc |= IXGBE_AUTOC_KX4_SUPP;
1eb99d5a 624 if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1
PW		 625 autoc |= IXGBE_AUTOC_KR_SUPP;
626 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
627 autoc |= IXGBE_AUTOC_KX_SUPP;
628 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
629 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
630 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
631 /* Switch from 1G SFI to 10G SFI if requested */
632 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
633 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
634 autoc &= ~IXGBE_AUTOC_LMS_MASK;
635 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
636 }
637 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
638 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
639 /* Switch from 10G SFI to 1G SFI if requested */
640 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
641 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
642 autoc &= ~IXGBE_AUTOC_LMS_MASK;
643 if (autoneg)
644 autoc |= IXGBE_AUTOC_LMS_1G_AN;
645 else
646 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
647 }
648 }
649
650 if (status == 0) {
651 /* Restart link */
652 autoc |= IXGBE_AUTOC_AN_RESTART;
653 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
654
655 /* Only poll for autoneg to complete if specified to do so */
656 if (autoneg_wait_to_complete) {
657 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
658 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
659 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
660 links_reg = 0; /*Just in case Autoneg time=0*/
661 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
662 links_reg =
663 IXGBE_READ_REG(hw, IXGBE_LINKS);
664 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
665 break;
666 msleep(100);
667 }
668 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
669 status =
670 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
671 hw_dbg(hw, "Autoneg did not "
672 "complete.\n");
673 }
674 }
675 }
676
677 /* Set up flow control */
678 status = ixgbe_setup_fc_generic(hw, 0);
679
680 /* Add delay to filter out noises during initial link setup */
681 msleep(50);
682 }
683
684 return status;
685}
686
687/**
688 * ixgbe_setup_copper_link_82599 - Setup copper link settings
689 * @hw: pointer to hardware structure
690 *
691 * Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
692 **/
693static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
694{
695 s32 status;
696
697 /* Restart autonegotiation on PHY */
698 status = hw->phy.ops.setup_link(hw);
699
700 /* Set up MAC */
701 ixgbe_setup_mac_link_82599(hw);
702
703 return status;
704}
705
706/**
707 * ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
708 * @hw: pointer to hardware structure
709 * @speed: new link speed
710 * @autoneg: true if autonegotiation enabled
711 * @autoneg_wait_to_complete: true if waiting is needed to complete
712 *
713 * Restarts link on PHY and MAC based on settings passed in.
714 **/
715static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
716 ixgbe_link_speed speed,
717 bool autoneg,
718 bool autoneg_wait_to_complete)
719{
720 s32 status;
721
722 /* Setup the PHY according to input speed */
723 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
724 autoneg_wait_to_complete);
725 /* Set up MAC */
726 ixgbe_setup_mac_link_82599(hw);
727
728 return status;
729}
730
731/**
732 * ixgbe_reset_hw_82599 - Perform hardware reset
733 * @hw: pointer to hardware structure
734 *
735 * Resets the hardware by resetting the transmit and receive units, masks
736 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
737 * reset.
738 **/
739s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
740{
741 s32 status = 0;
742 u32 ctrl, ctrl_ext;
743 u32 i;
744 u32 autoc;
745 u32 autoc2;
746
747 /* Call adapter stop to disable tx/rx and clear interrupts */
748 hw->mac.ops.stop_adapter(hw);
749
553b4497 750 /* PHY ops must be identified and initialized prior to reset */
04f165ef 751
553b4497
PW		 752 /* Init PHY and function pointers, perform SFP setup */
753 status = hw->phy.ops.init(hw);
04f165ef 754
553b4497
PW		 755 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
756 goto reset_hw_out;
04f165ef 757
553b4497
PW		 758 /* Setup SFP module if there is one present. */
759 if (hw->phy.sfp_setup_needed) {
760 status = hw->mac.ops.setup_sfp(hw);
761 hw->phy.sfp_setup_needed = false;
04f165ef 762 }
11afc1b1 763
553b4497
PW		 764 /* Reset PHY */
765 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
766 hw->phy.ops.reset(hw);
767
11afc1b1
PW		 768 /*
769 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
770 * access and verify no pending requests before reset
771 */
04f165ef
PW		 772 status = ixgbe_disable_pcie_master(hw);
773 if (status != 0) {
11afc1b1
PW		 774 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
775 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
776 }
777
778 /*
779 * Issue global reset to the MAC. This needs to be a SW reset.
780 * If link reset is used, it might reset the MAC when mng is using it
781 */
782 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
783 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
784 IXGBE_WRITE_FLUSH(hw);
785
786 /* Poll for reset bit to self-clear indicating reset is complete */
787 for (i = 0; i < 10; i++) {
788 udelay(1);
789 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
790 if (!(ctrl & IXGBE_CTRL_RST))
791 break;
792 }
793 if (ctrl & IXGBE_CTRL_RST) {
794 status = IXGBE_ERR_RESET_FAILED;
795 hw_dbg(hw, "Reset polling failed to complete.\n");
796 }
797 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
798 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
799 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
800 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
801
802 msleep(50);
803
804
805
806 /*
807 * Store the original AUTOC/AUTOC2 values if they have not been
808 * stored off yet. Otherwise restore the stored original
809 * values since the reset operation sets back to defaults.
810 */
811 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
812 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
813 if (hw->mac.orig_link_settings_stored == false) {
814 hw->mac.orig_autoc = autoc;
815 hw->mac.orig_autoc2 = autoc2;
816 hw->mac.orig_link_settings_stored = true;
4df10466 817 } else {
11afc1b1
PW		 818 if (autoc != hw->mac.orig_autoc)
819 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
820 IXGBE_AUTOC_AN_RESTART));
821
822 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
823 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
824 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
825 autoc2 |= (hw->mac.orig_autoc2 &
826 IXGBE_AUTOC2_UPPER_MASK);
827 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
828 }
829 }
830
aca6bee7
WJP		 831 /*
832 * Store MAC address from RAR0, clear receive address registers, and
833 * clear the multicast table. Also reset num_rar_entries to 128,
834 * since we modify this value when programming the SAN MAC address.
835 */
836 hw->mac.num_rar_entries = 128;
837 hw->mac.ops.init_rx_addrs(hw);
838
11afc1b1
PW		 839 /* Store the permanent mac address */
840 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
841
0365e6e4
PW		 842 /* Store the permanent SAN mac address */
843 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
844
aca6bee7
WJP		 845 /* Add the SAN MAC address to the RAR only if it's a valid address */
846 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
847 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
848 hw->mac.san_addr, 0, IXGBE_RAH_AV);
849
850 /* Reserve the last RAR for the SAN MAC address */
851 hw->mac.num_rar_entries--;
852 }
853
04f165ef 854reset_hw_out:
11afc1b1
PW		 855 return status;
856}
857
858/**
859 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
860 * @hw: pointer to hardware struct
861 * @rar: receive address register index to disassociate
862 * @vmdq: VMDq pool index to remove from the rar
863 **/
864s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
865{
866 u32 mpsar_lo, mpsar_hi;
867 u32 rar_entries = hw->mac.num_rar_entries;
868
869 if (rar < rar_entries) {
870 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
871 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
872
873 if (!mpsar_lo && !mpsar_hi)
874 goto done;
875
876 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
877 if (mpsar_lo) {
878 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
879 mpsar_lo = 0;
880 }
881 if (mpsar_hi) {
882 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
883 mpsar_hi = 0;
884 }
885 } else if (vmdq < 32) {
886 mpsar_lo &= ~(1 << vmdq);
887 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
888 } else {
889 mpsar_hi &= ~(1 << (vmdq - 32));
890 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
891 }
892
893 /* was that the last pool using this rar? */
894 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
895 hw->mac.ops.clear_rar(hw, rar);
896 } else {
897 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
898 }
899
900done:
901 return 0;
902}
903
904/**
905 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
906 * @hw: pointer to hardware struct
907 * @rar: receive address register index to associate with a VMDq index
908 * @vmdq: VMDq pool index
909 **/
910s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
911{
912 u32 mpsar;
913 u32 rar_entries = hw->mac.num_rar_entries;
914
915 if (rar < rar_entries) {
916 if (vmdq < 32) {
917 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
918 mpsar |= 1 << vmdq;
919 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
920 } else {
921 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
922 mpsar |= 1 << (vmdq - 32);
923 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
924 }
925 } else {
926 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
927 }
928 return 0;
929}
930
931/**
932 * ixgbe_set_vfta_82599 - Set VLAN filter table
933 * @hw: pointer to hardware structure
934 * @vlan: VLAN id to write to VLAN filter
935 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
936 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
937 *
938 * Turn on/off specified VLAN in the VLAN filter table.
939 **/
940s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
941 bool vlan_on)
942{
943 u32 regindex;
944 u32 bitindex;
945 u32 bits;
946 u32 first_empty_slot;
947
948 if (vlan > 4095)
949 return IXGBE_ERR_PARAM;
950
951 /*
952 * this is a 2 part operation - first the VFTA, then the
953 * VLVF and VLVFB if vind is set
954 */
955
956 /* Part 1
957 * The VFTA is a bitstring made up of 128 32-bit registers
958 * that enable the particular VLAN id, much like the MTA:
959 * bits[11-5]: which register
960 * bits[4-0]: which bit in the register
961 */
962 regindex = (vlan >> 5) & 0x7F;
963 bitindex = vlan & 0x1F;
964 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
965 if (vlan_on)
966 bits |= (1 << bitindex);
967 else
968 bits &= ~(1 << bitindex);
969 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
970
971
972 /* Part 2
973 * If the vind is set
974 * Either vlan_on
975 * make sure the vlan is in VLVF
976 * set the vind bit in the matching VLVFB
977 * Or !vlan_on
978 * clear the pool bit and possibly the vind
979 */
980 if (vind) {
981 /* find the vlanid or the first empty slot */
982 first_empty_slot = 0;
983
984 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
985 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
986 if (!bits && !first_empty_slot)
987 first_empty_slot = regindex;
988 else if ((bits & 0x0FFF) == vlan)
989 break;
990 }
991
992 if (regindex >= IXGBE_VLVF_ENTRIES) {
993 if (first_empty_slot)
994 regindex = first_empty_slot;
995 else {
996 hw_dbg(hw, "No space in VLVF.\n");
997 goto out;
998 }
999 }
1000
1001 if (vlan_on) {
1002 /* set the pool bit */
1003 if (vind < 32) {
1004 bits = IXGBE_READ_REG(hw,
1005 IXGBE_VLVFB(regindex * 2));
1006 bits |= (1 << vind);
1007 IXGBE_WRITE_REG(hw,
1008 IXGBE_VLVFB(regindex * 2), bits);
1009 } else {
1010 bits = IXGBE_READ_REG(hw,
1011 IXGBE_VLVFB((regindex * 2) + 1));
1012 bits |= (1 << vind);
1013 IXGBE_WRITE_REG(hw,
1014 IXGBE_VLVFB((regindex * 2) + 1), bits);
1015 }
1016 } else {
1017 /* clear the pool bit */
1018 if (vind < 32) {
1019 bits = IXGBE_READ_REG(hw,
1020 IXGBE_VLVFB(regindex * 2));
1021 bits &= ~(1 << vind);
1022 IXGBE_WRITE_REG(hw,
1023 IXGBE_VLVFB(regindex * 2), bits);
1024 bits |= IXGBE_READ_REG(hw,
1025 IXGBE_VLVFB((regindex * 2) + 1));
1026 } else {
1027 bits = IXGBE_READ_REG(hw,
1028 IXGBE_VLVFB((regindex * 2) + 1));
1029 bits &= ~(1 << vind);
1030 IXGBE_WRITE_REG(hw,
1031 IXGBE_VLVFB((regindex * 2) + 1), bits);
1032 bits |= IXGBE_READ_REG(hw,
1033 IXGBE_VLVFB(regindex * 2));
1034 }
1035 }
1036
1037 if (bits)
1038 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1039 (IXGBE_VLVF_VIEN | vlan));
1040 else
1041 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1042 }
1043
1044out:
1045 return 0;
1046}
1047
1048/**
1049 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1050 * @hw: pointer to hardware structure
1051 *
1052 * Clears the VLAN filer table, and the VMDq index associated with the filter
1053 **/
1054s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1055{
1056 u32 offset;
1057
1058 for (offset = 0; offset < hw->mac.vft_size; offset++)
1059 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1060
1061 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1062 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1063 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1064 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1065 }
1066
1067 return 0;
1068}
1069
11afc1b1
PW		 1070/**
1071 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1072 * @hw: pointer to hardware structure
1073 **/
1074s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1075{
1076 int i;
1077 hw_dbg(hw, " Clearing UTA\n");
1078
1079 for (i = 0; i < 128; i++)
1080 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1081
1082 return 0;
1083}
1084
1085/**
1086 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1087 * @hw: pointer to hardware structure
1088 * @reg: analog register to read
1089 * @val: read value
1090 *
1091 * Performs read operation to Omer analog register specified.
1092 **/
1093s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1094{
1095 u32 core_ctl;
1096
1097 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1098 (reg << 8));
1099 IXGBE_WRITE_FLUSH(hw);
1100 udelay(10);
1101 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1102 *val = (u8)core_ctl;
1103
1104 return 0;
1105}
1106
1107/**
1108 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1109 * @hw: pointer to hardware structure
1110 * @reg: atlas register to write
1111 * @val: value to write
1112 *
1113 * Performs write operation to Omer analog register specified.
1114 **/
1115s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1116{
1117 u32 core_ctl;
1118
1119 core_ctl = (reg << 8) | val;
1120 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1121 IXGBE_WRITE_FLUSH(hw);
1122 udelay(10);
1123
1124 return 0;
1125}
1126
1127/**
1128 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1129 * @hw: pointer to hardware structure
1130 *
1131 * Starts the hardware using the generic start_hw function.
1132 * Then performs device-specific:
1133 * Clears the rate limiter registers.
1134 **/
1135s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1136{
1137 u32 q_num;
1138
1139 ixgbe_start_hw_generic(hw);
1140
1141 /* Clear the rate limiters */
1142 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1143 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1144 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1145 }
1146 IXGBE_WRITE_FLUSH(hw);
1147
1148 return 0;
1149}
1150
1151/**
1152 * ixgbe_identify_phy_82599 - Get physical layer module
1153 * @hw: pointer to hardware structure
1154 *
1155 * Determines the physical layer module found on the current adapter.
1156 **/
1157s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1158{
1159 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1160 status = ixgbe_identify_phy_generic(hw);
1161 if (status != 0)
1162 status = ixgbe_identify_sfp_module_generic(hw);
1163 return status;
1164}
1165
1166/**
1167 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1168 * @hw: pointer to hardware structure
1169 *
1170 * Determines physical layer capabilities of the current configuration.
1171 **/
1172u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1173{
1174 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 1175 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1176 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1177 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1178 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1179 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1180 u16 ext_ability = 0;
1339b9e9 1181 u8 comp_codes_10g = 0;
11afc1b1 1182
04193058
PWJ		 1183 hw->phy.ops.identify(hw);
1184
1185 if (hw->phy.type == ixgbe_phy_tn ||
1186 hw->phy.type == ixgbe_phy_cu_unknown) {
6b73e10d
BH		 1187 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1188 &ext_ability);
1189 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 1190 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 1191 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 1192 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 1193 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 1194 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1195 goto out;
1196 }
1197
1198 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1199 case IXGBE_AUTOC_LMS_1G_AN:
1200 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1201 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1202 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1203 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1204 goto out;
1205 } else
1206 /* SFI mode so read SFP module */
1207 goto sfp_check;
11afc1b1 1208 break;
04193058
PWJ		 1209 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1210 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1211 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1212 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1213 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 1214 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1215 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 1216 goto out;
1217 break;
1218 case IXGBE_AUTOC_LMS_10G_SERIAL:
1219 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1220 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1221 goto out;
1222 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1223 goto sfp_check;
1224 break;
1225 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1226 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1227 if (autoc & IXGBE_AUTOC_KX_SUPP)
1228 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1229 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1230 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1231 if (autoc & IXGBE_AUTOC_KR_SUPP)
1232 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1233 goto out;
1234 break;
1235 default:
1236 goto out;
1237 break;
1238 }
11afc1b1 1239
04193058
PWJ		 1240sfp_check:
1241 /* SFP check must be done last since DA modules are sometimes used to
1242 * test KR mode - we need to id KR mode correctly before SFP module.
1243 * Call identify_sfp because the pluggable module may have changed */
1244 hw->phy.ops.identify_sfp(hw);
1245 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1246 goto out;
1247
1248 switch (hw->phy.type) {
1249 case ixgbe_phy_tw_tyco:
1250 case ixgbe_phy_tw_unknown:
1251 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1252 break;
1253 case ixgbe_phy_sfp_avago:
1254 case ixgbe_phy_sfp_ftl:
1255 case ixgbe_phy_sfp_intel:
1256 case ixgbe_phy_sfp_unknown:
1257 hw->phy.ops.read_i2c_eeprom(hw,
1258 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1259 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 1260 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 1261 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 1262 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
11afc1b1
PW		 1263 break;
1264 default:
11afc1b1
PW		 1265 break;
1266 }
1267
04193058 1268out:
11afc1b1
PW		 1269 return physical_layer;
1270}
1271
1272/**
1273 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1274 * @hw: pointer to hardware structure
1275 * @regval: register value to write to RXCTRL
1276 *
1277 * Enables the Rx DMA unit for 82599
1278 **/
1279s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1280{
1281#define IXGBE_MAX_SECRX_POLL 30
1282 int i;
1283 int secrxreg;
1284
1285 /*
1286 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1287 * If traffic is incoming before we enable the Rx unit, it could hang
1288 * the Rx DMA unit. Therefore, make sure the security engine is
1289 * completely disabled prior to enabling the Rx unit.
1290 */
1291 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1292 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1293 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1294 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1295 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1296 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1297 break;
1298 else
1299 udelay(10);
1300 }
1301
1302 /* For informational purposes only */
1303 if (i >= IXGBE_MAX_SECRX_POLL)
1304 hw_dbg(hw, "Rx unit being enabled before security "
1305 "path fully disabled. Continuing with init.\n");
1306
1307 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1308 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1309 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1310 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1311 IXGBE_WRITE_FLUSH(hw);
1312
1313 return 0;
1314}
1315
04193058
PWJ		 1316/**
1317 * ixgbe_get_device_caps_82599 - Get additional device capabilities
1318 * @hw: pointer to hardware structure
1319 * @device_caps: the EEPROM word with the extra device capabilities
1320 *
1321 * This function will read the EEPROM location for the device capabilities,
1322 * and return the word through device_caps.
1323 **/
1324s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
1325{
1326 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
1327
1328 return 0;
1329}
1330
0365e6e4
PW		 1331/**
1332 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
1333 * @hw: pointer to hardware structure
1334 * @san_mac_offset: SAN MAC address offset
1335 *
1336 * This function will read the EEPROM location for the SAN MAC address
1337 * pointer, and returns the value at that location. This is used in both
1338 * get and set mac_addr routines.
1339 **/
1340s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
1341 u16 *san_mac_offset)
1342{
1343 /*
1344 * First read the EEPROM pointer to see if the MAC addresses are
1345 * available.
1346 */
1347 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
1348
1349 return 0;
1350}
1351
1352/**
1353 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
1354 * @hw: pointer to hardware structure
1355 * @san_mac_addr: SAN MAC address
1356 *
1357 * Reads the SAN MAC address from the EEPROM, if it's available. This is
1358 * per-port, so set_lan_id() must be called before reading the addresses.
1359 * set_lan_id() is called by identify_sfp(), but this cannot be relied
1360 * upon for non-SFP connections, so we must call it here.
1361 **/
1362s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
1363{
1364 u16 san_mac_data, san_mac_offset;
1365 u8 i;
1366
1367 /*
1368 * First read the EEPROM pointer to see if the MAC addresses are
1369 * available. If they're not, no point in calling set_lan_id() here.
1370 */
1371 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
1372
1373 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
1374 /*
1375 * No addresses available in this EEPROM. It's not an
1376 * error though, so just wipe the local address and return.
1377 */
1378 for (i = 0; i < 6; i++)
1379 san_mac_addr[i] = 0xFF;
1380
1381 goto san_mac_addr_out;
1382 }
1383
1384 /* make sure we know which port we need to program */
1385 hw->mac.ops.set_lan_id(hw);
1386 /* apply the port offset to the address offset */
1387 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1388 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1389 for (i = 0; i < 3; i++) {
1390 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
1391 san_mac_addr[i * 2] = (u8)(san_mac_data);
1392 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
1393 san_mac_offset++;
1394 }
1395
1396san_mac_addr_out:
1397 return 0;
1398}
1399
11afc1b1
PW		 1400static struct ixgbe_mac_operations mac_ops_82599 = {
1401 .init_hw = &ixgbe_init_hw_generic,
1402 .reset_hw = &ixgbe_reset_hw_82599,
1403 .start_hw = &ixgbe_start_hw_82599,
1404 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1405 .get_media_type = &ixgbe_get_media_type_82599,
1406 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1407 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
1408 .get_mac_addr = &ixgbe_get_mac_addr_generic,
0365e6e4 1409 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
04193058 1410 .get_device_caps = &ixgbe_get_device_caps_82599,
11afc1b1
PW		 1411 .stop_adapter = &ixgbe_stop_adapter_generic,
1412 .get_bus_info = &ixgbe_get_bus_info_generic,
1413 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
1414 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
1415 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
1416 .setup_link = &ixgbe_setup_mac_link_82599,
1417 .setup_link_speed = &ixgbe_setup_mac_link_speed_82599,
1418 .check_link = &ixgbe_check_mac_link_82599,
1419 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
1420 .led_on = &ixgbe_led_on_generic,
1421 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 1422 .blink_led_start = &ixgbe_blink_led_start_generic,
1423 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 1424 .set_rar = &ixgbe_set_rar_generic,
1425 .clear_rar = &ixgbe_clear_rar_generic,
1426 .set_vmdq = &ixgbe_set_vmdq_82599,
1427 .clear_vmdq = &ixgbe_clear_vmdq_82599,
1428 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1429 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1430 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1431 .enable_mc = &ixgbe_enable_mc_generic,
1432 .disable_mc = &ixgbe_disable_mc_generic,
1433 .clear_vfta = &ixgbe_clear_vfta_82599,
1434 .set_vfta = &ixgbe_set_vfta_82599,
1435 .setup_fc = &ixgbe_setup_fc_generic,
1436 .init_uta_tables = &ixgbe_init_uta_tables_82599,
1437 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
1438};
1439
1440static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
1441 .init_params = &ixgbe_init_eeprom_params_generic,
1442 .read = &ixgbe_read_eeprom_generic,
1443 .write = &ixgbe_write_eeprom_generic,
1444 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1445 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1446};
1447
1448static struct ixgbe_phy_operations phy_ops_82599 = {
1449 .identify = &ixgbe_identify_phy_82599,
1450 .identify_sfp = &ixgbe_identify_sfp_module_generic,
04f165ef 1451 .init = &ixgbe_init_phy_ops_82599,
11afc1b1
PW		 1452 .reset = &ixgbe_reset_phy_generic,
1453 .read_reg = &ixgbe_read_phy_reg_generic,
1454 .write_reg = &ixgbe_write_phy_reg_generic,
1455 .setup_link = &ixgbe_setup_phy_link_generic,
1456 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1457 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
1458 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
1459 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
1460 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
1461};
1462
1463struct ixgbe_info ixgbe_82599_info = {
1464 .mac = ixgbe_mac_82599EB,
1465 .get_invariants = &ixgbe_get_invariants_82599,
1466 .mac_ops = &mac_ops_82599,
1467 .eeprom_ops = &eeprom_ops_82599,
1468 .phy_ops = &phy_ops_82599,
1469};
Linux kernel - Deliverables
This page took 0.121486 seconds and 5 git commands to generate.