projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgbe: fix sparse warning
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
11afc1b1
PW		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
096a58fd 34#include "ixgbe_mbx.h"
11afc1b1
PW		 35
36#define IXGBE_82599_MAX_TX_QUEUES 128
37#define IXGBE_82599_MAX_RX_QUEUES 128
38#define IXGBE_82599_RAR_ENTRIES 128
39#define IXGBE_82599_MC_TBL_SIZE 128
40#define IXGBE_82599_VFT_TBL_SIZE 128
e09ad236 41#define IXGBE_82599_RX_PB_SIZE 512
11afc1b1 42
5d5b7c39
ET		 43static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
48 bool autoneg,
49 bool autoneg_wait_to_complete);
cd7e1f0b
DS		 50static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed,
52 bool autoneg,
53 bool autoneg_wait_to_complete);
5d5b7c39
ET		 54static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
55 bool autoneg_wait_to_complete);
56static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
8620a103
MC		 57 ixgbe_link_speed speed,
58 bool autoneg,
59 bool autoneg_wait_to_complete);
8620a103
MC		 60static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
61 ixgbe_link_speed speed,
62 bool autoneg,
63 bool autoneg_wait_to_complete);
794caeb2 64static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
0fa6d832 65static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
11afc1b1 66
7b25cdba 67static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 68{
69 struct ixgbe_mac_info *mac = &hw->mac;
c6ecf39a
DS		 70
71 /* enable the laser control functions for SFP+ fiber */
72 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
61fac744
PW		 73 mac->ops.disable_tx_laser =
74 &ixgbe_disable_tx_laser_multispeed_fiber;
75 mac->ops.enable_tx_laser =
76 &ixgbe_enable_tx_laser_multispeed_fiber;
1097cd17 77 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
11afc1b1 78 } else {
61fac744
PW		 79 mac->ops.disable_tx_laser = NULL;
80 mac->ops.enable_tx_laser = NULL;
1097cd17 81 mac->ops.flap_tx_laser = NULL;
c6ecf39a
DS		 82 }
83
84 if (hw->phy.multispeed_fiber) {
85 /* Set up dual speed SFP+ support */
86 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
87 } else {
cd7e1f0b
DS		 88 if ((mac->ops.get_media_type(hw) ==
89 ixgbe_media_type_backplane) &&
90 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
0fa6d832
ET		 91 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
92 !ixgbe_verify_lesm_fw_enabled_82599(hw))
cd7e1f0b
DS		 93 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
94 else
95 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
11afc1b1
PW		 96 }
97}
98
7b25cdba 99static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 100{
101 s32 ret_val = 0;
a7f5a5fc
DS		 102 u32 reg_anlp1 = 0;
103 u32 i = 0;
11afc1b1
PW		 104 u16 list_offset, data_offset, data_value;
105
106 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
107 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 108
109 hw->phy.ops.reset = NULL;
110
11afc1b1
PW		 111 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
112 &data_offset);
11afc1b1
PW		 113 if (ret_val != 0)
114 goto setup_sfp_out;
115
aa5aec88 116 /* PHY config will finish before releasing the semaphore */
5e655105
DS		 117 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
118 IXGBE_GSSR_MAC_CSR_SM);
aa5aec88
PWJ		 119 if (ret_val != 0) {
120 ret_val = IXGBE_ERR_SWFW_SYNC;
121 goto setup_sfp_out;
122 }
123
11afc1b1
PW		 124 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
125 while (data_value != 0xffff) {
126 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
127 IXGBE_WRITE_FLUSH(hw);
128 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
129 }
aa5aec88
PWJ		 130
131 /* Release the semaphore */
6d980c3e 132 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
032b4325
DS		 133 /*
134 * Delay obtaining semaphore again to allow FW access,
135 * semaphore_delay is in ms usleep_range needs us.
136 */
137 usleep_range(hw->eeprom.semaphore_delay * 1000,
138 hw->eeprom.semaphore_delay * 2000);
a7f5a5fc
DS		 139
140 /* Now restart DSP by setting Restart_AN and clearing LMS */
141 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
142 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
143 IXGBE_AUTOC_AN_RESTART));
144
145 /* Wait for AN to leave state 0 */
146 for (i = 0; i < 10; i++) {
032b4325 147 usleep_range(4000, 8000);
a7f5a5fc
DS		 148 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
149 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
150 break;
151 }
152 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
153 hw_dbg(hw, "sfp module setup not complete\n");
154 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
155 goto setup_sfp_out;
156 }
157
158 /* Restart DSP by setting Restart_AN and return to SFI mode */
159 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
160 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
161 IXGBE_AUTOC_AN_RESTART));
11afc1b1
PW		 162 }
163
164setup_sfp_out:
165 return ret_val;
166}
167
11afc1b1
PW		 168static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
169{
170 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 171
04f165ef 172 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 173
04f165ef
PW		 174 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
175 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
176 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
177 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
178 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
21ce849b 179 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
11afc1b1 180
04f165ef
PW		 181 return 0;
182}
11afc1b1 183
04f165ef
PW		 184/**
185 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
186 * @hw: pointer to hardware structure
187 *
188 * Initialize any function pointers that were not able to be
189 * set during get_invariants because the PHY/SFP type was
190 * not known. Perform the SFP init if necessary.
191 *
192 **/
7b25cdba 193static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
04f165ef
PW		 194{
195 struct ixgbe_mac_info *mac = &hw->mac;
196 struct ixgbe_phy_info *phy = &hw->phy;
197 s32 ret_val = 0;
11afc1b1 198
04f165ef
PW		 199 /* Identify the PHY or SFP module */
200 ret_val = phy->ops.identify(hw);
201
202 /* Setup function pointers based on detected SFP module and speeds */
203 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 204
205 /* If copper media, overwrite with copper function pointers */
206 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
207 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
11afc1b1 208 mac->ops.get_link_capabilities =
a391f1d5 209 &ixgbe_get_copper_link_capabilities_generic;
11afc1b1
PW		 210 }
211
04f165ef 212 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 213 switch (hw->phy.type) {
214 case ixgbe_phy_tn:
215 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
216 phy->ops.get_firmware_version =
04f165ef 217 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1 218 break;
fe15e8e1
DS		 219 case ixgbe_phy_aq:
220 phy->ops.get_firmware_version =
221 &ixgbe_get_phy_firmware_version_generic;
222 break;
11afc1b1
PW		 223 default:
224 break;
225 }
226
11afc1b1
PW		 227 return ret_val;
228}
229
230/**
231 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
232 * @hw: pointer to hardware structure
233 * @speed: pointer to link speed
234 * @negotiation: true when autoneg or autotry is enabled
235 *
236 * Determines the link capabilities by reading the AUTOC register.
237 **/
7b25cdba
DS		 238static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
239 ixgbe_link_speed *speed,
240 bool *negotiation)
11afc1b1
PW		 241{
242 s32 status = 0;
1eb99d5a 243 u32 autoc = 0;
11afc1b1 244
cb836a97
DS		 245 /* Determine 1G link capabilities off of SFP+ type */
246 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
247 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
248 *speed = IXGBE_LINK_SPEED_1GB_FULL;
249 *negotiation = true;
250 goto out;
251 }
252
1eb99d5a
PW		 253 /*
254 * Determine link capabilities based on the stored value of AUTOC,
255 * which represents EEPROM defaults. If AUTOC value has not been
256 * stored, use the current register value.
257 */
258 if (hw->mac.orig_link_settings_stored)
259 autoc = hw->mac.orig_autoc;
260 else
261 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
262
263 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 264 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
265 *speed = IXGBE_LINK_SPEED_1GB_FULL;
266 *negotiation = false;
267 break;
268
269 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
270 *speed = IXGBE_LINK_SPEED_10GB_FULL;
271 *negotiation = false;
272 break;
273
274 case IXGBE_AUTOC_LMS_1G_AN:
275 *speed = IXGBE_LINK_SPEED_1GB_FULL;
276 *negotiation = true;
277 break;
278
279 case IXGBE_AUTOC_LMS_10G_SERIAL:
280 *speed = IXGBE_LINK_SPEED_10GB_FULL;
281 *negotiation = false;
282 break;
283
284 case IXGBE_AUTOC_LMS_KX4_KX_KR:
285 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
286 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 287 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 288 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 289 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 290 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 291 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 292 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
293 *negotiation = true;
294 break;
295
296 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
297 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 298 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 299 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 300 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 301 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 302 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 303 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
304 *negotiation = true;
305 break;
306
307 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
308 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
309 *negotiation = false;
310 break;
311
312 default:
313 status = IXGBE_ERR_LINK_SETUP;
314 goto out;
315 break;
316 }
317
318 if (hw->phy.multispeed_fiber) {
319 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
320 IXGBE_LINK_SPEED_1GB_FULL;
321 *negotiation = true;
322 }
323
324out:
325 return status;
326}
327
11afc1b1
PW		 328/**
329 * ixgbe_get_media_type_82599 - Get media type
330 * @hw: pointer to hardware structure
331 *
332 * Returns the media type (fiber, copper, backplane)
333 **/
7b25cdba 334static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 335{
336 enum ixgbe_media_type media_type;
337
338 /* Detect if there is a copper PHY attached. */
21cc5b4f
ET		 339 switch (hw->phy.type) {
340 case ixgbe_phy_cu_unknown:
341 case ixgbe_phy_tn:
342 case ixgbe_phy_aq:
11afc1b1
PW		 343 media_type = ixgbe_media_type_copper;
344 goto out;
21cc5b4f
ET		 345 default:
346 break;
11afc1b1
PW		 347 }
348
349 switch (hw->device_id) {
11afc1b1 350 case IXGBE_DEV_ID_82599_KX4:
dbfec662 351 case IXGBE_DEV_ID_82599_KX4_MEZZ:
312eb931 352 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
74757d49 353 case IXGBE_DEV_ID_82599_KR:
dbffcb21 354 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
1fcf03e6 355 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 356 /* Default device ID is mezzanine card KX/KX4 */
357 media_type = ixgbe_media_type_backplane;
358 break;
359 case IXGBE_DEV_ID_82599_SFP:
dbffcb21 360 case IXGBE_DEV_ID_82599_SFP_FCOE:
38ad1c8e 361 case IXGBE_DEV_ID_82599_SFP_EM:
4c40ef02 362 case IXGBE_DEV_ID_82599_SFP_SF2:
11afc1b1
PW		 363 media_type = ixgbe_media_type_fiber;
364 break;
8911184f 365 case IXGBE_DEV_ID_82599_CX4:
6b1be199 366 media_type = ixgbe_media_type_cx4;
8911184f 367 break;
21cc5b4f
ET		 368 case IXGBE_DEV_ID_82599_T3_LOM:
369 media_type = ixgbe_media_type_copper;
370 break;
11afc1b1
PW		 371 default:
372 media_type = ixgbe_media_type_unknown;
373 break;
374 }
375out:
376 return media_type;
377}
378
379/**
8620a103 380 * ixgbe_start_mac_link_82599 - Setup MAC link settings
11afc1b1 381 * @hw: pointer to hardware structure
8620a103 382 * @autoneg_wait_to_complete: true when waiting for completion is needed
11afc1b1
PW		 383 *
384 * Configures link settings based on values in the ixgbe_hw struct.
385 * Restarts the link. Performs autonegotiation if needed.
386 **/
5d5b7c39 387static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
8620a103 388 bool autoneg_wait_to_complete)
11afc1b1
PW		 389{
390 u32 autoc_reg;
391 u32 links_reg;
392 u32 i;
393 s32 status = 0;
394
395 /* Restart link */
396 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
397 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
398 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
399
400 /* Only poll for autoneg to complete if specified to do so */
8620a103 401 if (autoneg_wait_to_complete) {
11afc1b1
PW		 402 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
403 IXGBE_AUTOC_LMS_KX4_KX_KR ||
404 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
405 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
406 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
407 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
408 links_reg = 0; /* Just in case Autoneg time = 0 */
409 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
410 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
411 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
412 break;
413 msleep(100);
414 }
415 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
416 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
417 hw_dbg(hw, "Autoneg did not complete.\n");
418 }
419 }
420 }
421
11afc1b1
PW		 422 /* Add delay to filter out noises during initial link setup */
423 msleep(50);
424
425 return status;
426}
427
8c7bea32
ET		 428/**
429 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
430 * @hw: pointer to hardware structure
431 *
432 * The base drivers may require better control over SFP+ module
433 * PHY states. This includes selectively shutting down the Tx
434 * laser on the PHY, effectively halting physical link.
435 **/
5d5b7c39 436static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
61fac744
PW		 437{
438 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
439
440 /* Disable tx laser; allow 100us to go dark per spec */
441 esdp_reg |= IXGBE_ESDP_SDP3;
442 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
443 IXGBE_WRITE_FLUSH(hw);
444 udelay(100);
445}
446
447/**
448 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
449 * @hw: pointer to hardware structure
450 *
451 * The base drivers may require better control over SFP+ module
452 * PHY states. This includes selectively turning on the Tx
453 * laser on the PHY, effectively starting physical link.
454 **/
5d5b7c39 455static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
61fac744
PW		 456{
457 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
458
459 /* Enable tx laser; allow 100ms to light up */
460 esdp_reg &= ~IXGBE_ESDP_SDP3;
461 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
462 IXGBE_WRITE_FLUSH(hw);
463 msleep(100);
464}
465
1097cd17
MC		 466/**
467 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
468 * @hw: pointer to hardware structure
469 *
470 * When the driver changes the link speeds that it can support,
471 * it sets autotry_restart to true to indicate that we need to
472 * initiate a new autotry session with the link partner. To do
473 * so, we set the speed then disable and re-enable the tx laser, to
474 * alert the link partner that it also needs to restart autotry on its
475 * end. This is consistent with true clause 37 autoneg, which also
476 * involves a loss of signal.
477 **/
5d5b7c39 478static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
1097cd17 479{
1097cd17 480 if (hw->mac.autotry_restart) {
61fac744
PW		 481 ixgbe_disable_tx_laser_multispeed_fiber(hw);
482 ixgbe_enable_tx_laser_multispeed_fiber(hw);
1097cd17
MC		 483 hw->mac.autotry_restart = false;
484 }
485}
486
11afc1b1 487/**
8620a103 488 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
11afc1b1
PW		 489 * @hw: pointer to hardware structure
490 * @speed: new link speed
491 * @autoneg: true if autonegotiation enabled
492 * @autoneg_wait_to_complete: true when waiting for completion is needed
493 *
494 * Set the link speed in the AUTOC register and restarts link.
495 **/
b32c8dcc 496static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
8620a103
MC		 497 ixgbe_link_speed speed,
498 bool autoneg,
499 bool autoneg_wait_to_complete)
11afc1b1
PW		 500{
501 s32 status = 0;
037c6d0a 502 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
11afc1b1
PW		 503 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
504 u32 speedcnt = 0;
505 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
037c6d0a 506 u32 i = 0;
11afc1b1
PW		 507 bool link_up = false;
508 bool negotiation;
509
510 /* Mask off requested but non-supported speeds */
037c6d0a
ET		 511 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
512 &negotiation);
513 if (status != 0)
514 return status;
515
516 speed &= link_speed;
11afc1b1
PW		 517
518 /*
519 * Try each speed one by one, highest priority first. We do this in
520 * software because 10gb fiber doesn't support speed autonegotiation.
521 */
522 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
523 speedcnt++;
524 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
525
50ac58ba 526 /* If we already have link at this speed, just jump out */
037c6d0a
ET		 527 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
528 false);
529 if (status != 0)
530 return status;
50ac58ba 531
037c6d0a 532 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
50ac58ba
PWJ		 533 goto out;
534
535 /* Set the module link speed */
11afc1b1
PW		 536 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
537 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
1097cd17 538 IXGBE_WRITE_FLUSH(hw);
11afc1b1 539
50ac58ba
PWJ		 540 /* Allow module to change analog characteristics (1G->10G) */
541 msleep(40);
11afc1b1 542
8620a103 543 status = ixgbe_setup_mac_link_82599(hw,
037c6d0a
ET		 544 IXGBE_LINK_SPEED_10GB_FULL,
545 autoneg,
546 autoneg_wait_to_complete);
50ac58ba 547 if (status != 0)
c3c74327 548 return status;
50ac58ba
PWJ		 549
550 /* Flap the tx laser if it has not already been done */
1097cd17 551 hw->mac.ops.flap_tx_laser(hw);
50ac58ba 552
cd7e1f0b
DS		 553 /*
554 * Wait for the controller to acquire link. Per IEEE 802.3ap,
555 * Section 73.10.2, we may have to wait up to 500ms if KR is
556 * attempted. 82599 uses the same timing for 10g SFI.
557 */
50ac58ba
PWJ		 558 for (i = 0; i < 5; i++) {
559 /* Wait for the link partner to also set speed */
560 msleep(100);
561
562 /* If we have link, just jump out */
037c6d0a
ET		 563 status = hw->mac.ops.check_link(hw, &link_speed,
564 &link_up, false);
565 if (status != 0)
566 return status;
567
50ac58ba
PWJ		 568 if (link_up)
569 goto out;
570 }
11afc1b1
PW		 571 }
572
573 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
574 speedcnt++;
575 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
576 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
577
50ac58ba 578 /* If we already have link at this speed, just jump out */
037c6d0a
ET		 579 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
580 false);
581 if (status != 0)
582 return status;
50ac58ba 583
037c6d0a 584 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
50ac58ba
PWJ		 585 goto out;
586
587 /* Set the module link speed */
11afc1b1
PW		 588 esdp_reg &= ~IXGBE_ESDP_SDP5;
589 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
590 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
1097cd17 591 IXGBE_WRITE_FLUSH(hw);
11afc1b1 592
50ac58ba
PWJ		 593 /* Allow module to change analog characteristics (10G->1G) */
594 msleep(40);
11afc1b1 595
8620a103 596 status = ixgbe_setup_mac_link_82599(hw,
037c6d0a
ET		 597 IXGBE_LINK_SPEED_1GB_FULL,
598 autoneg,
599 autoneg_wait_to_complete);
50ac58ba 600 if (status != 0)
c3c74327 601 return status;
50ac58ba
PWJ		 602
603 /* Flap the tx laser if it has not already been done */
1097cd17 604 hw->mac.ops.flap_tx_laser(hw);
50ac58ba
PWJ		 605
606 /* Wait for the link partner to also set speed */
607 msleep(100);
11afc1b1
PW		 608
609 /* If we have link, just jump out */
037c6d0a
ET		 610 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
611 false);
612 if (status != 0)
613 return status;
614
11afc1b1
PW		 615 if (link_up)
616 goto out;
617 }
618
619 /*
620 * We didn't get link. Configure back to the highest speed we tried,
621 * (if there was more than one). We call ourselves back with just the
622 * single highest speed that the user requested.
623 */
624 if (speedcnt > 1)
8620a103
MC		 625 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
626 highest_link_speed,
627 autoneg,
628 autoneg_wait_to_complete);
11afc1b1
PW		 629
630out:
c3c74327
MC		 631 /* Set autoneg_advertised value based on input link speed */
632 hw->phy.autoneg_advertised = 0;
633
634 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
635 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
636
637 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
638 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
639
11afc1b1
PW		 640 return status;
641}
642
cd7e1f0b
DS		 643/**
644 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
645 * @hw: pointer to hardware structure
646 * @speed: new link speed
647 * @autoneg: true if autonegotiation enabled
648 * @autoneg_wait_to_complete: true when waiting for completion is needed
649 *
650 * Implements the Intel SmartSpeed algorithm.
651 **/
652static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
653 ixgbe_link_speed speed, bool autoneg,
654 bool autoneg_wait_to_complete)
655{
656 s32 status = 0;
037c6d0a 657 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
cd7e1f0b
DS		 658 s32 i, j;
659 bool link_up = false;
660 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
cd7e1f0b
DS		 661
662 /* Set autoneg_advertised value based on input link speed */
663 hw->phy.autoneg_advertised = 0;
664
665 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
666 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
667
668 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
669 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
670
671 if (speed & IXGBE_LINK_SPEED_100_FULL)
672 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
673
674 /*
675 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
676 * autoneg advertisement if link is unable to be established at the
677 * highest negotiated rate. This can sometimes happen due to integrity
678 * issues with the physical media connection.
679 */
680
681 /* First, try to get link with full advertisement */
682 hw->phy.smart_speed_active = false;
683 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
684 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
685 autoneg_wait_to_complete);
037c6d0a 686 if (status != 0)
cd7e1f0b
DS		 687 goto out;
688
689 /*
690 * Wait for the controller to acquire link. Per IEEE 802.3ap,
691 * Section 73.10.2, we may have to wait up to 500ms if KR is
692 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
693 * Table 9 in the AN MAS.
694 */
695 for (i = 0; i < 5; i++) {
696 mdelay(100);
697
698 /* If we have link, just jump out */
037c6d0a
ET		 699 status = hw->mac.ops.check_link(hw, &link_speed,
700 &link_up, false);
701 if (status != 0)
702 goto out;
703
cd7e1f0b
DS		 704 if (link_up)
705 goto out;
706 }
707 }
708
709 /*
710 * We didn't get link. If we advertised KR plus one of KX4/KX
711 * (or BX4/BX), then disable KR and try again.
712 */
713 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
714 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
715 goto out;
716
717 /* Turn SmartSpeed on to disable KR support */
718 hw->phy.smart_speed_active = true;
719 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
720 autoneg_wait_to_complete);
037c6d0a 721 if (status != 0)
cd7e1f0b
DS		 722 goto out;
723
724 /*
725 * Wait for the controller to acquire link. 600ms will allow for
726 * the AN link_fail_inhibit_timer as well for multiple cycles of
727 * parallel detect, both 10g and 1g. This allows for the maximum
728 * connect attempts as defined in the AN MAS table 73-7.
729 */
730 for (i = 0; i < 6; i++) {
731 mdelay(100);
732
733 /* If we have link, just jump out */
037c6d0a
ET		 734 status = hw->mac.ops.check_link(hw, &link_speed,
735 &link_up, false);
736 if (status != 0)
737 goto out;
738
cd7e1f0b
DS		 739 if (link_up)
740 goto out;
741 }
742
743 /* We didn't get link. Turn SmartSpeed back off. */
744 hw->phy.smart_speed_active = false;
745 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
746 autoneg_wait_to_complete);
747
748out:
c4ee6a53 749 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
037c6d0a 750 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
849c4542 751 "the maximum advertised\n");
cd7e1f0b
DS		 752 return status;
753}
754
11afc1b1 755/**
8620a103 756 * ixgbe_setup_mac_link_82599 - Set MAC link speed
11afc1b1
PW		 757 * @hw: pointer to hardware structure
758 * @speed: new link speed
759 * @autoneg: true if autonegotiation enabled
760 * @autoneg_wait_to_complete: true when waiting for completion is needed
761 *
762 * Set the link speed in the AUTOC register and restarts link.
763 **/
5d5b7c39 764static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
8620a103
MC		 765 ixgbe_link_speed speed, bool autoneg,
766 bool autoneg_wait_to_complete)
11afc1b1
PW		 767{
768 s32 status = 0;
769 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
770 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
50ac58ba 771 u32 start_autoc = autoc;
1eb99d5a 772 u32 orig_autoc = 0;
11afc1b1
PW		 773 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
774 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
775 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
776 u32 links_reg;
777 u32 i;
778 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
779
780 /* Check to see if speed passed in is supported. */
781 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
0b0c2b31
ET		 782 if (status != 0)
783 goto out;
784
11afc1b1
PW		 785 speed &= link_capabilities;
786
50ac58ba
PWJ		 787 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
788 status = IXGBE_ERR_LINK_SETUP;
789 goto out;
790 }
791
1eb99d5a
PW		 792 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
793 if (hw->mac.orig_link_settings_stored)
794 orig_autoc = hw->mac.orig_autoc;
795 else
796 orig_autoc = autoc;
797
50ac58ba
PWJ		 798 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
799 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
800 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
11afc1b1
PW		 801 /* Set KX4/KX/KR support according to speed requested */
802 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
803 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 804 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 805 autoc |= IXGBE_AUTOC_KX4_SUPP;
cd7e1f0b
DS		 806 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
807 (hw->phy.smart_speed_active == false))
11afc1b1
PW		 808 autoc |= IXGBE_AUTOC_KR_SUPP;
809 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
810 autoc |= IXGBE_AUTOC_KX_SUPP;
811 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
812 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
813 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
814 /* Switch from 1G SFI to 10G SFI if requested */
815 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
816 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
817 autoc &= ~IXGBE_AUTOC_LMS_MASK;
818 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
819 }
820 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
821 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
822 /* Switch from 10G SFI to 1G SFI if requested */
823 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
824 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
825 autoc &= ~IXGBE_AUTOC_LMS_MASK;
826 if (autoneg)
827 autoc |= IXGBE_AUTOC_LMS_1G_AN;
828 else
829 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
830 }
831 }
832
50ac58ba 833 if (autoc != start_autoc) {
11afc1b1
PW		 834 /* Restart link */
835 autoc |= IXGBE_AUTOC_AN_RESTART;
836 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
837
838 /* Only poll for autoneg to complete if specified to do so */
839 if (autoneg_wait_to_complete) {
840 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
841 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
842 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
843 links_reg = 0; /*Just in case Autoneg time=0*/
844 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
845 links_reg =
846 IXGBE_READ_REG(hw, IXGBE_LINKS);
847 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
848 break;
849 msleep(100);
850 }
851 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
852 status =
853 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
854 hw_dbg(hw, "Autoneg did not "
855 "complete.\n");
856 }
857 }
858 }
859
11afc1b1
PW		 860 /* Add delay to filter out noises during initial link setup */
861 msleep(50);
862 }
863
50ac58ba 864out:
11afc1b1
PW		 865 return status;
866}
867
868/**
8620a103 869 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
11afc1b1
PW		 870 * @hw: pointer to hardware structure
871 * @speed: new link speed
872 * @autoneg: true if autonegotiation enabled
873 * @autoneg_wait_to_complete: true if waiting is needed to complete
874 *
875 * Restarts link on PHY and MAC based on settings passed in.
876 **/
8620a103
MC		 877static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
878 ixgbe_link_speed speed,
879 bool autoneg,
880 bool autoneg_wait_to_complete)
11afc1b1
PW		 881{
882 s32 status;
883
884 /* Setup the PHY according to input speed */
885 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
886 autoneg_wait_to_complete);
887 /* Set up MAC */
8620a103 888 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
11afc1b1
PW		 889
890 return status;
891}
892
893/**
894 * ixgbe_reset_hw_82599 - Perform hardware reset
895 * @hw: pointer to hardware structure
896 *
897 * Resets the hardware by resetting the transmit and receive units, masks
898 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
899 * reset.
900 **/
7b25cdba 901static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 902{
903 s32 status = 0;
c9205697 904 u32 ctrl;
11afc1b1
PW		 905 u32 i;
906 u32 autoc;
907 u32 autoc2;
908
909 /* Call adapter stop to disable tx/rx and clear interrupts */
910 hw->mac.ops.stop_adapter(hw);
911
553b4497 912 /* PHY ops must be identified and initialized prior to reset */
04f165ef 913
037c6d0a 914 /* Identify PHY and related function pointers */
553b4497 915 status = hw->phy.ops.init(hw);
04f165ef 916
553b4497
PW		 917 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
918 goto reset_hw_out;
04f165ef 919
553b4497
PW		 920 /* Setup SFP module if there is one present. */
921 if (hw->phy.sfp_setup_needed) {
922 status = hw->mac.ops.setup_sfp(hw);
923 hw->phy.sfp_setup_needed = false;
04f165ef 924 }
11afc1b1 925
037c6d0a
ET		 926 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
927 goto reset_hw_out;
928
553b4497
PW		 929 /* Reset PHY */
930 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
931 hw->phy.ops.reset(hw);
932
11afc1b1
PW		 933 /*
934 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
935 * access and verify no pending requests before reset
936 */
a4297dc2 937 ixgbe_disable_pcie_master(hw);
11afc1b1 938
a4297dc2 939mac_reset_top:
11afc1b1
PW		 940 /*
941 * Issue global reset to the MAC. This needs to be a SW reset.
942 * If link reset is used, it might reset the MAC when mng is using it
943 */
944 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
945 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
946 IXGBE_WRITE_FLUSH(hw);
947
948 /* Poll for reset bit to self-clear indicating reset is complete */
949 for (i = 0; i < 10; i++) {
950 udelay(1);
951 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
952 if (!(ctrl & IXGBE_CTRL_RST))
953 break;
954 }
955 if (ctrl & IXGBE_CTRL_RST) {
956 status = IXGBE_ERR_RESET_FAILED;
957 hw_dbg(hw, "Reset polling failed to complete.\n");
958 }
11afc1b1 959
a4297dc2
ET		 960 /*
961 * Double resets are required for recovery from certain error
962 * conditions. Between resets, it is necessary to stall to allow time
963 * for any pending HW events to complete. We use 1usec since that is
964 * what is needed for ixgbe_disable_pcie_master(). The second reset
965 * then clears out any effects of those events.
966 */
967 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
968 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
969 udelay(1);
970 goto mac_reset_top;
971 }
972
11afc1b1
PW		 973 msleep(50);
974
11afc1b1
PW		 975 /*
976 * Store the original AUTOC/AUTOC2 values if they have not been
977 * stored off yet. Otherwise restore the stored original
978 * values since the reset operation sets back to defaults.
979 */
980 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
981 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
982 if (hw->mac.orig_link_settings_stored == false) {
983 hw->mac.orig_autoc = autoc;
984 hw->mac.orig_autoc2 = autoc2;
985 hw->mac.orig_link_settings_stored = true;
4df10466 986 } else {
11afc1b1
PW		 987 if (autoc != hw->mac.orig_autoc)
988 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
989 IXGBE_AUTOC_AN_RESTART));
990
991 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
992 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
993 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
994 autoc2 |= (hw->mac.orig_autoc2 &
995 IXGBE_AUTOC2_UPPER_MASK);
996 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
997 }
998 }
999
278675d8
ET		 1000 /* Store the permanent mac address */
1001 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1002
aca6bee7
WJP		 1003 /*
1004 * Store MAC address from RAR0, clear receive address registers, and
1005 * clear the multicast table. Also reset num_rar_entries to 128,
1006 * since we modify this value when programming the SAN MAC address.
1007 */
1008 hw->mac.num_rar_entries = 128;
1009 hw->mac.ops.init_rx_addrs(hw);
1010
0365e6e4
PW		 1011 /* Store the permanent SAN mac address */
1012 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1013
aca6bee7
WJP		 1014 /* Add the SAN MAC address to the RAR only if it's a valid address */
1015 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1016 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1017 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1018
1019 /* Reserve the last RAR for the SAN MAC address */
1020 hw->mac.num_rar_entries--;
1021 }
1022
383ff34b
YZ		 1023 /* Store the alternative WWNN/WWPN prefix */
1024 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1025 &hw->mac.wwpn_prefix);
1026
04f165ef 1027reset_hw_out:
11afc1b1
PW		 1028 return status;
1029}
1030
ffff4772
PWJ		 1031/**
1032 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1033 * @hw: pointer to hardware structure
1034 **/
1035s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1036{
1037 int i;
1038 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1039 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1040
1041 /*
1042 * Before starting reinitialization process,
1043 * FDIRCMD.CMD must be zero.
1044 */
1045 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1046 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1047 IXGBE_FDIRCMD_CMD_MASK))
1048 break;
1049 udelay(10);
1050 }
1051 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
905e4a41 1052 hw_dbg(hw, "Flow Director previous command isn't complete, "
d6dbee86 1053 "aborting table re-initialization.\n");
ffff4772
PWJ		 1054 return IXGBE_ERR_FDIR_REINIT_FAILED;
1055 }
1056
1057 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1058 IXGBE_WRITE_FLUSH(hw);
1059 /*
1060 * 82599 adapters flow director init flow cannot be restarted,
1061 * Workaround 82599 silicon errata by performing the following steps
1062 * before re-writing the FDIRCTRL control register with the same value.
1063 * - write 1 to bit 8 of FDIRCMD register &
1064 * - write 0 to bit 8 of FDIRCMD register
1065 */
1066 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1067 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1068 IXGBE_FDIRCMD_CLEARHT));
1069 IXGBE_WRITE_FLUSH(hw);
1070 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1071 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1072 ~IXGBE_FDIRCMD_CLEARHT));
1073 IXGBE_WRITE_FLUSH(hw);
1074 /*
1075 * Clear FDIR Hash register to clear any leftover hashes
1076 * waiting to be programmed.
1077 */
1078 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1079 IXGBE_WRITE_FLUSH(hw);
1080
1081 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1082 IXGBE_WRITE_FLUSH(hw);
1083
1084 /* Poll init-done after we write FDIRCTRL register */
1085 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1086 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1087 IXGBE_FDIRCTRL_INIT_DONE)
1088 break;
1089 udelay(10);
1090 }
1091 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1092 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1093 return IXGBE_ERR_FDIR_REINIT_FAILED;
1094 }
1095
1096 /* Clear FDIR statistics registers (read to clear) */
1097 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1098 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1099 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1100 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1101 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1102
1103 return 0;
1104}
1105
1106/**
1107 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1108 * @hw: pointer to hardware structure
1109 * @pballoc: which mode to allocate filters with
1110 **/
1111s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1112{
1113 u32 fdirctrl = 0;
1114 u32 pbsize;
1115 int i;
1116
1117 /*
1118 * Before enabling Flow Director, the Rx Packet Buffer size
1119 * must be reduced. The new value is the current size minus
1120 * flow director memory usage size.
1121 */
1122 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1123 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1124 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1125
1126 /*
1127 * The defaults in the HW for RX PB 1-7 are not zero and so should be
b595076a 1128 * initialized to zero for non DCB mode otherwise actual total RX PB
ffff4772
PWJ		 1129 * would be bigger than programmed and filter space would run into
1130 * the PB 0 region.
1131 */
1132 for (i = 1; i < 8; i++)
1133 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1134
1135 /* Send interrupt when 64 filters are left */
1136 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1137
1138 /* Set the maximum length per hash bucket to 0xA filters */
1139 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1140
1141 switch (pballoc) {
1142 case IXGBE_FDIR_PBALLOC_64K:
1143 /* 8k - 1 signature filters */
1144 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1145 break;
1146 case IXGBE_FDIR_PBALLOC_128K:
1147 /* 16k - 1 signature filters */
1148 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1149 break;
1150 case IXGBE_FDIR_PBALLOC_256K:
1151 /* 32k - 1 signature filters */
1152 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1153 break;
1154 default:
1155 /* bad value */
1156 return IXGBE_ERR_CONFIG;
1157 };
1158
1159 /* Move the flexible bytes to use the ethertype - shift 6 words */
1160 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1161
ffff4772
PWJ		 1162
1163 /* Prime the keys for hashing */
905e4a41
AD		 1164 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1165 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
ffff4772
PWJ		 1166
1167 /*
1168 * Poll init-done after we write the register. Estimated times:
1169 * 10G: PBALLOC = 11b, timing is 60us
1170 * 1G: PBALLOC = 11b, timing is 600us
1171 * 100M: PBALLOC = 11b, timing is 6ms
1172 *
1173 * Multiple these timings by 4 if under full Rx load
1174 *
1175 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1176 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1177 * this might not finish in our poll time, but we can live with that
1178 * for now.
1179 */
1180 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1181 IXGBE_WRITE_FLUSH(hw);
1182 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1183 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1184 IXGBE_FDIRCTRL_INIT_DONE)
1185 break;
032b4325 1186 usleep_range(1000, 2000);
ffff4772
PWJ		 1187 }
1188 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1189 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1190
1191 return 0;
1192}
1193
1194/**
1195 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1196 * @hw: pointer to hardware structure
1197 * @pballoc: which mode to allocate filters with
1198 **/
1199s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1200{
1201 u32 fdirctrl = 0;
1202 u32 pbsize;
1203 int i;
1204
1205 /*
1206 * Before enabling Flow Director, the Rx Packet Buffer size
1207 * must be reduced. The new value is the current size minus
1208 * flow director memory usage size.
1209 */
1210 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1211 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1212 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1213
1214 /*
1215 * The defaults in the HW for RX PB 1-7 are not zero and so should be
b595076a 1216 * initialized to zero for non DCB mode otherwise actual total RX PB
ffff4772
PWJ		 1217 * would be bigger than programmed and filter space would run into
1218 * the PB 0 region.
1219 */
1220 for (i = 1; i < 8; i++)
1221 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1222
1223 /* Send interrupt when 64 filters are left */
1224 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1225
9a713e7c
PW		 1226 /* Initialize the drop queue to Rx queue 127 */
1227 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1228
ffff4772
PWJ		 1229 switch (pballoc) {
1230 case IXGBE_FDIR_PBALLOC_64K:
1231 /* 2k - 1 perfect filters */
1232 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1233 break;
1234 case IXGBE_FDIR_PBALLOC_128K:
1235 /* 4k - 1 perfect filters */
1236 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1237 break;
1238 case IXGBE_FDIR_PBALLOC_256K:
1239 /* 8k - 1 perfect filters */
1240 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1241 break;
1242 default:
1243 /* bad value */
1244 return IXGBE_ERR_CONFIG;
1245 };
1246
1247 /* Turn perfect match filtering on */
1248 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1249 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1250
1251 /* Move the flexible bytes to use the ethertype - shift 6 words */
1252 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1253
1254 /* Prime the keys for hashing */
905e4a41
AD		 1255 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1256 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
ffff4772
PWJ		 1257
1258 /*
1259 * Poll init-done after we write the register. Estimated times:
1260 * 10G: PBALLOC = 11b, timing is 60us
1261 * 1G: PBALLOC = 11b, timing is 600us
1262 * 100M: PBALLOC = 11b, timing is 6ms
1263 *
1264 * Multiple these timings by 4 if under full Rx load
1265 *
1266 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1267 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1268 * this might not finish in our poll time, but we can live with that
1269 * for now.
1270 */
1271
1272 /* Set the maximum length per hash bucket to 0xA filters */
1273 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1274
1275 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1276 IXGBE_WRITE_FLUSH(hw);
1277 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1278 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1279 IXGBE_FDIRCTRL_INIT_DONE)
1280 break;
032b4325 1281 usleep_range(1000, 2000);
ffff4772
PWJ		 1282 }
1283 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1284 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1285
1286 return 0;
1287}
1288
1289
1290/**
1291 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1292 * @stream: input bitstream to compute the hash on
1293 * @key: 32-bit hash key
1294 **/
905e4a41
AD		 1295static u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
1296 u32 key)
ffff4772
PWJ		 1297{
1298 /*
1299 * The algorithm is as follows:
1300 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1301 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1302 * and A[n] x B[n] is bitwise AND between same length strings
1303 *
1304 * K[n] is 16 bits, defined as:
1305 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1306 * for n modulo 32 < 15, K[n] =
1307 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1308 *
1309 * S[n] is 16 bits, defined as:
1310 * for n >= 15, S[n] = S[n:n - 15]
1311 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1312 *
1313 * To simplify for programming, the algorithm is implemented
1314 * in software this way:
1315 *
905e4a41
AD		 1316 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
1317 *
1318 * for (i = 0; i < 352; i+=32)
1319 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
1320 *
1321 * lo_hash_dword[15:0] ^= Stream[15:0];
1322 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
1323 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
ffff4772 1324 *
905e4a41 1325 * hi_hash_dword[31:0] ^= Stream[351:320];
ffff4772 1326 *
905e4a41
AD		 1327 * if(key[0])
1328 * hash[15:0] ^= Stream[15:0];
1329 *
1330 * for (i = 0; i < 16; i++) {
1331 * if (key[i])
1332 * hash[15:0] ^= lo_hash_dword[(i+15):i];
1333 * if (key[i + 16])
1334 * hash[15:0] ^= hi_hash_dword[(i+15):i];
ffff4772 1335 * }
905e4a41 1336 *
ffff4772 1337 */
905e4a41
AD		 1338 __be32 common_hash_dword = 0;
1339 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1340 u32 hash_result = 0;
1341 u8 i;
ffff4772 1342
905e4a41
AD		 1343 /* record the flow_vm_vlan bits as they are a key part to the hash */
1344 flow_vm_vlan = ntohl(atr_input->dword_stream[0]);
ffff4772 1345
905e4a41
AD		 1346 /* generate common hash dword */
1347 for (i = 10; i; i -= 2)
1348 common_hash_dword ^= atr_input->dword_stream[i] ^
1349 atr_input->dword_stream[i - 1];
ffff4772 1350
905e4a41 1351 hi_hash_dword = ntohl(common_hash_dword);
ffff4772 1352
905e4a41
AD		 1353 /* low dword is word swapped version of common */
1354 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
ffff4772 1355
905e4a41
AD		 1356 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1357 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
ffff4772 1358
905e4a41
AD		 1359 /* Process bits 0 and 16 */
1360 if (key & 0x0001) hash_result ^= lo_hash_dword;
1361 if (key & 0x00010000) hash_result ^= hi_hash_dword;
ffff4772
PWJ		 1362
1363 /*
905e4a41
AD		 1364 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1365 * delay this because bit 0 of the stream should not be processed
1366 * so we do not add the vlan until after bit 0 was processed
ffff4772 1367 */
905e4a41 1368 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
ffff4772 1369
905e4a41
AD		 1370
1371 /* process the remaining 30 bits in the key 2 bits at a time */
1372 for (i = 15; i; i-- ) {
1373 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
1374 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
ffff4772
PWJ		 1375 }
1376
905e4a41 1377 return hash_result & IXGBE_ATR_HASH_MASK;
ffff4772
PWJ		 1378}
1379
69830529
AD		 1380/*
1381 * These defines allow us to quickly generate all of the necessary instructions
1382 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1383 * for values 0 through 15
1384 */
1385#define IXGBE_ATR_COMMON_HASH_KEY \
1386 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1387#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1388do { \
1389 u32 n = (_n); \
1390 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1391 common_hash ^= lo_hash_dword >> n; \
1392 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1393 bucket_hash ^= lo_hash_dword >> n; \
1394 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1395 sig_hash ^= lo_hash_dword << (16 - n); \
1396 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1397 common_hash ^= hi_hash_dword >> n; \
1398 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1399 bucket_hash ^= hi_hash_dword >> n; \
1400 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1401 sig_hash ^= hi_hash_dword << (16 - n); \
1402} while (0);
1403
1404/**
1405 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1406 * @stream: input bitstream to compute the hash on
1407 *
1408 * This function is almost identical to the function above but contains
1409 * several optomizations such as unwinding all of the loops, letting the
1410 * compiler work out all of the conditional ifs since the keys are static
1411 * defines, and computing two keys at once since the hashed dword stream
1412 * will be the same for both keys.
1413 **/
1414static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1415 union ixgbe_atr_hash_dword common)
1416{
1417 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1418 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1419
1420 /* record the flow_vm_vlan bits as they are a key part to the hash */
1421 flow_vm_vlan = ntohl(input.dword);
1422
1423 /* generate common hash dword */
1424 hi_hash_dword = ntohl(common.dword);
1425
1426 /* low dword is word swapped version of common */
1427 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1428
1429 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1430 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1431
1432 /* Process bits 0 and 16 */
1433 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1434
1435 /*
1436 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1437 * delay this because bit 0 of the stream should not be processed
1438 * so we do not add the vlan until after bit 0 was processed
1439 */
1440 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1441
1442 /* Process remaining 30 bit of the key */
1443 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1444 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1445 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1446 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1447 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1448 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1449 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1450 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1451 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1452 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1453 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1454 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1455 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1456 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1457 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1458
1459 /* combine common_hash result with signature and bucket hashes */
1460 bucket_hash ^= common_hash;
1461 bucket_hash &= IXGBE_ATR_HASH_MASK;
1462
1463 sig_hash ^= common_hash << 16;
1464 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1465
1466 /* return completed signature hash */
1467 return sig_hash ^ bucket_hash;
1468}
1469
ffff4772
PWJ		 1470/**
1471 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1472 * @hw: pointer to hardware structure
69830529
AD		 1473 * @input: unique input dword
1474 * @common: compressed common input dword
ffff4772
PWJ		 1475 * @queue: queue index to direct traffic to
1476 **/
1477s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
69830529
AD		 1478 union ixgbe_atr_hash_dword input,
1479 union ixgbe_atr_hash_dword common,
ffff4772
PWJ		 1480 u8 queue)
1481{
1482 u64 fdirhashcmd;
905e4a41 1483 u32 fdircmd;
ffff4772
PWJ		 1484
1485 /*
905e4a41
AD		 1486 * Get the flow_type in order to program FDIRCMD properly
1487 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
ffff4772 1488 */
69830529 1489 switch (input.formatted.flow_type) {
905e4a41
AD		 1490 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1491 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1492 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1493 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1494 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1495 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
ffff4772
PWJ		 1496 break;
1497 default:
905e4a41 1498 hw_dbg(hw, " Error on flow type input\n");
ffff4772
PWJ		 1499 return IXGBE_ERR_CONFIG;
1500 }
1501
905e4a41
AD		 1502 /* configure FDIRCMD register */
1503 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1504 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
69830529 1505 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
905e4a41
AD		 1506 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1507
1508 /*
1509 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1510 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1511 */
1512 fdirhashcmd = (u64)fdircmd << 32;
69830529 1513 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
ffff4772
PWJ		 1514
1515 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1516
69830529
AD		 1517 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1518
ffff4772
PWJ		 1519 return 0;
1520}
1521
45b9f509
AD		 1522/**
1523 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1524 * @input_mask: mask to be bit swapped
1525 *
1526 * The source and destination port masks for flow director are bit swapped
1527 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1528 * generate a correctly swapped value we need to bit swap the mask and that
1529 * is what is accomplished by this function.
1530 **/
1531static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks)
1532{
1533 u32 mask = ntohs(input_masks->dst_port_mask);
1534 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1535 mask |= ntohs(input_masks->src_port_mask);
1536 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1537 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1538 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1539 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1540}
1541
1542/*
1543 * These two macros are meant to address the fact that we have registers
1544 * that are either all or in part big-endian. As a result on big-endian
1545 * systems we will end up byte swapping the value to little-endian before
1546 * it is byte swapped again and written to the hardware in the original
1547 * big-endian format.
1548 */
1549#define IXGBE_STORE_AS_BE32(_value) \
1550 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1551 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1552
1553#define IXGBE_WRITE_REG_BE32(a, reg, value) \
1554 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1555
1556#define IXGBE_STORE_AS_BE16(_value) \
1557 (((u16)(_value) >> 8) | ((u16)(_value) << 8))
1558
ffff4772
PWJ		 1559/**
1560 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1561 * @hw: pointer to hardware structure
1562 * @input: input bitstream
9a713e7c
PW		 1563 * @input_masks: bitwise masks for relevant fields
1564 * @soft_id: software index into the silicon hash tables for filter storage
ffff4772
PWJ		 1565 * @queue: queue index to direct traffic to
1566 *
1567 * Note that the caller to this function must lock before calling, since the
1568 * hardware writes must be protected from one another.
1569 **/
1570s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
905e4a41 1571 union ixgbe_atr_input *input,
9a713e7c
PW		 1572 struct ixgbe_atr_input_masks *input_masks,
1573 u16 soft_id, u8 queue)
ffff4772 1574{
ffff4772 1575 u32 fdirhash;
45b9f509
AD		 1576 u32 fdircmd;
1577 u32 fdirport, fdirtcpm;
1578 u32 fdirvlan;
1579 /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
1580 u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX |
1581 IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
ffff4772
PWJ		 1582
1583 /*
45b9f509 1584 * Check flow_type formatting, and bail out before we touch the hardware
ffff4772
PWJ		 1585 * if there's a configuration issue
1586 */
45b9f509
AD		 1587 switch (input->formatted.flow_type) {
1588 case IXGBE_ATR_FLOW_TYPE_IPV4:
1589 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
1590 fdirm |= IXGBE_FDIRM_L4P;
1591 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1592 if (input_masks->dst_port_mask || input_masks->src_port_mask) {
1593 hw_dbg(hw, " Error on src/dst port mask\n");
1594 return IXGBE_ERR_CONFIG;
1595 }
1596 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1597 case IXGBE_ATR_FLOW_TYPE_UDPV4:
ffff4772
PWJ		 1598 break;
1599 default:
45b9f509 1600 hw_dbg(hw, " Error on flow type input\n");
ffff4772
PWJ		 1601 return IXGBE_ERR_CONFIG;
1602 }
1603
9a713e7c 1604 /*
45b9f509
AD		 1605 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1606 * are zero, then assume a full mask for that field. Also assume that
1607 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1608 * cannot be masked out in this implementation.
9a713e7c
PW		 1609 *
1610 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1611 * point in time.
1612 */
45b9f509
AD		 1613
1614 /* Program FDIRM */
1615 switch (ntohs(input_masks->vlan_id_mask) & 0xEFFF) {
1616 case 0xEFFF:
1617 /* Unmask VLAN ID - bit 0 and fall through to unmask prio */
1618 fdirm &= ~IXGBE_FDIRM_VLANID;
1619 case 0xE000:
1620 /* Unmask VLAN prio - bit 1 */
1621 fdirm &= ~IXGBE_FDIRM_VLANP;
9a713e7c 1622 break;
45b9f509
AD		 1623 case 0x0FFF:
1624 /* Unmask VLAN ID - bit 0 */
1625 fdirm &= ~IXGBE_FDIRM_VLANID;
9a713e7c 1626 break;
45b9f509
AD		 1627 case 0x0000:
1628 /* do nothing, vlans already masked */
9a713e7c 1629 break;
45b9f509
AD		 1630 default:
1631 hw_dbg(hw, " Error on VLAN mask\n");
1632 return IXGBE_ERR_CONFIG;
9a713e7c
PW		 1633 }
1634
45b9f509
AD		 1635 if (input_masks->flex_mask & 0xFFFF) {
1636 if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) {
1637 hw_dbg(hw, " Error on flexible byte mask\n");
1638 return IXGBE_ERR_CONFIG;
1639 }
1640 /* Unmask Flex Bytes - bit 4 */
1641 fdirm &= ~IXGBE_FDIRM_FLEX;
1642 }
9a713e7c
PW		 1643
1644 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
9a713e7c 1645 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
ffff4772 1646
45b9f509
AD		 1647 /* store the TCP/UDP port masks, bit reversed from port layout */
1648 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks);
1649
1650 /* write both the same so that UDP and TCP use the same mask */
1651 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1652 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1653
1654 /* store source and destination IP masks (big-enian) */
1655 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1656 ~input_masks->src_ip_mask[0]);
1657 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1658 ~input_masks->dst_ip_mask[0]);
1659
1660 /* Apply masks to input data */
1661 input->formatted.vlan_id &= input_masks->vlan_id_mask;
1662 input->formatted.flex_bytes &= input_masks->flex_mask;
1663 input->formatted.src_port &= input_masks->src_port_mask;
1664 input->formatted.dst_port &= input_masks->dst_port_mask;
1665 input->formatted.src_ip[0] &= input_masks->src_ip_mask[0];
1666 input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0];
1667
1668 /* record vlan (little-endian) and flex_bytes(big-endian) */
1669 fdirvlan =
1670 IXGBE_STORE_AS_BE16(ntohs(input->formatted.flex_bytes));
1671 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1672 fdirvlan |= ntohs(input->formatted.vlan_id);
1673 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1674
1675 /* record source and destination port (little-endian)*/
1676 fdirport = ntohs(input->formatted.dst_port);
1677 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1678 fdirport |= ntohs(input->formatted.src_port);
1679 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1680
1681 /* record the first 32 bits of the destination address (big-endian) */
1682 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1683
1684 /* record the source address (big-endian) */
1685 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1686
1687 /* configure FDIRCMD register */
1688 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1689 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1690 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1691 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1692
1693 /* we only want the bucket hash so drop the upper 16 bits */
1694 fdirhash = ixgbe_atr_compute_hash_82599(input,
1695 IXGBE_ATR_BUCKET_HASH_KEY);
1696 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
ffff4772
PWJ		 1697
1698 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1699 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1700
1701 return 0;
1702}
45b9f509 1703
11afc1b1
PW		 1704/**
1705 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1706 * @hw: pointer to hardware structure
1707 * @reg: analog register to read
1708 * @val: read value
1709 *
1710 * Performs read operation to Omer analog register specified.
1711 **/
7b25cdba 1712static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
11afc1b1
PW		 1713{
1714 u32 core_ctl;
1715
1716 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1717 (reg << 8));
1718 IXGBE_WRITE_FLUSH(hw);
1719 udelay(10);
1720 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1721 *val = (u8)core_ctl;
1722
1723 return 0;
1724}
1725
1726/**
1727 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1728 * @hw: pointer to hardware structure
1729 * @reg: atlas register to write
1730 * @val: value to write
1731 *
1732 * Performs write operation to Omer analog register specified.
1733 **/
7b25cdba 1734static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
11afc1b1
PW		 1735{
1736 u32 core_ctl;
1737
1738 core_ctl = (reg << 8) | val;
1739 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1740 IXGBE_WRITE_FLUSH(hw);
1741 udelay(10);
1742
1743 return 0;
1744}
1745
1746/**
1747 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1748 * @hw: pointer to hardware structure
1749 *
7184b7cf
ET		 1750 * Starts the hardware using the generic start_hw function
1751 * and the generation start_hw function.
1752 * Then performs revision-specific operations, if any.
11afc1b1 1753 **/
7b25cdba 1754static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
11afc1b1 1755{
7184b7cf 1756 s32 ret_val = 0;
11afc1b1 1757
794caeb2 1758 ret_val = ixgbe_start_hw_generic(hw);
7184b7cf
ET		 1759 if (ret_val != 0)
1760 goto out;
11afc1b1 1761
7184b7cf
ET		 1762 ret_val = ixgbe_start_hw_gen2(hw);
1763 if (ret_val != 0)
1764 goto out;
11afc1b1 1765
50ac58ba
PWJ		 1766 /* We need to run link autotry after the driver loads */
1767 hw->mac.autotry_restart = true;
e09ad236 1768 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
50ac58ba 1769
794caeb2
PWJ		 1770 if (ret_val == 0)
1771 ret_val = ixgbe_verify_fw_version_82599(hw);
7184b7cf 1772out:
794caeb2 1773 return ret_val;
11afc1b1
PW		 1774}
1775
1776/**
1777 * ixgbe_identify_phy_82599 - Get physical layer module
1778 * @hw: pointer to hardware structure
1779 *
1780 * Determines the physical layer module found on the current adapter.
21cc5b4f
ET		 1781 * If PHY already detected, maintains current PHY type in hw struct,
1782 * otherwise executes the PHY detection routine.
11afc1b1 1783 **/
d6cd8e0e 1784static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1785{
1786 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
21cc5b4f
ET		 1787
1788 /* Detect PHY if not unknown - returns success if already detected. */
11afc1b1 1789 status = ixgbe_identify_phy_generic(hw);
21cc5b4f
ET		 1790 if (status != 0) {
1791 /* 82599 10GBASE-T requires an external PHY */
1792 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1793 goto out;
1794 else
1795 status = ixgbe_identify_sfp_module_generic(hw);
1796 }
1797
1798 /* Set PHY type none if no PHY detected */
1799 if (hw->phy.type == ixgbe_phy_unknown) {
1800 hw->phy.type = ixgbe_phy_none;
1801 status = 0;
1802 }
1803
1804 /* Return error if SFP module has been detected but is not supported */
1805 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1806 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1807
1808out:
11afc1b1
PW		 1809 return status;
1810}
1811
1812/**
1813 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1814 * @hw: pointer to hardware structure
1815 *
1816 * Determines physical layer capabilities of the current configuration.
1817 **/
7b25cdba 1818static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1819{
1820 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 1821 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1822 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1823 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1824 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1825 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1826 u16 ext_ability = 0;
1339b9e9 1827 u8 comp_codes_10g = 0;
cb836a97 1828 u8 comp_codes_1g = 0;
11afc1b1 1829
04193058
PWJ		 1830 hw->phy.ops.identify(hw);
1831
21cc5b4f
ET		 1832 switch (hw->phy.type) {
1833 case ixgbe_phy_tn:
1834 case ixgbe_phy_aq:
1835 case ixgbe_phy_cu_unknown:
6b73e10d 1836 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
21cc5b4f 1837 &ext_ability);
6b73e10d 1838 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 1839 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 1840 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 1841 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 1842 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 1843 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1844 goto out;
21cc5b4f
ET		 1845 default:
1846 break;
04193058
PWJ		 1847 }
1848
1849 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1850 case IXGBE_AUTOC_LMS_1G_AN:
1851 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1852 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1853 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1854 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1855 goto out;
1856 } else
1857 /* SFI mode so read SFP module */
1858 goto sfp_check;
11afc1b1 1859 break;
04193058
PWJ		 1860 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1861 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1862 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1863 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1864 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 1865 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1866 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 1867 goto out;
1868 break;
1869 case IXGBE_AUTOC_LMS_10G_SERIAL:
1870 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1871 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1872 goto out;
1873 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1874 goto sfp_check;
1875 break;
1876 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1877 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1878 if (autoc & IXGBE_AUTOC_KX_SUPP)
1879 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1880 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1881 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1882 if (autoc & IXGBE_AUTOC_KR_SUPP)
1883 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1884 goto out;
1885 break;
1886 default:
1887 goto out;
1888 break;
1889 }
11afc1b1 1890
04193058
PWJ		 1891sfp_check:
1892 /* SFP check must be done last since DA modules are sometimes used to
1893 * test KR mode - we need to id KR mode correctly before SFP module.
1894 * Call identify_sfp because the pluggable module may have changed */
1895 hw->phy.ops.identify_sfp(hw);
1896 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1897 goto out;
1898
1899 switch (hw->phy.type) {
ea0a04df
DS		 1900 case ixgbe_phy_sfp_passive_tyco:
1901 case ixgbe_phy_sfp_passive_unknown:
04193058
PWJ		 1902 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1903 break;
ea0a04df
DS		 1904 case ixgbe_phy_sfp_ftl_active:
1905 case ixgbe_phy_sfp_active_unknown:
1906 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1907 break;
04193058
PWJ		 1908 case ixgbe_phy_sfp_avago:
1909 case ixgbe_phy_sfp_ftl:
1910 case ixgbe_phy_sfp_intel:
1911 case ixgbe_phy_sfp_unknown:
cb836a97
DS		 1912 hw->phy.ops.read_i2c_eeprom(hw,
1913 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
04193058
PWJ		 1914 hw->phy.ops.read_i2c_eeprom(hw,
1915 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1916 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 1917 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 1918 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 1919 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
cb836a97
DS		 1920 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1921 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
11afc1b1
PW		 1922 break;
1923 default:
11afc1b1
PW		 1924 break;
1925 }
1926
04193058 1927out:
11afc1b1
PW		 1928 return physical_layer;
1929}
1930
1931/**
1932 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1933 * @hw: pointer to hardware structure
1934 * @regval: register value to write to RXCTRL
1935 *
1936 * Enables the Rx DMA unit for 82599
1937 **/
7b25cdba 1938static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
11afc1b1
PW		 1939{
1940#define IXGBE_MAX_SECRX_POLL 30
1941 int i;
1942 int secrxreg;
1943
1944 /*
1945 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1946 * If traffic is incoming before we enable the Rx unit, it could hang
1947 * the Rx DMA unit. Therefore, make sure the security engine is
1948 * completely disabled prior to enabling the Rx unit.
1949 */
1950 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1951 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1952 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1953 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1954 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1955 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1956 break;
1957 else
8c7bea32 1958 /* Use interrupt-safe sleep just in case */
11afc1b1
PW		 1959 udelay(10);
1960 }
1961
1962 /* For informational purposes only */
1963 if (i >= IXGBE_MAX_SECRX_POLL)
1964 hw_dbg(hw, "Rx unit being enabled before security "
1965 "path fully disabled. Continuing with init.\n");
1966
1967 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1968 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1969 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1970 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1971 IXGBE_WRITE_FLUSH(hw);
1972
1973 return 0;
1974}
1975
794caeb2
PWJ		 1976/**
1977 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1978 * @hw: pointer to hardware structure
1979 *
1980 * Verifies that installed the firmware version is 0.6 or higher
1981 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1982 *
1983 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1984 * if the FW version is not supported.
1985 **/
1986static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
1987{
1988 s32 status = IXGBE_ERR_EEPROM_VERSION;
1989 u16 fw_offset, fw_ptp_cfg_offset;
1990 u16 fw_version = 0;
1991
1992 /* firmware check is only necessary for SFI devices */
1993 if (hw->phy.media_type != ixgbe_media_type_fiber) {
1994 status = 0;
1995 goto fw_version_out;
1996 }
1997
1998 /* get the offset to the Firmware Module block */
1999 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2000
2001 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2002 goto fw_version_out;
2003
2004 /* get the offset to the Pass Through Patch Configuration block */
2005 hw->eeprom.ops.read(hw, (fw_offset +
2006 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2007 &fw_ptp_cfg_offset);
2008
2009 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2010 goto fw_version_out;
2011
2012 /* get the firmware version */
2013 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2014 IXGBE_FW_PATCH_VERSION_4),
2015 &fw_version);
2016
2017 if (fw_version > 0x5)
2018 status = 0;
2019
2020fw_version_out:
2021 return status;
2022}
2023
0fa6d832
ET		 2024/**
2025 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2026 * @hw: pointer to hardware structure
2027 *
2028 * Returns true if the LESM FW module is present and enabled. Otherwise
2029 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2030 **/
2031static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2032{
2033 bool lesm_enabled = false;
2034 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2035 s32 status;
2036
2037 /* get the offset to the Firmware Module block */
2038 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2039
2040 if ((status != 0) ||
2041 (fw_offset == 0) || (fw_offset == 0xFFFF))
2042 goto out;
2043
2044 /* get the offset to the LESM Parameters block */
2045 status = hw->eeprom.ops.read(hw, (fw_offset +
2046 IXGBE_FW_LESM_PARAMETERS_PTR),
2047 &fw_lesm_param_offset);
2048
2049 if ((status != 0) ||
2050 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2051 goto out;
2052
2053 /* get the lesm state word */
2054 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2055 IXGBE_FW_LESM_STATE_1),
2056 &fw_lesm_state);
2057
2058 if ((status == 0) &&
2059 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2060 lesm_enabled = true;
2061
2062out:
2063 return lesm_enabled;
2064}
2065
68c7005d
ET		 2066/**
2067 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2068 * fastest available method
2069 *
2070 * @hw: pointer to hardware structure
2071 * @offset: offset of word in EEPROM to read
2072 * @words: number of words
2073 * @data: word(s) read from the EEPROM
2074 *
2075 * Retrieves 16 bit word(s) read from EEPROM
2076 **/
2077static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2078 u16 words, u16 *data)
2079{
2080 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2081 s32 ret_val = IXGBE_ERR_CONFIG;
2082
2083 /*
2084 * If EEPROM is detected and can be addressed using 14 bits,
2085 * use EERD otherwise use bit bang
2086 */
2087 if ((eeprom->type == ixgbe_eeprom_spi) &&
2088 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2089 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2090 data);
2091 else
2092 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2093 words,
2094 data);
2095
2096 return ret_val;
2097}
2098
0665b09f
ET		 2099/**
2100 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2101 * fastest available method
2102 *
2103 * @hw: pointer to hardware structure
2104 * @offset: offset of word in the EEPROM to read
2105 * @data: word read from the EEPROM
2106 *
2107 * Reads a 16 bit word from the EEPROM
2108 **/
2109static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2110 u16 offset, u16 *data)
2111{
2112 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2113 s32 ret_val = IXGBE_ERR_CONFIG;
2114
2115 /*
2116 * If EEPROM is detected and can be addressed using 14 bits,
2117 * use EERD otherwise use bit bang
2118 */
2119 if ((eeprom->type == ixgbe_eeprom_spi) &&
2120 (offset <= IXGBE_EERD_MAX_ADDR))
2121 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2122 else
2123 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2124
2125 return ret_val;
2126}
2127
11afc1b1
PW		 2128static struct ixgbe_mac_operations mac_ops_82599 = {
2129 .init_hw = &ixgbe_init_hw_generic,
2130 .reset_hw = &ixgbe_reset_hw_82599,
2131 .start_hw = &ixgbe_start_hw_82599,
2132 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2133 .get_media_type = &ixgbe_get_media_type_82599,
2134 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2135 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2136 .get_mac_addr = &ixgbe_get_mac_addr_generic,
21ce849b 2137 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
b776d104 2138 .get_device_caps = &ixgbe_get_device_caps_generic,
a391f1d5 2139 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
11afc1b1
PW		 2140 .stop_adapter = &ixgbe_stop_adapter_generic,
2141 .get_bus_info = &ixgbe_get_bus_info_generic,
2142 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2143 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2144 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2145 .setup_link = &ixgbe_setup_mac_link_82599,
21ce849b 2146 .check_link = &ixgbe_check_mac_link_generic,
11afc1b1
PW		 2147 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2148 .led_on = &ixgbe_led_on_generic,
2149 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 2150 .blink_led_start = &ixgbe_blink_led_start_generic,
2151 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 2152 .set_rar = &ixgbe_set_rar_generic,
2153 .clear_rar = &ixgbe_clear_rar_generic,
21ce849b
MC		 2154 .set_vmdq = &ixgbe_set_vmdq_generic,
2155 .clear_vmdq = &ixgbe_clear_vmdq_generic,
11afc1b1 2156 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
11afc1b1
PW		 2157 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2158 .enable_mc = &ixgbe_enable_mc_generic,
2159 .disable_mc = &ixgbe_disable_mc_generic,
21ce849b
MC		 2160 .clear_vfta = &ixgbe_clear_vfta_generic,
2161 .set_vfta = &ixgbe_set_vfta_generic,
2162 .fc_enable = &ixgbe_fc_enable_generic,
2163 .init_uta_tables = &ixgbe_init_uta_tables_generic,
11afc1b1 2164 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
a985b6c3
GR		 2165 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2166 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
5e655105
DS		 2167 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2168 .release_swfw_sync = &ixgbe_release_swfw_sync,
2169
11afc1b1
PW		 2170};
2171
2172static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
037c6d0a 2173 .init_params = &ixgbe_init_eeprom_params_generic,
0665b09f 2174 .read = &ixgbe_read_eeprom_82599,
68c7005d 2175 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
037c6d0a 2176 .write = &ixgbe_write_eeprom_generic,
68c7005d 2177 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
037c6d0a
ET		 2178 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2179 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2180 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
11afc1b1
PW		 2181};
2182
2183static struct ixgbe_phy_operations phy_ops_82599 = {
037c6d0a
ET		 2184 .identify = &ixgbe_identify_phy_82599,
2185 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2186 .init = &ixgbe_init_phy_ops_82599,
2187 .reset = &ixgbe_reset_phy_generic,
2188 .read_reg = &ixgbe_read_phy_reg_generic,
2189 .write_reg = &ixgbe_write_phy_reg_generic,
2190 .setup_link = &ixgbe_setup_phy_link_generic,
2191 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2192 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2193 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2194 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2195 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2196 .check_overtemp = &ixgbe_tn_check_overtemp,
11afc1b1
PW		 2197};
2198
2199struct ixgbe_info ixgbe_82599_info = {
2200 .mac = ixgbe_mac_82599EB,
2201 .get_invariants = &ixgbe_get_invariants_82599,
2202 .mac_ops = &mac_ops_82599,
2203 .eeprom_ops = &eeprom_ops_82599,
2204 .phy_ops = &phy_ops_82599,
a391f1d5 2205 .mbx_ops = &mbx_ops_generic,
11afc1b1 2206};
Linux kernel - Deliverables
This page took 0.38119 seconds and 5 git commands to generate.