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ixgbe: Allow the VF driver to be loaded before the PF driver
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
11afc1b1
PW		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
096a58fd 34#include "ixgbe_mbx.h"
11afc1b1
PW		 35
36#define IXGBE_82599_MAX_TX_QUEUES 128
37#define IXGBE_82599_MAX_RX_QUEUES 128
38#define IXGBE_82599_RAR_ENTRIES 128
39#define IXGBE_82599_MC_TBL_SIZE 128
40#define IXGBE_82599_VFT_TBL_SIZE 128
41
8620a103
MC		 42s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
43 ixgbe_link_speed speed,
44 bool autoneg,
45 bool autoneg_wait_to_complete);
cd7e1f0b
DS		 46static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
48 bool autoneg,
49 bool autoneg_wait_to_complete);
8620a103
MC		 50s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
51 bool autoneg_wait_to_complete);
52s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
53 ixgbe_link_speed speed,
54 bool autoneg,
55 bool autoneg_wait_to_complete);
11afc1b1
PW		 56static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
57 ixgbe_link_speed *speed,
58 bool *autoneg);
8620a103
MC		 59static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed speed,
61 bool autoneg,
62 bool autoneg_wait_to_complete);
794caeb2 63static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
11afc1b1 64
7b25cdba 65static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 66{
67 struct ixgbe_mac_info *mac = &hw->mac;
68 if (hw->phy.multispeed_fiber) {
69 /* Set up dual speed SFP+ support */
8620a103 70 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
11afc1b1 71 } else {
cd7e1f0b
DS		 72 if ((mac->ops.get_media_type(hw) ==
73 ixgbe_media_type_backplane) &&
74 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
75 hw->phy.smart_speed == ixgbe_smart_speed_on))
76 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
77 else
78 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
11afc1b1
PW		 79 }
80}
81
7b25cdba 82static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 83{
84 s32 ret_val = 0;
85 u16 list_offset, data_offset, data_value;
86
87 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
88 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 89
90 hw->phy.ops.reset = NULL;
91
11afc1b1
PW		 92 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
93 &data_offset);
94
95 if (ret_val != 0)
96 goto setup_sfp_out;
97
aa5aec88
PWJ		 98 /* PHY config will finish before releasing the semaphore */
99 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
100 if (ret_val != 0) {
101 ret_val = IXGBE_ERR_SWFW_SYNC;
102 goto setup_sfp_out;
103 }
104
11afc1b1
PW		 105 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
106 while (data_value != 0xffff) {
107 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
108 IXGBE_WRITE_FLUSH(hw);
109 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
110 }
1479ad4f
PWJ		 111 /* Now restart DSP by setting Restart_AN */
112 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
113 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
aa5aec88
PWJ		 114
115 /* Release the semaphore */
116 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
117 /* Delay obtaining semaphore again to allow FW access */
118 msleep(hw->eeprom.semaphore_delay);
11afc1b1
PW		 119 }
120
121setup_sfp_out:
122 return ret_val;
123}
124
125/**
126 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
127 * @hw: pointer to hardware structure
128 *
129 * Read PCIe configuration space, and get the MSI-X vector count from
130 * the capabilities table.
131 **/
7b25cdba 132static u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 133{
134 struct ixgbe_adapter *adapter = hw->back;
135 u16 msix_count;
136 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
137 &msix_count);
138 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
139
140 /* MSI-X count is zero-based in HW, so increment to give proper value */
141 msix_count++;
142
143 return msix_count;
144}
145
146static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
147{
148 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 149
04f165ef 150 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 151
04f165ef
PW		 152 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
153 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
154 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
155 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
156 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
157 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
11afc1b1 158
04f165ef
PW		 159 return 0;
160}
11afc1b1 161
04f165ef
PW		 162/**
163 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
164 * @hw: pointer to hardware structure
165 *
166 * Initialize any function pointers that were not able to be
167 * set during get_invariants because the PHY/SFP type was
168 * not known. Perform the SFP init if necessary.
169 *
170 **/
7b25cdba 171static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
04f165ef
PW		 172{
173 struct ixgbe_mac_info *mac = &hw->mac;
174 struct ixgbe_phy_info *phy = &hw->phy;
175 s32 ret_val = 0;
11afc1b1 176
04f165ef
PW		 177 /* Identify the PHY or SFP module */
178 ret_val = phy->ops.identify(hw);
179
180 /* Setup function pointers based on detected SFP module and speeds */
181 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 182
183 /* If copper media, overwrite with copper function pointers */
184 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
185 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
11afc1b1
PW		 186 mac->ops.get_link_capabilities =
187 &ixgbe_get_copper_link_capabilities_82599;
188 }
189
04f165ef 190 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 191 switch (hw->phy.type) {
192 case ixgbe_phy_tn:
193 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
194 phy->ops.get_firmware_version =
04f165ef 195 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 196 break;
197 default:
198 break;
199 }
200
11afc1b1
PW		 201 return ret_val;
202}
203
204/**
205 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
206 * @hw: pointer to hardware structure
207 * @speed: pointer to link speed
208 * @negotiation: true when autoneg or autotry is enabled
209 *
210 * Determines the link capabilities by reading the AUTOC register.
211 **/
7b25cdba
DS		 212static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
213 ixgbe_link_speed *speed,
214 bool *negotiation)
11afc1b1
PW		 215{
216 s32 status = 0;
1eb99d5a 217 u32 autoc = 0;
11afc1b1 218
1eb99d5a
PW		 219 /*
220 * Determine link capabilities based on the stored value of AUTOC,
221 * which represents EEPROM defaults. If AUTOC value has not been
222 * stored, use the current register value.
223 */
224 if (hw->mac.orig_link_settings_stored)
225 autoc = hw->mac.orig_autoc;
226 else
227 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
228
229 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 230 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
231 *speed = IXGBE_LINK_SPEED_1GB_FULL;
232 *negotiation = false;
233 break;
234
235 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
236 *speed = IXGBE_LINK_SPEED_10GB_FULL;
237 *negotiation = false;
238 break;
239
240 case IXGBE_AUTOC_LMS_1G_AN:
241 *speed = IXGBE_LINK_SPEED_1GB_FULL;
242 *negotiation = true;
243 break;
244
245 case IXGBE_AUTOC_LMS_10G_SERIAL:
246 *speed = IXGBE_LINK_SPEED_10GB_FULL;
247 *negotiation = false;
248 break;
249
250 case IXGBE_AUTOC_LMS_KX4_KX_KR:
251 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
252 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 253 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 254 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 255 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 256 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 257 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 258 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
259 *negotiation = true;
260 break;
261
262 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
263 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 264 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 265 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 266 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 267 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 268 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 269 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
270 *negotiation = true;
271 break;
272
273 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
274 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
275 *negotiation = false;
276 break;
277
278 default:
279 status = IXGBE_ERR_LINK_SETUP;
280 goto out;
281 break;
282 }
283
284 if (hw->phy.multispeed_fiber) {
285 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
286 IXGBE_LINK_SPEED_1GB_FULL;
287 *negotiation = true;
288 }
289
290out:
291 return status;
292}
293
294/**
295 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
296 * @hw: pointer to hardware structure
297 * @speed: pointer to link speed
298 * @autoneg: boolean auto-negotiation value
299 *
300 * Determines the link capabilities by reading the AUTOC register.
301 **/
302static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
303 ixgbe_link_speed *speed,
304 bool *autoneg)
305{
306 s32 status = IXGBE_ERR_LINK_SETUP;
307 u16 speed_ability;
308
309 *speed = 0;
310 *autoneg = true;
311
6b73e10d 312 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
11afc1b1
PW		 313 &speed_ability);
314
315 if (status == 0) {
6b73e10d 316 if (speed_ability & MDIO_SPEED_10G)
11afc1b1 317 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
6b73e10d 318 if (speed_ability & MDIO_PMA_SPEED_1000)
11afc1b1
PW		 319 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
320 }
321
322 return status;
323}
324
325/**
326 * ixgbe_get_media_type_82599 - Get media type
327 * @hw: pointer to hardware structure
328 *
329 * Returns the media type (fiber, copper, backplane)
330 **/
7b25cdba 331static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 332{
333 enum ixgbe_media_type media_type;
334
335 /* Detect if there is a copper PHY attached. */
336 if (hw->phy.type == ixgbe_phy_cu_unknown ||
337 hw->phy.type == ixgbe_phy_tn) {
338 media_type = ixgbe_media_type_copper;
339 goto out;
340 }
341
342 switch (hw->device_id) {
11afc1b1 343 case IXGBE_DEV_ID_82599_KX4:
dbfec662 344 case IXGBE_DEV_ID_82599_KX4_MEZZ:
312eb931 345 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
74757d49 346 case IXGBE_DEV_ID_82599_KR:
1fcf03e6 347 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 348 /* Default device ID is mezzanine card KX/KX4 */
349 media_type = ixgbe_media_type_backplane;
350 break;
351 case IXGBE_DEV_ID_82599_SFP:
38ad1c8e 352 case IXGBE_DEV_ID_82599_SFP_EM:
11afc1b1
PW		 353 media_type = ixgbe_media_type_fiber;
354 break;
8911184f 355 case IXGBE_DEV_ID_82599_CX4:
6b1be199 356 media_type = ixgbe_media_type_cx4;
8911184f 357 break;
11afc1b1
PW		 358 default:
359 media_type = ixgbe_media_type_unknown;
360 break;
361 }
362out:
363 return media_type;
364}
365
366/**
8620a103 367 * ixgbe_start_mac_link_82599 - Setup MAC link settings
11afc1b1 368 * @hw: pointer to hardware structure
8620a103 369 * @autoneg_wait_to_complete: true when waiting for completion is needed
11afc1b1
PW		 370 *
371 * Configures link settings based on values in the ixgbe_hw struct.
372 * Restarts the link. Performs autonegotiation if needed.
373 **/
8620a103
MC		 374s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
375 bool autoneg_wait_to_complete)
11afc1b1
PW		 376{
377 u32 autoc_reg;
378 u32 links_reg;
379 u32 i;
380 s32 status = 0;
381
382 /* Restart link */
383 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
384 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
385 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
386
387 /* Only poll for autoneg to complete if specified to do so */
8620a103 388 if (autoneg_wait_to_complete) {
11afc1b1
PW		 389 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
390 IXGBE_AUTOC_LMS_KX4_KX_KR ||
391 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
392 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
393 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
394 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
395 links_reg = 0; /* Just in case Autoneg time = 0 */
396 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
397 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
398 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
399 break;
400 msleep(100);
401 }
402 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
403 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
404 hw_dbg(hw, "Autoneg did not complete.\n");
405 }
406 }
407 }
408
11afc1b1
PW		 409 /* Add delay to filter out noises during initial link setup */
410 msleep(50);
411
412 return status;
413}
414
415/**
8620a103 416 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
11afc1b1
PW		 417 * @hw: pointer to hardware structure
418 * @speed: new link speed
419 * @autoneg: true if autonegotiation enabled
420 * @autoneg_wait_to_complete: true when waiting for completion is needed
421 *
422 * Set the link speed in the AUTOC register and restarts link.
423 **/
8620a103
MC		 424s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
425 ixgbe_link_speed speed,
426 bool autoneg,
427 bool autoneg_wait_to_complete)
11afc1b1
PW		 428{
429 s32 status = 0;
430 ixgbe_link_speed phy_link_speed;
431 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
432 u32 speedcnt = 0;
433 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
434 bool link_up = false;
435 bool negotiation;
50ac58ba 436 int i;
11afc1b1
PW		 437
438 /* Mask off requested but non-supported speeds */
439 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
440 speed &= phy_link_speed;
441
50ac58ba
PWJ		 442 /*
443 * When the driver changes the link speeds that it can support,
444 * it sets autotry_restart to true to indicate that we need to
445 * initiate a new autotry session with the link partner. To do
446 * so, we set the speed then disable and re-enable the tx laser, to
447 * alert the link partner that it also needs to restart autotry on its
448 * end. This is consistent with true clause 37 autoneg, which also
449 * involves a loss of signal.
450 */
451
11afc1b1
PW		 452 /*
453 * Try each speed one by one, highest priority first. We do this in
454 * software because 10gb fiber doesn't support speed autonegotiation.
455 */
456 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
457 speedcnt++;
458 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
459
50ac58ba
PWJ		 460 /* If we already have link at this speed, just jump out */
461 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
462
463 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
464 goto out;
465
466 /* Set the module link speed */
11afc1b1
PW		 467 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
468 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
469
50ac58ba
PWJ		 470 /* Allow module to change analog characteristics (1G->10G) */
471 msleep(40);
11afc1b1 472
8620a103
MC		 473 status = ixgbe_setup_mac_link_82599(hw,
474 IXGBE_LINK_SPEED_10GB_FULL,
475 autoneg,
476 autoneg_wait_to_complete);
50ac58ba 477 if (status != 0)
c3c74327 478 return status;
50ac58ba
PWJ		 479
480 /* Flap the tx laser if it has not already been done */
481 if (hw->mac.autotry_restart) {
482 /* Disable tx laser; allow 100us to go dark per spec */
483 esdp_reg |= IXGBE_ESDP_SDP3;
484 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
485 udelay(100);
486
487 /* Enable tx laser; allow 2ms to light up per spec */
488 esdp_reg &= ~IXGBE_ESDP_SDP3;
489 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
490 msleep(2);
491
492 hw->mac.autotry_restart = false;
493 }
494
cd7e1f0b
DS		 495 /*
496 * Wait for the controller to acquire link. Per IEEE 802.3ap,
497 * Section 73.10.2, we may have to wait up to 500ms if KR is
498 * attempted. 82599 uses the same timing for 10g SFI.
499 */
500
50ac58ba
PWJ		 501 for (i = 0; i < 5; i++) {
502 /* Wait for the link partner to also set speed */
503 msleep(100);
504
505 /* If we have link, just jump out */
506 hw->mac.ops.check_link(hw, &phy_link_speed,
507 &link_up, false);
508 if (link_up)
509 goto out;
510 }
11afc1b1
PW		 511 }
512
513 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
514 speedcnt++;
515 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
516 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
517
50ac58ba
PWJ		 518 /* If we already have link at this speed, just jump out */
519 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
520
521 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
522 goto out;
523
524 /* Set the module link speed */
11afc1b1
PW		 525 esdp_reg &= ~IXGBE_ESDP_SDP5;
526 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
527 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
528
50ac58ba
PWJ		 529 /* Allow module to change analog characteristics (10G->1G) */
530 msleep(40);
11afc1b1 531
8620a103 532 status = ixgbe_setup_mac_link_82599(hw,
50ac58ba
PWJ		 533 IXGBE_LINK_SPEED_1GB_FULL,
534 autoneg,
535 autoneg_wait_to_complete);
536 if (status != 0)
c3c74327 537 return status;
50ac58ba
PWJ		 538
539 /* Flap the tx laser if it has not already been done */
540 if (hw->mac.autotry_restart) {
541 /* Disable tx laser; allow 100us to go dark per spec */
542 esdp_reg |= IXGBE_ESDP_SDP3;
543 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
544 udelay(100);
545
546 /* Enable tx laser; allow 2ms to light up per spec */
547 esdp_reg &= ~IXGBE_ESDP_SDP3;
548 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
549 msleep(2);
550
551 hw->mac.autotry_restart = false;
552 }
553
554 /* Wait for the link partner to also set speed */
555 msleep(100);
11afc1b1
PW		 556
557 /* If we have link, just jump out */
558 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
559 if (link_up)
560 goto out;
561 }
562
563 /*
564 * We didn't get link. Configure back to the highest speed we tried,
565 * (if there was more than one). We call ourselves back with just the
566 * single highest speed that the user requested.
567 */
568 if (speedcnt > 1)
8620a103
MC		 569 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
570 highest_link_speed,
571 autoneg,
572 autoneg_wait_to_complete);
11afc1b1
PW		 573
574out:
c3c74327
MC		 575 /* Set autoneg_advertised value based on input link speed */
576 hw->phy.autoneg_advertised = 0;
577
578 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
579 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
580
581 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
582 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
583
11afc1b1
PW		 584 return status;
585}
586
cd7e1f0b
DS		 587/**
588 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
589 * @hw: pointer to hardware structure
590 * @speed: new link speed
591 * @autoneg: true if autonegotiation enabled
592 * @autoneg_wait_to_complete: true when waiting for completion is needed
593 *
594 * Implements the Intel SmartSpeed algorithm.
595 **/
596static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
597 ixgbe_link_speed speed, bool autoneg,
598 bool autoneg_wait_to_complete)
599{
600 s32 status = 0;
601 ixgbe_link_speed link_speed;
602 s32 i, j;
603 bool link_up = false;
604 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
605
606 hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n");
607
608 /* Set autoneg_advertised value based on input link speed */
609 hw->phy.autoneg_advertised = 0;
610
611 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
612 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
613
614 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
615 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
616
617 if (speed & IXGBE_LINK_SPEED_100_FULL)
618 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
619
620 /*
621 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
622 * autoneg advertisement if link is unable to be established at the
623 * highest negotiated rate. This can sometimes happen due to integrity
624 * issues with the physical media connection.
625 */
626
627 /* First, try to get link with full advertisement */
628 hw->phy.smart_speed_active = false;
629 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
630 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
631 autoneg_wait_to_complete);
632 if (status)
633 goto out;
634
635 /*
636 * Wait for the controller to acquire link. Per IEEE 802.3ap,
637 * Section 73.10.2, we may have to wait up to 500ms if KR is
638 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
639 * Table 9 in the AN MAS.
640 */
641 for (i = 0; i < 5; i++) {
642 mdelay(100);
643
644 /* If we have link, just jump out */
645 hw->mac.ops.check_link(hw, &link_speed,
646 &link_up, false);
647 if (link_up)
648 goto out;
649 }
650 }
651
652 /*
653 * We didn't get link. If we advertised KR plus one of KX4/KX
654 * (or BX4/BX), then disable KR and try again.
655 */
656 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
657 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
658 goto out;
659
660 /* Turn SmartSpeed on to disable KR support */
661 hw->phy.smart_speed_active = true;
662 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
663 autoneg_wait_to_complete);
664 if (status)
665 goto out;
666
667 /*
668 * Wait for the controller to acquire link. 600ms will allow for
669 * the AN link_fail_inhibit_timer as well for multiple cycles of
670 * parallel detect, both 10g and 1g. This allows for the maximum
671 * connect attempts as defined in the AN MAS table 73-7.
672 */
673 for (i = 0; i < 6; i++) {
674 mdelay(100);
675
676 /* If we have link, just jump out */
677 hw->mac.ops.check_link(hw, &link_speed,
678 &link_up, false);
679 if (link_up)
680 goto out;
681 }
682
683 /* We didn't get link. Turn SmartSpeed back off. */
684 hw->phy.smart_speed_active = false;
685 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
686 autoneg_wait_to_complete);
687
688out:
689 return status;
690}
691
11afc1b1
PW		 692/**
693 * ixgbe_check_mac_link_82599 - Determine link and speed status
694 * @hw: pointer to hardware structure
695 * @speed: pointer to link speed
696 * @link_up: true when link is up
697 * @link_up_wait_to_complete: bool used to wait for link up or not
698 *
699 * Reads the links register to determine if link is up and the current speed
700 **/
7b25cdba
DS		 701static s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
702 ixgbe_link_speed *speed,
703 bool *link_up,
704 bool link_up_wait_to_complete)
11afc1b1
PW		 705{
706 u32 links_reg;
707 u32 i;
708
709 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
710 if (link_up_wait_to_complete) {
711 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
712 if (links_reg & IXGBE_LINKS_UP) {
713 *link_up = true;
714 break;
715 } else {
716 *link_up = false;
717 }
718 msleep(100);
719 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
720 }
721 } else {
722 if (links_reg & IXGBE_LINKS_UP)
723 *link_up = true;
724 else
725 *link_up = false;
726 }
727
728 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
729 IXGBE_LINKS_SPEED_10G_82599)
730 *speed = IXGBE_LINK_SPEED_10GB_FULL;
731 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
732 IXGBE_LINKS_SPEED_1G_82599)
733 *speed = IXGBE_LINK_SPEED_1GB_FULL;
734 else
735 *speed = IXGBE_LINK_SPEED_100_FULL;
736
620fa036
MC		 737 /* if link is down, zero out the current_mode */
738 if (*link_up == false) {
739 hw->fc.current_mode = ixgbe_fc_none;
740 hw->fc.fc_was_autonegged = false;
741 }
11afc1b1
PW		 742
743 return 0;
744}
745
746/**
8620a103 747 * ixgbe_setup_mac_link_82599 - Set MAC link speed
11afc1b1
PW		 748 * @hw: pointer to hardware structure
749 * @speed: new link speed
750 * @autoneg: true if autonegotiation enabled
751 * @autoneg_wait_to_complete: true when waiting for completion is needed
752 *
753 * Set the link speed in the AUTOC register and restarts link.
754 **/
8620a103
MC		 755s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
756 ixgbe_link_speed speed, bool autoneg,
757 bool autoneg_wait_to_complete)
11afc1b1
PW		 758{
759 s32 status = 0;
760 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
761 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
50ac58ba 762 u32 start_autoc = autoc;
1eb99d5a 763 u32 orig_autoc = 0;
11afc1b1
PW		 764 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
765 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
766 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
767 u32 links_reg;
768 u32 i;
769 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
770
771 /* Check to see if speed passed in is supported. */
772 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
773 speed &= link_capabilities;
774
50ac58ba
PWJ		 775 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
776 status = IXGBE_ERR_LINK_SETUP;
777 goto out;
778 }
779
1eb99d5a
PW		 780 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
781 if (hw->mac.orig_link_settings_stored)
782 orig_autoc = hw->mac.orig_autoc;
783 else
784 orig_autoc = autoc;
785
786
50ac58ba
PWJ		 787 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
788 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
789 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
11afc1b1
PW		 790 /* Set KX4/KX/KR support according to speed requested */
791 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
792 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 793 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 794 autoc |= IXGBE_AUTOC_KX4_SUPP;
cd7e1f0b
DS		 795 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
796 (hw->phy.smart_speed_active == false))
11afc1b1
PW		 797 autoc |= IXGBE_AUTOC_KR_SUPP;
798 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
799 autoc |= IXGBE_AUTOC_KX_SUPP;
800 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
801 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
802 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
803 /* Switch from 1G SFI to 10G SFI if requested */
804 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
805 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
806 autoc &= ~IXGBE_AUTOC_LMS_MASK;
807 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
808 }
809 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
810 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
811 /* Switch from 10G SFI to 1G SFI if requested */
812 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
813 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
814 autoc &= ~IXGBE_AUTOC_LMS_MASK;
815 if (autoneg)
816 autoc |= IXGBE_AUTOC_LMS_1G_AN;
817 else
818 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
819 }
820 }
821
50ac58ba 822 if (autoc != start_autoc) {
11afc1b1
PW		 823 /* Restart link */
824 autoc |= IXGBE_AUTOC_AN_RESTART;
825 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
826
827 /* Only poll for autoneg to complete if specified to do so */
828 if (autoneg_wait_to_complete) {
829 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
830 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
831 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
832 links_reg = 0; /*Just in case Autoneg time=0*/
833 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
834 links_reg =
835 IXGBE_READ_REG(hw, IXGBE_LINKS);
836 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
837 break;
838 msleep(100);
839 }
840 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
841 status =
842 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
843 hw_dbg(hw, "Autoneg did not "
844 "complete.\n");
845 }
846 }
847 }
848
11afc1b1
PW		 849 /* Add delay to filter out noises during initial link setup */
850 msleep(50);
851 }
852
50ac58ba 853out:
11afc1b1
PW		 854 return status;
855}
856
857/**
8620a103 858 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
11afc1b1
PW		 859 * @hw: pointer to hardware structure
860 * @speed: new link speed
861 * @autoneg: true if autonegotiation enabled
862 * @autoneg_wait_to_complete: true if waiting is needed to complete
863 *
864 * Restarts link on PHY and MAC based on settings passed in.
865 **/
8620a103
MC		 866static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
867 ixgbe_link_speed speed,
868 bool autoneg,
869 bool autoneg_wait_to_complete)
11afc1b1
PW		 870{
871 s32 status;
872
873 /* Setup the PHY according to input speed */
874 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
875 autoneg_wait_to_complete);
876 /* Set up MAC */
8620a103 877 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
11afc1b1
PW		 878
879 return status;
880}
881
882/**
883 * ixgbe_reset_hw_82599 - Perform hardware reset
884 * @hw: pointer to hardware structure
885 *
886 * Resets the hardware by resetting the transmit and receive units, masks
887 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
888 * reset.
889 **/
7b25cdba 890static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 891{
892 s32 status = 0;
c9205697 893 u32 ctrl;
11afc1b1
PW		 894 u32 i;
895 u32 autoc;
896 u32 autoc2;
897
898 /* Call adapter stop to disable tx/rx and clear interrupts */
899 hw->mac.ops.stop_adapter(hw);
900
553b4497 901 /* PHY ops must be identified and initialized prior to reset */
04f165ef 902
553b4497
PW		 903 /* Init PHY and function pointers, perform SFP setup */
904 status = hw->phy.ops.init(hw);
04f165ef 905
553b4497
PW		 906 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
907 goto reset_hw_out;
04f165ef 908
553b4497
PW		 909 /* Setup SFP module if there is one present. */
910 if (hw->phy.sfp_setup_needed) {
911 status = hw->mac.ops.setup_sfp(hw);
912 hw->phy.sfp_setup_needed = false;
04f165ef 913 }
11afc1b1 914
553b4497
PW		 915 /* Reset PHY */
916 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
917 hw->phy.ops.reset(hw);
918
11afc1b1
PW		 919 /*
920 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
921 * access and verify no pending requests before reset
922 */
04f165ef
PW		 923 status = ixgbe_disable_pcie_master(hw);
924 if (status != 0) {
11afc1b1
PW		 925 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
926 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
927 }
928
929 /*
930 * Issue global reset to the MAC. This needs to be a SW reset.
931 * If link reset is used, it might reset the MAC when mng is using it
932 */
933 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
934 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
935 IXGBE_WRITE_FLUSH(hw);
936
937 /* Poll for reset bit to self-clear indicating reset is complete */
938 for (i = 0; i < 10; i++) {
939 udelay(1);
940 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
941 if (!(ctrl & IXGBE_CTRL_RST))
942 break;
943 }
944 if (ctrl & IXGBE_CTRL_RST) {
945 status = IXGBE_ERR_RESET_FAILED;
946 hw_dbg(hw, "Reset polling failed to complete.\n");
947 }
11afc1b1
PW		 948
949 msleep(50);
950
11afc1b1
PW		 951 /*
952 * Store the original AUTOC/AUTOC2 values if they have not been
953 * stored off yet. Otherwise restore the stored original
954 * values since the reset operation sets back to defaults.
955 */
956 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
957 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
958 if (hw->mac.orig_link_settings_stored == false) {
959 hw->mac.orig_autoc = autoc;
960 hw->mac.orig_autoc2 = autoc2;
961 hw->mac.orig_link_settings_stored = true;
4df10466 962 } else {
11afc1b1
PW		 963 if (autoc != hw->mac.orig_autoc)
964 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
965 IXGBE_AUTOC_AN_RESTART));
966
967 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
968 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
969 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
970 autoc2 |= (hw->mac.orig_autoc2 &
971 IXGBE_AUTOC2_UPPER_MASK);
972 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
973 }
974 }
975
aca6bee7
WJP		 976 /*
977 * Store MAC address from RAR0, clear receive address registers, and
978 * clear the multicast table. Also reset num_rar_entries to 128,
979 * since we modify this value when programming the SAN MAC address.
980 */
981 hw->mac.num_rar_entries = 128;
982 hw->mac.ops.init_rx_addrs(hw);
983
11afc1b1
PW		 984 /* Store the permanent mac address */
985 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
986
0365e6e4
PW		 987 /* Store the permanent SAN mac address */
988 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
989
aca6bee7
WJP		 990 /* Add the SAN MAC address to the RAR only if it's a valid address */
991 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
992 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
993 hw->mac.san_addr, 0, IXGBE_RAH_AV);
994
995 /* Reserve the last RAR for the SAN MAC address */
996 hw->mac.num_rar_entries--;
997 }
998
383ff34b
YZ		 999 /* Store the alternative WWNN/WWPN prefix */
1000 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1001 &hw->mac.wwpn_prefix);
1002
04f165ef 1003reset_hw_out:
11afc1b1
PW		 1004 return status;
1005}
1006
1007/**
1008 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
1009 * @hw: pointer to hardware struct
1010 * @rar: receive address register index to disassociate
1011 * @vmdq: VMDq pool index to remove from the rar
1012 **/
7b25cdba 1013static s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
11afc1b1
PW		 1014{
1015 u32 mpsar_lo, mpsar_hi;
1016 u32 rar_entries = hw->mac.num_rar_entries;
1017
1018 if (rar < rar_entries) {
1019 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1020 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1021
1022 if (!mpsar_lo && !mpsar_hi)
1023 goto done;
1024
1025 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
1026 if (mpsar_lo) {
1027 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
1028 mpsar_lo = 0;
1029 }
1030 if (mpsar_hi) {
1031 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
1032 mpsar_hi = 0;
1033 }
1034 } else if (vmdq < 32) {
1035 mpsar_lo &= ~(1 << vmdq);
1036 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
1037 } else {
1038 mpsar_hi &= ~(1 << (vmdq - 32));
1039 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
1040 }
1041
1042 /* was that the last pool using this rar? */
1043 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
1044 hw->mac.ops.clear_rar(hw, rar);
1045 } else {
1046 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1047 }
1048
1049done:
1050 return 0;
1051}
1052
1053/**
1054 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
1055 * @hw: pointer to hardware struct
1056 * @rar: receive address register index to associate with a VMDq index
1057 * @vmdq: VMDq pool index
1058 **/
7b25cdba 1059static s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
11afc1b1
PW		 1060{
1061 u32 mpsar;
1062 u32 rar_entries = hw->mac.num_rar_entries;
1063
1064 if (rar < rar_entries) {
1065 if (vmdq < 32) {
1066 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1067 mpsar |= 1 << vmdq;
1068 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
1069 } else {
1070 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1071 mpsar |= 1 << (vmdq - 32);
1072 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
1073 }
1074 } else {
1075 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1076 }
1077 return 0;
1078}
1079
1080/**
1081 * ixgbe_set_vfta_82599 - Set VLAN filter table
1082 * @hw: pointer to hardware structure
1083 * @vlan: VLAN id to write to VLAN filter
1084 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1085 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1086 *
1087 * Turn on/off specified VLAN in the VLAN filter table.
1088 **/
7b25cdba
DS		 1089static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1090 bool vlan_on)
11afc1b1
PW		 1091{
1092 u32 regindex;
096a58fd 1093 u32 vlvf_index;
11afc1b1
PW		 1094 u32 bitindex;
1095 u32 bits;
1096 u32 first_empty_slot;
096a58fd 1097 u32 vt_ctl;
11afc1b1
PW		 1098
1099 if (vlan > 4095)
1100 return IXGBE_ERR_PARAM;
1101
1102 /*
1103 * this is a 2 part operation - first the VFTA, then the
1104 * VLVF and VLVFB if vind is set
1105 */
1106
1107 /* Part 1
1108 * The VFTA is a bitstring made up of 128 32-bit registers
1109 * that enable the particular VLAN id, much like the MTA:
1110 * bits[11-5]: which register
1111 * bits[4-0]: which bit in the register
1112 */
1113 regindex = (vlan >> 5) & 0x7F;
1114 bitindex = vlan & 0x1F;
1115 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1116 if (vlan_on)
1117 bits |= (1 << bitindex);
1118 else
1119 bits &= ~(1 << bitindex);
1120 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1121
1122
1123 /* Part 2
096a58fd 1124 * If VT mode is set
11afc1b1
PW		 1125 * Either vlan_on
1126 * make sure the vlan is in VLVF
1127 * set the vind bit in the matching VLVFB
1128 * Or !vlan_on
1129 * clear the pool bit and possibly the vind
1130 */
096a58fd
GR		 1131 vt_ctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1132 if (!(vt_ctl & IXGBE_VT_CTL_VT_ENABLE))
1133 goto out;
11afc1b1 1134
096a58fd
GR		 1135 /* find the vlanid or the first empty slot */
1136 first_empty_slot = 0;
1137
1138 for (vlvf_index = 1; vlvf_index < IXGBE_VLVF_ENTRIES; vlvf_index++) {
1139 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(vlvf_index));
1140 if (!bits && !first_empty_slot)
1141 first_empty_slot = vlvf_index;
1142 else if ((bits & 0x0FFF) == vlan)
1143 break;
1144 }
1145
1146 if (vlvf_index >= IXGBE_VLVF_ENTRIES) {
1147 if (first_empty_slot)
1148 vlvf_index = first_empty_slot;
1149 else {
1150 hw_dbg(hw, "No space in VLVF.\n");
1151 goto out;
11afc1b1 1152 }
096a58fd 1153 }
11afc1b1 1154
096a58fd
GR		 1155 if (vlan_on) {
1156 /* set the pool bit */
1157 if (vind < 32) {
1158 bits = IXGBE_READ_REG(hw,
1159 IXGBE_VLVFB(vlvf_index * 2));
1160 bits |= (1 << vind);
1161 IXGBE_WRITE_REG(hw,
1162 IXGBE_VLVFB(vlvf_index * 2), bits);
11afc1b1 1163 } else {
096a58fd
GR		 1164 bits = IXGBE_READ_REG(hw,
1165 IXGBE_VLVFB((vlvf_index * 2) + 1));
1166 bits |= (1 << (vind - 32));
1167 IXGBE_WRITE_REG(hw,
1168 IXGBE_VLVFB((vlvf_index * 2) + 1), bits);
1169 }
1170 } else {
1171 /* clear the pool bit */
1172 if (vind < 32) {
1173 bits = IXGBE_READ_REG(hw,
1174 IXGBE_VLVFB(vlvf_index * 2));
11afc1b1 1175 bits &= ~(1 << vind);
096a58fd
GR		 1176 IXGBE_WRITE_REG(hw,
1177 IXGBE_VLVFB(vlvf_index * 2), bits);
1178 bits |= IXGBE_READ_REG(hw,
1179 IXGBE_VLVFB((vlvf_index * 2) + 1));
1180 } else {
1181 bits = IXGBE_READ_REG(hw,
1182 IXGBE_VLVFB((vlvf_index * 2) + 1));
1183 bits &= ~(1 << (vind - 32));
1184 IXGBE_WRITE_REG(hw,
1185 IXGBE_VLVFB((vlvf_index * 2) + 1), bits);
1186 bits |= IXGBE_READ_REG(hw,
1187 IXGBE_VLVFB(vlvf_index * 2));
11afc1b1 1188 }
096a58fd 1189 }
11afc1b1 1190
096a58fd
GR		 1191 if (bits) {
1192 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
1193 (IXGBE_VLVF_VIEN | vlan));
1194 /* if bits is non-zero then some pools/VFs are still
1195 * using this VLAN ID. Force the VFTA entry to on */
1196 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1197 bits |= (1 << bitindex);
1198 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
11afc1b1 1199 }
096a58fd
GR		 1200 else
1201 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
11afc1b1
PW		 1202
1203out:
1204 return 0;
1205}
1206
1207/**
1208 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1209 * @hw: pointer to hardware structure
1210 *
1211 * Clears the VLAN filer table, and the VMDq index associated with the filter
1212 **/
7b25cdba 1213static s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1214{
1215 u32 offset;
1216
1217 for (offset = 0; offset < hw->mac.vft_size; offset++)
1218 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1219
1220 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1221 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1222 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1223 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1224 }
1225
1226 return 0;
1227}
1228
11afc1b1
PW		 1229/**
1230 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1231 * @hw: pointer to hardware structure
1232 **/
7b25cdba 1233static s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1234{
1235 int i;
1236 hw_dbg(hw, " Clearing UTA\n");
1237
1238 for (i = 0; i < 128; i++)
1239 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1240
1241 return 0;
1242}
1243
ffff4772
PWJ		 1244/**
1245 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1246 * @hw: pointer to hardware structure
1247 **/
1248s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1249{
1250 int i;
1251 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1252 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1253
1254 /*
1255 * Before starting reinitialization process,
1256 * FDIRCMD.CMD must be zero.
1257 */
1258 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1259 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1260 IXGBE_FDIRCMD_CMD_MASK))
1261 break;
1262 udelay(10);
1263 }
1264 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1265 hw_dbg(hw ,"Flow Director previous command isn't complete, "
1266 "aborting table re-initialization. \n");
1267 return IXGBE_ERR_FDIR_REINIT_FAILED;
1268 }
1269
1270 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1271 IXGBE_WRITE_FLUSH(hw);
1272 /*
1273 * 82599 adapters flow director init flow cannot be restarted,
1274 * Workaround 82599 silicon errata by performing the following steps
1275 * before re-writing the FDIRCTRL control register with the same value.
1276 * - write 1 to bit 8 of FDIRCMD register &
1277 * - write 0 to bit 8 of FDIRCMD register
1278 */
1279 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1280 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1281 IXGBE_FDIRCMD_CLEARHT));
1282 IXGBE_WRITE_FLUSH(hw);
1283 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1284 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1285 ~IXGBE_FDIRCMD_CLEARHT));
1286 IXGBE_WRITE_FLUSH(hw);
1287 /*
1288 * Clear FDIR Hash register to clear any leftover hashes
1289 * waiting to be programmed.
1290 */
1291 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1292 IXGBE_WRITE_FLUSH(hw);
1293
1294 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1295 IXGBE_WRITE_FLUSH(hw);
1296
1297 /* Poll init-done after we write FDIRCTRL register */
1298 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1299 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1300 IXGBE_FDIRCTRL_INIT_DONE)
1301 break;
1302 udelay(10);
1303 }
1304 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1305 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1306 return IXGBE_ERR_FDIR_REINIT_FAILED;
1307 }
1308
1309 /* Clear FDIR statistics registers (read to clear) */
1310 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1311 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1312 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1313 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1314 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1315
1316 return 0;
1317}
1318
1319/**
1320 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1321 * @hw: pointer to hardware structure
1322 * @pballoc: which mode to allocate filters with
1323 **/
1324s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1325{
1326 u32 fdirctrl = 0;
1327 u32 pbsize;
1328 int i;
1329
1330 /*
1331 * Before enabling Flow Director, the Rx Packet Buffer size
1332 * must be reduced. The new value is the current size minus
1333 * flow director memory usage size.
1334 */
1335 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1336 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1337 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1338
1339 /*
1340 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1341 * intialized to zero for non DCB mode otherwise actual total RX PB
1342 * would be bigger than programmed and filter space would run into
1343 * the PB 0 region.
1344 */
1345 for (i = 1; i < 8; i++)
1346 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1347
1348 /* Send interrupt when 64 filters are left */
1349 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1350
1351 /* Set the maximum length per hash bucket to 0xA filters */
1352 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1353
1354 switch (pballoc) {
1355 case IXGBE_FDIR_PBALLOC_64K:
1356 /* 8k - 1 signature filters */
1357 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1358 break;
1359 case IXGBE_FDIR_PBALLOC_128K:
1360 /* 16k - 1 signature filters */
1361 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1362 break;
1363 case IXGBE_FDIR_PBALLOC_256K:
1364 /* 32k - 1 signature filters */
1365 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1366 break;
1367 default:
1368 /* bad value */
1369 return IXGBE_ERR_CONFIG;
1370 };
1371
1372 /* Move the flexible bytes to use the ethertype - shift 6 words */
1373 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1374
1375 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1376
1377 /* Prime the keys for hashing */
1378 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1379 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1380 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1381 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1382
1383 /*
1384 * Poll init-done after we write the register. Estimated times:
1385 * 10G: PBALLOC = 11b, timing is 60us
1386 * 1G: PBALLOC = 11b, timing is 600us
1387 * 100M: PBALLOC = 11b, timing is 6ms
1388 *
1389 * Multiple these timings by 4 if under full Rx load
1390 *
1391 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1392 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1393 * this might not finish in our poll time, but we can live with that
1394 * for now.
1395 */
1396 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1397 IXGBE_WRITE_FLUSH(hw);
1398 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1399 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1400 IXGBE_FDIRCTRL_INIT_DONE)
1401 break;
1402 msleep(1);
1403 }
1404 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1405 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1406
1407 return 0;
1408}
1409
1410/**
1411 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1412 * @hw: pointer to hardware structure
1413 * @pballoc: which mode to allocate filters with
1414 **/
1415s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1416{
1417 u32 fdirctrl = 0;
1418 u32 pbsize;
1419 int i;
1420
1421 /*
1422 * Before enabling Flow Director, the Rx Packet Buffer size
1423 * must be reduced. The new value is the current size minus
1424 * flow director memory usage size.
1425 */
1426 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1427 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1428 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1429
1430 /*
1431 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1432 * intialized to zero for non DCB mode otherwise actual total RX PB
1433 * would be bigger than programmed and filter space would run into
1434 * the PB 0 region.
1435 */
1436 for (i = 1; i < 8; i++)
1437 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1438
1439 /* Send interrupt when 64 filters are left */
1440 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1441
1442 switch (pballoc) {
1443 case IXGBE_FDIR_PBALLOC_64K:
1444 /* 2k - 1 perfect filters */
1445 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1446 break;
1447 case IXGBE_FDIR_PBALLOC_128K:
1448 /* 4k - 1 perfect filters */
1449 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1450 break;
1451 case IXGBE_FDIR_PBALLOC_256K:
1452 /* 8k - 1 perfect filters */
1453 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1454 break;
1455 default:
1456 /* bad value */
1457 return IXGBE_ERR_CONFIG;
1458 };
1459
1460 /* Turn perfect match filtering on */
1461 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1462 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1463
1464 /* Move the flexible bytes to use the ethertype - shift 6 words */
1465 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1466
1467 /* Prime the keys for hashing */
1468 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1469 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1470 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1471 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1472
1473 /*
1474 * Poll init-done after we write the register. Estimated times:
1475 * 10G: PBALLOC = 11b, timing is 60us
1476 * 1G: PBALLOC = 11b, timing is 600us
1477 * 100M: PBALLOC = 11b, timing is 6ms
1478 *
1479 * Multiple these timings by 4 if under full Rx load
1480 *
1481 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1482 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1483 * this might not finish in our poll time, but we can live with that
1484 * for now.
1485 */
1486
1487 /* Set the maximum length per hash bucket to 0xA filters */
1488 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1489
1490 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1491 IXGBE_WRITE_FLUSH(hw);
1492 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1493 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1494 IXGBE_FDIRCTRL_INIT_DONE)
1495 break;
1496 msleep(1);
1497 }
1498 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1499 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1500
1501 return 0;
1502}
1503
1504
1505/**
1506 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1507 * @stream: input bitstream to compute the hash on
1508 * @key: 32-bit hash key
1509 **/
7b25cdba
DS		 1510static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1511 u32 key)
ffff4772
PWJ		 1512{
1513 /*
1514 * The algorithm is as follows:
1515 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1516 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1517 * and A[n] x B[n] is bitwise AND between same length strings
1518 *
1519 * K[n] is 16 bits, defined as:
1520 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1521 * for n modulo 32 < 15, K[n] =
1522 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1523 *
1524 * S[n] is 16 bits, defined as:
1525 * for n >= 15, S[n] = S[n:n - 15]
1526 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1527 *
1528 * To simplify for programming, the algorithm is implemented
1529 * in software this way:
1530 *
1531 * Key[31:0], Stream[335:0]
1532 *
1533 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1534 * int_key[350:0] = tmp_key[351:1]
1535 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1536 *
1537 * hash[15:0] = 0;
1538 * for (i = 0; i < 351; i++) {
1539 * if (int_key[i])
1540 * hash ^= int_stream[(i + 15):i];
1541 * }
1542 */
1543
1544 union {
1545 u64 fill[6];
1546 u32 key[11];
1547 u8 key_stream[44];
1548 } tmp_key;
1549
1550 u8 *stream = (u8 *)atr_input;
1551 u8 int_key[44]; /* upper-most bit unused */
1552 u8 hash_str[46]; /* upper-most 2 bits unused */
1553 u16 hash_result = 0;
1554 int i, j, k, h;
1555
1556 /*
1557 * Initialize the fill member to prevent warnings
1558 * on some compilers
1559 */
1560 tmp_key.fill[0] = 0;
1561
1562 /* First load the temporary key stream */
1563 for (i = 0; i < 6; i++) {
1564 u64 fillkey = ((u64)key << 32) | key;
1565 tmp_key.fill[i] = fillkey;
1566 }
1567
1568 /*
1569 * Set the interim key for the hashing. Bit 352 is unused, so we must
1570 * shift and compensate when building the key.
1571 */
1572
1573 int_key[0] = tmp_key.key_stream[0] >> 1;
1574 for (i = 1, j = 0; i < 44; i++) {
1575 unsigned int this_key = tmp_key.key_stream[j] << 7;
1576 j++;
1577 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1578 }
1579
1580 /*
1581 * Set the interim bit string for the hashing. Bits 368 and 367 are
1582 * unused, so shift and compensate when building the string.
1583 */
1584 hash_str[0] = (stream[40] & 0x7f) >> 1;
1585 for (i = 1, j = 40; i < 46; i++) {
1586 unsigned int this_str = stream[j] << 7;
1587 j++;
1588 if (j > 41)
1589 j = 0;
1590 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1591 }
1592
1593 /*
1594 * Now compute the hash. i is the index into hash_str, j is into our
1595 * key stream, k is counting the number of bits, and h interates within
1596 * each byte.
1597 */
1598 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1599 for (h = 0; h < 8 && k < 351; h++, k++) {
1600 if (int_key[j] & (1 << h)) {
1601 /*
1602 * Key bit is set, XOR in the current 16-bit
1603 * string. Example of processing:
1604 * h = 0,
1605 * tmp = (hash_str[i - 2] & 0 << 16) |
1606 * (hash_str[i - 1] & 0xff << 8) |
1607 * (hash_str[i] & 0xff >> 0)
1608 * So tmp = hash_str[15 + k:k], since the
1609 * i + 2 clause rolls off the 16-bit value
1610 * h = 7,
1611 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1612 * (hash_str[i - 1] & 0xff << 1) |
1613 * (hash_str[i] & 0x80 >> 7)
1614 */
1615 int tmp = (hash_str[i] >> h);
1616 tmp |= (hash_str[i - 1] << (8 - h));
1617 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1618 << (16 - h);
1619 hash_result ^= (u16)tmp;
1620 }
1621 }
1622 }
1623
1624 return hash_result;
1625}
1626
1627/**
1628 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1629 * @input: input stream to modify
1630 * @vlan: the VLAN id to load
1631 **/
1632s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1633{
1634 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1635 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1636
1637 return 0;
1638}
1639
1640/**
1641 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1642 * @input: input stream to modify
1643 * @src_addr: the IP address to load
1644 **/
1645s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1646{
1647 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1648 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1649 (src_addr >> 16) & 0xff;
1650 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1651 (src_addr >> 8) & 0xff;
1652 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1653
1654 return 0;
1655}
1656
1657/**
1658 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1659 * @input: input stream to modify
1660 * @dst_addr: the IP address to load
1661 **/
1662s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1663{
1664 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1665 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1666 (dst_addr >> 16) & 0xff;
1667 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1668 (dst_addr >> 8) & 0xff;
1669 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1670
1671 return 0;
1672}
1673
1674/**
1675 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1676 * @input: input stream to modify
1677 * @src_addr_1: the first 4 bytes of the IP address to load
1678 * @src_addr_2: the second 4 bytes of the IP address to load
1679 * @src_addr_3: the third 4 bytes of the IP address to load
1680 * @src_addr_4: the fourth 4 bytes of the IP address to load
1681 **/
1682s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1683 u32 src_addr_1, u32 src_addr_2,
1684 u32 src_addr_3, u32 src_addr_4)
ffff4772
PWJ		 1685{
1686 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1687 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1688 (src_addr_4 >> 8) & 0xff;
1689 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1690 (src_addr_4 >> 16) & 0xff;
1691 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1692
1693 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1694 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1695 (src_addr_3 >> 8) & 0xff;
1696 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1697 (src_addr_3 >> 16) & 0xff;
1698 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1699
1700 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1701 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1702 (src_addr_2 >> 8) & 0xff;
1703 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1704 (src_addr_2 >> 16) & 0xff;
1705 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1706
1707 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1708 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1709 (src_addr_1 >> 8) & 0xff;
1710 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1711 (src_addr_1 >> 16) & 0xff;
1712 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1713
1714 return 0;
1715}
1716
1717/**
1718 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1719 * @input: input stream to modify
1720 * @dst_addr_1: the first 4 bytes of the IP address to load
1721 * @dst_addr_2: the second 4 bytes of the IP address to load
1722 * @dst_addr_3: the third 4 bytes of the IP address to load
1723 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1724 **/
1725s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1726 u32 dst_addr_1, u32 dst_addr_2,
1727 u32 dst_addr_3, u32 dst_addr_4)
ffff4772
PWJ		 1728{
1729 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1730 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1731 (dst_addr_4 >> 8) & 0xff;
1732 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1733 (dst_addr_4 >> 16) & 0xff;
1734 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1735
1736 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1737 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1738 (dst_addr_3 >> 8) & 0xff;
1739 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1740 (dst_addr_3 >> 16) & 0xff;
1741 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1742
1743 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1744 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1745 (dst_addr_2 >> 8) & 0xff;
1746 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1747 (dst_addr_2 >> 16) & 0xff;
1748 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1749
1750 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1751 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1752 (dst_addr_1 >> 8) & 0xff;
1753 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1754 (dst_addr_1 >> 16) & 0xff;
1755 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1756
1757 return 0;
1758}
1759
1760/**
1761 * ixgbe_atr_set_src_port_82599 - Sets the source port
1762 * @input: input stream to modify
1763 * @src_port: the source port to load
1764 **/
1765s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1766{
1767 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1768 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1769
1770 return 0;
1771}
1772
1773/**
1774 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1775 * @input: input stream to modify
1776 * @dst_port: the destination port to load
1777 **/
1778s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1779{
1780 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1781 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1782
1783 return 0;
1784}
1785
1786/**
1787 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1788 * @input: input stream to modify
1789 * @flex_bytes: the flexible bytes to load
1790 **/
1791s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1792{
1793 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1794 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1795
1796 return 0;
1797}
1798
1799/**
1800 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1801 * @input: input stream to modify
1802 * @vm_pool: the Virtual Machine pool to load
1803 **/
7b25cdba
DS		 1804s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
1805 u8 vm_pool)
ffff4772
PWJ		 1806{
1807 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1808
1809 return 0;
1810}
1811
1812/**
1813 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1814 * @input: input stream to modify
1815 * @l4type: the layer 4 type value to load
1816 **/
1817s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1818{
1819 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1820
1821 return 0;
1822}
1823
1824/**
1825 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1826 * @input: input stream to search
1827 * @vlan: the VLAN id to load
1828 **/
7b25cdba
DS		 1829static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input,
1830 u16 *vlan)
ffff4772
PWJ		 1831{
1832 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1833 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1834
1835 return 0;
1836}
1837
1838/**
1839 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1840 * @input: input stream to search
1841 * @src_addr: the IP address to load
1842 **/
7b25cdba
DS		 1843static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1844 u32 *src_addr)
ffff4772
PWJ		 1845{
1846 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1847 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1848 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1849 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1850
1851 return 0;
1852}
1853
1854/**
1855 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1856 * @input: input stream to search
1857 * @dst_addr: the IP address to load
1858 **/
7b25cdba
DS		 1859static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1860 u32 *dst_addr)
ffff4772
PWJ		 1861{
1862 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1863 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1864 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1865 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1866
1867 return 0;
1868}
1869
1870/**
1871 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1872 * @input: input stream to search
1873 * @src_addr_1: the first 4 bytes of the IP address to load
1874 * @src_addr_2: the second 4 bytes of the IP address to load
1875 * @src_addr_3: the third 4 bytes of the IP address to load
1876 * @src_addr_4: the fourth 4 bytes of the IP address to load
1877 **/
7b25cdba
DS		 1878static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1879 u32 *src_addr_1, u32 *src_addr_2,
1880 u32 *src_addr_3, u32 *src_addr_4)
ffff4772
PWJ		 1881{
1882 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1883 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1884 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1885 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1886
1887 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1888 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1889 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1890 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1891
1892 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1893 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1894 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1895 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1896
1897 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1898 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1899 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1900 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1901
1902 return 0;
1903}
1904
1905/**
1906 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1907 * @input: input stream to search
1908 * @dst_addr_1: the first 4 bytes of the IP address to load
1909 * @dst_addr_2: the second 4 bytes of the IP address to load
1910 * @dst_addr_3: the third 4 bytes of the IP address to load
1911 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1912 **/
1913s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1914 u32 *dst_addr_1, u32 *dst_addr_2,
1915 u32 *dst_addr_3, u32 *dst_addr_4)
ffff4772
PWJ		 1916{
1917 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1918 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1919 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1920 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1921
1922 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1923 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1924 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1925 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1926
1927 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1928 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1929 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1930 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1931
1932 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1933 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1934 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1935 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1936
1937 return 0;
1938}
1939
1940/**
1941 * ixgbe_atr_get_src_port_82599 - Gets the source port
1942 * @input: input stream to modify
1943 * @src_port: the source port to load
1944 *
1945 * Even though the input is given in big-endian, the FDIRPORT registers
1946 * expect the ports to be programmed in little-endian. Hence the need to swap
1947 * endianness when retrieving the data. This can be confusing since the
1948 * internal hash engine expects it to be big-endian.
1949 **/
7b25cdba
DS		 1950static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1951 u16 *src_port)
ffff4772
PWJ		 1952{
1953 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1954 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1955
1956 return 0;
1957}
1958
1959/**
1960 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1961 * @input: input stream to modify
1962 * @dst_port: the destination port to load
1963 *
1964 * Even though the input is given in big-endian, the FDIRPORT registers
1965 * expect the ports to be programmed in little-endian. Hence the need to swap
1966 * endianness when retrieving the data. This can be confusing since the
1967 * internal hash engine expects it to be big-endian.
1968 **/
7b25cdba
DS		 1969static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1970 u16 *dst_port)
ffff4772
PWJ		 1971{
1972 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1973 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1974
1975 return 0;
1976}
1977
1978/**
1979 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1980 * @input: input stream to modify
1981 * @flex_bytes: the flexible bytes to load
1982 **/
7b25cdba
DS		 1983static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1984 u16 *flex_byte)
ffff4772
PWJ		 1985{
1986 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1987 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1988
1989 return 0;
1990}
1991
1992/**
1993 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
1994 * @input: input stream to modify
1995 * @vm_pool: the Virtual Machine pool to load
1996 **/
7b25cdba
DS		 1997s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
1998 u8 *vm_pool)
ffff4772
PWJ		 1999{
2000 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
2001
2002 return 0;
2003}
2004
2005/**
2006 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
2007 * @input: input stream to modify
2008 * @l4type: the layer 4 type value to load
2009 **/
7b25cdba
DS		 2010static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
2011 u8 *l4type)
ffff4772
PWJ		 2012{
2013 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
2014
2015 return 0;
2016}
2017
2018/**
2019 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
2020 * @hw: pointer to hardware structure
2021 * @stream: input bitstream
2022 * @queue: queue index to direct traffic to
2023 **/
2024s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
2025 struct ixgbe_atr_input *input,
2026 u8 queue)
2027{
2028 u64 fdirhashcmd;
2029 u64 fdircmd;
2030 u32 fdirhash;
2031 u16 bucket_hash, sig_hash;
2032 u8 l4type;
2033
2034 bucket_hash = ixgbe_atr_compute_hash_82599(input,
2035 IXGBE_ATR_BUCKET_HASH_KEY);
2036
2037 /* bucket_hash is only 15 bits */
2038 bucket_hash &= IXGBE_ATR_HASH_MASK;
2039
2040 sig_hash = ixgbe_atr_compute_hash_82599(input,
2041 IXGBE_ATR_SIGNATURE_HASH_KEY);
2042
2043 /* Get the l4type in order to program FDIRCMD properly */
2044 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
2045 ixgbe_atr_get_l4type_82599(input, &l4type);
2046
2047 /*
2048 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
2049 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
2050 */
2051 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2052
2053 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
2054 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
2055
2056 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2057 case IXGBE_ATR_L4TYPE_TCP:
2058 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
2059 break;
2060 case IXGBE_ATR_L4TYPE_UDP:
2061 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
2062 break;
2063 case IXGBE_ATR_L4TYPE_SCTP:
2064 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
2065 break;
2066 default:
2067 hw_dbg(hw, "Error on l4type input\n");
2068 return IXGBE_ERR_CONFIG;
2069 }
2070
2071 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
2072 fdircmd |= IXGBE_FDIRCMD_IPV6;
2073
2074 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
2075 fdirhashcmd = ((fdircmd << 32) | fdirhash);
2076
2077 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
2078
2079 return 0;
2080}
2081
2082/**
2083 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
2084 * @hw: pointer to hardware structure
2085 * @input: input bitstream
2086 * @queue: queue index to direct traffic to
2087 *
2088 * Note that the caller to this function must lock before calling, since the
2089 * hardware writes must be protected from one another.
2090 **/
2091s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
7b25cdba
DS		 2092 struct ixgbe_atr_input *input,
2093 u16 soft_id,
2094 u8 queue)
ffff4772
PWJ		 2095{
2096 u32 fdircmd = 0;
2097 u32 fdirhash;
2098 u32 src_ipv4, dst_ipv4;
2099 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
2100 u16 src_port, dst_port, vlan_id, flex_bytes;
2101 u16 bucket_hash;
2102 u8 l4type;
2103
2104 /* Get our input values */
2105 ixgbe_atr_get_l4type_82599(input, &l4type);
2106
2107 /*
2108 * Check l4type formatting, and bail out before we touch the hardware
2109 * if there's a configuration issue
2110 */
2111 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2112 case IXGBE_ATR_L4TYPE_TCP:
2113 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
2114 break;
2115 case IXGBE_ATR_L4TYPE_UDP:
2116 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
2117 break;
2118 case IXGBE_ATR_L4TYPE_SCTP:
2119 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
2120 break;
2121 default:
2122 hw_dbg(hw, "Error on l4type input\n");
2123 return IXGBE_ERR_CONFIG;
2124 }
2125
2126 bucket_hash = ixgbe_atr_compute_hash_82599(input,
2127 IXGBE_ATR_BUCKET_HASH_KEY);
2128
2129 /* bucket_hash is only 15 bits */
2130 bucket_hash &= IXGBE_ATR_HASH_MASK;
2131
2132 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
2133 ixgbe_atr_get_src_port_82599(input, &src_port);
2134 ixgbe_atr_get_dst_port_82599(input, &dst_port);
2135 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
2136
2137 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2138
2139 /* Now figure out if we're IPv4 or IPv6 */
2140 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
2141 /* IPv6 */
2142 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
2143 &src_ipv6_3, &src_ipv6_4);
2144
2145 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
2146 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
2147 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
2148 /* The last 4 bytes is the same register as IPv4 */
2149 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
2150
2151 fdircmd |= IXGBE_FDIRCMD_IPV6;
2152 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
2153 } else {
2154 /* IPv4 */
2155 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
2156 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
2157
2158 }
2159
2160 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
2161 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
2162
2163 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
2164 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
2165 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
2166 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
2167
2168 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
2169 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
2170 fdircmd |= IXGBE_FDIRCMD_LAST;
2171 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
2172 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
2173
2174 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2175 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
2176
2177 return 0;
2178}
11afc1b1
PW		 2179/**
2180 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2181 * @hw: pointer to hardware structure
2182 * @reg: analog register to read
2183 * @val: read value
2184 *
2185 * Performs read operation to Omer analog register specified.
2186 **/
7b25cdba 2187static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
11afc1b1
PW		 2188{
2189 u32 core_ctl;
2190
2191 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2192 (reg << 8));
2193 IXGBE_WRITE_FLUSH(hw);
2194 udelay(10);
2195 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2196 *val = (u8)core_ctl;
2197
2198 return 0;
2199}
2200
2201/**
2202 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2203 * @hw: pointer to hardware structure
2204 * @reg: atlas register to write
2205 * @val: value to write
2206 *
2207 * Performs write operation to Omer analog register specified.
2208 **/
7b25cdba 2209static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
11afc1b1
PW		 2210{
2211 u32 core_ctl;
2212
2213 core_ctl = (reg << 8) | val;
2214 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2215 IXGBE_WRITE_FLUSH(hw);
2216 udelay(10);
2217
2218 return 0;
2219}
2220
2221/**
2222 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2223 * @hw: pointer to hardware structure
2224 *
2225 * Starts the hardware using the generic start_hw function.
2226 * Then performs device-specific:
2227 * Clears the rate limiter registers.
2228 **/
7b25cdba 2229static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2230{
2231 u32 q_num;
794caeb2 2232 s32 ret_val;
11afc1b1 2233
794caeb2 2234 ret_val = ixgbe_start_hw_generic(hw);
11afc1b1
PW		 2235
2236 /* Clear the rate limiters */
2237 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2238 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2239 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2240 }
2241 IXGBE_WRITE_FLUSH(hw);
2242
50ac58ba
PWJ		 2243 /* We need to run link autotry after the driver loads */
2244 hw->mac.autotry_restart = true;
2245
794caeb2
PWJ		 2246 if (ret_val == 0)
2247 ret_val = ixgbe_verify_fw_version_82599(hw);
2248
2249 return ret_val;
11afc1b1
PW		 2250}
2251
2252/**
2253 * ixgbe_identify_phy_82599 - Get physical layer module
2254 * @hw: pointer to hardware structure
2255 *
2256 * Determines the physical layer module found on the current adapter.
2257 **/
7b25cdba 2258static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2259{
2260 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2261 status = ixgbe_identify_phy_generic(hw);
2262 if (status != 0)
2263 status = ixgbe_identify_sfp_module_generic(hw);
2264 return status;
2265}
2266
2267/**
2268 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2269 * @hw: pointer to hardware structure
2270 *
2271 * Determines physical layer capabilities of the current configuration.
2272 **/
7b25cdba 2273static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2274{
2275 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 2276 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2277 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2278 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2279 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2280 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2281 u16 ext_ability = 0;
1339b9e9 2282 u8 comp_codes_10g = 0;
11afc1b1 2283
04193058
PWJ		 2284 hw->phy.ops.identify(hw);
2285
2286 if (hw->phy.type == ixgbe_phy_tn ||
2287 hw->phy.type == ixgbe_phy_cu_unknown) {
6b73e10d
BH		 2288 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2289 &ext_ability);
2290 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 2291 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 2292 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 2293 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 2294 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 2295 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2296 goto out;
2297 }
2298
2299 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2300 case IXGBE_AUTOC_LMS_1G_AN:
2301 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2302 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2303 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2304 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2305 goto out;
2306 } else
2307 /* SFI mode so read SFP module */
2308 goto sfp_check;
11afc1b1 2309 break;
04193058
PWJ		 2310 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2311 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2312 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2313 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2314 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 2315 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2316 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 2317 goto out;
2318 break;
2319 case IXGBE_AUTOC_LMS_10G_SERIAL:
2320 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2321 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2322 goto out;
2323 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2324 goto sfp_check;
2325 break;
2326 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2327 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2328 if (autoc & IXGBE_AUTOC_KX_SUPP)
2329 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2330 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2331 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2332 if (autoc & IXGBE_AUTOC_KR_SUPP)
2333 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2334 goto out;
2335 break;
2336 default:
2337 goto out;
2338 break;
2339 }
11afc1b1 2340
04193058
PWJ		 2341sfp_check:
2342 /* SFP check must be done last since DA modules are sometimes used to
2343 * test KR mode - we need to id KR mode correctly before SFP module.
2344 * Call identify_sfp because the pluggable module may have changed */
2345 hw->phy.ops.identify_sfp(hw);
2346 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2347 goto out;
2348
2349 switch (hw->phy.type) {
2350 case ixgbe_phy_tw_tyco:
2351 case ixgbe_phy_tw_unknown:
2352 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2353 break;
2354 case ixgbe_phy_sfp_avago:
2355 case ixgbe_phy_sfp_ftl:
2356 case ixgbe_phy_sfp_intel:
2357 case ixgbe_phy_sfp_unknown:
2358 hw->phy.ops.read_i2c_eeprom(hw,
2359 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2360 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 2361 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 2362 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 2363 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
11afc1b1
PW		 2364 break;
2365 default:
11afc1b1
PW		 2366 break;
2367 }
2368
04193058 2369out:
11afc1b1
PW		 2370 return physical_layer;
2371}
2372
2373/**
2374 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2375 * @hw: pointer to hardware structure
2376 * @regval: register value to write to RXCTRL
2377 *
2378 * Enables the Rx DMA unit for 82599
2379 **/
7b25cdba 2380static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
11afc1b1
PW		 2381{
2382#define IXGBE_MAX_SECRX_POLL 30
2383 int i;
2384 int secrxreg;
2385
2386 /*
2387 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2388 * If traffic is incoming before we enable the Rx unit, it could hang
2389 * the Rx DMA unit. Therefore, make sure the security engine is
2390 * completely disabled prior to enabling the Rx unit.
2391 */
2392 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2393 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2394 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2395 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2396 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2397 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2398 break;
2399 else
2400 udelay(10);
2401 }
2402
2403 /* For informational purposes only */
2404 if (i >= IXGBE_MAX_SECRX_POLL)
2405 hw_dbg(hw, "Rx unit being enabled before security "
2406 "path fully disabled. Continuing with init.\n");
2407
2408 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2409 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2410 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2411 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2412 IXGBE_WRITE_FLUSH(hw);
2413
2414 return 0;
2415}
2416
04193058
PWJ		 2417/**
2418 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2419 * @hw: pointer to hardware structure
2420 * @device_caps: the EEPROM word with the extra device capabilities
2421 *
2422 * This function will read the EEPROM location for the device capabilities,
2423 * and return the word through device_caps.
2424 **/
7b25cdba 2425static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
04193058
PWJ		 2426{
2427 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2428
2429 return 0;
2430}
2431
0365e6e4
PW		 2432/**
2433 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2434 * @hw: pointer to hardware structure
2435 * @san_mac_offset: SAN MAC address offset
2436 *
2437 * This function will read the EEPROM location for the SAN MAC address
2438 * pointer, and returns the value at that location. This is used in both
2439 * get and set mac_addr routines.
2440 **/
7b25cdba
DS		 2441static s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
2442 u16 *san_mac_offset)
0365e6e4
PW		 2443{
2444 /*
2445 * First read the EEPROM pointer to see if the MAC addresses are
2446 * available.
2447 */
2448 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2449
2450 return 0;
2451}
2452
2453/**
2454 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2455 * @hw: pointer to hardware structure
2456 * @san_mac_addr: SAN MAC address
2457 *
2458 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2459 * per-port, so set_lan_id() must be called before reading the addresses.
2460 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2461 * upon for non-SFP connections, so we must call it here.
2462 **/
7b25cdba 2463static s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
0365e6e4
PW		 2464{
2465 u16 san_mac_data, san_mac_offset;
2466 u8 i;
2467
2468 /*
2469 * First read the EEPROM pointer to see if the MAC addresses are
2470 * available. If they're not, no point in calling set_lan_id() here.
2471 */
2472 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2473
2474 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2475 /*
2476 * No addresses available in this EEPROM. It's not an
2477 * error though, so just wipe the local address and return.
2478 */
2479 for (i = 0; i < 6; i++)
2480 san_mac_addr[i] = 0xFF;
2481
2482 goto san_mac_addr_out;
2483 }
2484
2485 /* make sure we know which port we need to program */
2486 hw->mac.ops.set_lan_id(hw);
2487 /* apply the port offset to the address offset */
2488 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2489 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2490 for (i = 0; i < 3; i++) {
2491 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2492 san_mac_addr[i * 2] = (u8)(san_mac_data);
2493 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2494 san_mac_offset++;
2495 }
2496
2497san_mac_addr_out:
2498 return 0;
2499}
2500
794caeb2
PWJ		 2501/**
2502 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2503 * @hw: pointer to hardware structure
2504 *
2505 * Verifies that installed the firmware version is 0.6 or higher
2506 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2507 *
2508 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2509 * if the FW version is not supported.
2510 **/
2511static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2512{
2513 s32 status = IXGBE_ERR_EEPROM_VERSION;
2514 u16 fw_offset, fw_ptp_cfg_offset;
2515 u16 fw_version = 0;
2516
2517 /* firmware check is only necessary for SFI devices */
2518 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2519 status = 0;
2520 goto fw_version_out;
2521 }
2522
2523 /* get the offset to the Firmware Module block */
2524 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2525
2526 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2527 goto fw_version_out;
2528
2529 /* get the offset to the Pass Through Patch Configuration block */
2530 hw->eeprom.ops.read(hw, (fw_offset +
2531 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2532 &fw_ptp_cfg_offset);
2533
2534 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2535 goto fw_version_out;
2536
2537 /* get the firmware version */
2538 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2539 IXGBE_FW_PATCH_VERSION_4),
2540 &fw_version);
2541
2542 if (fw_version > 0x5)
2543 status = 0;
2544
2545fw_version_out:
2546 return status;
2547}
2548
383ff34b
YZ		 2549/**
2550 * ixgbe_get_wwn_prefix_82599 - Get alternative WWNN/WWPN prefix from
2551 * the EEPROM
2552 * @hw: pointer to hardware structure
2553 * @wwnn_prefix: the alternative WWNN prefix
2554 * @wwpn_prefix: the alternative WWPN prefix
2555 *
2556 * This function will read the EEPROM from the alternative SAN MAC address
2557 * block to check the support for the alternative WWNN/WWPN prefix support.
2558 **/
2559static s32 ixgbe_get_wwn_prefix_82599(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2560 u16 *wwpn_prefix)
2561{
2562 u16 offset, caps;
2563 u16 alt_san_mac_blk_offset;
2564
2565 /* clear output first */
2566 *wwnn_prefix = 0xFFFF;
2567 *wwpn_prefix = 0xFFFF;
2568
2569 /* check if alternative SAN MAC is supported */
2570 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2571 &alt_san_mac_blk_offset);
2572
2573 if ((alt_san_mac_blk_offset == 0) ||
2574 (alt_san_mac_blk_offset == 0xFFFF))
2575 goto wwn_prefix_out;
2576
2577 /* check capability in alternative san mac address block */
2578 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2579 hw->eeprom.ops.read(hw, offset, &caps);
2580 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2581 goto wwn_prefix_out;
2582
2583 /* get the corresponding prefix for WWNN/WWPN */
2584 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2585 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2586
2587 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2588 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2589
2590wwn_prefix_out:
2591 return 0;
2592}
2593
11afc1b1
PW		 2594static struct ixgbe_mac_operations mac_ops_82599 = {
2595 .init_hw = &ixgbe_init_hw_generic,
2596 .reset_hw = &ixgbe_reset_hw_82599,
2597 .start_hw = &ixgbe_start_hw_82599,
2598 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2599 .get_media_type = &ixgbe_get_media_type_82599,
2600 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2601 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2602 .get_mac_addr = &ixgbe_get_mac_addr_generic,
0365e6e4 2603 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
04193058 2604 .get_device_caps = &ixgbe_get_device_caps_82599,
383ff34b 2605 .get_wwn_prefix = &ixgbe_get_wwn_prefix_82599,
11afc1b1
PW		 2606 .stop_adapter = &ixgbe_stop_adapter_generic,
2607 .get_bus_info = &ixgbe_get_bus_info_generic,
2608 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2609 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2610 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2611 .setup_link = &ixgbe_setup_mac_link_82599,
11afc1b1
PW		 2612 .check_link = &ixgbe_check_mac_link_82599,
2613 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2614 .led_on = &ixgbe_led_on_generic,
2615 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 2616 .blink_led_start = &ixgbe_blink_led_start_generic,
2617 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 2618 .set_rar = &ixgbe_set_rar_generic,
2619 .clear_rar = &ixgbe_clear_rar_generic,
2620 .set_vmdq = &ixgbe_set_vmdq_82599,
2621 .clear_vmdq = &ixgbe_clear_vmdq_82599,
2622 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2623 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2624 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2625 .enable_mc = &ixgbe_enable_mc_generic,
2626 .disable_mc = &ixgbe_disable_mc_generic,
2627 .clear_vfta = &ixgbe_clear_vfta_82599,
2628 .set_vfta = &ixgbe_set_vfta_82599,
620fa036 2629 .fc_enable = &ixgbe_fc_enable_generic,
11afc1b1
PW		 2630 .init_uta_tables = &ixgbe_init_uta_tables_82599,
2631 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2632};
2633
2634static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2635 .init_params = &ixgbe_init_eeprom_params_generic,
2636 .read = &ixgbe_read_eeprom_generic,
2637 .write = &ixgbe_write_eeprom_generic,
2638 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2639 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2640};
2641
2642static struct ixgbe_phy_operations phy_ops_82599 = {
2643 .identify = &ixgbe_identify_phy_82599,
2644 .identify_sfp = &ixgbe_identify_sfp_module_generic,
04f165ef 2645 .init = &ixgbe_init_phy_ops_82599,
11afc1b1
PW		 2646 .reset = &ixgbe_reset_phy_generic,
2647 .read_reg = &ixgbe_read_phy_reg_generic,
2648 .write_reg = &ixgbe_write_phy_reg_generic,
2649 .setup_link = &ixgbe_setup_phy_link_generic,
2650 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2651 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2652 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2653 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2654 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2655};
2656
2657struct ixgbe_info ixgbe_82599_info = {
2658 .mac = ixgbe_mac_82599EB,
2659 .get_invariants = &ixgbe_get_invariants_82599,
2660 .mac_ops = &mac_ops_82599,
2661 .eeprom_ops = &eeprom_ops_82599,
2662 .phy_ops = &phy_ops_82599,
096a58fd 2663 .mbx_ops = &mbx_ops_82599,
11afc1b1 2664};
Linux kernel - Deliverables
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