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ixgbe: Use bool flag to see if the packet unmapping is delayed in HWRSC
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
11afc1b1
PW		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
096a58fd 34#include "ixgbe_mbx.h"
11afc1b1
PW		 35
36#define IXGBE_82599_MAX_TX_QUEUES 128
37#define IXGBE_82599_MAX_RX_QUEUES 128
38#define IXGBE_82599_RAR_ENTRIES 128
39#define IXGBE_82599_MC_TBL_SIZE 128
40#define IXGBE_82599_VFT_TBL_SIZE 128
41
61fac744
PW		 42void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
43void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
1097cd17 44void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
8620a103
MC		 45s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
cd7e1f0b
DS		 49static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg,
52 bool autoneg_wait_to_complete);
8620a103
MC		 53s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed speed,
57 bool autoneg,
58 bool autoneg_wait_to_complete);
11afc1b1
PW		 59static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed *speed,
61 bool *autoneg);
8620a103
MC		 62static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
63 ixgbe_link_speed speed,
64 bool autoneg,
65 bool autoneg_wait_to_complete);
794caeb2 66static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
11afc1b1 67
7b25cdba 68static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 69{
70 struct ixgbe_mac_info *mac = &hw->mac;
71 if (hw->phy.multispeed_fiber) {
72 /* Set up dual speed SFP+ support */
8620a103 73 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
61fac744
PW		 74 mac->ops.disable_tx_laser =
75 &ixgbe_disable_tx_laser_multispeed_fiber;
76 mac->ops.enable_tx_laser =
77 &ixgbe_enable_tx_laser_multispeed_fiber;
1097cd17 78 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
11afc1b1 79 } else {
61fac744
PW		 80 mac->ops.disable_tx_laser = NULL;
81 mac->ops.enable_tx_laser = NULL;
1097cd17 82 mac->ops.flap_tx_laser = NULL;
cd7e1f0b
DS		 83 if ((mac->ops.get_media_type(hw) ==
84 ixgbe_media_type_backplane) &&
85 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
86 hw->phy.smart_speed == ixgbe_smart_speed_on))
87 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
88 else
89 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
11afc1b1
PW		 90 }
91}
92
7b25cdba 93static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 94{
95 s32 ret_val = 0;
96 u16 list_offset, data_offset, data_value;
97
98 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
99 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 100
101 hw->phy.ops.reset = NULL;
102
11afc1b1
PW		 103 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
104 &data_offset);
105
106 if (ret_val != 0)
107 goto setup_sfp_out;
108
aa5aec88
PWJ		 109 /* PHY config will finish before releasing the semaphore */
110 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
111 if (ret_val != 0) {
112 ret_val = IXGBE_ERR_SWFW_SYNC;
113 goto setup_sfp_out;
114 }
115
11afc1b1
PW		 116 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
117 while (data_value != 0xffff) {
118 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
119 IXGBE_WRITE_FLUSH(hw);
120 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
121 }
1479ad4f
PWJ		 122 /* Now restart DSP by setting Restart_AN */
123 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
124 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
aa5aec88
PWJ		 125
126 /* Release the semaphore */
127 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
128 /* Delay obtaining semaphore again to allow FW access */
129 msleep(hw->eeprom.semaphore_delay);
11afc1b1
PW		 130 }
131
132setup_sfp_out:
133 return ret_val;
134}
135
136/**
137 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
138 * @hw: pointer to hardware structure
139 *
140 * Read PCIe configuration space, and get the MSI-X vector count from
141 * the capabilities table.
142 **/
7b25cdba 143static u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 144{
145 struct ixgbe_adapter *adapter = hw->back;
146 u16 msix_count;
147 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
148 &msix_count);
149 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
150
151 /* MSI-X count is zero-based in HW, so increment to give proper value */
152 msix_count++;
153
154 return msix_count;
155}
156
157static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
158{
159 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 160
04f165ef 161 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 162
04f165ef
PW		 163 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
164 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
165 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
166 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
167 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
168 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
11afc1b1 169
04f165ef
PW		 170 return 0;
171}
11afc1b1 172
04f165ef
PW		 173/**
174 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
175 * @hw: pointer to hardware structure
176 *
177 * Initialize any function pointers that were not able to be
178 * set during get_invariants because the PHY/SFP type was
179 * not known. Perform the SFP init if necessary.
180 *
181 **/
7b25cdba 182static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
04f165ef
PW		 183{
184 struct ixgbe_mac_info *mac = &hw->mac;
185 struct ixgbe_phy_info *phy = &hw->phy;
186 s32 ret_val = 0;
11afc1b1 187
04f165ef
PW		 188 /* Identify the PHY or SFP module */
189 ret_val = phy->ops.identify(hw);
190
191 /* Setup function pointers based on detected SFP module and speeds */
192 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 193
194 /* If copper media, overwrite with copper function pointers */
195 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
196 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
11afc1b1
PW		 197 mac->ops.get_link_capabilities =
198 &ixgbe_get_copper_link_capabilities_82599;
199 }
200
04f165ef 201 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 202 switch (hw->phy.type) {
203 case ixgbe_phy_tn:
204 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
205 phy->ops.get_firmware_version =
04f165ef 206 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 207 break;
208 default:
209 break;
210 }
211
11afc1b1
PW		 212 return ret_val;
213}
214
215/**
216 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
217 * @hw: pointer to hardware structure
218 * @speed: pointer to link speed
219 * @negotiation: true when autoneg or autotry is enabled
220 *
221 * Determines the link capabilities by reading the AUTOC register.
222 **/
7b25cdba
DS		 223static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
224 ixgbe_link_speed *speed,
225 bool *negotiation)
11afc1b1
PW		 226{
227 s32 status = 0;
1eb99d5a 228 u32 autoc = 0;
11afc1b1 229
1eb99d5a
PW		 230 /*
231 * Determine link capabilities based on the stored value of AUTOC,
232 * which represents EEPROM defaults. If AUTOC value has not been
233 * stored, use the current register value.
234 */
235 if (hw->mac.orig_link_settings_stored)
236 autoc = hw->mac.orig_autoc;
237 else
238 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
239
240 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 241 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
242 *speed = IXGBE_LINK_SPEED_1GB_FULL;
243 *negotiation = false;
244 break;
245
246 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
247 *speed = IXGBE_LINK_SPEED_10GB_FULL;
248 *negotiation = false;
249 break;
250
251 case IXGBE_AUTOC_LMS_1G_AN:
252 *speed = IXGBE_LINK_SPEED_1GB_FULL;
253 *negotiation = true;
254 break;
255
256 case IXGBE_AUTOC_LMS_10G_SERIAL:
257 *speed = IXGBE_LINK_SPEED_10GB_FULL;
258 *negotiation = false;
259 break;
260
261 case IXGBE_AUTOC_LMS_KX4_KX_KR:
262 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
263 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 264 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 265 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 266 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 267 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 268 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 269 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
270 *negotiation = true;
271 break;
272
273 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
274 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 275 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 276 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 277 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 278 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 279 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 280 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
281 *negotiation = true;
282 break;
283
284 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
285 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
286 *negotiation = false;
287 break;
288
289 default:
290 status = IXGBE_ERR_LINK_SETUP;
291 goto out;
292 break;
293 }
294
295 if (hw->phy.multispeed_fiber) {
296 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
297 IXGBE_LINK_SPEED_1GB_FULL;
298 *negotiation = true;
299 }
300
301out:
302 return status;
303}
304
305/**
306 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
307 * @hw: pointer to hardware structure
308 * @speed: pointer to link speed
309 * @autoneg: boolean auto-negotiation value
310 *
311 * Determines the link capabilities by reading the AUTOC register.
312 **/
313static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
314 ixgbe_link_speed *speed,
315 bool *autoneg)
316{
317 s32 status = IXGBE_ERR_LINK_SETUP;
318 u16 speed_ability;
319
320 *speed = 0;
321 *autoneg = true;
322
6b73e10d 323 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
11afc1b1
PW		 324 &speed_ability);
325
326 if (status == 0) {
6b73e10d 327 if (speed_ability & MDIO_SPEED_10G)
11afc1b1 328 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
6b73e10d 329 if (speed_ability & MDIO_PMA_SPEED_1000)
11afc1b1
PW		 330 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
331 }
332
333 return status;
334}
335
336/**
337 * ixgbe_get_media_type_82599 - Get media type
338 * @hw: pointer to hardware structure
339 *
340 * Returns the media type (fiber, copper, backplane)
341 **/
7b25cdba 342static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 343{
344 enum ixgbe_media_type media_type;
345
346 /* Detect if there is a copper PHY attached. */
347 if (hw->phy.type == ixgbe_phy_cu_unknown ||
348 hw->phy.type == ixgbe_phy_tn) {
349 media_type = ixgbe_media_type_copper;
350 goto out;
351 }
352
353 switch (hw->device_id) {
11afc1b1 354 case IXGBE_DEV_ID_82599_KX4:
dbfec662 355 case IXGBE_DEV_ID_82599_KX4_MEZZ:
312eb931 356 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
74757d49 357 case IXGBE_DEV_ID_82599_KR:
1fcf03e6 358 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 359 /* Default device ID is mezzanine card KX/KX4 */
360 media_type = ixgbe_media_type_backplane;
361 break;
362 case IXGBE_DEV_ID_82599_SFP:
38ad1c8e 363 case IXGBE_DEV_ID_82599_SFP_EM:
11afc1b1
PW		 364 media_type = ixgbe_media_type_fiber;
365 break;
8911184f 366 case IXGBE_DEV_ID_82599_CX4:
6b1be199 367 media_type = ixgbe_media_type_cx4;
8911184f 368 break;
11afc1b1
PW		 369 default:
370 media_type = ixgbe_media_type_unknown;
371 break;
372 }
373out:
374 return media_type;
375}
376
377/**
8620a103 378 * ixgbe_start_mac_link_82599 - Setup MAC link settings
11afc1b1 379 * @hw: pointer to hardware structure
8620a103 380 * @autoneg_wait_to_complete: true when waiting for completion is needed
11afc1b1
PW		 381 *
382 * Configures link settings based on values in the ixgbe_hw struct.
383 * Restarts the link. Performs autonegotiation if needed.
384 **/
8620a103
MC		 385s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
386 bool autoneg_wait_to_complete)
11afc1b1
PW		 387{
388 u32 autoc_reg;
389 u32 links_reg;
390 u32 i;
391 s32 status = 0;
392
393 /* Restart link */
394 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
395 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
396 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
397
398 /* Only poll for autoneg to complete if specified to do so */
8620a103 399 if (autoneg_wait_to_complete) {
11afc1b1
PW		 400 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
401 IXGBE_AUTOC_LMS_KX4_KX_KR ||
402 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
403 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
404 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
405 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
406 links_reg = 0; /* Just in case Autoneg time = 0 */
407 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
408 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
409 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
410 break;
411 msleep(100);
412 }
413 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
414 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
415 hw_dbg(hw, "Autoneg did not complete.\n");
416 }
417 }
418 }
419
11afc1b1
PW		 420 /* Add delay to filter out noises during initial link setup */
421 msleep(50);
422
423 return status;
424}
425
61fac744
PW		 426 /**
427 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
428 * @hw: pointer to hardware structure
429 *
430 * The base drivers may require better control over SFP+ module
431 * PHY states. This includes selectively shutting down the Tx
432 * laser on the PHY, effectively halting physical link.
433 **/
434void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
435{
436 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
437
438 /* Disable tx laser; allow 100us to go dark per spec */
439 esdp_reg |= IXGBE_ESDP_SDP3;
440 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
441 IXGBE_WRITE_FLUSH(hw);
442 udelay(100);
443}
444
445/**
446 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
447 * @hw: pointer to hardware structure
448 *
449 * The base drivers may require better control over SFP+ module
450 * PHY states. This includes selectively turning on the Tx
451 * laser on the PHY, effectively starting physical link.
452 **/
453void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
454{
455 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
456
457 /* Enable tx laser; allow 100ms to light up */
458 esdp_reg &= ~IXGBE_ESDP_SDP3;
459 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
460 IXGBE_WRITE_FLUSH(hw);
461 msleep(100);
462}
463
1097cd17
MC		 464/**
465 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
466 * @hw: pointer to hardware structure
467 *
468 * When the driver changes the link speeds that it can support,
469 * it sets autotry_restart to true to indicate that we need to
470 * initiate a new autotry session with the link partner. To do
471 * so, we set the speed then disable and re-enable the tx laser, to
472 * alert the link partner that it also needs to restart autotry on its
473 * end. This is consistent with true clause 37 autoneg, which also
474 * involves a loss of signal.
475 **/
476void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
477{
1097cd17
MC		 478 hw_dbg(hw, "ixgbe_flap_tx_laser_multispeed_fiber\n");
479
480 if (hw->mac.autotry_restart) {
61fac744
PW		 481 ixgbe_disable_tx_laser_multispeed_fiber(hw);
482 ixgbe_enable_tx_laser_multispeed_fiber(hw);
1097cd17
MC		 483 hw->mac.autotry_restart = false;
484 }
485}
486
11afc1b1 487/**
8620a103 488 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
11afc1b1
PW		 489 * @hw: pointer to hardware structure
490 * @speed: new link speed
491 * @autoneg: true if autonegotiation enabled
492 * @autoneg_wait_to_complete: true when waiting for completion is needed
493 *
494 * Set the link speed in the AUTOC register and restarts link.
495 **/
8620a103
MC		 496s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
497 ixgbe_link_speed speed,
498 bool autoneg,
499 bool autoneg_wait_to_complete)
11afc1b1
PW		 500{
501 s32 status = 0;
502 ixgbe_link_speed phy_link_speed;
503 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
504 u32 speedcnt = 0;
505 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
506 bool link_up = false;
507 bool negotiation;
50ac58ba 508 int i;
11afc1b1
PW		 509
510 /* Mask off requested but non-supported speeds */
511 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
512 speed &= phy_link_speed;
513
514 /*
515 * Try each speed one by one, highest priority first. We do this in
516 * software because 10gb fiber doesn't support speed autonegotiation.
517 */
518 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
519 speedcnt++;
520 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
521
50ac58ba
PWJ		 522 /* If we already have link at this speed, just jump out */
523 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
524
525 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
526 goto out;
527
528 /* Set the module link speed */
11afc1b1
PW		 529 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
530 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
1097cd17 531 IXGBE_WRITE_FLUSH(hw);
11afc1b1 532
50ac58ba
PWJ		 533 /* Allow module to change analog characteristics (1G->10G) */
534 msleep(40);
11afc1b1 535
8620a103
MC		 536 status = ixgbe_setup_mac_link_82599(hw,
537 IXGBE_LINK_SPEED_10GB_FULL,
538 autoneg,
539 autoneg_wait_to_complete);
50ac58ba 540 if (status != 0)
c3c74327 541 return status;
50ac58ba
PWJ		 542
543 /* Flap the tx laser if it has not already been done */
1097cd17 544 hw->mac.ops.flap_tx_laser(hw);
50ac58ba 545
cd7e1f0b
DS		 546 /*
547 * Wait for the controller to acquire link. Per IEEE 802.3ap,
548 * Section 73.10.2, we may have to wait up to 500ms if KR is
549 * attempted. 82599 uses the same timing for 10g SFI.
550 */
551
50ac58ba
PWJ		 552 for (i = 0; i < 5; i++) {
553 /* Wait for the link partner to also set speed */
554 msleep(100);
555
556 /* If we have link, just jump out */
557 hw->mac.ops.check_link(hw, &phy_link_speed,
558 &link_up, false);
559 if (link_up)
560 goto out;
561 }
11afc1b1
PW		 562 }
563
564 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
565 speedcnt++;
566 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
567 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
568
50ac58ba
PWJ		 569 /* If we already have link at this speed, just jump out */
570 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
571
572 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
573 goto out;
574
575 /* Set the module link speed */
11afc1b1
PW		 576 esdp_reg &= ~IXGBE_ESDP_SDP5;
577 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
578 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
1097cd17 579 IXGBE_WRITE_FLUSH(hw);
11afc1b1 580
50ac58ba
PWJ		 581 /* Allow module to change analog characteristics (10G->1G) */
582 msleep(40);
11afc1b1 583
8620a103 584 status = ixgbe_setup_mac_link_82599(hw,
50ac58ba
PWJ		 585 IXGBE_LINK_SPEED_1GB_FULL,
586 autoneg,
587 autoneg_wait_to_complete);
588 if (status != 0)
c3c74327 589 return status;
50ac58ba
PWJ		 590
591 /* Flap the tx laser if it has not already been done */
1097cd17 592 hw->mac.ops.flap_tx_laser(hw);
50ac58ba
PWJ		 593
594 /* Wait for the link partner to also set speed */
595 msleep(100);
11afc1b1
PW		 596
597 /* If we have link, just jump out */
598 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
599 if (link_up)
600 goto out;
601 }
602
603 /*
604 * We didn't get link. Configure back to the highest speed we tried,
605 * (if there was more than one). We call ourselves back with just the
606 * single highest speed that the user requested.
607 */
608 if (speedcnt > 1)
8620a103
MC		 609 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
610 highest_link_speed,
611 autoneg,
612 autoneg_wait_to_complete);
11afc1b1
PW		 613
614out:
c3c74327
MC		 615 /* Set autoneg_advertised value based on input link speed */
616 hw->phy.autoneg_advertised = 0;
617
618 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
619 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
620
621 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
622 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
623
11afc1b1
PW		 624 return status;
625}
626
cd7e1f0b
DS		 627/**
628 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
629 * @hw: pointer to hardware structure
630 * @speed: new link speed
631 * @autoneg: true if autonegotiation enabled
632 * @autoneg_wait_to_complete: true when waiting for completion is needed
633 *
634 * Implements the Intel SmartSpeed algorithm.
635 **/
636static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
637 ixgbe_link_speed speed, bool autoneg,
638 bool autoneg_wait_to_complete)
639{
640 s32 status = 0;
641 ixgbe_link_speed link_speed;
642 s32 i, j;
643 bool link_up = false;
644 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
c4ee6a53 645 struct ixgbe_adapter *adapter = hw->back;
cd7e1f0b
DS		 646
647 hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n");
648
649 /* Set autoneg_advertised value based on input link speed */
650 hw->phy.autoneg_advertised = 0;
651
652 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
653 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
654
655 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
656 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
657
658 if (speed & IXGBE_LINK_SPEED_100_FULL)
659 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
660
661 /*
662 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
663 * autoneg advertisement if link is unable to be established at the
664 * highest negotiated rate. This can sometimes happen due to integrity
665 * issues with the physical media connection.
666 */
667
668 /* First, try to get link with full advertisement */
669 hw->phy.smart_speed_active = false;
670 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
671 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
672 autoneg_wait_to_complete);
673 if (status)
674 goto out;
675
676 /*
677 * Wait for the controller to acquire link. Per IEEE 802.3ap,
678 * Section 73.10.2, we may have to wait up to 500ms if KR is
679 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
680 * Table 9 in the AN MAS.
681 */
682 for (i = 0; i < 5; i++) {
683 mdelay(100);
684
685 /* If we have link, just jump out */
686 hw->mac.ops.check_link(hw, &link_speed,
687 &link_up, false);
688 if (link_up)
689 goto out;
690 }
691 }
692
693 /*
694 * We didn't get link. If we advertised KR plus one of KX4/KX
695 * (or BX4/BX), then disable KR and try again.
696 */
697 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
698 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
699 goto out;
700
701 /* Turn SmartSpeed on to disable KR support */
702 hw->phy.smart_speed_active = true;
703 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
704 autoneg_wait_to_complete);
705 if (status)
706 goto out;
707
708 /*
709 * Wait for the controller to acquire link. 600ms will allow for
710 * the AN link_fail_inhibit_timer as well for multiple cycles of
711 * parallel detect, both 10g and 1g. This allows for the maximum
712 * connect attempts as defined in the AN MAS table 73-7.
713 */
714 for (i = 0; i < 6; i++) {
715 mdelay(100);
716
717 /* If we have link, just jump out */
718 hw->mac.ops.check_link(hw, &link_speed,
719 &link_up, false);
720 if (link_up)
721 goto out;
722 }
723
724 /* We didn't get link. Turn SmartSpeed back off. */
725 hw->phy.smart_speed_active = false;
726 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
727 autoneg_wait_to_complete);
728
729out:
c4ee6a53
AS		 730 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
731 netif_info(adapter, hw, adapter->netdev, "Smartspeed has"
732 " downgraded the link speed from the maximum"
733 " advertised\n");
cd7e1f0b
DS		 734 return status;
735}
736
11afc1b1
PW		 737/**
738 * ixgbe_check_mac_link_82599 - Determine link and speed status
739 * @hw: pointer to hardware structure
740 * @speed: pointer to link speed
741 * @link_up: true when link is up
742 * @link_up_wait_to_complete: bool used to wait for link up or not
743 *
744 * Reads the links register to determine if link is up and the current speed
745 **/
7b25cdba
DS		 746static s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
747 ixgbe_link_speed *speed,
748 bool *link_up,
749 bool link_up_wait_to_complete)
11afc1b1
PW		 750{
751 u32 links_reg;
752 u32 i;
753
754 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
755 if (link_up_wait_to_complete) {
756 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
757 if (links_reg & IXGBE_LINKS_UP) {
758 *link_up = true;
759 break;
760 } else {
761 *link_up = false;
762 }
763 msleep(100);
764 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
765 }
766 } else {
767 if (links_reg & IXGBE_LINKS_UP)
768 *link_up = true;
769 else
770 *link_up = false;
771 }
772
773 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
774 IXGBE_LINKS_SPEED_10G_82599)
775 *speed = IXGBE_LINK_SPEED_10GB_FULL;
776 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
777 IXGBE_LINKS_SPEED_1G_82599)
778 *speed = IXGBE_LINK_SPEED_1GB_FULL;
779 else
780 *speed = IXGBE_LINK_SPEED_100_FULL;
781
620fa036
MC		 782 /* if link is down, zero out the current_mode */
783 if (*link_up == false) {
784 hw->fc.current_mode = ixgbe_fc_none;
785 hw->fc.fc_was_autonegged = false;
786 }
11afc1b1
PW		 787
788 return 0;
789}
790
791/**
8620a103 792 * ixgbe_setup_mac_link_82599 - Set MAC link speed
11afc1b1
PW		 793 * @hw: pointer to hardware structure
794 * @speed: new link speed
795 * @autoneg: true if autonegotiation enabled
796 * @autoneg_wait_to_complete: true when waiting for completion is needed
797 *
798 * Set the link speed in the AUTOC register and restarts link.
799 **/
8620a103
MC		 800s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
801 ixgbe_link_speed speed, bool autoneg,
802 bool autoneg_wait_to_complete)
11afc1b1
PW		 803{
804 s32 status = 0;
805 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
806 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
50ac58ba 807 u32 start_autoc = autoc;
1eb99d5a 808 u32 orig_autoc = 0;
11afc1b1
PW		 809 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
810 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
811 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
812 u32 links_reg;
813 u32 i;
814 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
815
816 /* Check to see if speed passed in is supported. */
817 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
818 speed &= link_capabilities;
819
50ac58ba
PWJ		 820 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
821 status = IXGBE_ERR_LINK_SETUP;
822 goto out;
823 }
824
1eb99d5a
PW		 825 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
826 if (hw->mac.orig_link_settings_stored)
827 orig_autoc = hw->mac.orig_autoc;
828 else
829 orig_autoc = autoc;
830
831
50ac58ba
PWJ		 832 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
833 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
834 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
11afc1b1
PW		 835 /* Set KX4/KX/KR support according to speed requested */
836 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
837 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 838 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 839 autoc |= IXGBE_AUTOC_KX4_SUPP;
cd7e1f0b
DS		 840 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
841 (hw->phy.smart_speed_active == false))
11afc1b1
PW		 842 autoc |= IXGBE_AUTOC_KR_SUPP;
843 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
844 autoc |= IXGBE_AUTOC_KX_SUPP;
845 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
846 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
847 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
848 /* Switch from 1G SFI to 10G SFI if requested */
849 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
850 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
851 autoc &= ~IXGBE_AUTOC_LMS_MASK;
852 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
853 }
854 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
855 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
856 /* Switch from 10G SFI to 1G SFI if requested */
857 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
858 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
859 autoc &= ~IXGBE_AUTOC_LMS_MASK;
860 if (autoneg)
861 autoc |= IXGBE_AUTOC_LMS_1G_AN;
862 else
863 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
864 }
865 }
866
50ac58ba 867 if (autoc != start_autoc) {
11afc1b1
PW		 868 /* Restart link */
869 autoc |= IXGBE_AUTOC_AN_RESTART;
870 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
871
872 /* Only poll for autoneg to complete if specified to do so */
873 if (autoneg_wait_to_complete) {
874 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
875 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
876 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
877 links_reg = 0; /*Just in case Autoneg time=0*/
878 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
879 links_reg =
880 IXGBE_READ_REG(hw, IXGBE_LINKS);
881 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
882 break;
883 msleep(100);
884 }
885 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
886 status =
887 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
888 hw_dbg(hw, "Autoneg did not "
889 "complete.\n");
890 }
891 }
892 }
893
11afc1b1
PW		 894 /* Add delay to filter out noises during initial link setup */
895 msleep(50);
896 }
897
50ac58ba 898out:
11afc1b1
PW		 899 return status;
900}
901
902/**
8620a103 903 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
11afc1b1
PW		 904 * @hw: pointer to hardware structure
905 * @speed: new link speed
906 * @autoneg: true if autonegotiation enabled
907 * @autoneg_wait_to_complete: true if waiting is needed to complete
908 *
909 * Restarts link on PHY and MAC based on settings passed in.
910 **/
8620a103
MC		 911static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
912 ixgbe_link_speed speed,
913 bool autoneg,
914 bool autoneg_wait_to_complete)
11afc1b1
PW		 915{
916 s32 status;
917
918 /* Setup the PHY according to input speed */
919 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
920 autoneg_wait_to_complete);
921 /* Set up MAC */
8620a103 922 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
11afc1b1
PW		 923
924 return status;
925}
926
927/**
928 * ixgbe_reset_hw_82599 - Perform hardware reset
929 * @hw: pointer to hardware structure
930 *
931 * Resets the hardware by resetting the transmit and receive units, masks
932 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
933 * reset.
934 **/
7b25cdba 935static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 936{
937 s32 status = 0;
c9205697 938 u32 ctrl;
11afc1b1
PW		 939 u32 i;
940 u32 autoc;
941 u32 autoc2;
942
943 /* Call adapter stop to disable tx/rx and clear interrupts */
944 hw->mac.ops.stop_adapter(hw);
945
553b4497 946 /* PHY ops must be identified and initialized prior to reset */
04f165ef 947
553b4497
PW		 948 /* Init PHY and function pointers, perform SFP setup */
949 status = hw->phy.ops.init(hw);
04f165ef 950
553b4497
PW		 951 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
952 goto reset_hw_out;
04f165ef 953
553b4497
PW		 954 /* Setup SFP module if there is one present. */
955 if (hw->phy.sfp_setup_needed) {
956 status = hw->mac.ops.setup_sfp(hw);
957 hw->phy.sfp_setup_needed = false;
04f165ef 958 }
11afc1b1 959
553b4497
PW		 960 /* Reset PHY */
961 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
962 hw->phy.ops.reset(hw);
963
11afc1b1
PW		 964 /*
965 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
966 * access and verify no pending requests before reset
967 */
04f165ef
PW		 968 status = ixgbe_disable_pcie_master(hw);
969 if (status != 0) {
11afc1b1
PW		 970 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
971 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
972 }
973
974 /*
975 * Issue global reset to the MAC. This needs to be a SW reset.
976 * If link reset is used, it might reset the MAC when mng is using it
977 */
978 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
979 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
980 IXGBE_WRITE_FLUSH(hw);
981
982 /* Poll for reset bit to self-clear indicating reset is complete */
983 for (i = 0; i < 10; i++) {
984 udelay(1);
985 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
986 if (!(ctrl & IXGBE_CTRL_RST))
987 break;
988 }
989 if (ctrl & IXGBE_CTRL_RST) {
990 status = IXGBE_ERR_RESET_FAILED;
991 hw_dbg(hw, "Reset polling failed to complete.\n");
992 }
11afc1b1
PW		 993
994 msleep(50);
995
11afc1b1
PW		 996 /*
997 * Store the original AUTOC/AUTOC2 values if they have not been
998 * stored off yet. Otherwise restore the stored original
999 * values since the reset operation sets back to defaults.
1000 */
1001 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1002 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1003 if (hw->mac.orig_link_settings_stored == false) {
1004 hw->mac.orig_autoc = autoc;
1005 hw->mac.orig_autoc2 = autoc2;
1006 hw->mac.orig_link_settings_stored = true;
4df10466 1007 } else {
11afc1b1
PW		 1008 if (autoc != hw->mac.orig_autoc)
1009 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
1010 IXGBE_AUTOC_AN_RESTART));
1011
1012 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1013 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1014 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1015 autoc2 |= (hw->mac.orig_autoc2 &
1016 IXGBE_AUTOC2_UPPER_MASK);
1017 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1018 }
1019 }
1020
aca6bee7
WJP		 1021 /*
1022 * Store MAC address from RAR0, clear receive address registers, and
1023 * clear the multicast table. Also reset num_rar_entries to 128,
1024 * since we modify this value when programming the SAN MAC address.
1025 */
1026 hw->mac.num_rar_entries = 128;
1027 hw->mac.ops.init_rx_addrs(hw);
1028
11afc1b1
PW		 1029 /* Store the permanent mac address */
1030 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1031
0365e6e4
PW		 1032 /* Store the permanent SAN mac address */
1033 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1034
aca6bee7
WJP		 1035 /* Add the SAN MAC address to the RAR only if it's a valid address */
1036 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1037 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1038 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1039
1040 /* Reserve the last RAR for the SAN MAC address */
1041 hw->mac.num_rar_entries--;
1042 }
1043
383ff34b
YZ		 1044 /* Store the alternative WWNN/WWPN prefix */
1045 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1046 &hw->mac.wwpn_prefix);
1047
04f165ef 1048reset_hw_out:
11afc1b1
PW		 1049 return status;
1050}
1051
1052/**
1053 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
1054 * @hw: pointer to hardware struct
1055 * @rar: receive address register index to disassociate
1056 * @vmdq: VMDq pool index to remove from the rar
1057 **/
7b25cdba 1058static s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
11afc1b1
PW		 1059{
1060 u32 mpsar_lo, mpsar_hi;
1061 u32 rar_entries = hw->mac.num_rar_entries;
1062
1063 if (rar < rar_entries) {
1064 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1065 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1066
1067 if (!mpsar_lo && !mpsar_hi)
1068 goto done;
1069
1070 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
1071 if (mpsar_lo) {
1072 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
1073 mpsar_lo = 0;
1074 }
1075 if (mpsar_hi) {
1076 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
1077 mpsar_hi = 0;
1078 }
1079 } else if (vmdq < 32) {
1080 mpsar_lo &= ~(1 << vmdq);
1081 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
1082 } else {
1083 mpsar_hi &= ~(1 << (vmdq - 32));
1084 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
1085 }
1086
1087 /* was that the last pool using this rar? */
1088 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
1089 hw->mac.ops.clear_rar(hw, rar);
1090 } else {
1091 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1092 }
1093
1094done:
1095 return 0;
1096}
1097
1098/**
1099 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
1100 * @hw: pointer to hardware struct
1101 * @rar: receive address register index to associate with a VMDq index
1102 * @vmdq: VMDq pool index
1103 **/
7b25cdba 1104static s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
11afc1b1
PW		 1105{
1106 u32 mpsar;
1107 u32 rar_entries = hw->mac.num_rar_entries;
1108
1109 if (rar < rar_entries) {
1110 if (vmdq < 32) {
1111 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1112 mpsar |= 1 << vmdq;
1113 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
1114 } else {
1115 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1116 mpsar |= 1 << (vmdq - 32);
1117 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
1118 }
1119 } else {
1120 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1121 }
1122 return 0;
1123}
1124
1125/**
1126 * ixgbe_set_vfta_82599 - Set VLAN filter table
1127 * @hw: pointer to hardware structure
1128 * @vlan: VLAN id to write to VLAN filter
1129 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1130 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1131 *
1132 * Turn on/off specified VLAN in the VLAN filter table.
1133 **/
7b25cdba
DS		 1134static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1135 bool vlan_on)
11afc1b1
PW		 1136{
1137 u32 regindex;
096a58fd 1138 u32 vlvf_index;
11afc1b1
PW		 1139 u32 bitindex;
1140 u32 bits;
1141 u32 first_empty_slot;
096a58fd 1142 u32 vt_ctl;
11afc1b1
PW		 1143
1144 if (vlan > 4095)
1145 return IXGBE_ERR_PARAM;
1146
1147 /*
1148 * this is a 2 part operation - first the VFTA, then the
1149 * VLVF and VLVFB if vind is set
1150 */
1151
1152 /* Part 1
1153 * The VFTA is a bitstring made up of 128 32-bit registers
1154 * that enable the particular VLAN id, much like the MTA:
1155 * bits[11-5]: which register
1156 * bits[4-0]: which bit in the register
1157 */
1158 regindex = (vlan >> 5) & 0x7F;
1159 bitindex = vlan & 0x1F;
1160 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1161 if (vlan_on)
1162 bits |= (1 << bitindex);
1163 else
1164 bits &= ~(1 << bitindex);
1165 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1166
1167
1168 /* Part 2
096a58fd 1169 * If VT mode is set
11afc1b1
PW		 1170 * Either vlan_on
1171 * make sure the vlan is in VLVF
1172 * set the vind bit in the matching VLVFB
1173 * Or !vlan_on
1174 * clear the pool bit and possibly the vind
1175 */
096a58fd
GR		 1176 vt_ctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1177 if (!(vt_ctl & IXGBE_VT_CTL_VT_ENABLE))
1178 goto out;
11afc1b1 1179
096a58fd
GR		 1180 /* find the vlanid or the first empty slot */
1181 first_empty_slot = 0;
1182
1183 for (vlvf_index = 1; vlvf_index < IXGBE_VLVF_ENTRIES; vlvf_index++) {
1184 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(vlvf_index));
1185 if (!bits && !first_empty_slot)
1186 first_empty_slot = vlvf_index;
1187 else if ((bits & 0x0FFF) == vlan)
1188 break;
1189 }
1190
1191 if (vlvf_index >= IXGBE_VLVF_ENTRIES) {
1192 if (first_empty_slot)
1193 vlvf_index = first_empty_slot;
1194 else {
1195 hw_dbg(hw, "No space in VLVF.\n");
1196 goto out;
11afc1b1 1197 }
096a58fd 1198 }
11afc1b1 1199
096a58fd
GR		 1200 if (vlan_on) {
1201 /* set the pool bit */
1202 if (vind < 32) {
1203 bits = IXGBE_READ_REG(hw,
1204 IXGBE_VLVFB(vlvf_index * 2));
1205 bits |= (1 << vind);
1206 IXGBE_WRITE_REG(hw,
1207 IXGBE_VLVFB(vlvf_index * 2), bits);
11afc1b1 1208 } else {
096a58fd
GR		 1209 bits = IXGBE_READ_REG(hw,
1210 IXGBE_VLVFB((vlvf_index * 2) + 1));
1211 bits |= (1 << (vind - 32));
1212 IXGBE_WRITE_REG(hw,
1213 IXGBE_VLVFB((vlvf_index * 2) + 1), bits);
1214 }
1215 } else {
1216 /* clear the pool bit */
1217 if (vind < 32) {
1218 bits = IXGBE_READ_REG(hw,
1219 IXGBE_VLVFB(vlvf_index * 2));
11afc1b1 1220 bits &= ~(1 << vind);
096a58fd
GR		 1221 IXGBE_WRITE_REG(hw,
1222 IXGBE_VLVFB(vlvf_index * 2), bits);
1223 bits |= IXGBE_READ_REG(hw,
1224 IXGBE_VLVFB((vlvf_index * 2) + 1));
1225 } else {
1226 bits = IXGBE_READ_REG(hw,
1227 IXGBE_VLVFB((vlvf_index * 2) + 1));
1228 bits &= ~(1 << (vind - 32));
1229 IXGBE_WRITE_REG(hw,
1230 IXGBE_VLVFB((vlvf_index * 2) + 1), bits);
1231 bits |= IXGBE_READ_REG(hw,
1232 IXGBE_VLVFB(vlvf_index * 2));
11afc1b1 1233 }
096a58fd 1234 }
11afc1b1 1235
096a58fd
GR		 1236 if (bits) {
1237 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
1238 (IXGBE_VLVF_VIEN | vlan));
1239 /* if bits is non-zero then some pools/VFs are still
1240 * using this VLAN ID. Force the VFTA entry to on */
1241 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1242 bits |= (1 << bitindex);
1243 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
11afc1b1 1244 }
096a58fd
GR		 1245 else
1246 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
11afc1b1
PW		 1247
1248out:
1249 return 0;
1250}
1251
1252/**
1253 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1254 * @hw: pointer to hardware structure
1255 *
1256 * Clears the VLAN filer table, and the VMDq index associated with the filter
1257 **/
7b25cdba 1258static s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1259{
1260 u32 offset;
1261
1262 for (offset = 0; offset < hw->mac.vft_size; offset++)
1263 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1264
1265 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1266 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1267 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1268 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1269 }
1270
1271 return 0;
1272}
1273
11afc1b1
PW		 1274/**
1275 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1276 * @hw: pointer to hardware structure
1277 **/
7b25cdba 1278static s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1279{
1280 int i;
1281 hw_dbg(hw, " Clearing UTA\n");
1282
1283 for (i = 0; i < 128; i++)
1284 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1285
1286 return 0;
1287}
1288
ffff4772
PWJ		 1289/**
1290 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1291 * @hw: pointer to hardware structure
1292 **/
1293s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1294{
1295 int i;
1296 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1297 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1298
1299 /*
1300 * Before starting reinitialization process,
1301 * FDIRCMD.CMD must be zero.
1302 */
1303 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1304 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1305 IXGBE_FDIRCMD_CMD_MASK))
1306 break;
1307 udelay(10);
1308 }
1309 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1310 hw_dbg(hw ,"Flow Director previous command isn't complete, "
d6dbee86 1311 "aborting table re-initialization.\n");
ffff4772
PWJ		 1312 return IXGBE_ERR_FDIR_REINIT_FAILED;
1313 }
1314
1315 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1316 IXGBE_WRITE_FLUSH(hw);
1317 /*
1318 * 82599 adapters flow director init flow cannot be restarted,
1319 * Workaround 82599 silicon errata by performing the following steps
1320 * before re-writing the FDIRCTRL control register with the same value.
1321 * - write 1 to bit 8 of FDIRCMD register &
1322 * - write 0 to bit 8 of FDIRCMD register
1323 */
1324 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1325 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1326 IXGBE_FDIRCMD_CLEARHT));
1327 IXGBE_WRITE_FLUSH(hw);
1328 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1329 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1330 ~IXGBE_FDIRCMD_CLEARHT));
1331 IXGBE_WRITE_FLUSH(hw);
1332 /*
1333 * Clear FDIR Hash register to clear any leftover hashes
1334 * waiting to be programmed.
1335 */
1336 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1337 IXGBE_WRITE_FLUSH(hw);
1338
1339 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1340 IXGBE_WRITE_FLUSH(hw);
1341
1342 /* Poll init-done after we write FDIRCTRL register */
1343 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1344 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1345 IXGBE_FDIRCTRL_INIT_DONE)
1346 break;
1347 udelay(10);
1348 }
1349 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1350 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1351 return IXGBE_ERR_FDIR_REINIT_FAILED;
1352 }
1353
1354 /* Clear FDIR statistics registers (read to clear) */
1355 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1356 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1357 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1358 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1359 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1360
1361 return 0;
1362}
1363
1364/**
1365 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1366 * @hw: pointer to hardware structure
1367 * @pballoc: which mode to allocate filters with
1368 **/
1369s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1370{
1371 u32 fdirctrl = 0;
1372 u32 pbsize;
1373 int i;
1374
1375 /*
1376 * Before enabling Flow Director, the Rx Packet Buffer size
1377 * must be reduced. The new value is the current size minus
1378 * flow director memory usage size.
1379 */
1380 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1381 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1382 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1383
1384 /*
1385 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1386 * intialized to zero for non DCB mode otherwise actual total RX PB
1387 * would be bigger than programmed and filter space would run into
1388 * the PB 0 region.
1389 */
1390 for (i = 1; i < 8; i++)
1391 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1392
1393 /* Send interrupt when 64 filters are left */
1394 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1395
1396 /* Set the maximum length per hash bucket to 0xA filters */
1397 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1398
1399 switch (pballoc) {
1400 case IXGBE_FDIR_PBALLOC_64K:
1401 /* 8k - 1 signature filters */
1402 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1403 break;
1404 case IXGBE_FDIR_PBALLOC_128K:
1405 /* 16k - 1 signature filters */
1406 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1407 break;
1408 case IXGBE_FDIR_PBALLOC_256K:
1409 /* 32k - 1 signature filters */
1410 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1411 break;
1412 default:
1413 /* bad value */
1414 return IXGBE_ERR_CONFIG;
1415 };
1416
1417 /* Move the flexible bytes to use the ethertype - shift 6 words */
1418 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1419
1420 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1421
1422 /* Prime the keys for hashing */
1423 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1424 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1425 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1426 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1427
1428 /*
1429 * Poll init-done after we write the register. Estimated times:
1430 * 10G: PBALLOC = 11b, timing is 60us
1431 * 1G: PBALLOC = 11b, timing is 600us
1432 * 100M: PBALLOC = 11b, timing is 6ms
1433 *
1434 * Multiple these timings by 4 if under full Rx load
1435 *
1436 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1437 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1438 * this might not finish in our poll time, but we can live with that
1439 * for now.
1440 */
1441 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1442 IXGBE_WRITE_FLUSH(hw);
1443 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1444 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1445 IXGBE_FDIRCTRL_INIT_DONE)
1446 break;
1447 msleep(1);
1448 }
1449 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1450 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1451
1452 return 0;
1453}
1454
1455/**
1456 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1457 * @hw: pointer to hardware structure
1458 * @pballoc: which mode to allocate filters with
1459 **/
1460s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1461{
1462 u32 fdirctrl = 0;
1463 u32 pbsize;
1464 int i;
1465
1466 /*
1467 * Before enabling Flow Director, the Rx Packet Buffer size
1468 * must be reduced. The new value is the current size minus
1469 * flow director memory usage size.
1470 */
1471 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1472 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1473 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1474
1475 /*
1476 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1477 * intialized to zero for non DCB mode otherwise actual total RX PB
1478 * would be bigger than programmed and filter space would run into
1479 * the PB 0 region.
1480 */
1481 for (i = 1; i < 8; i++)
1482 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1483
1484 /* Send interrupt when 64 filters are left */
1485 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1486
9a713e7c
PW		 1487 /* Initialize the drop queue to Rx queue 127 */
1488 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1489
ffff4772
PWJ		 1490 switch (pballoc) {
1491 case IXGBE_FDIR_PBALLOC_64K:
1492 /* 2k - 1 perfect filters */
1493 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1494 break;
1495 case IXGBE_FDIR_PBALLOC_128K:
1496 /* 4k - 1 perfect filters */
1497 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1498 break;
1499 case IXGBE_FDIR_PBALLOC_256K:
1500 /* 8k - 1 perfect filters */
1501 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1502 break;
1503 default:
1504 /* bad value */
1505 return IXGBE_ERR_CONFIG;
1506 };
1507
1508 /* Turn perfect match filtering on */
1509 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1510 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1511
1512 /* Move the flexible bytes to use the ethertype - shift 6 words */
1513 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1514
1515 /* Prime the keys for hashing */
1516 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1517 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1518 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1519 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1520
1521 /*
1522 * Poll init-done after we write the register. Estimated times:
1523 * 10G: PBALLOC = 11b, timing is 60us
1524 * 1G: PBALLOC = 11b, timing is 600us
1525 * 100M: PBALLOC = 11b, timing is 6ms
1526 *
1527 * Multiple these timings by 4 if under full Rx load
1528 *
1529 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1530 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1531 * this might not finish in our poll time, but we can live with that
1532 * for now.
1533 */
1534
1535 /* Set the maximum length per hash bucket to 0xA filters */
1536 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1537
1538 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1539 IXGBE_WRITE_FLUSH(hw);
1540 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1541 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1542 IXGBE_FDIRCTRL_INIT_DONE)
1543 break;
1544 msleep(1);
1545 }
1546 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1547 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1548
1549 return 0;
1550}
1551
1552
1553/**
1554 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1555 * @stream: input bitstream to compute the hash on
1556 * @key: 32-bit hash key
1557 **/
7b25cdba
DS		 1558static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1559 u32 key)
ffff4772
PWJ		 1560{
1561 /*
1562 * The algorithm is as follows:
1563 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1564 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1565 * and A[n] x B[n] is bitwise AND between same length strings
1566 *
1567 * K[n] is 16 bits, defined as:
1568 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1569 * for n modulo 32 < 15, K[n] =
1570 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1571 *
1572 * S[n] is 16 bits, defined as:
1573 * for n >= 15, S[n] = S[n:n - 15]
1574 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1575 *
1576 * To simplify for programming, the algorithm is implemented
1577 * in software this way:
1578 *
1579 * Key[31:0], Stream[335:0]
1580 *
1581 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1582 * int_key[350:0] = tmp_key[351:1]
1583 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1584 *
1585 * hash[15:0] = 0;
1586 * for (i = 0; i < 351; i++) {
1587 * if (int_key[i])
1588 * hash ^= int_stream[(i + 15):i];
1589 * }
1590 */
1591
1592 union {
1593 u64 fill[6];
1594 u32 key[11];
1595 u8 key_stream[44];
1596 } tmp_key;
1597
1598 u8 *stream = (u8 *)atr_input;
1599 u8 int_key[44]; /* upper-most bit unused */
1600 u8 hash_str[46]; /* upper-most 2 bits unused */
1601 u16 hash_result = 0;
1602 int i, j, k, h;
1603
1604 /*
1605 * Initialize the fill member to prevent warnings
1606 * on some compilers
1607 */
1608 tmp_key.fill[0] = 0;
1609
1610 /* First load the temporary key stream */
1611 for (i = 0; i < 6; i++) {
1612 u64 fillkey = ((u64)key << 32) | key;
1613 tmp_key.fill[i] = fillkey;
1614 }
1615
1616 /*
1617 * Set the interim key for the hashing. Bit 352 is unused, so we must
1618 * shift and compensate when building the key.
1619 */
1620
1621 int_key[0] = tmp_key.key_stream[0] >> 1;
1622 for (i = 1, j = 0; i < 44; i++) {
1623 unsigned int this_key = tmp_key.key_stream[j] << 7;
1624 j++;
1625 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1626 }
1627
1628 /*
1629 * Set the interim bit string for the hashing. Bits 368 and 367 are
1630 * unused, so shift and compensate when building the string.
1631 */
1632 hash_str[0] = (stream[40] & 0x7f) >> 1;
1633 for (i = 1, j = 40; i < 46; i++) {
1634 unsigned int this_str = stream[j] << 7;
1635 j++;
1636 if (j > 41)
1637 j = 0;
1638 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1639 }
1640
1641 /*
1642 * Now compute the hash. i is the index into hash_str, j is into our
1643 * key stream, k is counting the number of bits, and h interates within
1644 * each byte.
1645 */
1646 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1647 for (h = 0; h < 8 && k < 351; h++, k++) {
1648 if (int_key[j] & (1 << h)) {
1649 /*
1650 * Key bit is set, XOR in the current 16-bit
1651 * string. Example of processing:
1652 * h = 0,
1653 * tmp = (hash_str[i - 2] & 0 << 16) |
1654 * (hash_str[i - 1] & 0xff << 8) |
1655 * (hash_str[i] & 0xff >> 0)
1656 * So tmp = hash_str[15 + k:k], since the
1657 * i + 2 clause rolls off the 16-bit value
1658 * h = 7,
1659 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1660 * (hash_str[i - 1] & 0xff << 1) |
1661 * (hash_str[i] & 0x80 >> 7)
1662 */
1663 int tmp = (hash_str[i] >> h);
1664 tmp |= (hash_str[i - 1] << (8 - h));
1665 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1666 << (16 - h);
1667 hash_result ^= (u16)tmp;
1668 }
1669 }
1670 }
1671
1672 return hash_result;
1673}
1674
1675/**
1676 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1677 * @input: input stream to modify
1678 * @vlan: the VLAN id to load
1679 **/
1680s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1681{
1682 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1683 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1684
1685 return 0;
1686}
1687
1688/**
1689 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1690 * @input: input stream to modify
1691 * @src_addr: the IP address to load
1692 **/
1693s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1694{
1695 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1696 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1697 (src_addr >> 16) & 0xff;
1698 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1699 (src_addr >> 8) & 0xff;
1700 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1701
1702 return 0;
1703}
1704
1705/**
1706 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1707 * @input: input stream to modify
1708 * @dst_addr: the IP address to load
1709 **/
1710s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1711{
1712 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1713 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1714 (dst_addr >> 16) & 0xff;
1715 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1716 (dst_addr >> 8) & 0xff;
1717 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1718
1719 return 0;
1720}
1721
1722/**
1723 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1724 * @input: input stream to modify
1725 * @src_addr_1: the first 4 bytes of the IP address to load
1726 * @src_addr_2: the second 4 bytes of the IP address to load
1727 * @src_addr_3: the third 4 bytes of the IP address to load
1728 * @src_addr_4: the fourth 4 bytes of the IP address to load
1729 **/
1730s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
9a713e7c
PW		 1731 u32 src_addr_1, u32 src_addr_2,
1732 u32 src_addr_3, u32 src_addr_4)
ffff4772
PWJ		 1733{
1734 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1735 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1736 (src_addr_4 >> 8) & 0xff;
1737 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1738 (src_addr_4 >> 16) & 0xff;
1739 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1740
1741 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1742 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1743 (src_addr_3 >> 8) & 0xff;
1744 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1745 (src_addr_3 >> 16) & 0xff;
1746 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1747
1748 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1749 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1750 (src_addr_2 >> 8) & 0xff;
1751 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1752 (src_addr_2 >> 16) & 0xff;
1753 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1754
1755 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1756 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1757 (src_addr_1 >> 8) & 0xff;
1758 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1759 (src_addr_1 >> 16) & 0xff;
1760 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1761
1762 return 0;
1763}
1764
1765/**
1766 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1767 * @input: input stream to modify
1768 * @dst_addr_1: the first 4 bytes of the IP address to load
1769 * @dst_addr_2: the second 4 bytes of the IP address to load
1770 * @dst_addr_3: the third 4 bytes of the IP address to load
1771 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1772 **/
1773s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
9a713e7c
PW		 1774 u32 dst_addr_1, u32 dst_addr_2,
1775 u32 dst_addr_3, u32 dst_addr_4)
ffff4772
PWJ		 1776{
1777 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1778 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1779 (dst_addr_4 >> 8) & 0xff;
1780 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1781 (dst_addr_4 >> 16) & 0xff;
1782 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1783
1784 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1785 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1786 (dst_addr_3 >> 8) & 0xff;
1787 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1788 (dst_addr_3 >> 16) & 0xff;
1789 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1790
1791 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1792 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1793 (dst_addr_2 >> 8) & 0xff;
1794 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1795 (dst_addr_2 >> 16) & 0xff;
1796 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1797
1798 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1799 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1800 (dst_addr_1 >> 8) & 0xff;
1801 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1802 (dst_addr_1 >> 16) & 0xff;
1803 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1804
1805 return 0;
1806}
1807
1808/**
1809 * ixgbe_atr_set_src_port_82599 - Sets the source port
1810 * @input: input stream to modify
1811 * @src_port: the source port to load
1812 **/
1813s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1814{
1815 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1816 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1817
1818 return 0;
1819}
1820
1821/**
1822 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1823 * @input: input stream to modify
1824 * @dst_port: the destination port to load
1825 **/
1826s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1827{
1828 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1829 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1830
1831 return 0;
1832}
1833
1834/**
1835 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1836 * @input: input stream to modify
1837 * @flex_bytes: the flexible bytes to load
1838 **/
1839s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1840{
1841 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1842 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1843
1844 return 0;
1845}
1846
1847/**
1848 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1849 * @input: input stream to modify
1850 * @vm_pool: the Virtual Machine pool to load
1851 **/
7b25cdba 1852s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
9a713e7c 1853 u8 vm_pool)
ffff4772
PWJ		 1854{
1855 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1856
1857 return 0;
1858}
1859
1860/**
1861 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1862 * @input: input stream to modify
1863 * @l4type: the layer 4 type value to load
1864 **/
1865s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1866{
1867 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1868
1869 return 0;
1870}
1871
1872/**
1873 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1874 * @input: input stream to search
1875 * @vlan: the VLAN id to load
1876 **/
9a713e7c 1877static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
ffff4772
PWJ		 1878{
1879 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1880 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1881
1882 return 0;
1883}
1884
1885/**
1886 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1887 * @input: input stream to search
1888 * @src_addr: the IP address to load
1889 **/
7b25cdba
DS		 1890static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1891 u32 *src_addr)
ffff4772
PWJ		 1892{
1893 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1894 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1895 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1896 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1897
1898 return 0;
1899}
1900
1901/**
1902 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1903 * @input: input stream to search
1904 * @dst_addr: the IP address to load
1905 **/
7b25cdba
DS		 1906static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1907 u32 *dst_addr)
ffff4772
PWJ		 1908{
1909 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1910 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1911 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1912 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1913
1914 return 0;
1915}
1916
1917/**
1918 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1919 * @input: input stream to search
1920 * @src_addr_1: the first 4 bytes of the IP address to load
1921 * @src_addr_2: the second 4 bytes of the IP address to load
1922 * @src_addr_3: the third 4 bytes of the IP address to load
1923 * @src_addr_4: the fourth 4 bytes of the IP address to load
1924 **/
7b25cdba
DS		 1925static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1926 u32 *src_addr_1, u32 *src_addr_2,
1927 u32 *src_addr_3, u32 *src_addr_4)
ffff4772
PWJ		 1928{
1929 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1930 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1931 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1932 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1933
1934 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1935 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1936 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1937 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1938
1939 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1940 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1941 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1942 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1943
1944 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1945 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1946 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1947 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1948
1949 return 0;
1950}
1951
1952/**
1953 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1954 * @input: input stream to search
1955 * @dst_addr_1: the first 4 bytes of the IP address to load
1956 * @dst_addr_2: the second 4 bytes of the IP address to load
1957 * @dst_addr_3: the third 4 bytes of the IP address to load
1958 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1959 **/
1960s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1961 u32 *dst_addr_1, u32 *dst_addr_2,
1962 u32 *dst_addr_3, u32 *dst_addr_4)
ffff4772
PWJ		 1963{
1964 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1965 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1966 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1967 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1968
1969 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1970 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1971 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1972 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1973
1974 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1975 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1976 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1977 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1978
1979 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1980 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1981 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1982 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1983
1984 return 0;
1985}
1986
1987/**
1988 * ixgbe_atr_get_src_port_82599 - Gets the source port
1989 * @input: input stream to modify
1990 * @src_port: the source port to load
1991 *
1992 * Even though the input is given in big-endian, the FDIRPORT registers
1993 * expect the ports to be programmed in little-endian. Hence the need to swap
1994 * endianness when retrieving the data. This can be confusing since the
1995 * internal hash engine expects it to be big-endian.
1996 **/
7b25cdba
DS		 1997static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1998 u16 *src_port)
ffff4772
PWJ		 1999{
2000 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
2001 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
2002
2003 return 0;
2004}
2005
2006/**
2007 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
2008 * @input: input stream to modify
2009 * @dst_port: the destination port to load
2010 *
2011 * Even though the input is given in big-endian, the FDIRPORT registers
2012 * expect the ports to be programmed in little-endian. Hence the need to swap
2013 * endianness when retrieving the data. This can be confusing since the
2014 * internal hash engine expects it to be big-endian.
2015 **/
7b25cdba
DS		 2016static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
2017 u16 *dst_port)
ffff4772
PWJ		 2018{
2019 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
2020 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
2021
2022 return 0;
2023}
2024
2025/**
2026 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
2027 * @input: input stream to modify
2028 * @flex_bytes: the flexible bytes to load
2029 **/
7b25cdba
DS		 2030static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
2031 u16 *flex_byte)
ffff4772
PWJ		 2032{
2033 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
2034 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
2035
2036 return 0;
2037}
2038
2039/**
2040 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
2041 * @input: input stream to modify
2042 * @vm_pool: the Virtual Machine pool to load
2043 **/
7b25cdba
DS		 2044s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
2045 u8 *vm_pool)
ffff4772
PWJ		 2046{
2047 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
2048
2049 return 0;
2050}
2051
2052/**
2053 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
2054 * @input: input stream to modify
2055 * @l4type: the layer 4 type value to load
2056 **/
7b25cdba
DS		 2057static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
2058 u8 *l4type)
ffff4772
PWJ		 2059{
2060 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
2061
2062 return 0;
2063}
2064
2065/**
2066 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
2067 * @hw: pointer to hardware structure
2068 * @stream: input bitstream
2069 * @queue: queue index to direct traffic to
2070 **/
2071s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
2072 struct ixgbe_atr_input *input,
2073 u8 queue)
2074{
2075 u64 fdirhashcmd;
2076 u64 fdircmd;
2077 u32 fdirhash;
2078 u16 bucket_hash, sig_hash;
2079 u8 l4type;
2080
2081 bucket_hash = ixgbe_atr_compute_hash_82599(input,
2082 IXGBE_ATR_BUCKET_HASH_KEY);
2083
2084 /* bucket_hash is only 15 bits */
2085 bucket_hash &= IXGBE_ATR_HASH_MASK;
2086
2087 sig_hash = ixgbe_atr_compute_hash_82599(input,
2088 IXGBE_ATR_SIGNATURE_HASH_KEY);
2089
2090 /* Get the l4type in order to program FDIRCMD properly */
2091 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
2092 ixgbe_atr_get_l4type_82599(input, &l4type);
2093
2094 /*
2095 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
2096 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
2097 */
2098 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2099
2100 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
2101 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
2102
2103 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2104 case IXGBE_ATR_L4TYPE_TCP:
2105 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
2106 break;
2107 case IXGBE_ATR_L4TYPE_UDP:
2108 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
2109 break;
2110 case IXGBE_ATR_L4TYPE_SCTP:
2111 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
2112 break;
2113 default:
2114 hw_dbg(hw, "Error on l4type input\n");
2115 return IXGBE_ERR_CONFIG;
2116 }
2117
2118 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
2119 fdircmd |= IXGBE_FDIRCMD_IPV6;
2120
2121 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
2122 fdirhashcmd = ((fdircmd << 32) | fdirhash);
2123
2124 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
2125
2126 return 0;
2127}
2128
2129/**
2130 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
2131 * @hw: pointer to hardware structure
2132 * @input: input bitstream
9a713e7c
PW		 2133 * @input_masks: bitwise masks for relevant fields
2134 * @soft_id: software index into the silicon hash tables for filter storage
ffff4772
PWJ		 2135 * @queue: queue index to direct traffic to
2136 *
2137 * Note that the caller to this function must lock before calling, since the
2138 * hardware writes must be protected from one another.
2139 **/
2140s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
9a713e7c
PW		 2141 struct ixgbe_atr_input *input,
2142 struct ixgbe_atr_input_masks *input_masks,
2143 u16 soft_id, u8 queue)
ffff4772
PWJ		 2144{
2145 u32 fdircmd = 0;
2146 u32 fdirhash;
9a713e7c 2147 u32 src_ipv4 = 0, dst_ipv4 = 0;
ffff4772
PWJ		 2148 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
2149 u16 src_port, dst_port, vlan_id, flex_bytes;
2150 u16 bucket_hash;
2151 u8 l4type;
9a713e7c 2152 u8 fdirm = 0;
ffff4772
PWJ		 2153
2154 /* Get our input values */
2155 ixgbe_atr_get_l4type_82599(input, &l4type);
2156
2157 /*
2158 * Check l4type formatting, and bail out before we touch the hardware
2159 * if there's a configuration issue
2160 */
2161 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2162 case IXGBE_ATR_L4TYPE_TCP:
2163 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
2164 break;
2165 case IXGBE_ATR_L4TYPE_UDP:
2166 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
2167 break;
2168 case IXGBE_ATR_L4TYPE_SCTP:
2169 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
2170 break;
2171 default:
2172 hw_dbg(hw, "Error on l4type input\n");
2173 return IXGBE_ERR_CONFIG;
2174 }
2175
2176 bucket_hash = ixgbe_atr_compute_hash_82599(input,
2177 IXGBE_ATR_BUCKET_HASH_KEY);
2178
2179 /* bucket_hash is only 15 bits */
2180 bucket_hash &= IXGBE_ATR_HASH_MASK;
2181
2182 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
2183 ixgbe_atr_get_src_port_82599(input, &src_port);
2184 ixgbe_atr_get_dst_port_82599(input, &dst_port);
2185 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
2186
2187 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2188
2189 /* Now figure out if we're IPv4 or IPv6 */
2190 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
2191 /* IPv6 */
2192 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
2193 &src_ipv6_3, &src_ipv6_4);
2194
2195 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
2196 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
2197 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
2198 /* The last 4 bytes is the same register as IPv4 */
2199 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
2200
2201 fdircmd |= IXGBE_FDIRCMD_IPV6;
2202 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
2203 } else {
2204 /* IPv4 */
2205 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
2206 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
ffff4772
PWJ		 2207 }
2208
2209 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
2210 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
2211
2212 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
2213 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
2214 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
9a713e7c
PW		 2215 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
2216
2217 /*
2218 * Program the relevant mask registers. If src/dst_port or src/dst_addr
2219 * are zero, then assume a full mask for that field. Also assume that
2220 * a VLAN of 0 is unspecified, so mask that out as well. L4type
2221 * cannot be masked out in this implementation.
2222 *
2223 * This also assumes IPv4 only. IPv6 masking isn't supported at this
2224 * point in time.
2225 */
2226 if (src_ipv4 == 0)
2227 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xffffffff);
2228 else
2229 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
2230
2231 if (dst_ipv4 == 0)
2232 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xffffffff);
2233 else
2234 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
2235
2236 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2237 case IXGBE_ATR_L4TYPE_TCP:
2238 if (src_port == 0)
2239 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xffff);
2240 else
2241 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
2242 input_masks->src_port_mask);
2243
2244 if (dst_port == 0)
2245 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
2246 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
2247 (0xffff << 16)));
2248 else
2249 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
2250 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
2251 (input_masks->dst_port_mask << 16)));
2252 break;
2253 case IXGBE_ATR_L4TYPE_UDP:
2254 if (src_port == 0)
2255 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xffff);
2256 else
2257 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
2258 input_masks->src_port_mask);
2259
2260 if (dst_port == 0)
2261 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
2262 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
2263 (0xffff << 16)));
2264 else
2265 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
2266 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
2267 (input_masks->src_port_mask << 16)));
2268 break;
2269 default:
2270 /* this already would have failed above */
2271 break;
2272 }
2273
2274 /* Program the last mask register, FDIRM */
2275 if (input_masks->vlan_id_mask || !vlan_id)
2276 /* Mask both VLAN and VLANP - bits 0 and 1 */
2277 fdirm |= 0x3;
2278
2279 if (input_masks->data_mask || !flex_bytes)
2280 /* Flex bytes need masking, so mask the whole thing - bit 4 */
2281 fdirm |= 0x10;
2282
2283 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
2284 fdirm |= 0x24;
2285
2286 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
ffff4772
PWJ		 2287
2288 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
2289 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
2290 fdircmd |= IXGBE_FDIRCMD_LAST;
2291 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
2292 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
2293
2294 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2295 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
2296
2297 return 0;
2298}
11afc1b1
PW		 2299/**
2300 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2301 * @hw: pointer to hardware structure
2302 * @reg: analog register to read
2303 * @val: read value
2304 *
2305 * Performs read operation to Omer analog register specified.
2306 **/
7b25cdba 2307static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
11afc1b1
PW		 2308{
2309 u32 core_ctl;
2310
2311 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2312 (reg << 8));
2313 IXGBE_WRITE_FLUSH(hw);
2314 udelay(10);
2315 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2316 *val = (u8)core_ctl;
2317
2318 return 0;
2319}
2320
2321/**
2322 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2323 * @hw: pointer to hardware structure
2324 * @reg: atlas register to write
2325 * @val: value to write
2326 *
2327 * Performs write operation to Omer analog register specified.
2328 **/
7b25cdba 2329static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
11afc1b1
PW		 2330{
2331 u32 core_ctl;
2332
2333 core_ctl = (reg << 8) | val;
2334 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2335 IXGBE_WRITE_FLUSH(hw);
2336 udelay(10);
2337
2338 return 0;
2339}
2340
2341/**
2342 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2343 * @hw: pointer to hardware structure
2344 *
2345 * Starts the hardware using the generic start_hw function.
2346 * Then performs device-specific:
2347 * Clears the rate limiter registers.
2348 **/
7b25cdba 2349static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2350{
2351 u32 q_num;
794caeb2 2352 s32 ret_val;
11afc1b1 2353
794caeb2 2354 ret_val = ixgbe_start_hw_generic(hw);
11afc1b1
PW		 2355
2356 /* Clear the rate limiters */
2357 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2358 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2359 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2360 }
2361 IXGBE_WRITE_FLUSH(hw);
2362
50ac58ba
PWJ		 2363 /* We need to run link autotry after the driver loads */
2364 hw->mac.autotry_restart = true;
2365
794caeb2
PWJ		 2366 if (ret_val == 0)
2367 ret_val = ixgbe_verify_fw_version_82599(hw);
2368
2369 return ret_val;
11afc1b1
PW		 2370}
2371
2372/**
2373 * ixgbe_identify_phy_82599 - Get physical layer module
2374 * @hw: pointer to hardware structure
2375 *
2376 * Determines the physical layer module found on the current adapter.
2377 **/
7b25cdba 2378static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2379{
2380 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2381 status = ixgbe_identify_phy_generic(hw);
2382 if (status != 0)
2383 status = ixgbe_identify_sfp_module_generic(hw);
2384 return status;
2385}
2386
2387/**
2388 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2389 * @hw: pointer to hardware structure
2390 *
2391 * Determines physical layer capabilities of the current configuration.
2392 **/
7b25cdba 2393static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2394{
2395 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 2396 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2397 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2398 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2399 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2400 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2401 u16 ext_ability = 0;
1339b9e9 2402 u8 comp_codes_10g = 0;
11afc1b1 2403
04193058
PWJ		 2404 hw->phy.ops.identify(hw);
2405
2406 if (hw->phy.type == ixgbe_phy_tn ||
2407 hw->phy.type == ixgbe_phy_cu_unknown) {
6b73e10d
BH		 2408 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2409 &ext_ability);
2410 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 2411 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 2412 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 2413 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 2414 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 2415 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2416 goto out;
2417 }
2418
2419 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2420 case IXGBE_AUTOC_LMS_1G_AN:
2421 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2422 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2423 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2424 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2425 goto out;
2426 } else
2427 /* SFI mode so read SFP module */
2428 goto sfp_check;
11afc1b1 2429 break;
04193058
PWJ		 2430 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2431 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2432 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2433 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2434 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 2435 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2436 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 2437 goto out;
2438 break;
2439 case IXGBE_AUTOC_LMS_10G_SERIAL:
2440 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2441 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2442 goto out;
2443 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2444 goto sfp_check;
2445 break;
2446 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2447 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2448 if (autoc & IXGBE_AUTOC_KX_SUPP)
2449 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2450 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2451 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2452 if (autoc & IXGBE_AUTOC_KR_SUPP)
2453 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2454 goto out;
2455 break;
2456 default:
2457 goto out;
2458 break;
2459 }
11afc1b1 2460
04193058
PWJ		 2461sfp_check:
2462 /* SFP check must be done last since DA modules are sometimes used to
2463 * test KR mode - we need to id KR mode correctly before SFP module.
2464 * Call identify_sfp because the pluggable module may have changed */
2465 hw->phy.ops.identify_sfp(hw);
2466 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2467 goto out;
2468
2469 switch (hw->phy.type) {
2470 case ixgbe_phy_tw_tyco:
2471 case ixgbe_phy_tw_unknown:
2472 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2473 break;
2474 case ixgbe_phy_sfp_avago:
2475 case ixgbe_phy_sfp_ftl:
2476 case ixgbe_phy_sfp_intel:
2477 case ixgbe_phy_sfp_unknown:
2478 hw->phy.ops.read_i2c_eeprom(hw,
2479 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2480 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 2481 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 2482 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 2483 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
11afc1b1
PW		 2484 break;
2485 default:
11afc1b1
PW		 2486 break;
2487 }
2488
04193058 2489out:
11afc1b1
PW		 2490 return physical_layer;
2491}
2492
2493/**
2494 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2495 * @hw: pointer to hardware structure
2496 * @regval: register value to write to RXCTRL
2497 *
2498 * Enables the Rx DMA unit for 82599
2499 **/
7b25cdba 2500static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
11afc1b1
PW		 2501{
2502#define IXGBE_MAX_SECRX_POLL 30
2503 int i;
2504 int secrxreg;
2505
2506 /*
2507 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2508 * If traffic is incoming before we enable the Rx unit, it could hang
2509 * the Rx DMA unit. Therefore, make sure the security engine is
2510 * completely disabled prior to enabling the Rx unit.
2511 */
2512 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2513 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2514 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2515 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2516 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2517 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2518 break;
2519 else
2520 udelay(10);
2521 }
2522
2523 /* For informational purposes only */
2524 if (i >= IXGBE_MAX_SECRX_POLL)
2525 hw_dbg(hw, "Rx unit being enabled before security "
2526 "path fully disabled. Continuing with init.\n");
2527
2528 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2529 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2530 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2531 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2532 IXGBE_WRITE_FLUSH(hw);
2533
2534 return 0;
2535}
2536
04193058
PWJ		 2537/**
2538 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2539 * @hw: pointer to hardware structure
2540 * @device_caps: the EEPROM word with the extra device capabilities
2541 *
2542 * This function will read the EEPROM location for the device capabilities,
2543 * and return the word through device_caps.
2544 **/
7b25cdba 2545static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
04193058
PWJ		 2546{
2547 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2548
2549 return 0;
2550}
2551
0365e6e4
PW		 2552/**
2553 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2554 * @hw: pointer to hardware structure
2555 * @san_mac_offset: SAN MAC address offset
2556 *
2557 * This function will read the EEPROM location for the SAN MAC address
2558 * pointer, and returns the value at that location. This is used in both
2559 * get and set mac_addr routines.
2560 **/
7b25cdba
DS		 2561static s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
2562 u16 *san_mac_offset)
0365e6e4
PW		 2563{
2564 /*
2565 * First read the EEPROM pointer to see if the MAC addresses are
2566 * available.
2567 */
2568 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2569
2570 return 0;
2571}
2572
2573/**
2574 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2575 * @hw: pointer to hardware structure
2576 * @san_mac_addr: SAN MAC address
2577 *
2578 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2579 * per-port, so set_lan_id() must be called before reading the addresses.
2580 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2581 * upon for non-SFP connections, so we must call it here.
2582 **/
7b25cdba 2583static s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
0365e6e4
PW		 2584{
2585 u16 san_mac_data, san_mac_offset;
2586 u8 i;
2587
2588 /*
2589 * First read the EEPROM pointer to see if the MAC addresses are
2590 * available. If they're not, no point in calling set_lan_id() here.
2591 */
2592 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2593
2594 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2595 /*
2596 * No addresses available in this EEPROM. It's not an
2597 * error though, so just wipe the local address and return.
2598 */
2599 for (i = 0; i < 6; i++)
2600 san_mac_addr[i] = 0xFF;
2601
2602 goto san_mac_addr_out;
2603 }
2604
2605 /* make sure we know which port we need to program */
2606 hw->mac.ops.set_lan_id(hw);
2607 /* apply the port offset to the address offset */
2608 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2609 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2610 for (i = 0; i < 3; i++) {
2611 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2612 san_mac_addr[i * 2] = (u8)(san_mac_data);
2613 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2614 san_mac_offset++;
2615 }
2616
2617san_mac_addr_out:
2618 return 0;
2619}
2620
794caeb2
PWJ		 2621/**
2622 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2623 * @hw: pointer to hardware structure
2624 *
2625 * Verifies that installed the firmware version is 0.6 or higher
2626 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2627 *
2628 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2629 * if the FW version is not supported.
2630 **/
2631static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2632{
2633 s32 status = IXGBE_ERR_EEPROM_VERSION;
2634 u16 fw_offset, fw_ptp_cfg_offset;
2635 u16 fw_version = 0;
2636
2637 /* firmware check is only necessary for SFI devices */
2638 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2639 status = 0;
2640 goto fw_version_out;
2641 }
2642
2643 /* get the offset to the Firmware Module block */
2644 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2645
2646 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2647 goto fw_version_out;
2648
2649 /* get the offset to the Pass Through Patch Configuration block */
2650 hw->eeprom.ops.read(hw, (fw_offset +
2651 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2652 &fw_ptp_cfg_offset);
2653
2654 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2655 goto fw_version_out;
2656
2657 /* get the firmware version */
2658 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2659 IXGBE_FW_PATCH_VERSION_4),
2660 &fw_version);
2661
2662 if (fw_version > 0x5)
2663 status = 0;
2664
2665fw_version_out:
2666 return status;
2667}
2668
383ff34b
YZ		 2669/**
2670 * ixgbe_get_wwn_prefix_82599 - Get alternative WWNN/WWPN prefix from
2671 * the EEPROM
2672 * @hw: pointer to hardware structure
2673 * @wwnn_prefix: the alternative WWNN prefix
2674 * @wwpn_prefix: the alternative WWPN prefix
2675 *
2676 * This function will read the EEPROM from the alternative SAN MAC address
2677 * block to check the support for the alternative WWNN/WWPN prefix support.
2678 **/
2679static s32 ixgbe_get_wwn_prefix_82599(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2680 u16 *wwpn_prefix)
2681{
2682 u16 offset, caps;
2683 u16 alt_san_mac_blk_offset;
2684
2685 /* clear output first */
2686 *wwnn_prefix = 0xFFFF;
2687 *wwpn_prefix = 0xFFFF;
2688
2689 /* check if alternative SAN MAC is supported */
2690 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2691 &alt_san_mac_blk_offset);
2692
2693 if ((alt_san_mac_blk_offset == 0) ||
2694 (alt_san_mac_blk_offset == 0xFFFF))
2695 goto wwn_prefix_out;
2696
2697 /* check capability in alternative san mac address block */
2698 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2699 hw->eeprom.ops.read(hw, offset, &caps);
2700 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2701 goto wwn_prefix_out;
2702
2703 /* get the corresponding prefix for WWNN/WWPN */
2704 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2705 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2706
2707 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2708 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2709
2710wwn_prefix_out:
2711 return 0;
2712}
2713
11afc1b1
PW		 2714static struct ixgbe_mac_operations mac_ops_82599 = {
2715 .init_hw = &ixgbe_init_hw_generic,
2716 .reset_hw = &ixgbe_reset_hw_82599,
2717 .start_hw = &ixgbe_start_hw_82599,
2718 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2719 .get_media_type = &ixgbe_get_media_type_82599,
2720 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2721 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2722 .get_mac_addr = &ixgbe_get_mac_addr_generic,
0365e6e4 2723 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
04193058 2724 .get_device_caps = &ixgbe_get_device_caps_82599,
383ff34b 2725 .get_wwn_prefix = &ixgbe_get_wwn_prefix_82599,
11afc1b1
PW		 2726 .stop_adapter = &ixgbe_stop_adapter_generic,
2727 .get_bus_info = &ixgbe_get_bus_info_generic,
2728 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2729 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2730 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2731 .setup_link = &ixgbe_setup_mac_link_82599,
11afc1b1
PW		 2732 .check_link = &ixgbe_check_mac_link_82599,
2733 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2734 .led_on = &ixgbe_led_on_generic,
2735 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 2736 .blink_led_start = &ixgbe_blink_led_start_generic,
2737 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 2738 .set_rar = &ixgbe_set_rar_generic,
2739 .clear_rar = &ixgbe_clear_rar_generic,
2740 .set_vmdq = &ixgbe_set_vmdq_82599,
2741 .clear_vmdq = &ixgbe_clear_vmdq_82599,
2742 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2743 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2744 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2745 .enable_mc = &ixgbe_enable_mc_generic,
2746 .disable_mc = &ixgbe_disable_mc_generic,
2747 .clear_vfta = &ixgbe_clear_vfta_82599,
2748 .set_vfta = &ixgbe_set_vfta_82599,
620fa036 2749 .fc_enable = &ixgbe_fc_enable_generic,
11afc1b1
PW		 2750 .init_uta_tables = &ixgbe_init_uta_tables_82599,
2751 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2752};
2753
2754static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2755 .init_params = &ixgbe_init_eeprom_params_generic,
2756 .read = &ixgbe_read_eeprom_generic,
2757 .write = &ixgbe_write_eeprom_generic,
2758 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2759 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2760};
2761
2762static struct ixgbe_phy_operations phy_ops_82599 = {
2763 .identify = &ixgbe_identify_phy_82599,
2764 .identify_sfp = &ixgbe_identify_sfp_module_generic,
04f165ef 2765 .init = &ixgbe_init_phy_ops_82599,
11afc1b1
PW		 2766 .reset = &ixgbe_reset_phy_generic,
2767 .read_reg = &ixgbe_read_phy_reg_generic,
2768 .write_reg = &ixgbe_write_phy_reg_generic,
2769 .setup_link = &ixgbe_setup_phy_link_generic,
2770 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2771 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2772 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2773 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2774 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2775};
2776
2777struct ixgbe_info ixgbe_82599_info = {
2778 .mac = ixgbe_mac_82599EB,
2779 .get_invariants = &ixgbe_get_invariants_82599,
2780 .mac_ops = &mac_ops_82599,
2781 .eeprom_ops = &eeprom_ops_82599,
2782 .phy_ops = &phy_ops_82599,
096a58fd 2783 .mbx_ops = &mbx_ops_82599,
11afc1b1 2784};
Linux kernel - Deliverables
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