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e1000: Fix for e1000 kills IPMI on a tagged vlan.
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
34
35#define IXGBE_82599_MAX_TX_QUEUES 128
36#define IXGBE_82599_MAX_RX_QUEUES 128
37#define IXGBE_82599_RAR_ENTRIES 128
38#define IXGBE_82599_MC_TBL_SIZE 128
39#define IXGBE_82599_VFT_TBL_SIZE 128
40
7b25cdba
DS		 41static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
42static s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
11afc1b1
PW		 43 ixgbe_link_speed speed, bool autoneg,
44 bool autoneg_wait_to_complete);
7b25cdba
DS		 45static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
46static s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
48 bool autoneg,
49 bool autoneg_wait_to_complete);
11afc1b1
PW		 50static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
51 ixgbe_link_speed *speed,
52 bool *autoneg);
53static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
54static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
55 ixgbe_link_speed speed,
56 bool autoneg,
57 bool autoneg_wait_to_complete);
794caeb2 58static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
11afc1b1 59
7b25cdba 60static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 61{
62 struct ixgbe_mac_info *mac = &hw->mac;
63 if (hw->phy.multispeed_fiber) {
64 /* Set up dual speed SFP+ support */
65 mac->ops.setup_link =
66 &ixgbe_setup_mac_link_multispeed_fiber;
67 mac->ops.setup_link_speed =
68 &ixgbe_setup_mac_link_speed_multispeed_fiber;
69 } else {
70 mac->ops.setup_link =
71 &ixgbe_setup_mac_link_82599;
72 mac->ops.setup_link_speed =
73 &ixgbe_setup_mac_link_speed_82599;
74 }
75}
76
7b25cdba 77static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 78{
79 s32 ret_val = 0;
80 u16 list_offset, data_offset, data_value;
81
82 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
83 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 84
85 hw->phy.ops.reset = NULL;
86
11afc1b1
PW		 87 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
88 &data_offset);
89
90 if (ret_val != 0)
91 goto setup_sfp_out;
92
aa5aec88
PWJ		 93 /* PHY config will finish before releasing the semaphore */
94 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
95 if (ret_val != 0) {
96 ret_val = IXGBE_ERR_SWFW_SYNC;
97 goto setup_sfp_out;
98 }
99
11afc1b1
PW		 100 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
101 while (data_value != 0xffff) {
102 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
103 IXGBE_WRITE_FLUSH(hw);
104 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
105 }
1479ad4f
PWJ		 106 /* Now restart DSP by setting Restart_AN */
107 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
108 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
aa5aec88
PWJ		 109
110 /* Release the semaphore */
111 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
112 /* Delay obtaining semaphore again to allow FW access */
113 msleep(hw->eeprom.semaphore_delay);
11afc1b1
PW		 114 }
115
116setup_sfp_out:
117 return ret_val;
118}
119
120/**
121 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
122 * @hw: pointer to hardware structure
123 *
124 * Read PCIe configuration space, and get the MSI-X vector count from
125 * the capabilities table.
126 **/
7b25cdba 127static u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 128{
129 struct ixgbe_adapter *adapter = hw->back;
130 u16 msix_count;
131 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
132 &msix_count);
133 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
134
135 /* MSI-X count is zero-based in HW, so increment to give proper value */
136 msix_count++;
137
138 return msix_count;
139}
140
141static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
142{
143 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 144
04f165ef 145 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 146
04f165ef
PW		 147 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
148 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
149 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
150 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
151 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
152 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
11afc1b1 153
04f165ef
PW		 154 return 0;
155}
11afc1b1 156
04f165ef
PW		 157/**
158 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
159 * @hw: pointer to hardware structure
160 *
161 * Initialize any function pointers that were not able to be
162 * set during get_invariants because the PHY/SFP type was
163 * not known. Perform the SFP init if necessary.
164 *
165 **/
7b25cdba 166static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
04f165ef
PW		 167{
168 struct ixgbe_mac_info *mac = &hw->mac;
169 struct ixgbe_phy_info *phy = &hw->phy;
170 s32 ret_val = 0;
11afc1b1 171
04f165ef
PW		 172 /* Identify the PHY or SFP module */
173 ret_val = phy->ops.identify(hw);
174
175 /* Setup function pointers based on detected SFP module and speeds */
176 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 177
178 /* If copper media, overwrite with copper function pointers */
179 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
180 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
181 mac->ops.setup_link_speed =
04f165ef 182 &ixgbe_setup_copper_link_speed_82599;
11afc1b1
PW		 183 mac->ops.get_link_capabilities =
184 &ixgbe_get_copper_link_capabilities_82599;
185 }
186
04f165ef 187 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 188 switch (hw->phy.type) {
189 case ixgbe_phy_tn:
190 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
191 phy->ops.get_firmware_version =
04f165ef 192 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 193 break;
194 default:
195 break;
196 }
197
11afc1b1
PW		 198 return ret_val;
199}
200
201/**
202 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
203 * @hw: pointer to hardware structure
204 * @speed: pointer to link speed
205 * @negotiation: true when autoneg or autotry is enabled
206 *
207 * Determines the link capabilities by reading the AUTOC register.
208 **/
7b25cdba
DS		 209static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
210 ixgbe_link_speed *speed,
211 bool *negotiation)
11afc1b1
PW		 212{
213 s32 status = 0;
1eb99d5a 214 u32 autoc = 0;
11afc1b1 215
1eb99d5a
PW		 216 /*
217 * Determine link capabilities based on the stored value of AUTOC,
218 * which represents EEPROM defaults. If AUTOC value has not been
219 * stored, use the current register value.
220 */
221 if (hw->mac.orig_link_settings_stored)
222 autoc = hw->mac.orig_autoc;
223 else
224 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
225
226 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 227 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
228 *speed = IXGBE_LINK_SPEED_1GB_FULL;
229 *negotiation = false;
230 break;
231
232 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
233 *speed = IXGBE_LINK_SPEED_10GB_FULL;
234 *negotiation = false;
235 break;
236
237 case IXGBE_AUTOC_LMS_1G_AN:
238 *speed = IXGBE_LINK_SPEED_1GB_FULL;
239 *negotiation = true;
240 break;
241
242 case IXGBE_AUTOC_LMS_10G_SERIAL:
243 *speed = IXGBE_LINK_SPEED_10GB_FULL;
244 *negotiation = false;
245 break;
246
247 case IXGBE_AUTOC_LMS_KX4_KX_KR:
248 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
249 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 250 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 251 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 252 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 253 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 254 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 255 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
256 *negotiation = true;
257 break;
258
259 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
260 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 261 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 262 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 263 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 264 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 265 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 266 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
267 *negotiation = true;
268 break;
269
270 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
271 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
272 *negotiation = false;
273 break;
274
275 default:
276 status = IXGBE_ERR_LINK_SETUP;
277 goto out;
278 break;
279 }
280
281 if (hw->phy.multispeed_fiber) {
282 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
283 IXGBE_LINK_SPEED_1GB_FULL;
284 *negotiation = true;
285 }
286
287out:
288 return status;
289}
290
291/**
292 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
293 * @hw: pointer to hardware structure
294 * @speed: pointer to link speed
295 * @autoneg: boolean auto-negotiation value
296 *
297 * Determines the link capabilities by reading the AUTOC register.
298 **/
299static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
300 ixgbe_link_speed *speed,
301 bool *autoneg)
302{
303 s32 status = IXGBE_ERR_LINK_SETUP;
304 u16 speed_ability;
305
306 *speed = 0;
307 *autoneg = true;
308
6b73e10d 309 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
11afc1b1
PW		 310 &speed_ability);
311
312 if (status == 0) {
6b73e10d 313 if (speed_ability & MDIO_SPEED_10G)
11afc1b1 314 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
6b73e10d 315 if (speed_ability & MDIO_PMA_SPEED_1000)
11afc1b1
PW		 316 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
317 }
318
319 return status;
320}
321
322/**
323 * ixgbe_get_media_type_82599 - Get media type
324 * @hw: pointer to hardware structure
325 *
326 * Returns the media type (fiber, copper, backplane)
327 **/
7b25cdba 328static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 329{
330 enum ixgbe_media_type media_type;
331
332 /* Detect if there is a copper PHY attached. */
333 if (hw->phy.type == ixgbe_phy_cu_unknown ||
334 hw->phy.type == ixgbe_phy_tn) {
335 media_type = ixgbe_media_type_copper;
336 goto out;
337 }
338
339 switch (hw->device_id) {
11afc1b1 340 case IXGBE_DEV_ID_82599_KX4:
1fcf03e6 341 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 342 /* Default device ID is mezzanine card KX/KX4 */
343 media_type = ixgbe_media_type_backplane;
344 break;
345 case IXGBE_DEV_ID_82599_SFP:
346 media_type = ixgbe_media_type_fiber;
347 break;
348 default:
349 media_type = ixgbe_media_type_unknown;
350 break;
351 }
352out:
353 return media_type;
354}
355
356/**
357 * ixgbe_setup_mac_link_82599 - Setup MAC link settings
358 * @hw: pointer to hardware structure
359 *
360 * Configures link settings based on values in the ixgbe_hw struct.
361 * Restarts the link. Performs autonegotiation if needed.
362 **/
7b25cdba 363static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 364{
365 u32 autoc_reg;
366 u32 links_reg;
367 u32 i;
368 s32 status = 0;
369
370 /* Restart link */
371 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
372 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
373 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
374
375 /* Only poll for autoneg to complete if specified to do so */
376 if (hw->phy.autoneg_wait_to_complete) {
377 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
378 IXGBE_AUTOC_LMS_KX4_KX_KR ||
379 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
380 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
381 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
382 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
383 links_reg = 0; /* Just in case Autoneg time = 0 */
384 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
385 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
386 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
387 break;
388 msleep(100);
389 }
390 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
391 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
392 hw_dbg(hw, "Autoneg did not complete.\n");
393 }
394 }
395 }
396
11afc1b1
PW		 397 /* Add delay to filter out noises during initial link setup */
398 msleep(50);
399
400 return status;
401}
402
403/**
404 * ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
405 * @hw: pointer to hardware structure
406 *
407 * Configures link settings based on values in the ixgbe_hw struct.
408 * Restarts the link for multi-speed fiber at 1G speed, if link
409 * fails at 10G.
410 * Performs autonegotiation if needed.
411 **/
7b25cdba 412static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
11afc1b1
PW		 413{
414 s32 status = 0;
415 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
4df10466 416 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, link_speed,
11afc1b1
PW		 417 true, true);
418 return status;
419}
420
421/**
422 * ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
423 * @hw: pointer to hardware structure
424 * @speed: new link speed
425 * @autoneg: true if autonegotiation enabled
426 * @autoneg_wait_to_complete: true when waiting for completion is needed
427 *
428 * Set the link speed in the AUTOC register and restarts link.
429 **/
7b25cdba 430static s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
11afc1b1
PW		 431 ixgbe_link_speed speed,
432 bool autoneg,
433 bool autoneg_wait_to_complete)
434{
435 s32 status = 0;
436 ixgbe_link_speed phy_link_speed;
437 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
438 u32 speedcnt = 0;
439 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
440 bool link_up = false;
441 bool negotiation;
50ac58ba 442 int i;
11afc1b1
PW		 443
444 /* Mask off requested but non-supported speeds */
445 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
446 speed &= phy_link_speed;
447
74766013
MC		 448 /* Set autoneg_advertised value based on input link speed */
449 hw->phy.autoneg_advertised = 0;
450
451 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
452 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
453
454 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
455 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
456
50ac58ba
PWJ		 457 /*
458 * When the driver changes the link speeds that it can support,
459 * it sets autotry_restart to true to indicate that we need to
460 * initiate a new autotry session with the link partner. To do
461 * so, we set the speed then disable and re-enable the tx laser, to
462 * alert the link partner that it also needs to restart autotry on its
463 * end. This is consistent with true clause 37 autoneg, which also
464 * involves a loss of signal.
465 */
466
11afc1b1
PW		 467 /*
468 * Try each speed one by one, highest priority first. We do this in
469 * software because 10gb fiber doesn't support speed autonegotiation.
470 */
471 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
472 speedcnt++;
473 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
474
50ac58ba
PWJ		 475 /* If we already have link at this speed, just jump out */
476 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
477
478 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
479 goto out;
480
481 /* Set the module link speed */
11afc1b1
PW		 482 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
483 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
484
50ac58ba
PWJ		 485 /* Allow module to change analog characteristics (1G->10G) */
486 msleep(40);
11afc1b1 487
50ac58ba
PWJ		 488 status = ixgbe_setup_mac_link_speed_82599(hw,
489 IXGBE_LINK_SPEED_10GB_FULL,
490 autoneg,
491 autoneg_wait_to_complete);
492 if (status != 0)
11afc1b1 493 goto out;
50ac58ba
PWJ		 494
495 /* Flap the tx laser if it has not already been done */
496 if (hw->mac.autotry_restart) {
497 /* Disable tx laser; allow 100us to go dark per spec */
498 esdp_reg |= IXGBE_ESDP_SDP3;
499 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
500 udelay(100);
501
502 /* Enable tx laser; allow 2ms to light up per spec */
503 esdp_reg &= ~IXGBE_ESDP_SDP3;
504 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
505 msleep(2);
506
507 hw->mac.autotry_restart = false;
508 }
509
510 /* The controller may take up to 500ms at 10g to acquire link */
511 for (i = 0; i < 5; i++) {
512 /* Wait for the link partner to also set speed */
513 msleep(100);
514
515 /* If we have link, just jump out */
516 hw->mac.ops.check_link(hw, &phy_link_speed,
517 &link_up, false);
518 if (link_up)
519 goto out;
520 }
11afc1b1
PW		 521 }
522
523 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
524 speedcnt++;
525 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
526 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
527
50ac58ba
PWJ		 528 /* If we already have link at this speed, just jump out */
529 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
530
531 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
532 goto out;
533
534 /* Set the module link speed */
11afc1b1
PW		 535 esdp_reg &= ~IXGBE_ESDP_SDP5;
536 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
537 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
538
50ac58ba
PWJ		 539 /* Allow module to change analog characteristics (10G->1G) */
540 msleep(40);
11afc1b1 541
50ac58ba
PWJ		 542 status = ixgbe_setup_mac_link_speed_82599(hw,
543 IXGBE_LINK_SPEED_1GB_FULL,
544 autoneg,
545 autoneg_wait_to_complete);
546 if (status != 0)
547 goto out;
548
549 /* Flap the tx laser if it has not already been done */
550 if (hw->mac.autotry_restart) {
551 /* Disable tx laser; allow 100us to go dark per spec */
552 esdp_reg |= IXGBE_ESDP_SDP3;
553 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
554 udelay(100);
555
556 /* Enable tx laser; allow 2ms to light up per spec */
557 esdp_reg &= ~IXGBE_ESDP_SDP3;
558 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
559 msleep(2);
560
561 hw->mac.autotry_restart = false;
562 }
563
564 /* Wait for the link partner to also set speed */
565 msleep(100);
11afc1b1
PW		 566
567 /* If we have link, just jump out */
568 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
569 if (link_up)
570 goto out;
571 }
572
573 /*
574 * We didn't get link. Configure back to the highest speed we tried,
575 * (if there was more than one). We call ourselves back with just the
576 * single highest speed that the user requested.
577 */
578 if (speedcnt > 1)
579 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
580 highest_link_speed,
581 autoneg,
582 autoneg_wait_to_complete);
583
584out:
585 return status;
586}
587
588/**
589 * ixgbe_check_mac_link_82599 - Determine link and speed status
590 * @hw: pointer to hardware structure
591 * @speed: pointer to link speed
592 * @link_up: true when link is up
593 * @link_up_wait_to_complete: bool used to wait for link up or not
594 *
595 * Reads the links register to determine if link is up and the current speed
596 **/
7b25cdba
DS		 597static s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
598 ixgbe_link_speed *speed,
599 bool *link_up,
600 bool link_up_wait_to_complete)
11afc1b1
PW		 601{
602 u32 links_reg;
603 u32 i;
604
605 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
606 if (link_up_wait_to_complete) {
607 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
608 if (links_reg & IXGBE_LINKS_UP) {
609 *link_up = true;
610 break;
611 } else {
612 *link_up = false;
613 }
614 msleep(100);
615 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
616 }
617 } else {
618 if (links_reg & IXGBE_LINKS_UP)
619 *link_up = true;
620 else
621 *link_up = false;
622 }
623
624 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
625 IXGBE_LINKS_SPEED_10G_82599)
626 *speed = IXGBE_LINK_SPEED_10GB_FULL;
627 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
628 IXGBE_LINKS_SPEED_1G_82599)
629 *speed = IXGBE_LINK_SPEED_1GB_FULL;
630 else
631 *speed = IXGBE_LINK_SPEED_100_FULL;
632
620fa036
MC		 633 /* if link is down, zero out the current_mode */
634 if (*link_up == false) {
635 hw->fc.current_mode = ixgbe_fc_none;
636 hw->fc.fc_was_autonegged = false;
637 }
11afc1b1
PW		 638
639 return 0;
640}
641
642/**
643 * ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
644 * @hw: pointer to hardware structure
645 * @speed: new link speed
646 * @autoneg: true if autonegotiation enabled
647 * @autoneg_wait_to_complete: true when waiting for completion is needed
648 *
649 * Set the link speed in the AUTOC register and restarts link.
650 **/
7b25cdba
DS		 651static s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
652 ixgbe_link_speed speed,
653 bool autoneg,
654 bool autoneg_wait_to_complete)
11afc1b1
PW		 655{
656 s32 status = 0;
657 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
658 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
50ac58ba 659 u32 start_autoc = autoc;
1eb99d5a 660 u32 orig_autoc = 0;
11afc1b1
PW		 661 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
662 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
663 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
664 u32 links_reg;
665 u32 i;
666 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
667
668 /* Check to see if speed passed in is supported. */
669 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
670 speed &= link_capabilities;
671
50ac58ba
PWJ		 672 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
673 status = IXGBE_ERR_LINK_SETUP;
674 goto out;
675 }
676
1eb99d5a
PW		 677 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
678 if (hw->mac.orig_link_settings_stored)
679 orig_autoc = hw->mac.orig_autoc;
680 else
681 orig_autoc = autoc;
682
683
50ac58ba
PWJ		 684 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
685 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
686 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
11afc1b1
PW		 687 /* Set KX4/KX/KR support according to speed requested */
688 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
689 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 690 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 691 autoc |= IXGBE_AUTOC_KX4_SUPP;
1eb99d5a 692 if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1
PW		 693 autoc |= IXGBE_AUTOC_KR_SUPP;
694 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
695 autoc |= IXGBE_AUTOC_KX_SUPP;
696 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
697 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
698 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
699 /* Switch from 1G SFI to 10G SFI if requested */
700 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
701 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
702 autoc &= ~IXGBE_AUTOC_LMS_MASK;
703 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
704 }
705 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
706 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
707 /* Switch from 10G SFI to 1G SFI if requested */
708 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
709 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
710 autoc &= ~IXGBE_AUTOC_LMS_MASK;
711 if (autoneg)
712 autoc |= IXGBE_AUTOC_LMS_1G_AN;
713 else
714 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
715 }
716 }
717
50ac58ba 718 if (autoc != start_autoc) {
11afc1b1
PW		 719 /* Restart link */
720 autoc |= IXGBE_AUTOC_AN_RESTART;
721 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
722
723 /* Only poll for autoneg to complete if specified to do so */
724 if (autoneg_wait_to_complete) {
725 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
726 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
727 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
728 links_reg = 0; /*Just in case Autoneg time=0*/
729 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
730 links_reg =
731 IXGBE_READ_REG(hw, IXGBE_LINKS);
732 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
733 break;
734 msleep(100);
735 }
736 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
737 status =
738 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
739 hw_dbg(hw, "Autoneg did not "
740 "complete.\n");
741 }
742 }
743 }
744
11afc1b1
PW		 745 /* Add delay to filter out noises during initial link setup */
746 msleep(50);
747 }
748
50ac58ba 749out:
11afc1b1
PW		 750 return status;
751}
752
753/**
754 * ixgbe_setup_copper_link_82599 - Setup copper link settings
755 * @hw: pointer to hardware structure
756 *
757 * Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
758 **/
759static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
760{
761 s32 status;
762
763 /* Restart autonegotiation on PHY */
764 status = hw->phy.ops.setup_link(hw);
765
766 /* Set up MAC */
767 ixgbe_setup_mac_link_82599(hw);
768
769 return status;
770}
771
772/**
773 * ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
774 * @hw: pointer to hardware structure
775 * @speed: new link speed
776 * @autoneg: true if autonegotiation enabled
777 * @autoneg_wait_to_complete: true if waiting is needed to complete
778 *
779 * Restarts link on PHY and MAC based on settings passed in.
780 **/
781static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
782 ixgbe_link_speed speed,
783 bool autoneg,
784 bool autoneg_wait_to_complete)
785{
786 s32 status;
787
788 /* Setup the PHY according to input speed */
789 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
790 autoneg_wait_to_complete);
791 /* Set up MAC */
792 ixgbe_setup_mac_link_82599(hw);
793
794 return status;
795}
796
797/**
798 * ixgbe_reset_hw_82599 - Perform hardware reset
799 * @hw: pointer to hardware structure
800 *
801 * Resets the hardware by resetting the transmit and receive units, masks
802 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
803 * reset.
804 **/
7b25cdba 805static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 806{
807 s32 status = 0;
808 u32 ctrl, ctrl_ext;
809 u32 i;
810 u32 autoc;
811 u32 autoc2;
812
813 /* Call adapter stop to disable tx/rx and clear interrupts */
814 hw->mac.ops.stop_adapter(hw);
815
553b4497 816 /* PHY ops must be identified and initialized prior to reset */
04f165ef 817
553b4497
PW		 818 /* Init PHY and function pointers, perform SFP setup */
819 status = hw->phy.ops.init(hw);
04f165ef 820
553b4497
PW		 821 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
822 goto reset_hw_out;
04f165ef 823
553b4497
PW		 824 /* Setup SFP module if there is one present. */
825 if (hw->phy.sfp_setup_needed) {
826 status = hw->mac.ops.setup_sfp(hw);
827 hw->phy.sfp_setup_needed = false;
04f165ef 828 }
11afc1b1 829
553b4497
PW		 830 /* Reset PHY */
831 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
832 hw->phy.ops.reset(hw);
833
11afc1b1
PW		 834 /*
835 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
836 * access and verify no pending requests before reset
837 */
04f165ef
PW		 838 status = ixgbe_disable_pcie_master(hw);
839 if (status != 0) {
11afc1b1
PW		 840 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
841 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
842 }
843
844 /*
845 * Issue global reset to the MAC. This needs to be a SW reset.
846 * If link reset is used, it might reset the MAC when mng is using it
847 */
848 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
849 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
850 IXGBE_WRITE_FLUSH(hw);
851
852 /* Poll for reset bit to self-clear indicating reset is complete */
853 for (i = 0; i < 10; i++) {
854 udelay(1);
855 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
856 if (!(ctrl & IXGBE_CTRL_RST))
857 break;
858 }
859 if (ctrl & IXGBE_CTRL_RST) {
860 status = IXGBE_ERR_RESET_FAILED;
861 hw_dbg(hw, "Reset polling failed to complete.\n");
862 }
863 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
864 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
865 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
866 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
867
868 msleep(50);
869
870
871
872 /*
873 * Store the original AUTOC/AUTOC2 values if they have not been
874 * stored off yet. Otherwise restore the stored original
875 * values since the reset operation sets back to defaults.
876 */
877 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
878 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
879 if (hw->mac.orig_link_settings_stored == false) {
880 hw->mac.orig_autoc = autoc;
881 hw->mac.orig_autoc2 = autoc2;
882 hw->mac.orig_link_settings_stored = true;
4df10466 883 } else {
11afc1b1
PW		 884 if (autoc != hw->mac.orig_autoc)
885 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
886 IXGBE_AUTOC_AN_RESTART));
887
888 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
889 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
890 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
891 autoc2 |= (hw->mac.orig_autoc2 &
892 IXGBE_AUTOC2_UPPER_MASK);
893 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
894 }
895 }
896
aca6bee7
WJP		 897 /*
898 * Store MAC address from RAR0, clear receive address registers, and
899 * clear the multicast table. Also reset num_rar_entries to 128,
900 * since we modify this value when programming the SAN MAC address.
901 */
902 hw->mac.num_rar_entries = 128;
903 hw->mac.ops.init_rx_addrs(hw);
904
11afc1b1
PW		 905 /* Store the permanent mac address */
906 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
907
0365e6e4
PW		 908 /* Store the permanent SAN mac address */
909 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
910
aca6bee7
WJP		 911 /* Add the SAN MAC address to the RAR only if it's a valid address */
912 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
913 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
914 hw->mac.san_addr, 0, IXGBE_RAH_AV);
915
916 /* Reserve the last RAR for the SAN MAC address */
917 hw->mac.num_rar_entries--;
918 }
919
04f165ef 920reset_hw_out:
11afc1b1
PW		 921 return status;
922}
923
924/**
925 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
926 * @hw: pointer to hardware struct
927 * @rar: receive address register index to disassociate
928 * @vmdq: VMDq pool index to remove from the rar
929 **/
7b25cdba 930static s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
11afc1b1
PW		 931{
932 u32 mpsar_lo, mpsar_hi;
933 u32 rar_entries = hw->mac.num_rar_entries;
934
935 if (rar < rar_entries) {
936 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
937 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
938
939 if (!mpsar_lo && !mpsar_hi)
940 goto done;
941
942 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
943 if (mpsar_lo) {
944 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
945 mpsar_lo = 0;
946 }
947 if (mpsar_hi) {
948 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
949 mpsar_hi = 0;
950 }
951 } else if (vmdq < 32) {
952 mpsar_lo &= ~(1 << vmdq);
953 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
954 } else {
955 mpsar_hi &= ~(1 << (vmdq - 32));
956 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
957 }
958
959 /* was that the last pool using this rar? */
960 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
961 hw->mac.ops.clear_rar(hw, rar);
962 } else {
963 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
964 }
965
966done:
967 return 0;
968}
969
970/**
971 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
972 * @hw: pointer to hardware struct
973 * @rar: receive address register index to associate with a VMDq index
974 * @vmdq: VMDq pool index
975 **/
7b25cdba 976static s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
11afc1b1
PW		 977{
978 u32 mpsar;
979 u32 rar_entries = hw->mac.num_rar_entries;
980
981 if (rar < rar_entries) {
982 if (vmdq < 32) {
983 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
984 mpsar |= 1 << vmdq;
985 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
986 } else {
987 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
988 mpsar |= 1 << (vmdq - 32);
989 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
990 }
991 } else {
992 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
993 }
994 return 0;
995}
996
997/**
998 * ixgbe_set_vfta_82599 - Set VLAN filter table
999 * @hw: pointer to hardware structure
1000 * @vlan: VLAN id to write to VLAN filter
1001 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1002 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1003 *
1004 * Turn on/off specified VLAN in the VLAN filter table.
1005 **/
7b25cdba
DS		 1006static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1007 bool vlan_on)
11afc1b1
PW		 1008{
1009 u32 regindex;
1010 u32 bitindex;
1011 u32 bits;
1012 u32 first_empty_slot;
1013
1014 if (vlan > 4095)
1015 return IXGBE_ERR_PARAM;
1016
1017 /*
1018 * this is a 2 part operation - first the VFTA, then the
1019 * VLVF and VLVFB if vind is set
1020 */
1021
1022 /* Part 1
1023 * The VFTA is a bitstring made up of 128 32-bit registers
1024 * that enable the particular VLAN id, much like the MTA:
1025 * bits[11-5]: which register
1026 * bits[4-0]: which bit in the register
1027 */
1028 regindex = (vlan >> 5) & 0x7F;
1029 bitindex = vlan & 0x1F;
1030 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1031 if (vlan_on)
1032 bits |= (1 << bitindex);
1033 else
1034 bits &= ~(1 << bitindex);
1035 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1036
1037
1038 /* Part 2
1039 * If the vind is set
1040 * Either vlan_on
1041 * make sure the vlan is in VLVF
1042 * set the vind bit in the matching VLVFB
1043 * Or !vlan_on
1044 * clear the pool bit and possibly the vind
1045 */
1046 if (vind) {
1047 /* find the vlanid or the first empty slot */
1048 first_empty_slot = 0;
1049
1050 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
1051 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
1052 if (!bits && !first_empty_slot)
1053 first_empty_slot = regindex;
1054 else if ((bits & 0x0FFF) == vlan)
1055 break;
1056 }
1057
1058 if (regindex >= IXGBE_VLVF_ENTRIES) {
1059 if (first_empty_slot)
1060 regindex = first_empty_slot;
1061 else {
1062 hw_dbg(hw, "No space in VLVF.\n");
1063 goto out;
1064 }
1065 }
1066
1067 if (vlan_on) {
1068 /* set the pool bit */
1069 if (vind < 32) {
1070 bits = IXGBE_READ_REG(hw,
1071 IXGBE_VLVFB(regindex * 2));
1072 bits |= (1 << vind);
1073 IXGBE_WRITE_REG(hw,
1074 IXGBE_VLVFB(regindex * 2), bits);
1075 } else {
1076 bits = IXGBE_READ_REG(hw,
1077 IXGBE_VLVFB((regindex * 2) + 1));
1078 bits |= (1 << vind);
1079 IXGBE_WRITE_REG(hw,
1080 IXGBE_VLVFB((regindex * 2) + 1), bits);
1081 }
1082 } else {
1083 /* clear the pool bit */
1084 if (vind < 32) {
1085 bits = IXGBE_READ_REG(hw,
1086 IXGBE_VLVFB(regindex * 2));
1087 bits &= ~(1 << vind);
1088 IXGBE_WRITE_REG(hw,
1089 IXGBE_VLVFB(regindex * 2), bits);
1090 bits |= IXGBE_READ_REG(hw,
1091 IXGBE_VLVFB((regindex * 2) + 1));
1092 } else {
1093 bits = IXGBE_READ_REG(hw,
1094 IXGBE_VLVFB((regindex * 2) + 1));
1095 bits &= ~(1 << vind);
1096 IXGBE_WRITE_REG(hw,
1097 IXGBE_VLVFB((regindex * 2) + 1), bits);
1098 bits |= IXGBE_READ_REG(hw,
1099 IXGBE_VLVFB(regindex * 2));
1100 }
1101 }
1102
1103 if (bits)
1104 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1105 (IXGBE_VLVF_VIEN | vlan));
1106 else
1107 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1108 }
1109
1110out:
1111 return 0;
1112}
1113
1114/**
1115 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1116 * @hw: pointer to hardware structure
1117 *
1118 * Clears the VLAN filer table, and the VMDq index associated with the filter
1119 **/
7b25cdba 1120static s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1121{
1122 u32 offset;
1123
1124 for (offset = 0; offset < hw->mac.vft_size; offset++)
1125 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1126
1127 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1128 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1129 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1130 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1131 }
1132
1133 return 0;
1134}
1135
11afc1b1
PW		 1136/**
1137 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1138 * @hw: pointer to hardware structure
1139 **/
7b25cdba 1140static s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1141{
1142 int i;
1143 hw_dbg(hw, " Clearing UTA\n");
1144
1145 for (i = 0; i < 128; i++)
1146 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1147
1148 return 0;
1149}
1150
ffff4772
PWJ		 1151/**
1152 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1153 * @hw: pointer to hardware structure
1154 **/
1155s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1156{
1157 int i;
1158 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1159 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1160
1161 /*
1162 * Before starting reinitialization process,
1163 * FDIRCMD.CMD must be zero.
1164 */
1165 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1166 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1167 IXGBE_FDIRCMD_CMD_MASK))
1168 break;
1169 udelay(10);
1170 }
1171 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1172 hw_dbg(hw ,"Flow Director previous command isn't complete, "
1173 "aborting table re-initialization. \n");
1174 return IXGBE_ERR_FDIR_REINIT_FAILED;
1175 }
1176
1177 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1178 IXGBE_WRITE_FLUSH(hw);
1179 /*
1180 * 82599 adapters flow director init flow cannot be restarted,
1181 * Workaround 82599 silicon errata by performing the following steps
1182 * before re-writing the FDIRCTRL control register with the same value.
1183 * - write 1 to bit 8 of FDIRCMD register &
1184 * - write 0 to bit 8 of FDIRCMD register
1185 */
1186 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1187 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1188 IXGBE_FDIRCMD_CLEARHT));
1189 IXGBE_WRITE_FLUSH(hw);
1190 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1191 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1192 ~IXGBE_FDIRCMD_CLEARHT));
1193 IXGBE_WRITE_FLUSH(hw);
1194 /*
1195 * Clear FDIR Hash register to clear any leftover hashes
1196 * waiting to be programmed.
1197 */
1198 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1199 IXGBE_WRITE_FLUSH(hw);
1200
1201 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1202 IXGBE_WRITE_FLUSH(hw);
1203
1204 /* Poll init-done after we write FDIRCTRL register */
1205 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1206 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1207 IXGBE_FDIRCTRL_INIT_DONE)
1208 break;
1209 udelay(10);
1210 }
1211 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1212 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1213 return IXGBE_ERR_FDIR_REINIT_FAILED;
1214 }
1215
1216 /* Clear FDIR statistics registers (read to clear) */
1217 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1218 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1219 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1220 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1221 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1222
1223 return 0;
1224}
1225
1226/**
1227 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1228 * @hw: pointer to hardware structure
1229 * @pballoc: which mode to allocate filters with
1230 **/
1231s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1232{
1233 u32 fdirctrl = 0;
1234 u32 pbsize;
1235 int i;
1236
1237 /*
1238 * Before enabling Flow Director, the Rx Packet Buffer size
1239 * must be reduced. The new value is the current size minus
1240 * flow director memory usage size.
1241 */
1242 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1243 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1244 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1245
1246 /*
1247 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1248 * intialized to zero for non DCB mode otherwise actual total RX PB
1249 * would be bigger than programmed and filter space would run into
1250 * the PB 0 region.
1251 */
1252 for (i = 1; i < 8; i++)
1253 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1254
1255 /* Send interrupt when 64 filters are left */
1256 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1257
1258 /* Set the maximum length per hash bucket to 0xA filters */
1259 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1260
1261 switch (pballoc) {
1262 case IXGBE_FDIR_PBALLOC_64K:
1263 /* 8k - 1 signature filters */
1264 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1265 break;
1266 case IXGBE_FDIR_PBALLOC_128K:
1267 /* 16k - 1 signature filters */
1268 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1269 break;
1270 case IXGBE_FDIR_PBALLOC_256K:
1271 /* 32k - 1 signature filters */
1272 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1273 break;
1274 default:
1275 /* bad value */
1276 return IXGBE_ERR_CONFIG;
1277 };
1278
1279 /* Move the flexible bytes to use the ethertype - shift 6 words */
1280 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1281
1282 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1283
1284 /* Prime the keys for hashing */
1285 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1286 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1287 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1288 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1289
1290 /*
1291 * Poll init-done after we write the register. Estimated times:
1292 * 10G: PBALLOC = 11b, timing is 60us
1293 * 1G: PBALLOC = 11b, timing is 600us
1294 * 100M: PBALLOC = 11b, timing is 6ms
1295 *
1296 * Multiple these timings by 4 if under full Rx load
1297 *
1298 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1299 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1300 * this might not finish in our poll time, but we can live with that
1301 * for now.
1302 */
1303 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1304 IXGBE_WRITE_FLUSH(hw);
1305 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1306 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1307 IXGBE_FDIRCTRL_INIT_DONE)
1308 break;
1309 msleep(1);
1310 }
1311 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1312 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1313
1314 return 0;
1315}
1316
1317/**
1318 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1319 * @hw: pointer to hardware structure
1320 * @pballoc: which mode to allocate filters with
1321 **/
1322s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1323{
1324 u32 fdirctrl = 0;
1325 u32 pbsize;
1326 int i;
1327
1328 /*
1329 * Before enabling Flow Director, the Rx Packet Buffer size
1330 * must be reduced. The new value is the current size minus
1331 * flow director memory usage size.
1332 */
1333 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1334 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1335 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1336
1337 /*
1338 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1339 * intialized to zero for non DCB mode otherwise actual total RX PB
1340 * would be bigger than programmed and filter space would run into
1341 * the PB 0 region.
1342 */
1343 for (i = 1; i < 8; i++)
1344 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1345
1346 /* Send interrupt when 64 filters are left */
1347 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1348
1349 switch (pballoc) {
1350 case IXGBE_FDIR_PBALLOC_64K:
1351 /* 2k - 1 perfect filters */
1352 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1353 break;
1354 case IXGBE_FDIR_PBALLOC_128K:
1355 /* 4k - 1 perfect filters */
1356 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1357 break;
1358 case IXGBE_FDIR_PBALLOC_256K:
1359 /* 8k - 1 perfect filters */
1360 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1361 break;
1362 default:
1363 /* bad value */
1364 return IXGBE_ERR_CONFIG;
1365 };
1366
1367 /* Turn perfect match filtering on */
1368 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1369 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1370
1371 /* Move the flexible bytes to use the ethertype - shift 6 words */
1372 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1373
1374 /* Prime the keys for hashing */
1375 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1376 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1377 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1378 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1379
1380 /*
1381 * Poll init-done after we write the register. Estimated times:
1382 * 10G: PBALLOC = 11b, timing is 60us
1383 * 1G: PBALLOC = 11b, timing is 600us
1384 * 100M: PBALLOC = 11b, timing is 6ms
1385 *
1386 * Multiple these timings by 4 if under full Rx load
1387 *
1388 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1389 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1390 * this might not finish in our poll time, but we can live with that
1391 * for now.
1392 */
1393
1394 /* Set the maximum length per hash bucket to 0xA filters */
1395 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1396
1397 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1398 IXGBE_WRITE_FLUSH(hw);
1399 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1400 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1401 IXGBE_FDIRCTRL_INIT_DONE)
1402 break;
1403 msleep(1);
1404 }
1405 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1406 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1407
1408 return 0;
1409}
1410
1411
1412/**
1413 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1414 * @stream: input bitstream to compute the hash on
1415 * @key: 32-bit hash key
1416 **/
7b25cdba
DS		 1417static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1418 u32 key)
ffff4772
PWJ		 1419{
1420 /*
1421 * The algorithm is as follows:
1422 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1423 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1424 * and A[n] x B[n] is bitwise AND between same length strings
1425 *
1426 * K[n] is 16 bits, defined as:
1427 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1428 * for n modulo 32 < 15, K[n] =
1429 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1430 *
1431 * S[n] is 16 bits, defined as:
1432 * for n >= 15, S[n] = S[n:n - 15]
1433 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1434 *
1435 * To simplify for programming, the algorithm is implemented
1436 * in software this way:
1437 *
1438 * Key[31:0], Stream[335:0]
1439 *
1440 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1441 * int_key[350:0] = tmp_key[351:1]
1442 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1443 *
1444 * hash[15:0] = 0;
1445 * for (i = 0; i < 351; i++) {
1446 * if (int_key[i])
1447 * hash ^= int_stream[(i + 15):i];
1448 * }
1449 */
1450
1451 union {
1452 u64 fill[6];
1453 u32 key[11];
1454 u8 key_stream[44];
1455 } tmp_key;
1456
1457 u8 *stream = (u8 *)atr_input;
1458 u8 int_key[44]; /* upper-most bit unused */
1459 u8 hash_str[46]; /* upper-most 2 bits unused */
1460 u16 hash_result = 0;
1461 int i, j, k, h;
1462
1463 /*
1464 * Initialize the fill member to prevent warnings
1465 * on some compilers
1466 */
1467 tmp_key.fill[0] = 0;
1468
1469 /* First load the temporary key stream */
1470 for (i = 0; i < 6; i++) {
1471 u64 fillkey = ((u64)key << 32) | key;
1472 tmp_key.fill[i] = fillkey;
1473 }
1474
1475 /*
1476 * Set the interim key for the hashing. Bit 352 is unused, so we must
1477 * shift and compensate when building the key.
1478 */
1479
1480 int_key[0] = tmp_key.key_stream[0] >> 1;
1481 for (i = 1, j = 0; i < 44; i++) {
1482 unsigned int this_key = tmp_key.key_stream[j] << 7;
1483 j++;
1484 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1485 }
1486
1487 /*
1488 * Set the interim bit string for the hashing. Bits 368 and 367 are
1489 * unused, so shift and compensate when building the string.
1490 */
1491 hash_str[0] = (stream[40] & 0x7f) >> 1;
1492 for (i = 1, j = 40; i < 46; i++) {
1493 unsigned int this_str = stream[j] << 7;
1494 j++;
1495 if (j > 41)
1496 j = 0;
1497 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1498 }
1499
1500 /*
1501 * Now compute the hash. i is the index into hash_str, j is into our
1502 * key stream, k is counting the number of bits, and h interates within
1503 * each byte.
1504 */
1505 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1506 for (h = 0; h < 8 && k < 351; h++, k++) {
1507 if (int_key[j] & (1 << h)) {
1508 /*
1509 * Key bit is set, XOR in the current 16-bit
1510 * string. Example of processing:
1511 * h = 0,
1512 * tmp = (hash_str[i - 2] & 0 << 16) |
1513 * (hash_str[i - 1] & 0xff << 8) |
1514 * (hash_str[i] & 0xff >> 0)
1515 * So tmp = hash_str[15 + k:k], since the
1516 * i + 2 clause rolls off the 16-bit value
1517 * h = 7,
1518 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1519 * (hash_str[i - 1] & 0xff << 1) |
1520 * (hash_str[i] & 0x80 >> 7)
1521 */
1522 int tmp = (hash_str[i] >> h);
1523 tmp |= (hash_str[i - 1] << (8 - h));
1524 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1525 << (16 - h);
1526 hash_result ^= (u16)tmp;
1527 }
1528 }
1529 }
1530
1531 return hash_result;
1532}
1533
1534/**
1535 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1536 * @input: input stream to modify
1537 * @vlan: the VLAN id to load
1538 **/
1539s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1540{
1541 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1542 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1543
1544 return 0;
1545}
1546
1547/**
1548 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1549 * @input: input stream to modify
1550 * @src_addr: the IP address to load
1551 **/
1552s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1553{
1554 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1555 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1556 (src_addr >> 16) & 0xff;
1557 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1558 (src_addr >> 8) & 0xff;
1559 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1560
1561 return 0;
1562}
1563
1564/**
1565 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1566 * @input: input stream to modify
1567 * @dst_addr: the IP address to load
1568 **/
1569s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1570{
1571 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1572 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1573 (dst_addr >> 16) & 0xff;
1574 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1575 (dst_addr >> 8) & 0xff;
1576 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1577
1578 return 0;
1579}
1580
1581/**
1582 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1583 * @input: input stream to modify
1584 * @src_addr_1: the first 4 bytes of the IP address to load
1585 * @src_addr_2: the second 4 bytes of the IP address to load
1586 * @src_addr_3: the third 4 bytes of the IP address to load
1587 * @src_addr_4: the fourth 4 bytes of the IP address to load
1588 **/
1589s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1590 u32 src_addr_1, u32 src_addr_2,
1591 u32 src_addr_3, u32 src_addr_4)
ffff4772
PWJ		 1592{
1593 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1594 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1595 (src_addr_4 >> 8) & 0xff;
1596 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1597 (src_addr_4 >> 16) & 0xff;
1598 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1599
1600 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1601 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1602 (src_addr_3 >> 8) & 0xff;
1603 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1604 (src_addr_3 >> 16) & 0xff;
1605 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1606
1607 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1608 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1609 (src_addr_2 >> 8) & 0xff;
1610 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1611 (src_addr_2 >> 16) & 0xff;
1612 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1613
1614 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1615 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1616 (src_addr_1 >> 8) & 0xff;
1617 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1618 (src_addr_1 >> 16) & 0xff;
1619 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1620
1621 return 0;
1622}
1623
1624/**
1625 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1626 * @input: input stream to modify
1627 * @dst_addr_1: the first 4 bytes of the IP address to load
1628 * @dst_addr_2: the second 4 bytes of the IP address to load
1629 * @dst_addr_3: the third 4 bytes of the IP address to load
1630 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1631 **/
1632s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1633 u32 dst_addr_1, u32 dst_addr_2,
1634 u32 dst_addr_3, u32 dst_addr_4)
ffff4772
PWJ		 1635{
1636 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1637 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1638 (dst_addr_4 >> 8) & 0xff;
1639 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1640 (dst_addr_4 >> 16) & 0xff;
1641 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1642
1643 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1644 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1645 (dst_addr_3 >> 8) & 0xff;
1646 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1647 (dst_addr_3 >> 16) & 0xff;
1648 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1649
1650 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1651 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1652 (dst_addr_2 >> 8) & 0xff;
1653 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1654 (dst_addr_2 >> 16) & 0xff;
1655 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1656
1657 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1658 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1659 (dst_addr_1 >> 8) & 0xff;
1660 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1661 (dst_addr_1 >> 16) & 0xff;
1662 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1663
1664 return 0;
1665}
1666
1667/**
1668 * ixgbe_atr_set_src_port_82599 - Sets the source port
1669 * @input: input stream to modify
1670 * @src_port: the source port to load
1671 **/
1672s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1673{
1674 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1675 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1676
1677 return 0;
1678}
1679
1680/**
1681 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1682 * @input: input stream to modify
1683 * @dst_port: the destination port to load
1684 **/
1685s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1686{
1687 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1688 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1689
1690 return 0;
1691}
1692
1693/**
1694 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1695 * @input: input stream to modify
1696 * @flex_bytes: the flexible bytes to load
1697 **/
1698s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1699{
1700 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1701 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1702
1703 return 0;
1704}
1705
1706/**
1707 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1708 * @input: input stream to modify
1709 * @vm_pool: the Virtual Machine pool to load
1710 **/
7b25cdba
DS		 1711s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
1712 u8 vm_pool)
ffff4772
PWJ		 1713{
1714 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1715
1716 return 0;
1717}
1718
1719/**
1720 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1721 * @input: input stream to modify
1722 * @l4type: the layer 4 type value to load
1723 **/
1724s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1725{
1726 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1727
1728 return 0;
1729}
1730
1731/**
1732 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1733 * @input: input stream to search
1734 * @vlan: the VLAN id to load
1735 **/
7b25cdba
DS		 1736static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input,
1737 u16 *vlan)
ffff4772
PWJ		 1738{
1739 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1740 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1741
1742 return 0;
1743}
1744
1745/**
1746 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1747 * @input: input stream to search
1748 * @src_addr: the IP address to load
1749 **/
7b25cdba
DS		 1750static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1751 u32 *src_addr)
ffff4772
PWJ		 1752{
1753 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1754 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1755 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1756 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1757
1758 return 0;
1759}
1760
1761/**
1762 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1763 * @input: input stream to search
1764 * @dst_addr: the IP address to load
1765 **/
7b25cdba
DS		 1766static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1767 u32 *dst_addr)
ffff4772
PWJ		 1768{
1769 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1770 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1771 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1772 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1773
1774 return 0;
1775}
1776
1777/**
1778 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1779 * @input: input stream to search
1780 * @src_addr_1: the first 4 bytes of the IP address to load
1781 * @src_addr_2: the second 4 bytes of the IP address to load
1782 * @src_addr_3: the third 4 bytes of the IP address to load
1783 * @src_addr_4: the fourth 4 bytes of the IP address to load
1784 **/
7b25cdba
DS		 1785static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1786 u32 *src_addr_1, u32 *src_addr_2,
1787 u32 *src_addr_3, u32 *src_addr_4)
ffff4772
PWJ		 1788{
1789 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1790 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1791 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1792 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1793
1794 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1795 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1796 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1797 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1798
1799 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1800 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1801 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1802 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1803
1804 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1805 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1806 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1807 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1808
1809 return 0;
1810}
1811
1812/**
1813 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1814 * @input: input stream to search
1815 * @dst_addr_1: the first 4 bytes of the IP address to load
1816 * @dst_addr_2: the second 4 bytes of the IP address to load
1817 * @dst_addr_3: the third 4 bytes of the IP address to load
1818 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1819 **/
1820s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1821 u32 *dst_addr_1, u32 *dst_addr_2,
1822 u32 *dst_addr_3, u32 *dst_addr_4)
ffff4772
PWJ		 1823{
1824 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1825 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1826 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1827 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1828
1829 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1830 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1831 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1832 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1833
1834 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1835 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1836 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1837 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1838
1839 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1840 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1841 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1842 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1843
1844 return 0;
1845}
1846
1847/**
1848 * ixgbe_atr_get_src_port_82599 - Gets the source port
1849 * @input: input stream to modify
1850 * @src_port: the source port to load
1851 *
1852 * Even though the input is given in big-endian, the FDIRPORT registers
1853 * expect the ports to be programmed in little-endian. Hence the need to swap
1854 * endianness when retrieving the data. This can be confusing since the
1855 * internal hash engine expects it to be big-endian.
1856 **/
7b25cdba
DS		 1857static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1858 u16 *src_port)
ffff4772
PWJ		 1859{
1860 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1861 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1862
1863 return 0;
1864}
1865
1866/**
1867 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1868 * @input: input stream to modify
1869 * @dst_port: the destination port to load
1870 *
1871 * Even though the input is given in big-endian, the FDIRPORT registers
1872 * expect the ports to be programmed in little-endian. Hence the need to swap
1873 * endianness when retrieving the data. This can be confusing since the
1874 * internal hash engine expects it to be big-endian.
1875 **/
7b25cdba
DS		 1876static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1877 u16 *dst_port)
ffff4772
PWJ		 1878{
1879 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1880 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1881
1882 return 0;
1883}
1884
1885/**
1886 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1887 * @input: input stream to modify
1888 * @flex_bytes: the flexible bytes to load
1889 **/
7b25cdba
DS		 1890static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1891 u16 *flex_byte)
ffff4772
PWJ		 1892{
1893 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1894 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1895
1896 return 0;
1897}
1898
1899/**
1900 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
1901 * @input: input stream to modify
1902 * @vm_pool: the Virtual Machine pool to load
1903 **/
7b25cdba
DS		 1904s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
1905 u8 *vm_pool)
ffff4772
PWJ		 1906{
1907 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
1908
1909 return 0;
1910}
1911
1912/**
1913 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1914 * @input: input stream to modify
1915 * @l4type: the layer 4 type value to load
1916 **/
7b25cdba
DS		 1917static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
1918 u8 *l4type)
ffff4772
PWJ		 1919{
1920 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
1921
1922 return 0;
1923}
1924
1925/**
1926 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1927 * @hw: pointer to hardware structure
1928 * @stream: input bitstream
1929 * @queue: queue index to direct traffic to
1930 **/
1931s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1932 struct ixgbe_atr_input *input,
1933 u8 queue)
1934{
1935 u64 fdirhashcmd;
1936 u64 fdircmd;
1937 u32 fdirhash;
1938 u16 bucket_hash, sig_hash;
1939 u8 l4type;
1940
1941 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1942 IXGBE_ATR_BUCKET_HASH_KEY);
1943
1944 /* bucket_hash is only 15 bits */
1945 bucket_hash &= IXGBE_ATR_HASH_MASK;
1946
1947 sig_hash = ixgbe_atr_compute_hash_82599(input,
1948 IXGBE_ATR_SIGNATURE_HASH_KEY);
1949
1950 /* Get the l4type in order to program FDIRCMD properly */
1951 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1952 ixgbe_atr_get_l4type_82599(input, &l4type);
1953
1954 /*
1955 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1956 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1957 */
1958 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1959
1960 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1961 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
1962
1963 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1964 case IXGBE_ATR_L4TYPE_TCP:
1965 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1966 break;
1967 case IXGBE_ATR_L4TYPE_UDP:
1968 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1969 break;
1970 case IXGBE_ATR_L4TYPE_SCTP:
1971 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1972 break;
1973 default:
1974 hw_dbg(hw, "Error on l4type input\n");
1975 return IXGBE_ERR_CONFIG;
1976 }
1977
1978 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
1979 fdircmd |= IXGBE_FDIRCMD_IPV6;
1980
1981 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
1982 fdirhashcmd = ((fdircmd << 32) | fdirhash);
1983
1984 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1985
1986 return 0;
1987}
1988
1989/**
1990 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1991 * @hw: pointer to hardware structure
1992 * @input: input bitstream
1993 * @queue: queue index to direct traffic to
1994 *
1995 * Note that the caller to this function must lock before calling, since the
1996 * hardware writes must be protected from one another.
1997 **/
1998s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
7b25cdba
DS		 1999 struct ixgbe_atr_input *input,
2000 u16 soft_id,
2001 u8 queue)
ffff4772
PWJ		 2002{
2003 u32 fdircmd = 0;
2004 u32 fdirhash;
2005 u32 src_ipv4, dst_ipv4;
2006 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
2007 u16 src_port, dst_port, vlan_id, flex_bytes;
2008 u16 bucket_hash;
2009 u8 l4type;
2010
2011 /* Get our input values */
2012 ixgbe_atr_get_l4type_82599(input, &l4type);
2013
2014 /*
2015 * Check l4type formatting, and bail out before we touch the hardware
2016 * if there's a configuration issue
2017 */
2018 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2019 case IXGBE_ATR_L4TYPE_TCP:
2020 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
2021 break;
2022 case IXGBE_ATR_L4TYPE_UDP:
2023 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
2024 break;
2025 case IXGBE_ATR_L4TYPE_SCTP:
2026 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
2027 break;
2028 default:
2029 hw_dbg(hw, "Error on l4type input\n");
2030 return IXGBE_ERR_CONFIG;
2031 }
2032
2033 bucket_hash = ixgbe_atr_compute_hash_82599(input,
2034 IXGBE_ATR_BUCKET_HASH_KEY);
2035
2036 /* bucket_hash is only 15 bits */
2037 bucket_hash &= IXGBE_ATR_HASH_MASK;
2038
2039 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
2040 ixgbe_atr_get_src_port_82599(input, &src_port);
2041 ixgbe_atr_get_dst_port_82599(input, &dst_port);
2042 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
2043
2044 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2045
2046 /* Now figure out if we're IPv4 or IPv6 */
2047 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
2048 /* IPv6 */
2049 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
2050 &src_ipv6_3, &src_ipv6_4);
2051
2052 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
2053 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
2054 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
2055 /* The last 4 bytes is the same register as IPv4 */
2056 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
2057
2058 fdircmd |= IXGBE_FDIRCMD_IPV6;
2059 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
2060 } else {
2061 /* IPv4 */
2062 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
2063 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
2064
2065 }
2066
2067 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
2068 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
2069
2070 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
2071 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
2072 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
2073 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
2074
2075 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
2076 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
2077 fdircmd |= IXGBE_FDIRCMD_LAST;
2078 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
2079 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
2080
2081 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2082 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
2083
2084 return 0;
2085}
11afc1b1
PW		 2086/**
2087 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2088 * @hw: pointer to hardware structure
2089 * @reg: analog register to read
2090 * @val: read value
2091 *
2092 * Performs read operation to Omer analog register specified.
2093 **/
7b25cdba 2094static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
11afc1b1
PW		 2095{
2096 u32 core_ctl;
2097
2098 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2099 (reg << 8));
2100 IXGBE_WRITE_FLUSH(hw);
2101 udelay(10);
2102 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2103 *val = (u8)core_ctl;
2104
2105 return 0;
2106}
2107
2108/**
2109 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2110 * @hw: pointer to hardware structure
2111 * @reg: atlas register to write
2112 * @val: value to write
2113 *
2114 * Performs write operation to Omer analog register specified.
2115 **/
7b25cdba 2116static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
11afc1b1
PW		 2117{
2118 u32 core_ctl;
2119
2120 core_ctl = (reg << 8) | val;
2121 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2122 IXGBE_WRITE_FLUSH(hw);
2123 udelay(10);
2124
2125 return 0;
2126}
2127
2128/**
2129 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2130 * @hw: pointer to hardware structure
2131 *
2132 * Starts the hardware using the generic start_hw function.
2133 * Then performs device-specific:
2134 * Clears the rate limiter registers.
2135 **/
7b25cdba 2136static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2137{
2138 u32 q_num;
794caeb2 2139 s32 ret_val;
11afc1b1 2140
794caeb2 2141 ret_val = ixgbe_start_hw_generic(hw);
11afc1b1
PW		 2142
2143 /* Clear the rate limiters */
2144 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2145 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2146 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2147 }
2148 IXGBE_WRITE_FLUSH(hw);
2149
50ac58ba
PWJ		 2150 /* We need to run link autotry after the driver loads */
2151 hw->mac.autotry_restart = true;
2152
794caeb2
PWJ		 2153 if (ret_val == 0)
2154 ret_val = ixgbe_verify_fw_version_82599(hw);
2155
2156 return ret_val;
11afc1b1
PW		 2157}
2158
2159/**
2160 * ixgbe_identify_phy_82599 - Get physical layer module
2161 * @hw: pointer to hardware structure
2162 *
2163 * Determines the physical layer module found on the current adapter.
2164 **/
7b25cdba 2165static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2166{
2167 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2168 status = ixgbe_identify_phy_generic(hw);
2169 if (status != 0)
2170 status = ixgbe_identify_sfp_module_generic(hw);
2171 return status;
2172}
2173
2174/**
2175 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2176 * @hw: pointer to hardware structure
2177 *
2178 * Determines physical layer capabilities of the current configuration.
2179 **/
7b25cdba 2180static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2181{
2182 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 2183 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2184 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2185 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2186 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2187 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2188 u16 ext_ability = 0;
1339b9e9 2189 u8 comp_codes_10g = 0;
11afc1b1 2190
04193058
PWJ		 2191 hw->phy.ops.identify(hw);
2192
2193 if (hw->phy.type == ixgbe_phy_tn ||
2194 hw->phy.type == ixgbe_phy_cu_unknown) {
6b73e10d
BH		 2195 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2196 &ext_ability);
2197 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 2198 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 2199 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 2200 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 2201 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 2202 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2203 goto out;
2204 }
2205
2206 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2207 case IXGBE_AUTOC_LMS_1G_AN:
2208 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2209 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2210 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2211 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2212 goto out;
2213 } else
2214 /* SFI mode so read SFP module */
2215 goto sfp_check;
11afc1b1 2216 break;
04193058
PWJ		 2217 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2218 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2219 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2220 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2221 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 2222 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2223 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 2224 goto out;
2225 break;
2226 case IXGBE_AUTOC_LMS_10G_SERIAL:
2227 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2228 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2229 goto out;
2230 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2231 goto sfp_check;
2232 break;
2233 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2234 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2235 if (autoc & IXGBE_AUTOC_KX_SUPP)
2236 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2237 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2238 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2239 if (autoc & IXGBE_AUTOC_KR_SUPP)
2240 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2241 goto out;
2242 break;
2243 default:
2244 goto out;
2245 break;
2246 }
11afc1b1 2247
04193058
PWJ		 2248sfp_check:
2249 /* SFP check must be done last since DA modules are sometimes used to
2250 * test KR mode - we need to id KR mode correctly before SFP module.
2251 * Call identify_sfp because the pluggable module may have changed */
2252 hw->phy.ops.identify_sfp(hw);
2253 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2254 goto out;
2255
2256 switch (hw->phy.type) {
2257 case ixgbe_phy_tw_tyco:
2258 case ixgbe_phy_tw_unknown:
2259 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2260 break;
2261 case ixgbe_phy_sfp_avago:
2262 case ixgbe_phy_sfp_ftl:
2263 case ixgbe_phy_sfp_intel:
2264 case ixgbe_phy_sfp_unknown:
2265 hw->phy.ops.read_i2c_eeprom(hw,
2266 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2267 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 2268 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 2269 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 2270 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
11afc1b1
PW		 2271 break;
2272 default:
11afc1b1
PW		 2273 break;
2274 }
2275
04193058 2276out:
11afc1b1
PW		 2277 return physical_layer;
2278}
2279
2280/**
2281 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2282 * @hw: pointer to hardware structure
2283 * @regval: register value to write to RXCTRL
2284 *
2285 * Enables the Rx DMA unit for 82599
2286 **/
7b25cdba 2287static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
11afc1b1
PW		 2288{
2289#define IXGBE_MAX_SECRX_POLL 30
2290 int i;
2291 int secrxreg;
2292
2293 /*
2294 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2295 * If traffic is incoming before we enable the Rx unit, it could hang
2296 * the Rx DMA unit. Therefore, make sure the security engine is
2297 * completely disabled prior to enabling the Rx unit.
2298 */
2299 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2300 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2301 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2302 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2303 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2304 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2305 break;
2306 else
2307 udelay(10);
2308 }
2309
2310 /* For informational purposes only */
2311 if (i >= IXGBE_MAX_SECRX_POLL)
2312 hw_dbg(hw, "Rx unit being enabled before security "
2313 "path fully disabled. Continuing with init.\n");
2314
2315 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2316 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2317 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2318 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2319 IXGBE_WRITE_FLUSH(hw);
2320
2321 return 0;
2322}
2323
04193058
PWJ		 2324/**
2325 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2326 * @hw: pointer to hardware structure
2327 * @device_caps: the EEPROM word with the extra device capabilities
2328 *
2329 * This function will read the EEPROM location for the device capabilities,
2330 * and return the word through device_caps.
2331 **/
7b25cdba 2332static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
04193058
PWJ		 2333{
2334 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2335
2336 return 0;
2337}
2338
0365e6e4
PW		 2339/**
2340 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2341 * @hw: pointer to hardware structure
2342 * @san_mac_offset: SAN MAC address offset
2343 *
2344 * This function will read the EEPROM location for the SAN MAC address
2345 * pointer, and returns the value at that location. This is used in both
2346 * get and set mac_addr routines.
2347 **/
7b25cdba
DS		 2348static s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
2349 u16 *san_mac_offset)
0365e6e4
PW		 2350{
2351 /*
2352 * First read the EEPROM pointer to see if the MAC addresses are
2353 * available.
2354 */
2355 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2356
2357 return 0;
2358}
2359
2360/**
2361 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2362 * @hw: pointer to hardware structure
2363 * @san_mac_addr: SAN MAC address
2364 *
2365 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2366 * per-port, so set_lan_id() must be called before reading the addresses.
2367 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2368 * upon for non-SFP connections, so we must call it here.
2369 **/
7b25cdba 2370static s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
0365e6e4
PW		 2371{
2372 u16 san_mac_data, san_mac_offset;
2373 u8 i;
2374
2375 /*
2376 * First read the EEPROM pointer to see if the MAC addresses are
2377 * available. If they're not, no point in calling set_lan_id() here.
2378 */
2379 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2380
2381 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2382 /*
2383 * No addresses available in this EEPROM. It's not an
2384 * error though, so just wipe the local address and return.
2385 */
2386 for (i = 0; i < 6; i++)
2387 san_mac_addr[i] = 0xFF;
2388
2389 goto san_mac_addr_out;
2390 }
2391
2392 /* make sure we know which port we need to program */
2393 hw->mac.ops.set_lan_id(hw);
2394 /* apply the port offset to the address offset */
2395 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2396 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2397 for (i = 0; i < 3; i++) {
2398 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2399 san_mac_addr[i * 2] = (u8)(san_mac_data);
2400 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2401 san_mac_offset++;
2402 }
2403
2404san_mac_addr_out:
2405 return 0;
2406}
2407
794caeb2
PWJ		 2408/**
2409 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2410 * @hw: pointer to hardware structure
2411 *
2412 * Verifies that installed the firmware version is 0.6 or higher
2413 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2414 *
2415 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2416 * if the FW version is not supported.
2417 **/
2418static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2419{
2420 s32 status = IXGBE_ERR_EEPROM_VERSION;
2421 u16 fw_offset, fw_ptp_cfg_offset;
2422 u16 fw_version = 0;
2423
2424 /* firmware check is only necessary for SFI devices */
2425 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2426 status = 0;
2427 goto fw_version_out;
2428 }
2429
2430 /* get the offset to the Firmware Module block */
2431 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2432
2433 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2434 goto fw_version_out;
2435
2436 /* get the offset to the Pass Through Patch Configuration block */
2437 hw->eeprom.ops.read(hw, (fw_offset +
2438 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2439 &fw_ptp_cfg_offset);
2440
2441 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2442 goto fw_version_out;
2443
2444 /* get the firmware version */
2445 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2446 IXGBE_FW_PATCH_VERSION_4),
2447 &fw_version);
2448
2449 if (fw_version > 0x5)
2450 status = 0;
2451
2452fw_version_out:
2453 return status;
2454}
2455
11afc1b1
PW		 2456static struct ixgbe_mac_operations mac_ops_82599 = {
2457 .init_hw = &ixgbe_init_hw_generic,
2458 .reset_hw = &ixgbe_reset_hw_82599,
2459 .start_hw = &ixgbe_start_hw_82599,
2460 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2461 .get_media_type = &ixgbe_get_media_type_82599,
2462 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2463 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2464 .get_mac_addr = &ixgbe_get_mac_addr_generic,
0365e6e4 2465 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
04193058 2466 .get_device_caps = &ixgbe_get_device_caps_82599,
11afc1b1
PW		 2467 .stop_adapter = &ixgbe_stop_adapter_generic,
2468 .get_bus_info = &ixgbe_get_bus_info_generic,
2469 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2470 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2471 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2472 .setup_link = &ixgbe_setup_mac_link_82599,
2473 .setup_link_speed = &ixgbe_setup_mac_link_speed_82599,
2474 .check_link = &ixgbe_check_mac_link_82599,
2475 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2476 .led_on = &ixgbe_led_on_generic,
2477 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 2478 .blink_led_start = &ixgbe_blink_led_start_generic,
2479 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 2480 .set_rar = &ixgbe_set_rar_generic,
2481 .clear_rar = &ixgbe_clear_rar_generic,
2482 .set_vmdq = &ixgbe_set_vmdq_82599,
2483 .clear_vmdq = &ixgbe_clear_vmdq_82599,
2484 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2485 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2486 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2487 .enable_mc = &ixgbe_enable_mc_generic,
2488 .disable_mc = &ixgbe_disable_mc_generic,
2489 .clear_vfta = &ixgbe_clear_vfta_82599,
2490 .set_vfta = &ixgbe_set_vfta_82599,
620fa036 2491 .fc_enable = &ixgbe_fc_enable_generic,
11afc1b1
PW		 2492 .init_uta_tables = &ixgbe_init_uta_tables_82599,
2493 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2494};
2495
2496static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2497 .init_params = &ixgbe_init_eeprom_params_generic,
2498 .read = &ixgbe_read_eeprom_generic,
2499 .write = &ixgbe_write_eeprom_generic,
2500 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2501 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2502};
2503
2504static struct ixgbe_phy_operations phy_ops_82599 = {
2505 .identify = &ixgbe_identify_phy_82599,
2506 .identify_sfp = &ixgbe_identify_sfp_module_generic,
04f165ef 2507 .init = &ixgbe_init_phy_ops_82599,
11afc1b1
PW		 2508 .reset = &ixgbe_reset_phy_generic,
2509 .read_reg = &ixgbe_read_phy_reg_generic,
2510 .write_reg = &ixgbe_write_phy_reg_generic,
2511 .setup_link = &ixgbe_setup_phy_link_generic,
2512 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2513 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2514 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2515 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2516 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2517};
2518
2519struct ixgbe_info ixgbe_82599_info = {
2520 .mac = ixgbe_mac_82599EB,
2521 .get_invariants = &ixgbe_get_invariants_82599,
2522 .mac_ops = &mac_ops_82599,
2523 .eeprom_ops = &eeprom_ops_82599,
2524 .phy_ops = &phy_ops_82599,
2525};
Linux kernel - Deliverables
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