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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland...
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
ccffad25 31#include <linux/netdevice.h>
9a799d71 32
11afc1b1 33#include "ixgbe.h"
9a799d71
AK		 34#include "ixgbe_common.h"
35#include "ixgbe_phy.h"
36
c44ade9e 37static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 38static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 40static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
43 u16 count);
44static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 48static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
49
c44ade9e
JB		 50static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
51static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
9a799d71 52static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
c44ade9e 53static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
7b25cdba 54static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
9a799d71
AK		 55
56/**
c44ade9e 57 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 58 * @hw: pointer to hardware structure
59 *
60 * Starts the hardware by filling the bus info structure and media type, clears
61 * all on chip counters, initializes receive address registers, multicast
62 * table, VLAN filter table, calls routine to set up link and flow control
63 * settings, and leaves transmit and receive units disabled and uninitialized
64 **/
c44ade9e 65s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71
AK		 66{
67 u32 ctrl_ext;
68
69 /* Set the media type */
70 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
71
72 /* Identify the PHY */
c44ade9e 73 hw->phy.ops.identify(hw);
9a799d71 74
9a799d71 75 /* Clear the VLAN filter table */
c44ade9e 76 hw->mac.ops.clear_vfta(hw);
9a799d71 77
9a799d71 78 /* Clear statistics registers */
c44ade9e 79 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 80
81 /* Set No Snoop Disable */
82 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
83 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
84 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 85 IXGBE_WRITE_FLUSH(hw);
9a799d71 86
620fa036
MC		 87 /* Setup flow control */
88 ixgbe_setup_fc(hw, 0);
89
9a799d71
AK		 90 /* Clear adapter stopped flag */
91 hw->adapter_stopped = false;
92
93 return 0;
94}
95
96/**
c44ade9e 97 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 98 * @hw: pointer to hardware structure
99 *
c44ade9e 100 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 101 * structure and media type, clears all on chip counters, initializes receive
102 * address registers, multicast table, VLAN filter table, calls routine to set
103 * up link and flow control settings, and leaves transmit and receive units
104 * disabled and uninitialized
105 **/
c44ade9e 106s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 107{
794caeb2
PWJ		 108 s32 status;
109
9a799d71 110 /* Reset the hardware */
794caeb2 111 status = hw->mac.ops.reset_hw(hw);
9a799d71 112
794caeb2
PWJ		 113 if (status == 0) {
114 /* Start the HW */
115 status = hw->mac.ops.start_hw(hw);
116 }
9a799d71 117
794caeb2 118 return status;
9a799d71
AK		 119}
120
121/**
c44ade9e 122 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 123 * @hw: pointer to hardware structure
124 *
125 * Clears all hardware statistics counters by reading them from the hardware
126 * Statistics counters are clear on read.
127 **/
c44ade9e 128s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 129{
130 u16 i = 0;
131
132 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
133 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
134 IXGBE_READ_REG(hw, IXGBE_ERRBC);
135 IXGBE_READ_REG(hw, IXGBE_MSPDC);
136 for (i = 0; i < 8; i++)
137 IXGBE_READ_REG(hw, IXGBE_MPC(i));
138
139 IXGBE_READ_REG(hw, IXGBE_MLFC);
140 IXGBE_READ_REG(hw, IXGBE_MRFC);
141 IXGBE_READ_REG(hw, IXGBE_RLEC);
142 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
143 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
144 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
145 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
146
147 for (i = 0; i < 8; i++) {
148 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
149 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
150 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
151 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
152 }
153
154 IXGBE_READ_REG(hw, IXGBE_PRC64);
155 IXGBE_READ_REG(hw, IXGBE_PRC127);
156 IXGBE_READ_REG(hw, IXGBE_PRC255);
157 IXGBE_READ_REG(hw, IXGBE_PRC511);
158 IXGBE_READ_REG(hw, IXGBE_PRC1023);
159 IXGBE_READ_REG(hw, IXGBE_PRC1522);
160 IXGBE_READ_REG(hw, IXGBE_GPRC);
161 IXGBE_READ_REG(hw, IXGBE_BPRC);
162 IXGBE_READ_REG(hw, IXGBE_MPRC);
163 IXGBE_READ_REG(hw, IXGBE_GPTC);
164 IXGBE_READ_REG(hw, IXGBE_GORCL);
165 IXGBE_READ_REG(hw, IXGBE_GORCH);
166 IXGBE_READ_REG(hw, IXGBE_GOTCL);
167 IXGBE_READ_REG(hw, IXGBE_GOTCH);
168 for (i = 0; i < 8; i++)
169 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
170 IXGBE_READ_REG(hw, IXGBE_RUC);
171 IXGBE_READ_REG(hw, IXGBE_RFC);
172 IXGBE_READ_REG(hw, IXGBE_ROC);
173 IXGBE_READ_REG(hw, IXGBE_RJC);
174 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
175 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
176 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
177 IXGBE_READ_REG(hw, IXGBE_TORL);
178 IXGBE_READ_REG(hw, IXGBE_TORH);
179 IXGBE_READ_REG(hw, IXGBE_TPR);
180 IXGBE_READ_REG(hw, IXGBE_TPT);
181 IXGBE_READ_REG(hw, IXGBE_PTC64);
182 IXGBE_READ_REG(hw, IXGBE_PTC127);
183 IXGBE_READ_REG(hw, IXGBE_PTC255);
184 IXGBE_READ_REG(hw, IXGBE_PTC511);
185 IXGBE_READ_REG(hw, IXGBE_PTC1023);
186 IXGBE_READ_REG(hw, IXGBE_PTC1522);
187 IXGBE_READ_REG(hw, IXGBE_MPTC);
188 IXGBE_READ_REG(hw, IXGBE_BPTC);
189 for (i = 0; i < 16; i++) {
190 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
191 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
192 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
193 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
194 }
195
196 return 0;
197}
198
199/**
c44ade9e
JB		 200 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
201 * @hw: pointer to hardware structure
202 * @pba_num: stores the part number from the EEPROM
203 *
204 * Reads the part number from the EEPROM.
205 **/
206s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
207{
208 s32 ret_val;
209 u16 data;
210
211 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
212 if (ret_val) {
213 hw_dbg(hw, "NVM Read Error\n");
214 return ret_val;
215 }
216 *pba_num = (u32)(data << 16);
217
218 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
219 if (ret_val) {
220 hw_dbg(hw, "NVM Read Error\n");
221 return ret_val;
222 }
223 *pba_num |= data;
224
225 return 0;
226}
227
228/**
229 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 230 * @hw: pointer to hardware structure
231 * @mac_addr: Adapter MAC address
232 *
233 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
234 * A reset of the adapter must be performed prior to calling this function
235 * in order for the MAC address to have been loaded from the EEPROM into RAR0
236 **/
c44ade9e 237s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 238{
239 u32 rar_high;
240 u32 rar_low;
241 u16 i;
242
243 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
244 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
245
246 for (i = 0; i < 4; i++)
247 mac_addr[i] = (u8)(rar_low >> (i*8));
248
249 for (i = 0; i < 2; i++)
250 mac_addr[i+4] = (u8)(rar_high >> (i*8));
251
252 return 0;
253}
254
11afc1b1
PW		 255/**
256 * ixgbe_get_bus_info_generic - Generic set PCI bus info
257 * @hw: pointer to hardware structure
258 *
259 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
260 **/
261s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
262{
263 struct ixgbe_adapter *adapter = hw->back;
264 struct ixgbe_mac_info *mac = &hw->mac;
265 u16 link_status;
266
267 hw->bus.type = ixgbe_bus_type_pci_express;
268
269 /* Get the negotiated link width and speed from PCI config space */
270 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
271 &link_status);
272
273 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
274 case IXGBE_PCI_LINK_WIDTH_1:
275 hw->bus.width = ixgbe_bus_width_pcie_x1;
276 break;
277 case IXGBE_PCI_LINK_WIDTH_2:
278 hw->bus.width = ixgbe_bus_width_pcie_x2;
279 break;
280 case IXGBE_PCI_LINK_WIDTH_4:
281 hw->bus.width = ixgbe_bus_width_pcie_x4;
282 break;
283 case IXGBE_PCI_LINK_WIDTH_8:
284 hw->bus.width = ixgbe_bus_width_pcie_x8;
285 break;
286 default:
287 hw->bus.width = ixgbe_bus_width_unknown;
288 break;
289 }
290
291 switch (link_status & IXGBE_PCI_LINK_SPEED) {
292 case IXGBE_PCI_LINK_SPEED_2500:
293 hw->bus.speed = ixgbe_bus_speed_2500;
294 break;
295 case IXGBE_PCI_LINK_SPEED_5000:
296 hw->bus.speed = ixgbe_bus_speed_5000;
297 break;
298 default:
299 hw->bus.speed = ixgbe_bus_speed_unknown;
300 break;
301 }
302
303 mac->ops.set_lan_id(hw);
304
305 return 0;
306}
307
308/**
309 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
310 * @hw: pointer to the HW structure
311 *
312 * Determines the LAN function id by reading memory-mapped registers
313 * and swaps the port value if requested.
314 **/
315void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
316{
317 struct ixgbe_bus_info *bus = &hw->bus;
318 u32 reg;
319
320 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
321 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
322 bus->lan_id = bus->func;
323
324 /* check for a port swap */
325 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
326 if (reg & IXGBE_FACTPS_LFS)
327 bus->func ^= 0x1;
328}
329
9a799d71 330/**
c44ade9e 331 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 332 * @hw: pointer to hardware structure
333 *
334 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
335 * disables transmit and receive units. The adapter_stopped flag is used by
336 * the shared code and drivers to determine if the adapter is in a stopped
337 * state and should not touch the hardware.
338 **/
c44ade9e 339s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71
AK		 340{
341 u32 number_of_queues;
342 u32 reg_val;
343 u16 i;
344
345 /*
346 * Set the adapter_stopped flag so other driver functions stop touching
347 * the hardware
348 */
349 hw->adapter_stopped = true;
350
351 /* Disable the receive unit */
352 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
353 reg_val &= ~(IXGBE_RXCTRL_RXEN);
354 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
c44ade9e 355 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 356 msleep(2);
357
358 /* Clear interrupt mask to stop from interrupts being generated */
359 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
360
361 /* Clear any pending interrupts */
362 IXGBE_READ_REG(hw, IXGBE_EICR);
363
364 /* Disable the transmit unit. Each queue must be disabled. */
c44ade9e 365 number_of_queues = hw->mac.max_tx_queues;
9a799d71
AK		 366 for (i = 0; i < number_of_queues; i++) {
367 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
368 if (reg_val & IXGBE_TXDCTL_ENABLE) {
369 reg_val &= ~IXGBE_TXDCTL_ENABLE;
370 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
371 }
372 }
373
c44ade9e
JB		 374 /*
375 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
376 * access and verify no pending requests
377 */
378 if (ixgbe_disable_pcie_master(hw) != 0)
379 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
380
9a799d71
AK		 381 return 0;
382}
383
384/**
c44ade9e 385 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 386 * @hw: pointer to hardware structure
387 * @index: led number to turn on
388 **/
c44ade9e 389s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 390{
391 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
392
393 /* To turn on the LED, set mode to ON. */
394 led_reg &= ~IXGBE_LED_MODE_MASK(index);
395 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
396 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 397 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 398
399 return 0;
400}
401
402/**
c44ade9e 403 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 404 * @hw: pointer to hardware structure
405 * @index: led number to turn off
406 **/
c44ade9e 407s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 408{
409 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
410
411 /* To turn off the LED, set mode to OFF. */
412 led_reg &= ~IXGBE_LED_MODE_MASK(index);
413 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
414 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 415 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 416
417 return 0;
418}
419
9a799d71 420/**
c44ade9e 421 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 422 * @hw: pointer to hardware structure
423 *
424 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
425 * ixgbe_hw struct in order to set up EEPROM access.
426 **/
c44ade9e 427s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 428{
429 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
430 u32 eec;
431 u16 eeprom_size;
432
433 if (eeprom->type == ixgbe_eeprom_uninitialized) {
434 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 435 /* Set default semaphore delay to 10ms which is a well
436 * tested value */
437 eeprom->semaphore_delay = 10;
9a799d71
AK		 438
439 /*
440 * Check for EEPROM present first.
441 * If not present leave as none
442 */
443 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
444 if (eec & IXGBE_EEC_PRES) {
445 eeprom->type = ixgbe_eeprom_spi;
446
447 /*
448 * SPI EEPROM is assumed here. This code would need to
449 * change if a future EEPROM is not SPI.
450 */
451 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
452 IXGBE_EEC_SIZE_SHIFT);
453 eeprom->word_size = 1 << (eeprom_size +
454 IXGBE_EEPROM_WORD_SIZE_SHIFT);
455 }
456
457 if (eec & IXGBE_EEC_ADDR_SIZE)
458 eeprom->address_bits = 16;
459 else
460 eeprom->address_bits = 8;
461 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
462 "%d\n", eeprom->type, eeprom->word_size,
463 eeprom->address_bits);
464 }
465
466 return 0;
467}
468
11afc1b1
PW		 469/**
470 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
471 * @hw: pointer to hardware structure
472 * @offset: offset within the EEPROM to be written to
473 * @data: 16 bit word to be written to the EEPROM
474 *
475 * If ixgbe_eeprom_update_checksum is not called after this function, the
476 * EEPROM will most likely contain an invalid checksum.
477 **/
478s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
479{
480 s32 status;
481 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
482
483 hw->eeprom.ops.init_params(hw);
484
485 if (offset >= hw->eeprom.word_size) {
486 status = IXGBE_ERR_EEPROM;
487 goto out;
488 }
489
490 /* Prepare the EEPROM for writing */
491 status = ixgbe_acquire_eeprom(hw);
492
493 if (status == 0) {
494 if (ixgbe_ready_eeprom(hw) != 0) {
495 ixgbe_release_eeprom(hw);
496 status = IXGBE_ERR_EEPROM;
497 }
498 }
499
500 if (status == 0) {
501 ixgbe_standby_eeprom(hw);
502
503 /* Send the WRITE ENABLE command (8 bit opcode ) */
504 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
505 IXGBE_EEPROM_OPCODE_BITS);
506
507 ixgbe_standby_eeprom(hw);
508
509 /*
510 * Some SPI eeproms use the 8th address bit embedded in the
511 * opcode
512 */
513 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
514 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
515
516 /* Send the Write command (8-bit opcode + addr) */
517 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
518 IXGBE_EEPROM_OPCODE_BITS);
519 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
520 hw->eeprom.address_bits);
521
522 /* Send the data */
523 data = (data >> 8) | (data << 8);
524 ixgbe_shift_out_eeprom_bits(hw, data, 16);
525 ixgbe_standby_eeprom(hw);
526
527 msleep(hw->eeprom.semaphore_delay);
528 /* Done with writing - release the EEPROM */
529 ixgbe_release_eeprom(hw);
530 }
531
532out:
533 return status;
534}
535
9a799d71 536/**
c44ade9e
JB		 537 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
538 * @hw: pointer to hardware structure
539 * @offset: offset within the EEPROM to be read
540 * @data: read 16 bit value from EEPROM
541 *
542 * Reads 16 bit value from EEPROM through bit-bang method
543 **/
544s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
545 u16 *data)
546{
547 s32 status;
548 u16 word_in;
549 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
550
551 hw->eeprom.ops.init_params(hw);
552
553 if (offset >= hw->eeprom.word_size) {
554 status = IXGBE_ERR_EEPROM;
555 goto out;
556 }
557
558 /* Prepare the EEPROM for reading */
559 status = ixgbe_acquire_eeprom(hw);
560
561 if (status == 0) {
562 if (ixgbe_ready_eeprom(hw) != 0) {
563 ixgbe_release_eeprom(hw);
564 status = IXGBE_ERR_EEPROM;
565 }
566 }
567
568 if (status == 0) {
569 ixgbe_standby_eeprom(hw);
570
571 /*
572 * Some SPI eeproms use the 8th address bit embedded in the
573 * opcode
574 */
575 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
576 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
577
578 /* Send the READ command (opcode + addr) */
579 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
580 IXGBE_EEPROM_OPCODE_BITS);
581 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
582 hw->eeprom.address_bits);
583
584 /* Read the data. */
585 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
586 *data = (word_in >> 8) | (word_in << 8);
587
588 /* End this read operation */
589 ixgbe_release_eeprom(hw);
590 }
591
592out:
593 return status;
594}
595
596/**
21ce849b 597 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
9a799d71
AK		 598 * @hw: pointer to hardware structure
599 * @offset: offset of word in the EEPROM to read
600 * @data: word read from the EEPROM
601 *
602 * Reads a 16 bit word from the EEPROM using the EERD register.
603 **/
21ce849b 604s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
9a799d71
AK		 605{
606 u32 eerd;
607 s32 status;
608
c44ade9e
JB		 609 hw->eeprom.ops.init_params(hw);
610
611 if (offset >= hw->eeprom.word_size) {
612 status = IXGBE_ERR_EEPROM;
613 goto out;
614 }
615
21ce849b
MC		 616 eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) +
617 IXGBE_EEPROM_RW_REG_START;
9a799d71
AK		 618
619 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
21ce849b 620 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
9a799d71
AK		 621
622 if (status == 0)
623 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
21ce849b 624 IXGBE_EEPROM_RW_REG_DATA);
9a799d71
AK		 625 else
626 hw_dbg(hw, "Eeprom read timed out\n");
627
c44ade9e 628out:
9a799d71
AK		 629 return status;
630}
631
632/**
21ce849b 633 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
9a799d71 634 * @hw: pointer to hardware structure
21ce849b 635 * @ee_reg: EEPROM flag for polling
9a799d71 636 *
21ce849b
MC		 637 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
638 * read or write is done respectively.
9a799d71 639 **/
21ce849b 640s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
9a799d71
AK		 641{
642 u32 i;
643 u32 reg;
644 s32 status = IXGBE_ERR_EEPROM;
645
21ce849b
MC		 646 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
647 if (ee_reg == IXGBE_NVM_POLL_READ)
648 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
649 else
650 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
651
652 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
9a799d71
AK		 653 status = 0;
654 break;
655 }
656 udelay(5);
657 }
658 return status;
659}
660
c44ade9e
JB		 661/**
662 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
663 * @hw: pointer to hardware structure
664 *
665 * Prepares EEPROM for access using bit-bang method. This function should
666 * be called before issuing a command to the EEPROM.
667 **/
668static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
669{
670 s32 status = 0;
fc1f2095 671 u32 eec = 0;
c44ade9e
JB		 672 u32 i;
673
674 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
675 status = IXGBE_ERR_SWFW_SYNC;
676
677 if (status == 0) {
678 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
679
680 /* Request EEPROM Access */
681 eec |= IXGBE_EEC_REQ;
682 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
683
684 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
685 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
686 if (eec & IXGBE_EEC_GNT)
687 break;
688 udelay(5);
689 }
690
691 /* Release if grant not acquired */
692 if (!(eec & IXGBE_EEC_GNT)) {
693 eec &= ~IXGBE_EEC_REQ;
694 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
695 hw_dbg(hw, "Could not acquire EEPROM grant\n");
696
697 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
698 status = IXGBE_ERR_EEPROM;
699 }
700 }
701
702 /* Setup EEPROM for Read/Write */
703 if (status == 0) {
704 /* Clear CS and SK */
705 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
706 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
707 IXGBE_WRITE_FLUSH(hw);
708 udelay(1);
709 }
710 return status;
711}
712
9a799d71
AK		 713/**
714 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
715 * @hw: pointer to hardware structure
716 *
717 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
718 **/
719static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
720{
721 s32 status = IXGBE_ERR_EEPROM;
722 u32 timeout;
723 u32 i;
724 u32 swsm;
725
726 /* Set timeout value based on size of EEPROM */
727 timeout = hw->eeprom.word_size + 1;
728
729 /* Get SMBI software semaphore between device drivers first */
730 for (i = 0; i < timeout; i++) {
731 /*
732 * If the SMBI bit is 0 when we read it, then the bit will be
733 * set and we have the semaphore
734 */
735 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
736 if (!(swsm & IXGBE_SWSM_SMBI)) {
737 status = 0;
738 break;
739 }
740 msleep(1);
741 }
742
743 /* Now get the semaphore between SW/FW through the SWESMBI bit */
744 if (status == 0) {
745 for (i = 0; i < timeout; i++) {
746 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
747
748 /* Set the SW EEPROM semaphore bit to request access */
749 swsm |= IXGBE_SWSM_SWESMBI;
750 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
751
752 /*
753 * If we set the bit successfully then we got the
754 * semaphore.
755 */
756 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
757 if (swsm & IXGBE_SWSM_SWESMBI)
758 break;
759
760 udelay(50);
761 }
762
763 /*
764 * Release semaphores and return error if SW EEPROM semaphore
765 * was not granted because we don't have access to the EEPROM
766 */
767 if (i >= timeout) {
768 hw_dbg(hw, "Driver can't access the Eeprom - Semaphore "
b4617240 769 "not granted.\n");
9a799d71
AK		 770 ixgbe_release_eeprom_semaphore(hw);
771 status = IXGBE_ERR_EEPROM;
772 }
773 }
774
775 return status;
776}
777
778/**
779 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
780 * @hw: pointer to hardware structure
781 *
782 * This function clears hardware semaphore bits.
783 **/
784static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
785{
786 u32 swsm;
787
788 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
789
790 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
791 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
792 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
3957d63d 793 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 794}
795
c44ade9e
JB		 796/**
797 * ixgbe_ready_eeprom - Polls for EEPROM ready
798 * @hw: pointer to hardware structure
799 **/
800static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
801{
802 s32 status = 0;
803 u16 i;
804 u8 spi_stat_reg;
805
806 /*
807 * Read "Status Register" repeatedly until the LSB is cleared. The
808 * EEPROM will signal that the command has been completed by clearing
809 * bit 0 of the internal status register. If it's not cleared within
810 * 5 milliseconds, then error out.
811 */
812 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
813 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
814 IXGBE_EEPROM_OPCODE_BITS);
815 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
816 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
817 break;
818
819 udelay(5);
820 ixgbe_standby_eeprom(hw);
821 };
822
823 /*
824 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
825 * devices (and only 0-5mSec on 5V devices)
826 */
827 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
828 hw_dbg(hw, "SPI EEPROM Status error\n");
829 status = IXGBE_ERR_EEPROM;
830 }
831
832 return status;
833}
834
835/**
836 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
837 * @hw: pointer to hardware structure
838 **/
839static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
840{
841 u32 eec;
842
843 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
844
845 /* Toggle CS to flush commands */
846 eec |= IXGBE_EEC_CS;
847 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
848 IXGBE_WRITE_FLUSH(hw);
849 udelay(1);
850 eec &= ~IXGBE_EEC_CS;
851 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
852 IXGBE_WRITE_FLUSH(hw);
853 udelay(1);
854}
855
856/**
857 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
858 * @hw: pointer to hardware structure
859 * @data: data to send to the EEPROM
860 * @count: number of bits to shift out
861 **/
862static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
863 u16 count)
864{
865 u32 eec;
866 u32 mask;
867 u32 i;
868
869 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
870
871 /*
872 * Mask is used to shift "count" bits of "data" out to the EEPROM
873 * one bit at a time. Determine the starting bit based on count
874 */
875 mask = 0x01 << (count - 1);
876
877 for (i = 0; i < count; i++) {
878 /*
879 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
880 * "1", and then raising and then lowering the clock (the SK
881 * bit controls the clock input to the EEPROM). A "0" is
882 * shifted out to the EEPROM by setting "DI" to "0" and then
883 * raising and then lowering the clock.
884 */
885 if (data & mask)
886 eec |= IXGBE_EEC_DI;
887 else
888 eec &= ~IXGBE_EEC_DI;
889
890 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
891 IXGBE_WRITE_FLUSH(hw);
892
893 udelay(1);
894
895 ixgbe_raise_eeprom_clk(hw, &eec);
896 ixgbe_lower_eeprom_clk(hw, &eec);
897
898 /*
899 * Shift mask to signify next bit of data to shift in to the
900 * EEPROM
901 */
902 mask = mask >> 1;
903 };
904
905 /* We leave the "DI" bit set to "0" when we leave this routine. */
906 eec &= ~IXGBE_EEC_DI;
907 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
908 IXGBE_WRITE_FLUSH(hw);
909}
910
911/**
912 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
913 * @hw: pointer to hardware structure
914 **/
915static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
916{
917 u32 eec;
918 u32 i;
919 u16 data = 0;
920
921 /*
922 * In order to read a register from the EEPROM, we need to shift
923 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
924 * the clock input to the EEPROM (setting the SK bit), and then reading
925 * the value of the "DO" bit. During this "shifting in" process the
926 * "DI" bit should always be clear.
927 */
928 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
929
930 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
931
932 for (i = 0; i < count; i++) {
933 data = data << 1;
934 ixgbe_raise_eeprom_clk(hw, &eec);
935
936 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
937
938 eec &= ~(IXGBE_EEC_DI);
939 if (eec & IXGBE_EEC_DO)
940 data |= 1;
941
942 ixgbe_lower_eeprom_clk(hw, &eec);
943 }
944
945 return data;
946}
947
948/**
949 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
950 * @hw: pointer to hardware structure
951 * @eec: EEC register's current value
952 **/
953static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
954{
955 /*
956 * Raise the clock input to the EEPROM
957 * (setting the SK bit), then delay
958 */
959 *eec = *eec | IXGBE_EEC_SK;
960 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
961 IXGBE_WRITE_FLUSH(hw);
962 udelay(1);
963}
964
965/**
966 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
967 * @hw: pointer to hardware structure
968 * @eecd: EECD's current value
969 **/
970static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
971{
972 /*
973 * Lower the clock input to the EEPROM (clearing the SK bit), then
974 * delay
975 */
976 *eec = *eec & ~IXGBE_EEC_SK;
977 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
978 IXGBE_WRITE_FLUSH(hw);
979 udelay(1);
980}
981
982/**
983 * ixgbe_release_eeprom - Release EEPROM, release semaphores
984 * @hw: pointer to hardware structure
985 **/
986static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
987{
988 u32 eec;
989
990 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
991
992 eec |= IXGBE_EEC_CS; /* Pull CS high */
993 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
994
995 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
996 IXGBE_WRITE_FLUSH(hw);
997
998 udelay(1);
999
1000 /* Stop requesting EEPROM access */
1001 eec &= ~IXGBE_EEC_REQ;
1002 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1003
1004 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1005}
1006
9a799d71
AK		 1007/**
1008 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
1009 * @hw: pointer to hardware structure
1010 **/
1011static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
1012{
1013 u16 i;
1014 u16 j;
1015 u16 checksum = 0;
1016 u16 length = 0;
1017 u16 pointer = 0;
1018 u16 word = 0;
1019
1020 /* Include 0x0-0x3F in the checksum */
1021 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
c44ade9e 1022 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
9a799d71
AK		 1023 hw_dbg(hw, "EEPROM read failed\n");
1024 break;
1025 }
1026 checksum += word;
1027 }
1028
1029 /* Include all data from pointers except for the fw pointer */
1030 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
c44ade9e 1031 hw->eeprom.ops.read(hw, i, &pointer);
9a799d71
AK		 1032
1033 /* Make sure the pointer seems valid */
1034 if (pointer != 0xFFFF && pointer != 0) {
c44ade9e 1035 hw->eeprom.ops.read(hw, pointer, &length);
9a799d71
AK		 1036
1037 if (length != 0xFFFF && length != 0) {
1038 for (j = pointer+1; j <= pointer+length; j++) {
c44ade9e 1039 hw->eeprom.ops.read(hw, j, &word);
9a799d71
AK		 1040 checksum += word;
1041 }
1042 }
1043 }
1044 }
1045
1046 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1047
1048 return checksum;
1049}
1050
1051/**
c44ade9e 1052 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1053 * @hw: pointer to hardware structure
1054 * @checksum_val: calculated checksum
1055 *
1056 * Performs checksum calculation and validates the EEPROM checksum. If the
1057 * caller does not need checksum_val, the value can be NULL.
1058 **/
c44ade9e
JB		 1059s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1060 u16 *checksum_val)
9a799d71
AK		 1061{
1062 s32 status;
1063 u16 checksum;
1064 u16 read_checksum = 0;
1065
1066 /*
1067 * Read the first word from the EEPROM. If this times out or fails, do
1068 * not continue or we could be in for a very long wait while every
1069 * EEPROM read fails
1070 */
c44ade9e 1071 status = hw->eeprom.ops.read(hw, 0, &checksum);
9a799d71
AK		 1072
1073 if (status == 0) {
1074 checksum = ixgbe_calc_eeprom_checksum(hw);
1075
c44ade9e 1076 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
9a799d71
AK		 1077
1078 /*
1079 * Verify read checksum from EEPROM is the same as
1080 * calculated checksum
1081 */
1082 if (read_checksum != checksum)
1083 status = IXGBE_ERR_EEPROM_CHECKSUM;
1084
1085 /* If the user cares, return the calculated checksum */
1086 if (checksum_val)
1087 *checksum_val = checksum;
1088 } else {
1089 hw_dbg(hw, "EEPROM read failed\n");
1090 }
1091
1092 return status;
1093}
1094
c44ade9e
JB		 1095/**
1096 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1097 * @hw: pointer to hardware structure
1098 **/
1099s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1100{
1101 s32 status;
1102 u16 checksum;
1103
1104 /*
1105 * Read the first word from the EEPROM. If this times out or fails, do
1106 * not continue or we could be in for a very long wait while every
1107 * EEPROM read fails
1108 */
1109 status = hw->eeprom.ops.read(hw, 0, &checksum);
1110
1111 if (status == 0) {
1112 checksum = ixgbe_calc_eeprom_checksum(hw);
1113 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1114 checksum);
1115 } else {
1116 hw_dbg(hw, "EEPROM read failed\n");
1117 }
1118
1119 return status;
1120}
1121
9a799d71
AK		 1122/**
1123 * ixgbe_validate_mac_addr - Validate MAC address
1124 * @mac_addr: pointer to MAC address.
1125 *
1126 * Tests a MAC address to ensure it is a valid Individual Address
1127 **/
1128s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1129{
1130 s32 status = 0;
1131
1132 /* Make sure it is not a multicast address */
1133 if (IXGBE_IS_MULTICAST(mac_addr))
1134 status = IXGBE_ERR_INVALID_MAC_ADDR;
1135 /* Not a broadcast address */
1136 else if (IXGBE_IS_BROADCAST(mac_addr))
1137 status = IXGBE_ERR_INVALID_MAC_ADDR;
1138 /* Reject the zero address */
1139 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
c44ade9e 1140 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
9a799d71
AK		 1141 status = IXGBE_ERR_INVALID_MAC_ADDR;
1142
1143 return status;
1144}
1145
1146/**
c44ade9e 1147 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1148 * @hw: pointer to hardware structure
9a799d71 1149 * @index: Receive address register to write
c44ade9e
JB		 1150 * @addr: Address to put into receive address register
1151 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1152 * @enable_addr: set flag that address is active
1153 *
1154 * Puts an ethernet address into a receive address register.
1155 **/
c44ade9e
JB		 1156s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1157 u32 enable_addr)
9a799d71
AK		 1158{
1159 u32 rar_low, rar_high;
c44ade9e
JB		 1160 u32 rar_entries = hw->mac.num_rar_entries;
1161
1162 /* setup VMDq pool selection before this RAR gets enabled */
1163 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1164
c44ade9e
JB		 1165 /* Make sure we are using a valid rar index range */
1166 if (index < rar_entries) {
b4617240 1167 /*
c44ade9e
JB		 1168 * HW expects these in little endian so we reverse the byte
1169 * order from network order (big endian) to little endian
b4617240
PW		 1170 */
1171 rar_low = ((u32)addr[0] |
1172 ((u32)addr[1] << 8) |
1173 ((u32)addr[2] << 16) |
1174 ((u32)addr[3] << 24));
c44ade9e
JB		 1175 /*
1176 * Some parts put the VMDq setting in the extra RAH bits,
1177 * so save everything except the lower 16 bits that hold part
1178 * of the address and the address valid bit.
1179 */
1180 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1181 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1182 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1183
b4617240
PW		 1184 if (enable_addr != 0)
1185 rar_high |= IXGBE_RAH_AV;
9a799d71 1186
b4617240
PW		 1187 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1188 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1189 } else {
1190 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1191 }
1192
1193 return 0;
1194}
1195
1196/**
1197 * ixgbe_clear_rar_generic - Remove Rx address register
1198 * @hw: pointer to hardware structure
1199 * @index: Receive address register to write
1200 *
1201 * Clears an ethernet address from a receive address register.
1202 **/
1203s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1204{
1205 u32 rar_high;
1206 u32 rar_entries = hw->mac.num_rar_entries;
1207
1208 /* Make sure we are using a valid rar index range */
1209 if (index < rar_entries) {
1210 /*
1211 * Some parts put the VMDq setting in the extra RAH bits,
1212 * so save everything except the lower 16 bits that hold part
1213 * of the address and the address valid bit.
1214 */
1215 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1216 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1217
1218 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1219 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1220 } else {
1221 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1222 }
1223
1224 /* clear VMDq pool/queue selection for this RAR */
1225 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1226
1227 return 0;
1228}
1229
1230/**
c44ade9e
JB		 1231 * ixgbe_enable_rar - Enable Rx address register
1232 * @hw: pointer to hardware structure
1233 * @index: index into the RAR table
1234 *
1235 * Enables the select receive address register.
1236 **/
1237static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
1238{
1239 u32 rar_high;
1240
1241 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1242 rar_high |= IXGBE_RAH_AV;
1243 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1244}
1245
1246/**
1247 * ixgbe_disable_rar - Disable Rx address register
1248 * @hw: pointer to hardware structure
1249 * @index: index into the RAR table
1250 *
1251 * Disables the select receive address register.
1252 **/
1253static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
1254{
1255 u32 rar_high;
1256
1257 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1258 rar_high &= (~IXGBE_RAH_AV);
1259 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1260}
1261
1262/**
1263 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1264 * @hw: pointer to hardware structure
1265 *
1266 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1267 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1268 * the receiver is in reset when the routine is called.
1269 **/
c44ade9e 1270s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1271{
1272 u32 i;
2c5645cf 1273 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1274
1275 /*
1276 * If the current mac address is valid, assume it is a software override
1277 * to the permanent address.
1278 * Otherwise, use the permanent address from the eeprom.
1279 */
1280 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1281 IXGBE_ERR_INVALID_MAC_ADDR) {
1282 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1283 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1284
ce7194d8 1285 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1286 } else {
1287 /* Setup the receive address. */
1288 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1289 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1290
c44ade9e 1291 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71 1292 }
c44ade9e 1293 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1294
1295 hw->addr_ctrl.rar_used_count = 1;
1296
1297 /* Zero out the other receive addresses. */
c44ade9e 1298 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1299 for (i = 1; i < rar_entries; i++) {
1300 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1301 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1302 }
1303
1304 /* Clear the MTA */
1305 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1306 hw->addr_ctrl.mta_in_use = 0;
1307 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1308
1309 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1310 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1311 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1312
c44ade9e
JB		 1313 if (hw->mac.ops.init_uta_tables)
1314 hw->mac.ops.init_uta_tables(hw);
1315
9a799d71
AK		 1316 return 0;
1317}
1318
2c5645cf
CL		 1319/**
1320 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1321 * @hw: pointer to hardware structure
1322 * @addr: new address
1323 *
1324 * Adds it to unused receive address register or goes into promiscuous mode.
1325 **/
c44ade9e 1326static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2c5645cf
CL		 1327{
1328 u32 rar_entries = hw->mac.num_rar_entries;
1329 u32 rar;
1330
1331 hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1332 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1333
1334 /*
1335 * Place this address in the RAR if there is room,
1336 * else put the controller into promiscuous mode
1337 */
1338 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1339 rar = hw->addr_ctrl.rar_used_count -
1340 hw->addr_ctrl.mc_addr_in_rar_count;
c44ade9e 1341 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2c5645cf
CL		 1342 hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
1343 hw->addr_ctrl.rar_used_count++;
1344 } else {
1345 hw->addr_ctrl.overflow_promisc++;
1346 }
1347
1348 hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
1349}
1350
1351/**
c44ade9e 1352 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2c5645cf 1353 * @hw: pointer to hardware structure
32e7bfc4 1354 * @netdev: pointer to net device structure
2c5645cf
CL		 1355 *
1356 * The given list replaces any existing list. Clears the secondary addrs from
1357 * receive address registers. Uses unused receive address registers for the
1358 * first secondary addresses, and falls back to promiscuous mode as needed.
1359 *
1360 * Drivers using secondary unicast addresses must set user_set_promisc when
1361 * manually putting the device into promiscuous mode.
1362 **/
ccffad25 1363s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw,
32e7bfc4 1364 struct net_device *netdev)
2c5645cf 1365{
2c5645cf
CL		 1366 u32 i;
1367 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1368 u32 uc_addr_in_use;
1369 u32 fctrl;
ccffad25 1370 struct netdev_hw_addr *ha;
2c5645cf
CL		 1371
1372 /*
1373 * Clear accounting of old secondary address list,
1374 * don't count RAR[0]
1375 */
495dce12 1376 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2c5645cf
CL		 1377 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1378 hw->addr_ctrl.overflow_promisc = 0;
1379
1380 /* Zero out the other receive addresses */
91152c32
SN		 1381 hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use + 1);
1382 for (i = 0; i < uc_addr_in_use; i++) {
1383 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
1384 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2c5645cf
CL		 1385 }
1386
1387 /* Add the new addresses */
32e7bfc4 1388 netdev_for_each_uc_addr(ha, netdev) {
2c5645cf 1389 hw_dbg(hw, " Adding the secondary addresses:\n");
ccffad25 1390 ixgbe_add_uc_addr(hw, ha->addr, 0);
2c5645cf
CL		 1391 }
1392
1393 if (hw->addr_ctrl.overflow_promisc) {
1394 /* enable promisc if not already in overflow or set by user */
1395 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1396 hw_dbg(hw, " Entering address overflow promisc mode\n");
1397 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1398 fctrl |= IXGBE_FCTRL_UPE;
1399 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
e433ea1f 1400 hw->addr_ctrl.uc_set_promisc = true;
2c5645cf
CL		 1401 }
1402 } else {
1403 /* only disable if set by overflow, not by user */
e433ea1f
ET		 1404 if ((old_promisc_setting && hw->addr_ctrl.uc_set_promisc) &&
1405 !(hw->addr_ctrl.user_set_promisc)) {
2c5645cf
CL		 1406 hw_dbg(hw, " Leaving address overflow promisc mode\n");
1407 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1408 fctrl &= ~IXGBE_FCTRL_UPE;
1409 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
e433ea1f 1410 hw->addr_ctrl.uc_set_promisc = false;
2c5645cf
CL		 1411 }
1412 }
1413
c44ade9e 1414 hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
2c5645cf
CL		 1415 return 0;
1416}
1417
9a799d71
AK		 1418/**
1419 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1420 * @hw: pointer to hardware structure
1421 * @mc_addr: the multicast address
1422 *
1423 * Extracts the 12 bits, from a multicast address, to determine which
1424 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1425 * incoming rx multicast addresses, to determine the bit-vector to check in
1426 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1427 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1428 * to mc_filter_type.
1429 **/
1430static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1431{
1432 u32 vector = 0;
1433
1434 switch (hw->mac.mc_filter_type) {
b4617240 1435 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1436 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1437 break;
b4617240 1438 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1439 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1440 break;
b4617240 1441 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1442 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1443 break;
b4617240 1444 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1445 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1446 break;
b4617240 1447 default: /* Invalid mc_filter_type */
9a799d71
AK		 1448 hw_dbg(hw, "MC filter type param set incorrectly\n");
1449 break;
1450 }
1451
1452 /* vector can only be 12-bits or boundary will be exceeded */
1453 vector &= 0xFFF;
1454 return vector;
1455}
1456
1457/**
1458 * ixgbe_set_mta - Set bit-vector in multicast table
1459 * @hw: pointer to hardware structure
1460 * @hash_value: Multicast address hash value
1461 *
1462 * Sets the bit-vector in the multicast table.
1463 **/
1464static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1465{
1466 u32 vector;
1467 u32 vector_bit;
1468 u32 vector_reg;
1469 u32 mta_reg;
1470
1471 hw->addr_ctrl.mta_in_use++;
1472
1473 vector = ixgbe_mta_vector(hw, mc_addr);
1474 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1475
1476 /*
1477 * The MTA is a register array of 128 32-bit registers. It is treated
1478 * like an array of 4096 bits. We want to set bit
1479 * BitArray[vector_value]. So we figure out what register the bit is
1480 * in, read it, OR in the new bit, then write back the new value. The
1481 * register is determined by the upper 7 bits of the vector value and
1482 * the bit within that register are determined by the lower 5 bits of
1483 * the value.
1484 */
1485 vector_reg = (vector >> 5) & 0x7F;
1486 vector_bit = vector & 0x1F;
1487 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
1488 mta_reg |= (1 << vector_bit);
1489 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
1490}
1491
9a799d71 1492/**
c44ade9e 1493 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71 1494 * @hw: pointer to hardware structure
2853eb89 1495 * @netdev: pointer to net device structure
9a799d71
AK		 1496 *
1497 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 1498 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 1499 * registers for the first multicast addresses, and hashes the rest into the
1500 * multicast table.
1501 **/
2853eb89
JP		 1502s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1503 struct net_device *netdev)
9a799d71 1504{
22bedad3 1505 struct netdev_hw_addr *ha;
9a799d71 1506 u32 i;
9a799d71
AK		 1507
1508 /*
1509 * Set the new number of MC addresses that we are being requested to
1510 * use.
1511 */
2853eb89 1512 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
9a799d71
AK		 1513 hw->addr_ctrl.mta_in_use = 0;
1514
9a799d71
AK		 1515 /* Clear the MTA */
1516 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1517 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1518 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1519
1520 /* Add the new addresses */
22bedad3 1521 netdev_for_each_mc_addr(ha, netdev) {
9a799d71 1522 hw_dbg(hw, " Adding the multicast addresses:\n");
22bedad3 1523 ixgbe_set_mta(hw, ha->addr);
9a799d71
AK		 1524 }
1525
1526 /* Enable mta */
1527 if (hw->addr_ctrl.mta_in_use > 0)
1528 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
b4617240 1529 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 1530
c44ade9e 1531 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 1532 return 0;
1533}
1534
1535/**
c44ade9e 1536 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 1537 * @hw: pointer to hardware structure
1538 *
c44ade9e 1539 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 1540 **/
c44ade9e 1541s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1542{
c44ade9e
JB		 1543 u32 i;
1544 u32 rar_entries = hw->mac.num_rar_entries;
1545 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 1546
c44ade9e
JB		 1547 if (a->mc_addr_in_rar_count > 0)
1548 for (i = (rar_entries - a->mc_addr_in_rar_count);
1549 i < rar_entries; i++)
1550 ixgbe_enable_rar(hw, i);
9a799d71 1551
c44ade9e
JB		 1552 if (a->mta_in_use > 0)
1553 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1554 hw->mac.mc_filter_type);
9a799d71
AK		 1555
1556 return 0;
1557}
1558
1559/**
c44ade9e 1560 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 1561 * @hw: pointer to hardware structure
9a799d71 1562 *
c44ade9e 1563 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 1564 **/
c44ade9e 1565s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1566{
c44ade9e
JB		 1567 u32 i;
1568 u32 rar_entries = hw->mac.num_rar_entries;
1569 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 1570
c44ade9e
JB		 1571 if (a->mc_addr_in_rar_count > 0)
1572 for (i = (rar_entries - a->mc_addr_in_rar_count);
1573 i < rar_entries; i++)
1574 ixgbe_disable_rar(hw, i);
9a799d71 1575
c44ade9e
JB		 1576 if (a->mta_in_use > 0)
1577 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 1578
1579 return 0;
1580}
1581
11afc1b1 1582/**
620fa036 1583 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1
PW		 1584 * @hw: pointer to hardware structure
1585 * @packetbuf_num: packet buffer number (0-7)
1586 *
1587 * Enable flow control according to the current settings.
1588 **/
620fa036 1589s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 1590{
1591 s32 ret_val = 0;
620fa036 1592 u32 mflcn_reg, fccfg_reg;
11afc1b1 1593 u32 reg;
70b77628
PWJ		 1594 u32 rx_pba_size;
1595
1596#ifdef CONFIG_DCB
1597 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1598 goto out;
1599
1600#endif /* CONFIG_DCB */
620fa036
MC		 1601 /* Negotiate the fc mode to use */
1602 ret_val = ixgbe_fc_autoneg(hw);
1603 if (ret_val)
1604 goto out;
11afc1b1 1605
620fa036 1606 /* Disable any previous flow control settings */
11afc1b1
PW		 1607 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1608 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1609
1610 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1611 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1612
1613 /*
1614 * The possible values of fc.current_mode are:
1615 * 0: Flow control is completely disabled
1616 * 1: Rx flow control is enabled (we can receive pause frames,
1617 * but not send pause frames).
bb3daa4a
PW		 1618 * 2: Tx flow control is enabled (we can send pause frames but
1619 * we do not support receiving pause frames).
11afc1b1 1620 * 3: Both Rx and Tx flow control (symmetric) are enabled.
bb3daa4a 1621 * 4: Priority Flow Control is enabled.
11afc1b1
PW		 1622 * other: Invalid.
1623 */
1624 switch (hw->fc.current_mode) {
1625 case ixgbe_fc_none:
620fa036
MC		 1626 /*
1627 * Flow control is disabled by software override or autoneg.
1628 * The code below will actually disable it in the HW.
1629 */
11afc1b1
PW		 1630 break;
1631 case ixgbe_fc_rx_pause:
1632 /*
1633 * Rx Flow control is enabled and Tx Flow control is
1634 * disabled by software override. Since there really
1635 * isn't a way to advertise that we are capable of RX
1636 * Pause ONLY, we will advertise that we support both
1637 * symmetric and asymmetric Rx PAUSE. Later, we will
1638 * disable the adapter's ability to send PAUSE frames.
1639 */
1640 mflcn_reg |= IXGBE_MFLCN_RFCE;
1641 break;
1642 case ixgbe_fc_tx_pause:
1643 /*
1644 * Tx Flow control is enabled, and Rx Flow control is
1645 * disabled by software override.
1646 */
1647 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1648 break;
1649 case ixgbe_fc_full:
1650 /* Flow control (both Rx and Tx) is enabled by SW override. */
1651 mflcn_reg |= IXGBE_MFLCN_RFCE;
1652 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1653 break;
bb3daa4a
PW		 1654#ifdef CONFIG_DCB
1655 case ixgbe_fc_pfc:
1656 goto out;
1657 break;
620fa036 1658#endif /* CONFIG_DCB */
11afc1b1
PW		 1659 default:
1660 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 1661 ret_val = IXGBE_ERR_CONFIG;
11afc1b1
PW		 1662 goto out;
1663 break;
1664 }
1665
620fa036 1666 /* Set 802.3x based flow control settings. */
2132d381 1667 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 1668 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1669 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1670
70b77628
PWJ		 1671 reg = IXGBE_READ_REG(hw, IXGBE_MTQC);
1672 /* Thresholds are different for link flow control when in DCB mode */
1673 if (reg & IXGBE_MTQC_RT_ENA) {
620fa036
MC		 1674 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
1675
70b77628 1676 /* Always disable XON for LFC when in DCB mode */
620fa036
MC		 1677 reg = (rx_pba_size >> 5) & 0xFFE0;
1678 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg);
264857b8 1679
70b77628
PWJ		 1680 reg = (rx_pba_size >> 2) & 0xFFE0;
1681 if (hw->fc.current_mode & ixgbe_fc_tx_pause)
1682 reg |= IXGBE_FCRTH_FCEN;
1683 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg);
1684 } else {
1685 /*
1686 * Set up and enable Rx high/low water mark thresholds,
1687 * enable XON.
1688 */
1689 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1690 if (hw->fc.send_xon) {
1691 IXGBE_WRITE_REG(hw,
1692 IXGBE_FCRTL_82599(packetbuf_num),
1693 (hw->fc.low_water |
1694 IXGBE_FCRTL_XONE));
1695 } else {
1696 IXGBE_WRITE_REG(hw,
1697 IXGBE_FCRTL_82599(packetbuf_num),
1698 hw->fc.low_water);
1699 }
1700
1701 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
1702 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
1703 }
11afc1b1
PW		 1704 }
1705
1706 /* Configure pause time (2 TCs per register) */
70b77628 1707 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
11afc1b1
PW		 1708 if ((packetbuf_num & 1) == 0)
1709 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1710 else
1711 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1712 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1713
1714 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1715
1716out:
1717 return ret_val;
1718}
1719
0ecc061d
PWJ		 1720/**
1721 * ixgbe_fc_autoneg - Configure flow control
1722 * @hw: pointer to hardware structure
1723 *
620fa036
MC		 1724 * Compares our advertised flow control capabilities to those advertised by
1725 * our link partner, and determines the proper flow control mode to use.
0ecc061d
PWJ		 1726 **/
1727s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1728{
1729 s32 ret_val = 0;
620fa036
MC		 1730 ixgbe_link_speed speed;
1731 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
539e5f02 1732 u32 links2, anlp1_reg, autoc_reg, links;
620fa036 1733 bool link_up;
0ecc061d
PWJ		 1734
1735 /*
620fa036
MC		 1736 * AN should have completed when the cable was plugged in.
1737 * Look for reasons to bail out. Bail out if:
1738 * - FC autoneg is disabled, or if
539e5f02 1739 * - link is not up.
620fa036 1740 *
539e5f02 1741 * Since we're being called from an LSC, link is already known to be up.
620fa036 1742 * So use link_up_wait_to_complete=false.
0ecc061d 1743 */
620fa036 1744 hw->mac.ops.check_link(hw, &speed, &link_up, false);
539e5f02
PWJ		 1745
1746 if (hw->fc.disable_fc_autoneg || (!link_up)) {
620fa036
MC		 1747 hw->fc.fc_was_autonegged = false;
1748 hw->fc.current_mode = hw->fc.requested_mode;
0ecc061d
PWJ		 1749 goto out;
1750 }
1751
539e5f02
PWJ		 1752 /*
1753 * On backplane, bail out if
1754 * - backplane autoneg was not completed, or if
000c486d 1755 * - we are 82599 and link partner is not AN enabled
539e5f02
PWJ		 1756 */
1757 if (hw->phy.media_type == ixgbe_media_type_backplane) {
1758 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
000c486d 1759 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
539e5f02
PWJ		 1760 hw->fc.fc_was_autonegged = false;
1761 hw->fc.current_mode = hw->fc.requested_mode;
1762 goto out;
1763 }
000c486d
DS		 1764
1765 if (hw->mac.type == ixgbe_mac_82599EB) {
1766 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
1767 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
1768 hw->fc.fc_was_autonegged = false;
1769 hw->fc.current_mode = hw->fc.requested_mode;
1770 goto out;
1771 }
1772 }
539e5f02
PWJ		 1773 }
1774
1775 /*
1776 * On multispeed fiber at 1g, bail out if
1777 * - link is up but AN did not complete, or if
1778 * - link is up and AN completed but timed out
1779 */
1780 if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) {
1781 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1782 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
1783 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
1784 hw->fc.fc_was_autonegged = false;
1785 hw->fc.current_mode = hw->fc.requested_mode;
1786 goto out;
1787 }
1788 }
1789
9bbe3a57
PW		 1790 /*
1791 * Bail out on
1792 * - copper or CX4 adapters
1793 * - fiber adapters running at 10gig
1794 */
1795 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
1796 (hw->phy.media_type == ixgbe_media_type_cx4) ||
1797 ((hw->phy.media_type == ixgbe_media_type_fiber) &&
1798 (speed == IXGBE_LINK_SPEED_10GB_FULL))) {
1799 hw->fc.fc_was_autonegged = false;
1800 hw->fc.current_mode = hw->fc.requested_mode;
1801 goto out;
1802 }
1803
0ecc061d
PWJ		 1804 /*
1805 * Read the AN advertisement and LP ability registers and resolve
1806 * local flow control settings accordingly
1807 */
539e5f02
PWJ		 1808 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1809 (hw->phy.media_type != ixgbe_media_type_backplane)) {
1810 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1811 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1812 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1813 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
1814 /*
1815 * Now we need to check if the user selected Rx ONLY
1816 * of pause frames. In this case, we had to advertise
1817 * FULL flow control because we could not advertise RX
1818 * ONLY. Hence, we must now check to see if we need to
1819 * turn OFF the TRANSMISSION of PAUSE frames.
1820 */
1821 if (hw->fc.requested_mode == ixgbe_fc_full) {
1822 hw->fc.current_mode = ixgbe_fc_full;
1823 hw_dbg(hw, "Flow Control = FULL.\n");
1824 } else {
1825 hw->fc.current_mode = ixgbe_fc_rx_pause;
1826 hw_dbg(hw, "Flow Control=RX PAUSE only\n");
1827 }
1828 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1829 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1830 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1831 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1832 hw->fc.current_mode = ixgbe_fc_tx_pause;
1833 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1834 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1835 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1836 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1837 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1838 hw->fc.current_mode = ixgbe_fc_rx_pause;
1839 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1840 } else {
1841 hw->fc.current_mode = ixgbe_fc_none;
1842 hw_dbg(hw, "Flow Control = NONE.\n");
1843 }
1844 }
1845
1846 if (hw->phy.media_type == ixgbe_media_type_backplane) {
0ecc061d 1847 /*
539e5f02
PWJ		 1848 * Read the 10g AN autoc and LP ability registers and resolve
1849 * local flow control settings accordingly
0ecc061d 1850 */
539e5f02
PWJ		 1851 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1852 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
1853
1854 if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1855 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) {
1856 /*
1857 * Now we need to check if the user selected Rx ONLY
1858 * of pause frames. In this case, we had to advertise
1859 * FULL flow control because we could not advertise RX
1860 * ONLY. Hence, we must now check to see if we need to
1861 * turn OFF the TRANSMISSION of PAUSE frames.
1862 */
1863 if (hw->fc.requested_mode == ixgbe_fc_full) {
1864 hw->fc.current_mode = ixgbe_fc_full;
1865 hw_dbg(hw, "Flow Control = FULL.\n");
1866 } else {
1867 hw->fc.current_mode = ixgbe_fc_rx_pause;
1868 hw_dbg(hw, "Flow Control=RX PAUSE only\n");
1869 }
1870 } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1871 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
1872 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
1873 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
1874 hw->fc.current_mode = ixgbe_fc_tx_pause;
1875 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1876 } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1877 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
1878 !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
1879 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
0ecc061d
PWJ		 1880 hw->fc.current_mode = ixgbe_fc_rx_pause;
1881 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
539e5f02
PWJ		 1882 } else {
1883 hw->fc.current_mode = ixgbe_fc_none;
1884 hw_dbg(hw, "Flow Control = NONE.\n");
0ecc061d 1885 }
0ecc061d 1886 }
620fa036
MC		 1887 /* Record that current_mode is the result of a successful autoneg */
1888 hw->fc.fc_was_autonegged = true;
1889
0ecc061d
PWJ		 1890out:
1891 return ret_val;
1892}
1893
11afc1b1 1894/**
620fa036 1895 * ixgbe_setup_fc - Set up flow control
11afc1b1
PW		 1896 * @hw: pointer to hardware structure
1897 *
620fa036 1898 * Called at init time to set up flow control.
11afc1b1 1899 **/
7b25cdba 1900static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 1901{
1902 s32 ret_val = 0;
620fa036 1903 u32 reg;
11afc1b1 1904
bb3daa4a
PW		 1905#ifdef CONFIG_DCB
1906 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
1907 hw->fc.current_mode = hw->fc.requested_mode;
1908 goto out;
1909 }
1910
1911#endif
11afc1b1
PW		 1912 /* Validate the packetbuf configuration */
1913 if (packetbuf_num < 0 || packetbuf_num > 7) {
1914 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
1915 "is 0-7\n", packetbuf_num);
1916 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1917 goto out;
1918 }
1919
1920 /*
1921 * Validate the water mark configuration. Zero water marks are invalid
1922 * because it causes the controller to just blast out fc packets.
1923 */
1924 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
620fa036
MC		 1925 hw_dbg(hw, "Invalid water mark configuration\n");
1926 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1927 goto out;
11afc1b1
PW		 1928 }
1929
1930 /*
1931 * Validate the requested mode. Strict IEEE mode does not allow
620fa036 1932 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
11afc1b1
PW		 1933 */
1934 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
1935 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
1936 "IEEE mode\n");
1937 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1938 goto out;
1939 }
1940
1941 /*
1942 * 10gig parts do not have a word in the EEPROM to determine the
1943 * default flow control setting, so we explicitly set it to full.
1944 */
1945 if (hw->fc.requested_mode == ixgbe_fc_default)
1946 hw->fc.requested_mode = ixgbe_fc_full;
1947
1948 /*
620fa036
MC		 1949 * Set up the 1G flow control advertisement registers so the HW will be
1950 * able to do fc autoneg once the cable is plugged in. If we end up
1951 * using 10g instead, this is harmless.
11afc1b1 1952 */
620fa036 1953 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
11afc1b1 1954
620fa036
MC		 1955 /*
1956 * The possible values of fc.requested_mode are:
1957 * 0: Flow control is completely disabled
1958 * 1: Rx flow control is enabled (we can receive pause frames,
1959 * but not send pause frames).
1960 * 2: Tx flow control is enabled (we can send pause frames but
1961 * we do not support receiving pause frames).
1962 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1963#ifdef CONFIG_DCB
1964 * 4: Priority Flow Control is enabled.
1965#endif
1966 * other: Invalid.
1967 */
1968 switch (hw->fc.requested_mode) {
1969 case ixgbe_fc_none:
1970 /* Flow control completely disabled by software override. */
1971 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1972 break;
1973 case ixgbe_fc_rx_pause:
1974 /*
1975 * Rx Flow control is enabled and Tx Flow control is
1976 * disabled by software override. Since there really
1977 * isn't a way to advertise that we are capable of RX
1978 * Pause ONLY, we will advertise that we support both
1979 * symmetric and asymmetric Rx PAUSE. Later, we will
1980 * disable the adapter's ability to send PAUSE frames.
1981 */
1982 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1983 break;
1984 case ixgbe_fc_tx_pause:
1985 /*
1986 * Tx Flow control is enabled, and Rx Flow control is
1987 * disabled by software override.
1988 */
1989 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
1990 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
1991 break;
1992 case ixgbe_fc_full:
1993 /* Flow control (both Rx and Tx) is enabled by SW override. */
1994 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1995 break;
1996#ifdef CONFIG_DCB
1997 case ixgbe_fc_pfc:
11afc1b1 1998 goto out;
620fa036
MC		 1999 break;
2000#endif /* CONFIG_DCB */
2001 default:
2002 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 2003 ret_val = IXGBE_ERR_CONFIG;
620fa036
MC		 2004 goto out;
2005 break;
2006 }
2007
2008 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
2009 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
11afc1b1 2010
620fa036
MC		 2011 /* Disable AN timeout */
2012 if (hw->fc.strict_ieee)
2013 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
2014
2015 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
2016 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
11afc1b1 2017
539e5f02
PWJ		 2018 /*
2019 * Set up the 10G flow control advertisement registers so the HW
2020 * can do fc autoneg once the cable is plugged in. If we end up
2021 * using 1g instead, this is harmless.
2022 */
2023 reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2024
2025 /*
2026 * The possible values of fc.requested_mode are:
2027 * 0: Flow control is completely disabled
2028 * 1: Rx flow control is enabled (we can receive pause frames,
2029 * but not send pause frames).
2030 * 2: Tx flow control is enabled (we can send pause frames but
2031 * we do not support receiving pause frames).
2032 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2033 * other: Invalid.
2034 */
2035 switch (hw->fc.requested_mode) {
2036 case ixgbe_fc_none:
2037 /* Flow control completely disabled by software override. */
2038 reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2039 break;
2040 case ixgbe_fc_rx_pause:
2041 /*
2042 * Rx Flow control is enabled and Tx Flow control is
2043 * disabled by software override. Since there really
2044 * isn't a way to advertise that we are capable of RX
2045 * Pause ONLY, we will advertise that we support both
2046 * symmetric and asymmetric Rx PAUSE. Later, we will
2047 * disable the adapter's ability to send PAUSE frames.
2048 */
2049 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2050 break;
2051 case ixgbe_fc_tx_pause:
2052 /*
2053 * Tx Flow control is enabled, and Rx Flow control is
2054 * disabled by software override.
2055 */
2056 reg |= (IXGBE_AUTOC_ASM_PAUSE);
2057 reg &= ~(IXGBE_AUTOC_SYM_PAUSE);
2058 break;
2059 case ixgbe_fc_full:
2060 /* Flow control (both Rx and Tx) is enabled by SW override. */
2061 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2062 break;
2063#ifdef CONFIG_DCB
2064 case ixgbe_fc_pfc:
2065 goto out;
2066 break;
2067#endif /* CONFIG_DCB */
2068 default:
2069 hw_dbg(hw, "Flow control param set incorrectly\n");
2070 ret_val = IXGBE_ERR_CONFIG;
2071 goto out;
2072 break;
2073 }
2074 /*
2075 * AUTOC restart handles negotiation of 1G and 10G. There is
2076 * no need to set the PCS1GCTL register.
2077 */
2078 reg |= IXGBE_AUTOC_AN_RESTART;
2079 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg);
2080 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
2081
11afc1b1
PW		 2082out:
2083 return ret_val;
2084}
2085
9a799d71
AK		 2086/**
2087 * ixgbe_disable_pcie_master - Disable PCI-express master access
2088 * @hw: pointer to hardware structure
2089 *
2090 * Disables PCI-Express master access and verifies there are no pending
2091 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2092 * bit hasn't caused the master requests to be disabled, else 0
2093 * is returned signifying master requests disabled.
2094 **/
2095s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2096{
c44ade9e
JB		 2097 u32 i;
2098 u32 reg_val;
2099 u32 number_of_queues;
9a799d71
AK		 2100 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2101
c44ade9e
JB		 2102 /* Disable the receive unit by stopping each queue */
2103 number_of_queues = hw->mac.max_rx_queues;
2104 for (i = 0; i < number_of_queues; i++) {
2105 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
2106 if (reg_val & IXGBE_RXDCTL_ENABLE) {
2107 reg_val &= ~IXGBE_RXDCTL_ENABLE;
2108 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
2109 }
2110 }
2111
2112 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2113 reg_val |= IXGBE_CTRL_GIO_DIS;
2114 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
9a799d71
AK		 2115
2116 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2117 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
2118 status = 0;
2119 break;
2120 }
2121 udelay(100);
2122 }
2123
2124 return status;
2125}
2126
2127
2128/**
c44ade9e 2129 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2130 * @hw: pointer to hardware structure
c44ade9e 2131 * @mask: Mask to specify which semaphore to acquire
9a799d71 2132 *
c44ade9e 2133 * Acquires the SWFW semaphore thought the GSSR register for the specified
9a799d71
AK		 2134 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2135 **/
2136s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2137{
2138 u32 gssr;
2139 u32 swmask = mask;
2140 u32 fwmask = mask << 5;
2141 s32 timeout = 200;
2142
2143 while (timeout) {
2144 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2145 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2146
2147 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2148 if (!(gssr & (fwmask | swmask)))
2149 break;
2150
2151 /*
2152 * Firmware currently using resource (fwmask) or other software
2153 * thread currently using resource (swmask)
2154 */
2155 ixgbe_release_eeprom_semaphore(hw);
2156 msleep(5);
2157 timeout--;
2158 }
2159
2160 if (!timeout) {
2161 hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
539e5f02 2162 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2163 }
2164
2165 gssr |= swmask;
2166 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2167
2168 ixgbe_release_eeprom_semaphore(hw);
2169 return 0;
2170}
2171
2172/**
2173 * ixgbe_release_swfw_sync - Release SWFW semaphore
2174 * @hw: pointer to hardware structure
c44ade9e 2175 * @mask: Mask to specify which semaphore to release
9a799d71 2176 *
c44ade9e 2177 * Releases the SWFW semaphore thought the GSSR register for the specified
9a799d71
AK		 2178 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2179 **/
2180void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2181{
2182 u32 gssr;
2183 u32 swmask = mask;
2184
2185 ixgbe_get_eeprom_semaphore(hw);
2186
2187 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2188 gssr &= ~swmask;
2189 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2190
2191 ixgbe_release_eeprom_semaphore(hw);
2192}
2193
11afc1b1
PW		 2194/**
2195 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2196 * @hw: pointer to hardware structure
2197 * @regval: register value to write to RXCTRL
2198 *
2199 * Enables the Rx DMA unit
2200 **/
2201s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2202{
2203 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2204
2205 return 0;
2206}
87c12017
PW		 2207
2208/**
2209 * ixgbe_blink_led_start_generic - Blink LED based on index.
2210 * @hw: pointer to hardware structure
2211 * @index: led number to blink
2212 **/
2213s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2214{
2215 ixgbe_link_speed speed = 0;
2216 bool link_up = 0;
2217 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2218 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2219
2220 /*
2221 * Link must be up to auto-blink the LEDs;
2222 * Force it if link is down.
2223 */
2224 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2225
2226 if (!link_up) {
50ac58ba 2227 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017
PW		 2228 autoc_reg |= IXGBE_AUTOC_FLU;
2229 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2230 msleep(10);
2231 }
2232
2233 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2234 led_reg |= IXGBE_LED_BLINK(index);
2235 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2236 IXGBE_WRITE_FLUSH(hw);
2237
2238 return 0;
2239}
2240
2241/**
2242 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2243 * @hw: pointer to hardware structure
2244 * @index: led number to stop blinking
2245 **/
2246s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2247{
2248 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2249 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2250
2251 autoc_reg &= ~IXGBE_AUTOC_FLU;
2252 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2253 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2254
2255 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2256 led_reg &= ~IXGBE_LED_BLINK(index);
2257 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2258 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2259 IXGBE_WRITE_FLUSH(hw);
2260
2261 return 0;
2262}
21ce849b
MC		 2263
2264/**
2265 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2266 * @hw: pointer to hardware structure
2267 * @san_mac_offset: SAN MAC address offset
2268 *
2269 * This function will read the EEPROM location for the SAN MAC address
2270 * pointer, and returns the value at that location. This is used in both
2271 * get and set mac_addr routines.
2272 **/
2273static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2274 u16 *san_mac_offset)
2275{
2276 /*
2277 * First read the EEPROM pointer to see if the MAC addresses are
2278 * available.
2279 */
2280 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2281
2282 return 0;
2283}
2284
2285/**
2286 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2287 * @hw: pointer to hardware structure
2288 * @san_mac_addr: SAN MAC address
2289 *
2290 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2291 * per-port, so set_lan_id() must be called before reading the addresses.
2292 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2293 * upon for non-SFP connections, so we must call it here.
2294 **/
2295s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2296{
2297 u16 san_mac_data, san_mac_offset;
2298 u8 i;
2299
2300 /*
2301 * First read the EEPROM pointer to see if the MAC addresses are
2302 * available. If they're not, no point in calling set_lan_id() here.
2303 */
2304 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2305
2306 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2307 /*
2308 * No addresses available in this EEPROM. It's not an
2309 * error though, so just wipe the local address and return.
2310 */
2311 for (i = 0; i < 6; i++)
2312 san_mac_addr[i] = 0xFF;
2313
2314 goto san_mac_addr_out;
2315 }
2316
2317 /* make sure we know which port we need to program */
2318 hw->mac.ops.set_lan_id(hw);
2319 /* apply the port offset to the address offset */
2320 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2321 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2322 for (i = 0; i < 3; i++) {
2323 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2324 san_mac_addr[i * 2] = (u8)(san_mac_data);
2325 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2326 san_mac_offset++;
2327 }
2328
2329san_mac_addr_out:
2330 return 0;
2331}
2332
2333/**
2334 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2335 * @hw: pointer to hardware structure
2336 *
2337 * Read PCIe configuration space, and get the MSI-X vector count from
2338 * the capabilities table.
2339 **/
2340u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2341{
2342 struct ixgbe_adapter *adapter = hw->back;
2343 u16 msix_count;
2344 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
2345 &msix_count);
2346 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2347
2348 /* MSI-X count is zero-based in HW, so increment to give proper value */
2349 msix_count++;
2350
2351 return msix_count;
2352}
2353
2354/**
2355 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2356 * @hw: pointer to hardware struct
2357 * @rar: receive address register index to disassociate
2358 * @vmdq: VMDq pool index to remove from the rar
2359 **/
2360s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2361{
2362 u32 mpsar_lo, mpsar_hi;
2363 u32 rar_entries = hw->mac.num_rar_entries;
2364
2365 if (rar < rar_entries) {
2366 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2367 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2368
2369 if (!mpsar_lo && !mpsar_hi)
2370 goto done;
2371
2372 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2373 if (mpsar_lo) {
2374 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2375 mpsar_lo = 0;
2376 }
2377 if (mpsar_hi) {
2378 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2379 mpsar_hi = 0;
2380 }
2381 } else if (vmdq < 32) {
2382 mpsar_lo &= ~(1 << vmdq);
2383 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2384 } else {
2385 mpsar_hi &= ~(1 << (vmdq - 32));
2386 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2387 }
2388
2389 /* was that the last pool using this rar? */
2390 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2391 hw->mac.ops.clear_rar(hw, rar);
2392 } else {
2393 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2394 }
2395
2396done:
2397 return 0;
2398}
2399
2400/**
2401 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2402 * @hw: pointer to hardware struct
2403 * @rar: receive address register index to associate with a VMDq index
2404 * @vmdq: VMDq pool index
2405 **/
2406s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2407{
2408 u32 mpsar;
2409 u32 rar_entries = hw->mac.num_rar_entries;
2410
2411 if (rar < rar_entries) {
2412 if (vmdq < 32) {
2413 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2414 mpsar |= 1 << vmdq;
2415 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2416 } else {
2417 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2418 mpsar |= 1 << (vmdq - 32);
2419 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2420 }
2421 } else {
2422 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2423 }
2424 return 0;
2425}
2426
2427/**
2428 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2429 * @hw: pointer to hardware structure
2430 **/
2431s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2432{
2433 int i;
2434
2435
2436 for (i = 0; i < 128; i++)
2437 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2438
2439 return 0;
2440}
2441
2442/**
2443 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2444 * @hw: pointer to hardware structure
2445 * @vlan: VLAN id to write to VLAN filter
2446 *
2447 * return the VLVF index where this VLAN id should be placed
2448 *
2449 **/
2450s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
2451{
2452 u32 bits = 0;
2453 u32 first_empty_slot = 0;
2454 s32 regindex;
2455
2456 /* short cut the special case */
2457 if (vlan == 0)
2458 return 0;
2459
2460 /*
2461 * Search for the vlan id in the VLVF entries. Save off the first empty
2462 * slot found along the way
2463 */
2464 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2465 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2466 if (!bits && !(first_empty_slot))
2467 first_empty_slot = regindex;
2468 else if ((bits & 0x0FFF) == vlan)
2469 break;
2470 }
2471
2472 /*
2473 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2474 * in the VLVF. Else use the first empty VLVF register for this
2475 * vlan id.
2476 */
2477 if (regindex >= IXGBE_VLVF_ENTRIES) {
2478 if (first_empty_slot)
2479 regindex = first_empty_slot;
2480 else {
2481 hw_dbg(hw, "No space in VLVF.\n");
2482 regindex = IXGBE_ERR_NO_SPACE;
2483 }
2484 }
2485
2486 return regindex;
2487}
2488
2489/**
2490 * ixgbe_set_vfta_generic - Set VLAN filter table
2491 * @hw: pointer to hardware structure
2492 * @vlan: VLAN id to write to VLAN filter
2493 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2494 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2495 *
2496 * Turn on/off specified VLAN in the VLAN filter table.
2497 **/
2498s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
2499 bool vlan_on)
2500{
2501 s32 regindex;
2502 u32 bitindex;
2503 u32 vfta;
2504 u32 bits;
2505 u32 vt;
2506 u32 targetbit;
2507 bool vfta_changed = false;
2508
2509 if (vlan > 4095)
2510 return IXGBE_ERR_PARAM;
2511
2512 /*
2513 * this is a 2 part operation - first the VFTA, then the
2514 * VLVF and VLVFB if VT Mode is set
2515 * We don't write the VFTA until we know the VLVF part succeeded.
2516 */
2517
2518 /* Part 1
2519 * The VFTA is a bitstring made up of 128 32-bit registers
2520 * that enable the particular VLAN id, much like the MTA:
2521 * bits[11-5]: which register
2522 * bits[4-0]: which bit in the register
2523 */
2524 regindex = (vlan >> 5) & 0x7F;
2525 bitindex = vlan & 0x1F;
2526 targetbit = (1 << bitindex);
2527 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
2528
2529 if (vlan_on) {
2530 if (!(vfta & targetbit)) {
2531 vfta |= targetbit;
2532 vfta_changed = true;
2533 }
2534 } else {
2535 if ((vfta & targetbit)) {
2536 vfta &= ~targetbit;
2537 vfta_changed = true;
2538 }
2539 }
2540
2541 /* Part 2
2542 * If VT Mode is set
2543 * Either vlan_on
2544 * make sure the vlan is in VLVF
2545 * set the vind bit in the matching VLVFB
2546 * Or !vlan_on
2547 * clear the pool bit and possibly the vind
2548 */
2549 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2550 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
2551 s32 vlvf_index;
2552
2553 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
2554 if (vlvf_index < 0)
2555 return vlvf_index;
2556
2557 if (vlan_on) {
2558 /* set the pool bit */
2559 if (vind < 32) {
2560 bits = IXGBE_READ_REG(hw,
2561 IXGBE_VLVFB(vlvf_index*2));
2562 bits |= (1 << vind);
2563 IXGBE_WRITE_REG(hw,
2564 IXGBE_VLVFB(vlvf_index*2),
2565 bits);
2566 } else {
2567 bits = IXGBE_READ_REG(hw,
2568 IXGBE_VLVFB((vlvf_index*2)+1));
2569 bits |= (1 << (vind-32));
2570 IXGBE_WRITE_REG(hw,
2571 IXGBE_VLVFB((vlvf_index*2)+1),
2572 bits);
2573 }
2574 } else {
2575 /* clear the pool bit */
2576 if (vind < 32) {
2577 bits = IXGBE_READ_REG(hw,
2578 IXGBE_VLVFB(vlvf_index*2));
2579 bits &= ~(1 << vind);
2580 IXGBE_WRITE_REG(hw,
2581 IXGBE_VLVFB(vlvf_index*2),
2582 bits);
2583 bits |= IXGBE_READ_REG(hw,
2584 IXGBE_VLVFB((vlvf_index*2)+1));
2585 } else {
2586 bits = IXGBE_READ_REG(hw,
2587 IXGBE_VLVFB((vlvf_index*2)+1));
2588 bits &= ~(1 << (vind-32));
2589 IXGBE_WRITE_REG(hw,
2590 IXGBE_VLVFB((vlvf_index*2)+1),
2591 bits);
2592 bits |= IXGBE_READ_REG(hw,
2593 IXGBE_VLVFB(vlvf_index*2));
2594 }
2595 }
2596
2597 /*
2598 * If there are still bits set in the VLVFB registers
2599 * for the VLAN ID indicated we need to see if the
2600 * caller is requesting that we clear the VFTA entry bit.
2601 * If the caller has requested that we clear the VFTA
2602 * entry bit but there are still pools/VFs using this VLAN
2603 * ID entry then ignore the request. We're not worried
2604 * about the case where we're turning the VFTA VLAN ID
2605 * entry bit on, only when requested to turn it off as
2606 * there may be multiple pools and/or VFs using the
2607 * VLAN ID entry. In that case we cannot clear the
2608 * VFTA bit until all pools/VFs using that VLAN ID have also
2609 * been cleared. This will be indicated by "bits" being
2610 * zero.
2611 */
2612 if (bits) {
2613 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
2614 (IXGBE_VLVF_VIEN | vlan));
2615 if (!vlan_on) {
2616 /* someone wants to clear the vfta entry
2617 * but some pools/VFs are still using it.
2618 * Ignore it. */
2619 vfta_changed = false;
2620 }
2621 }
2622 else
2623 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
2624 }
2625
2626 if (vfta_changed)
2627 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
2628
2629 return 0;
2630}
2631
2632/**
2633 * ixgbe_clear_vfta_generic - Clear VLAN filter table
2634 * @hw: pointer to hardware structure
2635 *
2636 * Clears the VLAN filer table, and the VMDq index associated with the filter
2637 **/
2638s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
2639{
2640 u32 offset;
2641
2642 for (offset = 0; offset < hw->mac.vft_size; offset++)
2643 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
2644
2645 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
2646 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
2647 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
2648 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
2649 }
2650
2651 return 0;
2652}
2653
2654/**
2655 * ixgbe_check_mac_link_generic - Determine link and speed status
2656 * @hw: pointer to hardware structure
2657 * @speed: pointer to link speed
2658 * @link_up: true when link is up
2659 * @link_up_wait_to_complete: bool used to wait for link up or not
2660 *
2661 * Reads the links register to determine if link is up and the current speed
2662 **/
2663s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2664 bool *link_up, bool link_up_wait_to_complete)
2665{
2666 u32 links_reg;
2667 u32 i;
2668
2669 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2670 if (link_up_wait_to_complete) {
2671 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
2672 if (links_reg & IXGBE_LINKS_UP) {
2673 *link_up = true;
2674 break;
2675 } else {
2676 *link_up = false;
2677 }
2678 msleep(100);
2679 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2680 }
2681 } else {
2682 if (links_reg & IXGBE_LINKS_UP)
2683 *link_up = true;
2684 else
2685 *link_up = false;
2686 }
2687
2688 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2689 IXGBE_LINKS_SPEED_10G_82599)
2690 *speed = IXGBE_LINK_SPEED_10GB_FULL;
2691 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2692 IXGBE_LINKS_SPEED_1G_82599)
2693 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2694 else
2695 *speed = IXGBE_LINK_SPEED_100_FULL;
2696
2697 /* if link is down, zero out the current_mode */
2698 if (*link_up == false) {
2699 hw->fc.current_mode = ixgbe_fc_none;
2700 hw->fc.fc_was_autonegged = false;
2701 }
2702
2703 return 0;
2704}
2705
2706/**
2707 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
2708 * the EEPROM
2709 * @hw: pointer to hardware structure
2710 * @wwnn_prefix: the alternative WWNN prefix
2711 * @wwpn_prefix: the alternative WWPN prefix
2712 *
2713 * This function will read the EEPROM from the alternative SAN MAC address
2714 * block to check the support for the alternative WWNN/WWPN prefix support.
2715 **/
2716s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2717 u16 *wwpn_prefix)
2718{
2719 u16 offset, caps;
2720 u16 alt_san_mac_blk_offset;
2721
2722 /* clear output first */
2723 *wwnn_prefix = 0xFFFF;
2724 *wwpn_prefix = 0xFFFF;
2725
2726 /* check if alternative SAN MAC is supported */
2727 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2728 &alt_san_mac_blk_offset);
2729
2730 if ((alt_san_mac_blk_offset == 0) ||
2731 (alt_san_mac_blk_offset == 0xFFFF))
2732 goto wwn_prefix_out;
2733
2734 /* check capability in alternative san mac address block */
2735 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2736 hw->eeprom.ops.read(hw, offset, &caps);
2737 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2738 goto wwn_prefix_out;
2739
2740 /* get the corresponding prefix for WWNN/WWPN */
2741 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2742 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2743
2744 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2745 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2746
2747wwn_prefix_out:
2748 return 0;
2749}
Linux kernel - Deliverables
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