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Merge 2.6.38-rc5 into staging-next
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
ccffad25 31#include <linux/netdevice.h>
9a799d71 32
11afc1b1 33#include "ixgbe.h"
9a799d71
AK		 34#include "ixgbe_common.h"
35#include "ixgbe_phy.h"
36
c44ade9e 37static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 38static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 40static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
43 u16 count);
44static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71 48
c44ade9e
JB		 49static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
50static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
9a799d71 51static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
c44ade9e 52static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
7b25cdba 53static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
9a799d71
AK		 54
55/**
c44ade9e 56 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 57 * @hw: pointer to hardware structure
58 *
59 * Starts the hardware by filling the bus info structure and media type, clears
60 * all on chip counters, initializes receive address registers, multicast
61 * table, VLAN filter table, calls routine to set up link and flow control
62 * settings, and leaves transmit and receive units disabled and uninitialized
63 **/
c44ade9e 64s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71
AK		 65{
66 u32 ctrl_ext;
67
68 /* Set the media type */
69 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
70
71 /* Identify the PHY */
c44ade9e 72 hw->phy.ops.identify(hw);
9a799d71 73
9a799d71 74 /* Clear the VLAN filter table */
c44ade9e 75 hw->mac.ops.clear_vfta(hw);
9a799d71 76
9a799d71 77 /* Clear statistics registers */
c44ade9e 78 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 79
80 /* Set No Snoop Disable */
81 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
82 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
83 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 84 IXGBE_WRITE_FLUSH(hw);
9a799d71 85
620fa036
MC		 86 /* Setup flow control */
87 ixgbe_setup_fc(hw, 0);
88
9a799d71
AK		 89 /* Clear adapter stopped flag */
90 hw->adapter_stopped = false;
91
92 return 0;
93}
94
95/**
c44ade9e 96 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 97 * @hw: pointer to hardware structure
98 *
c44ade9e 99 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 100 * structure and media type, clears all on chip counters, initializes receive
101 * address registers, multicast table, VLAN filter table, calls routine to set
102 * up link and flow control settings, and leaves transmit and receive units
103 * disabled and uninitialized
104 **/
c44ade9e 105s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 106{
794caeb2
PWJ		 107 s32 status;
108
9a799d71 109 /* Reset the hardware */
794caeb2 110 status = hw->mac.ops.reset_hw(hw);
9a799d71 111
794caeb2
PWJ		 112 if (status == 0) {
113 /* Start the HW */
114 status = hw->mac.ops.start_hw(hw);
115 }
9a799d71 116
794caeb2 117 return status;
9a799d71
AK		 118}
119
120/**
c44ade9e 121 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 122 * @hw: pointer to hardware structure
123 *
124 * Clears all hardware statistics counters by reading them from the hardware
125 * Statistics counters are clear on read.
126 **/
c44ade9e 127s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 128{
129 u16 i = 0;
130
131 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
132 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
133 IXGBE_READ_REG(hw, IXGBE_ERRBC);
134 IXGBE_READ_REG(hw, IXGBE_MSPDC);
135 for (i = 0; i < 8; i++)
136 IXGBE_READ_REG(hw, IXGBE_MPC(i));
137
138 IXGBE_READ_REG(hw, IXGBE_MLFC);
139 IXGBE_READ_REG(hw, IXGBE_MRFC);
140 IXGBE_READ_REG(hw, IXGBE_RLEC);
141 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
142 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
143 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
144 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
145
146 for (i = 0; i < 8; i++) {
147 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
148 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
149 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
150 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
151 }
152
153 IXGBE_READ_REG(hw, IXGBE_PRC64);
154 IXGBE_READ_REG(hw, IXGBE_PRC127);
155 IXGBE_READ_REG(hw, IXGBE_PRC255);
156 IXGBE_READ_REG(hw, IXGBE_PRC511);
157 IXGBE_READ_REG(hw, IXGBE_PRC1023);
158 IXGBE_READ_REG(hw, IXGBE_PRC1522);
159 IXGBE_READ_REG(hw, IXGBE_GPRC);
160 IXGBE_READ_REG(hw, IXGBE_BPRC);
161 IXGBE_READ_REG(hw, IXGBE_MPRC);
162 IXGBE_READ_REG(hw, IXGBE_GPTC);
163 IXGBE_READ_REG(hw, IXGBE_GORCL);
164 IXGBE_READ_REG(hw, IXGBE_GORCH);
165 IXGBE_READ_REG(hw, IXGBE_GOTCL);
166 IXGBE_READ_REG(hw, IXGBE_GOTCH);
167 for (i = 0; i < 8; i++)
168 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
169 IXGBE_READ_REG(hw, IXGBE_RUC);
170 IXGBE_READ_REG(hw, IXGBE_RFC);
171 IXGBE_READ_REG(hw, IXGBE_ROC);
172 IXGBE_READ_REG(hw, IXGBE_RJC);
173 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
174 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
175 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
176 IXGBE_READ_REG(hw, IXGBE_TORL);
177 IXGBE_READ_REG(hw, IXGBE_TORH);
178 IXGBE_READ_REG(hw, IXGBE_TPR);
179 IXGBE_READ_REG(hw, IXGBE_TPT);
180 IXGBE_READ_REG(hw, IXGBE_PTC64);
181 IXGBE_READ_REG(hw, IXGBE_PTC127);
182 IXGBE_READ_REG(hw, IXGBE_PTC255);
183 IXGBE_READ_REG(hw, IXGBE_PTC511);
184 IXGBE_READ_REG(hw, IXGBE_PTC1023);
185 IXGBE_READ_REG(hw, IXGBE_PTC1522);
186 IXGBE_READ_REG(hw, IXGBE_MPTC);
187 IXGBE_READ_REG(hw, IXGBE_BPTC);
188 for (i = 0; i < 16; i++) {
189 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
190 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
191 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
192 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
193 }
194
195 return 0;
196}
197
198/**
289700db 199 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
c44ade9e 200 * @hw: pointer to hardware structure
289700db
DS		 201 * @pba_num: stores the part number string from the EEPROM
202 * @pba_num_size: part number string buffer length
c44ade9e 203 *
289700db 204 * Reads the part number string from the EEPROM.
c44ade9e 205 **/
289700db
DS		 206s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
207 u32 pba_num_size)
c44ade9e
JB		 208{
209 s32 ret_val;
210 u16 data;
289700db
DS		 211 u16 pba_ptr;
212 u16 offset;
213 u16 length;
214
215 if (pba_num == NULL) {
216 hw_dbg(hw, "PBA string buffer was null\n");
217 return IXGBE_ERR_INVALID_ARGUMENT;
218 }
c44ade9e
JB		 219
220 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
221 if (ret_val) {
222 hw_dbg(hw, "NVM Read Error\n");
223 return ret_val;
224 }
c44ade9e 225
289700db 226 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
c44ade9e
JB		 227 if (ret_val) {
228 hw_dbg(hw, "NVM Read Error\n");
229 return ret_val;
230 }
289700db
DS		 231
232 /*
233 * if data is not ptr guard the PBA must be in legacy format which
234 * means pba_ptr is actually our second data word for the PBA number
235 * and we can decode it into an ascii string
236 */
237 if (data != IXGBE_PBANUM_PTR_GUARD) {
238 hw_dbg(hw, "NVM PBA number is not stored as string\n");
239
240 /* we will need 11 characters to store the PBA */
241 if (pba_num_size < 11) {
242 hw_dbg(hw, "PBA string buffer too small\n");
243 return IXGBE_ERR_NO_SPACE;
244 }
245
246 /* extract hex string from data and pba_ptr */
247 pba_num[0] = (data >> 12) & 0xF;
248 pba_num[1] = (data >> 8) & 0xF;
249 pba_num[2] = (data >> 4) & 0xF;
250 pba_num[3] = data & 0xF;
251 pba_num[4] = (pba_ptr >> 12) & 0xF;
252 pba_num[5] = (pba_ptr >> 8) & 0xF;
253 pba_num[6] = '-';
254 pba_num[7] = 0;
255 pba_num[8] = (pba_ptr >> 4) & 0xF;
256 pba_num[9] = pba_ptr & 0xF;
257
258 /* put a null character on the end of our string */
259 pba_num[10] = '\0';
260
261 /* switch all the data but the '-' to hex char */
262 for (offset = 0; offset < 10; offset++) {
263 if (pba_num[offset] < 0xA)
264 pba_num[offset] += '0';
265 else if (pba_num[offset] < 0x10)
266 pba_num[offset] += 'A' - 0xA;
267 }
268
269 return 0;
270 }
271
272 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
273 if (ret_val) {
274 hw_dbg(hw, "NVM Read Error\n");
275 return ret_val;
276 }
277
278 if (length == 0xFFFF || length == 0) {
279 hw_dbg(hw, "NVM PBA number section invalid length\n");
280 return IXGBE_ERR_PBA_SECTION;
281 }
282
283 /* check if pba_num buffer is big enough */
284 if (pba_num_size < (((u32)length * 2) - 1)) {
285 hw_dbg(hw, "PBA string buffer too small\n");
286 return IXGBE_ERR_NO_SPACE;
287 }
288
289 /* trim pba length from start of string */
290 pba_ptr++;
291 length--;
292
293 for (offset = 0; offset < length; offset++) {
294 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
295 if (ret_val) {
296 hw_dbg(hw, "NVM Read Error\n");
297 return ret_val;
298 }
299 pba_num[offset * 2] = (u8)(data >> 8);
300 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
301 }
302 pba_num[offset * 2] = '\0';
c44ade9e
JB		 303
304 return 0;
305}
306
307/**
308 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 309 * @hw: pointer to hardware structure
310 * @mac_addr: Adapter MAC address
311 *
312 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
313 * A reset of the adapter must be performed prior to calling this function
314 * in order for the MAC address to have been loaded from the EEPROM into RAR0
315 **/
c44ade9e 316s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 317{
318 u32 rar_high;
319 u32 rar_low;
320 u16 i;
321
322 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
323 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
324
325 for (i = 0; i < 4; i++)
326 mac_addr[i] = (u8)(rar_low >> (i*8));
327
328 for (i = 0; i < 2; i++)
329 mac_addr[i+4] = (u8)(rar_high >> (i*8));
330
331 return 0;
332}
333
11afc1b1
PW		 334/**
335 * ixgbe_get_bus_info_generic - Generic set PCI bus info
336 * @hw: pointer to hardware structure
337 *
338 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
339 **/
340s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
341{
342 struct ixgbe_adapter *adapter = hw->back;
343 struct ixgbe_mac_info *mac = &hw->mac;
344 u16 link_status;
345
346 hw->bus.type = ixgbe_bus_type_pci_express;
347
348 /* Get the negotiated link width and speed from PCI config space */
349 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
350 &link_status);
351
352 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
353 case IXGBE_PCI_LINK_WIDTH_1:
354 hw->bus.width = ixgbe_bus_width_pcie_x1;
355 break;
356 case IXGBE_PCI_LINK_WIDTH_2:
357 hw->bus.width = ixgbe_bus_width_pcie_x2;
358 break;
359 case IXGBE_PCI_LINK_WIDTH_4:
360 hw->bus.width = ixgbe_bus_width_pcie_x4;
361 break;
362 case IXGBE_PCI_LINK_WIDTH_8:
363 hw->bus.width = ixgbe_bus_width_pcie_x8;
364 break;
365 default:
366 hw->bus.width = ixgbe_bus_width_unknown;
367 break;
368 }
369
370 switch (link_status & IXGBE_PCI_LINK_SPEED) {
371 case IXGBE_PCI_LINK_SPEED_2500:
372 hw->bus.speed = ixgbe_bus_speed_2500;
373 break;
374 case IXGBE_PCI_LINK_SPEED_5000:
375 hw->bus.speed = ixgbe_bus_speed_5000;
376 break;
377 default:
378 hw->bus.speed = ixgbe_bus_speed_unknown;
379 break;
380 }
381
382 mac->ops.set_lan_id(hw);
383
384 return 0;
385}
386
387/**
388 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
389 * @hw: pointer to the HW structure
390 *
391 * Determines the LAN function id by reading memory-mapped registers
392 * and swaps the port value if requested.
393 **/
394void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
395{
396 struct ixgbe_bus_info *bus = &hw->bus;
397 u32 reg;
398
399 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
400 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
401 bus->lan_id = bus->func;
402
403 /* check for a port swap */
404 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
405 if (reg & IXGBE_FACTPS_LFS)
406 bus->func ^= 0x1;
407}
408
9a799d71 409/**
c44ade9e 410 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 411 * @hw: pointer to hardware structure
412 *
413 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
414 * disables transmit and receive units. The adapter_stopped flag is used by
415 * the shared code and drivers to determine if the adapter is in a stopped
416 * state and should not touch the hardware.
417 **/
c44ade9e 418s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71
AK		 419{
420 u32 number_of_queues;
421 u32 reg_val;
422 u16 i;
423
424 /*
425 * Set the adapter_stopped flag so other driver functions stop touching
426 * the hardware
427 */
428 hw->adapter_stopped = true;
429
430 /* Disable the receive unit */
431 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
432 reg_val &= ~(IXGBE_RXCTRL_RXEN);
433 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
c44ade9e 434 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 435 msleep(2);
436
437 /* Clear interrupt mask to stop from interrupts being generated */
438 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
439
440 /* Clear any pending interrupts */
441 IXGBE_READ_REG(hw, IXGBE_EICR);
442
443 /* Disable the transmit unit. Each queue must be disabled. */
c44ade9e 444 number_of_queues = hw->mac.max_tx_queues;
9a799d71
AK		 445 for (i = 0; i < number_of_queues; i++) {
446 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
447 if (reg_val & IXGBE_TXDCTL_ENABLE) {
448 reg_val &= ~IXGBE_TXDCTL_ENABLE;
449 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
450 }
451 }
452
c44ade9e
JB		 453 /*
454 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
455 * access and verify no pending requests
456 */
457 if (ixgbe_disable_pcie_master(hw) != 0)
458 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
459
9a799d71
AK		 460 return 0;
461}
462
463/**
c44ade9e 464 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 465 * @hw: pointer to hardware structure
466 * @index: led number to turn on
467 **/
c44ade9e 468s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 469{
470 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
471
472 /* To turn on the LED, set mode to ON. */
473 led_reg &= ~IXGBE_LED_MODE_MASK(index);
474 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
475 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 476 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 477
478 return 0;
479}
480
481/**
c44ade9e 482 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 483 * @hw: pointer to hardware structure
484 * @index: led number to turn off
485 **/
c44ade9e 486s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 487{
488 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
489
490 /* To turn off the LED, set mode to OFF. */
491 led_reg &= ~IXGBE_LED_MODE_MASK(index);
492 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
493 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 494 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 495
496 return 0;
497}
498
9a799d71 499/**
c44ade9e 500 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 501 * @hw: pointer to hardware structure
502 *
503 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
504 * ixgbe_hw struct in order to set up EEPROM access.
505 **/
c44ade9e 506s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 507{
508 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
509 u32 eec;
510 u16 eeprom_size;
511
512 if (eeprom->type == ixgbe_eeprom_uninitialized) {
513 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 514 /* Set default semaphore delay to 10ms which is a well
515 * tested value */
516 eeprom->semaphore_delay = 10;
9a799d71
AK		 517
518 /*
519 * Check for EEPROM present first.
520 * If not present leave as none
521 */
522 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
523 if (eec & IXGBE_EEC_PRES) {
524 eeprom->type = ixgbe_eeprom_spi;
525
526 /*
527 * SPI EEPROM is assumed here. This code would need to
528 * change if a future EEPROM is not SPI.
529 */
530 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
531 IXGBE_EEC_SIZE_SHIFT);
532 eeprom->word_size = 1 << (eeprom_size +
533 IXGBE_EEPROM_WORD_SIZE_SHIFT);
534 }
535
536 if (eec & IXGBE_EEC_ADDR_SIZE)
537 eeprom->address_bits = 16;
538 else
539 eeprom->address_bits = 8;
540 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
541 "%d\n", eeprom->type, eeprom->word_size,
542 eeprom->address_bits);
543 }
544
545 return 0;
546}
547
11afc1b1
PW		 548/**
549 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
550 * @hw: pointer to hardware structure
551 * @offset: offset within the EEPROM to be written to
552 * @data: 16 bit word to be written to the EEPROM
553 *
554 * If ixgbe_eeprom_update_checksum is not called after this function, the
555 * EEPROM will most likely contain an invalid checksum.
556 **/
557s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
558{
559 s32 status;
560 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
561
562 hw->eeprom.ops.init_params(hw);
563
564 if (offset >= hw->eeprom.word_size) {
565 status = IXGBE_ERR_EEPROM;
566 goto out;
567 }
568
569 /* Prepare the EEPROM for writing */
570 status = ixgbe_acquire_eeprom(hw);
571
572 if (status == 0) {
573 if (ixgbe_ready_eeprom(hw) != 0) {
574 ixgbe_release_eeprom(hw);
575 status = IXGBE_ERR_EEPROM;
576 }
577 }
578
579 if (status == 0) {
580 ixgbe_standby_eeprom(hw);
581
582 /* Send the WRITE ENABLE command (8 bit opcode ) */
583 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
584 IXGBE_EEPROM_OPCODE_BITS);
585
586 ixgbe_standby_eeprom(hw);
587
588 /*
589 * Some SPI eeproms use the 8th address bit embedded in the
590 * opcode
591 */
592 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
593 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
594
595 /* Send the Write command (8-bit opcode + addr) */
596 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
597 IXGBE_EEPROM_OPCODE_BITS);
598 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
599 hw->eeprom.address_bits);
600
601 /* Send the data */
602 data = (data >> 8) | (data << 8);
603 ixgbe_shift_out_eeprom_bits(hw, data, 16);
604 ixgbe_standby_eeprom(hw);
605
606 msleep(hw->eeprom.semaphore_delay);
607 /* Done with writing - release the EEPROM */
608 ixgbe_release_eeprom(hw);
609 }
610
611out:
612 return status;
613}
614
9a799d71 615/**
c44ade9e
JB		 616 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
617 * @hw: pointer to hardware structure
618 * @offset: offset within the EEPROM to be read
619 * @data: read 16 bit value from EEPROM
620 *
621 * Reads 16 bit value from EEPROM through bit-bang method
622 **/
623s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
624 u16 *data)
625{
626 s32 status;
627 u16 word_in;
628 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
629
630 hw->eeprom.ops.init_params(hw);
631
632 if (offset >= hw->eeprom.word_size) {
633 status = IXGBE_ERR_EEPROM;
634 goto out;
635 }
636
637 /* Prepare the EEPROM for reading */
638 status = ixgbe_acquire_eeprom(hw);
639
640 if (status == 0) {
641 if (ixgbe_ready_eeprom(hw) != 0) {
642 ixgbe_release_eeprom(hw);
643 status = IXGBE_ERR_EEPROM;
644 }
645 }
646
647 if (status == 0) {
648 ixgbe_standby_eeprom(hw);
649
650 /*
651 * Some SPI eeproms use the 8th address bit embedded in the
652 * opcode
653 */
654 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
655 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
656
657 /* Send the READ command (opcode + addr) */
658 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
659 IXGBE_EEPROM_OPCODE_BITS);
660 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
661 hw->eeprom.address_bits);
662
663 /* Read the data. */
664 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
665 *data = (word_in >> 8) | (word_in << 8);
666
667 /* End this read operation */
668 ixgbe_release_eeprom(hw);
669 }
670
671out:
672 return status;
673}
674
675/**
21ce849b 676 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
9a799d71
AK		 677 * @hw: pointer to hardware structure
678 * @offset: offset of word in the EEPROM to read
679 * @data: word read from the EEPROM
680 *
681 * Reads a 16 bit word from the EEPROM using the EERD register.
682 **/
21ce849b 683s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
9a799d71
AK		 684{
685 u32 eerd;
686 s32 status;
687
c44ade9e
JB		 688 hw->eeprom.ops.init_params(hw);
689
690 if (offset >= hw->eeprom.word_size) {
691 status = IXGBE_ERR_EEPROM;
692 goto out;
693 }
694
21ce849b
MC		 695 eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) +
696 IXGBE_EEPROM_RW_REG_START;
9a799d71
AK		 697
698 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
21ce849b 699 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
9a799d71
AK		 700
701 if (status == 0)
702 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
21ce849b 703 IXGBE_EEPROM_RW_REG_DATA);
9a799d71
AK		 704 else
705 hw_dbg(hw, "Eeprom read timed out\n");
706
c44ade9e 707out:
9a799d71
AK		 708 return status;
709}
710
711/**
21ce849b 712 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
9a799d71 713 * @hw: pointer to hardware structure
21ce849b 714 * @ee_reg: EEPROM flag for polling
9a799d71 715 *
21ce849b
MC		 716 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
717 * read or write is done respectively.
9a799d71 718 **/
a391f1d5 719s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
9a799d71
AK		 720{
721 u32 i;
722 u32 reg;
723 s32 status = IXGBE_ERR_EEPROM;
724
21ce849b
MC		 725 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
726 if (ee_reg == IXGBE_NVM_POLL_READ)
727 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
728 else
729 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
730
731 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
9a799d71
AK		 732 status = 0;
733 break;
734 }
735 udelay(5);
736 }
737 return status;
738}
739
c44ade9e
JB		 740/**
741 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
742 * @hw: pointer to hardware structure
743 *
744 * Prepares EEPROM for access using bit-bang method. This function should
745 * be called before issuing a command to the EEPROM.
746 **/
747static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
748{
749 s32 status = 0;
fc1f2095 750 u32 eec = 0;
c44ade9e
JB		 751 u32 i;
752
753 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
754 status = IXGBE_ERR_SWFW_SYNC;
755
756 if (status == 0) {
757 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
758
759 /* Request EEPROM Access */
760 eec |= IXGBE_EEC_REQ;
761 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
762
763 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
764 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
765 if (eec & IXGBE_EEC_GNT)
766 break;
767 udelay(5);
768 }
769
770 /* Release if grant not acquired */
771 if (!(eec & IXGBE_EEC_GNT)) {
772 eec &= ~IXGBE_EEC_REQ;
773 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
774 hw_dbg(hw, "Could not acquire EEPROM grant\n");
775
776 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
777 status = IXGBE_ERR_EEPROM;
778 }
779 }
780
781 /* Setup EEPROM for Read/Write */
782 if (status == 0) {
783 /* Clear CS and SK */
784 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
785 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
786 IXGBE_WRITE_FLUSH(hw);
787 udelay(1);
788 }
789 return status;
790}
791
9a799d71
AK		 792/**
793 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
794 * @hw: pointer to hardware structure
795 *
796 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
797 **/
798static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
799{
800 s32 status = IXGBE_ERR_EEPROM;
801 u32 timeout;
802 u32 i;
803 u32 swsm;
804
805 /* Set timeout value based on size of EEPROM */
806 timeout = hw->eeprom.word_size + 1;
807
808 /* Get SMBI software semaphore between device drivers first */
809 for (i = 0; i < timeout; i++) {
810 /*
811 * If the SMBI bit is 0 when we read it, then the bit will be
812 * set and we have the semaphore
813 */
814 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
815 if (!(swsm & IXGBE_SWSM_SMBI)) {
816 status = 0;
817 break;
818 }
819 msleep(1);
820 }
821
822 /* Now get the semaphore between SW/FW through the SWESMBI bit */
823 if (status == 0) {
824 for (i = 0; i < timeout; i++) {
825 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
826
827 /* Set the SW EEPROM semaphore bit to request access */
828 swsm |= IXGBE_SWSM_SWESMBI;
829 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
830
831 /*
832 * If we set the bit successfully then we got the
833 * semaphore.
834 */
835 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
836 if (swsm & IXGBE_SWSM_SWESMBI)
837 break;
838
839 udelay(50);
840 }
841
842 /*
843 * Release semaphores and return error if SW EEPROM semaphore
844 * was not granted because we don't have access to the EEPROM
845 */
846 if (i >= timeout) {
847 hw_dbg(hw, "Driver can't access the Eeprom - Semaphore "
b4617240 848 "not granted.\n");
9a799d71
AK		 849 ixgbe_release_eeprom_semaphore(hw);
850 status = IXGBE_ERR_EEPROM;
851 }
852 }
853
854 return status;
855}
856
857/**
858 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
859 * @hw: pointer to hardware structure
860 *
861 * This function clears hardware semaphore bits.
862 **/
863static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
864{
865 u32 swsm;
866
867 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
868
869 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
870 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
871 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
3957d63d 872 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 873}
874
c44ade9e
JB		 875/**
876 * ixgbe_ready_eeprom - Polls for EEPROM ready
877 * @hw: pointer to hardware structure
878 **/
879static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
880{
881 s32 status = 0;
882 u16 i;
883 u8 spi_stat_reg;
884
885 /*
886 * Read "Status Register" repeatedly until the LSB is cleared. The
887 * EEPROM will signal that the command has been completed by clearing
888 * bit 0 of the internal status register. If it's not cleared within
889 * 5 milliseconds, then error out.
890 */
891 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
892 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
893 IXGBE_EEPROM_OPCODE_BITS);
894 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
895 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
896 break;
897
898 udelay(5);
899 ixgbe_standby_eeprom(hw);
900 };
901
902 /*
903 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
904 * devices (and only 0-5mSec on 5V devices)
905 */
906 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
907 hw_dbg(hw, "SPI EEPROM Status error\n");
908 status = IXGBE_ERR_EEPROM;
909 }
910
911 return status;
912}
913
914/**
915 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
916 * @hw: pointer to hardware structure
917 **/
918static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
919{
920 u32 eec;
921
922 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
923
924 /* Toggle CS to flush commands */
925 eec |= IXGBE_EEC_CS;
926 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
927 IXGBE_WRITE_FLUSH(hw);
928 udelay(1);
929 eec &= ~IXGBE_EEC_CS;
930 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
931 IXGBE_WRITE_FLUSH(hw);
932 udelay(1);
933}
934
935/**
936 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
937 * @hw: pointer to hardware structure
938 * @data: data to send to the EEPROM
939 * @count: number of bits to shift out
940 **/
941static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
942 u16 count)
943{
944 u32 eec;
945 u32 mask;
946 u32 i;
947
948 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
949
950 /*
951 * Mask is used to shift "count" bits of "data" out to the EEPROM
952 * one bit at a time. Determine the starting bit based on count
953 */
954 mask = 0x01 << (count - 1);
955
956 for (i = 0; i < count; i++) {
957 /*
958 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
959 * "1", and then raising and then lowering the clock (the SK
960 * bit controls the clock input to the EEPROM). A "0" is
961 * shifted out to the EEPROM by setting "DI" to "0" and then
962 * raising and then lowering the clock.
963 */
964 if (data & mask)
965 eec |= IXGBE_EEC_DI;
966 else
967 eec &= ~IXGBE_EEC_DI;
968
969 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
970 IXGBE_WRITE_FLUSH(hw);
971
972 udelay(1);
973
974 ixgbe_raise_eeprom_clk(hw, &eec);
975 ixgbe_lower_eeprom_clk(hw, &eec);
976
977 /*
978 * Shift mask to signify next bit of data to shift in to the
979 * EEPROM
980 */
981 mask = mask >> 1;
982 };
983
984 /* We leave the "DI" bit set to "0" when we leave this routine. */
985 eec &= ~IXGBE_EEC_DI;
986 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
987 IXGBE_WRITE_FLUSH(hw);
988}
989
990/**
991 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
992 * @hw: pointer to hardware structure
993 **/
994static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
995{
996 u32 eec;
997 u32 i;
998 u16 data = 0;
999
1000 /*
1001 * In order to read a register from the EEPROM, we need to shift
1002 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1003 * the clock input to the EEPROM (setting the SK bit), and then reading
1004 * the value of the "DO" bit. During this "shifting in" process the
1005 * "DI" bit should always be clear.
1006 */
1007 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1008
1009 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1010
1011 for (i = 0; i < count; i++) {
1012 data = data << 1;
1013 ixgbe_raise_eeprom_clk(hw, &eec);
1014
1015 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1016
1017 eec &= ~(IXGBE_EEC_DI);
1018 if (eec & IXGBE_EEC_DO)
1019 data |= 1;
1020
1021 ixgbe_lower_eeprom_clk(hw, &eec);
1022 }
1023
1024 return data;
1025}
1026
1027/**
1028 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1029 * @hw: pointer to hardware structure
1030 * @eec: EEC register's current value
1031 **/
1032static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1033{
1034 /*
1035 * Raise the clock input to the EEPROM
1036 * (setting the SK bit), then delay
1037 */
1038 *eec = *eec | IXGBE_EEC_SK;
1039 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1040 IXGBE_WRITE_FLUSH(hw);
1041 udelay(1);
1042}
1043
1044/**
1045 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1046 * @hw: pointer to hardware structure
1047 * @eecd: EECD's current value
1048 **/
1049static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1050{
1051 /*
1052 * Lower the clock input to the EEPROM (clearing the SK bit), then
1053 * delay
1054 */
1055 *eec = *eec & ~IXGBE_EEC_SK;
1056 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1057 IXGBE_WRITE_FLUSH(hw);
1058 udelay(1);
1059}
1060
1061/**
1062 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1063 * @hw: pointer to hardware structure
1064 **/
1065static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1066{
1067 u32 eec;
1068
1069 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1070
1071 eec |= IXGBE_EEC_CS; /* Pull CS high */
1072 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1073
1074 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1075 IXGBE_WRITE_FLUSH(hw);
1076
1077 udelay(1);
1078
1079 /* Stop requesting EEPROM access */
1080 eec &= ~IXGBE_EEC_REQ;
1081 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1082
1083 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1084}
1085
9a799d71
AK		 1086/**
1087 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
1088 * @hw: pointer to hardware structure
1089 **/
a391f1d5 1090u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1091{
1092 u16 i;
1093 u16 j;
1094 u16 checksum = 0;
1095 u16 length = 0;
1096 u16 pointer = 0;
1097 u16 word = 0;
1098
1099 /* Include 0x0-0x3F in the checksum */
1100 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
c44ade9e 1101 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
9a799d71
AK		 1102 hw_dbg(hw, "EEPROM read failed\n");
1103 break;
1104 }
1105 checksum += word;
1106 }
1107
1108 /* Include all data from pointers except for the fw pointer */
1109 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
c44ade9e 1110 hw->eeprom.ops.read(hw, i, &pointer);
9a799d71
AK		 1111
1112 /* Make sure the pointer seems valid */
1113 if (pointer != 0xFFFF && pointer != 0) {
c44ade9e 1114 hw->eeprom.ops.read(hw, pointer, &length);
9a799d71
AK		 1115
1116 if (length != 0xFFFF && length != 0) {
1117 for (j = pointer+1; j <= pointer+length; j++) {
c44ade9e 1118 hw->eeprom.ops.read(hw, j, &word);
9a799d71
AK		 1119 checksum += word;
1120 }
1121 }
1122 }
1123 }
1124
1125 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1126
1127 return checksum;
1128}
1129
1130/**
c44ade9e 1131 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1132 * @hw: pointer to hardware structure
1133 * @checksum_val: calculated checksum
1134 *
1135 * Performs checksum calculation and validates the EEPROM checksum. If the
1136 * caller does not need checksum_val, the value can be NULL.
1137 **/
c44ade9e
JB		 1138s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1139 u16 *checksum_val)
9a799d71
AK		 1140{
1141 s32 status;
1142 u16 checksum;
1143 u16 read_checksum = 0;
1144
1145 /*
1146 * Read the first word from the EEPROM. If this times out or fails, do
1147 * not continue or we could be in for a very long wait while every
1148 * EEPROM read fails
1149 */
c44ade9e 1150 status = hw->eeprom.ops.read(hw, 0, &checksum);
9a799d71
AK		 1151
1152 if (status == 0) {
a391f1d5 1153 checksum = hw->eeprom.ops.calc_checksum(hw);
9a799d71 1154
c44ade9e 1155 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
9a799d71
AK		 1156
1157 /*
1158 * Verify read checksum from EEPROM is the same as
1159 * calculated checksum
1160 */
1161 if (read_checksum != checksum)
1162 status = IXGBE_ERR_EEPROM_CHECKSUM;
1163
1164 /* If the user cares, return the calculated checksum */
1165 if (checksum_val)
1166 *checksum_val = checksum;
1167 } else {
1168 hw_dbg(hw, "EEPROM read failed\n");
1169 }
1170
1171 return status;
1172}
1173
c44ade9e
JB		 1174/**
1175 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1176 * @hw: pointer to hardware structure
1177 **/
1178s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1179{
1180 s32 status;
1181 u16 checksum;
1182
1183 /*
1184 * Read the first word from the EEPROM. If this times out or fails, do
1185 * not continue or we could be in for a very long wait while every
1186 * EEPROM read fails
1187 */
1188 status = hw->eeprom.ops.read(hw, 0, &checksum);
1189
1190 if (status == 0) {
a391f1d5 1191 checksum = hw->eeprom.ops.calc_checksum(hw);
c44ade9e
JB		 1192 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1193 checksum);
1194 } else {
1195 hw_dbg(hw, "EEPROM read failed\n");
1196 }
1197
1198 return status;
1199}
1200
9a799d71
AK		 1201/**
1202 * ixgbe_validate_mac_addr - Validate MAC address
1203 * @mac_addr: pointer to MAC address.
1204 *
1205 * Tests a MAC address to ensure it is a valid Individual Address
1206 **/
1207s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1208{
1209 s32 status = 0;
1210
1211 /* Make sure it is not a multicast address */
1212 if (IXGBE_IS_MULTICAST(mac_addr))
1213 status = IXGBE_ERR_INVALID_MAC_ADDR;
1214 /* Not a broadcast address */
1215 else if (IXGBE_IS_BROADCAST(mac_addr))
1216 status = IXGBE_ERR_INVALID_MAC_ADDR;
1217 /* Reject the zero address */
1218 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
c44ade9e 1219 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
9a799d71
AK		 1220 status = IXGBE_ERR_INVALID_MAC_ADDR;
1221
1222 return status;
1223}
1224
1225/**
c44ade9e 1226 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1227 * @hw: pointer to hardware structure
9a799d71 1228 * @index: Receive address register to write
c44ade9e
JB		 1229 * @addr: Address to put into receive address register
1230 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1231 * @enable_addr: set flag that address is active
1232 *
1233 * Puts an ethernet address into a receive address register.
1234 **/
c44ade9e
JB		 1235s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1236 u32 enable_addr)
9a799d71
AK		 1237{
1238 u32 rar_low, rar_high;
c44ade9e
JB		 1239 u32 rar_entries = hw->mac.num_rar_entries;
1240
1241 /* setup VMDq pool selection before this RAR gets enabled */
1242 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1243
c44ade9e
JB		 1244 /* Make sure we are using a valid rar index range */
1245 if (index < rar_entries) {
b4617240 1246 /*
c44ade9e
JB		 1247 * HW expects these in little endian so we reverse the byte
1248 * order from network order (big endian) to little endian
b4617240
PW		 1249 */
1250 rar_low = ((u32)addr[0] |
1251 ((u32)addr[1] << 8) |
1252 ((u32)addr[2] << 16) |
1253 ((u32)addr[3] << 24));
c44ade9e
JB		 1254 /*
1255 * Some parts put the VMDq setting in the extra RAH bits,
1256 * so save everything except the lower 16 bits that hold part
1257 * of the address and the address valid bit.
1258 */
1259 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1260 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1261 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1262
b4617240
PW		 1263 if (enable_addr != 0)
1264 rar_high |= IXGBE_RAH_AV;
9a799d71 1265
b4617240
PW		 1266 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1267 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1268 } else {
1269 hw_dbg(hw, "RAR index %d is out of range.\n", index);
a1868dc2 1270 return IXGBE_ERR_RAR_INDEX;
c44ade9e
JB		 1271 }
1272
1273 return 0;
1274}
1275
1276/**
1277 * ixgbe_clear_rar_generic - Remove Rx address register
1278 * @hw: pointer to hardware structure
1279 * @index: Receive address register to write
1280 *
1281 * Clears an ethernet address from a receive address register.
1282 **/
1283s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1284{
1285 u32 rar_high;
1286 u32 rar_entries = hw->mac.num_rar_entries;
1287
1288 /* Make sure we are using a valid rar index range */
1289 if (index < rar_entries) {
1290 /*
1291 * Some parts put the VMDq setting in the extra RAH bits,
1292 * so save everything except the lower 16 bits that hold part
1293 * of the address and the address valid bit.
1294 */
1295 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1296 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1297
1298 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1299 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1300 } else {
1301 hw_dbg(hw, "RAR index %d is out of range.\n", index);
a1868dc2 1302 return IXGBE_ERR_RAR_INDEX;
c44ade9e
JB		 1303 }
1304
1305 /* clear VMDq pool/queue selection for this RAR */
1306 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1307
1308 return 0;
1309}
1310
1311/**
c44ade9e
JB		 1312 * ixgbe_enable_rar - Enable Rx address register
1313 * @hw: pointer to hardware structure
1314 * @index: index into the RAR table
1315 *
1316 * Enables the select receive address register.
1317 **/
1318static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
1319{
1320 u32 rar_high;
1321
1322 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1323 rar_high |= IXGBE_RAH_AV;
1324 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1325}
1326
1327/**
1328 * ixgbe_disable_rar - Disable Rx address register
1329 * @hw: pointer to hardware structure
1330 * @index: index into the RAR table
1331 *
1332 * Disables the select receive address register.
1333 **/
1334static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
1335{
1336 u32 rar_high;
1337
1338 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1339 rar_high &= (~IXGBE_RAH_AV);
1340 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1341}
1342
1343/**
1344 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1345 * @hw: pointer to hardware structure
1346 *
1347 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1348 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1349 * the receiver is in reset when the routine is called.
1350 **/
c44ade9e 1351s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1352{
1353 u32 i;
2c5645cf 1354 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1355
1356 /*
1357 * If the current mac address is valid, assume it is a software override
1358 * to the permanent address.
1359 * Otherwise, use the permanent address from the eeprom.
1360 */
1361 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1362 IXGBE_ERR_INVALID_MAC_ADDR) {
1363 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1364 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1365
ce7194d8 1366 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1367 } else {
1368 /* Setup the receive address. */
1369 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1370 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1371
c44ade9e 1372 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
96cc6372
AD		 1373
1374 /* clear VMDq pool/queue selection for RAR 0 */
1375 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
9a799d71 1376 }
c44ade9e 1377 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1378
1379 hw->addr_ctrl.rar_used_count = 1;
1380
1381 /* Zero out the other receive addresses. */
c44ade9e 1382 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1383 for (i = 1; i < rar_entries; i++) {
1384 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1385 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1386 }
1387
1388 /* Clear the MTA */
1389 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1390 hw->addr_ctrl.mta_in_use = 0;
1391 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1392
1393 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1394 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1395 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1396
c44ade9e
JB		 1397 if (hw->mac.ops.init_uta_tables)
1398 hw->mac.ops.init_uta_tables(hw);
1399
9a799d71
AK		 1400 return 0;
1401}
1402
2c5645cf
CL		 1403/**
1404 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1405 * @hw: pointer to hardware structure
1406 * @addr: new address
1407 *
1408 * Adds it to unused receive address register or goes into promiscuous mode.
1409 **/
c44ade9e 1410static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2c5645cf
CL		 1411{
1412 u32 rar_entries = hw->mac.num_rar_entries;
1413 u32 rar;
1414
1415 hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1416 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1417
1418 /*
1419 * Place this address in the RAR if there is room,
1420 * else put the controller into promiscuous mode
1421 */
1422 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1423 rar = hw->addr_ctrl.rar_used_count -
1424 hw->addr_ctrl.mc_addr_in_rar_count;
c44ade9e 1425 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2c5645cf
CL		 1426 hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
1427 hw->addr_ctrl.rar_used_count++;
1428 } else {
1429 hw->addr_ctrl.overflow_promisc++;
1430 }
1431
1432 hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
1433}
1434
1435/**
c44ade9e 1436 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2c5645cf 1437 * @hw: pointer to hardware structure
32e7bfc4 1438 * @netdev: pointer to net device structure
2c5645cf
CL		 1439 *
1440 * The given list replaces any existing list. Clears the secondary addrs from
1441 * receive address registers. Uses unused receive address registers for the
1442 * first secondary addresses, and falls back to promiscuous mode as needed.
1443 *
1444 * Drivers using secondary unicast addresses must set user_set_promisc when
1445 * manually putting the device into promiscuous mode.
1446 **/
ccffad25 1447s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw,
32e7bfc4 1448 struct net_device *netdev)
2c5645cf 1449{
2c5645cf
CL		 1450 u32 i;
1451 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1452 u32 uc_addr_in_use;
1453 u32 fctrl;
ccffad25 1454 struct netdev_hw_addr *ha;
2c5645cf
CL		 1455
1456 /*
1457 * Clear accounting of old secondary address list,
1458 * don't count RAR[0]
1459 */
495dce12 1460 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2c5645cf
CL		 1461 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1462 hw->addr_ctrl.overflow_promisc = 0;
1463
1464 /* Zero out the other receive addresses */
91152c32
SN		 1465 hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use + 1);
1466 for (i = 0; i < uc_addr_in_use; i++) {
1467 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
1468 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2c5645cf
CL		 1469 }
1470
1471 /* Add the new addresses */
32e7bfc4 1472 netdev_for_each_uc_addr(ha, netdev) {
2c5645cf 1473 hw_dbg(hw, " Adding the secondary addresses:\n");
ccffad25 1474 ixgbe_add_uc_addr(hw, ha->addr, 0);
2c5645cf
CL		 1475 }
1476
1477 if (hw->addr_ctrl.overflow_promisc) {
1478 /* enable promisc if not already in overflow or set by user */
1479 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1480 hw_dbg(hw, " Entering address overflow promisc mode\n");
1481 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1482 fctrl |= IXGBE_FCTRL_UPE;
1483 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
e433ea1f 1484 hw->addr_ctrl.uc_set_promisc = true;
2c5645cf
CL		 1485 }
1486 } else {
1487 /* only disable if set by overflow, not by user */
e433ea1f
ET		 1488 if ((old_promisc_setting && hw->addr_ctrl.uc_set_promisc) &&
1489 !(hw->addr_ctrl.user_set_promisc)) {
2c5645cf
CL		 1490 hw_dbg(hw, " Leaving address overflow promisc mode\n");
1491 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1492 fctrl &= ~IXGBE_FCTRL_UPE;
1493 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
e433ea1f 1494 hw->addr_ctrl.uc_set_promisc = false;
2c5645cf
CL		 1495 }
1496 }
1497
c44ade9e 1498 hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
2c5645cf
CL		 1499 return 0;
1500}
1501
9a799d71
AK		 1502/**
1503 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1504 * @hw: pointer to hardware structure
1505 * @mc_addr: the multicast address
1506 *
1507 * Extracts the 12 bits, from a multicast address, to determine which
1508 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1509 * incoming rx multicast addresses, to determine the bit-vector to check in
1510 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1511 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1512 * to mc_filter_type.
1513 **/
1514static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1515{
1516 u32 vector = 0;
1517
1518 switch (hw->mac.mc_filter_type) {
b4617240 1519 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1520 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1521 break;
b4617240 1522 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1523 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1524 break;
b4617240 1525 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1526 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1527 break;
b4617240 1528 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1529 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1530 break;
b4617240 1531 default: /* Invalid mc_filter_type */
9a799d71
AK		 1532 hw_dbg(hw, "MC filter type param set incorrectly\n");
1533 break;
1534 }
1535
1536 /* vector can only be 12-bits or boundary will be exceeded */
1537 vector &= 0xFFF;
1538 return vector;
1539}
1540
1541/**
1542 * ixgbe_set_mta - Set bit-vector in multicast table
1543 * @hw: pointer to hardware structure
1544 * @hash_value: Multicast address hash value
1545 *
1546 * Sets the bit-vector in the multicast table.
1547 **/
1548static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1549{
1550 u32 vector;
1551 u32 vector_bit;
1552 u32 vector_reg;
1553 u32 mta_reg;
1554
1555 hw->addr_ctrl.mta_in_use++;
1556
1557 vector = ixgbe_mta_vector(hw, mc_addr);
1558 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1559
1560 /*
1561 * The MTA is a register array of 128 32-bit registers. It is treated
1562 * like an array of 4096 bits. We want to set bit
1563 * BitArray[vector_value]. So we figure out what register the bit is
1564 * in, read it, OR in the new bit, then write back the new value. The
1565 * register is determined by the upper 7 bits of the vector value and
1566 * the bit within that register are determined by the lower 5 bits of
1567 * the value.
1568 */
1569 vector_reg = (vector >> 5) & 0x7F;
1570 vector_bit = vector & 0x1F;
1571 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
1572 mta_reg |= (1 << vector_bit);
1573 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
1574}
1575
9a799d71 1576/**
c44ade9e 1577 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71 1578 * @hw: pointer to hardware structure
2853eb89 1579 * @netdev: pointer to net device structure
9a799d71
AK		 1580 *
1581 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 1582 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 1583 * registers for the first multicast addresses, and hashes the rest into the
1584 * multicast table.
1585 **/
2853eb89
JP		 1586s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1587 struct net_device *netdev)
9a799d71 1588{
22bedad3 1589 struct netdev_hw_addr *ha;
9a799d71 1590 u32 i;
9a799d71
AK		 1591
1592 /*
1593 * Set the new number of MC addresses that we are being requested to
1594 * use.
1595 */
2853eb89 1596 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
9a799d71
AK		 1597 hw->addr_ctrl.mta_in_use = 0;
1598
9a799d71
AK		 1599 /* Clear the MTA */
1600 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1601 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1602 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1603
1604 /* Add the new addresses */
22bedad3 1605 netdev_for_each_mc_addr(ha, netdev) {
9a799d71 1606 hw_dbg(hw, " Adding the multicast addresses:\n");
22bedad3 1607 ixgbe_set_mta(hw, ha->addr);
9a799d71
AK		 1608 }
1609
1610 /* Enable mta */
1611 if (hw->addr_ctrl.mta_in_use > 0)
1612 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
b4617240 1613 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 1614
c44ade9e 1615 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 1616 return 0;
1617}
1618
1619/**
c44ade9e 1620 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 1621 * @hw: pointer to hardware structure
1622 *
c44ade9e 1623 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 1624 **/
c44ade9e 1625s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1626{
c44ade9e
JB		 1627 u32 i;
1628 u32 rar_entries = hw->mac.num_rar_entries;
1629 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 1630
c44ade9e
JB		 1631 if (a->mc_addr_in_rar_count > 0)
1632 for (i = (rar_entries - a->mc_addr_in_rar_count);
1633 i < rar_entries; i++)
1634 ixgbe_enable_rar(hw, i);
9a799d71 1635
c44ade9e
JB		 1636 if (a->mta_in_use > 0)
1637 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1638 hw->mac.mc_filter_type);
9a799d71
AK		 1639
1640 return 0;
1641}
1642
1643/**
c44ade9e 1644 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 1645 * @hw: pointer to hardware structure
9a799d71 1646 *
c44ade9e 1647 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 1648 **/
c44ade9e 1649s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1650{
c44ade9e
JB		 1651 u32 i;
1652 u32 rar_entries = hw->mac.num_rar_entries;
1653 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 1654
c44ade9e
JB		 1655 if (a->mc_addr_in_rar_count > 0)
1656 for (i = (rar_entries - a->mc_addr_in_rar_count);
1657 i < rar_entries; i++)
1658 ixgbe_disable_rar(hw, i);
9a799d71 1659
c44ade9e
JB		 1660 if (a->mta_in_use > 0)
1661 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 1662
1663 return 0;
1664}
1665
11afc1b1 1666/**
620fa036 1667 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1
PW		 1668 * @hw: pointer to hardware structure
1669 * @packetbuf_num: packet buffer number (0-7)
1670 *
1671 * Enable flow control according to the current settings.
1672 **/
620fa036 1673s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 1674{
1675 s32 ret_val = 0;
620fa036 1676 u32 mflcn_reg, fccfg_reg;
11afc1b1 1677 u32 reg;
70b77628 1678 u32 rx_pba_size;
16b61beb 1679 u32 fcrtl, fcrth;
70b77628
PWJ		 1680
1681#ifdef CONFIG_DCB
1682 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1683 goto out;
1684
1685#endif /* CONFIG_DCB */
620fa036
MC		 1686 /* Negotiate the fc mode to use */
1687 ret_val = ixgbe_fc_autoneg(hw);
1688 if (ret_val)
1689 goto out;
11afc1b1 1690
620fa036 1691 /* Disable any previous flow control settings */
11afc1b1
PW		 1692 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1693 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1694
1695 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1696 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1697
1698 /*
1699 * The possible values of fc.current_mode are:
1700 * 0: Flow control is completely disabled
1701 * 1: Rx flow control is enabled (we can receive pause frames,
1702 * but not send pause frames).
bb3daa4a
PW		 1703 * 2: Tx flow control is enabled (we can send pause frames but
1704 * we do not support receiving pause frames).
11afc1b1 1705 * 3: Both Rx and Tx flow control (symmetric) are enabled.
bb3daa4a 1706 * 4: Priority Flow Control is enabled.
11afc1b1
PW		 1707 * other: Invalid.
1708 */
1709 switch (hw->fc.current_mode) {
1710 case ixgbe_fc_none:
620fa036
MC		 1711 /*
1712 * Flow control is disabled by software override or autoneg.
1713 * The code below will actually disable it in the HW.
1714 */
11afc1b1
PW		 1715 break;
1716 case ixgbe_fc_rx_pause:
1717 /*
1718 * Rx Flow control is enabled and Tx Flow control is
1719 * disabled by software override. Since there really
1720 * isn't a way to advertise that we are capable of RX
1721 * Pause ONLY, we will advertise that we support both
1722 * symmetric and asymmetric Rx PAUSE. Later, we will
1723 * disable the adapter's ability to send PAUSE frames.
1724 */
1725 mflcn_reg |= IXGBE_MFLCN_RFCE;
1726 break;
1727 case ixgbe_fc_tx_pause:
1728 /*
1729 * Tx Flow control is enabled, and Rx Flow control is
1730 * disabled by software override.
1731 */
1732 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1733 break;
1734 case ixgbe_fc_full:
1735 /* Flow control (both Rx and Tx) is enabled by SW override. */
1736 mflcn_reg |= IXGBE_MFLCN_RFCE;
1737 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1738 break;
bb3daa4a
PW		 1739#ifdef CONFIG_DCB
1740 case ixgbe_fc_pfc:
1741 goto out;
1742 break;
620fa036 1743#endif /* CONFIG_DCB */
11afc1b1
PW		 1744 default:
1745 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 1746 ret_val = IXGBE_ERR_CONFIG;
11afc1b1
PW		 1747 goto out;
1748 break;
1749 }
1750
620fa036 1751 /* Set 802.3x based flow control settings. */
2132d381 1752 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 1753 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1754 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1755
16b61beb
JF		 1756 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
1757 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
620fa036 1758
16b61beb
JF		 1759 fcrth = (rx_pba_size - hw->fc.high_water) << 10;
1760 fcrtl = (rx_pba_size - hw->fc.low_water) << 10;
264857b8 1761
16b61beb
JF		 1762 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1763 fcrth |= IXGBE_FCRTH_FCEN;
1764 if (hw->fc.send_xon)
1765 fcrtl |= IXGBE_FCRTL_XONE;
11afc1b1
PW		 1766 }
1767
16b61beb
JF		 1768 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth);
1769 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl);
1770
11afc1b1 1771 /* Configure pause time (2 TCs per register) */
70b77628 1772 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
11afc1b1
PW		 1773 if ((packetbuf_num & 1) == 0)
1774 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1775 else
1776 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1777 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1778
1779 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1780
1781out:
1782 return ret_val;
1783}
1784
0ecc061d
PWJ		 1785/**
1786 * ixgbe_fc_autoneg - Configure flow control
1787 * @hw: pointer to hardware structure
1788 *
620fa036
MC		 1789 * Compares our advertised flow control capabilities to those advertised by
1790 * our link partner, and determines the proper flow control mode to use.
0ecc061d
PWJ		 1791 **/
1792s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1793{
1794 s32 ret_val = 0;
620fa036
MC		 1795 ixgbe_link_speed speed;
1796 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
539e5f02 1797 u32 links2, anlp1_reg, autoc_reg, links;
620fa036 1798 bool link_up;
0ecc061d
PWJ		 1799
1800 /*
620fa036
MC		 1801 * AN should have completed when the cable was plugged in.
1802 * Look for reasons to bail out. Bail out if:
1803 * - FC autoneg is disabled, or if
539e5f02 1804 * - link is not up.
620fa036 1805 *
539e5f02 1806 * Since we're being called from an LSC, link is already known to be up.
620fa036 1807 * So use link_up_wait_to_complete=false.
0ecc061d 1808 */
620fa036 1809 hw->mac.ops.check_link(hw, &speed, &link_up, false);
539e5f02
PWJ		 1810
1811 if (hw->fc.disable_fc_autoneg || (!link_up)) {
620fa036
MC		 1812 hw->fc.fc_was_autonegged = false;
1813 hw->fc.current_mode = hw->fc.requested_mode;
0ecc061d
PWJ		 1814 goto out;
1815 }
1816
539e5f02
PWJ		 1817 /*
1818 * On backplane, bail out if
1819 * - backplane autoneg was not completed, or if
000c486d 1820 * - we are 82599 and link partner is not AN enabled
539e5f02
PWJ		 1821 */
1822 if (hw->phy.media_type == ixgbe_media_type_backplane) {
1823 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
000c486d 1824 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
539e5f02
PWJ		 1825 hw->fc.fc_was_autonegged = false;
1826 hw->fc.current_mode = hw->fc.requested_mode;
1827 goto out;
1828 }
000c486d
DS		 1829
1830 if (hw->mac.type == ixgbe_mac_82599EB) {
1831 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
1832 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
1833 hw->fc.fc_was_autonegged = false;
1834 hw->fc.current_mode = hw->fc.requested_mode;
1835 goto out;
1836 }
1837 }
539e5f02
PWJ		 1838 }
1839
1840 /*
1841 * On multispeed fiber at 1g, bail out if
1842 * - link is up but AN did not complete, or if
1843 * - link is up and AN completed but timed out
1844 */
1845 if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) {
1846 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1847 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
1848 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
1849 hw->fc.fc_was_autonegged = false;
1850 hw->fc.current_mode = hw->fc.requested_mode;
1851 goto out;
1852 }
1853 }
1854
9bbe3a57
PW		 1855 /*
1856 * Bail out on
1857 * - copper or CX4 adapters
1858 * - fiber adapters running at 10gig
1859 */
1860 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
1861 (hw->phy.media_type == ixgbe_media_type_cx4) ||
1862 ((hw->phy.media_type == ixgbe_media_type_fiber) &&
1863 (speed == IXGBE_LINK_SPEED_10GB_FULL))) {
1864 hw->fc.fc_was_autonegged = false;
1865 hw->fc.current_mode = hw->fc.requested_mode;
1866 goto out;
1867 }
1868
0ecc061d
PWJ		 1869 /*
1870 * Read the AN advertisement and LP ability registers and resolve
1871 * local flow control settings accordingly
1872 */
539e5f02
PWJ		 1873 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1874 (hw->phy.media_type != ixgbe_media_type_backplane)) {
1875 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1876 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1877 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1878 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
1879 /*
1880 * Now we need to check if the user selected Rx ONLY
1881 * of pause frames. In this case, we had to advertise
1882 * FULL flow control because we could not advertise RX
1883 * ONLY. Hence, we must now check to see if we need to
1884 * turn OFF the TRANSMISSION of PAUSE frames.
1885 */
1886 if (hw->fc.requested_mode == ixgbe_fc_full) {
1887 hw->fc.current_mode = ixgbe_fc_full;
1888 hw_dbg(hw, "Flow Control = FULL.\n");
1889 } else {
1890 hw->fc.current_mode = ixgbe_fc_rx_pause;
1891 hw_dbg(hw, "Flow Control=RX PAUSE only\n");
1892 }
1893 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1894 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1895 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1896 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1897 hw->fc.current_mode = ixgbe_fc_tx_pause;
1898 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1899 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1900 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1901 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1902 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1903 hw->fc.current_mode = ixgbe_fc_rx_pause;
1904 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1905 } else {
1906 hw->fc.current_mode = ixgbe_fc_none;
1907 hw_dbg(hw, "Flow Control = NONE.\n");
1908 }
1909 }
1910
1911 if (hw->phy.media_type == ixgbe_media_type_backplane) {
0ecc061d 1912 /*
539e5f02
PWJ		 1913 * Read the 10g AN autoc and LP ability registers and resolve
1914 * local flow control settings accordingly
0ecc061d 1915 */
539e5f02
PWJ		 1916 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1917 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
1918
1919 if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1920 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) {
1921 /*
1922 * Now we need to check if the user selected Rx ONLY
1923 * of pause frames. In this case, we had to advertise
1924 * FULL flow control because we could not advertise RX
1925 * ONLY. Hence, we must now check to see if we need to
1926 * turn OFF the TRANSMISSION of PAUSE frames.
1927 */
1928 if (hw->fc.requested_mode == ixgbe_fc_full) {
1929 hw->fc.current_mode = ixgbe_fc_full;
1930 hw_dbg(hw, "Flow Control = FULL.\n");
1931 } else {
1932 hw->fc.current_mode = ixgbe_fc_rx_pause;
1933 hw_dbg(hw, "Flow Control=RX PAUSE only\n");
1934 }
1935 } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1936 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
1937 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
1938 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
1939 hw->fc.current_mode = ixgbe_fc_tx_pause;
1940 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1941 } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1942 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
1943 !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
1944 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
0ecc061d
PWJ		 1945 hw->fc.current_mode = ixgbe_fc_rx_pause;
1946 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
539e5f02
PWJ		 1947 } else {
1948 hw->fc.current_mode = ixgbe_fc_none;
1949 hw_dbg(hw, "Flow Control = NONE.\n");
0ecc061d 1950 }
0ecc061d 1951 }
620fa036
MC		 1952 /* Record that current_mode is the result of a successful autoneg */
1953 hw->fc.fc_was_autonegged = true;
1954
0ecc061d
PWJ		 1955out:
1956 return ret_val;
1957}
1958
11afc1b1 1959/**
620fa036 1960 * ixgbe_setup_fc - Set up flow control
11afc1b1
PW		 1961 * @hw: pointer to hardware structure
1962 *
620fa036 1963 * Called at init time to set up flow control.
11afc1b1 1964 **/
7b25cdba 1965static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 1966{
1967 s32 ret_val = 0;
620fa036 1968 u32 reg;
11afc1b1 1969
bb3daa4a
PW		 1970#ifdef CONFIG_DCB
1971 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
1972 hw->fc.current_mode = hw->fc.requested_mode;
1973 goto out;
1974 }
1975
1976#endif
11afc1b1
PW		 1977 /* Validate the packetbuf configuration */
1978 if (packetbuf_num < 0 || packetbuf_num > 7) {
1979 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
1980 "is 0-7\n", packetbuf_num);
1981 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1982 goto out;
1983 }
1984
1985 /*
1986 * Validate the water mark configuration. Zero water marks are invalid
1987 * because it causes the controller to just blast out fc packets.
1988 */
1989 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
620fa036
MC		 1990 hw_dbg(hw, "Invalid water mark configuration\n");
1991 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1992 goto out;
11afc1b1
PW		 1993 }
1994
1995 /*
1996 * Validate the requested mode. Strict IEEE mode does not allow
620fa036 1997 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
11afc1b1
PW		 1998 */
1999 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2000 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
2001 "IEEE mode\n");
2002 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2003 goto out;
2004 }
2005
2006 /*
2007 * 10gig parts do not have a word in the EEPROM to determine the
2008 * default flow control setting, so we explicitly set it to full.
2009 */
2010 if (hw->fc.requested_mode == ixgbe_fc_default)
2011 hw->fc.requested_mode = ixgbe_fc_full;
2012
2013 /*
620fa036
MC		 2014 * Set up the 1G flow control advertisement registers so the HW will be
2015 * able to do fc autoneg once the cable is plugged in. If we end up
2016 * using 10g instead, this is harmless.
11afc1b1 2017 */
620fa036 2018 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
11afc1b1 2019
620fa036
MC		 2020 /*
2021 * The possible values of fc.requested_mode are:
2022 * 0: Flow control is completely disabled
2023 * 1: Rx flow control is enabled (we can receive pause frames,
2024 * but not send pause frames).
2025 * 2: Tx flow control is enabled (we can send pause frames but
2026 * we do not support receiving pause frames).
2027 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2028#ifdef CONFIG_DCB
2029 * 4: Priority Flow Control is enabled.
2030#endif
2031 * other: Invalid.
2032 */
2033 switch (hw->fc.requested_mode) {
2034 case ixgbe_fc_none:
2035 /* Flow control completely disabled by software override. */
2036 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2037 break;
2038 case ixgbe_fc_rx_pause:
2039 /*
2040 * Rx Flow control is enabled and Tx Flow control is
2041 * disabled by software override. Since there really
2042 * isn't a way to advertise that we are capable of RX
2043 * Pause ONLY, we will advertise that we support both
2044 * symmetric and asymmetric Rx PAUSE. Later, we will
2045 * disable the adapter's ability to send PAUSE frames.
2046 */
2047 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2048 break;
2049 case ixgbe_fc_tx_pause:
2050 /*
2051 * Tx Flow control is enabled, and Rx Flow control is
2052 * disabled by software override.
2053 */
2054 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
2055 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
2056 break;
2057 case ixgbe_fc_full:
2058 /* Flow control (both Rx and Tx) is enabled by SW override. */
2059 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2060 break;
2061#ifdef CONFIG_DCB
2062 case ixgbe_fc_pfc:
11afc1b1 2063 goto out;
620fa036
MC		 2064 break;
2065#endif /* CONFIG_DCB */
2066 default:
2067 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 2068 ret_val = IXGBE_ERR_CONFIG;
620fa036
MC		 2069 goto out;
2070 break;
2071 }
2072
2073 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
2074 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
11afc1b1 2075
620fa036
MC		 2076 /* Disable AN timeout */
2077 if (hw->fc.strict_ieee)
2078 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
2079
2080 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
2081 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
11afc1b1 2082
539e5f02
PWJ		 2083 /*
2084 * Set up the 10G flow control advertisement registers so the HW
2085 * can do fc autoneg once the cable is plugged in. If we end up
2086 * using 1g instead, this is harmless.
2087 */
2088 reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2089
2090 /*
2091 * The possible values of fc.requested_mode are:
2092 * 0: Flow control is completely disabled
2093 * 1: Rx flow control is enabled (we can receive pause frames,
2094 * but not send pause frames).
2095 * 2: Tx flow control is enabled (we can send pause frames but
2096 * we do not support receiving pause frames).
2097 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2098 * other: Invalid.
2099 */
2100 switch (hw->fc.requested_mode) {
2101 case ixgbe_fc_none:
2102 /* Flow control completely disabled by software override. */
2103 reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2104 break;
2105 case ixgbe_fc_rx_pause:
2106 /*
2107 * Rx Flow control is enabled and Tx Flow control is
2108 * disabled by software override. Since there really
2109 * isn't a way to advertise that we are capable of RX
2110 * Pause ONLY, we will advertise that we support both
2111 * symmetric and asymmetric Rx PAUSE. Later, we will
2112 * disable the adapter's ability to send PAUSE frames.
2113 */
2114 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2115 break;
2116 case ixgbe_fc_tx_pause:
2117 /*
2118 * Tx Flow control is enabled, and Rx Flow control is
2119 * disabled by software override.
2120 */
2121 reg |= (IXGBE_AUTOC_ASM_PAUSE);
2122 reg &= ~(IXGBE_AUTOC_SYM_PAUSE);
2123 break;
2124 case ixgbe_fc_full:
2125 /* Flow control (both Rx and Tx) is enabled by SW override. */
2126 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2127 break;
2128#ifdef CONFIG_DCB
2129 case ixgbe_fc_pfc:
2130 goto out;
2131 break;
2132#endif /* CONFIG_DCB */
2133 default:
2134 hw_dbg(hw, "Flow control param set incorrectly\n");
2135 ret_val = IXGBE_ERR_CONFIG;
2136 goto out;
2137 break;
2138 }
2139 /*
2140 * AUTOC restart handles negotiation of 1G and 10G. There is
2141 * no need to set the PCS1GCTL register.
2142 */
2143 reg |= IXGBE_AUTOC_AN_RESTART;
2144 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg);
2145 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
2146
11afc1b1
PW		 2147out:
2148 return ret_val;
2149}
2150
9a799d71
AK		 2151/**
2152 * ixgbe_disable_pcie_master - Disable PCI-express master access
2153 * @hw: pointer to hardware structure
2154 *
2155 * Disables PCI-Express master access and verifies there are no pending
2156 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2157 * bit hasn't caused the master requests to be disabled, else 0
2158 * is returned signifying master requests disabled.
2159 **/
2160s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2161{
c44ade9e
JB		 2162 u32 i;
2163 u32 reg_val;
2164 u32 number_of_queues;
9a799d71
AK		 2165 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2166
c44ade9e
JB		 2167 /* Disable the receive unit by stopping each queue */
2168 number_of_queues = hw->mac.max_rx_queues;
2169 for (i = 0; i < number_of_queues; i++) {
2170 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
2171 if (reg_val & IXGBE_RXDCTL_ENABLE) {
2172 reg_val &= ~IXGBE_RXDCTL_ENABLE;
2173 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
2174 }
2175 }
2176
2177 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2178 reg_val |= IXGBE_CTRL_GIO_DIS;
2179 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
9a799d71
AK		 2180
2181 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2182 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
2183 status = 0;
2184 break;
2185 }
2186 udelay(100);
2187 }
2188
2189 return status;
2190}
2191
2192
2193/**
c44ade9e 2194 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2195 * @hw: pointer to hardware structure
c44ade9e 2196 * @mask: Mask to specify which semaphore to acquire
9a799d71 2197 *
c44ade9e 2198 * Acquires the SWFW semaphore thought the GSSR register for the specified
9a799d71
AK		 2199 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2200 **/
2201s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2202{
2203 u32 gssr;
2204 u32 swmask = mask;
2205 u32 fwmask = mask << 5;
2206 s32 timeout = 200;
2207
2208 while (timeout) {
2209 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2210 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2211
2212 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2213 if (!(gssr & (fwmask | swmask)))
2214 break;
2215
2216 /*
2217 * Firmware currently using resource (fwmask) or other software
2218 * thread currently using resource (swmask)
2219 */
2220 ixgbe_release_eeprom_semaphore(hw);
2221 msleep(5);
2222 timeout--;
2223 }
2224
2225 if (!timeout) {
2226 hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
539e5f02 2227 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2228 }
2229
2230 gssr |= swmask;
2231 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2232
2233 ixgbe_release_eeprom_semaphore(hw);
2234 return 0;
2235}
2236
2237/**
2238 * ixgbe_release_swfw_sync - Release SWFW semaphore
2239 * @hw: pointer to hardware structure
c44ade9e 2240 * @mask: Mask to specify which semaphore to release
9a799d71 2241 *
c44ade9e 2242 * Releases the SWFW semaphore thought the GSSR register for the specified
9a799d71
AK		 2243 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2244 **/
2245void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2246{
2247 u32 gssr;
2248 u32 swmask = mask;
2249
2250 ixgbe_get_eeprom_semaphore(hw);
2251
2252 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2253 gssr &= ~swmask;
2254 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2255
2256 ixgbe_release_eeprom_semaphore(hw);
2257}
2258
11afc1b1
PW		 2259/**
2260 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2261 * @hw: pointer to hardware structure
2262 * @regval: register value to write to RXCTRL
2263 *
2264 * Enables the Rx DMA unit
2265 **/
2266s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2267{
2268 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2269
2270 return 0;
2271}
87c12017
PW		 2272
2273/**
2274 * ixgbe_blink_led_start_generic - Blink LED based on index.
2275 * @hw: pointer to hardware structure
2276 * @index: led number to blink
2277 **/
2278s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2279{
2280 ixgbe_link_speed speed = 0;
2281 bool link_up = 0;
2282 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2283 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2284
2285 /*
2286 * Link must be up to auto-blink the LEDs;
2287 * Force it if link is down.
2288 */
2289 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2290
2291 if (!link_up) {
50ac58ba 2292 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017
PW		 2293 autoc_reg |= IXGBE_AUTOC_FLU;
2294 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2295 msleep(10);
2296 }
2297
2298 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2299 led_reg |= IXGBE_LED_BLINK(index);
2300 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2301 IXGBE_WRITE_FLUSH(hw);
2302
2303 return 0;
2304}
2305
2306/**
2307 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2308 * @hw: pointer to hardware structure
2309 * @index: led number to stop blinking
2310 **/
2311s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2312{
2313 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2314 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2315
2316 autoc_reg &= ~IXGBE_AUTOC_FLU;
2317 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2318 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2319
2320 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2321 led_reg &= ~IXGBE_LED_BLINK(index);
2322 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2323 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2324 IXGBE_WRITE_FLUSH(hw);
2325
2326 return 0;
2327}
21ce849b
MC		 2328
2329/**
2330 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2331 * @hw: pointer to hardware structure
2332 * @san_mac_offset: SAN MAC address offset
2333 *
2334 * This function will read the EEPROM location for the SAN MAC address
2335 * pointer, and returns the value at that location. This is used in both
2336 * get and set mac_addr routines.
2337 **/
2338static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2339 u16 *san_mac_offset)
2340{
2341 /*
2342 * First read the EEPROM pointer to see if the MAC addresses are
2343 * available.
2344 */
2345 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2346
2347 return 0;
2348}
2349
2350/**
2351 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2352 * @hw: pointer to hardware structure
2353 * @san_mac_addr: SAN MAC address
2354 *
2355 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2356 * per-port, so set_lan_id() must be called before reading the addresses.
2357 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2358 * upon for non-SFP connections, so we must call it here.
2359 **/
2360s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2361{
2362 u16 san_mac_data, san_mac_offset;
2363 u8 i;
2364
2365 /*
2366 * First read the EEPROM pointer to see if the MAC addresses are
2367 * available. If they're not, no point in calling set_lan_id() here.
2368 */
2369 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2370
2371 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2372 /*
2373 * No addresses available in this EEPROM. It's not an
2374 * error though, so just wipe the local address and return.
2375 */
2376 for (i = 0; i < 6; i++)
2377 san_mac_addr[i] = 0xFF;
2378
2379 goto san_mac_addr_out;
2380 }
2381
2382 /* make sure we know which port we need to program */
2383 hw->mac.ops.set_lan_id(hw);
2384 /* apply the port offset to the address offset */
2385 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2386 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2387 for (i = 0; i < 3; i++) {
2388 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2389 san_mac_addr[i * 2] = (u8)(san_mac_data);
2390 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2391 san_mac_offset++;
2392 }
2393
2394san_mac_addr_out:
2395 return 0;
2396}
2397
2398/**
2399 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2400 * @hw: pointer to hardware structure
2401 *
2402 * Read PCIe configuration space, and get the MSI-X vector count from
2403 * the capabilities table.
2404 **/
2405u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2406{
2407 struct ixgbe_adapter *adapter = hw->back;
2408 u16 msix_count;
2409 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
2410 &msix_count);
2411 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2412
2413 /* MSI-X count is zero-based in HW, so increment to give proper value */
2414 msix_count++;
2415
2416 return msix_count;
2417}
2418
2419/**
2420 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2421 * @hw: pointer to hardware struct
2422 * @rar: receive address register index to disassociate
2423 * @vmdq: VMDq pool index to remove from the rar
2424 **/
2425s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2426{
2427 u32 mpsar_lo, mpsar_hi;
2428 u32 rar_entries = hw->mac.num_rar_entries;
2429
2430 if (rar < rar_entries) {
2431 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2432 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2433
2434 if (!mpsar_lo && !mpsar_hi)
2435 goto done;
2436
2437 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2438 if (mpsar_lo) {
2439 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2440 mpsar_lo = 0;
2441 }
2442 if (mpsar_hi) {
2443 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2444 mpsar_hi = 0;
2445 }
2446 } else if (vmdq < 32) {
2447 mpsar_lo &= ~(1 << vmdq);
2448 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2449 } else {
2450 mpsar_hi &= ~(1 << (vmdq - 32));
2451 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2452 }
2453
2454 /* was that the last pool using this rar? */
2455 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2456 hw->mac.ops.clear_rar(hw, rar);
2457 } else {
2458 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2459 }
2460
2461done:
2462 return 0;
2463}
2464
2465/**
2466 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2467 * @hw: pointer to hardware struct
2468 * @rar: receive address register index to associate with a VMDq index
2469 * @vmdq: VMDq pool index
2470 **/
2471s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2472{
2473 u32 mpsar;
2474 u32 rar_entries = hw->mac.num_rar_entries;
2475
2476 if (rar < rar_entries) {
2477 if (vmdq < 32) {
2478 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2479 mpsar |= 1 << vmdq;
2480 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2481 } else {
2482 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2483 mpsar |= 1 << (vmdq - 32);
2484 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2485 }
2486 } else {
2487 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2488 }
2489 return 0;
2490}
2491
2492/**
2493 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2494 * @hw: pointer to hardware structure
2495 **/
2496s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2497{
2498 int i;
2499
2500
2501 for (i = 0; i < 128; i++)
2502 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2503
2504 return 0;
2505}
2506
2507/**
2508 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2509 * @hw: pointer to hardware structure
2510 * @vlan: VLAN id to write to VLAN filter
2511 *
2512 * return the VLVF index where this VLAN id should be placed
2513 *
2514 **/
5d5b7c39 2515static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
21ce849b
MC		 2516{
2517 u32 bits = 0;
2518 u32 first_empty_slot = 0;
2519 s32 regindex;
2520
2521 /* short cut the special case */
2522 if (vlan == 0)
2523 return 0;
2524
2525 /*
2526 * Search for the vlan id in the VLVF entries. Save off the first empty
2527 * slot found along the way
2528 */
2529 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2530 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2531 if (!bits && !(first_empty_slot))
2532 first_empty_slot = regindex;
2533 else if ((bits & 0x0FFF) == vlan)
2534 break;
2535 }
2536
2537 /*
2538 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2539 * in the VLVF. Else use the first empty VLVF register for this
2540 * vlan id.
2541 */
2542 if (regindex >= IXGBE_VLVF_ENTRIES) {
2543 if (first_empty_slot)
2544 regindex = first_empty_slot;
2545 else {
2546 hw_dbg(hw, "No space in VLVF.\n");
2547 regindex = IXGBE_ERR_NO_SPACE;
2548 }
2549 }
2550
2551 return regindex;
2552}
2553
2554/**
2555 * ixgbe_set_vfta_generic - Set VLAN filter table
2556 * @hw: pointer to hardware structure
2557 * @vlan: VLAN id to write to VLAN filter
2558 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2559 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2560 *
2561 * Turn on/off specified VLAN in the VLAN filter table.
2562 **/
2563s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
2564 bool vlan_on)
2565{
2566 s32 regindex;
2567 u32 bitindex;
2568 u32 vfta;
2569 u32 bits;
2570 u32 vt;
2571 u32 targetbit;
2572 bool vfta_changed = false;
2573
2574 if (vlan > 4095)
2575 return IXGBE_ERR_PARAM;
2576
2577 /*
2578 * this is a 2 part operation - first the VFTA, then the
2579 * VLVF and VLVFB if VT Mode is set
2580 * We don't write the VFTA until we know the VLVF part succeeded.
2581 */
2582
2583 /* Part 1
2584 * The VFTA is a bitstring made up of 128 32-bit registers
2585 * that enable the particular VLAN id, much like the MTA:
2586 * bits[11-5]: which register
2587 * bits[4-0]: which bit in the register
2588 */
2589 regindex = (vlan >> 5) & 0x7F;
2590 bitindex = vlan & 0x1F;
2591 targetbit = (1 << bitindex);
2592 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
2593
2594 if (vlan_on) {
2595 if (!(vfta & targetbit)) {
2596 vfta |= targetbit;
2597 vfta_changed = true;
2598 }
2599 } else {
2600 if ((vfta & targetbit)) {
2601 vfta &= ~targetbit;
2602 vfta_changed = true;
2603 }
2604 }
2605
2606 /* Part 2
2607 * If VT Mode is set
2608 * Either vlan_on
2609 * make sure the vlan is in VLVF
2610 * set the vind bit in the matching VLVFB
2611 * Or !vlan_on
2612 * clear the pool bit and possibly the vind
2613 */
2614 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2615 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
2616 s32 vlvf_index;
2617
2618 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
2619 if (vlvf_index < 0)
2620 return vlvf_index;
2621
2622 if (vlan_on) {
2623 /* set the pool bit */
2624 if (vind < 32) {
2625 bits = IXGBE_READ_REG(hw,
2626 IXGBE_VLVFB(vlvf_index*2));
2627 bits |= (1 << vind);
2628 IXGBE_WRITE_REG(hw,
2629 IXGBE_VLVFB(vlvf_index*2),
2630 bits);
2631 } else {
2632 bits = IXGBE_READ_REG(hw,
2633 IXGBE_VLVFB((vlvf_index*2)+1));
2634 bits |= (1 << (vind-32));
2635 IXGBE_WRITE_REG(hw,
2636 IXGBE_VLVFB((vlvf_index*2)+1),
2637 bits);
2638 }
2639 } else {
2640 /* clear the pool bit */
2641 if (vind < 32) {
2642 bits = IXGBE_READ_REG(hw,
2643 IXGBE_VLVFB(vlvf_index*2));
2644 bits &= ~(1 << vind);
2645 IXGBE_WRITE_REG(hw,
2646 IXGBE_VLVFB(vlvf_index*2),
2647 bits);
2648 bits |= IXGBE_READ_REG(hw,
2649 IXGBE_VLVFB((vlvf_index*2)+1));
2650 } else {
2651 bits = IXGBE_READ_REG(hw,
2652 IXGBE_VLVFB((vlvf_index*2)+1));
2653 bits &= ~(1 << (vind-32));
2654 IXGBE_WRITE_REG(hw,
2655 IXGBE_VLVFB((vlvf_index*2)+1),
2656 bits);
2657 bits |= IXGBE_READ_REG(hw,
2658 IXGBE_VLVFB(vlvf_index*2));
2659 }
2660 }
2661
2662 /*
2663 * If there are still bits set in the VLVFB registers
2664 * for the VLAN ID indicated we need to see if the
2665 * caller is requesting that we clear the VFTA entry bit.
2666 * If the caller has requested that we clear the VFTA
2667 * entry bit but there are still pools/VFs using this VLAN
2668 * ID entry then ignore the request. We're not worried
2669 * about the case where we're turning the VFTA VLAN ID
2670 * entry bit on, only when requested to turn it off as
2671 * there may be multiple pools and/or VFs using the
2672 * VLAN ID entry. In that case we cannot clear the
2673 * VFTA bit until all pools/VFs using that VLAN ID have also
2674 * been cleared. This will be indicated by "bits" being
2675 * zero.
2676 */
2677 if (bits) {
2678 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
2679 (IXGBE_VLVF_VIEN | vlan));
2680 if (!vlan_on) {
2681 /* someone wants to clear the vfta entry
2682 * but some pools/VFs are still using it.
2683 * Ignore it. */
2684 vfta_changed = false;
2685 }
2686 }
2687 else
2688 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
2689 }
2690
2691 if (vfta_changed)
2692 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
2693
2694 return 0;
2695}
2696
2697/**
2698 * ixgbe_clear_vfta_generic - Clear VLAN filter table
2699 * @hw: pointer to hardware structure
2700 *
2701 * Clears the VLAN filer table, and the VMDq index associated with the filter
2702 **/
2703s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
2704{
2705 u32 offset;
2706
2707 for (offset = 0; offset < hw->mac.vft_size; offset++)
2708 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
2709
2710 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
2711 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
2712 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
2713 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
2714 }
2715
2716 return 0;
2717}
2718
2719/**
2720 * ixgbe_check_mac_link_generic - Determine link and speed status
2721 * @hw: pointer to hardware structure
2722 * @speed: pointer to link speed
2723 * @link_up: true when link is up
2724 * @link_up_wait_to_complete: bool used to wait for link up or not
2725 *
2726 * Reads the links register to determine if link is up and the current speed
2727 **/
2728s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2729 bool *link_up, bool link_up_wait_to_complete)
2730{
2731 u32 links_reg;
2732 u32 i;
2733
2734 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2735 if (link_up_wait_to_complete) {
2736 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
2737 if (links_reg & IXGBE_LINKS_UP) {
2738 *link_up = true;
2739 break;
2740 } else {
2741 *link_up = false;
2742 }
2743 msleep(100);
2744 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2745 }
2746 } else {
2747 if (links_reg & IXGBE_LINKS_UP)
2748 *link_up = true;
2749 else
2750 *link_up = false;
2751 }
2752
2753 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2754 IXGBE_LINKS_SPEED_10G_82599)
2755 *speed = IXGBE_LINK_SPEED_10GB_FULL;
2756 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2757 IXGBE_LINKS_SPEED_1G_82599)
2758 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2759 else
2760 *speed = IXGBE_LINK_SPEED_100_FULL;
2761
2762 /* if link is down, zero out the current_mode */
2763 if (*link_up == false) {
2764 hw->fc.current_mode = ixgbe_fc_none;
2765 hw->fc.fc_was_autonegged = false;
2766 }
2767
2768 return 0;
2769}
a391f1d5
DS		 2770
2771/**
2772 * ixgbe_get_wwn_prefix_generic Get alternative WWNN/WWPN prefix from
2773 * the EEPROM
2774 * @hw: pointer to hardware structure
2775 * @wwnn_prefix: the alternative WWNN prefix
2776 * @wwpn_prefix: the alternative WWPN prefix
2777 *
2778 * This function will read the EEPROM from the alternative SAN MAC address
2779 * block to check the support for the alternative WWNN/WWPN prefix support.
2780 **/
2781s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2782 u16 *wwpn_prefix)
2783{
2784 u16 offset, caps;
2785 u16 alt_san_mac_blk_offset;
2786
2787 /* clear output first */
2788 *wwnn_prefix = 0xFFFF;
2789 *wwpn_prefix = 0xFFFF;
2790
2791 /* check if alternative SAN MAC is supported */
2792 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2793 &alt_san_mac_blk_offset);
2794
2795 if ((alt_san_mac_blk_offset == 0) ||
2796 (alt_san_mac_blk_offset == 0xFFFF))
2797 goto wwn_prefix_out;
2798
2799 /* check capability in alternative san mac address block */
2800 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2801 hw->eeprom.ops.read(hw, offset, &caps);
2802 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2803 goto wwn_prefix_out;
2804
2805 /* get the corresponding prefix for WWNN/WWPN */
2806 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2807 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2808
2809 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2810 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2811
2812wwn_prefix_out:
2813 return 0;
2814}
a985b6c3
GR		 2815
2816/**
2817 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
2818 * @hw: pointer to hardware structure
2819 * @enable: enable or disable switch for anti-spoofing
2820 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
2821 *
2822 **/
2823void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
2824{
2825 int j;
2826 int pf_target_reg = pf >> 3;
2827 int pf_target_shift = pf % 8;
2828 u32 pfvfspoof = 0;
2829
2830 if (hw->mac.type == ixgbe_mac_82598EB)
2831 return;
2832
2833 if (enable)
2834 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
2835
2836 /*
2837 * PFVFSPOOF register array is size 8 with 8 bits assigned to
2838 * MAC anti-spoof enables in each register array element.
2839 */
2840 for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
2841 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
2842
2843 /* If not enabling anti-spoofing then done */
2844 if (!enable)
2845 return;
2846
2847 /*
2848 * The PF should be allowed to spoof so that it can support
2849 * emulation mode NICs. Reset the bit assigned to the PF
2850 */
2851 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
2852 pfvfspoof ^= (1 << pf_target_shift);
2853 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
2854}
2855
2856/**
2857 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
2858 * @hw: pointer to hardware structure
2859 * @enable: enable or disable switch for VLAN anti-spoofing
2860 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
2861 *
2862 **/
2863void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
2864{
2865 int vf_target_reg = vf >> 3;
2866 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
2867 u32 pfvfspoof;
2868
2869 if (hw->mac.type == ixgbe_mac_82598EB)
2870 return;
2871
2872 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
2873 if (enable)
2874 pfvfspoof |= (1 << vf_target_shift);
2875 else
2876 pfvfspoof &= ~(1 << vf_target_shift);
2877 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
2878}
Linux kernel - Deliverables
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