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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
8c47eaa7 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
60127865 | 37 | #include <linux/pkt_sched.h> |
9a799d71 | 38 | #include <linux/ipv6.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
9a799d71 AK |
40 | #include <net/checksum.h> |
41 | #include <net/ip6_checksum.h> | |
42 | #include <linux/ethtool.h> | |
43 | #include <linux/if_vlan.h> | |
eacd73f7 | 44 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
45 | |
46 | #include "ixgbe.h" | |
47 | #include "ixgbe_common.h" | |
ee5f784a | 48 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 49 | #include "ixgbe_sriov.h" |
9a799d71 AK |
50 | |
51 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 52 | static const char ixgbe_driver_string[] = |
b4617240 | 53 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
9a799d71 | 54 | |
92eb879f | 55 | #define DRV_VERSION "2.0.62-k2" |
9c8eb720 | 56 | const char ixgbe_driver_version[] = DRV_VERSION; |
8c47eaa7 | 57 | static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation."; |
9a799d71 AK |
58 | |
59 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 60 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 61 | [board_82599] = &ixgbe_82599_info, |
9a799d71 AK |
62 | }; |
63 | ||
64 | /* ixgbe_pci_tbl - PCI Device ID Table | |
65 | * | |
66 | * Wildcard entries (PCI_ANY_ID) should come last | |
67 | * Last entry must be all 0s | |
68 | * | |
69 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
70 | * Class, Class Mask, private data (not used) } | |
71 | */ | |
a3aa1884 | 72 | static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { |
1e336d0f DS |
73 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), |
74 | board_82598 }, | |
9a799d71 | 75 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), |
3957d63d | 76 | board_82598 }, |
9a799d71 | 77 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 78 | board_82598 }, |
0befdb3e JB |
79 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
80 | board_82598 }, | |
3845bec0 PWJ |
81 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), |
82 | board_82598 }, | |
9a799d71 | 83 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 84 | board_82598 }, |
8d792cd9 JB |
85 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
86 | board_82598 }, | |
c4900be0 DS |
87 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
88 | board_82598 }, | |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
90 | board_82598 }, | |
b95f5fcb JB |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
92 | board_82598 }, | |
c4900be0 DS |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
94 | board_82598 }, | |
2f21bdd3 DS |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), |
96 | board_82598 }, | |
e8e26350 PW |
97 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), |
98 | board_82599 }, | |
1fcf03e6 PWJ |
99 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), |
100 | board_82599 }, | |
74757d49 DS |
101 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), |
102 | board_82599 }, | |
e8e26350 PW |
103 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), |
104 | board_82599 }, | |
38ad1c8e DS |
105 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), |
106 | board_82599 }, | |
dbfec662 DS |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), |
108 | board_82599 }, | |
8911184f PWJ |
109 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), |
110 | board_82599 }, | |
119fc60a MC |
111 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), |
112 | board_82599 }, | |
312eb931 DS |
113 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), |
114 | board_82599 }, | |
9a799d71 AK |
115 | |
116 | /* required last entry */ | |
117 | {0, } | |
118 | }; | |
119 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
120 | ||
5dd2d332 | 121 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 122 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
b4617240 | 123 | void *p); |
bd0362dd JC |
124 | static struct notifier_block dca_notifier = { |
125 | .notifier_call = ixgbe_notify_dca, | |
126 | .next = NULL, | |
127 | .priority = 0 | |
128 | }; | |
129 | #endif | |
130 | ||
1cdd1ec8 GR |
131 | #ifdef CONFIG_PCI_IOV |
132 | static unsigned int max_vfs; | |
133 | module_param(max_vfs, uint, 0); | |
134 | MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " | |
135 | "per physical function"); | |
136 | #endif /* CONFIG_PCI_IOV */ | |
137 | ||
9a799d71 AK |
138 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
139 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
140 | MODULE_LICENSE("GPL"); | |
141 | MODULE_VERSION(DRV_VERSION); | |
142 | ||
143 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
144 | ||
1cdd1ec8 GR |
145 | static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter) |
146 | { | |
147 | struct ixgbe_hw *hw = &adapter->hw; | |
148 | u32 gcr; | |
149 | u32 gpie; | |
150 | u32 vmdctl; | |
151 | ||
152 | #ifdef CONFIG_PCI_IOV | |
153 | /* disable iov and allow time for transactions to clear */ | |
154 | pci_disable_sriov(adapter->pdev); | |
155 | #endif | |
156 | ||
157 | /* turn off device IOV mode */ | |
158 | gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
159 | gcr &= ~(IXGBE_GCR_EXT_SRIOV); | |
160 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr); | |
161 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
162 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
163 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
164 | ||
165 | /* set default pool back to 0 */ | |
166 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
167 | vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; | |
168 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); | |
169 | ||
170 | /* take a breather then clean up driver data */ | |
171 | msleep(100); | |
172 | if (adapter->vfinfo) | |
173 | kfree(adapter->vfinfo); | |
174 | adapter->vfinfo = NULL; | |
175 | ||
176 | adapter->num_vfs = 0; | |
177 | adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; | |
178 | } | |
179 | ||
dcd79aeb TI |
180 | struct ixgbe_reg_info { |
181 | u32 ofs; | |
182 | char *name; | |
183 | }; | |
184 | ||
185 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
186 | ||
187 | /* General Registers */ | |
188 | {IXGBE_CTRL, "CTRL"}, | |
189 | {IXGBE_STATUS, "STATUS"}, | |
190 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
191 | ||
192 | /* Interrupt Registers */ | |
193 | {IXGBE_EICR, "EICR"}, | |
194 | ||
195 | /* RX Registers */ | |
196 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
197 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
198 | {IXGBE_RDLEN(0), "RDLEN"}, | |
199 | {IXGBE_RDH(0), "RDH"}, | |
200 | {IXGBE_RDT(0), "RDT"}, | |
201 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
202 | {IXGBE_RDBAL(0), "RDBAL"}, | |
203 | {IXGBE_RDBAH(0), "RDBAH"}, | |
204 | ||
205 | /* TX Registers */ | |
206 | {IXGBE_TDBAL(0), "TDBAL"}, | |
207 | {IXGBE_TDBAH(0), "TDBAH"}, | |
208 | {IXGBE_TDLEN(0), "TDLEN"}, | |
209 | {IXGBE_TDH(0), "TDH"}, | |
210 | {IXGBE_TDT(0), "TDT"}, | |
211 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
212 | ||
213 | /* List Terminator */ | |
214 | {} | |
215 | }; | |
216 | ||
217 | ||
218 | /* | |
219 | * ixgbe_regdump - register printout routine | |
220 | */ | |
221 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
222 | { | |
223 | int i = 0, j = 0; | |
224 | char rname[16]; | |
225 | u32 regs[64]; | |
226 | ||
227 | switch (reginfo->ofs) { | |
228 | case IXGBE_SRRCTL(0): | |
229 | for (i = 0; i < 64; i++) | |
230 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
231 | break; | |
232 | case IXGBE_DCA_RXCTRL(0): | |
233 | for (i = 0; i < 64; i++) | |
234 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
235 | break; | |
236 | case IXGBE_RDLEN(0): | |
237 | for (i = 0; i < 64; i++) | |
238 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
239 | break; | |
240 | case IXGBE_RDH(0): | |
241 | for (i = 0; i < 64; i++) | |
242 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
243 | break; | |
244 | case IXGBE_RDT(0): | |
245 | for (i = 0; i < 64; i++) | |
246 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
247 | break; | |
248 | case IXGBE_RXDCTL(0): | |
249 | for (i = 0; i < 64; i++) | |
250 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
251 | break; | |
252 | case IXGBE_RDBAL(0): | |
253 | for (i = 0; i < 64; i++) | |
254 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
255 | break; | |
256 | case IXGBE_RDBAH(0): | |
257 | for (i = 0; i < 64; i++) | |
258 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
259 | break; | |
260 | case IXGBE_TDBAL(0): | |
261 | for (i = 0; i < 64; i++) | |
262 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
263 | break; | |
264 | case IXGBE_TDBAH(0): | |
265 | for (i = 0; i < 64; i++) | |
266 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
267 | break; | |
268 | case IXGBE_TDLEN(0): | |
269 | for (i = 0; i < 64; i++) | |
270 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
271 | break; | |
272 | case IXGBE_TDH(0): | |
273 | for (i = 0; i < 64; i++) | |
274 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
275 | break; | |
276 | case IXGBE_TDT(0): | |
277 | for (i = 0; i < 64; i++) | |
278 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
279 | break; | |
280 | case IXGBE_TXDCTL(0): | |
281 | for (i = 0; i < 64; i++) | |
282 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
283 | break; | |
284 | default: | |
285 | printk(KERN_INFO "%-15s %08x\n", reginfo->name, | |
286 | IXGBE_READ_REG(hw, reginfo->ofs)); | |
287 | return; | |
288 | } | |
289 | ||
290 | for (i = 0; i < 8; i++) { | |
291 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); | |
292 | printk(KERN_ERR "%-15s ", rname); | |
293 | for (j = 0; j < 8; j++) | |
294 | printk(KERN_CONT "%08x ", regs[i*8+j]); | |
295 | printk(KERN_CONT "\n"); | |
296 | } | |
297 | ||
298 | } | |
299 | ||
300 | /* | |
301 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
302 | */ | |
303 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
304 | { | |
305 | struct net_device *netdev = adapter->netdev; | |
306 | struct ixgbe_hw *hw = &adapter->hw; | |
307 | struct ixgbe_reg_info *reginfo; | |
308 | int n = 0; | |
309 | struct ixgbe_ring *tx_ring; | |
310 | struct ixgbe_tx_buffer *tx_buffer_info; | |
311 | union ixgbe_adv_tx_desc *tx_desc; | |
312 | struct my_u0 { u64 a; u64 b; } *u0; | |
313 | struct ixgbe_ring *rx_ring; | |
314 | union ixgbe_adv_rx_desc *rx_desc; | |
315 | struct ixgbe_rx_buffer *rx_buffer_info; | |
316 | u32 staterr; | |
317 | int i = 0; | |
318 | ||
319 | if (!netif_msg_hw(adapter)) | |
320 | return; | |
321 | ||
322 | /* Print netdevice Info */ | |
323 | if (netdev) { | |
324 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
325 | printk(KERN_INFO "Device Name state " | |
326 | "trans_start last_rx\n"); | |
327 | printk(KERN_INFO "%-15s %016lX %016lX %016lX\n", | |
328 | netdev->name, | |
329 | netdev->state, | |
330 | netdev->trans_start, | |
331 | netdev->last_rx); | |
332 | } | |
333 | ||
334 | /* Print Registers */ | |
335 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
336 | printk(KERN_INFO " Register Name Value\n"); | |
337 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; | |
338 | reginfo->name; reginfo++) { | |
339 | ixgbe_regdump(hw, reginfo); | |
340 | } | |
341 | ||
342 | /* Print TX Ring Summary */ | |
343 | if (!netdev || !netif_running(netdev)) | |
344 | goto exit; | |
345 | ||
346 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
347 | printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ] " | |
348 | "leng ntw timestamp\n"); | |
349 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
350 | tx_ring = adapter->tx_ring[n]; | |
351 | tx_buffer_info = | |
352 | &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; | |
353 | printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n", | |
354 | n, tx_ring->next_to_use, tx_ring->next_to_clean, | |
355 | (u64)tx_buffer_info->dma, | |
356 | tx_buffer_info->length, | |
357 | tx_buffer_info->next_to_watch, | |
358 | (u64)tx_buffer_info->time_stamp); | |
359 | } | |
360 | ||
361 | /* Print TX Rings */ | |
362 | if (!netif_msg_tx_done(adapter)) | |
363 | goto rx_ring_summary; | |
364 | ||
365 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
366 | ||
367 | /* Transmit Descriptor Formats | |
368 | * | |
369 | * Advanced Transmit Descriptor | |
370 | * +--------------------------------------------------------------+ | |
371 | * 0 | Buffer Address [63:0] | | |
372 | * +--------------------------------------------------------------+ | |
373 | * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | | |
374 | * +--------------------------------------------------------------+ | |
375 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
376 | */ | |
377 | ||
378 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
379 | tx_ring = adapter->tx_ring[n]; | |
380 | printk(KERN_INFO "------------------------------------\n"); | |
381 | printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
382 | printk(KERN_INFO "------------------------------------\n"); | |
383 | printk(KERN_INFO "T [desc] [address 63:0 ] " | |
384 | "[PlPOIdStDDt Ln] [bi->dma ] " | |
385 | "leng ntw timestamp bi->skb\n"); | |
386 | ||
387 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
388 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); | |
389 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
390 | u0 = (struct my_u0 *)tx_desc; | |
391 | printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX" | |
392 | " %04X %3X %016llX %p", i, | |
393 | le64_to_cpu(u0->a), | |
394 | le64_to_cpu(u0->b), | |
395 | (u64)tx_buffer_info->dma, | |
396 | tx_buffer_info->length, | |
397 | tx_buffer_info->next_to_watch, | |
398 | (u64)tx_buffer_info->time_stamp, | |
399 | tx_buffer_info->skb); | |
400 | if (i == tx_ring->next_to_use && | |
401 | i == tx_ring->next_to_clean) | |
402 | printk(KERN_CONT " NTC/U\n"); | |
403 | else if (i == tx_ring->next_to_use) | |
404 | printk(KERN_CONT " NTU\n"); | |
405 | else if (i == tx_ring->next_to_clean) | |
406 | printk(KERN_CONT " NTC\n"); | |
407 | else | |
408 | printk(KERN_CONT "\n"); | |
409 | ||
410 | if (netif_msg_pktdata(adapter) && | |
411 | tx_buffer_info->dma != 0) | |
412 | print_hex_dump(KERN_INFO, "", | |
413 | DUMP_PREFIX_ADDRESS, 16, 1, | |
414 | phys_to_virt(tx_buffer_info->dma), | |
415 | tx_buffer_info->length, true); | |
416 | } | |
417 | } | |
418 | ||
419 | /* Print RX Rings Summary */ | |
420 | rx_ring_summary: | |
421 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
422 | printk(KERN_INFO "Queue [NTU] [NTC]\n"); | |
423 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
424 | rx_ring = adapter->rx_ring[n]; | |
425 | printk(KERN_INFO "%5d %5X %5X\n", n, | |
426 | rx_ring->next_to_use, rx_ring->next_to_clean); | |
427 | } | |
428 | ||
429 | /* Print RX Rings */ | |
430 | if (!netif_msg_rx_status(adapter)) | |
431 | goto exit; | |
432 | ||
433 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
434 | ||
435 | /* Advanced Receive Descriptor (Read) Format | |
436 | * 63 1 0 | |
437 | * +-----------------------------------------------------+ | |
438 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
439 | * +----------------------------------------------+------+ | |
440 | * 8 | Header Buffer Address [63:1] | DD | | |
441 | * +-----------------------------------------------------+ | |
442 | * | |
443 | * | |
444 | * Advanced Receive Descriptor (Write-Back) Format | |
445 | * | |
446 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
447 | * +------------------------------------------------------+ | |
448 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
449 | * | Checksum Ident | | | | Type | Type | | |
450 | * +------------------------------------------------------+ | |
451 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
452 | * +------------------------------------------------------+ | |
453 | * 63 48 47 32 31 20 19 0 | |
454 | */ | |
455 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
456 | rx_ring = adapter->rx_ring[n]; | |
457 | printk(KERN_INFO "------------------------------------\n"); | |
458 | printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
459 | printk(KERN_INFO "------------------------------------\n"); | |
460 | printk(KERN_INFO "R [desc] [ PktBuf A0] " | |
461 | "[ HeadBuf DD] [bi->dma ] [bi->skb] " | |
462 | "<-- Adv Rx Read format\n"); | |
463 | printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] " | |
464 | "[vl er S cks ln] ---------------- [bi->skb] " | |
465 | "<-- Adv Rx Write-Back format\n"); | |
466 | ||
467 | for (i = 0; i < rx_ring->count; i++) { | |
468 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
469 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
470 | u0 = (struct my_u0 *)rx_desc; | |
471 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
472 | if (staterr & IXGBE_RXD_STAT_DD) { | |
473 | /* Descriptor Done */ | |
474 | printk(KERN_INFO "RWB[0x%03X] %016llX " | |
475 | "%016llX ---------------- %p", i, | |
476 | le64_to_cpu(u0->a), | |
477 | le64_to_cpu(u0->b), | |
478 | rx_buffer_info->skb); | |
479 | } else { | |
480 | printk(KERN_INFO "R [0x%03X] %016llX " | |
481 | "%016llX %016llX %p", i, | |
482 | le64_to_cpu(u0->a), | |
483 | le64_to_cpu(u0->b), | |
484 | (u64)rx_buffer_info->dma, | |
485 | rx_buffer_info->skb); | |
486 | ||
487 | if (netif_msg_pktdata(adapter)) { | |
488 | print_hex_dump(KERN_INFO, "", | |
489 | DUMP_PREFIX_ADDRESS, 16, 1, | |
490 | phys_to_virt(rx_buffer_info->dma), | |
491 | rx_ring->rx_buf_len, true); | |
492 | ||
493 | if (rx_ring->rx_buf_len | |
494 | < IXGBE_RXBUFFER_2048) | |
495 | print_hex_dump(KERN_INFO, "", | |
496 | DUMP_PREFIX_ADDRESS, 16, 1, | |
497 | phys_to_virt( | |
498 | rx_buffer_info->page_dma + | |
499 | rx_buffer_info->page_offset | |
500 | ), | |
501 | PAGE_SIZE/2, true); | |
502 | } | |
503 | } | |
504 | ||
505 | if (i == rx_ring->next_to_use) | |
506 | printk(KERN_CONT " NTU\n"); | |
507 | else if (i == rx_ring->next_to_clean) | |
508 | printk(KERN_CONT " NTC\n"); | |
509 | else | |
510 | printk(KERN_CONT "\n"); | |
511 | ||
512 | } | |
513 | } | |
514 | ||
515 | exit: | |
516 | return; | |
517 | } | |
518 | ||
5eba3699 AV |
519 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
520 | { | |
521 | u32 ctrl_ext; | |
522 | ||
523 | /* Let firmware take over control of h/w */ | |
524 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
525 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 526 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
527 | } |
528 | ||
529 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
530 | { | |
531 | u32 ctrl_ext; | |
532 | ||
533 | /* Let firmware know the driver has taken over */ | |
534 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
535 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 536 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 537 | } |
9a799d71 | 538 | |
e8e26350 PW |
539 | /* |
540 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
541 | * @adapter: pointer to adapter struct | |
542 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
543 | * @queue: queue to map the corresponding interrupt to | |
544 | * @msix_vector: the vector to map to the corresponding queue | |
545 | * | |
546 | */ | |
547 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
548 | u8 queue, u8 msix_vector) | |
9a799d71 AK |
549 | { |
550 | u32 ivar, index; | |
e8e26350 PW |
551 | struct ixgbe_hw *hw = &adapter->hw; |
552 | switch (hw->mac.type) { | |
553 | case ixgbe_mac_82598EB: | |
554 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
555 | if (direction == -1) | |
556 | direction = 0; | |
557 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
558 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
559 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
560 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
561 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
562 | break; | |
563 | case ixgbe_mac_82599EB: | |
564 | if (direction == -1) { | |
565 | /* other causes */ | |
566 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
567 | index = ((queue & 1) * 8); | |
568 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
569 | ivar &= ~(0xFF << index); | |
570 | ivar |= (msix_vector << index); | |
571 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
572 | break; | |
573 | } else { | |
574 | /* tx or rx causes */ | |
575 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
576 | index = ((16 * (queue & 1)) + (8 * direction)); | |
577 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
578 | ivar &= ~(0xFF << index); | |
579 | ivar |= (msix_vector << index); | |
580 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
581 | break; | |
582 | } | |
583 | default: | |
584 | break; | |
585 | } | |
9a799d71 AK |
586 | } |
587 | ||
fe49f04a AD |
588 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
589 | u64 qmask) | |
590 | { | |
591 | u32 mask; | |
592 | ||
593 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
594 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
595 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
596 | } else { | |
597 | mask = (qmask & 0xFFFFFFFF); | |
598 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
599 | mask = (qmask >> 32); | |
600 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
601 | } | |
602 | } | |
603 | ||
9a799d71 | 604 | static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter, |
b4617240 PW |
605 | struct ixgbe_tx_buffer |
606 | *tx_buffer_info) | |
9a799d71 | 607 | { |
e5a43549 AD |
608 | if (tx_buffer_info->dma) { |
609 | if (tx_buffer_info->mapped_as_page) | |
1b507730 | 610 | dma_unmap_page(&adapter->pdev->dev, |
e5a43549 AD |
611 | tx_buffer_info->dma, |
612 | tx_buffer_info->length, | |
1b507730 | 613 | DMA_TO_DEVICE); |
e5a43549 | 614 | else |
1b507730 | 615 | dma_unmap_single(&adapter->pdev->dev, |
e5a43549 AD |
616 | tx_buffer_info->dma, |
617 | tx_buffer_info->length, | |
1b507730 | 618 | DMA_TO_DEVICE); |
e5a43549 AD |
619 | tx_buffer_info->dma = 0; |
620 | } | |
9a799d71 AK |
621 | if (tx_buffer_info->skb) { |
622 | dev_kfree_skb_any(tx_buffer_info->skb); | |
623 | tx_buffer_info->skb = NULL; | |
624 | } | |
44df32c5 | 625 | tx_buffer_info->time_stamp = 0; |
9a799d71 AK |
626 | /* tx_buffer_info must be completely set up in the transmit path */ |
627 | } | |
628 | ||
26f23d82 | 629 | /** |
7483d9dd | 630 | * ixgbe_tx_xon_state - check the tx ring xon state |
26f23d82 YZ |
631 | * @adapter: the ixgbe adapter |
632 | * @tx_ring: the corresponding tx_ring | |
633 | * | |
634 | * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the | |
635 | * corresponding TC of this tx_ring when checking TFCS. | |
636 | * | |
7483d9dd | 637 | * Returns : true if in xon state (currently not paused) |
26f23d82 | 638 | */ |
7483d9dd | 639 | static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter, |
26f23d82 YZ |
640 | struct ixgbe_ring *tx_ring) |
641 | { | |
26f23d82 YZ |
642 | u32 txoff = IXGBE_TFCS_TXOFF; |
643 | ||
644 | #ifdef CONFIG_IXGBE_DCB | |
ca739481 | 645 | if (adapter->dcb_cfg.pfc_mode_enable) { |
30b76832 | 646 | int tc; |
26f23d82 YZ |
647 | int reg_idx = tx_ring->reg_idx; |
648 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
649 | ||
6837e895 PW |
650 | switch (adapter->hw.mac.type) { |
651 | case ixgbe_mac_82598EB: | |
26f23d82 YZ |
652 | tc = reg_idx >> 2; |
653 | txoff = IXGBE_TFCS_TXOFF0; | |
6837e895 PW |
654 | break; |
655 | case ixgbe_mac_82599EB: | |
26f23d82 YZ |
656 | tc = 0; |
657 | txoff = IXGBE_TFCS_TXOFF; | |
658 | if (dcb_i == 8) { | |
659 | /* TC0, TC1 */ | |
660 | tc = reg_idx >> 5; | |
661 | if (tc == 2) /* TC2, TC3 */ | |
662 | tc += (reg_idx - 64) >> 4; | |
663 | else if (tc == 3) /* TC4, TC5, TC6, TC7 */ | |
664 | tc += 1 + ((reg_idx - 96) >> 3); | |
665 | } else if (dcb_i == 4) { | |
666 | /* TC0, TC1 */ | |
667 | tc = reg_idx >> 6; | |
668 | if (tc == 1) { | |
669 | tc += (reg_idx - 64) >> 5; | |
670 | if (tc == 2) /* TC2, TC3 */ | |
671 | tc += (reg_idx - 96) >> 4; | |
672 | } | |
673 | } | |
6837e895 PW |
674 | break; |
675 | default: | |
676 | tc = 0; | |
26f23d82 YZ |
677 | } |
678 | txoff <<= tc; | |
679 | } | |
680 | #endif | |
681 | return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff; | |
682 | } | |
683 | ||
9a799d71 | 684 | static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter, |
b4617240 PW |
685 | struct ixgbe_ring *tx_ring, |
686 | unsigned int eop) | |
9a799d71 | 687 | { |
e01c31a5 | 688 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 689 | |
9a799d71 | 690 | /* Detect a transmit hang in hardware, this serializes the |
e01c31a5 | 691 | * check with the clearing of time_stamp and movement of eop */ |
9a799d71 | 692 | adapter->detect_tx_hung = false; |
44df32c5 | 693 | if (tx_ring->tx_buffer_info[eop].time_stamp && |
9a799d71 | 694 | time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) && |
7483d9dd | 695 | ixgbe_tx_xon_state(adapter, tx_ring)) { |
9a799d71 | 696 | /* detected Tx unit hang */ |
e01c31a5 JB |
697 | union ixgbe_adv_tx_desc *tx_desc; |
698 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
9a799d71 | 699 | DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n" |
e01c31a5 JB |
700 | " Tx Queue <%d>\n" |
701 | " TDH, TDT <%x>, <%x>\n" | |
9a799d71 AK |
702 | " next_to_use <%x>\n" |
703 | " next_to_clean <%x>\n" | |
704 | "tx_buffer_info[next_to_clean]\n" | |
705 | " time_stamp <%lx>\n" | |
e01c31a5 JB |
706 | " jiffies <%lx>\n", |
707 | tx_ring->queue_index, | |
44df32c5 AD |
708 | IXGBE_READ_REG(hw, tx_ring->head), |
709 | IXGBE_READ_REG(hw, tx_ring->tail), | |
e01c31a5 JB |
710 | tx_ring->next_to_use, eop, |
711 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
9a799d71 AK |
712 | return true; |
713 | } | |
714 | ||
715 | return false; | |
716 | } | |
717 | ||
b4617240 PW |
718 | #define IXGBE_MAX_TXD_PWR 14 |
719 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
720 | |
721 | /* Tx Descriptors needed, worst case */ | |
722 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
723 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
724 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 725 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 726 | |
e01c31a5 JB |
727 | static void ixgbe_tx_timeout(struct net_device *netdev); |
728 | ||
9a799d71 AK |
729 | /** |
730 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 731 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 732 | * @tx_ring: tx ring to clean |
9a799d71 | 733 | **/ |
fe49f04a | 734 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e01c31a5 | 735 | struct ixgbe_ring *tx_ring) |
9a799d71 | 736 | { |
fe49f04a | 737 | struct ixgbe_adapter *adapter = q_vector->adapter; |
e01c31a5 | 738 | struct net_device *netdev = adapter->netdev; |
12207e49 PWJ |
739 | union ixgbe_adv_tx_desc *tx_desc, *eop_desc; |
740 | struct ixgbe_tx_buffer *tx_buffer_info; | |
741 | unsigned int i, eop, count = 0; | |
e01c31a5 | 742 | unsigned int total_bytes = 0, total_packets = 0; |
9a799d71 AK |
743 | |
744 | i = tx_ring->next_to_clean; | |
12207e49 PWJ |
745 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
746 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
747 | ||
748 | while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && | |
9a1a69ad | 749 | (count < tx_ring->work_limit)) { |
12207e49 PWJ |
750 | bool cleaned = false; |
751 | for ( ; !cleaned; count++) { | |
752 | struct sk_buff *skb; | |
9a799d71 AK |
753 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); |
754 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
12207e49 | 755 | cleaned = (i == eop); |
e01c31a5 | 756 | skb = tx_buffer_info->skb; |
9a799d71 | 757 | |
12207e49 | 758 | if (cleaned && skb) { |
e092be60 | 759 | unsigned int segs, bytecount; |
3d8fd385 | 760 | unsigned int hlen = skb_headlen(skb); |
e01c31a5 JB |
761 | |
762 | /* gso_segs is currently only valid for tcp */ | |
e092be60 | 763 | segs = skb_shinfo(skb)->gso_segs ?: 1; |
3d8fd385 YZ |
764 | #ifdef IXGBE_FCOE |
765 | /* adjust for FCoE Sequence Offload */ | |
766 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
767 | && (skb->protocol == htons(ETH_P_FCOE)) && | |
768 | skb_is_gso(skb)) { | |
769 | hlen = skb_transport_offset(skb) + | |
770 | sizeof(struct fc_frame_header) + | |
771 | sizeof(struct fcoe_crc_eof); | |
772 | segs = DIV_ROUND_UP(skb->len - hlen, | |
773 | skb_shinfo(skb)->gso_size); | |
774 | } | |
775 | #endif /* IXGBE_FCOE */ | |
e092be60 | 776 | /* multiply data chunks by size of headers */ |
3d8fd385 | 777 | bytecount = ((segs - 1) * hlen) + skb->len; |
e01c31a5 JB |
778 | total_packets += segs; |
779 | total_bytes += bytecount; | |
e092be60 | 780 | } |
e01c31a5 | 781 | |
9a799d71 | 782 | ixgbe_unmap_and_free_tx_resource(adapter, |
e01c31a5 | 783 | tx_buffer_info); |
9a799d71 | 784 | |
12207e49 PWJ |
785 | tx_desc->wb.status = 0; |
786 | ||
9a799d71 AK |
787 | i++; |
788 | if (i == tx_ring->count) | |
789 | i = 0; | |
e01c31a5 | 790 | } |
12207e49 PWJ |
791 | |
792 | eop = tx_ring->tx_buffer_info[i].next_to_watch; | |
793 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
794 | } | |
795 | ||
9a799d71 AK |
796 | tx_ring->next_to_clean = i; |
797 | ||
e092be60 | 798 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
e01c31a5 JB |
799 | if (unlikely(count && netif_carrier_ok(netdev) && |
800 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
e092be60 AV |
801 | /* Make sure that anybody stopping the queue after this |
802 | * sees the new next_to_clean. | |
803 | */ | |
804 | smp_mb(); | |
30eba97a AV |
805 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
806 | !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
807 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
7ca3bc58 | 808 | ++tx_ring->restart_queue; |
30eba97a | 809 | } |
e092be60 | 810 | } |
9a799d71 | 811 | |
e01c31a5 JB |
812 | if (adapter->detect_tx_hung) { |
813 | if (ixgbe_check_tx_hang(adapter, tx_ring, i)) { | |
814 | /* schedule immediate reset if we believe we hung */ | |
815 | DPRINTK(PROBE, INFO, | |
816 | "tx hang %d detected, resetting adapter\n", | |
817 | adapter->tx_timeout_count + 1); | |
818 | ixgbe_tx_timeout(adapter->netdev); | |
819 | } | |
820 | } | |
9a799d71 | 821 | |
e01c31a5 | 822 | /* re-arm the interrupt */ |
fe49f04a AD |
823 | if (count >= tx_ring->work_limit) |
824 | ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
9a799d71 | 825 | |
e01c31a5 JB |
826 | tx_ring->total_bytes += total_bytes; |
827 | tx_ring->total_packets += total_packets; | |
e01c31a5 | 828 | tx_ring->stats.packets += total_packets; |
12207e49 | 829 | tx_ring->stats.bytes += total_bytes; |
9a1a69ad | 830 | return (count < tx_ring->work_limit); |
9a799d71 AK |
831 | } |
832 | ||
5dd2d332 | 833 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 834 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
b4617240 | 835 | struct ixgbe_ring *rx_ring) |
bd0362dd JC |
836 | { |
837 | u32 rxctrl; | |
838 | int cpu = get_cpu(); | |
4a0b9ca0 | 839 | int q = rx_ring->reg_idx; |
bd0362dd | 840 | |
3a581073 | 841 | if (rx_ring->cpu != cpu) { |
bd0362dd | 842 | rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q)); |
e8e26350 PW |
843 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
844 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
845 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
846 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
847 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; | |
848 | rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
849 | IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); | |
850 | } | |
bd0362dd JC |
851 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
852 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
15005a32 DS |
853 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); |
854 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | | |
e8e26350 | 855 | IXGBE_DCA_RXCTRL_DESC_HSRO_EN); |
bd0362dd | 856 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); |
3a581073 | 857 | rx_ring->cpu = cpu; |
bd0362dd JC |
858 | } |
859 | put_cpu(); | |
860 | } | |
861 | ||
862 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
b4617240 | 863 | struct ixgbe_ring *tx_ring) |
bd0362dd JC |
864 | { |
865 | u32 txctrl; | |
866 | int cpu = get_cpu(); | |
4a0b9ca0 | 867 | int q = tx_ring->reg_idx; |
ee5f784a | 868 | struct ixgbe_hw *hw = &adapter->hw; |
bd0362dd | 869 | |
3a581073 | 870 | if (tx_ring->cpu != cpu) { |
e8e26350 | 871 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
ee5f784a | 872 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q)); |
e8e26350 PW |
873 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; |
874 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
ee5f784a DS |
875 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
876 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl); | |
e8e26350 | 877 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
ee5f784a | 878 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q)); |
e8e26350 PW |
879 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; |
880 | txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
ee5f784a DS |
881 | IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); |
882 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
883 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl); | |
e8e26350 | 884 | } |
3a581073 | 885 | tx_ring->cpu = cpu; |
bd0362dd JC |
886 | } |
887 | put_cpu(); | |
888 | } | |
889 | ||
890 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
891 | { | |
892 | int i; | |
893 | ||
894 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
895 | return; | |
896 | ||
e35ec126 AD |
897 | /* always use CB2 mode, difference is masked in the CB driver */ |
898 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
899 | ||
bd0362dd | 900 | for (i = 0; i < adapter->num_tx_queues; i++) { |
4a0b9ca0 PW |
901 | adapter->tx_ring[i]->cpu = -1; |
902 | ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]); | |
bd0362dd JC |
903 | } |
904 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4a0b9ca0 PW |
905 | adapter->rx_ring[i]->cpu = -1; |
906 | ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]); | |
bd0362dd JC |
907 | } |
908 | } | |
909 | ||
910 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
911 | { | |
912 | struct net_device *netdev = dev_get_drvdata(dev); | |
913 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
914 | unsigned long event = *(unsigned long *)data; | |
915 | ||
916 | switch (event) { | |
917 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
918 | /* if we're already enabled, don't do it again */ |
919 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
920 | break; | |
652f093f | 921 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 922 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
923 | ixgbe_setup_dca(adapter); |
924 | break; | |
925 | } | |
926 | /* Fall Through since DCA is disabled. */ | |
927 | case DCA_PROVIDER_REMOVE: | |
928 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
929 | dca_remove_requester(dev); | |
930 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
931 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
932 | } | |
933 | break; | |
934 | } | |
935 | ||
652f093f | 936 | return 0; |
bd0362dd JC |
937 | } |
938 | ||
5dd2d332 | 939 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
940 | /** |
941 | * ixgbe_receive_skb - Send a completed packet up the stack | |
942 | * @adapter: board private structure | |
943 | * @skb: packet to send up | |
177db6ff MC |
944 | * @status: hardware indication of status of receive |
945 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
946 | * @rx_desc: rx descriptor | |
9a799d71 | 947 | **/ |
78b6f4ce | 948 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
b4617240 | 949 | struct sk_buff *skb, u8 status, |
fdaff1ce | 950 | struct ixgbe_ring *ring, |
177db6ff | 951 | union ixgbe_adv_rx_desc *rx_desc) |
9a799d71 | 952 | { |
78b6f4ce HX |
953 | struct ixgbe_adapter *adapter = q_vector->adapter; |
954 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
955 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
956 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 957 | |
fdaff1ce | 958 | skb_record_rx_queue(skb, ring->queue_index); |
182ff8df | 959 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { |
8a62babf | 960 | if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK)) |
78b6f4ce | 961 | vlan_gro_receive(napi, adapter->vlgrp, tag, skb); |
9a799d71 | 962 | else |
78b6f4ce | 963 | napi_gro_receive(napi, skb); |
177db6ff | 964 | } else { |
8a62babf | 965 | if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK)) |
182ff8df AD |
966 | vlan_hwaccel_rx(skb, adapter->vlgrp, tag); |
967 | else | |
968 | netif_rx(skb); | |
9a799d71 AK |
969 | } |
970 | } | |
971 | ||
e59bd25d AV |
972 | /** |
973 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
974 | * @adapter: address of board private structure | |
975 | * @status_err: hardware indication of status of receive | |
976 | * @skb: skb currently being received and modified | |
977 | **/ | |
9a799d71 | 978 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
8bae1b2b DS |
979 | union ixgbe_adv_rx_desc *rx_desc, |
980 | struct sk_buff *skb) | |
9a799d71 | 981 | { |
8bae1b2b DS |
982 | u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error); |
983 | ||
9a799d71 AK |
984 | skb->ip_summed = CHECKSUM_NONE; |
985 | ||
712744be JB |
986 | /* Rx csum disabled */ |
987 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 988 | return; |
e59bd25d AV |
989 | |
990 | /* if IP and error */ | |
991 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
992 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
993 | adapter->hw_csum_rx_error++; |
994 | return; | |
995 | } | |
e59bd25d AV |
996 | |
997 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
998 | return; | |
999 | ||
1000 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
8bae1b2b DS |
1001 | u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
1002 | ||
1003 | /* | |
1004 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
1005 | * checksum errors. | |
1006 | */ | |
1007 | if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) && | |
1008 | (adapter->hw.mac.type == ixgbe_mac_82599EB)) | |
1009 | return; | |
1010 | ||
e59bd25d AV |
1011 | adapter->hw_csum_rx_error++; |
1012 | return; | |
1013 | } | |
1014 | ||
9a799d71 | 1015 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 1016 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
1017 | } |
1018 | ||
e8e26350 PW |
1019 | static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw, |
1020 | struct ixgbe_ring *rx_ring, u32 val) | |
1021 | { | |
1022 | /* | |
1023 | * Force memory writes to complete before letting h/w | |
1024 | * know there are new descriptors to fetch. (Only | |
1025 | * applicable for weak-ordered memory model archs, | |
1026 | * such as IA-64). | |
1027 | */ | |
1028 | wmb(); | |
1029 | IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val); | |
1030 | } | |
1031 | ||
9a799d71 AK |
1032 | /** |
1033 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
1034 | * @adapter: address of board private structure | |
1035 | **/ | |
1036 | static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter, | |
7c6e0a43 JB |
1037 | struct ixgbe_ring *rx_ring, |
1038 | int cleaned_count) | |
9a799d71 | 1039 | { |
9a799d71 AK |
1040 | struct pci_dev *pdev = adapter->pdev; |
1041 | union ixgbe_adv_rx_desc *rx_desc; | |
3a581073 | 1042 | struct ixgbe_rx_buffer *bi; |
9a799d71 | 1043 | unsigned int i; |
9a799d71 AK |
1044 | |
1045 | i = rx_ring->next_to_use; | |
3a581073 | 1046 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
1047 | |
1048 | while (cleaned_count--) { | |
1049 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
1050 | ||
762f4c57 | 1051 | if (!bi->page_dma && |
6e455b89 | 1052 | (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) { |
3a581073 | 1053 | if (!bi->page) { |
762f4c57 JB |
1054 | bi->page = alloc_page(GFP_ATOMIC); |
1055 | if (!bi->page) { | |
1056 | adapter->alloc_rx_page_failed++; | |
1057 | goto no_buffers; | |
1058 | } | |
1059 | bi->page_offset = 0; | |
1060 | } else { | |
1061 | /* use a half page if we're re-using */ | |
1062 | bi->page_offset ^= (PAGE_SIZE / 2); | |
9a799d71 | 1063 | } |
762f4c57 | 1064 | |
1b507730 | 1065 | bi->page_dma = dma_map_page(&pdev->dev, bi->page, |
762f4c57 JB |
1066 | bi->page_offset, |
1067 | (PAGE_SIZE / 2), | |
1b507730 | 1068 | DMA_FROM_DEVICE); |
9a799d71 AK |
1069 | } |
1070 | ||
3a581073 | 1071 | if (!bi->skb) { |
5ecc3614 | 1072 | struct sk_buff *skb; |
7ca3bc58 JB |
1073 | /* netdev_alloc_skb reserves 32 bytes up front!! */ |
1074 | uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES; | |
1075 | skb = netdev_alloc_skb(adapter->netdev, bufsz); | |
9a799d71 AK |
1076 | |
1077 | if (!skb) { | |
1078 | adapter->alloc_rx_buff_failed++; | |
1079 | goto no_buffers; | |
1080 | } | |
1081 | ||
7ca3bc58 JB |
1082 | /* advance the data pointer to the next cache line */ |
1083 | skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES) | |
1084 | - skb->data)); | |
1085 | ||
3a581073 | 1086 | bi->skb = skb; |
1b507730 | 1087 | bi->dma = dma_map_single(&pdev->dev, skb->data, |
4f57ca6e | 1088 | rx_ring->rx_buf_len, |
1b507730 | 1089 | DMA_FROM_DEVICE); |
9a799d71 AK |
1090 | } |
1091 | /* Refresh the desc even if buffer_addrs didn't change because | |
1092 | * each write-back erases this info. */ | |
6e455b89 | 1093 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
3a581073 JB |
1094 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
1095 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 1096 | } else { |
3a581073 | 1097 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
9a799d71 AK |
1098 | } |
1099 | ||
1100 | i++; | |
1101 | if (i == rx_ring->count) | |
1102 | i = 0; | |
3a581073 | 1103 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 | 1104 | } |
7c6e0a43 | 1105 | |
9a799d71 AK |
1106 | no_buffers: |
1107 | if (rx_ring->next_to_use != i) { | |
1108 | rx_ring->next_to_use = i; | |
1109 | if (i-- == 0) | |
1110 | i = (rx_ring->count - 1); | |
1111 | ||
e8e26350 | 1112 | ixgbe_release_rx_desc(&adapter->hw, rx_ring, i); |
9a799d71 AK |
1113 | } |
1114 | } | |
1115 | ||
7c6e0a43 JB |
1116 | static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc) |
1117 | { | |
1118 | return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
1119 | } | |
1120 | ||
1121 | static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc) | |
1122 | { | |
1123 | return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
1124 | } | |
1125 | ||
f8212f97 AD |
1126 | static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc) |
1127 | { | |
1128 | return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) & | |
1129 | IXGBE_RXDADV_RSCCNT_MASK) >> | |
1130 | IXGBE_RXDADV_RSCCNT_SHIFT; | |
1131 | } | |
1132 | ||
1133 | /** | |
1134 | * ixgbe_transform_rsc_queue - change rsc queue into a full packet | |
1135 | * @skb: pointer to the last skb in the rsc queue | |
94b982b2 | 1136 | * @count: pointer to number of packets coalesced in this context |
f8212f97 AD |
1137 | * |
1138 | * This function changes a queue full of hw rsc buffers into a completed | |
1139 | * packet. It uses the ->prev pointers to find the first packet and then | |
1140 | * turns it into the frag list owner. | |
1141 | **/ | |
94b982b2 MC |
1142 | static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb, |
1143 | u64 *count) | |
f8212f97 AD |
1144 | { |
1145 | unsigned int frag_list_size = 0; | |
1146 | ||
1147 | while (skb->prev) { | |
1148 | struct sk_buff *prev = skb->prev; | |
1149 | frag_list_size += skb->len; | |
1150 | skb->prev = NULL; | |
1151 | skb = prev; | |
94b982b2 | 1152 | *count += 1; |
f8212f97 AD |
1153 | } |
1154 | ||
1155 | skb_shinfo(skb)->frag_list = skb->next; | |
1156 | skb->next = NULL; | |
1157 | skb->len += frag_list_size; | |
1158 | skb->data_len += frag_list_size; | |
1159 | skb->truesize += frag_list_size; | |
1160 | return skb; | |
1161 | } | |
1162 | ||
43634e82 MC |
1163 | struct ixgbe_rsc_cb { |
1164 | dma_addr_t dma; | |
e8171aaa | 1165 | bool delay_unmap; |
43634e82 MC |
1166 | }; |
1167 | ||
1168 | #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb) | |
1169 | ||
78b6f4ce | 1170 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
b4617240 PW |
1171 | struct ixgbe_ring *rx_ring, |
1172 | int *work_done, int work_to_do) | |
9a799d71 | 1173 | { |
78b6f4ce | 1174 | struct ixgbe_adapter *adapter = q_vector->adapter; |
2d86f139 | 1175 | struct net_device *netdev = adapter->netdev; |
9a799d71 AK |
1176 | struct pci_dev *pdev = adapter->pdev; |
1177 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; | |
1178 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
1179 | struct sk_buff *skb; | |
f8212f97 | 1180 | unsigned int i, rsc_count = 0; |
7c6e0a43 | 1181 | u32 len, staterr; |
177db6ff MC |
1182 | u16 hdr_info; |
1183 | bool cleaned = false; | |
9a799d71 | 1184 | int cleaned_count = 0; |
d2f4fbe2 | 1185 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
3d8fd385 YZ |
1186 | #ifdef IXGBE_FCOE |
1187 | int ddp_bytes = 0; | |
1188 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
1189 | |
1190 | i = rx_ring->next_to_clean; | |
9a799d71 AK |
1191 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); |
1192 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
1193 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
9a799d71 AK |
1194 | |
1195 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 1196 | u32 upper_len = 0; |
9a799d71 AK |
1197 | if (*work_done >= work_to_do) |
1198 | break; | |
1199 | (*work_done)++; | |
1200 | ||
3c945e5b | 1201 | rmb(); /* read descriptor and rx_buffer_info after status DD */ |
6e455b89 | 1202 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
7c6e0a43 JB |
1203 | hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); |
1204 | len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
762f4c57 | 1205 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; |
9a799d71 | 1206 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); |
0b746e08 SN |
1207 | if ((len > IXGBE_RX_HDR_SIZE) || |
1208 | (upper_len && !(hdr_info & IXGBE_RXDADV_SPH))) | |
1209 | len = IXGBE_RX_HDR_SIZE; | |
7c6e0a43 | 1210 | } else { |
9a799d71 | 1211 | len = le16_to_cpu(rx_desc->wb.upper.length); |
7c6e0a43 | 1212 | } |
9a799d71 AK |
1213 | |
1214 | cleaned = true; | |
1215 | skb = rx_buffer_info->skb; | |
7ca3bc58 | 1216 | prefetch(skb->data); |
9a799d71 AK |
1217 | rx_buffer_info->skb = NULL; |
1218 | ||
21fa4e66 | 1219 | if (rx_buffer_info->dma) { |
43634e82 MC |
1220 | if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && |
1221 | (!(staterr & IXGBE_RXD_STAT_EOP)) && | |
e8171aaa | 1222 | (!(skb->prev))) { |
43634e82 MC |
1223 | /* |
1224 | * When HWRSC is enabled, delay unmapping | |
1225 | * of the first packet. It carries the | |
1226 | * header information, HW may still | |
1227 | * access the header after the writeback. | |
1228 | * Only unmap it when EOP is reached | |
1229 | */ | |
e8171aaa | 1230 | IXGBE_RSC_CB(skb)->delay_unmap = true; |
43634e82 | 1231 | IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma; |
e8171aaa | 1232 | } else { |
1b507730 | 1233 | dma_unmap_single(&pdev->dev, |
e8171aaa | 1234 | rx_buffer_info->dma, |
43634e82 | 1235 | rx_ring->rx_buf_len, |
e8171aaa MC |
1236 | DMA_FROM_DEVICE); |
1237 | } | |
4f57ca6e | 1238 | rx_buffer_info->dma = 0; |
9a799d71 AK |
1239 | skb_put(skb, len); |
1240 | } | |
1241 | ||
1242 | if (upper_len) { | |
1b507730 NN |
1243 | dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma, |
1244 | PAGE_SIZE / 2, DMA_FROM_DEVICE); | |
9a799d71 AK |
1245 | rx_buffer_info->page_dma = 0; |
1246 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
762f4c57 JB |
1247 | rx_buffer_info->page, |
1248 | rx_buffer_info->page_offset, | |
1249 | upper_len); | |
1250 | ||
1251 | if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) || | |
1252 | (page_count(rx_buffer_info->page) != 1)) | |
1253 | rx_buffer_info->page = NULL; | |
1254 | else | |
1255 | get_page(rx_buffer_info->page); | |
9a799d71 AK |
1256 | |
1257 | skb->len += upper_len; | |
1258 | skb->data_len += upper_len; | |
1259 | skb->truesize += upper_len; | |
1260 | } | |
1261 | ||
1262 | i++; | |
1263 | if (i == rx_ring->count) | |
1264 | i = 0; | |
9a799d71 AK |
1265 | |
1266 | next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
1267 | prefetch(next_rxd); | |
9a799d71 | 1268 | cleaned_count++; |
f8212f97 | 1269 | |
0c19d6af | 1270 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
f8212f97 AD |
1271 | rsc_count = ixgbe_get_rsc_count(rx_desc); |
1272 | ||
1273 | if (rsc_count) { | |
1274 | u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >> | |
1275 | IXGBE_RXDADV_NEXTP_SHIFT; | |
1276 | next_buffer = &rx_ring->rx_buffer_info[nextp]; | |
f8212f97 AD |
1277 | } else { |
1278 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
1279 | } | |
1280 | ||
9a799d71 | 1281 | if (staterr & IXGBE_RXD_STAT_EOP) { |
f8212f97 | 1282 | if (skb->prev) |
94b982b2 MC |
1283 | skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count)); |
1284 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { | |
e8171aaa | 1285 | if (IXGBE_RSC_CB(skb)->delay_unmap) { |
1b507730 NN |
1286 | dma_unmap_single(&pdev->dev, |
1287 | IXGBE_RSC_CB(skb)->dma, | |
43634e82 | 1288 | rx_ring->rx_buf_len, |
1b507730 | 1289 | DMA_FROM_DEVICE); |
fd3686a8 | 1290 | IXGBE_RSC_CB(skb)->dma = 0; |
e8171aaa | 1291 | IXGBE_RSC_CB(skb)->delay_unmap = false; |
fd3686a8 | 1292 | } |
94b982b2 MC |
1293 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) |
1294 | rx_ring->rsc_count += skb_shinfo(skb)->nr_frags; | |
1295 | else | |
1296 | rx_ring->rsc_count++; | |
1297 | rx_ring->rsc_flush++; | |
1298 | } | |
9a799d71 AK |
1299 | rx_ring->stats.packets++; |
1300 | rx_ring->stats.bytes += skb->len; | |
1301 | } else { | |
6e455b89 | 1302 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
f8212f97 AD |
1303 | rx_buffer_info->skb = next_buffer->skb; |
1304 | rx_buffer_info->dma = next_buffer->dma; | |
1305 | next_buffer->skb = skb; | |
1306 | next_buffer->dma = 0; | |
1307 | } else { | |
1308 | skb->next = next_buffer->skb; | |
1309 | skb->next->prev = skb; | |
1310 | } | |
7ca3bc58 | 1311 | rx_ring->non_eop_descs++; |
9a799d71 AK |
1312 | goto next_desc; |
1313 | } | |
1314 | ||
1315 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { | |
1316 | dev_kfree_skb_irq(skb); | |
1317 | goto next_desc; | |
1318 | } | |
1319 | ||
8bae1b2b | 1320 | ixgbe_rx_checksum(adapter, rx_desc, skb); |
d2f4fbe2 AV |
1321 | |
1322 | /* probably a little skewed due to removing CRC */ | |
1323 | total_rx_bytes += skb->len; | |
1324 | total_rx_packets++; | |
1325 | ||
74ce8dd2 | 1326 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
332d4a7d YZ |
1327 | #ifdef IXGBE_FCOE |
1328 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
3d8fd385 YZ |
1329 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { |
1330 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); | |
1331 | if (!ddp_bytes) | |
332d4a7d | 1332 | goto next_desc; |
3d8fd385 | 1333 | } |
332d4a7d | 1334 | #endif /* IXGBE_FCOE */ |
fdaff1ce | 1335 | ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc); |
9a799d71 AK |
1336 | |
1337 | next_desc: | |
1338 | rx_desc->wb.upper.status_error = 0; | |
1339 | ||
1340 | /* return some buffers to hardware, one at a time is too slow */ | |
1341 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
1342 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
1343 | cleaned_count = 0; | |
1344 | } | |
1345 | ||
1346 | /* use prefetched values */ | |
1347 | rx_desc = next_rxd; | |
f8212f97 | 1348 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
1349 | |
1350 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
177db6ff MC |
1351 | } |
1352 | ||
9a799d71 AK |
1353 | rx_ring->next_to_clean = i; |
1354 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
1355 | ||
1356 | if (cleaned_count) | |
1357 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
1358 | ||
3d8fd385 YZ |
1359 | #ifdef IXGBE_FCOE |
1360 | /* include DDPed FCoE data */ | |
1361 | if (ddp_bytes > 0) { | |
1362 | unsigned int mss; | |
1363 | ||
1364 | mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) - | |
1365 | sizeof(struct fc_frame_header) - | |
1366 | sizeof(struct fcoe_crc_eof); | |
1367 | if (mss > 512) | |
1368 | mss &= ~511; | |
1369 | total_rx_bytes += ddp_bytes; | |
1370 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
1371 | } | |
1372 | #endif /* IXGBE_FCOE */ | |
1373 | ||
f494e8fa AV |
1374 | rx_ring->total_packets += total_rx_packets; |
1375 | rx_ring->total_bytes += total_rx_bytes; | |
2d86f139 AK |
1376 | netdev->stats.rx_bytes += total_rx_bytes; |
1377 | netdev->stats.rx_packets += total_rx_packets; | |
f494e8fa | 1378 | |
9a799d71 AK |
1379 | return cleaned; |
1380 | } | |
1381 | ||
021230d4 | 1382 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
1383 | /** |
1384 | * ixgbe_configure_msix - Configure MSI-X hardware | |
1385 | * @adapter: board private structure | |
1386 | * | |
1387 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
1388 | * interrupts. | |
1389 | **/ | |
1390 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
1391 | { | |
021230d4 AV |
1392 | struct ixgbe_q_vector *q_vector; |
1393 | int i, j, q_vectors, v_idx, r_idx; | |
1394 | u32 mask; | |
9a799d71 | 1395 | |
021230d4 | 1396 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 1397 | |
4df10466 JB |
1398 | /* |
1399 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
1400 | * corresponding register. |
1401 | */ | |
1402 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
7a921c93 | 1403 | q_vector = adapter->q_vector[v_idx]; |
984b3f57 | 1404 | /* XXX for_each_set_bit(...) */ |
021230d4 | 1405 | r_idx = find_first_bit(q_vector->rxr_idx, |
b4617240 | 1406 | adapter->num_rx_queues); |
021230d4 AV |
1407 | |
1408 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 1409 | j = adapter->rx_ring[r_idx]->reg_idx; |
e8e26350 | 1410 | ixgbe_set_ivar(adapter, 0, j, v_idx); |
021230d4 | 1411 | r_idx = find_next_bit(q_vector->rxr_idx, |
b4617240 PW |
1412 | adapter->num_rx_queues, |
1413 | r_idx + 1); | |
021230d4 AV |
1414 | } |
1415 | r_idx = find_first_bit(q_vector->txr_idx, | |
b4617240 | 1416 | adapter->num_tx_queues); |
021230d4 AV |
1417 | |
1418 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1419 | j = adapter->tx_ring[r_idx]->reg_idx; |
e8e26350 | 1420 | ixgbe_set_ivar(adapter, 1, j, v_idx); |
021230d4 | 1421 | r_idx = find_next_bit(q_vector->txr_idx, |
b4617240 PW |
1422 | adapter->num_tx_queues, |
1423 | r_idx + 1); | |
021230d4 AV |
1424 | } |
1425 | ||
021230d4 | 1426 | if (q_vector->txr_count && !q_vector->rxr_count) |
f7554a2b NS |
1427 | /* tx only */ |
1428 | q_vector->eitr = adapter->tx_eitr_param; | |
509ee935 | 1429 | else if (q_vector->rxr_count) |
f7554a2b NS |
1430 | /* rx or mixed */ |
1431 | q_vector->eitr = adapter->rx_eitr_param; | |
021230d4 | 1432 | |
fe49f04a | 1433 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
1434 | } |
1435 | ||
e8e26350 PW |
1436 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
1437 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, | |
1438 | v_idx); | |
1439 | else if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
1440 | ixgbe_set_ivar(adapter, -1, 1, v_idx); | |
021230d4 AV |
1441 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1442 | ||
41fb9248 | 1443 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 1444 | mask = IXGBE_EIMS_ENABLE_MASK; |
1cdd1ec8 GR |
1445 | if (adapter->num_vfs) |
1446 | mask &= ~(IXGBE_EIMS_OTHER | | |
1447 | IXGBE_EIMS_MAILBOX | | |
1448 | IXGBE_EIMS_LSC); | |
1449 | else | |
1450 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); | |
021230d4 | 1451 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
1452 | } |
1453 | ||
f494e8fa AV |
1454 | enum latency_range { |
1455 | lowest_latency = 0, | |
1456 | low_latency = 1, | |
1457 | bulk_latency = 2, | |
1458 | latency_invalid = 255 | |
1459 | }; | |
1460 | ||
1461 | /** | |
1462 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
1463 | * @adapter: pointer to adapter | |
1464 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
1465 | * @itr_setting: current throttle rate in ints/second | |
1466 | * @packets: the number of packets during this measurement interval | |
1467 | * @bytes: the number of bytes during this measurement interval | |
1468 | * | |
1469 | * Stores a new ITR value based on packets and byte | |
1470 | * counts during the last interrupt. The advantage of per interrupt | |
1471 | * computation is faster updates and more accurate ITR for the current | |
1472 | * traffic pattern. Constants in this function were computed | |
1473 | * based on theoretical maximum wire speed and thresholds were set based | |
1474 | * on testing data as well as attempting to minimize response time | |
1475 | * while increasing bulk throughput. | |
1476 | * this functionality is controlled by the InterruptThrottleRate module | |
1477 | * parameter (see ixgbe_param.c) | |
1478 | **/ | |
1479 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
b4617240 PW |
1480 | u32 eitr, u8 itr_setting, |
1481 | int packets, int bytes) | |
f494e8fa AV |
1482 | { |
1483 | unsigned int retval = itr_setting; | |
1484 | u32 timepassed_us; | |
1485 | u64 bytes_perint; | |
1486 | ||
1487 | if (packets == 0) | |
1488 | goto update_itr_done; | |
1489 | ||
1490 | ||
1491 | /* simple throttlerate management | |
1492 | * 0-20MB/s lowest (100000 ints/s) | |
1493 | * 20-100MB/s low (20000 ints/s) | |
1494 | * 100-1249MB/s bulk (8000 ints/s) | |
1495 | */ | |
1496 | /* what was last interrupt timeslice? */ | |
1497 | timepassed_us = 1000000/eitr; | |
1498 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
1499 | ||
1500 | switch (itr_setting) { | |
1501 | case lowest_latency: | |
1502 | if (bytes_perint > adapter->eitr_low) | |
1503 | retval = low_latency; | |
1504 | break; | |
1505 | case low_latency: | |
1506 | if (bytes_perint > adapter->eitr_high) | |
1507 | retval = bulk_latency; | |
1508 | else if (bytes_perint <= adapter->eitr_low) | |
1509 | retval = lowest_latency; | |
1510 | break; | |
1511 | case bulk_latency: | |
1512 | if (bytes_perint <= adapter->eitr_high) | |
1513 | retval = low_latency; | |
1514 | break; | |
1515 | } | |
1516 | ||
1517 | update_itr_done: | |
1518 | return retval; | |
1519 | } | |
1520 | ||
509ee935 JB |
1521 | /** |
1522 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1523 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1524 | * |
1525 | * This function is made to be called by ethtool and by the driver | |
1526 | * when it needs to update EITR registers at runtime. Hardware | |
1527 | * specific quirks/differences are taken care of here. | |
1528 | */ | |
fe49f04a | 1529 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1530 | { |
fe49f04a | 1531 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1532 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
1533 | int v_idx = q_vector->v_idx; |
1534 | u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr); | |
1535 | ||
509ee935 JB |
1536 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
1537 | /* must write high and low 16 bits to reset counter */ | |
1538 | itr_reg |= (itr_reg << 16); | |
1539 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
f8d1dcaf JB |
1540 | /* |
1541 | * 82599 can support a value of zero, so allow it for | |
1542 | * max interrupt rate, but there is an errata where it can | |
1543 | * not be zero with RSC | |
1544 | */ | |
1545 | if (itr_reg == 8 && | |
1546 | !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) | |
1547 | itr_reg = 0; | |
1548 | ||
509ee935 JB |
1549 | /* |
1550 | * set the WDIS bit to not clear the timer bits and cause an | |
1551 | * immediate assertion of the interrupt | |
1552 | */ | |
1553 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
1554 | } | |
1555 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1556 | } | |
1557 | ||
f494e8fa AV |
1558 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) |
1559 | { | |
1560 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f494e8fa AV |
1561 | u32 new_itr; |
1562 | u8 current_itr, ret_itr; | |
fe49f04a | 1563 | int i, r_idx; |
f494e8fa AV |
1564 | struct ixgbe_ring *rx_ring, *tx_ring; |
1565 | ||
1566 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1567 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1568 | tx_ring = adapter->tx_ring[r_idx]; |
f494e8fa | 1569 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, |
b4617240 PW |
1570 | q_vector->tx_itr, |
1571 | tx_ring->total_packets, | |
1572 | tx_ring->total_bytes); | |
f494e8fa AV |
1573 | /* if the result for this queue would decrease interrupt |
1574 | * rate for this vector then use that result */ | |
30efa5a3 | 1575 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
b4617240 | 1576 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 1577 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1578 | r_idx + 1); |
f494e8fa AV |
1579 | } |
1580 | ||
1581 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1582 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 1583 | rx_ring = adapter->rx_ring[r_idx]; |
f494e8fa | 1584 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, |
b4617240 PW |
1585 | q_vector->rx_itr, |
1586 | rx_ring->total_packets, | |
1587 | rx_ring->total_bytes); | |
f494e8fa AV |
1588 | /* if the result for this queue would decrease interrupt |
1589 | * rate for this vector then use that result */ | |
30efa5a3 | 1590 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
b4617240 | 1591 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 1592 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
b4617240 | 1593 | r_idx + 1); |
f494e8fa AV |
1594 | } |
1595 | ||
30efa5a3 | 1596 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1597 | |
1598 | switch (current_itr) { | |
1599 | /* counts and packets in update_itr are dependent on these numbers */ | |
1600 | case lowest_latency: | |
1601 | new_itr = 100000; | |
1602 | break; | |
1603 | case low_latency: | |
1604 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1605 | break; | |
1606 | case bulk_latency: | |
1607 | default: | |
1608 | new_itr = 8000; | |
1609 | break; | |
1610 | } | |
1611 | ||
1612 | if (new_itr != q_vector->eitr) { | |
fe49f04a AD |
1613 | /* do an exponential smoothing */ |
1614 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
509ee935 JB |
1615 | |
1616 | /* save the algorithm value here, not the smoothed one */ | |
1617 | q_vector->eitr = new_itr; | |
fe49f04a AD |
1618 | |
1619 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 1620 | } |
f494e8fa AV |
1621 | } |
1622 | ||
119fc60a MC |
1623 | /** |
1624 | * ixgbe_check_overtemp_task - worker thread to check over tempurature | |
1625 | * @work: pointer to work_struct containing our data | |
1626 | **/ | |
1627 | static void ixgbe_check_overtemp_task(struct work_struct *work) | |
1628 | { | |
1629 | struct ixgbe_adapter *adapter = container_of(work, | |
1630 | struct ixgbe_adapter, | |
1631 | check_overtemp_task); | |
1632 | struct ixgbe_hw *hw = &adapter->hw; | |
1633 | u32 eicr = adapter->interrupt_event; | |
1634 | ||
1635 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { | |
1636 | switch (hw->device_id) { | |
1637 | case IXGBE_DEV_ID_82599_T3_LOM: { | |
1638 | u32 autoneg; | |
1639 | bool link_up = false; | |
1640 | ||
1641 | if (hw->mac.ops.check_link) | |
1642 | hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
1643 | ||
1644 | if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) || | |
1645 | (eicr & IXGBE_EICR_LSC)) | |
1646 | /* Check if this is due to overtemp */ | |
1647 | if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP) | |
1648 | break; | |
1649 | } | |
1650 | return; | |
1651 | default: | |
1652 | if (!(eicr & IXGBE_EICR_GPI_SDP0)) | |
1653 | return; | |
1654 | break; | |
1655 | } | |
1656 | DPRINTK(DRV, ERR, "Network adapter has been stopped because it " | |
1657 | "has over heated. Restart the computer. If the problem " | |
1658 | "persists, power off the system and replace the " | |
1659 | "adapter\n"); | |
1660 | /* write to clear the interrupt */ | |
1661 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0); | |
1662 | } | |
1663 | } | |
1664 | ||
0befdb3e JB |
1665 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
1666 | { | |
1667 | struct ixgbe_hw *hw = &adapter->hw; | |
1668 | ||
1669 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
1670 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
1671 | DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n"); | |
1672 | /* write to clear the interrupt */ | |
1673 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1674 | } | |
1675 | } | |
cf8280ee | 1676 | |
e8e26350 PW |
1677 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
1678 | { | |
1679 | struct ixgbe_hw *hw = &adapter->hw; | |
1680 | ||
1681 | if (eicr & IXGBE_EICR_GPI_SDP1) { | |
1682 | /* Clear the interrupt */ | |
1683 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1684 | schedule_work(&adapter->multispeed_fiber_task); | |
1685 | } else if (eicr & IXGBE_EICR_GPI_SDP2) { | |
1686 | /* Clear the interrupt */ | |
1687 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
1688 | schedule_work(&adapter->sfp_config_module_task); | |
1689 | } else { | |
1690 | /* Interrupt isn't for us... */ | |
1691 | return; | |
1692 | } | |
1693 | } | |
1694 | ||
cf8280ee JB |
1695 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
1696 | { | |
1697 | struct ixgbe_hw *hw = &adapter->hw; | |
1698 | ||
1699 | adapter->lsc_int++; | |
1700 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
1701 | adapter->link_check_timeout = jiffies; | |
1702 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1703 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 1704 | IXGBE_WRITE_FLUSH(hw); |
cf8280ee JB |
1705 | schedule_work(&adapter->watchdog_task); |
1706 | } | |
1707 | } | |
1708 | ||
9a799d71 AK |
1709 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
1710 | { | |
1711 | struct net_device *netdev = data; | |
1712 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1713 | struct ixgbe_hw *hw = &adapter->hw; | |
54037505 DS |
1714 | u32 eicr; |
1715 | ||
1716 | /* | |
1717 | * Workaround for Silicon errata. Use clear-by-write instead | |
1718 | * of clear-by-read. Reading with EICS will return the | |
1719 | * interrupt causes without clearing, which later be done | |
1720 | * with the write to EICR. | |
1721 | */ | |
1722 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
1723 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
9a799d71 | 1724 | |
cf8280ee JB |
1725 | if (eicr & IXGBE_EICR_LSC) |
1726 | ixgbe_check_lsc(adapter); | |
d4f80882 | 1727 | |
1cdd1ec8 GR |
1728 | if (eicr & IXGBE_EICR_MAILBOX) |
1729 | ixgbe_msg_task(adapter); | |
1730 | ||
e8e26350 PW |
1731 | if (hw->mac.type == ixgbe_mac_82598EB) |
1732 | ixgbe_check_fan_failure(adapter, eicr); | |
0befdb3e | 1733 | |
c4cf55e5 | 1734 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 1735 | ixgbe_check_sfp_event(adapter, eicr); |
119fc60a MC |
1736 | adapter->interrupt_event = eicr; |
1737 | if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && | |
1738 | ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) | |
1739 | schedule_work(&adapter->check_overtemp_task); | |
c4cf55e5 PWJ |
1740 | |
1741 | /* Handle Flow Director Full threshold interrupt */ | |
1742 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
1743 | int i; | |
1744 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR); | |
1745 | /* Disable transmits before FDIR Re-initialization */ | |
1746 | netif_tx_stop_all_queues(netdev); | |
1747 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1748 | struct ixgbe_ring *tx_ring = | |
4a0b9ca0 | 1749 | adapter->tx_ring[i]; |
c4cf55e5 PWJ |
1750 | if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE, |
1751 | &tx_ring->reinit_state)) | |
1752 | schedule_work(&adapter->fdir_reinit_task); | |
1753 | } | |
1754 | } | |
1755 | } | |
d4f80882 AV |
1756 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1757 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
1758 | |
1759 | return IRQ_HANDLED; | |
1760 | } | |
1761 | ||
fe49f04a AD |
1762 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
1763 | u64 qmask) | |
1764 | { | |
1765 | u32 mask; | |
1766 | ||
1767 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1768 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1769 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); | |
1770 | } else { | |
1771 | mask = (qmask & 0xFFFFFFFF); | |
1772 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask); | |
1773 | mask = (qmask >> 32); | |
1774 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask); | |
1775 | } | |
1776 | /* skip the flush */ | |
1777 | } | |
1778 | ||
1779 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
1780 | u64 qmask) | |
1781 | { | |
1782 | u32 mask; | |
1783 | ||
1784 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1785 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1786 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask); | |
1787 | } else { | |
1788 | mask = (qmask & 0xFFFFFFFF); | |
1789 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask); | |
1790 | mask = (qmask >> 32); | |
1791 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask); | |
1792 | } | |
1793 | /* skip the flush */ | |
1794 | } | |
1795 | ||
9a799d71 AK |
1796 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) |
1797 | { | |
021230d4 AV |
1798 | struct ixgbe_q_vector *q_vector = data; |
1799 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1800 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
1801 | int i, r_idx; |
1802 | ||
1803 | if (!q_vector->txr_count) | |
1804 | return IRQ_HANDLED; | |
1805 | ||
1806 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1807 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1808 | tx_ring = adapter->tx_ring[r_idx]; |
3a581073 JB |
1809 | tx_ring->total_bytes = 0; |
1810 | tx_ring->total_packets = 0; | |
021230d4 | 1811 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1812 | r_idx + 1); |
021230d4 | 1813 | } |
9a799d71 | 1814 | |
9b471446 | 1815 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 AD |
1816 | napi_schedule(&q_vector->napi); |
1817 | ||
9a799d71 AK |
1818 | return IRQ_HANDLED; |
1819 | } | |
1820 | ||
021230d4 AV |
1821 | /** |
1822 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
1823 | * @irq: unused | |
1824 | * @data: pointer to our q_vector struct for this interrupt vector | |
1825 | **/ | |
9a799d71 AK |
1826 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
1827 | { | |
021230d4 AV |
1828 | struct ixgbe_q_vector *q_vector = data; |
1829 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1830 | struct ixgbe_ring *rx_ring; |
021230d4 | 1831 | int r_idx; |
30efa5a3 | 1832 | int i; |
021230d4 AV |
1833 | |
1834 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
30efa5a3 | 1835 | for (i = 0; i < q_vector->rxr_count; i++) { |
4a0b9ca0 | 1836 | rx_ring = adapter->rx_ring[r_idx]; |
30efa5a3 JB |
1837 | rx_ring->total_bytes = 0; |
1838 | rx_ring->total_packets = 0; | |
1839 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1840 | r_idx + 1); | |
1841 | } | |
1842 | ||
021230d4 AV |
1843 | if (!q_vector->rxr_count) |
1844 | return IRQ_HANDLED; | |
1845 | ||
021230d4 | 1846 | /* disable interrupts on this vector only */ |
9b471446 | 1847 | /* EIAM disabled interrupts (on this vector) for us */ |
288379f0 | 1848 | napi_schedule(&q_vector->napi); |
021230d4 AV |
1849 | |
1850 | return IRQ_HANDLED; | |
1851 | } | |
1852 | ||
1853 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
1854 | { | |
91281fd3 AD |
1855 | struct ixgbe_q_vector *q_vector = data; |
1856 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
1857 | struct ixgbe_ring *ring; | |
1858 | int r_idx; | |
1859 | int i; | |
1860 | ||
1861 | if (!q_vector->txr_count && !q_vector->rxr_count) | |
1862 | return IRQ_HANDLED; | |
1863 | ||
1864 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1865 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1866 | ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
1867 | ring->total_bytes = 0; |
1868 | ring->total_packets = 0; | |
1869 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
1870 | r_idx + 1); | |
1871 | } | |
1872 | ||
1873 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1874 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 1875 | ring = adapter->rx_ring[r_idx]; |
91281fd3 AD |
1876 | ring->total_bytes = 0; |
1877 | ring->total_packets = 0; | |
1878 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1879 | r_idx + 1); | |
1880 | } | |
1881 | ||
9b471446 | 1882 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 1883 | napi_schedule(&q_vector->napi); |
9a799d71 | 1884 | |
9a799d71 AK |
1885 | return IRQ_HANDLED; |
1886 | } | |
1887 | ||
021230d4 AV |
1888 | /** |
1889 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
1890 | * @napi: napi struct with our devices info in it | |
1891 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1892 | * | |
f0848276 JB |
1893 | * This function is optimized for cleaning one queue only on a single |
1894 | * q_vector!!! | |
021230d4 | 1895 | **/ |
9a799d71 AK |
1896 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
1897 | { | |
021230d4 | 1898 | struct ixgbe_q_vector *q_vector = |
b4617240 | 1899 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 1900 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 1901 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 1902 | int work_done = 0; |
021230d4 | 1903 | long r_idx; |
9a799d71 | 1904 | |
021230d4 | 1905 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
4a0b9ca0 | 1906 | rx_ring = adapter->rx_ring[r_idx]; |
5dd2d332 | 1907 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1908 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1909 | ixgbe_update_rx_dca(adapter, rx_ring); |
bd0362dd | 1910 | #endif |
9a799d71 | 1911 | |
78b6f4ce | 1912 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
9a799d71 | 1913 | |
021230d4 AV |
1914 | /* If all Rx work done, exit the polling mode */ |
1915 | if (work_done < budget) { | |
288379f0 | 1916 | napi_complete(napi); |
f7554a2b | 1917 | if (adapter->rx_itr_setting & 1) |
f494e8fa | 1918 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 1919 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
fe49f04a AD |
1920 | ixgbe_irq_enable_queues(adapter, |
1921 | ((u64)1 << q_vector->v_idx)); | |
9a799d71 AK |
1922 | } |
1923 | ||
1924 | return work_done; | |
1925 | } | |
1926 | ||
f0848276 | 1927 | /** |
91281fd3 | 1928 | * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine |
f0848276 JB |
1929 | * @napi: napi struct with our devices info in it |
1930 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1931 | * | |
1932 | * This function will clean more than one rx queue associated with a | |
1933 | * q_vector. | |
1934 | **/ | |
91281fd3 | 1935 | static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget) |
f0848276 JB |
1936 | { |
1937 | struct ixgbe_q_vector *q_vector = | |
1938 | container_of(napi, struct ixgbe_q_vector, napi); | |
1939 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
91281fd3 | 1940 | struct ixgbe_ring *ring = NULL; |
f0848276 JB |
1941 | int work_done = 0, i; |
1942 | long r_idx; | |
91281fd3 AD |
1943 | bool tx_clean_complete = true; |
1944 | ||
1945 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1946 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1947 | ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
1948 | #ifdef CONFIG_IXGBE_DCA |
1949 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1950 | ixgbe_update_tx_dca(adapter, ring); | |
1951 | #endif | |
1952 | tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring); | |
1953 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
1954 | r_idx + 1); | |
1955 | } | |
f0848276 JB |
1956 | |
1957 | /* attempt to distribute budget to each queue fairly, but don't allow | |
1958 | * the budget to go below 1 because we'll exit polling */ | |
1959 | budget /= (q_vector->rxr_count ?: 1); | |
1960 | budget = max(budget, 1); | |
1961 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1962 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 1963 | ring = adapter->rx_ring[r_idx]; |
5dd2d332 | 1964 | #ifdef CONFIG_IXGBE_DCA |
f0848276 | 1965 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
91281fd3 | 1966 | ixgbe_update_rx_dca(adapter, ring); |
f0848276 | 1967 | #endif |
91281fd3 | 1968 | ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget); |
f0848276 JB |
1969 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
1970 | r_idx + 1); | |
1971 | } | |
1972 | ||
1973 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
4a0b9ca0 | 1974 | ring = adapter->rx_ring[r_idx]; |
f0848276 | 1975 | /* If all Rx work done, exit the polling mode */ |
7f821875 | 1976 | if (work_done < budget) { |
288379f0 | 1977 | napi_complete(napi); |
f7554a2b | 1978 | if (adapter->rx_itr_setting & 1) |
f0848276 JB |
1979 | ixgbe_set_itr_msix(q_vector); |
1980 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
fe49f04a AD |
1981 | ixgbe_irq_enable_queues(adapter, |
1982 | ((u64)1 << q_vector->v_idx)); | |
f0848276 JB |
1983 | return 0; |
1984 | } | |
1985 | ||
1986 | return work_done; | |
1987 | } | |
91281fd3 AD |
1988 | |
1989 | /** | |
1990 | * ixgbe_clean_txonly - msix (aka one shot) tx clean routine | |
1991 | * @napi: napi struct with our devices info in it | |
1992 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1993 | * | |
1994 | * This function is optimized for cleaning one queue only on a single | |
1995 | * q_vector!!! | |
1996 | **/ | |
1997 | static int ixgbe_clean_txonly(struct napi_struct *napi, int budget) | |
1998 | { | |
1999 | struct ixgbe_q_vector *q_vector = | |
2000 | container_of(napi, struct ixgbe_q_vector, napi); | |
2001 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
2002 | struct ixgbe_ring *tx_ring = NULL; | |
2003 | int work_done = 0; | |
2004 | long r_idx; | |
2005 | ||
2006 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
4a0b9ca0 | 2007 | tx_ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
2008 | #ifdef CONFIG_IXGBE_DCA |
2009 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2010 | ixgbe_update_tx_dca(adapter, tx_ring); | |
2011 | #endif | |
2012 | ||
2013 | if (!ixgbe_clean_tx_irq(q_vector, tx_ring)) | |
2014 | work_done = budget; | |
2015 | ||
f7554a2b | 2016 | /* If all Tx work done, exit the polling mode */ |
91281fd3 AD |
2017 | if (work_done < budget) { |
2018 | napi_complete(napi); | |
f7554a2b | 2019 | if (adapter->tx_itr_setting & 1) |
91281fd3 AD |
2020 | ixgbe_set_itr_msix(q_vector); |
2021 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2022 | ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
2023 | } | |
2024 | ||
2025 | return work_done; | |
2026 | } | |
2027 | ||
021230d4 | 2028 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
b4617240 | 2029 | int r_idx) |
021230d4 | 2030 | { |
7a921c93 AD |
2031 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
2032 | ||
2033 | set_bit(r_idx, q_vector->rxr_idx); | |
2034 | q_vector->rxr_count++; | |
021230d4 AV |
2035 | } |
2036 | ||
2037 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
7a921c93 | 2038 | int t_idx) |
021230d4 | 2039 | { |
7a921c93 AD |
2040 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
2041 | ||
2042 | set_bit(t_idx, q_vector->txr_idx); | |
2043 | q_vector->txr_count++; | |
021230d4 AV |
2044 | } |
2045 | ||
9a799d71 | 2046 | /** |
021230d4 AV |
2047 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
2048 | * @adapter: board private structure to initialize | |
2049 | * @vectors: allotted vector count for descriptor rings | |
9a799d71 | 2050 | * |
021230d4 AV |
2051 | * This function maps descriptor rings to the queue-specific vectors |
2052 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
2053 | * one vector per ring/queue, but on a constrained vector budget, we | |
2054 | * group the rings as "efficiently" as possible. You would add new | |
2055 | * mapping configurations in here. | |
9a799d71 | 2056 | **/ |
021230d4 | 2057 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 2058 | int vectors) |
021230d4 AV |
2059 | { |
2060 | int v_start = 0; | |
2061 | int rxr_idx = 0, txr_idx = 0; | |
2062 | int rxr_remaining = adapter->num_rx_queues; | |
2063 | int txr_remaining = adapter->num_tx_queues; | |
2064 | int i, j; | |
2065 | int rqpv, tqpv; | |
2066 | int err = 0; | |
2067 | ||
2068 | /* No mapping required if MSI-X is disabled. */ | |
2069 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2070 | goto out; | |
9a799d71 | 2071 | |
021230d4 AV |
2072 | /* |
2073 | * The ideal configuration... | |
2074 | * We have enough vectors to map one per queue. | |
2075 | */ | |
2076 | if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) { | |
2077 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) | |
2078 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 2079 | |
021230d4 AV |
2080 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
2081 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 2082 | |
9a799d71 | 2083 | goto out; |
021230d4 | 2084 | } |
9a799d71 | 2085 | |
021230d4 AV |
2086 | /* |
2087 | * If we don't have enough vectors for a 1-to-1 | |
2088 | * mapping, we'll have to group them so there are | |
2089 | * multiple queues per vector. | |
2090 | */ | |
2091 | /* Re-adjusting *qpv takes care of the remainder. */ | |
2092 | for (i = v_start; i < vectors; i++) { | |
2093 | rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i); | |
2094 | for (j = 0; j < rqpv; j++) { | |
2095 | map_vector_to_rxq(adapter, i, rxr_idx); | |
2096 | rxr_idx++; | |
2097 | rxr_remaining--; | |
2098 | } | |
2099 | } | |
2100 | for (i = v_start; i < vectors; i++) { | |
2101 | tqpv = DIV_ROUND_UP(txr_remaining, vectors - i); | |
2102 | for (j = 0; j < tqpv; j++) { | |
2103 | map_vector_to_txq(adapter, i, txr_idx); | |
2104 | txr_idx++; | |
2105 | txr_remaining--; | |
9a799d71 | 2106 | } |
9a799d71 AK |
2107 | } |
2108 | ||
021230d4 AV |
2109 | out: |
2110 | return err; | |
2111 | } | |
2112 | ||
2113 | /** | |
2114 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
2115 | * @adapter: board private structure | |
2116 | * | |
2117 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
2118 | * interrupts from the kernel. | |
2119 | **/ | |
2120 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
2121 | { | |
2122 | struct net_device *netdev = adapter->netdev; | |
2123 | irqreturn_t (*handler)(int, void *); | |
2124 | int i, vector, q_vectors, err; | |
cb13fc20 | 2125 | int ri=0, ti=0; |
021230d4 AV |
2126 | |
2127 | /* Decrement for Other and TCP Timer vectors */ | |
2128 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2129 | ||
2130 | /* Map the Tx/Rx rings to the vectors we were allotted. */ | |
2131 | err = ixgbe_map_rings_to_vectors(adapter, q_vectors); | |
2132 | if (err) | |
2133 | goto out; | |
2134 | ||
2135 | #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \ | |
b4617240 PW |
2136 | (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \ |
2137 | &ixgbe_msix_clean_many) | |
021230d4 | 2138 | for (vector = 0; vector < q_vectors; vector++) { |
7a921c93 | 2139 | handler = SET_HANDLER(adapter->q_vector[vector]); |
cb13fc20 RO |
2140 | |
2141 | if(handler == &ixgbe_msix_clean_rx) { | |
2142 | sprintf(adapter->name[vector], "%s-%s-%d", | |
2143 | netdev->name, "rx", ri++); | |
2144 | } | |
2145 | else if(handler == &ixgbe_msix_clean_tx) { | |
2146 | sprintf(adapter->name[vector], "%s-%s-%d", | |
2147 | netdev->name, "tx", ti++); | |
2148 | } | |
2149 | else | |
2150 | sprintf(adapter->name[vector], "%s-%s-%d", | |
2151 | netdev->name, "TxRx", vector); | |
2152 | ||
021230d4 | 2153 | err = request_irq(adapter->msix_entries[vector].vector, |
b4617240 | 2154 | handler, 0, adapter->name[vector], |
7a921c93 | 2155 | adapter->q_vector[vector]); |
9a799d71 AK |
2156 | if (err) { |
2157 | DPRINTK(PROBE, ERR, | |
b4617240 PW |
2158 | "request_irq failed for MSIX interrupt " |
2159 | "Error: %d\n", err); | |
021230d4 | 2160 | goto free_queue_irqs; |
9a799d71 | 2161 | } |
9a799d71 AK |
2162 | } |
2163 | ||
021230d4 AV |
2164 | sprintf(adapter->name[vector], "%s:lsc", netdev->name); |
2165 | err = request_irq(adapter->msix_entries[vector].vector, | |
a0607fd3 | 2166 | ixgbe_msix_lsc, 0, adapter->name[vector], netdev); |
9a799d71 AK |
2167 | if (err) { |
2168 | DPRINTK(PROBE, ERR, | |
2169 | "request_irq for msix_lsc failed: %d\n", err); | |
021230d4 | 2170 | goto free_queue_irqs; |
9a799d71 AK |
2171 | } |
2172 | ||
9a799d71 AK |
2173 | return 0; |
2174 | ||
021230d4 AV |
2175 | free_queue_irqs: |
2176 | for (i = vector - 1; i >= 0; i--) | |
2177 | free_irq(adapter->msix_entries[--vector].vector, | |
7a921c93 | 2178 | adapter->q_vector[i]); |
021230d4 AV |
2179 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
2180 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
2181 | kfree(adapter->msix_entries); |
2182 | adapter->msix_entries = NULL; | |
021230d4 | 2183 | out: |
9a799d71 AK |
2184 | return err; |
2185 | } | |
2186 | ||
f494e8fa AV |
2187 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
2188 | { | |
7a921c93 | 2189 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
f494e8fa AV |
2190 | u8 current_itr; |
2191 | u32 new_itr = q_vector->eitr; | |
4a0b9ca0 PW |
2192 | struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; |
2193 | struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; | |
f494e8fa | 2194 | |
30efa5a3 | 2195 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
2196 | q_vector->tx_itr, |
2197 | tx_ring->total_packets, | |
2198 | tx_ring->total_bytes); | |
30efa5a3 | 2199 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
2200 | q_vector->rx_itr, |
2201 | rx_ring->total_packets, | |
2202 | rx_ring->total_bytes); | |
f494e8fa | 2203 | |
30efa5a3 | 2204 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
2205 | |
2206 | switch (current_itr) { | |
2207 | /* counts and packets in update_itr are dependent on these numbers */ | |
2208 | case lowest_latency: | |
2209 | new_itr = 100000; | |
2210 | break; | |
2211 | case low_latency: | |
2212 | new_itr = 20000; /* aka hwitr = ~200 */ | |
2213 | break; | |
2214 | case bulk_latency: | |
2215 | new_itr = 8000; | |
2216 | break; | |
2217 | default: | |
2218 | break; | |
2219 | } | |
2220 | ||
2221 | if (new_itr != q_vector->eitr) { | |
fe49f04a AD |
2222 | /* do an exponential smoothing */ |
2223 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
509ee935 JB |
2224 | |
2225 | /* save the algorithm value here, not the smoothed one */ | |
2226 | q_vector->eitr = new_itr; | |
fe49f04a AD |
2227 | |
2228 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 2229 | } |
f494e8fa AV |
2230 | } |
2231 | ||
79aefa45 AD |
2232 | /** |
2233 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
2234 | * @adapter: board private structure | |
2235 | **/ | |
2236 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) | |
2237 | { | |
2238 | u32 mask; | |
835462fc NS |
2239 | |
2240 | mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); | |
119fc60a MC |
2241 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
2242 | mask |= IXGBE_EIMS_GPI_SDP0; | |
6ab33d51 DM |
2243 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
2244 | mask |= IXGBE_EIMS_GPI_SDP1; | |
e8e26350 | 2245 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
2a41ff81 | 2246 | mask |= IXGBE_EIMS_ECC; |
e8e26350 PW |
2247 | mask |= IXGBE_EIMS_GPI_SDP1; |
2248 | mask |= IXGBE_EIMS_GPI_SDP2; | |
1cdd1ec8 GR |
2249 | if (adapter->num_vfs) |
2250 | mask |= IXGBE_EIMS_MAILBOX; | |
e8e26350 | 2251 | } |
c4cf55e5 PWJ |
2252 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
2253 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
2254 | mask |= IXGBE_EIMS_FLOW_DIR; | |
e8e26350 | 2255 | |
79aefa45 | 2256 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
835462fc | 2257 | ixgbe_irq_enable_queues(adapter, ~0); |
79aefa45 | 2258 | IXGBE_WRITE_FLUSH(&adapter->hw); |
1cdd1ec8 GR |
2259 | |
2260 | if (adapter->num_vfs > 32) { | |
2261 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
2262 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
2263 | } | |
79aefa45 | 2264 | } |
021230d4 | 2265 | |
9a799d71 | 2266 | /** |
021230d4 | 2267 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
2268 | * @irq: interrupt number |
2269 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
2270 | **/ |
2271 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
2272 | { | |
2273 | struct net_device *netdev = data; | |
2274 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2275 | struct ixgbe_hw *hw = &adapter->hw; | |
7a921c93 | 2276 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
2277 | u32 eicr; |
2278 | ||
54037505 DS |
2279 | /* |
2280 | * Workaround for silicon errata. Mask the interrupts | |
2281 | * before the read of EICR. | |
2282 | */ | |
2283 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
2284 | ||
021230d4 AV |
2285 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
2286 | * therefore no explict interrupt disable is necessary */ | |
2287 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e JB |
2288 | if (!eicr) { |
2289 | /* shared interrupt alert! | |
2290 | * make sure interrupts are enabled because the read will | |
2291 | * have disabled interrupts due to EIAM */ | |
2292 | ixgbe_irq_enable(adapter); | |
9a799d71 | 2293 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 2294 | } |
9a799d71 | 2295 | |
cf8280ee JB |
2296 | if (eicr & IXGBE_EICR_LSC) |
2297 | ixgbe_check_lsc(adapter); | |
021230d4 | 2298 | |
e8e26350 PW |
2299 | if (hw->mac.type == ixgbe_mac_82599EB) |
2300 | ixgbe_check_sfp_event(adapter, eicr); | |
2301 | ||
0befdb3e | 2302 | ixgbe_check_fan_failure(adapter, eicr); |
119fc60a MC |
2303 | if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
2304 | ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) | |
2305 | schedule_work(&adapter->check_overtemp_task); | |
0befdb3e | 2306 | |
7a921c93 | 2307 | if (napi_schedule_prep(&(q_vector->napi))) { |
4a0b9ca0 PW |
2308 | adapter->tx_ring[0]->total_packets = 0; |
2309 | adapter->tx_ring[0]->total_bytes = 0; | |
2310 | adapter->rx_ring[0]->total_packets = 0; | |
2311 | adapter->rx_ring[0]->total_bytes = 0; | |
021230d4 | 2312 | /* would disable interrupts here but EIAM disabled it */ |
7a921c93 | 2313 | __napi_schedule(&(q_vector->napi)); |
9a799d71 AK |
2314 | } |
2315 | ||
2316 | return IRQ_HANDLED; | |
2317 | } | |
2318 | ||
021230d4 AV |
2319 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
2320 | { | |
2321 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2322 | ||
2323 | for (i = 0; i < q_vectors; i++) { | |
7a921c93 | 2324 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; |
021230d4 AV |
2325 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); |
2326 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
2327 | q_vector->rxr_count = 0; | |
2328 | q_vector->txr_count = 0; | |
2329 | } | |
2330 | } | |
2331 | ||
9a799d71 AK |
2332 | /** |
2333 | * ixgbe_request_irq - initialize interrupts | |
2334 | * @adapter: board private structure | |
2335 | * | |
2336 | * Attempts to configure interrupts using the best available | |
2337 | * capabilities of the hardware and kernel. | |
2338 | **/ | |
021230d4 | 2339 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2340 | { |
2341 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 2342 | int err; |
9a799d71 | 2343 | |
021230d4 AV |
2344 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2345 | err = ixgbe_request_msix_irqs(adapter); | |
2346 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
a0607fd3 | 2347 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
b4617240 | 2348 | netdev->name, netdev); |
021230d4 | 2349 | } else { |
a0607fd3 | 2350 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
b4617240 | 2351 | netdev->name, netdev); |
9a799d71 AK |
2352 | } |
2353 | ||
9a799d71 AK |
2354 | if (err) |
2355 | DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err); | |
2356 | ||
9a799d71 AK |
2357 | return err; |
2358 | } | |
2359 | ||
2360 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
2361 | { | |
2362 | struct net_device *netdev = adapter->netdev; | |
2363 | ||
2364 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 2365 | int i, q_vectors; |
9a799d71 | 2366 | |
021230d4 AV |
2367 | q_vectors = adapter->num_msix_vectors; |
2368 | ||
2369 | i = q_vectors - 1; | |
9a799d71 | 2370 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 2371 | |
021230d4 AV |
2372 | i--; |
2373 | for (; i >= 0; i--) { | |
2374 | free_irq(adapter->msix_entries[i].vector, | |
7a921c93 | 2375 | adapter->q_vector[i]); |
021230d4 AV |
2376 | } |
2377 | ||
2378 | ixgbe_reset_q_vectors(adapter); | |
2379 | } else { | |
2380 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
2381 | } |
2382 | } | |
2383 | ||
22d5a71b JB |
2384 | /** |
2385 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
2386 | * @adapter: board private structure | |
2387 | **/ | |
2388 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
2389 | { | |
835462fc NS |
2390 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
2391 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); | |
2392 | } else { | |
2393 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); | |
2394 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 2395 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
1cdd1ec8 GR |
2396 | if (adapter->num_vfs > 32) |
2397 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
22d5a71b JB |
2398 | } |
2399 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
2400 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
2401 | int i; | |
2402 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
2403 | synchronize_irq(adapter->msix_entries[i].vector); | |
2404 | } else { | |
2405 | synchronize_irq(adapter->pdev->irq); | |
2406 | } | |
2407 | } | |
2408 | ||
9a799d71 AK |
2409 | /** |
2410 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
2411 | * | |
2412 | **/ | |
2413 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
2414 | { | |
9a799d71 AK |
2415 | struct ixgbe_hw *hw = &adapter->hw; |
2416 | ||
021230d4 | 2417 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
f7554a2b | 2418 | EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param)); |
9a799d71 | 2419 | |
e8e26350 PW |
2420 | ixgbe_set_ivar(adapter, 0, 0, 0); |
2421 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 AV |
2422 | |
2423 | map_vector_to_rxq(adapter, 0, 0); | |
2424 | map_vector_to_txq(adapter, 0, 0); | |
2425 | ||
2426 | DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n"); | |
9a799d71 AK |
2427 | } |
2428 | ||
2429 | /** | |
3a581073 | 2430 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
2431 | * @adapter: board private structure |
2432 | * | |
2433 | * Configure the Tx unit of the MAC after a reset. | |
2434 | **/ | |
2435 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
2436 | { | |
12207e49 | 2437 | u64 tdba; |
9a799d71 | 2438 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 2439 | u32 i, j, tdlen, txctrl; |
9a799d71 AK |
2440 | |
2441 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
2442 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 2443 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
e01c31a5 JB |
2444 | j = ring->reg_idx; |
2445 | tdba = ring->dma; | |
2446 | tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc); | |
021230d4 | 2447 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), |
284901a9 | 2448 | (tdba & DMA_BIT_MASK(32))); |
021230d4 AV |
2449 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); |
2450 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen); | |
2451 | IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); | |
2452 | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | |
4a0b9ca0 PW |
2453 | adapter->tx_ring[i]->head = IXGBE_TDH(j); |
2454 | adapter->tx_ring[i]->tail = IXGBE_TDT(j); | |
84f62d4b PWJ |
2455 | /* |
2456 | * Disable Tx Head Writeback RO bit, since this hoses | |
021230d4 AV |
2457 | * bookkeeping if things aren't delivered in order. |
2458 | */ | |
84f62d4b PWJ |
2459 | switch (hw->mac.type) { |
2460 | case ixgbe_mac_82598EB: | |
2461 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); | |
2462 | break; | |
2463 | case ixgbe_mac_82599EB: | |
2464 | default: | |
2465 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j)); | |
2466 | break; | |
2467 | } | |
021230d4 | 2468 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; |
84f62d4b PWJ |
2469 | switch (hw->mac.type) { |
2470 | case ixgbe_mac_82598EB: | |
2471 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); | |
2472 | break; | |
2473 | case ixgbe_mac_82599EB: | |
2474 | default: | |
2475 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl); | |
2476 | break; | |
2477 | } | |
9a799d71 | 2478 | } |
ee5f784a | 2479 | |
e8e26350 | 2480 | if (hw->mac.type == ixgbe_mac_82599EB) { |
ee5f784a | 2481 | u32 rttdcs; |
1cdd1ec8 | 2482 | u32 mask; |
ee5f784a DS |
2483 | |
2484 | /* disable the arbiter while setting MTQC */ | |
2485 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
2486 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
2487 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2488 | ||
1cdd1ec8 GR |
2489 | /* set transmit pool layout */ |
2490 | mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED); | |
2491 | switch (adapter->flags & mask) { | |
2492 | ||
2493 | case (IXGBE_FLAG_SRIOV_ENABLED): | |
2494 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2495 | (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF)); | |
2496 | break; | |
2497 | ||
2498 | case (IXGBE_FLAG_DCB_ENABLED): | |
2499 | /* We enable 8 traffic classes, DCB only */ | |
2500 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2501 | (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ)); | |
2502 | break; | |
2503 | ||
2504 | default: | |
ee5f784a | 2505 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB); |
1cdd1ec8 GR |
2506 | break; |
2507 | } | |
ee5f784a DS |
2508 | |
2509 | /* re-eable the arbiter */ | |
2510 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2511 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
e8e26350 | 2512 | } |
9a799d71 AK |
2513 | } |
2514 | ||
e8e26350 | 2515 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2516 | |
a6616b42 YZ |
2517 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
2518 | struct ixgbe_ring *rx_ring) | |
cc41ac7c | 2519 | { |
cc41ac7c | 2520 | u32 srrctl; |
a6616b42 | 2521 | int index; |
0cefafad | 2522 | struct ixgbe_ring_feature *feature = adapter->ring_feature; |
3be1adfb | 2523 | |
a6616b42 YZ |
2524 | index = rx_ring->reg_idx; |
2525 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2526 | unsigned long mask; | |
0cefafad | 2527 | mask = (unsigned long) feature[RING_F_RSS].mask; |
3be1adfb | 2528 | index = index & mask; |
cc41ac7c | 2529 | } |
cc41ac7c JB |
2530 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index)); |
2531 | ||
2532 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2533 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
2534 | ||
afafd5b0 AD |
2535 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
2536 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2537 | ||
6e455b89 | 2538 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { |
afafd5b0 AD |
2539 | #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER |
2540 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2541 | #else | |
2542 | srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2543 | #endif | |
cc41ac7c | 2544 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
cc41ac7c | 2545 | } else { |
afafd5b0 AD |
2546 | srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >> |
2547 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
cc41ac7c | 2548 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
cc41ac7c | 2549 | } |
e8e26350 | 2550 | |
cc41ac7c JB |
2551 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl); |
2552 | } | |
9a799d71 | 2553 | |
0cefafad JB |
2554 | static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
2555 | { | |
2556 | u32 mrqc = 0; | |
2557 | int mask; | |
2558 | ||
2559 | if (!(adapter->hw.mac.type == ixgbe_mac_82599EB)) | |
2560 | return mrqc; | |
2561 | ||
2562 | mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
2563 | #ifdef CONFIG_IXGBE_DCB | |
2564 | | IXGBE_FLAG_DCB_ENABLED | |
2565 | #endif | |
1cdd1ec8 | 2566 | | IXGBE_FLAG_SRIOV_ENABLED |
0cefafad JB |
2567 | ); |
2568 | ||
2569 | switch (mask) { | |
2570 | case (IXGBE_FLAG_RSS_ENABLED): | |
2571 | mrqc = IXGBE_MRQC_RSSEN; | |
2572 | break; | |
1cdd1ec8 GR |
2573 | case (IXGBE_FLAG_SRIOV_ENABLED): |
2574 | mrqc = IXGBE_MRQC_VMDQEN; | |
2575 | break; | |
0cefafad JB |
2576 | #ifdef CONFIG_IXGBE_DCB |
2577 | case (IXGBE_FLAG_DCB_ENABLED): | |
2578 | mrqc = IXGBE_MRQC_RT8TCEN; | |
2579 | break; | |
2580 | #endif /* CONFIG_IXGBE_DCB */ | |
2581 | default: | |
2582 | break; | |
2583 | } | |
2584 | ||
2585 | return mrqc; | |
2586 | } | |
2587 | ||
bb5a9ad2 NS |
2588 | /** |
2589 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
2590 | * @adapter: address of board private structure | |
2591 | * @index: index of ring to set | |
bb5a9ad2 | 2592 | **/ |
edd2ea55 | 2593 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index) |
bb5a9ad2 NS |
2594 | { |
2595 | struct ixgbe_ring *rx_ring; | |
2596 | struct ixgbe_hw *hw = &adapter->hw; | |
2597 | int j; | |
2598 | u32 rscctrl; | |
edd2ea55 | 2599 | int rx_buf_len; |
bb5a9ad2 | 2600 | |
4a0b9ca0 | 2601 | rx_ring = adapter->rx_ring[index]; |
bb5a9ad2 | 2602 | j = rx_ring->reg_idx; |
edd2ea55 | 2603 | rx_buf_len = rx_ring->rx_buf_len; |
bb5a9ad2 NS |
2604 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j)); |
2605 | rscctrl |= IXGBE_RSCCTL_RSCEN; | |
2606 | /* | |
2607 | * we must limit the number of descriptors so that the | |
2608 | * total size of max desc * buf_len is not greater | |
2609 | * than 65535 | |
2610 | */ | |
2611 | if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { | |
2612 | #if (MAX_SKB_FRAGS > 16) | |
2613 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2614 | #elif (MAX_SKB_FRAGS > 8) | |
2615 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2616 | #elif (MAX_SKB_FRAGS > 4) | |
2617 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2618 | #else | |
2619 | rscctrl |= IXGBE_RSCCTL_MAXDESC_1; | |
2620 | #endif | |
2621 | } else { | |
2622 | if (rx_buf_len < IXGBE_RXBUFFER_4096) | |
2623 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2624 | else if (rx_buf_len < IXGBE_RXBUFFER_8192) | |
2625 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2626 | else | |
2627 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2628 | } | |
2629 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl); | |
2630 | } | |
2631 | ||
9a799d71 | 2632 | /** |
3a581073 | 2633 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset |
9a799d71 AK |
2634 | * @adapter: board private structure |
2635 | * | |
2636 | * Configure the Rx unit of the MAC after a reset. | |
2637 | **/ | |
2638 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
2639 | { | |
2640 | u64 rdba; | |
2641 | struct ixgbe_hw *hw = &adapter->hw; | |
a6616b42 | 2642 | struct ixgbe_ring *rx_ring; |
9a799d71 AK |
2643 | struct net_device *netdev = adapter->netdev; |
2644 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
021230d4 | 2645 | int i, j; |
9a799d71 | 2646 | u32 rdlen, rxctrl, rxcsum; |
7c6e0a43 JB |
2647 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, |
2648 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, | |
2649 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
9a799d71 | 2650 | u32 fctrl, hlreg0; |
509ee935 | 2651 | u32 reta = 0, mrqc = 0; |
cc41ac7c | 2652 | u32 rdrxctl; |
7c6e0a43 | 2653 | int rx_buf_len; |
9a799d71 AK |
2654 | |
2655 | /* Decide whether to use packet split mode or not */ | |
1cdd1ec8 GR |
2656 | /* Do not use packet split if we're in SR-IOV Mode */ |
2657 | if (!adapter->num_vfs) | |
2658 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; | |
9a799d71 AK |
2659 | |
2660 | /* Set the RX buffer length according to the mode */ | |
2661 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 2662 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
e8e26350 PW |
2663 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2664 | /* PSRTYPE must be initialized in 82599 */ | |
2665 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
2666 | IXGBE_PSRTYPE_UDPHDR | | |
2667 | IXGBE_PSRTYPE_IPV4HDR | | |
dfa12f05 YZ |
2668 | IXGBE_PSRTYPE_IPV6HDR | |
2669 | IXGBE_PSRTYPE_L2HDR; | |
1cdd1ec8 GR |
2670 | IXGBE_WRITE_REG(hw, |
2671 | IXGBE_PSRTYPE(adapter->num_vfs), | |
2672 | psrtype); | |
e8e26350 | 2673 | } |
9a799d71 | 2674 | } else { |
0c19d6af | 2675 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && |
f8212f97 | 2676 | (netdev->mtu <= ETH_DATA_LEN)) |
7c6e0a43 | 2677 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 2678 | else |
7c6e0a43 | 2679 | rx_buf_len = ALIGN(max_frame, 1024); |
9a799d71 AK |
2680 | } |
2681 | ||
2682 | fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); | |
2683 | fctrl |= IXGBE_FCTRL_BAM; | |
021230d4 | 2684 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ |
e8e26350 | 2685 | fctrl |= IXGBE_FCTRL_PMCF; |
9a799d71 AK |
2686 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl); |
2687 | ||
2688 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
2689 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
2690 | hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; | |
2691 | else | |
2692 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
63f39bd1 | 2693 | #ifdef IXGBE_FCOE |
f34c5c82 | 2694 | if (netdev->features & NETIF_F_FCOE_MTU) |
63f39bd1 YZ |
2695 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; |
2696 | #endif | |
9a799d71 AK |
2697 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); |
2698 | ||
4a0b9ca0 | 2699 | rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc); |
9a799d71 AK |
2700 | /* disable receives while setting up the descriptors */ |
2701 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
2702 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
2703 | ||
0cefafad JB |
2704 | /* |
2705 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
2706 | * the Base and Length of the Rx Descriptor Ring | |
2707 | */ | |
9a799d71 | 2708 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 2709 | rx_ring = adapter->rx_ring[i]; |
a6616b42 YZ |
2710 | rdba = rx_ring->dma; |
2711 | j = rx_ring->reg_idx; | |
284901a9 | 2712 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32))); |
7c6e0a43 JB |
2713 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); |
2714 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen); | |
2715 | IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); | |
2716 | IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); | |
a6616b42 YZ |
2717 | rx_ring->head = IXGBE_RDH(j); |
2718 | rx_ring->tail = IXGBE_RDT(j); | |
2719 | rx_ring->rx_buf_len = rx_buf_len; | |
cc41ac7c | 2720 | |
6e455b89 YZ |
2721 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) |
2722 | rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED; | |
1b3ff02e PWJ |
2723 | else |
2724 | rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED; | |
cc41ac7c | 2725 | |
63f39bd1 | 2726 | #ifdef IXGBE_FCOE |
f34c5c82 | 2727 | if (netdev->features & NETIF_F_FCOE_MTU) { |
63f39bd1 YZ |
2728 | struct ixgbe_ring_feature *f; |
2729 | f = &adapter->ring_feature[RING_F_FCOE]; | |
6e455b89 YZ |
2730 | if ((i >= f->mask) && (i < f->mask + f->indices)) { |
2731 | rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED; | |
2732 | if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) | |
2733 | rx_ring->rx_buf_len = | |
2734 | IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
2735 | } | |
63f39bd1 YZ |
2736 | } |
2737 | ||
2738 | #endif /* IXGBE_FCOE */ | |
a6616b42 | 2739 | ixgbe_configure_srrctl(adapter, rx_ring); |
9a799d71 AK |
2740 | } |
2741 | ||
e8e26350 PW |
2742 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2743 | /* | |
2744 | * For VMDq support of different descriptor types or | |
2745 | * buffer sizes through the use of multiple SRRCTL | |
2746 | * registers, RDRXCTL.MVMEN must be set to 1 | |
2747 | * | |
2748 | * also, the manual doesn't mention it clearly but DCA hints | |
2749 | * will only use queue 0's tags unless this bit is set. Side | |
2750 | * effects of setting this bit are only that SRRCTL must be | |
2751 | * fully programmed [0..15] | |
2752 | */ | |
2a41ff81 JB |
2753 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); |
2754 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
2755 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
2f90b865 | 2756 | } |
177db6ff | 2757 | |
1cdd1ec8 GR |
2758 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
2759 | u32 vt_reg_bits; | |
2760 | u32 reg_offset, vf_shift; | |
2761 | u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
2762 | vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | |
2763 | | IXGBE_VT_CTL_REPLEN; | |
2764 | vt_reg_bits |= (adapter->num_vfs << | |
2765 | IXGBE_VT_CTL_POOL_SHIFT); | |
2766 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits); | |
2767 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0); | |
2768 | ||
2769 | vf_shift = adapter->num_vfs % 32; | |
2770 | reg_offset = adapter->num_vfs / 32; | |
2771 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0); | |
2772 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0); | |
2773 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0); | |
2774 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0); | |
2775 | /* Enable only the PF's pool for Tx/Rx */ | |
2776 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift)); | |
2777 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift)); | |
2778 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
f0412776 | 2779 | ixgbe_set_vmolr(hw, adapter->num_vfs, true); |
1cdd1ec8 GR |
2780 | } |
2781 | ||
e8e26350 | 2782 | /* Program MRQC for the distribution of queues */ |
0cefafad | 2783 | mrqc = ixgbe_setup_mrqc(adapter); |
e8e26350 | 2784 | |
021230d4 | 2785 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
9a799d71 | 2786 | /* Fill out redirection table */ |
021230d4 AV |
2787 | for (i = 0, j = 0; i < 128; i++, j++) { |
2788 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
2789 | j = 0; | |
2790 | /* reta = 4-byte sliding window of | |
2791 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2792 | reta = (reta << 8) | (j * 0x11); | |
2793 | if ((i & 3) == 3) | |
2794 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
9a799d71 AK |
2795 | } |
2796 | ||
2797 | /* Fill out hash function seeds */ | |
2798 | for (i = 0; i < 10; i++) | |
7c6e0a43 | 2799 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); |
9a799d71 | 2800 | |
2a41ff81 JB |
2801 | if (hw->mac.type == ixgbe_mac_82598EB) |
2802 | mrqc |= IXGBE_MRQC_RSSEN; | |
9a799d71 | 2803 | /* Perform hash on these packet types */ |
2a41ff81 JB |
2804 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
2805 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
2806 | | IXGBE_MRQC_RSS_FIELD_IPV4_UDP | |
2807 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
2808 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP | |
2809 | | IXGBE_MRQC_RSS_FIELD_IPV6_UDP; | |
021230d4 | 2810 | } |
2a41ff81 | 2811 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
9a799d71 | 2812 | |
1cdd1ec8 GR |
2813 | if (adapter->num_vfs) { |
2814 | u32 reg; | |
2815 | ||
2816 | /* Map PF MAC address in RAR Entry 0 to first pool | |
2817 | * following VFs */ | |
2818 | hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs); | |
2819 | ||
2820 | /* Set up VF register offsets for selected VT Mode, i.e. | |
2821 | * 64 VFs for SR-IOV */ | |
2822 | reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
2823 | reg |= IXGBE_GCR_EXT_SRIOV; | |
2824 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg); | |
2825 | } | |
2826 | ||
021230d4 AV |
2827 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); |
2828 | ||
2829 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED || | |
2830 | adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) { | |
2831 | /* Disable indicating checksum in descriptor, enables | |
2832 | * RSS hash */ | |
9a799d71 | 2833 | rxcsum |= IXGBE_RXCSUM_PCSD; |
9a799d71 | 2834 | } |
021230d4 AV |
2835 | if (!(rxcsum & IXGBE_RXCSUM_PCSD)) { |
2836 | /* Enable IPv4 payload checksum for UDP fragments | |
2837 | * if PCSD is not set */ | |
2838 | rxcsum |= IXGBE_RXCSUM_IPPCSE; | |
2839 | } | |
2840 | ||
2841 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
e8e26350 PW |
2842 | |
2843 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2844 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
2845 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
f8212f97 | 2846 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; |
e8e26350 PW |
2847 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); |
2848 | } | |
f8212f97 | 2849 | |
0c19d6af | 2850 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 2851 | /* Enable 82599 HW-RSC */ |
bb5a9ad2 | 2852 | for (i = 0; i < adapter->num_rx_queues; i++) |
edd2ea55 | 2853 | ixgbe_configure_rscctl(adapter, i); |
bb5a9ad2 | 2854 | |
f8212f97 AD |
2855 | /* Disable RSC for ACK packets */ |
2856 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
2857 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
2858 | } | |
9a799d71 AK |
2859 | } |
2860 | ||
068c89b0 DS |
2861 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
2862 | { | |
2863 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2864 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 2865 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
2866 | |
2867 | /* add VID to filter table */ | |
1ada1b1b | 2868 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true); |
068c89b0 DS |
2869 | } |
2870 | ||
2871 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
2872 | { | |
2873 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2874 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 2875 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
2876 | |
2877 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2878 | ixgbe_irq_disable(adapter); | |
2879 | ||
2880 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
2881 | ||
2882 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2883 | ixgbe_irq_enable(adapter); | |
2884 | ||
2885 | /* remove VID from filter table */ | |
1ada1b1b | 2886 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false); |
068c89b0 DS |
2887 | } |
2888 | ||
5f6c0181 JB |
2889 | /** |
2890 | * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering | |
2891 | * @adapter: driver data | |
2892 | */ | |
2893 | static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter) | |
2894 | { | |
2895 | struct ixgbe_hw *hw = &adapter->hw; | |
2896 | u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
2897 | int i, j; | |
2898 | ||
2899 | switch (hw->mac.type) { | |
2900 | case ixgbe_mac_82598EB: | |
38e0bd98 YZ |
2901 | vlnctrl &= ~IXGBE_VLNCTRL_VFE; |
2902 | #ifdef CONFIG_IXGBE_DCB | |
2903 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) | |
2904 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
2905 | #endif | |
5f6c0181 JB |
2906 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; |
2907 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2908 | break; | |
2909 | case ixgbe_mac_82599EB: | |
2910 | vlnctrl &= ~IXGBE_VLNCTRL_VFE; | |
2911 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2912 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
38e0bd98 YZ |
2913 | #ifdef CONFIG_IXGBE_DCB |
2914 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
2915 | break; | |
2916 | #endif | |
5f6c0181 JB |
2917 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2918 | j = adapter->rx_ring[i]->reg_idx; | |
2919 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2920 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
2921 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
2922 | } | |
2923 | break; | |
2924 | default: | |
2925 | break; | |
2926 | } | |
2927 | } | |
2928 | ||
2929 | /** | |
2930 | * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering | |
2931 | * @adapter: driver data | |
2932 | */ | |
2933 | static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter) | |
2934 | { | |
2935 | struct ixgbe_hw *hw = &adapter->hw; | |
2936 | u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
2937 | int i, j; | |
2938 | ||
2939 | switch (hw->mac.type) { | |
2940 | case ixgbe_mac_82598EB: | |
2941 | vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2942 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2943 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2944 | break; | |
2945 | case ixgbe_mac_82599EB: | |
2946 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
2947 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2948 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2949 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2950 | j = adapter->rx_ring[i]->reg_idx; | |
2951 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2952 | vlnctrl |= IXGBE_RXDCTL_VME; | |
2953 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
2954 | } | |
2955 | break; | |
2956 | default: | |
2957 | break; | |
2958 | } | |
2959 | } | |
2960 | ||
9a799d71 | 2961 | static void ixgbe_vlan_rx_register(struct net_device *netdev, |
b4617240 | 2962 | struct vlan_group *grp) |
9a799d71 AK |
2963 | { |
2964 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 | 2965 | |
d4f80882 AV |
2966 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2967 | ixgbe_irq_disable(adapter); | |
9a799d71 AK |
2968 | adapter->vlgrp = grp; |
2969 | ||
2f90b865 AD |
2970 | /* |
2971 | * For a DCB driver, always enable VLAN tag stripping so we can | |
2972 | * still receive traffic from a DCB-enabled host even if we're | |
2973 | * not in DCB mode. | |
2974 | */ | |
5f6c0181 | 2975 | ixgbe_vlan_filter_enable(adapter); |
dc63d377 | 2976 | |
e8e26350 | 2977 | ixgbe_vlan_rx_add_vid(netdev, 0); |
9a799d71 | 2978 | |
d4f80882 AV |
2979 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2980 | ixgbe_irq_enable(adapter); | |
9a799d71 AK |
2981 | } |
2982 | ||
9a799d71 AK |
2983 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
2984 | { | |
2985 | ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
2986 | ||
2987 | if (adapter->vlgrp) { | |
2988 | u16 vid; | |
2989 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
2990 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
2991 | continue; | |
2992 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
2993 | } | |
2994 | } | |
2995 | } | |
2996 | ||
2997 | /** | |
2c5645cf | 2998 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
2999 | * @netdev: network interface device structure |
3000 | * | |
2c5645cf CL |
3001 | * The set_rx_method entry point is called whenever the unicast/multicast |
3002 | * address list or the network interface flags are updated. This routine is | |
3003 | * responsible for configuring the hardware for proper unicast, multicast and | |
3004 | * promiscuous mode. | |
9a799d71 | 3005 | **/ |
7f870475 | 3006 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
3007 | { |
3008 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3009 | struct ixgbe_hw *hw = &adapter->hw; | |
5f6c0181 | 3010 | u32 fctrl; |
9a799d71 AK |
3011 | |
3012 | /* Check for Promiscuous and All Multicast modes */ | |
3013 | ||
3014 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3015 | ||
3016 | if (netdev->flags & IFF_PROMISC) { | |
e433ea1f | 3017 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 3018 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
5f6c0181 JB |
3019 | /* don't hardware filter vlans in promisc mode */ |
3020 | ixgbe_vlan_filter_disable(adapter); | |
9a799d71 | 3021 | } else { |
746b9f02 PM |
3022 | if (netdev->flags & IFF_ALLMULTI) { |
3023 | fctrl |= IXGBE_FCTRL_MPE; | |
3024 | fctrl &= ~IXGBE_FCTRL_UPE; | |
e433ea1f | 3025 | } else if (!hw->addr_ctrl.uc_set_promisc) { |
746b9f02 PM |
3026 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
3027 | } | |
5f6c0181 | 3028 | ixgbe_vlan_filter_enable(adapter); |
e433ea1f | 3029 | hw->addr_ctrl.user_set_promisc = false; |
9a799d71 AK |
3030 | } |
3031 | ||
3032 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3033 | ||
2c5645cf | 3034 | /* reprogram secondary unicast list */ |
32e7bfc4 | 3035 | hw->mac.ops.update_uc_addr_list(hw, netdev); |
9a799d71 | 3036 | |
2c5645cf | 3037 | /* reprogram multicast list */ |
2853eb89 JP |
3038 | hw->mac.ops.update_mc_addr_list(hw, netdev); |
3039 | ||
1cdd1ec8 GR |
3040 | if (adapter->num_vfs) |
3041 | ixgbe_restore_vf_multicasts(adapter); | |
9a799d71 AK |
3042 | } |
3043 | ||
021230d4 AV |
3044 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
3045 | { | |
3046 | int q_idx; | |
3047 | struct ixgbe_q_vector *q_vector; | |
3048 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3049 | ||
3050 | /* legacy and MSI only use one vector */ | |
3051 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3052 | q_vectors = 1; | |
3053 | ||
3054 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 3055 | struct napi_struct *napi; |
7a921c93 | 3056 | q_vector = adapter->q_vector[q_idx]; |
f0848276 | 3057 | napi = &q_vector->napi; |
91281fd3 AD |
3058 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
3059 | if (!q_vector->rxr_count || !q_vector->txr_count) { | |
3060 | if (q_vector->txr_count == 1) | |
3061 | napi->poll = &ixgbe_clean_txonly; | |
3062 | else if (q_vector->rxr_count == 1) | |
3063 | napi->poll = &ixgbe_clean_rxonly; | |
3064 | } | |
3065 | } | |
f0848276 JB |
3066 | |
3067 | napi_enable(napi); | |
021230d4 AV |
3068 | } |
3069 | } | |
3070 | ||
3071 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
3072 | { | |
3073 | int q_idx; | |
3074 | struct ixgbe_q_vector *q_vector; | |
3075 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3076 | ||
3077 | /* legacy and MSI only use one vector */ | |
3078 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3079 | q_vectors = 1; | |
3080 | ||
3081 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 3082 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
3083 | napi_disable(&q_vector->napi); |
3084 | } | |
3085 | } | |
3086 | ||
7a6b6f51 | 3087 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3088 | /* |
3089 | * ixgbe_configure_dcb - Configure DCB hardware | |
3090 | * @adapter: ixgbe adapter struct | |
3091 | * | |
3092 | * This is called by the driver on open to configure the DCB hardware. | |
3093 | * This is also called by the gennetlink interface when reconfiguring | |
3094 | * the DCB state. | |
3095 | */ | |
3096 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
3097 | { | |
3098 | struct ixgbe_hw *hw = &adapter->hw; | |
5f6c0181 | 3099 | u32 txdctl; |
2f90b865 AD |
3100 | int i, j; |
3101 | ||
3102 | ixgbe_dcb_check_config(&adapter->dcb_cfg); | |
3103 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG); | |
3104 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG); | |
3105 | ||
3106 | /* reconfigure the hardware */ | |
3107 | ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg); | |
3108 | ||
3109 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 3110 | j = adapter->tx_ring[i]->reg_idx; |
2f90b865 AD |
3111 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); |
3112 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
3113 | txdctl |= 32; | |
3114 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); | |
3115 | } | |
3116 | /* Enable VLAN tag insert/strip */ | |
5f6c0181 JB |
3117 | ixgbe_vlan_filter_enable(adapter); |
3118 | ||
2f90b865 AD |
3119 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
3120 | } | |
3121 | ||
3122 | #endif | |
9a799d71 AK |
3123 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
3124 | { | |
3125 | struct net_device *netdev = adapter->netdev; | |
c4cf55e5 | 3126 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
3127 | int i; |
3128 | ||
2c5645cf | 3129 | ixgbe_set_rx_mode(netdev); |
9a799d71 AK |
3130 | |
3131 | ixgbe_restore_vlan(adapter); | |
7a6b6f51 | 3132 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 | 3133 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
b352e40d YZ |
3134 | if (hw->mac.type == ixgbe_mac_82598EB) |
3135 | netif_set_gso_max_size(netdev, 32768); | |
3136 | else | |
3137 | netif_set_gso_max_size(netdev, 65536); | |
2f90b865 AD |
3138 | ixgbe_configure_dcb(adapter); |
3139 | } else { | |
3140 | netif_set_gso_max_size(netdev, 65536); | |
3141 | } | |
3142 | #else | |
3143 | netif_set_gso_max_size(netdev, 65536); | |
3144 | #endif | |
9a799d71 | 3145 | |
eacd73f7 YZ |
3146 | #ifdef IXGBE_FCOE |
3147 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
3148 | ixgbe_configure_fcoe(adapter); | |
3149 | ||
3150 | #endif /* IXGBE_FCOE */ | |
c4cf55e5 PWJ |
3151 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
3152 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 3153 | adapter->tx_ring[i]->atr_sample_rate = |
c4cf55e5 PWJ |
3154 | adapter->atr_sample_rate; |
3155 | ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc); | |
3156 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { | |
3157 | ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc); | |
3158 | } | |
3159 | ||
9a799d71 AK |
3160 | ixgbe_configure_tx(adapter); |
3161 | ixgbe_configure_rx(adapter); | |
3162 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 PW |
3163 | ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i], |
3164 | (adapter->rx_ring[i]->count - 1)); | |
9a799d71 AK |
3165 | } |
3166 | ||
e8e26350 PW |
3167 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
3168 | { | |
3169 | switch (hw->phy.type) { | |
3170 | case ixgbe_phy_sfp_avago: | |
3171 | case ixgbe_phy_sfp_ftl: | |
3172 | case ixgbe_phy_sfp_intel: | |
3173 | case ixgbe_phy_sfp_unknown: | |
ea0a04df DS |
3174 | case ixgbe_phy_sfp_passive_tyco: |
3175 | case ixgbe_phy_sfp_passive_unknown: | |
3176 | case ixgbe_phy_sfp_active_unknown: | |
3177 | case ixgbe_phy_sfp_ftl_active: | |
e8e26350 PW |
3178 | return true; |
3179 | default: | |
3180 | return false; | |
3181 | } | |
3182 | } | |
3183 | ||
0ecc061d | 3184 | /** |
e8e26350 PW |
3185 | * ixgbe_sfp_link_config - set up SFP+ link |
3186 | * @adapter: pointer to private adapter struct | |
3187 | **/ | |
3188 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
3189 | { | |
3190 | struct ixgbe_hw *hw = &adapter->hw; | |
3191 | ||
3192 | if (hw->phy.multispeed_fiber) { | |
3193 | /* | |
3194 | * In multispeed fiber setups, the device may not have | |
3195 | * had a physical connection when the driver loaded. | |
3196 | * If that's the case, the initial link configuration | |
3197 | * couldn't get the MAC into 10G or 1G mode, so we'll | |
3198 | * never have a link status change interrupt fire. | |
3199 | * We need to try and force an autonegotiation | |
3200 | * session, then bring up link. | |
3201 | */ | |
3202 | hw->mac.ops.setup_sfp(hw); | |
3203 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) | |
3204 | schedule_work(&adapter->multispeed_fiber_task); | |
3205 | } else { | |
3206 | /* | |
3207 | * Direct Attach Cu and non-multispeed fiber modules | |
3208 | * still need to be configured properly prior to | |
3209 | * attempting link. | |
3210 | */ | |
3211 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK)) | |
3212 | schedule_work(&adapter->sfp_config_module_task); | |
3213 | } | |
3214 | } | |
3215 | ||
3216 | /** | |
3217 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
3218 | * @hw: pointer to private hardware struct |
3219 | * | |
3220 | * Returns 0 on success, negative on failure | |
3221 | **/ | |
e8e26350 | 3222 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
3223 | { |
3224 | u32 autoneg; | |
8620a103 | 3225 | bool negotiation, link_up = false; |
0ecc061d PWJ |
3226 | u32 ret = IXGBE_ERR_LINK_SETUP; |
3227 | ||
3228 | if (hw->mac.ops.check_link) | |
3229 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
3230 | ||
3231 | if (ret) | |
3232 | goto link_cfg_out; | |
3233 | ||
3234 | if (hw->mac.ops.get_link_capabilities) | |
8620a103 | 3235 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); |
0ecc061d PWJ |
3236 | if (ret) |
3237 | goto link_cfg_out; | |
3238 | ||
8620a103 MC |
3239 | if (hw->mac.ops.setup_link) |
3240 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
3241 | link_cfg_out: |
3242 | return ret; | |
3243 | } | |
3244 | ||
e8e26350 PW |
3245 | #define IXGBE_MAX_RX_DESC_POLL 10 |
3246 | static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
3247 | int rxr) | |
3248 | { | |
4a0b9ca0 | 3249 | int j = adapter->rx_ring[rxr]->reg_idx; |
e8e26350 PW |
3250 | int k; |
3251 | ||
3252 | for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) { | |
3253 | if (IXGBE_READ_REG(&adapter->hw, | |
3254 | IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE) | |
3255 | break; | |
3256 | else | |
3257 | msleep(1); | |
3258 | } | |
3259 | if (k >= IXGBE_MAX_RX_DESC_POLL) { | |
3260 | DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d " | |
3261 | "not set within the polling period\n", rxr); | |
3262 | } | |
4a0b9ca0 PW |
3263 | ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr], |
3264 | (adapter->rx_ring[rxr]->count - 1)); | |
e8e26350 PW |
3265 | } |
3266 | ||
9a799d71 AK |
3267 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) |
3268 | { | |
3269 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 3270 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 3271 | int i, j = 0; |
e8e26350 | 3272 | int num_rx_rings = adapter->num_rx_queues; |
0ecc061d | 3273 | int err; |
9a799d71 | 3274 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 | 3275 | u32 txdctl, rxdctl, mhadd; |
e8e26350 | 3276 | u32 dmatxctl; |
021230d4 | 3277 | u32 gpie; |
c9205697 | 3278 | u32 ctrl_ext; |
9a799d71 | 3279 | |
5eba3699 AV |
3280 | ixgbe_get_hw_control(adapter); |
3281 | ||
021230d4 AV |
3282 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) || |
3283 | (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) { | |
9a799d71 AK |
3284 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
3285 | gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME | | |
b4617240 | 3286 | IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD); |
9a799d71 AK |
3287 | } else { |
3288 | /* MSI only */ | |
021230d4 | 3289 | gpie = 0; |
9a799d71 | 3290 | } |
1cdd1ec8 GR |
3291 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
3292 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
3293 | gpie |= IXGBE_GPIE_VTMODE_64; | |
3294 | } | |
021230d4 AV |
3295 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
3296 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
3297 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
9a799d71 AK |
3298 | } |
3299 | ||
9b471446 JB |
3300 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
3301 | /* | |
3302 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
3303 | * this saves a register write for every interrupt | |
3304 | */ | |
3305 | switch (hw->mac.type) { | |
3306 | case ixgbe_mac_82598EB: | |
3307 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3308 | break; | |
3309 | default: | |
3310 | case ixgbe_mac_82599EB: | |
3311 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); | |
3312 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
3313 | break; | |
3314 | } | |
3315 | } else { | |
021230d4 AV |
3316 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
3317 | * specifically only auto mask tx and rx interrupts */ | |
3318 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3319 | } | |
9a799d71 | 3320 | |
119fc60a MC |
3321 | /* Enable Thermal over heat sensor interrupt */ |
3322 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { | |
3323 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
3324 | gpie |= IXGBE_SDP0_GPIEN; | |
3325 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
3326 | } | |
3327 | ||
0befdb3e JB |
3328 | /* Enable fan failure interrupt if media type is copper */ |
3329 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
3330 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
3331 | gpie |= IXGBE_SDP1_GPIEN; | |
3332 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
3333 | } | |
3334 | ||
e8e26350 PW |
3335 | if (hw->mac.type == ixgbe_mac_82599EB) { |
3336 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
3337 | gpie |= IXGBE_SDP1_GPIEN; | |
3338 | gpie |= IXGBE_SDP2_GPIEN; | |
3339 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
3340 | } | |
3341 | ||
63f39bd1 YZ |
3342 | #ifdef IXGBE_FCOE |
3343 | /* adjust max frame to be able to do baby jumbo for FCoE */ | |
f34c5c82 | 3344 | if ((netdev->features & NETIF_F_FCOE_MTU) && |
63f39bd1 YZ |
3345 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) |
3346 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
3347 | ||
3348 | #endif /* IXGBE_FCOE */ | |
021230d4 | 3349 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
9a799d71 AK |
3350 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { |
3351 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
3352 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
3353 | ||
3354 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
3355 | } | |
3356 | ||
3357 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 3358 | j = adapter->tx_ring[i]->reg_idx; |
021230d4 | 3359 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); |
ef021194 JB |
3360 | if (adapter->rx_itr_setting == 0) { |
3361 | /* cannot set wthresh when itr==0 */ | |
3362 | txdctl &= ~0x007F0000; | |
3363 | } else { | |
3364 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ | |
3365 | txdctl |= (8 << 16); | |
3366 | } | |
e8e26350 PW |
3367 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
3368 | } | |
3369 | ||
3370 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
3371 | /* DMATXCTL.EN must be set after all Tx queue config is done */ | |
3372 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
3373 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
3374 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
3375 | } | |
3376 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 3377 | j = adapter->tx_ring[i]->reg_idx; |
e8e26350 | 3378 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); |
9a799d71 | 3379 | txdctl |= IXGBE_TXDCTL_ENABLE; |
021230d4 | 3380 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
1cdd1ec8 GR |
3381 | if (hw->mac.type == ixgbe_mac_82599EB) { |
3382 | int wait_loop = 10; | |
3383 | /* poll for Tx Enable ready */ | |
3384 | do { | |
3385 | msleep(1); | |
3386 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
3387 | } while (--wait_loop && | |
3388 | !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
3389 | if (!wait_loop) | |
3390 | DPRINTK(DRV, ERR, "Could not enable " | |
3391 | "Tx Queue %d\n", j); | |
3392 | } | |
9a799d71 AK |
3393 | } |
3394 | ||
e8e26350 | 3395 | for (i = 0; i < num_rx_rings; i++) { |
4a0b9ca0 | 3396 | j = adapter->rx_ring[i]->reg_idx; |
021230d4 AV |
3397 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); |
3398 | /* enable PTHRESH=32 descriptors (half the internal cache) | |
3399 | * and HTHRESH=0 descriptors (to minimize latency on fetch), | |
3400 | * this also removes a pesky rx_no_buffer_count increment */ | |
3401 | rxdctl |= 0x0020; | |
9a799d71 | 3402 | rxdctl |= IXGBE_RXDCTL_ENABLE; |
021230d4 | 3403 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl); |
e8e26350 PW |
3404 | if (hw->mac.type == ixgbe_mac_82599EB) |
3405 | ixgbe_rx_desc_queue_enable(adapter, i); | |
9a799d71 AK |
3406 | } |
3407 | /* enable all receives */ | |
3408 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
e8e26350 PW |
3409 | if (hw->mac.type == ixgbe_mac_82598EB) |
3410 | rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN); | |
3411 | else | |
3412 | rxdctl |= IXGBE_RXCTRL_RXEN; | |
3413 | hw->mac.ops.enable_rx_dma(hw, rxdctl); | |
9a799d71 AK |
3414 | |
3415 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
3416 | ixgbe_configure_msix(adapter); | |
3417 | else | |
3418 | ixgbe_configure_msi_and_legacy(adapter); | |
3419 | ||
61fac744 PW |
3420 | /* enable the optics */ |
3421 | if (hw->phy.multispeed_fiber) | |
3422 | hw->mac.ops.enable_tx_laser(hw); | |
3423 | ||
9a799d71 | 3424 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
3425 | ixgbe_napi_enable_all(adapter); |
3426 | ||
3427 | /* clear any pending interrupts, may auto mask */ | |
3428 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
3429 | ||
9a799d71 AK |
3430 | ixgbe_irq_enable(adapter); |
3431 | ||
bf069c97 DS |
3432 | /* |
3433 | * If this adapter has a fan, check to see if we had a failure | |
3434 | * before we enabled the interrupt. | |
3435 | */ | |
3436 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
3437 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
3438 | if (esdp & IXGBE_ESDP_SDP1) | |
3439 | DPRINTK(DRV, CRIT, | |
3440 | "Fan has stopped, replace the adapter\n"); | |
3441 | } | |
3442 | ||
e8e26350 PW |
3443 | /* |
3444 | * For hot-pluggable SFP+ devices, a new SFP+ module may have | |
19343de2 DS |
3445 | * arrived before interrupts were enabled but after probe. Such |
3446 | * devices wouldn't have their type identified yet. We need to | |
3447 | * kick off the SFP+ module setup first, then try to bring up link. | |
e8e26350 PW |
3448 | * If we're not hot-pluggable SFP+, we just need to configure link |
3449 | * and bring it up. | |
3450 | */ | |
19343de2 DS |
3451 | if (hw->phy.type == ixgbe_phy_unknown) { |
3452 | err = hw->phy.ops.identify(hw); | |
3453 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
5da43c1a DS |
3454 | /* |
3455 | * Take the device down and schedule the sfp tasklet | |
3456 | * which will unregister_netdev and log it. | |
3457 | */ | |
19343de2 | 3458 | ixgbe_down(adapter); |
5da43c1a | 3459 | schedule_work(&adapter->sfp_config_module_task); |
19343de2 DS |
3460 | return err; |
3461 | } | |
e8e26350 PW |
3462 | } |
3463 | ||
3464 | if (ixgbe_is_sfp(hw)) { | |
3465 | ixgbe_sfp_link_config(adapter); | |
3466 | } else { | |
3467 | err = ixgbe_non_sfp_link_config(hw); | |
3468 | if (err) | |
3469 | DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err); | |
3470 | } | |
0ecc061d | 3471 | |
c4cf55e5 PWJ |
3472 | for (i = 0; i < adapter->num_tx_queues; i++) |
3473 | set_bit(__IXGBE_FDIR_INIT_DONE, | |
4a0b9ca0 | 3474 | &(adapter->tx_ring[i]->reinit_state)); |
c4cf55e5 | 3475 | |
1da100bb PWJ |
3476 | /* enable transmits */ |
3477 | netif_tx_start_all_queues(netdev); | |
3478 | ||
9a799d71 AK |
3479 | /* bring the link up in the watchdog, this could race with our first |
3480 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
3481 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
3482 | adapter->link_check_timeout = jiffies; | |
9a799d71 | 3483 | mod_timer(&adapter->watchdog_timer, jiffies); |
c9205697 GR |
3484 | |
3485 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
3486 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
3487 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
3488 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
3489 | ||
9a799d71 AK |
3490 | return 0; |
3491 | } | |
3492 | ||
d4f80882 AV |
3493 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
3494 | { | |
3495 | WARN_ON(in_interrupt()); | |
3496 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
3497 | msleep(1); | |
3498 | ixgbe_down(adapter); | |
5809a1ae GR |
3499 | /* |
3500 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
3501 | * back up to give the VFs time to respond to the reset. The | |
3502 | * two second wait is based upon the watchdog timer cycle in | |
3503 | * the VF driver. | |
3504 | */ | |
3505 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3506 | msleep(2000); | |
d4f80882 AV |
3507 | ixgbe_up(adapter); |
3508 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
3509 | } | |
3510 | ||
9a799d71 AK |
3511 | int ixgbe_up(struct ixgbe_adapter *adapter) |
3512 | { | |
3513 | /* hardware has been reset, we need to reload some things */ | |
3514 | ixgbe_configure(adapter); | |
3515 | ||
3516 | return ixgbe_up_complete(adapter); | |
3517 | } | |
3518 | ||
3519 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
3520 | { | |
c44ade9e | 3521 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
3522 | int err; |
3523 | ||
3524 | err = hw->mac.ops.init_hw(hw); | |
da4dd0f7 PWJ |
3525 | switch (err) { |
3526 | case 0: | |
3527 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
3528 | break; | |
3529 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
3530 | dev_err(&adapter->pdev->dev, "master disable timed out\n"); | |
3531 | break; | |
794caeb2 PWJ |
3532 | case IXGBE_ERR_EEPROM_VERSION: |
3533 | /* We are running on a pre-production device, log a warning */ | |
3534 | dev_warn(&adapter->pdev->dev, "This device is a pre-production " | |
3535 | "adapter/LOM. Please be aware there may be issues " | |
3536 | "associated with your hardware. If you are " | |
3537 | "experiencing problems please contact your Intel or " | |
3538 | "hardware representative who provided you with this " | |
3539 | "hardware.\n"); | |
3540 | break; | |
da4dd0f7 PWJ |
3541 | default: |
3542 | dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err); | |
3543 | } | |
9a799d71 AK |
3544 | |
3545 | /* reprogram the RAR[0] in case user changed it. */ | |
1cdd1ec8 GR |
3546 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
3547 | IXGBE_RAH_AV); | |
9a799d71 AK |
3548 | } |
3549 | ||
9a799d71 AK |
3550 | /** |
3551 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
3552 | * @adapter: board private structure | |
3553 | * @rx_ring: ring to free buffers from | |
3554 | **/ | |
3555 | static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 3556 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
3557 | { |
3558 | struct pci_dev *pdev = adapter->pdev; | |
3559 | unsigned long size; | |
3560 | unsigned int i; | |
3561 | ||
3562 | /* Free all the Rx ring sk_buffs */ | |
3563 | ||
3564 | for (i = 0; i < rx_ring->count; i++) { | |
3565 | struct ixgbe_rx_buffer *rx_buffer_info; | |
3566 | ||
3567 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
3568 | if (rx_buffer_info->dma) { | |
1b507730 | 3569 | dma_unmap_single(&pdev->dev, rx_buffer_info->dma, |
b4617240 | 3570 | rx_ring->rx_buf_len, |
1b507730 | 3571 | DMA_FROM_DEVICE); |
9a799d71 AK |
3572 | rx_buffer_info->dma = 0; |
3573 | } | |
3574 | if (rx_buffer_info->skb) { | |
f8212f97 | 3575 | struct sk_buff *skb = rx_buffer_info->skb; |
9a799d71 | 3576 | rx_buffer_info->skb = NULL; |
f8212f97 AD |
3577 | do { |
3578 | struct sk_buff *this = skb; | |
e8171aaa | 3579 | if (IXGBE_RSC_CB(this)->delay_unmap) { |
1b507730 NN |
3580 | dma_unmap_single(&pdev->dev, |
3581 | IXGBE_RSC_CB(this)->dma, | |
43634e82 | 3582 | rx_ring->rx_buf_len, |
1b507730 | 3583 | DMA_FROM_DEVICE); |
fd3686a8 | 3584 | IXGBE_RSC_CB(this)->dma = 0; |
e8171aaa | 3585 | IXGBE_RSC_CB(skb)->delay_unmap = false; |
fd3686a8 | 3586 | } |
f8212f97 AD |
3587 | skb = skb->prev; |
3588 | dev_kfree_skb(this); | |
3589 | } while (skb); | |
9a799d71 AK |
3590 | } |
3591 | if (!rx_buffer_info->page) | |
3592 | continue; | |
4f57ca6e | 3593 | if (rx_buffer_info->page_dma) { |
1b507730 NN |
3594 | dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma, |
3595 | PAGE_SIZE / 2, DMA_FROM_DEVICE); | |
4f57ca6e JB |
3596 | rx_buffer_info->page_dma = 0; |
3597 | } | |
9a799d71 AK |
3598 | put_page(rx_buffer_info->page); |
3599 | rx_buffer_info->page = NULL; | |
762f4c57 | 3600 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
3601 | } |
3602 | ||
3603 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
3604 | memset(rx_ring->rx_buffer_info, 0, size); | |
3605 | ||
3606 | /* Zero out the descriptor ring */ | |
3607 | memset(rx_ring->desc, 0, rx_ring->size); | |
3608 | ||
3609 | rx_ring->next_to_clean = 0; | |
3610 | rx_ring->next_to_use = 0; | |
3611 | ||
9891ca7c JB |
3612 | if (rx_ring->head) |
3613 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
3614 | if (rx_ring->tail) | |
3615 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
9a799d71 AK |
3616 | } |
3617 | ||
3618 | /** | |
3619 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
3620 | * @adapter: board private structure | |
3621 | * @tx_ring: ring to be cleaned | |
3622 | **/ | |
3623 | static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 3624 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
3625 | { |
3626 | struct ixgbe_tx_buffer *tx_buffer_info; | |
3627 | unsigned long size; | |
3628 | unsigned int i; | |
3629 | ||
3630 | /* Free all the Tx ring sk_buffs */ | |
3631 | ||
3632 | for (i = 0; i < tx_ring->count; i++) { | |
3633 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3634 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
3635 | } | |
3636 | ||
3637 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
3638 | memset(tx_ring->tx_buffer_info, 0, size); | |
3639 | ||
3640 | /* Zero out the descriptor ring */ | |
3641 | memset(tx_ring->desc, 0, tx_ring->size); | |
3642 | ||
3643 | tx_ring->next_to_use = 0; | |
3644 | tx_ring->next_to_clean = 0; | |
3645 | ||
9891ca7c JB |
3646 | if (tx_ring->head) |
3647 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
3648 | if (tx_ring->tail) | |
3649 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
9a799d71 AK |
3650 | } |
3651 | ||
3652 | /** | |
021230d4 | 3653 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
3654 | * @adapter: board private structure |
3655 | **/ | |
021230d4 | 3656 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3657 | { |
3658 | int i; | |
3659 | ||
021230d4 | 3660 | for (i = 0; i < adapter->num_rx_queues; i++) |
4a0b9ca0 | 3661 | ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]); |
9a799d71 AK |
3662 | } |
3663 | ||
3664 | /** | |
021230d4 | 3665 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
3666 | * @adapter: board private structure |
3667 | **/ | |
021230d4 | 3668 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3669 | { |
3670 | int i; | |
3671 | ||
021230d4 | 3672 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 3673 | ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]); |
9a799d71 AK |
3674 | } |
3675 | ||
3676 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
3677 | { | |
3678 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 3679 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 3680 | u32 rxctrl; |
7f821875 JB |
3681 | u32 txdctl; |
3682 | int i, j; | |
9a799d71 AK |
3683 | |
3684 | /* signal that we are down to the interrupt handler */ | |
3685 | set_bit(__IXGBE_DOWN, &adapter->state); | |
3686 | ||
767081ad GR |
3687 | /* disable receive for all VFs and wait one second */ |
3688 | if (adapter->num_vfs) { | |
767081ad GR |
3689 | /* ping all the active vfs to let them know we are going down */ |
3690 | ixgbe_ping_all_vfs(adapter); | |
581d1aa7 | 3691 | |
767081ad GR |
3692 | /* Disable all VFTE/VFRE TX/RX */ |
3693 | ixgbe_disable_tx_rx(adapter); | |
581d1aa7 GR |
3694 | |
3695 | /* Mark all the VFs as inactive */ | |
3696 | for (i = 0 ; i < adapter->num_vfs; i++) | |
3697 | adapter->vfinfo[i].clear_to_send = 0; | |
767081ad GR |
3698 | } |
3699 | ||
9a799d71 | 3700 | /* disable receives */ |
7f821875 JB |
3701 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
3702 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 | 3703 | |
7f821875 | 3704 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
3705 | msleep(10); |
3706 | ||
7f821875 JB |
3707 | netif_tx_stop_all_queues(netdev); |
3708 | ||
0a1f87cb DS |
3709 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
3710 | del_timer_sync(&adapter->sfp_timer); | |
9a799d71 | 3711 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 3712 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 3713 | |
c0dfb90e JF |
3714 | netif_carrier_off(netdev); |
3715 | netif_tx_disable(netdev); | |
3716 | ||
3717 | ixgbe_irq_disable(adapter); | |
3718 | ||
3719 | ixgbe_napi_disable_all(adapter); | |
3720 | ||
c4cf55e5 PWJ |
3721 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
3722 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
3723 | cancel_work_sync(&adapter->fdir_reinit_task); | |
3724 | ||
119fc60a MC |
3725 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
3726 | cancel_work_sync(&adapter->check_overtemp_task); | |
3727 | ||
7f821875 JB |
3728 | /* disable transmits in the hardware now that interrupts are off */ |
3729 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 3730 | j = adapter->tx_ring[i]->reg_idx; |
7f821875 JB |
3731 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); |
3732 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), | |
3733 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); | |
3734 | } | |
88512539 PW |
3735 | /* Disable the Tx DMA engine on 82599 */ |
3736 | if (hw->mac.type == ixgbe_mac_82599EB) | |
3737 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, | |
3738 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & | |
3739 | ~IXGBE_DMATXCTL_TE)); | |
7f821875 | 3740 | |
9f756f01 JF |
3741 | /* power down the optics */ |
3742 | if (hw->phy.multispeed_fiber) | |
3743 | hw->mac.ops.disable_tx_laser(hw); | |
3744 | ||
9a713e7c PW |
3745 | /* clear n-tuple filters that are cached */ |
3746 | ethtool_ntuple_flush(netdev); | |
3747 | ||
6f4a0e45 PL |
3748 | if (!pci_channel_offline(adapter->pdev)) |
3749 | ixgbe_reset(adapter); | |
9a799d71 AK |
3750 | ixgbe_clean_all_tx_rings(adapter); |
3751 | ixgbe_clean_all_rx_rings(adapter); | |
3752 | ||
5dd2d332 | 3753 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 3754 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 3755 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 3756 | #endif |
9a799d71 AK |
3757 | } |
3758 | ||
9a799d71 | 3759 | /** |
021230d4 AV |
3760 | * ixgbe_poll - NAPI Rx polling callback |
3761 | * @napi: structure for representing this polling device | |
3762 | * @budget: how many packets driver is allowed to clean | |
3763 | * | |
3764 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 3765 | **/ |
021230d4 | 3766 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 3767 | { |
9a1a69ad JB |
3768 | struct ixgbe_q_vector *q_vector = |
3769 | container_of(napi, struct ixgbe_q_vector, napi); | |
021230d4 | 3770 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a1a69ad | 3771 | int tx_clean_complete, work_done = 0; |
9a799d71 | 3772 | |
5dd2d332 | 3773 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 3774 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
4a0b9ca0 PW |
3775 | ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]); |
3776 | ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]); | |
bd0362dd JC |
3777 | } |
3778 | #endif | |
3779 | ||
4a0b9ca0 PW |
3780 | tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]); |
3781 | ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget); | |
9a799d71 | 3782 | |
9a1a69ad | 3783 | if (!tx_clean_complete) |
d2c7ddd6 DM |
3784 | work_done = budget; |
3785 | ||
53e52c72 DM |
3786 | /* If budget not fully consumed, exit the polling mode */ |
3787 | if (work_done < budget) { | |
288379f0 | 3788 | napi_complete(napi); |
f7554a2b | 3789 | if (adapter->rx_itr_setting & 1) |
f494e8fa | 3790 | ixgbe_set_itr(adapter); |
d4f80882 | 3791 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 3792 | ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 3793 | } |
9a799d71 AK |
3794 | return work_done; |
3795 | } | |
3796 | ||
3797 | /** | |
3798 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
3799 | * @netdev: network interface device structure | |
3800 | **/ | |
3801 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
3802 | { | |
3803 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3804 | ||
3805 | /* Do the reset outside of interrupt context */ | |
3806 | schedule_work(&adapter->reset_task); | |
3807 | } | |
3808 | ||
3809 | static void ixgbe_reset_task(struct work_struct *work) | |
3810 | { | |
3811 | struct ixgbe_adapter *adapter; | |
3812 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
3813 | ||
2f90b865 AD |
3814 | /* If we're already down or resetting, just bail */ |
3815 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
3816 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
3817 | return; | |
3818 | ||
9a799d71 AK |
3819 | adapter->tx_timeout_count++; |
3820 | ||
dcd79aeb TI |
3821 | ixgbe_dump(adapter); |
3822 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
d4f80882 | 3823 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
3824 | } |
3825 | ||
bc97114d PWJ |
3826 | #ifdef CONFIG_IXGBE_DCB |
3827 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
b9804972 | 3828 | { |
bc97114d | 3829 | bool ret = false; |
0cefafad | 3830 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB]; |
b9804972 | 3831 | |
0cefafad JB |
3832 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) |
3833 | return ret; | |
3834 | ||
3835 | f->mask = 0x7 << 3; | |
3836 | adapter->num_rx_queues = f->indices; | |
3837 | adapter->num_tx_queues = f->indices; | |
3838 | ret = true; | |
2f90b865 | 3839 | |
bc97114d PWJ |
3840 | return ret; |
3841 | } | |
3842 | #endif | |
3843 | ||
4df10466 JB |
3844 | /** |
3845 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
3846 | * @adapter: board private structure to initialize | |
3847 | * | |
3848 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
3849 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
3850 | * | |
3851 | **/ | |
bc97114d PWJ |
3852 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
3853 | { | |
3854 | bool ret = false; | |
0cefafad | 3855 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS]; |
bc97114d PWJ |
3856 | |
3857 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
0cefafad JB |
3858 | f->mask = 0xF; |
3859 | adapter->num_rx_queues = f->indices; | |
3860 | adapter->num_tx_queues = f->indices; | |
bc97114d PWJ |
3861 | ret = true; |
3862 | } else { | |
bc97114d | 3863 | ret = false; |
b9804972 JB |
3864 | } |
3865 | ||
bc97114d PWJ |
3866 | return ret; |
3867 | } | |
3868 | ||
c4cf55e5 PWJ |
3869 | /** |
3870 | * ixgbe_set_fdir_queues: Allocate queues for Flow Director | |
3871 | * @adapter: board private structure to initialize | |
3872 | * | |
3873 | * Flow Director is an advanced Rx filter, attempting to get Rx flows back | |
3874 | * to the original CPU that initiated the Tx session. This runs in addition | |
3875 | * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the | |
3876 | * Rx load across CPUs using RSS. | |
3877 | * | |
3878 | **/ | |
3879 | static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter) | |
3880 | { | |
3881 | bool ret = false; | |
3882 | struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR]; | |
3883 | ||
3884 | f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices); | |
3885 | f_fdir->mask = 0; | |
3886 | ||
3887 | /* Flow Director must have RSS enabled */ | |
3888 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
3889 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
3890 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) { | |
3891 | adapter->num_tx_queues = f_fdir->indices; | |
3892 | adapter->num_rx_queues = f_fdir->indices; | |
3893 | ret = true; | |
3894 | } else { | |
3895 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
3896 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
3897 | } | |
3898 | return ret; | |
3899 | } | |
3900 | ||
0331a832 YZ |
3901 | #ifdef IXGBE_FCOE |
3902 | /** | |
3903 | * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE) | |
3904 | * @adapter: board private structure to initialize | |
3905 | * | |
3906 | * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges. | |
3907 | * The ring feature mask is not used as a mask for FCoE, as it can take any 8 | |
3908 | * rx queues out of the max number of rx queues, instead, it is used as the | |
3909 | * index of the first rx queue used by FCoE. | |
3910 | * | |
3911 | **/ | |
3912 | static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter) | |
3913 | { | |
3914 | bool ret = false; | |
3915 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
3916 | ||
3917 | f->indices = min((int)num_online_cpus(), f->indices); | |
3918 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
8de8b2e6 YZ |
3919 | adapter->num_rx_queues = 1; |
3920 | adapter->num_tx_queues = 1; | |
0331a832 YZ |
3921 | #ifdef CONFIG_IXGBE_DCB |
3922 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
d6dbee86 | 3923 | DPRINTK(PROBE, INFO, "FCoE enabled with DCB\n"); |
0331a832 YZ |
3924 | ixgbe_set_dcb_queues(adapter); |
3925 | } | |
3926 | #endif | |
3927 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
d6dbee86 | 3928 | DPRINTK(PROBE, INFO, "FCoE enabled with RSS\n"); |
8faa2a78 YZ |
3929 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || |
3930 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) | |
3931 | ixgbe_set_fdir_queues(adapter); | |
3932 | else | |
3933 | ixgbe_set_rss_queues(adapter); | |
0331a832 YZ |
3934 | } |
3935 | /* adding FCoE rx rings to the end */ | |
3936 | f->mask = adapter->num_rx_queues; | |
3937 | adapter->num_rx_queues += f->indices; | |
8de8b2e6 | 3938 | adapter->num_tx_queues += f->indices; |
0331a832 YZ |
3939 | |
3940 | ret = true; | |
3941 | } | |
3942 | ||
3943 | return ret; | |
3944 | } | |
3945 | ||
3946 | #endif /* IXGBE_FCOE */ | |
1cdd1ec8 GR |
3947 | /** |
3948 | * ixgbe_set_sriov_queues: Allocate queues for IOV use | |
3949 | * @adapter: board private structure to initialize | |
3950 | * | |
3951 | * IOV doesn't actually use anything, so just NAK the | |
3952 | * request for now and let the other queue routines | |
3953 | * figure out what to do. | |
3954 | */ | |
3955 | static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter) | |
3956 | { | |
3957 | return false; | |
3958 | } | |
3959 | ||
4df10466 JB |
3960 | /* |
3961 | * ixgbe_set_num_queues: Allocate queues for device, feature dependant | |
3962 | * @adapter: board private structure to initialize | |
3963 | * | |
3964 | * This is the top level queue allocation routine. The order here is very | |
3965 | * important, starting with the "most" number of features turned on at once, | |
3966 | * and ending with the smallest set of features. This way large combinations | |
3967 | * can be allocated if they're turned on, and smaller combinations are the | |
3968 | * fallthrough conditions. | |
3969 | * | |
3970 | **/ | |
bc97114d PWJ |
3971 | static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
3972 | { | |
1cdd1ec8 GR |
3973 | /* Start with base case */ |
3974 | adapter->num_rx_queues = 1; | |
3975 | adapter->num_tx_queues = 1; | |
3976 | adapter->num_rx_pools = adapter->num_rx_queues; | |
3977 | adapter->num_rx_queues_per_pool = 1; | |
3978 | ||
3979 | if (ixgbe_set_sriov_queues(adapter)) | |
3980 | return; | |
3981 | ||
0331a832 YZ |
3982 | #ifdef IXGBE_FCOE |
3983 | if (ixgbe_set_fcoe_queues(adapter)) | |
3984 | goto done; | |
3985 | ||
3986 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3987 | #ifdef CONFIG_IXGBE_DCB |
3988 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 3989 | goto done; |
bc97114d PWJ |
3990 | |
3991 | #endif | |
c4cf55e5 PWJ |
3992 | if (ixgbe_set_fdir_queues(adapter)) |
3993 | goto done; | |
3994 | ||
bc97114d | 3995 | if (ixgbe_set_rss_queues(adapter)) |
af22ab1b WF |
3996 | goto done; |
3997 | ||
3998 | /* fallback to base case */ | |
3999 | adapter->num_rx_queues = 1; | |
4000 | adapter->num_tx_queues = 1; | |
4001 | ||
4002 | done: | |
4003 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ | |
f0796d5c | 4004 | netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); |
b9804972 JB |
4005 | } |
4006 | ||
021230d4 | 4007 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 4008 | int vectors) |
021230d4 AV |
4009 | { |
4010 | int err, vector_threshold; | |
4011 | ||
4012 | /* We'll want at least 3 (vector_threshold): | |
4013 | * 1) TxQ[0] Cleanup | |
4014 | * 2) RxQ[0] Cleanup | |
4015 | * 3) Other (Link Status Change, etc.) | |
4016 | * 4) TCP Timer (optional) | |
4017 | */ | |
4018 | vector_threshold = MIN_MSIX_COUNT; | |
4019 | ||
4020 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
4021 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
4022 | * Right now, we simply care about how many we'll get; we'll | |
4023 | * set them up later while requesting irq's. | |
4024 | */ | |
4025 | while (vectors >= vector_threshold) { | |
4026 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
b4617240 | 4027 | vectors); |
021230d4 AV |
4028 | if (!err) /* Success in acquiring all requested vectors. */ |
4029 | break; | |
4030 | else if (err < 0) | |
4031 | vectors = 0; /* Nasty failure, quit now */ | |
4032 | else /* err == number of vectors we should try again with */ | |
4033 | vectors = err; | |
4034 | } | |
4035 | ||
4036 | if (vectors < vector_threshold) { | |
4037 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
4038 | * This just means we'll go with either a single MSI | |
4039 | * vector or fall back to legacy interrupts. | |
4040 | */ | |
4041 | DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n"); | |
4042 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
4043 | kfree(adapter->msix_entries); | |
4044 | adapter->msix_entries = NULL; | |
021230d4 AV |
4045 | } else { |
4046 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
4047 | /* |
4048 | * Adjust for only the vectors we'll use, which is minimum | |
4049 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
4050 | * vectors we were allocated. | |
4051 | */ | |
4052 | adapter->num_msix_vectors = min(vectors, | |
4053 | adapter->max_msix_q_vectors + NON_Q_VECTORS); | |
021230d4 AV |
4054 | } |
4055 | } | |
4056 | ||
021230d4 | 4057 | /** |
bc97114d | 4058 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
4059 | * @adapter: board private structure to initialize |
4060 | * | |
bc97114d PWJ |
4061 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
4062 | * | |
021230d4 | 4063 | **/ |
bc97114d | 4064 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 4065 | { |
bc97114d PWJ |
4066 | int i; |
4067 | bool ret = false; | |
4068 | ||
4069 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
4070 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 4071 | adapter->rx_ring[i]->reg_idx = i; |
bc97114d | 4072 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 4073 | adapter->tx_ring[i]->reg_idx = i; |
bc97114d PWJ |
4074 | ret = true; |
4075 | } else { | |
4076 | ret = false; | |
4077 | } | |
4078 | ||
4079 | return ret; | |
4080 | } | |
4081 | ||
4082 | #ifdef CONFIG_IXGBE_DCB | |
4083 | /** | |
4084 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
4085 | * @adapter: board private structure to initialize | |
4086 | * | |
4087 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
4088 | * | |
4089 | **/ | |
4090 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
4091 | { | |
4092 | int i; | |
4093 | bool ret = false; | |
4094 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
4095 | ||
4096 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
4097 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2f90b865 AD |
4098 | /* the number of queues is assumed to be symmetric */ |
4099 | for (i = 0; i < dcb_i; i++) { | |
4a0b9ca0 PW |
4100 | adapter->rx_ring[i]->reg_idx = i << 3; |
4101 | adapter->tx_ring[i]->reg_idx = i << 2; | |
2f90b865 | 4102 | } |
bc97114d | 4103 | ret = true; |
e8e26350 | 4104 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
f92ef202 PW |
4105 | if (dcb_i == 8) { |
4106 | /* | |
4107 | * Tx TC0 starts at: descriptor queue 0 | |
4108 | * Tx TC1 starts at: descriptor queue 32 | |
4109 | * Tx TC2 starts at: descriptor queue 64 | |
4110 | * Tx TC3 starts at: descriptor queue 80 | |
4111 | * Tx TC4 starts at: descriptor queue 96 | |
4112 | * Tx TC5 starts at: descriptor queue 104 | |
4113 | * Tx TC6 starts at: descriptor queue 112 | |
4114 | * Tx TC7 starts at: descriptor queue 120 | |
4115 | * | |
4116 | * Rx TC0-TC7 are offset by 16 queues each | |
4117 | */ | |
4118 | for (i = 0; i < 3; i++) { | |
4a0b9ca0 PW |
4119 | adapter->tx_ring[i]->reg_idx = i << 5; |
4120 | adapter->rx_ring[i]->reg_idx = i << 4; | |
f92ef202 PW |
4121 | } |
4122 | for ( ; i < 5; i++) { | |
4a0b9ca0 | 4123 | adapter->tx_ring[i]->reg_idx = |
f92ef202 | 4124 | ((i + 2) << 4); |
4a0b9ca0 | 4125 | adapter->rx_ring[i]->reg_idx = i << 4; |
f92ef202 PW |
4126 | } |
4127 | for ( ; i < dcb_i; i++) { | |
4a0b9ca0 | 4128 | adapter->tx_ring[i]->reg_idx = |
f92ef202 | 4129 | ((i + 8) << 3); |
4a0b9ca0 | 4130 | adapter->rx_ring[i]->reg_idx = i << 4; |
f92ef202 PW |
4131 | } |
4132 | ||
4133 | ret = true; | |
4134 | } else if (dcb_i == 4) { | |
4135 | /* | |
4136 | * Tx TC0 starts at: descriptor queue 0 | |
4137 | * Tx TC1 starts at: descriptor queue 64 | |
4138 | * Tx TC2 starts at: descriptor queue 96 | |
4139 | * Tx TC3 starts at: descriptor queue 112 | |
4140 | * | |
4141 | * Rx TC0-TC3 are offset by 32 queues each | |
4142 | */ | |
4a0b9ca0 PW |
4143 | adapter->tx_ring[0]->reg_idx = 0; |
4144 | adapter->tx_ring[1]->reg_idx = 64; | |
4145 | adapter->tx_ring[2]->reg_idx = 96; | |
4146 | adapter->tx_ring[3]->reg_idx = 112; | |
f92ef202 | 4147 | for (i = 0 ; i < dcb_i; i++) |
4a0b9ca0 | 4148 | adapter->rx_ring[i]->reg_idx = i << 5; |
f92ef202 PW |
4149 | |
4150 | ret = true; | |
4151 | } else { | |
4152 | ret = false; | |
e8e26350 | 4153 | } |
bc97114d PWJ |
4154 | } else { |
4155 | ret = false; | |
021230d4 | 4156 | } |
bc97114d PWJ |
4157 | } else { |
4158 | ret = false; | |
021230d4 | 4159 | } |
bc97114d PWJ |
4160 | |
4161 | return ret; | |
4162 | } | |
4163 | #endif | |
4164 | ||
c4cf55e5 PWJ |
4165 | /** |
4166 | * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director | |
4167 | * @adapter: board private structure to initialize | |
4168 | * | |
4169 | * Cache the descriptor ring offsets for Flow Director to the assigned rings. | |
4170 | * | |
4171 | **/ | |
4172 | static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter) | |
4173 | { | |
4174 | int i; | |
4175 | bool ret = false; | |
4176 | ||
4177 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
4178 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
4179 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) { | |
4180 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 4181 | adapter->rx_ring[i]->reg_idx = i; |
c4cf55e5 | 4182 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 4183 | adapter->tx_ring[i]->reg_idx = i; |
c4cf55e5 PWJ |
4184 | ret = true; |
4185 | } | |
4186 | ||
4187 | return ret; | |
4188 | } | |
4189 | ||
0331a832 YZ |
4190 | #ifdef IXGBE_FCOE |
4191 | /** | |
4192 | * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE | |
4193 | * @adapter: board private structure to initialize | |
4194 | * | |
4195 | * Cache the descriptor ring offsets for FCoE mode to the assigned rings. | |
4196 | * | |
4197 | */ | |
4198 | static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter) | |
4199 | { | |
8de8b2e6 | 4200 | int i, fcoe_rx_i = 0, fcoe_tx_i = 0; |
0331a832 YZ |
4201 | bool ret = false; |
4202 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
4203 | ||
4204 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
4205 | #ifdef CONFIG_IXGBE_DCB | |
4206 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
8de8b2e6 YZ |
4207 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; |
4208 | ||
0331a832 | 4209 | ixgbe_cache_ring_dcb(adapter); |
8de8b2e6 | 4210 | /* find out queues in TC for FCoE */ |
4a0b9ca0 PW |
4211 | fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1; |
4212 | fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1; | |
8de8b2e6 YZ |
4213 | /* |
4214 | * In 82599, the number of Tx queues for each traffic | |
4215 | * class for both 8-TC and 4-TC modes are: | |
4216 | * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 | |
4217 | * 8 TCs: 32 32 16 16 8 8 8 8 | |
4218 | * 4 TCs: 64 64 32 32 | |
4219 | * We have max 8 queues for FCoE, where 8 the is | |
4220 | * FCoE redirection table size. If TC for FCoE is | |
4221 | * less than or equal to TC3, we have enough queues | |
4222 | * to add max of 8 queues for FCoE, so we start FCoE | |
4223 | * tx descriptor from the next one, i.e., reg_idx + 1. | |
4224 | * If TC for FCoE is above TC3, implying 8 TC mode, | |
4225 | * and we need 8 for FCoE, we have to take all queues | |
4226 | * in that traffic class for FCoE. | |
4227 | */ | |
4228 | if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3)) | |
4229 | fcoe_tx_i--; | |
0331a832 YZ |
4230 | } |
4231 | #endif /* CONFIG_IXGBE_DCB */ | |
4232 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
8faa2a78 YZ |
4233 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || |
4234 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) | |
4235 | ixgbe_cache_ring_fdir(adapter); | |
4236 | else | |
4237 | ixgbe_cache_ring_rss(adapter); | |
4238 | ||
8de8b2e6 YZ |
4239 | fcoe_rx_i = f->mask; |
4240 | fcoe_tx_i = f->mask; | |
4241 | } | |
4242 | for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) { | |
4a0b9ca0 PW |
4243 | adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i; |
4244 | adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i; | |
0331a832 | 4245 | } |
0331a832 YZ |
4246 | ret = true; |
4247 | } | |
4248 | return ret; | |
4249 | } | |
4250 | ||
4251 | #endif /* IXGBE_FCOE */ | |
1cdd1ec8 GR |
4252 | /** |
4253 | * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov | |
4254 | * @adapter: board private structure to initialize | |
4255 | * | |
4256 | * SR-IOV doesn't use any descriptor rings but changes the default if | |
4257 | * no other mapping is used. | |
4258 | * | |
4259 | */ | |
4260 | static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter) | |
4261 | { | |
4a0b9ca0 PW |
4262 | adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2; |
4263 | adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2; | |
1cdd1ec8 GR |
4264 | if (adapter->num_vfs) |
4265 | return true; | |
4266 | else | |
4267 | return false; | |
4268 | } | |
4269 | ||
bc97114d PWJ |
4270 | /** |
4271 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
4272 | * @adapter: board private structure to initialize | |
4273 | * | |
4274 | * Once we know the feature-set enabled for the device, we'll cache | |
4275 | * the register offset the descriptor ring is assigned to. | |
4276 | * | |
4277 | * Note, the order the various feature calls is important. It must start with | |
4278 | * the "most" features enabled at the same time, then trickle down to the | |
4279 | * least amount of features turned on at once. | |
4280 | **/ | |
4281 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
4282 | { | |
4283 | /* start with default case */ | |
4a0b9ca0 PW |
4284 | adapter->rx_ring[0]->reg_idx = 0; |
4285 | adapter->tx_ring[0]->reg_idx = 0; | |
bc97114d | 4286 | |
1cdd1ec8 GR |
4287 | if (ixgbe_cache_ring_sriov(adapter)) |
4288 | return; | |
4289 | ||
0331a832 YZ |
4290 | #ifdef IXGBE_FCOE |
4291 | if (ixgbe_cache_ring_fcoe(adapter)) | |
4292 | return; | |
4293 | ||
4294 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
4295 | #ifdef CONFIG_IXGBE_DCB |
4296 | if (ixgbe_cache_ring_dcb(adapter)) | |
4297 | return; | |
4298 | ||
4299 | #endif | |
c4cf55e5 PWJ |
4300 | if (ixgbe_cache_ring_fdir(adapter)) |
4301 | return; | |
4302 | ||
bc97114d PWJ |
4303 | if (ixgbe_cache_ring_rss(adapter)) |
4304 | return; | |
021230d4 AV |
4305 | } |
4306 | ||
9a799d71 AK |
4307 | /** |
4308 | * ixgbe_alloc_queues - Allocate memory for all rings | |
4309 | * @adapter: board private structure to initialize | |
4310 | * | |
4311 | * We allocate one ring per queue at run-time since we don't know the | |
4df10466 JB |
4312 | * number of queues at compile-time. The polling_netdev array is |
4313 | * intended for Multiqueue, but should work fine with a single queue. | |
9a799d71 | 4314 | **/ |
2f90b865 | 4315 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4316 | { |
4317 | int i; | |
4a0b9ca0 | 4318 | int orig_node = adapter->node; |
9a799d71 | 4319 | |
021230d4 | 4320 | for (i = 0; i < adapter->num_tx_queues; i++) { |
4a0b9ca0 PW |
4321 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
4322 | if (orig_node == -1) { | |
4323 | int cur_node = next_online_node(adapter->node); | |
4324 | if (cur_node == MAX_NUMNODES) | |
4325 | cur_node = first_online_node; | |
4326 | adapter->node = cur_node; | |
4327 | } | |
4328 | ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL, | |
4329 | adapter->node); | |
4330 | if (!ring) | |
4331 | ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL); | |
4332 | if (!ring) | |
4333 | goto err_tx_ring_allocation; | |
4334 | ring->count = adapter->tx_ring_count; | |
4335 | ring->queue_index = i; | |
4336 | ring->numa_node = adapter->node; | |
4337 | ||
4338 | adapter->tx_ring[i] = ring; | |
021230d4 | 4339 | } |
b9804972 | 4340 | |
4a0b9ca0 PW |
4341 | /* Restore the adapter's original node */ |
4342 | adapter->node = orig_node; | |
4343 | ||
9a799d71 | 4344 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 PW |
4345 | struct ixgbe_ring *ring = adapter->rx_ring[i]; |
4346 | if (orig_node == -1) { | |
4347 | int cur_node = next_online_node(adapter->node); | |
4348 | if (cur_node == MAX_NUMNODES) | |
4349 | cur_node = first_online_node; | |
4350 | adapter->node = cur_node; | |
4351 | } | |
4352 | ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL, | |
4353 | adapter->node); | |
4354 | if (!ring) | |
4355 | ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL); | |
4356 | if (!ring) | |
4357 | goto err_rx_ring_allocation; | |
4358 | ring->count = adapter->rx_ring_count; | |
4359 | ring->queue_index = i; | |
4360 | ring->numa_node = adapter->node; | |
4361 | ||
4362 | adapter->rx_ring[i] = ring; | |
021230d4 AV |
4363 | } |
4364 | ||
4a0b9ca0 PW |
4365 | /* Restore the adapter's original node */ |
4366 | adapter->node = orig_node; | |
4367 | ||
021230d4 AV |
4368 | ixgbe_cache_ring_register(adapter); |
4369 | ||
4370 | return 0; | |
4371 | ||
4372 | err_rx_ring_allocation: | |
4a0b9ca0 PW |
4373 | for (i = 0; i < adapter->num_tx_queues; i++) |
4374 | kfree(adapter->tx_ring[i]); | |
021230d4 AV |
4375 | err_tx_ring_allocation: |
4376 | return -ENOMEM; | |
4377 | } | |
4378 | ||
4379 | /** | |
4380 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
4381 | * @adapter: board private structure to initialize | |
4382 | * | |
4383 | * Attempt to configure the interrupts using the best available | |
4384 | * capabilities of the hardware and the kernel. | |
4385 | **/ | |
feea6a57 | 4386 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 4387 | { |
8be0e467 | 4388 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
4389 | int err = 0; |
4390 | int vector, v_budget; | |
4391 | ||
4392 | /* | |
4393 | * It's easy to be greedy for MSI-X vectors, but it really | |
4394 | * doesn't do us much good if we have a lot more vectors | |
4395 | * than CPU's. So let's be conservative and only ask for | |
342bde1b | 4396 | * (roughly) the same number of vectors as there are CPU's. |
021230d4 AV |
4397 | */ |
4398 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
342bde1b | 4399 | (int)num_online_cpus()) + NON_Q_VECTORS; |
021230d4 AV |
4400 | |
4401 | /* | |
4402 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
4403 | * hw.mac->max_msix_vectors vectors. With features |
4404 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
4405 | * descriptor queues supported by our device. Thus, we cap it off in | |
4406 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 4407 | */ |
8be0e467 | 4408 | v_budget = min(v_budget, (int)hw->mac.max_msix_vectors); |
021230d4 AV |
4409 | |
4410 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
4411 | * mean we disable MSI-X capabilities of the adapter. */ | |
4412 | adapter->msix_entries = kcalloc(v_budget, | |
b4617240 | 4413 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
4414 | if (adapter->msix_entries) { |
4415 | for (vector = 0; vector < v_budget; vector++) | |
4416 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 4417 | |
7a921c93 | 4418 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 4419 | |
7a921c93 AD |
4420 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
4421 | goto out; | |
4422 | } | |
26d27844 | 4423 | |
7a921c93 AD |
4424 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
4425 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
c4cf55e5 PWJ |
4426 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
4427 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
4428 | adapter->atr_sample_rate = 0; | |
1cdd1ec8 GR |
4429 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
4430 | ixgbe_disable_sriov(adapter); | |
4431 | ||
7a921c93 | 4432 | ixgbe_set_num_queues(adapter); |
021230d4 | 4433 | |
021230d4 AV |
4434 | err = pci_enable_msi(adapter->pdev); |
4435 | if (!err) { | |
4436 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
4437 | } else { | |
4438 | DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, " | |
b4617240 | 4439 | "falling back to legacy. Error: %d\n", err); |
021230d4 AV |
4440 | /* reset err */ |
4441 | err = 0; | |
4442 | } | |
4443 | ||
4444 | out: | |
021230d4 AV |
4445 | return err; |
4446 | } | |
4447 | ||
7a921c93 AD |
4448 | /** |
4449 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
4450 | * @adapter: board private structure to initialize | |
4451 | * | |
4452 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
4453 | * return -ENOMEM. | |
4454 | **/ | |
4455 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
4456 | { | |
4457 | int q_idx, num_q_vectors; | |
4458 | struct ixgbe_q_vector *q_vector; | |
4459 | int napi_vectors; | |
4460 | int (*poll)(struct napi_struct *, int); | |
4461 | ||
4462 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
4463 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
4464 | napi_vectors = adapter->num_rx_queues; | |
91281fd3 | 4465 | poll = &ixgbe_clean_rxtx_many; |
7a921c93 AD |
4466 | } else { |
4467 | num_q_vectors = 1; | |
4468 | napi_vectors = 1; | |
4469 | poll = &ixgbe_poll; | |
4470 | } | |
4471 | ||
4472 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
1a6c14a2 JB |
4473 | q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector), |
4474 | GFP_KERNEL, adapter->node); | |
4475 | if (!q_vector) | |
4476 | q_vector = kzalloc(sizeof(struct ixgbe_q_vector), | |
4477 | GFP_KERNEL); | |
7a921c93 AD |
4478 | if (!q_vector) |
4479 | goto err_out; | |
4480 | q_vector->adapter = adapter; | |
f7554a2b NS |
4481 | if (q_vector->txr_count && !q_vector->rxr_count) |
4482 | q_vector->eitr = adapter->tx_eitr_param; | |
4483 | else | |
4484 | q_vector->eitr = adapter->rx_eitr_param; | |
fe49f04a | 4485 | q_vector->v_idx = q_idx; |
91281fd3 | 4486 | netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64); |
7a921c93 AD |
4487 | adapter->q_vector[q_idx] = q_vector; |
4488 | } | |
4489 | ||
4490 | return 0; | |
4491 | ||
4492 | err_out: | |
4493 | while (q_idx) { | |
4494 | q_idx--; | |
4495 | q_vector = adapter->q_vector[q_idx]; | |
4496 | netif_napi_del(&q_vector->napi); | |
4497 | kfree(q_vector); | |
4498 | adapter->q_vector[q_idx] = NULL; | |
4499 | } | |
4500 | return -ENOMEM; | |
4501 | } | |
4502 | ||
4503 | /** | |
4504 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
4505 | * @adapter: board private structure to initialize | |
4506 | * | |
4507 | * This function frees the memory allocated to the q_vectors. In addition if | |
4508 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
4509 | * to freeing the q_vector. | |
4510 | **/ | |
4511 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
4512 | { | |
4513 | int q_idx, num_q_vectors; | |
7a921c93 | 4514 | |
91281fd3 | 4515 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
7a921c93 | 4516 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
91281fd3 | 4517 | else |
7a921c93 | 4518 | num_q_vectors = 1; |
7a921c93 AD |
4519 | |
4520 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
4521 | struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx]; | |
7a921c93 | 4522 | adapter->q_vector[q_idx] = NULL; |
91281fd3 | 4523 | netif_napi_del(&q_vector->napi); |
7a921c93 AD |
4524 | kfree(q_vector); |
4525 | } | |
4526 | } | |
4527 | ||
7b25cdba | 4528 | static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
4529 | { |
4530 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
4531 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
4532 | pci_disable_msix(adapter->pdev); | |
4533 | kfree(adapter->msix_entries); | |
4534 | adapter->msix_entries = NULL; | |
4535 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
4536 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
4537 | pci_disable_msi(adapter->pdev); | |
4538 | } | |
021230d4 AV |
4539 | } |
4540 | ||
4541 | /** | |
4542 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
4543 | * @adapter: board private structure to initialize | |
4544 | * | |
4545 | * We determine which interrupt scheme to use based on... | |
4546 | * - Kernel support (MSI, MSI-X) | |
4547 | * - which can be user-defined (via MODULE_PARAM) | |
4548 | * - Hardware queue count (num_*_queues) | |
4549 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
4550 | **/ | |
2f90b865 | 4551 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
4552 | { |
4553 | int err; | |
4554 | ||
4555 | /* Number of supported queues */ | |
4556 | ixgbe_set_num_queues(adapter); | |
4557 | ||
021230d4 AV |
4558 | err = ixgbe_set_interrupt_capability(adapter); |
4559 | if (err) { | |
4560 | DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n"); | |
4561 | goto err_set_interrupt; | |
9a799d71 AK |
4562 | } |
4563 | ||
7a921c93 AD |
4564 | err = ixgbe_alloc_q_vectors(adapter); |
4565 | if (err) { | |
4566 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queue " | |
4567 | "vectors\n"); | |
4568 | goto err_alloc_q_vectors; | |
4569 | } | |
4570 | ||
4571 | err = ixgbe_alloc_queues(adapter); | |
4572 | if (err) { | |
4573 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); | |
4574 | goto err_alloc_queues; | |
4575 | } | |
4576 | ||
021230d4 | 4577 | DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, " |
b4617240 PW |
4578 | "Tx Queue count = %u\n", |
4579 | (adapter->num_rx_queues > 1) ? "Enabled" : | |
4580 | "Disabled", adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
4581 | |
4582 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4583 | ||
9a799d71 | 4584 | return 0; |
021230d4 | 4585 | |
7a921c93 AD |
4586 | err_alloc_queues: |
4587 | ixgbe_free_q_vectors(adapter); | |
4588 | err_alloc_q_vectors: | |
4589 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 4590 | err_set_interrupt: |
7a921c93 AD |
4591 | return err; |
4592 | } | |
4593 | ||
4594 | /** | |
4595 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
4596 | * @adapter: board private structure to clear interrupt scheme on | |
4597 | * | |
4598 | * We go through and clear interrupt specific resources and reset the structure | |
4599 | * to pre-load conditions | |
4600 | **/ | |
4601 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
4602 | { | |
4a0b9ca0 PW |
4603 | int i; |
4604 | ||
4605 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4606 | kfree(adapter->tx_ring[i]); | |
4607 | adapter->tx_ring[i] = NULL; | |
4608 | } | |
4609 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4610 | kfree(adapter->rx_ring[i]); | |
4611 | adapter->rx_ring[i] = NULL; | |
4612 | } | |
7a921c93 AD |
4613 | |
4614 | ixgbe_free_q_vectors(adapter); | |
4615 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
4616 | } |
4617 | ||
c4900be0 DS |
4618 | /** |
4619 | * ixgbe_sfp_timer - worker thread to find a missing module | |
4620 | * @data: pointer to our adapter struct | |
4621 | **/ | |
4622 | static void ixgbe_sfp_timer(unsigned long data) | |
4623 | { | |
4624 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
4625 | ||
4df10466 JB |
4626 | /* |
4627 | * Do the sfp_timer outside of interrupt context due to the | |
c4900be0 DS |
4628 | * delays that sfp+ detection requires |
4629 | */ | |
4630 | schedule_work(&adapter->sfp_task); | |
4631 | } | |
4632 | ||
4633 | /** | |
4634 | * ixgbe_sfp_task - worker thread to find a missing module | |
4635 | * @work: pointer to work_struct containing our data | |
4636 | **/ | |
4637 | static void ixgbe_sfp_task(struct work_struct *work) | |
4638 | { | |
4639 | struct ixgbe_adapter *adapter = container_of(work, | |
4640 | struct ixgbe_adapter, | |
4641 | sfp_task); | |
4642 | struct ixgbe_hw *hw = &adapter->hw; | |
4643 | ||
4644 | if ((hw->phy.type == ixgbe_phy_nl) && | |
4645 | (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { | |
4646 | s32 ret = hw->phy.ops.identify_sfp(hw); | |
63d6e1d8 | 4647 | if (ret == IXGBE_ERR_SFP_NOT_PRESENT) |
c4900be0 DS |
4648 | goto reschedule; |
4649 | ret = hw->phy.ops.reset(hw); | |
4650 | if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
88d2b81f DS |
4651 | dev_err(&adapter->pdev->dev, "failed to initialize " |
4652 | "because an unsupported SFP+ module type " | |
4653 | "was detected.\n" | |
4654 | "Reload the driver after installing a " | |
4655 | "supported module.\n"); | |
c4900be0 DS |
4656 | unregister_netdev(adapter->netdev); |
4657 | } else { | |
4658 | DPRINTK(PROBE, INFO, "detected SFP+: %d\n", | |
4659 | hw->phy.sfp_type); | |
4660 | } | |
4661 | /* don't need this routine any more */ | |
4662 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
4663 | } | |
4664 | return; | |
4665 | reschedule: | |
4666 | if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) | |
4667 | mod_timer(&adapter->sfp_timer, | |
4668 | round_jiffies(jiffies + (2 * HZ))); | |
4669 | } | |
4670 | ||
9a799d71 AK |
4671 | /** |
4672 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
4673 | * @adapter: board private structure to initialize | |
4674 | * | |
4675 | * ixgbe_sw_init initializes the Adapter private data structure. | |
4676 | * Fields are initialized based on PCI device information and | |
4677 | * OS network device settings (MTU size). | |
4678 | **/ | |
4679 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
4680 | { | |
4681 | struct ixgbe_hw *hw = &adapter->hw; | |
4682 | struct pci_dev *pdev = adapter->pdev; | |
9a713e7c | 4683 | struct net_device *dev = adapter->netdev; |
021230d4 | 4684 | unsigned int rss; |
7a6b6f51 | 4685 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4686 | int j; |
4687 | struct tc_configuration *tc; | |
4688 | #endif | |
021230d4 | 4689 | |
c44ade9e JB |
4690 | /* PCI config space info */ |
4691 | ||
4692 | hw->vendor_id = pdev->vendor; | |
4693 | hw->device_id = pdev->device; | |
4694 | hw->revision_id = pdev->revision; | |
4695 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
4696 | hw->subsystem_device_id = pdev->subsystem_device; | |
4697 | ||
021230d4 AV |
4698 | /* Set capability flags */ |
4699 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
4700 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
4701 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 4702 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
bf069c97 DS |
4703 | if (hw->mac.type == ixgbe_mac_82598EB) { |
4704 | if (hw->device_id == IXGBE_DEV_ID_82598AT) | |
4705 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 4706 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bf069c97 | 4707 | } else if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 4708 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
0c19d6af PWJ |
4709 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
4710 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
119fc60a MC |
4711 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) |
4712 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
9a713e7c PW |
4713 | if (dev->features & NETIF_F_NTUPLE) { |
4714 | /* Flow Director perfect filter enabled */ | |
4715 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
4716 | adapter->atr_sample_rate = 0; | |
4717 | spin_lock_init(&adapter->fdir_perfect_lock); | |
4718 | } else { | |
4719 | /* Flow Director hash filters enabled */ | |
4720 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
4721 | adapter->atr_sample_rate = 20; | |
4722 | } | |
c4cf55e5 PWJ |
4723 | adapter->ring_feature[RING_F_FDIR].indices = |
4724 | IXGBE_MAX_FDIR_INDICES; | |
c4cf55e5 | 4725 | adapter->fdir_pballoc = 0; |
eacd73f7 | 4726 | #ifdef IXGBE_FCOE |
0d551589 YZ |
4727 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
4728 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
4729 | adapter->ring_feature[RING_F_FCOE].indices = 0; | |
61a0f421 | 4730 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 YZ |
4731 | /* Default traffic class to use for FCoE */ |
4732 | adapter->fcoe.tc = IXGBE_FCOE_DEFTC; | |
61a0f421 | 4733 | #endif |
eacd73f7 | 4734 | #endif /* IXGBE_FCOE */ |
f8212f97 | 4735 | } |
2f90b865 | 4736 | |
7a6b6f51 | 4737 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4738 | /* Configure DCB traffic classes */ |
4739 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
4740 | tc = &adapter->dcb_cfg.tc_config[j]; | |
4741 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
4742 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
4743 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
4744 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
4745 | tc->dcb_pfc = pfc_disabled; | |
4746 | } | |
4747 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
4748 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
4749 | adapter->dcb_cfg.rx_pba_cfg = pba_equal; | |
264857b8 | 4750 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 AD |
4751 | adapter->dcb_cfg.round_robin_enable = false; |
4752 | adapter->dcb_set_bitmap = 0x00; | |
4753 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, | |
4754 | adapter->ring_feature[RING_F_DCB].indices); | |
4755 | ||
4756 | #endif | |
9a799d71 AK |
4757 | |
4758 | /* default flow control settings */ | |
cd7664f6 | 4759 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 4760 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
264857b8 PWJ |
4761 | #ifdef CONFIG_DCB |
4762 | adapter->last_lfc_mode = hw->fc.current_mode; | |
4763 | #endif | |
2b9ade93 JB |
4764 | hw->fc.high_water = IXGBE_DEFAULT_FCRTH; |
4765 | hw->fc.low_water = IXGBE_DEFAULT_FCRTL; | |
4766 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; | |
4767 | hw->fc.send_xon = true; | |
71fd570b | 4768 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 4769 | |
30efa5a3 | 4770 | /* enable itr by default in dynamic mode */ |
f7554a2b NS |
4771 | adapter->rx_itr_setting = 1; |
4772 | adapter->rx_eitr_param = 20000; | |
4773 | adapter->tx_itr_setting = 1; | |
4774 | adapter->tx_eitr_param = 10000; | |
30efa5a3 JB |
4775 | |
4776 | /* set defaults for eitr in MegaBytes */ | |
4777 | adapter->eitr_low = 10; | |
4778 | adapter->eitr_high = 20; | |
4779 | ||
4780 | /* set default ring sizes */ | |
4781 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
4782 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
4783 | ||
9a799d71 | 4784 | /* initialize eeprom parameters */ |
c44ade9e | 4785 | if (ixgbe_init_eeprom_params_generic(hw)) { |
9a799d71 AK |
4786 | dev_err(&pdev->dev, "EEPROM initialization failed\n"); |
4787 | return -EIO; | |
4788 | } | |
4789 | ||
021230d4 | 4790 | /* enable rx csum by default */ |
9a799d71 AK |
4791 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
4792 | ||
1a6c14a2 JB |
4793 | /* get assigned NUMA node */ |
4794 | adapter->node = dev_to_node(&pdev->dev); | |
4795 | ||
9a799d71 AK |
4796 | set_bit(__IXGBE_DOWN, &adapter->state); |
4797 | ||
4798 | return 0; | |
4799 | } | |
4800 | ||
4801 | /** | |
4802 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
4803 | * @adapter: board private structure | |
3a581073 | 4804 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4805 | * |
4806 | * Return 0 on success, negative on failure | |
4807 | **/ | |
4808 | int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter, | |
e01c31a5 | 4809 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
4810 | { |
4811 | struct pci_dev *pdev = adapter->pdev; | |
4812 | int size; | |
4813 | ||
3a581073 | 4814 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
4a0b9ca0 | 4815 | tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node); |
1a6c14a2 JB |
4816 | if (!tx_ring->tx_buffer_info) |
4817 | tx_ring->tx_buffer_info = vmalloc(size); | |
e01c31a5 JB |
4818 | if (!tx_ring->tx_buffer_info) |
4819 | goto err; | |
3a581073 | 4820 | memset(tx_ring->tx_buffer_info, 0, size); |
9a799d71 AK |
4821 | |
4822 | /* round up to nearest 4K */ | |
12207e49 | 4823 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 4824 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 4825 | |
1b507730 NN |
4826 | tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size, |
4827 | &tx_ring->dma, GFP_KERNEL); | |
e01c31a5 JB |
4828 | if (!tx_ring->desc) |
4829 | goto err; | |
9a799d71 | 4830 | |
3a581073 JB |
4831 | tx_ring->next_to_use = 0; |
4832 | tx_ring->next_to_clean = 0; | |
4833 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 4834 | return 0; |
e01c31a5 JB |
4835 | |
4836 | err: | |
4837 | vfree(tx_ring->tx_buffer_info); | |
4838 | tx_ring->tx_buffer_info = NULL; | |
4839 | DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit " | |
4840 | "descriptor ring\n"); | |
4841 | return -ENOMEM; | |
9a799d71 AK |
4842 | } |
4843 | ||
69888674 AD |
4844 | /** |
4845 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
4846 | * @adapter: board private structure | |
4847 | * | |
4848 | * If this function returns with an error, then it's possible one or | |
4849 | * more of the rings is populated (while the rest are not). It is the | |
4850 | * callers duty to clean those orphaned rings. | |
4851 | * | |
4852 | * Return 0 on success, negative on failure | |
4853 | **/ | |
4854 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
4855 | { | |
4856 | int i, err = 0; | |
4857 | ||
4858 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 4859 | err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]); |
69888674 AD |
4860 | if (!err) |
4861 | continue; | |
4862 | DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i); | |
4863 | break; | |
4864 | } | |
4865 | ||
4866 | return err; | |
4867 | } | |
4868 | ||
9a799d71 AK |
4869 | /** |
4870 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
4871 | * @adapter: board private structure | |
3a581073 | 4872 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4873 | * |
4874 | * Returns 0 on success, negative on failure | |
4875 | **/ | |
4876 | int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, | |
b4617240 | 4877 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
4878 | { |
4879 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 4880 | int size; |
9a799d71 | 4881 | |
3a581073 | 4882 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
1a6c14a2 JB |
4883 | rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node); |
4884 | if (!rx_ring->rx_buffer_info) | |
4885 | rx_ring->rx_buffer_info = vmalloc(size); | |
3a581073 | 4886 | if (!rx_ring->rx_buffer_info) { |
9a799d71 | 4887 | DPRINTK(PROBE, ERR, |
b4617240 | 4888 | "vmalloc allocation failed for the rx desc ring\n"); |
177db6ff | 4889 | goto alloc_failed; |
9a799d71 | 4890 | } |
3a581073 | 4891 | memset(rx_ring->rx_buffer_info, 0, size); |
9a799d71 | 4892 | |
9a799d71 | 4893 | /* Round up to nearest 4K */ |
3a581073 JB |
4894 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
4895 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 4896 | |
1b507730 NN |
4897 | rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size, |
4898 | &rx_ring->dma, GFP_KERNEL); | |
9a799d71 | 4899 | |
3a581073 | 4900 | if (!rx_ring->desc) { |
9a799d71 | 4901 | DPRINTK(PROBE, ERR, |
b4617240 | 4902 | "Memory allocation failed for the rx desc ring\n"); |
3a581073 | 4903 | vfree(rx_ring->rx_buffer_info); |
177db6ff | 4904 | goto alloc_failed; |
9a799d71 AK |
4905 | } |
4906 | ||
3a581073 JB |
4907 | rx_ring->next_to_clean = 0; |
4908 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
4909 | |
4910 | return 0; | |
177db6ff MC |
4911 | |
4912 | alloc_failed: | |
177db6ff | 4913 | return -ENOMEM; |
9a799d71 AK |
4914 | } |
4915 | ||
69888674 AD |
4916 | /** |
4917 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
4918 | * @adapter: board private structure | |
4919 | * | |
4920 | * If this function returns with an error, then it's possible one or | |
4921 | * more of the rings is populated (while the rest are not). It is the | |
4922 | * callers duty to clean those orphaned rings. | |
4923 | * | |
4924 | * Return 0 on success, negative on failure | |
4925 | **/ | |
4926 | ||
4927 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) | |
4928 | { | |
4929 | int i, err = 0; | |
4930 | ||
4931 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4a0b9ca0 | 4932 | err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); |
69888674 AD |
4933 | if (!err) |
4934 | continue; | |
4935 | DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i); | |
4936 | break; | |
4937 | } | |
4938 | ||
4939 | return err; | |
4940 | } | |
4941 | ||
9a799d71 AK |
4942 | /** |
4943 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
4944 | * @adapter: board private structure | |
4945 | * @tx_ring: Tx descriptor ring for a specific queue | |
4946 | * | |
4947 | * Free all transmit software resources | |
4948 | **/ | |
c431f97e JB |
4949 | void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter, |
4950 | struct ixgbe_ring *tx_ring) | |
9a799d71 AK |
4951 | { |
4952 | struct pci_dev *pdev = adapter->pdev; | |
4953 | ||
4954 | ixgbe_clean_tx_ring(adapter, tx_ring); | |
4955 | ||
4956 | vfree(tx_ring->tx_buffer_info); | |
4957 | tx_ring->tx_buffer_info = NULL; | |
4958 | ||
1b507730 NN |
4959 | dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, |
4960 | tx_ring->dma); | |
9a799d71 AK |
4961 | |
4962 | tx_ring->desc = NULL; | |
4963 | } | |
4964 | ||
4965 | /** | |
4966 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
4967 | * @adapter: board private structure | |
4968 | * | |
4969 | * Free all transmit software resources | |
4970 | **/ | |
4971 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
4972 | { | |
4973 | int i; | |
4974 | ||
4975 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 PW |
4976 | if (adapter->tx_ring[i]->desc) |
4977 | ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
4978 | } |
4979 | ||
4980 | /** | |
b4617240 | 4981 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
4982 | * @adapter: board private structure |
4983 | * @rx_ring: ring to clean the resources from | |
4984 | * | |
4985 | * Free all receive software resources | |
4986 | **/ | |
c431f97e JB |
4987 | void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter, |
4988 | struct ixgbe_ring *rx_ring) | |
9a799d71 AK |
4989 | { |
4990 | struct pci_dev *pdev = adapter->pdev; | |
4991 | ||
4992 | ixgbe_clean_rx_ring(adapter, rx_ring); | |
4993 | ||
4994 | vfree(rx_ring->rx_buffer_info); | |
4995 | rx_ring->rx_buffer_info = NULL; | |
4996 | ||
1b507730 NN |
4997 | dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, |
4998 | rx_ring->dma); | |
9a799d71 AK |
4999 | |
5000 | rx_ring->desc = NULL; | |
5001 | } | |
5002 | ||
5003 | /** | |
5004 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
5005 | * @adapter: board private structure | |
5006 | * | |
5007 | * Free all receive software resources | |
5008 | **/ | |
5009 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
5010 | { | |
5011 | int i; | |
5012 | ||
5013 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 PW |
5014 | if (adapter->rx_ring[i]->desc) |
5015 | ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]); | |
9a799d71 AK |
5016 | } |
5017 | ||
9a799d71 AK |
5018 | /** |
5019 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
5020 | * @netdev: network interface device structure | |
5021 | * @new_mtu: new value for maximum frame size | |
5022 | * | |
5023 | * Returns 0 on success, negative on failure | |
5024 | **/ | |
5025 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
5026 | { | |
5027 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5028 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
5029 | ||
42c783c5 JB |
5030 | /* MTU < 68 is an error and causes problems on some kernels */ |
5031 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
9a799d71 AK |
5032 | return -EINVAL; |
5033 | ||
021230d4 | 5034 | DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n", |
b4617240 | 5035 | netdev->mtu, new_mtu); |
021230d4 | 5036 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
5037 | netdev->mtu = new_mtu; |
5038 | ||
d4f80882 AV |
5039 | if (netif_running(netdev)) |
5040 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
5041 | |
5042 | return 0; | |
5043 | } | |
5044 | ||
5045 | /** | |
5046 | * ixgbe_open - Called when a network interface is made active | |
5047 | * @netdev: network interface device structure | |
5048 | * | |
5049 | * Returns 0 on success, negative value on failure | |
5050 | * | |
5051 | * The open entry point is called when a network interface is made | |
5052 | * active by the system (IFF_UP). At this point all resources needed | |
5053 | * for transmit and receive operations are allocated, the interrupt | |
5054 | * handler is registered with the OS, the watchdog timer is started, | |
5055 | * and the stack is notified that the interface is ready. | |
5056 | **/ | |
5057 | static int ixgbe_open(struct net_device *netdev) | |
5058 | { | |
5059 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5060 | int err; | |
4bebfaa5 AK |
5061 | |
5062 | /* disallow open during test */ | |
5063 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
5064 | return -EBUSY; | |
9a799d71 | 5065 | |
54386467 JB |
5066 | netif_carrier_off(netdev); |
5067 | ||
9a799d71 AK |
5068 | /* allocate transmit descriptors */ |
5069 | err = ixgbe_setup_all_tx_resources(adapter); | |
5070 | if (err) | |
5071 | goto err_setup_tx; | |
5072 | ||
9a799d71 AK |
5073 | /* allocate receive descriptors */ |
5074 | err = ixgbe_setup_all_rx_resources(adapter); | |
5075 | if (err) | |
5076 | goto err_setup_rx; | |
5077 | ||
5078 | ixgbe_configure(adapter); | |
5079 | ||
021230d4 | 5080 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
5081 | if (err) |
5082 | goto err_req_irq; | |
5083 | ||
9a799d71 AK |
5084 | err = ixgbe_up_complete(adapter); |
5085 | if (err) | |
5086 | goto err_up; | |
5087 | ||
d55b53ff JK |
5088 | netif_tx_start_all_queues(netdev); |
5089 | ||
9a799d71 AK |
5090 | return 0; |
5091 | ||
5092 | err_up: | |
5eba3699 | 5093 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5094 | ixgbe_free_irq(adapter); |
5095 | err_req_irq: | |
9a799d71 | 5096 | err_setup_rx: |
a20a1199 | 5097 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 5098 | err_setup_tx: |
a20a1199 | 5099 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
5100 | ixgbe_reset(adapter); |
5101 | ||
5102 | return err; | |
5103 | } | |
5104 | ||
5105 | /** | |
5106 | * ixgbe_close - Disables a network interface | |
5107 | * @netdev: network interface device structure | |
5108 | * | |
5109 | * Returns 0, this is not allowed to fail | |
5110 | * | |
5111 | * The close entry point is called when an interface is de-activated | |
5112 | * by the OS. The hardware is still under the drivers control, but | |
5113 | * needs to be disabled. A global MAC reset is issued to stop the | |
5114 | * hardware, and all transmit and receive resources are freed. | |
5115 | **/ | |
5116 | static int ixgbe_close(struct net_device *netdev) | |
5117 | { | |
5118 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
5119 | |
5120 | ixgbe_down(adapter); | |
5121 | ixgbe_free_irq(adapter); | |
5122 | ||
5123 | ixgbe_free_all_tx_resources(adapter); | |
5124 | ixgbe_free_all_rx_resources(adapter); | |
5125 | ||
5eba3699 | 5126 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5127 | |
5128 | return 0; | |
5129 | } | |
5130 | ||
b3c8b4ba AD |
5131 | #ifdef CONFIG_PM |
5132 | static int ixgbe_resume(struct pci_dev *pdev) | |
5133 | { | |
5134 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5135 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5136 | u32 err; | |
5137 | ||
5138 | pci_set_power_state(pdev, PCI_D0); | |
5139 | pci_restore_state(pdev); | |
656ab817 DS |
5140 | /* |
5141 | * pci_restore_state clears dev->state_saved so call | |
5142 | * pci_save_state to restore it. | |
5143 | */ | |
5144 | pci_save_state(pdev); | |
9ce77666 | 5145 | |
5146 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 5147 | if (err) { |
69888674 | 5148 | printk(KERN_ERR "ixgbe: Cannot enable PCI device from " |
b3c8b4ba AD |
5149 | "suspend\n"); |
5150 | return err; | |
5151 | } | |
5152 | pci_set_master(pdev); | |
5153 | ||
dd4d8ca6 | 5154 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
5155 | |
5156 | err = ixgbe_init_interrupt_scheme(adapter); | |
5157 | if (err) { | |
5158 | printk(KERN_ERR "ixgbe: Cannot initialize interrupts for " | |
5159 | "device\n"); | |
5160 | return err; | |
5161 | } | |
5162 | ||
b3c8b4ba AD |
5163 | ixgbe_reset(adapter); |
5164 | ||
495dce12 WJP |
5165 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
5166 | ||
b3c8b4ba AD |
5167 | if (netif_running(netdev)) { |
5168 | err = ixgbe_open(adapter->netdev); | |
5169 | if (err) | |
5170 | return err; | |
5171 | } | |
5172 | ||
5173 | netif_device_attach(netdev); | |
5174 | ||
5175 | return 0; | |
5176 | } | |
b3c8b4ba | 5177 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
5178 | |
5179 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba AD |
5180 | { |
5181 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5182 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
e8e26350 PW |
5183 | struct ixgbe_hw *hw = &adapter->hw; |
5184 | u32 ctrl, fctrl; | |
5185 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
5186 | #ifdef CONFIG_PM |
5187 | int retval = 0; | |
5188 | #endif | |
5189 | ||
5190 | netif_device_detach(netdev); | |
5191 | ||
5192 | if (netif_running(netdev)) { | |
5193 | ixgbe_down(adapter); | |
5194 | ixgbe_free_irq(adapter); | |
5195 | ixgbe_free_all_tx_resources(adapter); | |
5196 | ixgbe_free_all_rx_resources(adapter); | |
5197 | } | |
b3c8b4ba AD |
5198 | |
5199 | #ifdef CONFIG_PM | |
5200 | retval = pci_save_state(pdev); | |
5201 | if (retval) | |
5202 | return retval; | |
4df10466 | 5203 | |
b3c8b4ba | 5204 | #endif |
e8e26350 PW |
5205 | if (wufc) { |
5206 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 5207 | |
e8e26350 PW |
5208 | /* turn on all-multi mode if wake on multicast is enabled */ |
5209 | if (wufc & IXGBE_WUFC_MC) { | |
5210 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5211 | fctrl |= IXGBE_FCTRL_MPE; | |
5212 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
5213 | } | |
5214 | ||
5215 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
5216 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
5217 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
5218 | ||
5219 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
5220 | } else { | |
5221 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
5222 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
5223 | } | |
5224 | ||
dd4d8ca6 DS |
5225 | if (wufc && hw->mac.type == ixgbe_mac_82599EB) |
5226 | pci_wake_from_d3(pdev, true); | |
5227 | else | |
5228 | pci_wake_from_d3(pdev, false); | |
b3c8b4ba | 5229 | |
9d8d05ae RW |
5230 | *enable_wake = !!wufc; |
5231 | ||
fa378134 AG |
5232 | ixgbe_clear_interrupt_scheme(adapter); |
5233 | ||
b3c8b4ba AD |
5234 | ixgbe_release_hw_control(adapter); |
5235 | ||
5236 | pci_disable_device(pdev); | |
5237 | ||
9d8d05ae RW |
5238 | return 0; |
5239 | } | |
5240 | ||
5241 | #ifdef CONFIG_PM | |
5242 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
5243 | { | |
5244 | int retval; | |
5245 | bool wake; | |
5246 | ||
5247 | retval = __ixgbe_shutdown(pdev, &wake); | |
5248 | if (retval) | |
5249 | return retval; | |
5250 | ||
5251 | if (wake) { | |
5252 | pci_prepare_to_sleep(pdev); | |
5253 | } else { | |
5254 | pci_wake_from_d3(pdev, false); | |
5255 | pci_set_power_state(pdev, PCI_D3hot); | |
5256 | } | |
b3c8b4ba AD |
5257 | |
5258 | return 0; | |
5259 | } | |
9d8d05ae | 5260 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
5261 | |
5262 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
5263 | { | |
9d8d05ae RW |
5264 | bool wake; |
5265 | ||
5266 | __ixgbe_shutdown(pdev, &wake); | |
5267 | ||
5268 | if (system_state == SYSTEM_POWER_OFF) { | |
5269 | pci_wake_from_d3(pdev, wake); | |
5270 | pci_set_power_state(pdev, PCI_D3hot); | |
5271 | } | |
b3c8b4ba AD |
5272 | } |
5273 | ||
9a799d71 AK |
5274 | /** |
5275 | * ixgbe_update_stats - Update the board statistics counters. | |
5276 | * @adapter: board private structure | |
5277 | **/ | |
5278 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
5279 | { | |
2d86f139 | 5280 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 5281 | struct ixgbe_hw *hw = &adapter->hw; |
6f11eef7 AV |
5282 | u64 total_mpc = 0; |
5283 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
eb985f09 | 5284 | u64 non_eop_descs = 0, restart_queue = 0; |
9a799d71 | 5285 | |
d08935c2 DS |
5286 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5287 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5288 | return; | |
5289 | ||
94b982b2 | 5290 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 5291 | u64 rsc_count = 0; |
94b982b2 | 5292 | u64 rsc_flush = 0; |
d51019a4 PW |
5293 | for (i = 0; i < 16; i++) |
5294 | adapter->hw_rx_no_dma_resources += | |
5295 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
94b982b2 | 5296 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 PW |
5297 | rsc_count += adapter->rx_ring[i]->rsc_count; |
5298 | rsc_flush += adapter->rx_ring[i]->rsc_flush; | |
94b982b2 MC |
5299 | } |
5300 | adapter->rsc_total_count = rsc_count; | |
5301 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
5302 | } |
5303 | ||
7ca3bc58 JB |
5304 | /* gather some stats to the adapter struct that are per queue */ |
5305 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 5306 | restart_queue += adapter->tx_ring[i]->restart_queue; |
eb985f09 | 5307 | adapter->restart_queue = restart_queue; |
7ca3bc58 JB |
5308 | |
5309 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 5310 | non_eop_descs += adapter->rx_ring[i]->non_eop_descs; |
eb985f09 | 5311 | adapter->non_eop_descs = non_eop_descs; |
7ca3bc58 | 5312 | |
9a799d71 | 5313 | adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
6f11eef7 AV |
5314 | for (i = 0; i < 8; i++) { |
5315 | /* for packet buffers not used, the register should read 0 */ | |
5316 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
5317 | missed_rx += mpc; | |
5318 | adapter->stats.mpc[i] += mpc; | |
5319 | total_mpc += adapter->stats.mpc[i]; | |
e8e26350 PW |
5320 | if (hw->mac.type == ixgbe_mac_82598EB) |
5321 | adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
2f90b865 AD |
5322 | adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); |
5323 | adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
5324 | adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
5325 | adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
e8e26350 PW |
5326 | if (hw->mac.type == ixgbe_mac_82599EB) { |
5327 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
5328 | IXGBE_PXONRXCNT(i)); | |
5329 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
5330 | IXGBE_PXOFFRXCNT(i)); | |
5331 | adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
e8e26350 PW |
5332 | } else { |
5333 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
5334 | IXGBE_PXONRXC(i)); | |
5335 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
5336 | IXGBE_PXOFFRXC(i)); | |
5337 | } | |
2f90b865 AD |
5338 | adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw, |
5339 | IXGBE_PXONTXC(i)); | |
2f90b865 | 5340 | adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw, |
e8e26350 | 5341 | IXGBE_PXOFFTXC(i)); |
6f11eef7 AV |
5342 | } |
5343 | adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); | |
5344 | /* work around hardware counting issue */ | |
5345 | adapter->stats.gprc -= missed_rx; | |
5346 | ||
5347 | /* 82598 hardware only has a 32 bit counter in the high register */ | |
e8e26350 | 5348 | if (hw->mac.type == ixgbe_mac_82599EB) { |
aad71918 | 5349 | u64 tmp; |
e8e26350 | 5350 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
aad71918 BG |
5351 | tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */ |
5352 | adapter->stats.gorc += (tmp << 32); | |
e8e26350 | 5353 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
aad71918 BG |
5354 | tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */ |
5355 | adapter->stats.gotc += (tmp << 32); | |
e8e26350 PW |
5356 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
5357 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ | |
5358 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); | |
5359 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
c4cf55e5 PWJ |
5360 | adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
5361 | adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c YZ |
5362 | #ifdef IXGBE_FCOE |
5363 | adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); | |
5364 | adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
5365 | adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
5366 | adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
5367 | adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
5368 | adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
5369 | #endif /* IXGBE_FCOE */ | |
e8e26350 PW |
5370 | } else { |
5371 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
5372 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
5373 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); | |
5374 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
5375 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
5376 | } | |
9a799d71 AK |
5377 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
5378 | adapter->stats.bprc += bprc; | |
5379 | adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 PW |
5380 | if (hw->mac.type == ixgbe_mac_82598EB) |
5381 | adapter->stats.mprc -= bprc; | |
9a799d71 AK |
5382 | adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC); |
5383 | adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
5384 | adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
5385 | adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
5386 | adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
5387 | adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
5388 | adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
9a799d71 | 5389 | adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); |
6f11eef7 AV |
5390 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
5391 | adapter->stats.lxontxc += lxon; | |
5392 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
5393 | adapter->stats.lxofftxc += lxoff; | |
9a799d71 AK |
5394 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
5395 | adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
6f11eef7 AV |
5396 | adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); |
5397 | /* | |
5398 | * 82598 errata - tx of flow control packets is included in tx counters | |
5399 | */ | |
5400 | xon_off_tot = lxon + lxoff; | |
5401 | adapter->stats.gptc -= xon_off_tot; | |
5402 | adapter->stats.mptc -= xon_off_tot; | |
5403 | adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
9a799d71 AK |
5404 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
5405 | adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
5406 | adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
9a799d71 AK |
5407 | adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR); |
5408 | adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6f11eef7 | 5409 | adapter->stats.ptc64 -= xon_off_tot; |
9a799d71 AK |
5410 | adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); |
5411 | adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
5412 | adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
5413 | adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
5414 | adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
9a799d71 AK |
5415 | adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); |
5416 | ||
5417 | /* Fill out the OS statistics structure */ | |
2d86f139 | 5418 | netdev->stats.multicast = adapter->stats.mprc; |
9a799d71 AK |
5419 | |
5420 | /* Rx Errors */ | |
2d86f139 | 5421 | netdev->stats.rx_errors = adapter->stats.crcerrs + |
b4617240 | 5422 | adapter->stats.rlec; |
2d86f139 AK |
5423 | netdev->stats.rx_dropped = 0; |
5424 | netdev->stats.rx_length_errors = adapter->stats.rlec; | |
5425 | netdev->stats.rx_crc_errors = adapter->stats.crcerrs; | |
5426 | netdev->stats.rx_missed_errors = total_mpc; | |
9a799d71 AK |
5427 | } |
5428 | ||
5429 | /** | |
5430 | * ixgbe_watchdog - Timer Call-back | |
5431 | * @data: pointer to adapter cast into an unsigned long | |
5432 | **/ | |
5433 | static void ixgbe_watchdog(unsigned long data) | |
5434 | { | |
5435 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee | 5436 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
5437 | u64 eics = 0; |
5438 | int i; | |
cf8280ee | 5439 | |
fe49f04a AD |
5440 | /* |
5441 | * Do the watchdog outside of interrupt context due to the lovely | |
5442 | * delays that some of the newer hardware requires | |
5443 | */ | |
22d5a71b | 5444 | |
fe49f04a AD |
5445 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
5446 | goto watchdog_short_circuit; | |
22d5a71b | 5447 | |
fe49f04a AD |
5448 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
5449 | /* | |
5450 | * for legacy and MSI interrupts don't set any bits | |
5451 | * that are enabled for EIAM, because this operation | |
5452 | * would set *both* EIMS and EICS for any bit in EIAM | |
5453 | */ | |
5454 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
5455 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
5456 | goto watchdog_reschedule; | |
5457 | } | |
5458 | ||
5459 | /* get one bit for every active tx/rx interrupt vector */ | |
5460 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { | |
5461 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; | |
5462 | if (qv->rxr_count || qv->txr_count) | |
5463 | eics |= ((u64)1 << i); | |
cf8280ee | 5464 | } |
9a799d71 | 5465 | |
fe49f04a AD |
5466 | /* Cause software interrupt to ensure rx rings are cleaned */ |
5467 | ixgbe_irq_rearm_queues(adapter, eics); | |
5468 | ||
5469 | watchdog_reschedule: | |
5470 | /* Reset the timer */ | |
5471 | mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ)); | |
5472 | ||
5473 | watchdog_short_circuit: | |
cf8280ee JB |
5474 | schedule_work(&adapter->watchdog_task); |
5475 | } | |
5476 | ||
e8e26350 PW |
5477 | /** |
5478 | * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber | |
5479 | * @work: pointer to work_struct containing our data | |
5480 | **/ | |
5481 | static void ixgbe_multispeed_fiber_task(struct work_struct *work) | |
5482 | { | |
5483 | struct ixgbe_adapter *adapter = container_of(work, | |
5484 | struct ixgbe_adapter, | |
5485 | multispeed_fiber_task); | |
5486 | struct ixgbe_hw *hw = &adapter->hw; | |
5487 | u32 autoneg; | |
8620a103 | 5488 | bool negotiation; |
e8e26350 PW |
5489 | |
5490 | adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK; | |
a1f25324 MC |
5491 | autoneg = hw->phy.autoneg_advertised; |
5492 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
8620a103 | 5493 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); |
1097cd17 | 5494 | hw->mac.autotry_restart = false; |
8620a103 MC |
5495 | if (hw->mac.ops.setup_link) |
5496 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
e8e26350 PW |
5497 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
5498 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK; | |
5499 | } | |
5500 | ||
5501 | /** | |
5502 | * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module | |
5503 | * @work: pointer to work_struct containing our data | |
5504 | **/ | |
5505 | static void ixgbe_sfp_config_module_task(struct work_struct *work) | |
5506 | { | |
5507 | struct ixgbe_adapter *adapter = container_of(work, | |
5508 | struct ixgbe_adapter, | |
5509 | sfp_config_module_task); | |
5510 | struct ixgbe_hw *hw = &adapter->hw; | |
5511 | u32 err; | |
5512 | ||
5513 | adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK; | |
63d6e1d8 DS |
5514 | |
5515 | /* Time for electrical oscillations to settle down */ | |
5516 | msleep(100); | |
e8e26350 | 5517 | err = hw->phy.ops.identify_sfp(hw); |
63d6e1d8 | 5518 | |
e8e26350 | 5519 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { |
88d2b81f DS |
5520 | dev_err(&adapter->pdev->dev, "failed to initialize because " |
5521 | "an unsupported SFP+ module type was detected.\n" | |
5522 | "Reload the driver after installing a supported " | |
5523 | "module.\n"); | |
63d6e1d8 | 5524 | unregister_netdev(adapter->netdev); |
e8e26350 PW |
5525 | return; |
5526 | } | |
5527 | hw->mac.ops.setup_sfp(hw); | |
5528 | ||
8d1c3c07 | 5529 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) |
e8e26350 PW |
5530 | /* This will also work for DA Twinax connections */ |
5531 | schedule_work(&adapter->multispeed_fiber_task); | |
5532 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK; | |
5533 | } | |
5534 | ||
c4cf55e5 PWJ |
5535 | /** |
5536 | * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table | |
5537 | * @work: pointer to work_struct containing our data | |
5538 | **/ | |
5539 | static void ixgbe_fdir_reinit_task(struct work_struct *work) | |
5540 | { | |
5541 | struct ixgbe_adapter *adapter = container_of(work, | |
5542 | struct ixgbe_adapter, | |
5543 | fdir_reinit_task); | |
5544 | struct ixgbe_hw *hw = &adapter->hw; | |
5545 | int i; | |
5546 | ||
5547 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { | |
5548 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5549 | set_bit(__IXGBE_FDIR_INIT_DONE, | |
4a0b9ca0 | 5550 | &(adapter->tx_ring[i]->reinit_state)); |
c4cf55e5 PWJ |
5551 | } else { |
5552 | DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, " | |
d6dbee86 | 5553 | "ignored adding FDIR ATR filters\n"); |
c4cf55e5 PWJ |
5554 | } |
5555 | /* Done FDIR Re-initialization, enable transmits */ | |
5556 | netif_tx_start_all_queues(adapter->netdev); | |
5557 | } | |
5558 | ||
10eec955 JF |
5559 | static DEFINE_MUTEX(ixgbe_watchdog_lock); |
5560 | ||
cf8280ee | 5561 | /** |
69888674 AD |
5562 | * ixgbe_watchdog_task - worker thread to bring link up |
5563 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
5564 | **/ |
5565 | static void ixgbe_watchdog_task(struct work_struct *work) | |
5566 | { | |
5567 | struct ixgbe_adapter *adapter = container_of(work, | |
5568 | struct ixgbe_adapter, | |
5569 | watchdog_task); | |
5570 | struct net_device *netdev = adapter->netdev; | |
5571 | struct ixgbe_hw *hw = &adapter->hw; | |
10eec955 JF |
5572 | u32 link_speed; |
5573 | bool link_up; | |
bc59fcda NS |
5574 | int i; |
5575 | struct ixgbe_ring *tx_ring; | |
5576 | int some_tx_pending = 0; | |
cf8280ee | 5577 | |
10eec955 JF |
5578 | mutex_lock(&ixgbe_watchdog_lock); |
5579 | ||
5580 | link_up = adapter->link_up; | |
5581 | link_speed = adapter->link_speed; | |
cf8280ee JB |
5582 | |
5583 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
5584 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
264857b8 PWJ |
5585 | if (link_up) { |
5586 | #ifdef CONFIG_DCB | |
5587 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
5588 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) | |
620fa036 | 5589 | hw->mac.ops.fc_enable(hw, i); |
264857b8 | 5590 | } else { |
620fa036 | 5591 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
5592 | } |
5593 | #else | |
620fa036 | 5594 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
5595 | #endif |
5596 | } | |
5597 | ||
cf8280ee JB |
5598 | if (link_up || |
5599 | time_after(jiffies, (adapter->link_check_timeout + | |
5600 | IXGBE_TRY_LINK_TIMEOUT))) { | |
cf8280ee | 5601 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
264857b8 | 5602 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); |
cf8280ee JB |
5603 | } |
5604 | adapter->link_up = link_up; | |
5605 | adapter->link_speed = link_speed; | |
5606 | } | |
9a799d71 AK |
5607 | |
5608 | if (link_up) { | |
5609 | if (!netif_carrier_ok(netdev)) { | |
e8e26350 PW |
5610 | bool flow_rx, flow_tx; |
5611 | ||
5612 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
5613 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
5614 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
078788b6 PWJ |
5615 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); |
5616 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
e8e26350 PW |
5617 | } else { |
5618 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5619 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
078788b6 PWJ |
5620 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); |
5621 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
e8e26350 PW |
5622 | } |
5623 | ||
a46e534b JK |
5624 | printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, " |
5625 | "Flow Control: %s\n", | |
5626 | netdev->name, | |
5627 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
5628 | "10 Gbps" : | |
5629 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
5630 | "1 Gbps" : "unknown speed")), | |
e8e26350 PW |
5631 | ((flow_rx && flow_tx) ? "RX/TX" : |
5632 | (flow_rx ? "RX" : | |
5633 | (flow_tx ? "TX" : "None")))); | |
9a799d71 AK |
5634 | |
5635 | netif_carrier_on(netdev); | |
9a799d71 AK |
5636 | } else { |
5637 | /* Force detection of hung controller */ | |
5638 | adapter->detect_tx_hung = true; | |
5639 | } | |
5640 | } else { | |
cf8280ee JB |
5641 | adapter->link_up = false; |
5642 | adapter->link_speed = 0; | |
9a799d71 | 5643 | if (netif_carrier_ok(netdev)) { |
a46e534b JK |
5644 | printk(KERN_INFO "ixgbe: %s NIC Link is Down\n", |
5645 | netdev->name); | |
9a799d71 | 5646 | netif_carrier_off(netdev); |
9a799d71 AK |
5647 | } |
5648 | } | |
5649 | ||
bc59fcda NS |
5650 | if (!netif_carrier_ok(netdev)) { |
5651 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 5652 | tx_ring = adapter->tx_ring[i]; |
bc59fcda NS |
5653 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { |
5654 | some_tx_pending = 1; | |
5655 | break; | |
5656 | } | |
5657 | } | |
5658 | ||
5659 | if (some_tx_pending) { | |
5660 | /* We've lost link, so the controller stops DMA, | |
5661 | * but we've got queued Tx work that's never going | |
5662 | * to get done, so reset controller to flush Tx. | |
5663 | * (Do the reset outside of interrupt context). | |
5664 | */ | |
5665 | schedule_work(&adapter->reset_task); | |
5666 | } | |
5667 | } | |
5668 | ||
9a799d71 | 5669 | ixgbe_update_stats(adapter); |
10eec955 | 5670 | mutex_unlock(&ixgbe_watchdog_lock); |
9a799d71 AK |
5671 | } |
5672 | ||
9a799d71 | 5673 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
b4617240 PW |
5674 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
5675 | u32 tx_flags, u8 *hdr_len) | |
9a799d71 AK |
5676 | { |
5677 | struct ixgbe_adv_tx_context_desc *context_desc; | |
5678 | unsigned int i; | |
5679 | int err; | |
5680 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
5681 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
5682 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
5683 | |
5684 | if (skb_is_gso(skb)) { | |
5685 | if (skb_header_cloned(skb)) { | |
5686 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
5687 | if (err) | |
5688 | return err; | |
5689 | } | |
5690 | l4len = tcp_hdrlen(skb); | |
5691 | *hdr_len += l4len; | |
5692 | ||
8327d000 | 5693 | if (skb->protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
5694 | struct iphdr *iph = ip_hdr(skb); |
5695 | iph->tot_len = 0; | |
5696 | iph->check = 0; | |
5697 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
b4617240 PW |
5698 | iph->daddr, 0, |
5699 | IPPROTO_TCP, | |
5700 | 0); | |
8e1e8a47 | 5701 | } else if (skb_is_gso_v6(skb)) { |
9a799d71 AK |
5702 | ipv6_hdr(skb)->payload_len = 0; |
5703 | tcp_hdr(skb)->check = | |
5704 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
b4617240 PW |
5705 | &ipv6_hdr(skb)->daddr, |
5706 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
5707 | } |
5708 | ||
5709 | i = tx_ring->next_to_use; | |
5710 | ||
5711 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
5712 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
5713 | ||
5714 | /* VLAN MACLEN IPLEN */ | |
5715 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
5716 | vlan_macip_lens |= | |
5717 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
5718 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
b4617240 | 5719 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
5720 | *hdr_len += skb_network_offset(skb); |
5721 | vlan_macip_lens |= | |
5722 | (skb_transport_header(skb) - skb_network_header(skb)); | |
5723 | *hdr_len += | |
5724 | (skb_transport_header(skb) - skb_network_header(skb)); | |
5725 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
5726 | context_desc->seqnum_seed = 0; | |
5727 | ||
5728 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 5729 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
b4617240 | 5730 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 5731 | |
8327d000 | 5732 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
5733 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
5734 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
5735 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
5736 | ||
5737 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 5738 | mss_l4len_idx = |
9a799d71 AK |
5739 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
5740 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
5741 | /* use index 1 for TSO */ |
5742 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
5743 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
5744 | ||
5745 | tx_buffer_info->time_stamp = jiffies; | |
5746 | tx_buffer_info->next_to_watch = i; | |
5747 | ||
5748 | i++; | |
5749 | if (i == tx_ring->count) | |
5750 | i = 0; | |
5751 | tx_ring->next_to_use = i; | |
5752 | ||
5753 | return true; | |
5754 | } | |
5755 | return false; | |
5756 | } | |
5757 | ||
5758 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, | |
b4617240 PW |
5759 | struct ixgbe_ring *tx_ring, |
5760 | struct sk_buff *skb, u32 tx_flags) | |
9a799d71 AK |
5761 | { |
5762 | struct ixgbe_adv_tx_context_desc *context_desc; | |
5763 | unsigned int i; | |
5764 | struct ixgbe_tx_buffer *tx_buffer_info; | |
5765 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
5766 | ||
5767 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
5768 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
5769 | i = tx_ring->next_to_use; | |
5770 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
5771 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
5772 | ||
5773 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
5774 | vlan_macip_lens |= | |
5775 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
5776 | vlan_macip_lens |= (skb_network_offset(skb) << | |
b4617240 | 5777 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
5778 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
5779 | vlan_macip_lens |= (skb_transport_header(skb) - | |
b4617240 | 5780 | skb_network_header(skb)); |
9a799d71 AK |
5781 | |
5782 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
5783 | context_desc->seqnum_seed = 0; | |
5784 | ||
5785 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
b4617240 | 5786 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 AK |
5787 | |
5788 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
ca553980 GS |
5789 | __be16 protocol; |
5790 | ||
5791 | if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) { | |
5792 | const struct vlan_ethhdr *vhdr = | |
5793 | (const struct vlan_ethhdr *)skb->data; | |
5794 | ||
5795 | protocol = vhdr->h_vlan_encapsulated_proto; | |
5796 | } else { | |
5797 | protocol = skb->protocol; | |
5798 | } | |
5799 | ||
5800 | switch (protocol) { | |
09640e63 | 5801 | case cpu_to_be16(ETH_P_IP): |
9a799d71 | 5802 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
41825d71 AK |
5803 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
5804 | type_tucmd_mlhl |= | |
b4617240 | 5805 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
5806 | else if (ip_hdr(skb)->protocol == IPPROTO_SCTP) |
5807 | type_tucmd_mlhl |= | |
5808 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 5809 | break; |
09640e63 | 5810 | case cpu_to_be16(ETH_P_IPV6): |
41825d71 AK |
5811 | /* XXX what about other V6 headers?? */ |
5812 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
5813 | type_tucmd_mlhl |= | |
b4617240 | 5814 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
5815 | else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP) |
5816 | type_tucmd_mlhl |= | |
5817 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 5818 | break; |
41825d71 AK |
5819 | default: |
5820 | if (unlikely(net_ratelimit())) { | |
5821 | DPRINTK(PROBE, WARNING, | |
5822 | "partial checksum but proto=%x!\n", | |
5823 | skb->protocol); | |
5824 | } | |
5825 | break; | |
5826 | } | |
9a799d71 AK |
5827 | } |
5828 | ||
5829 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 5830 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
5831 | context_desc->mss_l4len_idx = 0; |
5832 | ||
5833 | tx_buffer_info->time_stamp = jiffies; | |
5834 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 5835 | |
9a799d71 AK |
5836 | i++; |
5837 | if (i == tx_ring->count) | |
5838 | i = 0; | |
5839 | tx_ring->next_to_use = i; | |
5840 | ||
5841 | return true; | |
5842 | } | |
9f8cdf4f | 5843 | |
9a799d71 AK |
5844 | return false; |
5845 | } | |
5846 | ||
5847 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
b4617240 | 5848 | struct ixgbe_ring *tx_ring, |
eacd73f7 YZ |
5849 | struct sk_buff *skb, u32 tx_flags, |
5850 | unsigned int first) | |
9a799d71 | 5851 | { |
e5a43549 | 5852 | struct pci_dev *pdev = adapter->pdev; |
9a799d71 | 5853 | struct ixgbe_tx_buffer *tx_buffer_info; |
eacd73f7 YZ |
5854 | unsigned int len; |
5855 | unsigned int total = skb->len; | |
9a799d71 AK |
5856 | unsigned int offset = 0, size, count = 0, i; |
5857 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
5858 | unsigned int f; | |
9a799d71 AK |
5859 | |
5860 | i = tx_ring->next_to_use; | |
5861 | ||
eacd73f7 YZ |
5862 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) |
5863 | /* excluding fcoe_crc_eof for FCoE */ | |
5864 | total -= sizeof(struct fcoe_crc_eof); | |
5865 | ||
5866 | len = min(skb_headlen(skb), total); | |
9a799d71 AK |
5867 | while (len) { |
5868 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
5869 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
5870 | ||
5871 | tx_buffer_info->length = size; | |
e5a43549 | 5872 | tx_buffer_info->mapped_as_page = false; |
1b507730 | 5873 | tx_buffer_info->dma = dma_map_single(&pdev->dev, |
e5a43549 | 5874 | skb->data + offset, |
1b507730 NN |
5875 | size, DMA_TO_DEVICE); |
5876 | if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma)) | |
e5a43549 | 5877 | goto dma_error; |
9a799d71 AK |
5878 | tx_buffer_info->time_stamp = jiffies; |
5879 | tx_buffer_info->next_to_watch = i; | |
5880 | ||
5881 | len -= size; | |
eacd73f7 | 5882 | total -= size; |
9a799d71 AK |
5883 | offset += size; |
5884 | count++; | |
44df32c5 AD |
5885 | |
5886 | if (len) { | |
5887 | i++; | |
5888 | if (i == tx_ring->count) | |
5889 | i = 0; | |
5890 | } | |
9a799d71 AK |
5891 | } |
5892 | ||
5893 | for (f = 0; f < nr_frags; f++) { | |
5894 | struct skb_frag_struct *frag; | |
5895 | ||
5896 | frag = &skb_shinfo(skb)->frags[f]; | |
eacd73f7 | 5897 | len = min((unsigned int)frag->size, total); |
e5a43549 | 5898 | offset = frag->page_offset; |
9a799d71 AK |
5899 | |
5900 | while (len) { | |
44df32c5 AD |
5901 | i++; |
5902 | if (i == tx_ring->count) | |
5903 | i = 0; | |
5904 | ||
9a799d71 AK |
5905 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
5906 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
5907 | ||
5908 | tx_buffer_info->length = size; | |
1b507730 | 5909 | tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev, |
e5a43549 AD |
5910 | frag->page, |
5911 | offset, size, | |
1b507730 | 5912 | DMA_TO_DEVICE); |
e5a43549 | 5913 | tx_buffer_info->mapped_as_page = true; |
1b507730 | 5914 | if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma)) |
e5a43549 | 5915 | goto dma_error; |
9a799d71 AK |
5916 | tx_buffer_info->time_stamp = jiffies; |
5917 | tx_buffer_info->next_to_watch = i; | |
5918 | ||
5919 | len -= size; | |
eacd73f7 | 5920 | total -= size; |
9a799d71 AK |
5921 | offset += size; |
5922 | count++; | |
9a799d71 | 5923 | } |
eacd73f7 YZ |
5924 | if (total == 0) |
5925 | break; | |
9a799d71 | 5926 | } |
44df32c5 | 5927 | |
9a799d71 AK |
5928 | tx_ring->tx_buffer_info[i].skb = skb; |
5929 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
5930 | ||
e5a43549 AD |
5931 | return count; |
5932 | ||
5933 | dma_error: | |
5934 | dev_err(&pdev->dev, "TX DMA map failed\n"); | |
5935 | ||
5936 | /* clear timestamp and dma mappings for failed tx_buffer_info map */ | |
5937 | tx_buffer_info->dma = 0; | |
5938 | tx_buffer_info->time_stamp = 0; | |
5939 | tx_buffer_info->next_to_watch = 0; | |
c1fa347f RK |
5940 | if (count) |
5941 | count--; | |
e5a43549 AD |
5942 | |
5943 | /* clear timestamp and dma mappings for remaining portion of packet */ | |
c1fa347f RK |
5944 | while (count--) { |
5945 | if (i==0) | |
e5a43549 | 5946 | i += tx_ring->count; |
c1fa347f | 5947 | i--; |
e5a43549 AD |
5948 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
5949 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
5950 | } | |
5951 | ||
e44d38e1 | 5952 | return 0; |
9a799d71 AK |
5953 | } |
5954 | ||
5955 | static void ixgbe_tx_queue(struct ixgbe_adapter *adapter, | |
b4617240 PW |
5956 | struct ixgbe_ring *tx_ring, |
5957 | int tx_flags, int count, u32 paylen, u8 hdr_len) | |
9a799d71 AK |
5958 | { |
5959 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
5960 | struct ixgbe_tx_buffer *tx_buffer_info; | |
5961 | u32 olinfo_status = 0, cmd_type_len = 0; | |
5962 | unsigned int i; | |
5963 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
5964 | ||
5965 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
5966 | ||
5967 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
5968 | ||
5969 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
5970 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
5971 | ||
5972 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
5973 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
5974 | ||
5975 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 5976 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 5977 | |
4eeae6fd PW |
5978 | /* use index 1 context for tso */ |
5979 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
5980 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
5981 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
b4617240 | 5982 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
5983 | |
5984 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
5985 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 5986 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 5987 | |
eacd73f7 YZ |
5988 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
5989 | olinfo_status |= IXGBE_ADVTXD_CC; | |
5990 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
5991 | if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
5992 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
5993 | } | |
5994 | ||
9a799d71 AK |
5995 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); |
5996 | ||
5997 | i = tx_ring->next_to_use; | |
5998 | while (count--) { | |
5999 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
6000 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); | |
6001 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); | |
6002 | tx_desc->read.cmd_type_len = | |
b4617240 | 6003 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 6004 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
6005 | i++; |
6006 | if (i == tx_ring->count) | |
6007 | i = 0; | |
6008 | } | |
6009 | ||
6010 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
6011 | ||
6012 | /* | |
6013 | * Force memory writes to complete before letting h/w | |
6014 | * know there are new descriptors to fetch. (Only | |
6015 | * applicable for weak-ordered memory model archs, | |
6016 | * such as IA-64). | |
6017 | */ | |
6018 | wmb(); | |
6019 | ||
6020 | tx_ring->next_to_use = i; | |
6021 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
6022 | } | |
6023 | ||
c4cf55e5 PWJ |
6024 | static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb, |
6025 | int queue, u32 tx_flags) | |
6026 | { | |
c4cf55e5 PWJ |
6027 | struct ixgbe_atr_input atr_input; |
6028 | struct tcphdr *th; | |
c4cf55e5 PWJ |
6029 | struct iphdr *iph = ip_hdr(skb); |
6030 | struct ethhdr *eth = (struct ethhdr *)skb->data; | |
6031 | u16 vlan_id, src_port, dst_port, flex_bytes; | |
6032 | u32 src_ipv4_addr, dst_ipv4_addr; | |
6033 | u8 l4type = 0; | |
6034 | ||
d3ead241 GG |
6035 | /* Right now, we support IPv4 only */ |
6036 | if (skb->protocol != htons(ETH_P_IP)) | |
6037 | return; | |
c4cf55e5 PWJ |
6038 | /* check if we're UDP or TCP */ |
6039 | if (iph->protocol == IPPROTO_TCP) { | |
6040 | th = tcp_hdr(skb); | |
6041 | src_port = th->source; | |
6042 | dst_port = th->dest; | |
6043 | l4type |= IXGBE_ATR_L4TYPE_TCP; | |
6044 | /* l4type IPv4 type is 0, no need to assign */ | |
c4cf55e5 PWJ |
6045 | } else { |
6046 | /* Unsupported L4 header, just bail here */ | |
6047 | return; | |
6048 | } | |
6049 | ||
6050 | memset(&atr_input, 0, sizeof(struct ixgbe_atr_input)); | |
6051 | ||
6052 | vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >> | |
6053 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
6054 | src_ipv4_addr = iph->saddr; | |
6055 | dst_ipv4_addr = iph->daddr; | |
6056 | flex_bytes = eth->h_proto; | |
6057 | ||
6058 | ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id); | |
6059 | ixgbe_atr_set_src_port_82599(&atr_input, dst_port); | |
6060 | ixgbe_atr_set_dst_port_82599(&atr_input, src_port); | |
6061 | ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes); | |
6062 | ixgbe_atr_set_l4type_82599(&atr_input, l4type); | |
6063 | /* src and dst are inverted, think how the receiver sees them */ | |
6064 | ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr); | |
6065 | ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr); | |
6066 | ||
6067 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
6068 | ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue); | |
6069 | } | |
6070 | ||
e092be60 | 6071 | static int __ixgbe_maybe_stop_tx(struct net_device *netdev, |
b4617240 | 6072 | struct ixgbe_ring *tx_ring, int size) |
e092be60 | 6073 | { |
30eba97a | 6074 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
6075 | /* Herbert's original patch had: |
6076 | * smp_mb__after_netif_stop_queue(); | |
6077 | * but since that doesn't exist yet, just open code it. */ | |
6078 | smp_mb(); | |
6079 | ||
6080 | /* We need to check again in a case another CPU has just | |
6081 | * made room available. */ | |
6082 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
6083 | return -EBUSY; | |
6084 | ||
6085 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
af72166f | 6086 | netif_start_subqueue(netdev, tx_ring->queue_index); |
7ca3bc58 | 6087 | ++tx_ring->restart_queue; |
e092be60 AV |
6088 | return 0; |
6089 | } | |
6090 | ||
6091 | static int ixgbe_maybe_stop_tx(struct net_device *netdev, | |
b4617240 | 6092 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
6093 | { |
6094 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
6095 | return 0; | |
6096 | return __ixgbe_maybe_stop_tx(netdev, tx_ring, size); | |
6097 | } | |
6098 | ||
09a3b1f8 SH |
6099 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
6100 | { | |
6101 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5f715823 | 6102 | int txq = smp_processor_id(); |
09a3b1f8 | 6103 | |
fdd3d631 KK |
6104 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
6105 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
6106 | txq -= dev->real_num_tx_queues; | |
5f715823 | 6107 | return txq; |
fdd3d631 | 6108 | } |
c4cf55e5 | 6109 | |
5f715823 YZ |
6110 | #ifdef IXGBE_FCOE |
6111 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
ca77cd59 RL |
6112 | ((skb->protocol == htons(ETH_P_FCOE)) || |
6113 | (skb->protocol == htons(ETH_P_FIP)))) { | |
5f715823 YZ |
6114 | txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1); |
6115 | txq += adapter->ring_feature[RING_F_FCOE].mask; | |
6116 | return txq; | |
6117 | } | |
6118 | #endif | |
2ea186ae JF |
6119 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
6120 | if (skb->priority == TC_PRIO_CONTROL) | |
6121 | txq = adapter->ring_feature[RING_F_DCB].indices-1; | |
6122 | else | |
6123 | txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) | |
6124 | >> 13; | |
6125 | return txq; | |
6126 | } | |
09a3b1f8 SH |
6127 | |
6128 | return skb_tx_hash(dev, skb); | |
6129 | } | |
6130 | ||
3b29a56d SH |
6131 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, |
6132 | struct net_device *netdev) | |
9a799d71 AK |
6133 | { |
6134 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6135 | struct ixgbe_ring *tx_ring; | |
60d51134 | 6136 | struct netdev_queue *txq; |
9a799d71 AK |
6137 | unsigned int first; |
6138 | unsigned int tx_flags = 0; | |
30eba97a | 6139 | u8 hdr_len = 0; |
5f715823 | 6140 | int tso; |
9a799d71 AK |
6141 | int count = 0; |
6142 | unsigned int f; | |
9f8cdf4f | 6143 | |
9f8cdf4f JB |
6144 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { |
6145 | tx_flags |= vlan_tx_tag_get(skb); | |
2f90b865 AD |
6146 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
6147 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
5f715823 | 6148 | tx_flags |= ((skb->queue_mapping & 0x7) << 13); |
2f90b865 AD |
6149 | } |
6150 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
6151 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
33c66bd1 JF |
6152 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED && |
6153 | skb->priority != TC_PRIO_CONTROL) { | |
2ea186ae JF |
6154 | tx_flags |= ((skb->queue_mapping & 0x7) << 13); |
6155 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
6156 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 6157 | } |
eacd73f7 | 6158 | |
4a0b9ca0 | 6159 | tx_ring = adapter->tx_ring[skb->queue_mapping]; |
60127865 | 6160 | |
09ad1cc0 | 6161 | #ifdef IXGBE_FCOE |
ca77cd59 | 6162 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { |
61a0f421 | 6163 | #ifdef CONFIG_IXGBE_DCB |
ca77cd59 RL |
6164 | /* for FCoE with DCB, we force the priority to what |
6165 | * was specified by the switch */ | |
6166 | if ((skb->protocol == htons(ETH_P_FCOE)) || | |
6167 | (skb->protocol == htons(ETH_P_FIP))) { | |
6168 | tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK | |
6169 | << IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6170 | tx_flags |= ((adapter->fcoe.up << 13) | |
6171 | << IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6172 | } | |
09ad1cc0 | 6173 | #endif |
ca77cd59 RL |
6174 | /* flag for FCoE offloads */ |
6175 | if (skb->protocol == htons(ETH_P_FCOE)) | |
6176 | tx_flags |= IXGBE_TX_FLAGS_FCOE; | |
09ad1cc0 | 6177 | } |
ca77cd59 RL |
6178 | #endif |
6179 | ||
eacd73f7 | 6180 | /* four things can cause us to need a context descriptor */ |
9f8cdf4f JB |
6181 | if (skb_is_gso(skb) || |
6182 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
eacd73f7 YZ |
6183 | (tx_flags & IXGBE_TX_FLAGS_VLAN) || |
6184 | (tx_flags & IXGBE_TX_FLAGS_FCOE)) | |
9a799d71 AK |
6185 | count++; |
6186 | ||
9f8cdf4f JB |
6187 | count += TXD_USE_COUNT(skb_headlen(skb)); |
6188 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
6189 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
6190 | ||
e092be60 | 6191 | if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) { |
9a799d71 | 6192 | adapter->tx_busy++; |
9a799d71 AK |
6193 | return NETDEV_TX_BUSY; |
6194 | } | |
9a799d71 | 6195 | |
9a799d71 | 6196 | first = tx_ring->next_to_use; |
eacd73f7 YZ |
6197 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
6198 | #ifdef IXGBE_FCOE | |
6199 | /* setup tx offload for FCoE */ | |
6200 | tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
6201 | if (tso < 0) { | |
6202 | dev_kfree_skb_any(skb); | |
6203 | return NETDEV_TX_OK; | |
6204 | } | |
6205 | if (tso) | |
6206 | tx_flags |= IXGBE_TX_FLAGS_FSO; | |
6207 | #endif /* IXGBE_FCOE */ | |
6208 | } else { | |
6209 | if (skb->protocol == htons(ETH_P_IP)) | |
6210 | tx_flags |= IXGBE_TX_FLAGS_IPV4; | |
6211 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
6212 | if (tso < 0) { | |
6213 | dev_kfree_skb_any(skb); | |
6214 | return NETDEV_TX_OK; | |
6215 | } | |
9a799d71 | 6216 | |
eacd73f7 YZ |
6217 | if (tso) |
6218 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
6219 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) && | |
6220 | (skb->ip_summed == CHECKSUM_PARTIAL)) | |
6221 | tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
6222 | } | |
9a799d71 | 6223 | |
eacd73f7 | 6224 | count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first); |
44df32c5 | 6225 | if (count) { |
c4cf55e5 PWJ |
6226 | /* add the ATR filter if ATR is on */ |
6227 | if (tx_ring->atr_sample_rate) { | |
6228 | ++tx_ring->atr_count; | |
6229 | if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) && | |
6230 | test_bit(__IXGBE_FDIR_INIT_DONE, | |
6231 | &tx_ring->reinit_state)) { | |
6232 | ixgbe_atr(adapter, skb, tx_ring->queue_index, | |
6233 | tx_flags); | |
6234 | tx_ring->atr_count = 0; | |
6235 | } | |
6236 | } | |
60d51134 ED |
6237 | txq = netdev_get_tx_queue(netdev, tx_ring->queue_index); |
6238 | txq->tx_bytes += skb->len; | |
6239 | txq->tx_packets++; | |
44df32c5 AD |
6240 | ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len, |
6241 | hdr_len); | |
44df32c5 | 6242 | ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED); |
9a799d71 | 6243 | |
44df32c5 AD |
6244 | } else { |
6245 | dev_kfree_skb_any(skb); | |
6246 | tx_ring->tx_buffer_info[first].time_stamp = 0; | |
6247 | tx_ring->next_to_use = first; | |
6248 | } | |
9a799d71 AK |
6249 | |
6250 | return NETDEV_TX_OK; | |
6251 | } | |
6252 | ||
9a799d71 AK |
6253 | /** |
6254 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
6255 | * @netdev: network interface device structure | |
6256 | * @p: pointer to an address structure | |
6257 | * | |
6258 | * Returns 0 on success, negative on failure | |
6259 | **/ | |
6260 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
6261 | { | |
6262 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 6263 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
6264 | struct sockaddr *addr = p; |
6265 | ||
6266 | if (!is_valid_ether_addr(addr->sa_data)) | |
6267 | return -EADDRNOTAVAIL; | |
6268 | ||
6269 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 6270 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 6271 | |
1cdd1ec8 GR |
6272 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
6273 | IXGBE_RAH_AV); | |
9a799d71 AK |
6274 | |
6275 | return 0; | |
6276 | } | |
6277 | ||
6b73e10d BH |
6278 | static int |
6279 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
6280 | { | |
6281 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6282 | struct ixgbe_hw *hw = &adapter->hw; | |
6283 | u16 value; | |
6284 | int rc; | |
6285 | ||
6286 | if (prtad != hw->phy.mdio.prtad) | |
6287 | return -EINVAL; | |
6288 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
6289 | if (!rc) | |
6290 | rc = value; | |
6291 | return rc; | |
6292 | } | |
6293 | ||
6294 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
6295 | u16 addr, u16 value) | |
6296 | { | |
6297 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6298 | struct ixgbe_hw *hw = &adapter->hw; | |
6299 | ||
6300 | if (prtad != hw->phy.mdio.prtad) | |
6301 | return -EINVAL; | |
6302 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
6303 | } | |
6304 | ||
6305 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
6306 | { | |
6307 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6308 | ||
6309 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
6310 | } | |
6311 | ||
0365e6e4 PW |
6312 | /** |
6313 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 6314 | * netdev->dev_addrs |
0365e6e4 PW |
6315 | * @netdev: network interface device structure |
6316 | * | |
6317 | * Returns non-zero on failure | |
6318 | **/ | |
6319 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
6320 | { | |
6321 | int err = 0; | |
6322 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6323 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6324 | ||
6325 | if (is_valid_ether_addr(mac->san_addr)) { | |
6326 | rtnl_lock(); | |
6327 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6328 | rtnl_unlock(); | |
6329 | } | |
6330 | return err; | |
6331 | } | |
6332 | ||
6333 | /** | |
6334 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 6335 | * netdev->dev_addrs |
0365e6e4 PW |
6336 | * @netdev: network interface device structure |
6337 | * | |
6338 | * Returns non-zero on failure | |
6339 | **/ | |
6340 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
6341 | { | |
6342 | int err = 0; | |
6343 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6344 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6345 | ||
6346 | if (is_valid_ether_addr(mac->san_addr)) { | |
6347 | rtnl_lock(); | |
6348 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6349 | rtnl_unlock(); | |
6350 | } | |
6351 | return err; | |
6352 | } | |
6353 | ||
9a799d71 AK |
6354 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6355 | /* | |
6356 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
6357 | * without having to re-enable interrupts. It's not called while | |
6358 | * the interrupt routine is executing. | |
6359 | */ | |
6360 | static void ixgbe_netpoll(struct net_device *netdev) | |
6361 | { | |
6362 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 6363 | int i; |
9a799d71 | 6364 | |
1a647bd2 AD |
6365 | /* if interface is down do nothing */ |
6366 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
6367 | return; | |
6368 | ||
9a799d71 | 6369 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 PWJ |
6370 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
6371 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
6372 | for (i = 0; i < num_q_vectors; i++) { | |
6373 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
6374 | ixgbe_msix_clean_many(0, q_vector); | |
6375 | } | |
6376 | } else { | |
6377 | ixgbe_intr(adapter->pdev->irq, netdev); | |
6378 | } | |
9a799d71 | 6379 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 AK |
6380 | } |
6381 | #endif | |
6382 | ||
0edc3527 SH |
6383 | static const struct net_device_ops ixgbe_netdev_ops = { |
6384 | .ndo_open = ixgbe_open, | |
6385 | .ndo_stop = ixgbe_close, | |
00829823 | 6386 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 6387 | .ndo_select_queue = ixgbe_select_queue, |
e90d400c | 6388 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
6389 | .ndo_set_multicast_list = ixgbe_set_rx_mode, |
6390 | .ndo_validate_addr = eth_validate_addr, | |
6391 | .ndo_set_mac_address = ixgbe_set_mac, | |
6392 | .ndo_change_mtu = ixgbe_change_mtu, | |
6393 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
6394 | .ndo_vlan_rx_register = ixgbe_vlan_rx_register, | |
6395 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, | |
6396 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 6397 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
6398 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
6399 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
6400 | .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw, | |
6401 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, | |
0edc3527 SH |
6402 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6403 | .ndo_poll_controller = ixgbe_netpoll, | |
6404 | #endif | |
332d4a7d YZ |
6405 | #ifdef IXGBE_FCOE |
6406 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
6407 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, | |
8450ff8c YZ |
6408 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
6409 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 6410 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
332d4a7d | 6411 | #endif /* IXGBE_FCOE */ |
0edc3527 SH |
6412 | }; |
6413 | ||
1cdd1ec8 GR |
6414 | static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter, |
6415 | const struct ixgbe_info *ii) | |
6416 | { | |
6417 | #ifdef CONFIG_PCI_IOV | |
6418 | struct ixgbe_hw *hw = &adapter->hw; | |
6419 | int err; | |
6420 | ||
6421 | if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs) | |
6422 | return; | |
6423 | ||
6424 | /* The 82599 supports up to 64 VFs per physical function | |
6425 | * but this implementation limits allocation to 63 so that | |
6426 | * basic networking resources are still available to the | |
6427 | * physical function | |
6428 | */ | |
6429 | adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs; | |
6430 | adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED; | |
6431 | err = pci_enable_sriov(adapter->pdev, adapter->num_vfs); | |
6432 | if (err) { | |
6433 | DPRINTK(PROBE, ERR, | |
6434 | "Failed to enable PCI sriov: %d\n", err); | |
6435 | goto err_novfs; | |
6436 | } | |
6437 | /* If call to enable VFs succeeded then allocate memory | |
6438 | * for per VF control structures. | |
6439 | */ | |
6440 | adapter->vfinfo = | |
6441 | kcalloc(adapter->num_vfs, | |
6442 | sizeof(struct vf_data_storage), GFP_KERNEL); | |
6443 | if (adapter->vfinfo) { | |
6444 | /* Now that we're sure SR-IOV is enabled | |
6445 | * and memory allocated set up the mailbox parameters | |
6446 | */ | |
6447 | ixgbe_init_mbx_params_pf(hw); | |
6448 | memcpy(&hw->mbx.ops, ii->mbx_ops, | |
6449 | sizeof(hw->mbx.ops)); | |
6450 | ||
6451 | /* Disable RSC when in SR-IOV mode */ | |
6452 | adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE | | |
6453 | IXGBE_FLAG2_RSC_ENABLED); | |
6454 | return; | |
6455 | } | |
6456 | ||
6457 | /* Oh oh */ | |
6458 | DPRINTK(PROBE, ERR, | |
6459 | "Unable to allocate memory for VF " | |
6460 | "Data Storage - SRIOV disabled\n"); | |
6461 | pci_disable_sriov(adapter->pdev); | |
6462 | ||
6463 | err_novfs: | |
6464 | adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; | |
6465 | adapter->num_vfs = 0; | |
6466 | #endif /* CONFIG_PCI_IOV */ | |
6467 | } | |
6468 | ||
9a799d71 AK |
6469 | /** |
6470 | * ixgbe_probe - Device Initialization Routine | |
6471 | * @pdev: PCI device information struct | |
6472 | * @ent: entry in ixgbe_pci_tbl | |
6473 | * | |
6474 | * Returns 0 on success, negative on failure | |
6475 | * | |
6476 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
6477 | * The OS initialization, configuring of the adapter private structure, | |
6478 | * and a hardware reset occur. | |
6479 | **/ | |
6480 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
b4617240 | 6481 | const struct pci_device_id *ent) |
9a799d71 AK |
6482 | { |
6483 | struct net_device *netdev; | |
6484 | struct ixgbe_adapter *adapter = NULL; | |
6485 | struct ixgbe_hw *hw; | |
6486 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
6487 | static int cards_found; |
6488 | int i, err, pci_using_dac; | |
c85a2618 | 6489 | unsigned int indices = num_possible_cpus(); |
eacd73f7 YZ |
6490 | #ifdef IXGBE_FCOE |
6491 | u16 device_caps; | |
6492 | #endif | |
c44ade9e | 6493 | u32 part_num, eec; |
9a799d71 | 6494 | |
9ce77666 | 6495 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
6496 | if (err) |
6497 | return err; | |
6498 | ||
1b507730 NN |
6499 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && |
6500 | !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
6501 | pci_using_dac = 1; |
6502 | } else { | |
1b507730 | 6503 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 6504 | if (err) { |
1b507730 NN |
6505 | err = dma_set_coherent_mask(&pdev->dev, |
6506 | DMA_BIT_MASK(32)); | |
9a799d71 | 6507 | if (err) { |
b4617240 PW |
6508 | dev_err(&pdev->dev, "No usable DMA " |
6509 | "configuration, aborting\n"); | |
9a799d71 AK |
6510 | goto err_dma; |
6511 | } | |
6512 | } | |
6513 | pci_using_dac = 0; | |
6514 | } | |
6515 | ||
9ce77666 | 6516 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
6517 | IORESOURCE_MEM), ixgbe_driver_name); | |
9a799d71 | 6518 | if (err) { |
9ce77666 | 6519 | dev_err(&pdev->dev, |
6520 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
6521 | goto err_pci_reg; |
6522 | } | |
6523 | ||
19d5afd4 | 6524 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 6525 | |
9a799d71 | 6526 | pci_set_master(pdev); |
fb3b27bc | 6527 | pci_save_state(pdev); |
9a799d71 | 6528 | |
c85a2618 JF |
6529 | if (ii->mac == ixgbe_mac_82598EB) |
6530 | indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); | |
6531 | else | |
6532 | indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); | |
6533 | ||
6534 | indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES); | |
6535 | #ifdef IXGBE_FCOE | |
6536 | indices += min_t(unsigned int, num_possible_cpus(), | |
6537 | IXGBE_MAX_FCOE_INDICES); | |
6538 | #endif | |
c85a2618 | 6539 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
6540 | if (!netdev) { |
6541 | err = -ENOMEM; | |
6542 | goto err_alloc_etherdev; | |
6543 | } | |
6544 | ||
9a799d71 AK |
6545 | SET_NETDEV_DEV(netdev, &pdev->dev); |
6546 | ||
6547 | pci_set_drvdata(pdev, netdev); | |
6548 | adapter = netdev_priv(netdev); | |
6549 | ||
6550 | adapter->netdev = netdev; | |
6551 | adapter->pdev = pdev; | |
6552 | hw = &adapter->hw; | |
6553 | hw->back = adapter; | |
6554 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
6555 | ||
05857980 JK |
6556 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
6557 | pci_resource_len(pdev, 0)); | |
9a799d71 AK |
6558 | if (!hw->hw_addr) { |
6559 | err = -EIO; | |
6560 | goto err_ioremap; | |
6561 | } | |
6562 | ||
6563 | for (i = 1; i <= 5; i++) { | |
6564 | if (pci_resource_len(pdev, i) == 0) | |
6565 | continue; | |
6566 | } | |
6567 | ||
0edc3527 | 6568 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 6569 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 6570 | netdev->watchdog_timeo = 5 * HZ; |
9a799d71 AK |
6571 | strcpy(netdev->name, pci_name(pdev)); |
6572 | ||
9a799d71 AK |
6573 | adapter->bd_number = cards_found; |
6574 | ||
9a799d71 AK |
6575 | /* Setup hw api */ |
6576 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 6577 | hw->mac.type = ii->mac; |
9a799d71 | 6578 | |
c44ade9e JB |
6579 | /* EEPROM */ |
6580 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
6581 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
6582 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
6583 | if (!(eec & (1 << 8))) | |
6584 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
6585 | ||
6586 | /* PHY */ | |
6587 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 6588 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
6589 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
6590 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
6591 | hw->phy.mdio.mmds = 0; | |
6592 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
6593 | hw->phy.mdio.dev = netdev; | |
6594 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
6595 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 DS |
6596 | |
6597 | /* set up this timer and work struct before calling get_invariants | |
6598 | * which might start the timer | |
6599 | */ | |
6600 | init_timer(&adapter->sfp_timer); | |
6601 | adapter->sfp_timer.function = &ixgbe_sfp_timer; | |
6602 | adapter->sfp_timer.data = (unsigned long) adapter; | |
6603 | ||
6604 | INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); | |
c44ade9e | 6605 | |
e8e26350 PW |
6606 | /* multispeed fiber has its own tasklet, called from GPI SDP1 context */ |
6607 | INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task); | |
6608 | ||
6609 | /* a new SFP+ module arrival, called from GPI SDP2 context */ | |
6610 | INIT_WORK(&adapter->sfp_config_module_task, | |
6611 | ixgbe_sfp_config_module_task); | |
6612 | ||
8ca783ab | 6613 | ii->get_invariants(hw); |
9a799d71 AK |
6614 | |
6615 | /* setup the private structure */ | |
6616 | err = ixgbe_sw_init(adapter); | |
6617 | if (err) | |
6618 | goto err_sw_init; | |
6619 | ||
e86bff0e DS |
6620 | /* Make it possible the adapter to be woken up via WOL */ |
6621 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
6622 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); | |
6623 | ||
bf069c97 DS |
6624 | /* |
6625 | * If there is a fan on this device and it has failed log the | |
6626 | * failure. | |
6627 | */ | |
6628 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
6629 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
6630 | if (esdp & IXGBE_ESDP_SDP1) | |
6631 | DPRINTK(PROBE, CRIT, | |
6632 | "Fan has stopped, replace the adapter\n"); | |
6633 | } | |
6634 | ||
c44ade9e | 6635 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 6636 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 6637 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 6638 | hw->phy.reset_if_overtemp = false; |
8ca783ab DS |
6639 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
6640 | hw->mac.type == ixgbe_mac_82598EB) { | |
6641 | /* | |
6642 | * Start a kernel thread to watch for a module to arrive. | |
6643 | * Only do this for 82598, since 82599 will generate | |
6644 | * interrupts on module arrival. | |
6645 | */ | |
6646 | set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
6647 | mod_timer(&adapter->sfp_timer, | |
6648 | round_jiffies(jiffies + (2 * HZ))); | |
6649 | err = 0; | |
6650 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
88d2b81f DS |
6651 | dev_err(&adapter->pdev->dev, "failed to initialize because " |
6652 | "an unsupported SFP+ module type was detected.\n" | |
6653 | "Reload the driver after installing a supported " | |
6654 | "module.\n"); | |
04f165ef PW |
6655 | goto err_sw_init; |
6656 | } else if (err) { | |
c44ade9e JB |
6657 | dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err); |
6658 | goto err_sw_init; | |
6659 | } | |
6660 | ||
1cdd1ec8 GR |
6661 | ixgbe_probe_vf(adapter, ii); |
6662 | ||
9a799d71 | 6663 | netdev->features = NETIF_F_SG | |
b4617240 PW |
6664 | NETIF_F_IP_CSUM | |
6665 | NETIF_F_HW_VLAN_TX | | |
6666 | NETIF_F_HW_VLAN_RX | | |
6667 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 6668 | |
e9990a9c | 6669 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 6670 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 6671 | netdev->features |= NETIF_F_TSO6; |
78b6f4ce | 6672 | netdev->features |= NETIF_F_GRO; |
ad31c402 | 6673 | |
45a5ead0 JB |
6674 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
6675 | netdev->features |= NETIF_F_SCTP_CSUM; | |
6676 | ||
ad31c402 JK |
6677 | netdev->vlan_features |= NETIF_F_TSO; |
6678 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 6679 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 6680 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
6681 | netdev->vlan_features |= NETIF_F_SG; |
6682 | ||
1cdd1ec8 GR |
6683 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
6684 | adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED | | |
6685 | IXGBE_FLAG_DCB_ENABLED); | |
2f90b865 AD |
6686 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
6687 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
6688 | ||
7a6b6f51 | 6689 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
6690 | netdev->dcbnl_ops = &dcbnl_ops; |
6691 | #endif | |
6692 | ||
eacd73f7 | 6693 | #ifdef IXGBE_FCOE |
0d551589 | 6694 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
6695 | if (hw->mac.ops.get_device_caps) { |
6696 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
6697 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
6698 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 YZ |
6699 | } |
6700 | } | |
6701 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
6702 | if (pci_using_dac) |
6703 | netdev->features |= NETIF_F_HIGHDMA; | |
6704 | ||
0c19d6af | 6705 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
6706 | netdev->features |= NETIF_F_LRO; |
6707 | ||
9a799d71 | 6708 | /* make sure the EEPROM is good */ |
c44ade9e | 6709 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
9a799d71 AK |
6710 | dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); |
6711 | err = -EIO; | |
6712 | goto err_eeprom; | |
6713 | } | |
6714 | ||
6715 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
6716 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
6717 | ||
c44ade9e JB |
6718 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
6719 | dev_err(&pdev->dev, "invalid MAC address\n"); | |
9a799d71 AK |
6720 | err = -EIO; |
6721 | goto err_eeprom; | |
6722 | } | |
6723 | ||
61fac744 PW |
6724 | /* power down the optics */ |
6725 | if (hw->phy.multispeed_fiber) | |
6726 | hw->mac.ops.disable_tx_laser(hw); | |
6727 | ||
9a799d71 AK |
6728 | init_timer(&adapter->watchdog_timer); |
6729 | adapter->watchdog_timer.function = &ixgbe_watchdog; | |
6730 | adapter->watchdog_timer.data = (unsigned long)adapter; | |
6731 | ||
6732 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 6733 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 6734 | |
021230d4 AV |
6735 | err = ixgbe_init_interrupt_scheme(adapter); |
6736 | if (err) | |
6737 | goto err_sw_init; | |
9a799d71 | 6738 | |
e8e26350 PW |
6739 | switch (pdev->device) { |
6740 | case IXGBE_DEV_ID_82599_KX4: | |
495dce12 WJP |
6741 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | |
6742 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); | |
e8e26350 PW |
6743 | break; |
6744 | default: | |
6745 | adapter->wol = 0; | |
6746 | break; | |
6747 | } | |
e8e26350 PW |
6748 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
6749 | ||
04f165ef PW |
6750 | /* pick up the PCI bus settings for reporting later */ |
6751 | hw->mac.ops.get_bus_info(hw); | |
6752 | ||
9a799d71 | 6753 | /* print bus type/speed/width info */ |
7c510e4b | 6754 | dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n", |
e8e26350 PW |
6755 | ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s": |
6756 | (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"), | |
6757 | ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" : | |
6758 | (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" : | |
6759 | (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" : | |
b4617240 | 6760 | "Unknown"), |
7c510e4b | 6761 | netdev->dev_addr); |
c44ade9e | 6762 | ixgbe_read_pba_num_generic(hw, &part_num); |
e8e26350 PW |
6763 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
6764 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n", | |
6765 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, | |
6766 | (part_num >> 8), (part_num & 0xff)); | |
6767 | else | |
6768 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", | |
6769 | hw->mac.type, hw->phy.type, | |
6770 | (part_num >> 8), (part_num & 0xff)); | |
9a799d71 | 6771 | |
e8e26350 | 6772 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
0c254d86 | 6773 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for " |
b4617240 PW |
6774 | "this card is not sufficient for optimal " |
6775 | "performance.\n"); | |
0c254d86 | 6776 | dev_warn(&pdev->dev, "For optimal performance a x8 " |
b4617240 | 6777 | "PCI-Express slot is required.\n"); |
0c254d86 AK |
6778 | } |
6779 | ||
34b0368c PWJ |
6780 | /* save off EEPROM version number */ |
6781 | hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version); | |
6782 | ||
9a799d71 | 6783 | /* reset the hardware with the new settings */ |
794caeb2 | 6784 | err = hw->mac.ops.start_hw(hw); |
c44ade9e | 6785 | |
794caeb2 PWJ |
6786 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
6787 | /* We are running on a pre-production device, log a warning */ | |
6788 | dev_warn(&pdev->dev, "This device is a pre-production " | |
6789 | "adapter/LOM. Please be aware there may be issues " | |
6790 | "associated with your hardware. If you are " | |
6791 | "experiencing problems please contact your Intel or " | |
6792 | "hardware representative who provided you with this " | |
6793 | "hardware.\n"); | |
6794 | } | |
9a799d71 AK |
6795 | strcpy(netdev->name, "eth%d"); |
6796 | err = register_netdev(netdev); | |
6797 | if (err) | |
6798 | goto err_register; | |
6799 | ||
54386467 JB |
6800 | /* carrier off reporting is important to ethtool even BEFORE open */ |
6801 | netif_carrier_off(netdev); | |
6802 | ||
c4cf55e5 PWJ |
6803 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
6804 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
6805 | INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task); | |
6806 | ||
119fc60a MC |
6807 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
6808 | INIT_WORK(&adapter->check_overtemp_task, ixgbe_check_overtemp_task); | |
5dd2d332 | 6809 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 6810 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 6811 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
6812 | ixgbe_setup_dca(adapter); |
6813 | } | |
6814 | #endif | |
1cdd1ec8 GR |
6815 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
6816 | DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n", | |
6817 | adapter->num_vfs); | |
6818 | for (i = 0; i < adapter->num_vfs; i++) | |
6819 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
6820 | } | |
6821 | ||
0365e6e4 PW |
6822 | /* add san mac addr to netdev */ |
6823 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 AK |
6824 | |
6825 | dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n"); | |
6826 | cards_found++; | |
6827 | return 0; | |
6828 | ||
6829 | err_register: | |
5eba3699 | 6830 | ixgbe_release_hw_control(adapter); |
7a921c93 | 6831 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 AK |
6832 | err_sw_init: |
6833 | err_eeprom: | |
1cdd1ec8 GR |
6834 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
6835 | ixgbe_disable_sriov(adapter); | |
c4900be0 DS |
6836 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
6837 | del_timer_sync(&adapter->sfp_timer); | |
6838 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
6839 | cancel_work_sync(&adapter->multispeed_fiber_task); |
6840 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
6841 | iounmap(hw->hw_addr); |
6842 | err_ioremap: | |
6843 | free_netdev(netdev); | |
6844 | err_alloc_etherdev: | |
9ce77666 | 6845 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
6846 | IORESOURCE_MEM)); | |
9a799d71 AK |
6847 | err_pci_reg: |
6848 | err_dma: | |
6849 | pci_disable_device(pdev); | |
6850 | return err; | |
6851 | } | |
6852 | ||
6853 | /** | |
6854 | * ixgbe_remove - Device Removal Routine | |
6855 | * @pdev: PCI device information struct | |
6856 | * | |
6857 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
6858 | * that it should release a PCI device. The could be caused by a | |
6859 | * Hot-Plug event, or because the driver is going to be removed from | |
6860 | * memory. | |
6861 | **/ | |
6862 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
6863 | { | |
6864 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6865 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6866 | ||
6867 | set_bit(__IXGBE_DOWN, &adapter->state); | |
c4900be0 DS |
6868 | /* clear the module not found bit to make sure the worker won't |
6869 | * reschedule | |
6870 | */ | |
6871 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
9a799d71 AK |
6872 | del_timer_sync(&adapter->watchdog_timer); |
6873 | ||
c4900be0 DS |
6874 | del_timer_sync(&adapter->sfp_timer); |
6875 | cancel_work_sync(&adapter->watchdog_task); | |
6876 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
6877 | cancel_work_sync(&adapter->multispeed_fiber_task); |
6878 | cancel_work_sync(&adapter->sfp_config_module_task); | |
c4cf55e5 PWJ |
6879 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
6880 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
6881 | cancel_work_sync(&adapter->fdir_reinit_task); | |
9a799d71 AK |
6882 | flush_scheduled_work(); |
6883 | ||
5dd2d332 | 6884 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
6885 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
6886 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
6887 | dca_remove_requester(&pdev->dev); | |
6888 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
6889 | } | |
6890 | ||
6891 | #endif | |
332d4a7d YZ |
6892 | #ifdef IXGBE_FCOE |
6893 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
6894 | ixgbe_cleanup_fcoe(adapter); | |
6895 | ||
6896 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
6897 | |
6898 | /* remove the added san mac */ | |
6899 | ixgbe_del_sanmac_netdev(netdev); | |
6900 | ||
c4900be0 DS |
6901 | if (netdev->reg_state == NETREG_REGISTERED) |
6902 | unregister_netdev(netdev); | |
9a799d71 | 6903 | |
1cdd1ec8 GR |
6904 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
6905 | ixgbe_disable_sriov(adapter); | |
6906 | ||
7a921c93 | 6907 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 6908 | |
021230d4 | 6909 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
6910 | |
6911 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 6912 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
6913 | IORESOURCE_MEM)); | |
9a799d71 | 6914 | |
021230d4 | 6915 | DPRINTK(PROBE, INFO, "complete\n"); |
021230d4 | 6916 | |
9a799d71 AK |
6917 | free_netdev(netdev); |
6918 | ||
19d5afd4 | 6919 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 6920 | |
9a799d71 AK |
6921 | pci_disable_device(pdev); |
6922 | } | |
6923 | ||
6924 | /** | |
6925 | * ixgbe_io_error_detected - called when PCI error is detected | |
6926 | * @pdev: Pointer to PCI device | |
6927 | * @state: The current pci connection state | |
6928 | * | |
6929 | * This function is called after a PCI bus error affecting | |
6930 | * this device has been detected. | |
6931 | */ | |
6932 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
b4617240 | 6933 | pci_channel_state_t state) |
9a799d71 AK |
6934 | { |
6935 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 6936 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
6937 | |
6938 | netif_device_detach(netdev); | |
6939 | ||
3044b8d1 BL |
6940 | if (state == pci_channel_io_perm_failure) |
6941 | return PCI_ERS_RESULT_DISCONNECT; | |
6942 | ||
9a799d71 AK |
6943 | if (netif_running(netdev)) |
6944 | ixgbe_down(adapter); | |
6945 | pci_disable_device(pdev); | |
6946 | ||
b4617240 | 6947 | /* Request a slot reset. */ |
9a799d71 AK |
6948 | return PCI_ERS_RESULT_NEED_RESET; |
6949 | } | |
6950 | ||
6951 | /** | |
6952 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
6953 | * @pdev: Pointer to PCI device | |
6954 | * | |
6955 | * Restart the card from scratch, as if from a cold-boot. | |
6956 | */ | |
6957 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
6958 | { | |
6959 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 6960 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
6fabd715 PWJ |
6961 | pci_ers_result_t result; |
6962 | int err; | |
9a799d71 | 6963 | |
9ce77666 | 6964 | if (pci_enable_device_mem(pdev)) { |
9a799d71 | 6965 | DPRINTK(PROBE, ERR, |
b4617240 | 6966 | "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
6967 | result = PCI_ERS_RESULT_DISCONNECT; |
6968 | } else { | |
6969 | pci_set_master(pdev); | |
6970 | pci_restore_state(pdev); | |
c0e1f68b | 6971 | pci_save_state(pdev); |
9a799d71 | 6972 | |
dd4d8ca6 | 6973 | pci_wake_from_d3(pdev, false); |
9a799d71 | 6974 | |
6fabd715 | 6975 | ixgbe_reset(adapter); |
88512539 | 6976 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
6977 | result = PCI_ERS_RESULT_RECOVERED; |
6978 | } | |
6979 | ||
6980 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
6981 | if (err) { | |
6982 | dev_err(&pdev->dev, | |
6983 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err); | |
6984 | /* non-fatal, continue */ | |
6985 | } | |
9a799d71 | 6986 | |
6fabd715 | 6987 | return result; |
9a799d71 AK |
6988 | } |
6989 | ||
6990 | /** | |
6991 | * ixgbe_io_resume - called when traffic can start flowing again. | |
6992 | * @pdev: Pointer to PCI device | |
6993 | * | |
6994 | * This callback is called when the error recovery driver tells us that | |
6995 | * its OK to resume normal operation. | |
6996 | */ | |
6997 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
6998 | { | |
6999 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 7000 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
7001 | |
7002 | if (netif_running(netdev)) { | |
7003 | if (ixgbe_up(adapter)) { | |
7004 | DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n"); | |
7005 | return; | |
7006 | } | |
7007 | } | |
7008 | ||
7009 | netif_device_attach(netdev); | |
9a799d71 AK |
7010 | } |
7011 | ||
7012 | static struct pci_error_handlers ixgbe_err_handler = { | |
7013 | .error_detected = ixgbe_io_error_detected, | |
7014 | .slot_reset = ixgbe_io_slot_reset, | |
7015 | .resume = ixgbe_io_resume, | |
7016 | }; | |
7017 | ||
7018 | static struct pci_driver ixgbe_driver = { | |
7019 | .name = ixgbe_driver_name, | |
7020 | .id_table = ixgbe_pci_tbl, | |
7021 | .probe = ixgbe_probe, | |
7022 | .remove = __devexit_p(ixgbe_remove), | |
7023 | #ifdef CONFIG_PM | |
7024 | .suspend = ixgbe_suspend, | |
7025 | .resume = ixgbe_resume, | |
7026 | #endif | |
7027 | .shutdown = ixgbe_shutdown, | |
7028 | .err_handler = &ixgbe_err_handler | |
7029 | }; | |
7030 | ||
7031 | /** | |
7032 | * ixgbe_init_module - Driver Registration Routine | |
7033 | * | |
7034 | * ixgbe_init_module is the first routine called when the driver is | |
7035 | * loaded. All it does is register with the PCI subsystem. | |
7036 | **/ | |
7037 | static int __init ixgbe_init_module(void) | |
7038 | { | |
7039 | int ret; | |
7040 | printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name, | |
7041 | ixgbe_driver_string, ixgbe_driver_version); | |
7042 | ||
7043 | printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright); | |
7044 | ||
5dd2d332 | 7045 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7046 | dca_register_notify(&dca_notifier); |
bd0362dd | 7047 | #endif |
5dd2d332 | 7048 | |
9a799d71 AK |
7049 | ret = pci_register_driver(&ixgbe_driver); |
7050 | return ret; | |
7051 | } | |
b4617240 | 7052 | |
9a799d71 AK |
7053 | module_init(ixgbe_init_module); |
7054 | ||
7055 | /** | |
7056 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
7057 | * | |
7058 | * ixgbe_exit_module is called just before the driver is removed | |
7059 | * from memory. | |
7060 | **/ | |
7061 | static void __exit ixgbe_exit_module(void) | |
7062 | { | |
5dd2d332 | 7063 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7064 | dca_unregister_notify(&dca_notifier); |
7065 | #endif | |
9a799d71 AK |
7066 | pci_unregister_driver(&ixgbe_driver); |
7067 | } | |
bd0362dd | 7068 | |
5dd2d332 | 7069 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7070 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
b4617240 | 7071 | void *p) |
bd0362dd JC |
7072 | { |
7073 | int ret_val; | |
7074 | ||
7075 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
b4617240 | 7076 | __ixgbe_notify_dca); |
bd0362dd JC |
7077 | |
7078 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
7079 | } | |
b453368d | 7080 | |
5dd2d332 | 7081 | #endif /* CONFIG_IXGBE_DCA */ |
b453368d AD |
7082 | #ifdef DEBUG |
7083 | /** | |
7084 | * ixgbe_get_hw_dev_name - return device name string | |
7085 | * used by hardware layer to print debugging information | |
7086 | **/ | |
7087 | char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw) | |
7088 | { | |
7089 | struct ixgbe_adapter *adapter = hw->back; | |
7090 | return adapter->netdev->name; | |
7091 | } | |
bd0362dd | 7092 | |
b453368d | 7093 | #endif |
9a799d71 AK |
7094 | module_exit(ixgbe_exit_module); |
7095 | ||
7096 | /* ixgbe_main.c */ |