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netsched: Allow var_sk_bound_if meta to work on all namespaces
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71
AK		 38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
eacd73f7 43#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 44
45#include "ixgbe.h"
46#include "ixgbe_common.h"
ee5f784a 47#include "ixgbe_dcb_82599.h"
9a799d71
AK		 48
49char ixgbe_driver_name[] = "ixgbe";
9c8eb720 50static const char ixgbe_driver_string[] =
b4617240 51 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 52
e0f4daff 53#define DRV_VERSION "2.0.44-k2"
9c8eb720 54const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 55static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 56
57static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 58 [board_82598] = &ixgbe_82598_info,
e8e26350 59 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 60};
61
62/* ixgbe_pci_tbl - PCI Device ID Table
63 *
64 * Wildcard entries (PCI_ANY_ID) should come last
65 * Last entry must be all 0s
66 *
67 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
68 * Class, Class Mask, private data (not used) }
69 */
70static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 76 board_82598 },
0befdb3e
JB		 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
78 board_82598 },
3845bec0
PWJ		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
80 board_82598 },
9a799d71 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 82 board_82598 },
8d792cd9
JB		 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
84 board_82598 },
c4900be0
DS		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
86 board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
88 board_82598 },
b95f5fcb
JB		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
90 board_82598 },
c4900be0
DS		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
92 board_82598 },
2f21bdd3
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
94 board_82598 },
e8e26350
PW		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
96 board_82599 },
1fcf03e6
PWJ		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
98 board_82599 },
e8e26350
PW		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
100 board_82599 },
38ad1c8e
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
102 board_82599 },
dbfec662
DS		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
104 board_82599 },
8911184f
PWJ		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
106 board_82599 },
312eb931
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
108 board_82599 },
9a799d71
AK		 109
110 /* required last entry */
111 {0, }
112};
113MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
114
5dd2d332 115#ifdef CONFIG_IXGBE_DCA
bd0362dd 116static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 117 void *p);
bd0362dd
JC		 118static struct notifier_block dca_notifier = {
119 .notifier_call = ixgbe_notify_dca,
120 .next = NULL,
121 .priority = 0
122};
123#endif
124
9a799d71
AK		 125MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
126MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
127MODULE_LICENSE("GPL");
128MODULE_VERSION(DRV_VERSION);
129
130#define DEFAULT_DEBUG_LEVEL_SHIFT 3
131
5eba3699
AV		 132static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
133{
134 u32 ctrl_ext;
135
136 /* Let firmware take over control of h/w */
137 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
138 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 139 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 140}
141
142static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
143{
144 u32 ctrl_ext;
145
146 /* Let firmware know the driver has taken over */
147 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
148 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 149 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 150}
9a799d71 151
e8e26350
PW		 152/*
153 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
154 * @adapter: pointer to adapter struct
155 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
156 * @queue: queue to map the corresponding interrupt to
157 * @msix_vector: the vector to map to the corresponding queue
158 *
159 */
160static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
161 u8 queue, u8 msix_vector)
9a799d71
AK		 162{
163 u32 ivar, index;
e8e26350
PW		 164 struct ixgbe_hw *hw = &adapter->hw;
165 switch (hw->mac.type) {
166 case ixgbe_mac_82598EB:
167 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
168 if (direction == -1)
169 direction = 0;
170 index = (((direction * 64) + queue) >> 2) & 0x1F;
171 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
172 ivar &= ~(0xFF << (8 * (queue & 0x3)));
173 ivar |= (msix_vector << (8 * (queue & 0x3)));
174 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
175 break;
176 case ixgbe_mac_82599EB:
177 if (direction == -1) {
178 /* other causes */
179 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
180 index = ((queue & 1) * 8);
181 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
182 ivar &= ~(0xFF << index);
183 ivar |= (msix_vector << index);
184 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
185 break;
186 } else {
187 /* tx or rx causes */
188 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
189 index = ((16 * (queue & 1)) + (8 * direction));
190 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
191 ivar &= ~(0xFF << index);
192 ivar |= (msix_vector << index);
193 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
194 break;
195 }
196 default:
197 break;
198 }
9a799d71
AK		 199}
200
fe49f04a
AD		 201static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
202 u64 qmask)
203{
204 u32 mask;
205
206 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
207 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
208 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
209 } else {
210 mask = (qmask & 0xFFFFFFFF);
211 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
212 mask = (qmask >> 32);
213 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
214 }
215}
216
9a799d71 217static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 218 struct ixgbe_tx_buffer
219 *tx_buffer_info)
9a799d71 220{
44df32c5 221 tx_buffer_info->dma = 0;
9a799d71 222 if (tx_buffer_info->skb) {
44df32c5
AD		 223 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
224 DMA_TO_DEVICE);
9a799d71
AK		 225 dev_kfree_skb_any(tx_buffer_info->skb);
226 tx_buffer_info->skb = NULL;
227 }
44df32c5 228 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 229 /* tx_buffer_info must be completely set up in the transmit path */
230}
231
26f23d82
YZ		 232/**
233 * ixgbe_tx_is_paused - check if the tx ring is paused
234 * @adapter: the ixgbe adapter
235 * @tx_ring: the corresponding tx_ring
236 *
237 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
238 * corresponding TC of this tx_ring when checking TFCS.
239 *
240 * Returns : true if paused
241 */
242static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
243 struct ixgbe_ring *tx_ring)
244{
245 int tc;
246 u32 txoff = IXGBE_TFCS_TXOFF;
247
248#ifdef CONFIG_IXGBE_DCB
249 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
250 int reg_idx = tx_ring->reg_idx;
251 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
252
253 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
254 tc = reg_idx >> 2;
255 txoff = IXGBE_TFCS_TXOFF0;
256 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
257 tc = 0;
258 txoff = IXGBE_TFCS_TXOFF;
259 if (dcb_i == 8) {
260 /* TC0, TC1 */
261 tc = reg_idx >> 5;
262 if (tc == 2) /* TC2, TC3 */
263 tc += (reg_idx - 64) >> 4;
264 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
265 tc += 1 + ((reg_idx - 96) >> 3);
266 } else if (dcb_i == 4) {
267 /* TC0, TC1 */
268 tc = reg_idx >> 6;
269 if (tc == 1) {
270 tc += (reg_idx - 64) >> 5;
271 if (tc == 2) /* TC2, TC3 */
272 tc += (reg_idx - 96) >> 4;
273 }
274 }
275 }
276 txoff <<= tc;
277 }
278#endif
279 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
280}
281
9a799d71 282static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 283 struct ixgbe_ring *tx_ring,
284 unsigned int eop)
9a799d71 285{
e01c31a5 286 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 287
9a799d71 288 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 289 * check with the clearing of time_stamp and movement of eop */
9a799d71 290 adapter->detect_tx_hung = false;
44df32c5 291 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 292 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
26f23d82 293 !ixgbe_tx_is_paused(adapter, tx_ring)) {
9a799d71 294 /* detected Tx unit hang */
e01c31a5
JB		 295 union ixgbe_adv_tx_desc *tx_desc;
296 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 297 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 298 " Tx Queue <%d>\n"
299 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 300 " next_to_use <%x>\n"
301 " next_to_clean <%x>\n"
302 "tx_buffer_info[next_to_clean]\n"
303 " time_stamp <%lx>\n"
e01c31a5
JB		 304 " jiffies <%lx>\n",
305 tx_ring->queue_index,
44df32c5
AD		 306 IXGBE_READ_REG(hw, tx_ring->head),
307 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 308 tx_ring->next_to_use, eop,
309 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 310 return true;
311 }
312
313 return false;
314}
315
b4617240
PW		 316#define IXGBE_MAX_TXD_PWR 14
317#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 318
319/* Tx Descriptors needed, worst case */
320#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
321 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
322#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 323 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 324
e01c31a5
JB		 325static void ixgbe_tx_timeout(struct net_device *netdev);
326
9a799d71
AK		 327/**
328 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 329 * @q_vector: structure containing interrupt and ring information
e01c31a5 330 * @tx_ring: tx ring to clean
9a799d71 331 **/
fe49f04a 332static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 333 struct ixgbe_ring *tx_ring)
9a799d71 334{
fe49f04a 335 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 336 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 337 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
338 struct ixgbe_tx_buffer *tx_buffer_info;
339 unsigned int i, eop, count = 0;
e01c31a5 340 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 341
342 i = tx_ring->next_to_clean;
12207e49
PWJ		 343 eop = tx_ring->tx_buffer_info[i].next_to_watch;
344 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
345
346 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 347 (count < tx_ring->work_limit)) {
12207e49
PWJ		 348 bool cleaned = false;
349 for ( ; !cleaned; count++) {
350 struct sk_buff *skb;
9a799d71
AK		 351 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
352 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 353 cleaned = (i == eop);
e01c31a5 354 skb = tx_buffer_info->skb;
9a799d71 355
12207e49 356 if (cleaned && skb) {
e092be60 357 unsigned int segs, bytecount;
3d8fd385 358 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 359
360 /* gso_segs is currently only valid for tcp */
e092be60 361 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 362#ifdef IXGBE_FCOE
363 /* adjust for FCoE Sequence Offload */
364 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
365 && (skb->protocol == htons(ETH_P_FCOE)) &&
366 skb_is_gso(skb)) {
367 hlen = skb_transport_offset(skb) +
368 sizeof(struct fc_frame_header) +
369 sizeof(struct fcoe_crc_eof);
370 segs = DIV_ROUND_UP(skb->len - hlen,
371 skb_shinfo(skb)->gso_size);
372 }
373#endif /* IXGBE_FCOE */
e092be60 374 /* multiply data chunks by size of headers */
3d8fd385 375 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 376 total_packets += segs;
377 total_bytes += bytecount;
e092be60 378 }
e01c31a5 379
9a799d71 380 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 381 tx_buffer_info);
9a799d71 382
12207e49
PWJ		 383 tx_desc->wb.status = 0;
384
9a799d71
AK		 385 i++;
386 if (i == tx_ring->count)
387 i = 0;
e01c31a5 388 }
12207e49
PWJ		 389
390 eop = tx_ring->tx_buffer_info[i].next_to_watch;
391 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
392 }
393
9a799d71
AK		 394 tx_ring->next_to_clean = i;
395
e092be60 396#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 397 if (unlikely(count && netif_carrier_ok(netdev) &&
398 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 399 /* Make sure that anybody stopping the queue after this
400 * sees the new next_to_clean.
401 */
402 smp_mb();
30eba97a
AV		 403 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
404 !test_bit(__IXGBE_DOWN, &adapter->state)) {
405 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 406 ++adapter->restart_queue;
30eba97a 407 }
e092be60 408 }
9a799d71 409
e01c31a5
JB		 410 if (adapter->detect_tx_hung) {
411 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
412 /* schedule immediate reset if we believe we hung */
413 DPRINTK(PROBE, INFO,
414 "tx hang %d detected, resetting adapter\n",
415 adapter->tx_timeout_count + 1);
416 ixgbe_tx_timeout(adapter->netdev);
417 }
418 }
9a799d71 419
e01c31a5 420 /* re-arm the interrupt */
fe49f04a
AD		 421 if (count >= tx_ring->work_limit)
422 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 423
e01c31a5
JB		 424 tx_ring->total_bytes += total_bytes;
425 tx_ring->total_packets += total_packets;
e01c31a5 426 tx_ring->stats.packets += total_packets;
12207e49 427 tx_ring->stats.bytes += total_bytes;
2d86f139
AK		 428 netdev->stats.tx_bytes += total_bytes;
429 netdev->stats.tx_packets += total_packets;
9a1a69ad 430 return (count < tx_ring->work_limit);
9a799d71
AK		 431}
432
5dd2d332 433#ifdef CONFIG_IXGBE_DCA
bd0362dd 434static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 435 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 436{
437 u32 rxctrl;
438 int cpu = get_cpu();
3a581073 439 int q = rx_ring - adapter->rx_ring;
bd0362dd 440
3a581073 441 if (rx_ring->cpu != cpu) {
bd0362dd 442 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 443 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
444 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
445 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
446 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
447 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
448 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
449 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
450 }
bd0362dd
JC		 451 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
452 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 453 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
454 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 455 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 456 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 457 rx_ring->cpu = cpu;
bd0362dd
JC		 458 }
459 put_cpu();
460}
461
462static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 463 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 464{
465 u32 txctrl;
466 int cpu = get_cpu();
3a581073 467 int q = tx_ring - adapter->tx_ring;
ee5f784a 468 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 469
3a581073 470 if (tx_ring->cpu != cpu) {
e8e26350 471 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 472 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 473 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
474 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 475 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
476 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 477 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 478 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 479 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
480 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 481 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
482 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
483 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 484 }
3a581073 485 tx_ring->cpu = cpu;
bd0362dd
JC		 486 }
487 put_cpu();
488}
489
490static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
491{
492 int i;
493
494 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
495 return;
496
e35ec126
AD		 497 /* always use CB2 mode, difference is masked in the CB driver */
498 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
499
bd0362dd
JC		 500 for (i = 0; i < adapter->num_tx_queues; i++) {
501 adapter->tx_ring[i].cpu = -1;
502 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
503 }
504 for (i = 0; i < adapter->num_rx_queues; i++) {
505 adapter->rx_ring[i].cpu = -1;
506 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
507 }
508}
509
510static int __ixgbe_notify_dca(struct device *dev, void *data)
511{
512 struct net_device *netdev = dev_get_drvdata(dev);
513 struct ixgbe_adapter *adapter = netdev_priv(netdev);
514 unsigned long event = *(unsigned long *)data;
515
516 switch (event) {
517 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 518 /* if we're already enabled, don't do it again */
519 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
520 break;
652f093f 521 if (dca_add_requester(dev) == 0) {
96b0e0f6 522 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 523 ixgbe_setup_dca(adapter);
524 break;
525 }
526 /* Fall Through since DCA is disabled. */
527 case DCA_PROVIDER_REMOVE:
528 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
529 dca_remove_requester(dev);
530 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
531 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
532 }
533 break;
534 }
535
652f093f 536 return 0;
bd0362dd
JC		 537}
538
5dd2d332 539#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 540/**
541 * ixgbe_receive_skb - Send a completed packet up the stack
542 * @adapter: board private structure
543 * @skb: packet to send up
177db6ff
MC		 544 * @status: hardware indication of status of receive
545 * @rx_ring: rx descriptor ring (for a specific queue) to setup
546 * @rx_desc: rx descriptor
9a799d71 547 **/
78b6f4ce 548static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 549 struct sk_buff *skb, u8 status,
fdaff1ce 550 struct ixgbe_ring *ring,
177db6ff 551 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 552{
78b6f4ce
HX		 553 struct ixgbe_adapter *adapter = q_vector->adapter;
554 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 555 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
556 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 557
fdaff1ce 558 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 559 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 560 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 561 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 562 else
78b6f4ce 563 napi_gro_receive(napi, skb);
177db6ff 564 } else {
8a62babf 565 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 566 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
567 else
568 netif_rx(skb);
9a799d71
AK		 569 }
570}
571
e59bd25d
AV		 572/**
573 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
574 * @adapter: address of board private structure
575 * @status_err: hardware indication of status of receive
576 * @skb: skb currently being received and modified
577 **/
9a799d71 578static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 579 union ixgbe_adv_rx_desc *rx_desc,
580 struct sk_buff *skb)
9a799d71 581{
8bae1b2b
DS		 582 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
583
9a799d71
AK		 584 skb->ip_summed = CHECKSUM_NONE;
585
712744be
JB		 586 /* Rx csum disabled */
587 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 588 return;
e59bd25d
AV		 589
590 /* if IP and error */
591 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
592 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 593 adapter->hw_csum_rx_error++;
594 return;
595 }
e59bd25d
AV		 596
597 if (!(status_err & IXGBE_RXD_STAT_L4CS))
598 return;
599
600 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 601 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
602
603 /*
604 * 82599 errata, UDP frames with a 0 checksum can be marked as
605 * checksum errors.
606 */
607 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
608 (adapter->hw.mac.type == ixgbe_mac_82599EB))
609 return;
610
e59bd25d
AV		 611 adapter->hw_csum_rx_error++;
612 return;
613 }
614
9a799d71 615 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 616 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 617 adapter->hw_csum_rx_good++;
618}
619
e8e26350
PW		 620static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
621 struct ixgbe_ring *rx_ring, u32 val)
622{
623 /*
624 * Force memory writes to complete before letting h/w
625 * know there are new descriptors to fetch. (Only
626 * applicable for weak-ordered memory model archs,
627 * such as IA-64).
628 */
629 wmb();
630 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
631}
632
9a799d71
AK		 633/**
634 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
635 * @adapter: address of board private structure
636 **/
637static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 638 struct ixgbe_ring *rx_ring,
639 int cleaned_count)
9a799d71 640{
9a799d71
AK		 641 struct pci_dev *pdev = adapter->pdev;
642 union ixgbe_adv_rx_desc *rx_desc;
3a581073 643 struct ixgbe_rx_buffer *bi;
9a799d71 644 unsigned int i;
9a799d71
AK		 645
646 i = rx_ring->next_to_use;
3a581073 647 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 648
649 while (cleaned_count--) {
650 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
651
762f4c57 652 if (!bi->page_dma &&
6e455b89 653 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 654 if (!bi->page) {
762f4c57
JB		 655 bi->page = alloc_page(GFP_ATOMIC);
656 if (!bi->page) {
657 adapter->alloc_rx_page_failed++;
658 goto no_buffers;
659 }
660 bi->page_offset = 0;
661 } else {
662 /* use a half page if we're re-using */
663 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 664 }
762f4c57
JB		 665
666 bi->page_dma = pci_map_page(pdev, bi->page,
667 bi->page_offset,
668 (PAGE_SIZE / 2),
669 PCI_DMA_FROMDEVICE);
9a799d71
AK		 670 }
671
3a581073 672 if (!bi->skb) {
5ecc3614 673 struct sk_buff *skb;
89d71a66
ED		 674 skb = netdev_alloc_skb_ip_align(adapter->netdev,
675 rx_ring->rx_buf_len);
9a799d71
AK		 676
677 if (!skb) {
678 adapter->alloc_rx_buff_failed++;
679 goto no_buffers;
680 }
681
3a581073 682 bi->skb = skb;
4f57ca6e
JB		 683 bi->dma = pci_map_single(pdev, skb->data,
684 rx_ring->rx_buf_len,
3a581073 685 PCI_DMA_FROMDEVICE);
9a799d71
AK		 686 }
687 /* Refresh the desc even if buffer_addrs didn't change because
688 * each write-back erases this info. */
6e455b89 689 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 690 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
691 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 692 } else {
3a581073 693 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 694 }
695
696 i++;
697 if (i == rx_ring->count)
698 i = 0;
3a581073 699 bi = &rx_ring->rx_buffer_info[i];
9a799d71 700 }
7c6e0a43 701
9a799d71
AK		 702no_buffers:
703 if (rx_ring->next_to_use != i) {
704 rx_ring->next_to_use = i;
705 if (i-- == 0)
706 i = (rx_ring->count - 1);
707
e8e26350 708 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 709 }
710}
711
7c6e0a43
JB		 712static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
713{
714 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
715}
716
717static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
718{
719 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
720}
721
f8212f97
AD		 722static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
723{
724 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
725 IXGBE_RXDADV_RSCCNT_MASK) >>
726 IXGBE_RXDADV_RSCCNT_SHIFT;
727}
728
729/**
730 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
731 * @skb: pointer to the last skb in the rsc queue
732 *
733 * This function changes a queue full of hw rsc buffers into a completed
734 * packet. It uses the ->prev pointers to find the first packet and then
735 * turns it into the frag list owner.
736 **/
737static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
738{
739 unsigned int frag_list_size = 0;
740
741 while (skb->prev) {
742 struct sk_buff *prev = skb->prev;
743 frag_list_size += skb->len;
744 skb->prev = NULL;
745 skb = prev;
746 }
747
748 skb_shinfo(skb)->frag_list = skb->next;
749 skb->next = NULL;
750 skb->len += frag_list_size;
751 skb->data_len += frag_list_size;
752 skb->truesize += frag_list_size;
753 return skb;
754}
755
78b6f4ce 756static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 757 struct ixgbe_ring *rx_ring,
758 int *work_done, int work_to_do)
9a799d71 759{
78b6f4ce 760 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 761 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 762 struct pci_dev *pdev = adapter->pdev;
763 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
764 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
765 struct sk_buff *skb;
f8212f97 766 unsigned int i, rsc_count = 0;
7c6e0a43 767 u32 len, staterr;
177db6ff
MC		 768 u16 hdr_info;
769 bool cleaned = false;
9a799d71 770 int cleaned_count = 0;
d2f4fbe2 771 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 772#ifdef IXGBE_FCOE
773 int ddp_bytes = 0;
774#endif /* IXGBE_FCOE */
9a799d71
AK		 775
776 i = rx_ring->next_to_clean;
9a799d71
AK		 777 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
778 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
779 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 780
781 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 782 u32 upper_len = 0;
9a799d71
AK		 783 if (*work_done >= work_to_do)
784 break;
785 (*work_done)++;
786
6e455b89 787 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 788 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
789 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 790 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 791 if (hdr_info & IXGBE_RXDADV_SPH)
792 adapter->rx_hdr_split++;
793 if (len > IXGBE_RX_HDR_SIZE)
794 len = IXGBE_RX_HDR_SIZE;
795 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 796 } else {
9a799d71 797 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 798 }
9a799d71
AK		 799
800 cleaned = true;
801 skb = rx_buffer_info->skb;
802 prefetch(skb->data - NET_IP_ALIGN);
803 rx_buffer_info->skb = NULL;
804
21fa4e66 805 if (rx_buffer_info->dma) {
9a799d71 806 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 807 rx_ring->rx_buf_len,
b4617240 808 PCI_DMA_FROMDEVICE);
4f57ca6e 809 rx_buffer_info->dma = 0;
9a799d71
AK		 810 skb_put(skb, len);
811 }
812
813 if (upper_len) {
814 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 815 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 816 rx_buffer_info->page_dma = 0;
817 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 818 rx_buffer_info->page,
819 rx_buffer_info->page_offset,
820 upper_len);
821
822 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
823 (page_count(rx_buffer_info->page) != 1))
824 rx_buffer_info->page = NULL;
825 else
826 get_page(rx_buffer_info->page);
9a799d71
AK		 827
828 skb->len += upper_len;
829 skb->data_len += upper_len;
830 skb->truesize += upper_len;
831 }
832
833 i++;
834 if (i == rx_ring->count)
835 i = 0;
9a799d71
AK		 836
837 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
838 prefetch(next_rxd);
9a799d71 839 cleaned_count++;
f8212f97 840
0c19d6af 841 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 842 rsc_count = ixgbe_get_rsc_count(rx_desc);
843
844 if (rsc_count) {
845 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
846 IXGBE_RXDADV_NEXTP_SHIFT;
847 next_buffer = &rx_ring->rx_buffer_info[nextp];
848 rx_ring->rsc_count += (rsc_count - 1);
849 } else {
850 next_buffer = &rx_ring->rx_buffer_info[i];
851 }
852
9a799d71 853 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97
AD		 854 if (skb->prev)
855 skb = ixgbe_transform_rsc_queue(skb);
9a799d71
AK		 856 rx_ring->stats.packets++;
857 rx_ring->stats.bytes += skb->len;
858 } else {
6e455b89 859 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 860 rx_buffer_info->skb = next_buffer->skb;
861 rx_buffer_info->dma = next_buffer->dma;
862 next_buffer->skb = skb;
863 next_buffer->dma = 0;
864 } else {
865 skb->next = next_buffer->skb;
866 skb->next->prev = skb;
867 }
9a799d71
AK		 868 adapter->non_eop_descs++;
869 goto next_desc;
870 }
871
872 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
873 dev_kfree_skb_irq(skb);
874 goto next_desc;
875 }
876
8bae1b2b 877 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 878
879 /* probably a little skewed due to removing CRC */
880 total_rx_bytes += skb->len;
881 total_rx_packets++;
882
74ce8dd2 883 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 884#ifdef IXGBE_FCOE
885 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 886 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
887 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
888 if (!ddp_bytes)
332d4a7d 889 goto next_desc;
3d8fd385 890 }
332d4a7d 891#endif /* IXGBE_FCOE */
fdaff1ce 892 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 893
894next_desc:
895 rx_desc->wb.upper.status_error = 0;
896
897 /* return some buffers to hardware, one at a time is too slow */
898 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
899 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
900 cleaned_count = 0;
901 }
902
903 /* use prefetched values */
904 rx_desc = next_rxd;
f8212f97 905 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 906
907 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 908 }
909
9a799d71
AK		 910 rx_ring->next_to_clean = i;
911 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
912
913 if (cleaned_count)
914 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
915
3d8fd385
YZ		 916#ifdef IXGBE_FCOE
917 /* include DDPed FCoE data */
918 if (ddp_bytes > 0) {
919 unsigned int mss;
920
921 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
922 sizeof(struct fc_frame_header) -
923 sizeof(struct fcoe_crc_eof);
924 if (mss > 512)
925 mss &= ~511;
926 total_rx_bytes += ddp_bytes;
927 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
928 }
929#endif /* IXGBE_FCOE */
930
f494e8fa
AV		 931 rx_ring->total_packets += total_rx_packets;
932 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 933 netdev->stats.rx_bytes += total_rx_bytes;
934 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 935
9a799d71
AK		 936 return cleaned;
937}
938
021230d4 939static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 940/**
941 * ixgbe_configure_msix - Configure MSI-X hardware
942 * @adapter: board private structure
943 *
944 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
945 * interrupts.
946 **/
947static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
948{
021230d4
AV		 949 struct ixgbe_q_vector *q_vector;
950 int i, j, q_vectors, v_idx, r_idx;
951 u32 mask;
9a799d71 952
021230d4 953 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 954
4df10466
JB		 955 /*
956 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 957 * corresponding register.
958 */
959 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 960 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 961 /* XXX for_each_bit(...) */
962 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 963 adapter->num_rx_queues);
021230d4
AV		 964
965 for (i = 0; i < q_vector->rxr_count; i++) {
966 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 967 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 968 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 969 adapter->num_rx_queues,
970 r_idx + 1);
021230d4
AV		 971 }
972 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 973 adapter->num_tx_queues);
021230d4
AV		 974
975 for (i = 0; i < q_vector->txr_count; i++) {
976 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 977 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 978 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 979 adapter->num_tx_queues,
980 r_idx + 1);
021230d4
AV		 981 }
982
021230d4 983 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 984 /* tx only */
985 q_vector->eitr = adapter->tx_eitr_param;
509ee935 986 else if (q_vector->rxr_count)
f7554a2b
NS		 987 /* rx or mixed */
988 q_vector->eitr = adapter->rx_eitr_param;
021230d4 989
fe49f04a 990 ixgbe_write_eitr(q_vector);
9a799d71
AK		 991 }
992
e8e26350
PW		 993 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
994 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
995 v_idx);
996 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
997 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 998 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
999
41fb9248 1000 /* set up to autoclear timer, and the vectors */
021230d4 1001 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 1002 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1003 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1004}
1005
f494e8fa
AV		 1006enum latency_range {
1007 lowest_latency = 0,
1008 low_latency = 1,
1009 bulk_latency = 2,
1010 latency_invalid = 255
1011};
1012
1013/**
1014 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1015 * @adapter: pointer to adapter
1016 * @eitr: eitr setting (ints per sec) to give last timeslice
1017 * @itr_setting: current throttle rate in ints/second
1018 * @packets: the number of packets during this measurement interval
1019 * @bytes: the number of bytes during this measurement interval
1020 *
1021 * Stores a new ITR value based on packets and byte
1022 * counts during the last interrupt. The advantage of per interrupt
1023 * computation is faster updates and more accurate ITR for the current
1024 * traffic pattern. Constants in this function were computed
1025 * based on theoretical maximum wire speed and thresholds were set based
1026 * on testing data as well as attempting to minimize response time
1027 * while increasing bulk throughput.
1028 * this functionality is controlled by the InterruptThrottleRate module
1029 * parameter (see ixgbe_param.c)
1030 **/
1031static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1032 u32 eitr, u8 itr_setting,
1033 int packets, int bytes)
f494e8fa
AV		 1034{
1035 unsigned int retval = itr_setting;
1036 u32 timepassed_us;
1037 u64 bytes_perint;
1038
1039 if (packets == 0)
1040 goto update_itr_done;
1041
1042
1043 /* simple throttlerate management
1044 * 0-20MB/s lowest (100000 ints/s)
1045 * 20-100MB/s low (20000 ints/s)
1046 * 100-1249MB/s bulk (8000 ints/s)
1047 */
1048 /* what was last interrupt timeslice? */
1049 timepassed_us = 1000000/eitr;
1050 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1051
1052 switch (itr_setting) {
1053 case lowest_latency:
1054 if (bytes_perint > adapter->eitr_low)
1055 retval = low_latency;
1056 break;
1057 case low_latency:
1058 if (bytes_perint > adapter->eitr_high)
1059 retval = bulk_latency;
1060 else if (bytes_perint <= adapter->eitr_low)
1061 retval = lowest_latency;
1062 break;
1063 case bulk_latency:
1064 if (bytes_perint <= adapter->eitr_high)
1065 retval = low_latency;
1066 break;
1067 }
1068
1069update_itr_done:
1070 return retval;
1071}
1072
509ee935
JB		 1073/**
1074 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1075 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1076 *
1077 * This function is made to be called by ethtool and by the driver
1078 * when it needs to update EITR registers at runtime. Hardware
1079 * specific quirks/differences are taken care of here.
1080 */
fe49f04a 1081void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1082{
fe49f04a 1083 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1084 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1085 int v_idx = q_vector->v_idx;
1086 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1087
509ee935
JB		 1088 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1089 /* must write high and low 16 bits to reset counter */
1090 itr_reg |= (itr_reg << 16);
1091 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1092 /*
1093 * set the WDIS bit to not clear the timer bits and cause an
1094 * immediate assertion of the interrupt
1095 */
1096 itr_reg |= IXGBE_EITR_CNT_WDIS;
1097 }
1098 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1099}
1100
f494e8fa
AV		 1101static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1102{
1103 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1104 u32 new_itr;
1105 u8 current_itr, ret_itr;
fe49f04a 1106 int i, r_idx;
f494e8fa
AV		 1107 struct ixgbe_ring *rx_ring, *tx_ring;
1108
1109 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1110 for (i = 0; i < q_vector->txr_count; i++) {
1111 tx_ring = &(adapter->tx_ring[r_idx]);
1112 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1113 q_vector->tx_itr,
1114 tx_ring->total_packets,
1115 tx_ring->total_bytes);
f494e8fa
AV		 1116 /* if the result for this queue would decrease interrupt
1117 * rate for this vector then use that result */
30efa5a3 1118 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1119 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1120 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1121 r_idx + 1);
f494e8fa
AV		 1122 }
1123
1124 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1125 for (i = 0; i < q_vector->rxr_count; i++) {
1126 rx_ring = &(adapter->rx_ring[r_idx]);
1127 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1128 q_vector->rx_itr,
1129 rx_ring->total_packets,
1130 rx_ring->total_bytes);
f494e8fa
AV		 1131 /* if the result for this queue would decrease interrupt
1132 * rate for this vector then use that result */
30efa5a3 1133 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1134 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1135 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1136 r_idx + 1);
f494e8fa
AV		 1137 }
1138
30efa5a3 1139 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1140
1141 switch (current_itr) {
1142 /* counts and packets in update_itr are dependent on these numbers */
1143 case lowest_latency:
1144 new_itr = 100000;
1145 break;
1146 case low_latency:
1147 new_itr = 20000; /* aka hwitr = ~200 */
1148 break;
1149 case bulk_latency:
1150 default:
1151 new_itr = 8000;
1152 break;
1153 }
1154
1155 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1156 /* do an exponential smoothing */
1157 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1158
1159 /* save the algorithm value here, not the smoothed one */
1160 q_vector->eitr = new_itr;
fe49f04a
AD		 1161
1162 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1163 }
1164
1165 return;
1166}
1167
0befdb3e
JB		 1168static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1169{
1170 struct ixgbe_hw *hw = &adapter->hw;
1171
1172 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1173 (eicr & IXGBE_EICR_GPI_SDP1)) {
1174 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1175 /* write to clear the interrupt */
1176 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1177 }
1178}
cf8280ee 1179
e8e26350
PW		 1180static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1181{
1182 struct ixgbe_hw *hw = &adapter->hw;
1183
1184 if (eicr & IXGBE_EICR_GPI_SDP1) {
1185 /* Clear the interrupt */
1186 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1187 schedule_work(&adapter->multispeed_fiber_task);
1188 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1189 /* Clear the interrupt */
1190 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1191 schedule_work(&adapter->sfp_config_module_task);
1192 } else {
1193 /* Interrupt isn't for us... */
1194 return;
1195 }
1196}
1197
cf8280ee
JB		 1198static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1199{
1200 struct ixgbe_hw *hw = &adapter->hw;
1201
1202 adapter->lsc_int++;
1203 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1204 adapter->link_check_timeout = jiffies;
1205 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1206 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1207 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1208 schedule_work(&adapter->watchdog_task);
1209 }
1210}
1211
9a799d71
AK		 1212static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1213{
1214 struct net_device *netdev = data;
1215 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1216 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1217 u32 eicr;
1218
1219 /*
1220 * Workaround for Silicon errata. Use clear-by-write instead
1221 * of clear-by-read. Reading with EICS will return the
1222 * interrupt causes without clearing, which later be done
1223 * with the write to EICR.
1224 */
1225 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1226 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1227
cf8280ee
JB		 1228 if (eicr & IXGBE_EICR_LSC)
1229 ixgbe_check_lsc(adapter);
d4f80882 1230
e8e26350
PW		 1231 if (hw->mac.type == ixgbe_mac_82598EB)
1232 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1233
c4cf55e5 1234 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1235 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1236
1237 /* Handle Flow Director Full threshold interrupt */
1238 if (eicr & IXGBE_EICR_FLOW_DIR) {
1239 int i;
1240 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1241 /* Disable transmits before FDIR Re-initialization */
1242 netif_tx_stop_all_queues(netdev);
1243 for (i = 0; i < adapter->num_tx_queues; i++) {
1244 struct ixgbe_ring *tx_ring =
1245 &adapter->tx_ring[i];
1246 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1247 &tx_ring->reinit_state))
1248 schedule_work(&adapter->fdir_reinit_task);
1249 }
1250 }
1251 }
d4f80882
AV		 1252 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1253 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1254
1255 return IRQ_HANDLED;
1256}
1257
fe49f04a
AD		 1258static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1259 u64 qmask)
1260{
1261 u32 mask;
1262
1263 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1264 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1265 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1266 } else {
1267 mask = (qmask & 0xFFFFFFFF);
1268 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1269 mask = (qmask >> 32);
1270 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1271 }
1272 /* skip the flush */
1273}
1274
1275static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1276 u64 qmask)
1277{
1278 u32 mask;
1279
1280 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1281 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1282 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1283 } else {
1284 mask = (qmask & 0xFFFFFFFF);
1285 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1286 mask = (qmask >> 32);
1287 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1288 }
1289 /* skip the flush */
1290}
1291
9a799d71
AK		 1292static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1293{
021230d4
AV		 1294 struct ixgbe_q_vector *q_vector = data;
1295 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1296 struct ixgbe_ring *tx_ring;
021230d4
AV		 1297 int i, r_idx;
1298
1299 if (!q_vector->txr_count)
1300 return IRQ_HANDLED;
1301
1302 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1303 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1304 tx_ring = &(adapter->tx_ring[r_idx]);
3a581073
JB		 1305 tx_ring->total_bytes = 0;
1306 tx_ring->total_packets = 0;
021230d4 1307 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1308 r_idx + 1);
021230d4 1309 }
9a799d71 1310
91281fd3
AD		 1311 /* disable interrupts on this vector only */
1312 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1313 napi_schedule(&q_vector->napi);
1314
9a799d71
AK		 1315 return IRQ_HANDLED;
1316}
1317
021230d4
AV		 1318/**
1319 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1320 * @irq: unused
1321 * @data: pointer to our q_vector struct for this interrupt vector
1322 **/
9a799d71
AK		 1323static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1324{
021230d4
AV		 1325 struct ixgbe_q_vector *q_vector = data;
1326 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1327 struct ixgbe_ring *rx_ring;
021230d4 1328 int r_idx;
30efa5a3 1329 int i;
021230d4
AV		 1330
1331 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1332 for (i = 0; i < q_vector->rxr_count; i++) {
1333 rx_ring = &(adapter->rx_ring[r_idx]);
1334 rx_ring->total_bytes = 0;
1335 rx_ring->total_packets = 0;
1336 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1337 r_idx + 1);
1338 }
1339
021230d4
AV		 1340 if (!q_vector->rxr_count)
1341 return IRQ_HANDLED;
1342
021230d4 1343 /* disable interrupts on this vector only */
fe49f04a 1344 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
288379f0 1345 napi_schedule(&q_vector->napi);
021230d4
AV		 1346
1347 return IRQ_HANDLED;
1348}
1349
1350static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1351{
91281fd3
AD		 1352 struct ixgbe_q_vector *q_vector = data;
1353 struct ixgbe_adapter *adapter = q_vector->adapter;
1354 struct ixgbe_ring *ring;
1355 int r_idx;
1356 int i;
1357
1358 if (!q_vector->txr_count && !q_vector->rxr_count)
1359 return IRQ_HANDLED;
1360
1361 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1362 for (i = 0; i < q_vector->txr_count; i++) {
1363 ring = &(adapter->tx_ring[r_idx]);
1364 ring->total_bytes = 0;
1365 ring->total_packets = 0;
1366 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1367 r_idx + 1);
1368 }
1369
1370 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1371 for (i = 0; i < q_vector->rxr_count; i++) {
1372 ring = &(adapter->rx_ring[r_idx]);
1373 ring->total_bytes = 0;
1374 ring->total_packets = 0;
1375 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1376 r_idx + 1);
1377 }
1378
1379 /* disable interrupts on this vector only */
1380 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1381 napi_schedule(&q_vector->napi);
9a799d71 1382
9a799d71
AK		 1383 return IRQ_HANDLED;
1384}
1385
021230d4
AV		 1386/**
1387 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1388 * @napi: napi struct with our devices info in it
1389 * @budget: amount of work driver is allowed to do this pass, in packets
1390 *
f0848276
JB		 1391 * This function is optimized for cleaning one queue only on a single
1392 * q_vector!!!
021230d4 1393 **/
9a799d71
AK		 1394static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1395{
021230d4 1396 struct ixgbe_q_vector *q_vector =
b4617240 1397 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1398 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1399 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1400 int work_done = 0;
021230d4 1401 long r_idx;
9a799d71 1402
021230d4 1403 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1404 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1405#ifdef CONFIG_IXGBE_DCA
bd0362dd 1406 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1407 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1408#endif
9a799d71 1409
78b6f4ce 1410 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1411
021230d4
AV		 1412 /* If all Rx work done, exit the polling mode */
1413 if (work_done < budget) {
288379f0 1414 napi_complete(napi);
f7554a2b 1415 if (adapter->rx_itr_setting & 1)
f494e8fa 1416 ixgbe_set_itr_msix(q_vector);
9a799d71 1417 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1418 ixgbe_irq_enable_queues(adapter,
1419 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1420 }
1421
1422 return work_done;
1423}
1424
f0848276 1425/**
91281fd3 1426 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1427 * @napi: napi struct with our devices info in it
1428 * @budget: amount of work driver is allowed to do this pass, in packets
1429 *
1430 * This function will clean more than one rx queue associated with a
1431 * q_vector.
1432 **/
91281fd3 1433static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1434{
1435 struct ixgbe_q_vector *q_vector =
1436 container_of(napi, struct ixgbe_q_vector, napi);
1437 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1438 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1439 int work_done = 0, i;
1440 long r_idx;
91281fd3
AD		 1441 bool tx_clean_complete = true;
1442
1443 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1444 for (i = 0; i < q_vector->txr_count; i++) {
1445 ring = &(adapter->tx_ring[r_idx]);
1446#ifdef CONFIG_IXGBE_DCA
1447 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1448 ixgbe_update_tx_dca(adapter, ring);
1449#endif
1450 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1451 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1452 r_idx + 1);
1453 }
f0848276
JB		 1454
1455 /* attempt to distribute budget to each queue fairly, but don't allow
1456 * the budget to go below 1 because we'll exit polling */
1457 budget /= (q_vector->rxr_count ?: 1);
1458 budget = max(budget, 1);
1459 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1460 for (i = 0; i < q_vector->rxr_count; i++) {
91281fd3 1461 ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1462#ifdef CONFIG_IXGBE_DCA
f0848276 1463 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1464 ixgbe_update_rx_dca(adapter, ring);
f0848276 1465#endif
91281fd3 1466 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1467 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1468 r_idx + 1);
1469 }
1470
1471 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
91281fd3 1472 ring = &(adapter->rx_ring[r_idx]);
f0848276 1473 /* If all Rx work done, exit the polling mode */
7f821875 1474 if (work_done < budget) {
288379f0 1475 napi_complete(napi);
f7554a2b 1476 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1477 ixgbe_set_itr_msix(q_vector);
1478 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1479 ixgbe_irq_enable_queues(adapter,
1480 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1481 return 0;
1482 }
1483
1484 return work_done;
1485}
91281fd3
AD		 1486
1487/**
1488 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1489 * @napi: napi struct with our devices info in it
1490 * @budget: amount of work driver is allowed to do this pass, in packets
1491 *
1492 * This function is optimized for cleaning one queue only on a single
1493 * q_vector!!!
1494 **/
1495static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1496{
1497 struct ixgbe_q_vector *q_vector =
1498 container_of(napi, struct ixgbe_q_vector, napi);
1499 struct ixgbe_adapter *adapter = q_vector->adapter;
1500 struct ixgbe_ring *tx_ring = NULL;
1501 int work_done = 0;
1502 long r_idx;
1503
1504 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1505 tx_ring = &(adapter->tx_ring[r_idx]);
1506#ifdef CONFIG_IXGBE_DCA
1507 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1508 ixgbe_update_tx_dca(adapter, tx_ring);
1509#endif
1510
1511 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1512 work_done = budget;
1513
f7554a2b 1514 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 1515 if (work_done < budget) {
1516 napi_complete(napi);
f7554a2b 1517 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 1518 ixgbe_set_itr_msix(q_vector);
1519 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1520 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1521 }
1522
1523 return work_done;
1524}
1525
021230d4 1526static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1527 int r_idx)
021230d4 1528{
7a921c93
AD		 1529 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1530
1531 set_bit(r_idx, q_vector->rxr_idx);
1532 q_vector->rxr_count++;
021230d4
AV		 1533}
1534
1535static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1536 int t_idx)
021230d4 1537{
7a921c93
AD		 1538 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1539
1540 set_bit(t_idx, q_vector->txr_idx);
1541 q_vector->txr_count++;
021230d4
AV		 1542}
1543
9a799d71 1544/**
021230d4
AV		 1545 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1546 * @adapter: board private structure to initialize
1547 * @vectors: allotted vector count for descriptor rings
9a799d71 1548 *
021230d4
AV		 1549 * This function maps descriptor rings to the queue-specific vectors
1550 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1551 * one vector per ring/queue, but on a constrained vector budget, we
1552 * group the rings as "efficiently" as possible. You would add new
1553 * mapping configurations in here.
9a799d71 1554 **/
021230d4 1555static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1556 int vectors)
021230d4
AV		 1557{
1558 int v_start = 0;
1559 int rxr_idx = 0, txr_idx = 0;
1560 int rxr_remaining = adapter->num_rx_queues;
1561 int txr_remaining = adapter->num_tx_queues;
1562 int i, j;
1563 int rqpv, tqpv;
1564 int err = 0;
1565
1566 /* No mapping required if MSI-X is disabled. */
1567 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1568 goto out;
9a799d71 1569
021230d4
AV		 1570 /*
1571 * The ideal configuration...
1572 * We have enough vectors to map one per queue.
1573 */
1574 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1575 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1576 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1577
021230d4
AV		 1578 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1579 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1580
9a799d71 1581 goto out;
021230d4 1582 }
9a799d71 1583
021230d4
AV		 1584 /*
1585 * If we don't have enough vectors for a 1-to-1
1586 * mapping, we'll have to group them so there are
1587 * multiple queues per vector.
1588 */
1589 /* Re-adjusting *qpv takes care of the remainder. */
1590 for (i = v_start; i < vectors; i++) {
1591 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1592 for (j = 0; j < rqpv; j++) {
1593 map_vector_to_rxq(adapter, i, rxr_idx);
1594 rxr_idx++;
1595 rxr_remaining--;
1596 }
1597 }
1598 for (i = v_start; i < vectors; i++) {
1599 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1600 for (j = 0; j < tqpv; j++) {
1601 map_vector_to_txq(adapter, i, txr_idx);
1602 txr_idx++;
1603 txr_remaining--;
9a799d71 1604 }
9a799d71
AK		 1605 }
1606
021230d4
AV		 1607out:
1608 return err;
1609}
1610
1611/**
1612 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1613 * @adapter: board private structure
1614 *
1615 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1616 * interrupts from the kernel.
1617 **/
1618static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1619{
1620 struct net_device *netdev = adapter->netdev;
1621 irqreturn_t (*handler)(int, void *);
1622 int i, vector, q_vectors, err;
cb13fc20 1623 int ri=0, ti=0;
021230d4
AV		 1624
1625 /* Decrement for Other and TCP Timer vectors */
1626 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1627
1628 /* Map the Tx/Rx rings to the vectors we were allotted. */
1629 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1630 if (err)
1631 goto out;
1632
1633#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1634 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1635 &ixgbe_msix_clean_many)
021230d4 1636 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1637 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1638
1639 if(handler == &ixgbe_msix_clean_rx) {
1640 sprintf(adapter->name[vector], "%s-%s-%d",
1641 netdev->name, "rx", ri++);
1642 }
1643 else if(handler == &ixgbe_msix_clean_tx) {
1644 sprintf(adapter->name[vector], "%s-%s-%d",
1645 netdev->name, "tx", ti++);
1646 }
1647 else
1648 sprintf(adapter->name[vector], "%s-%s-%d",
1649 netdev->name, "TxRx", vector);
1650
021230d4 1651 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1652 handler, 0, adapter->name[vector],
7a921c93 1653 adapter->q_vector[vector]);
9a799d71
AK		 1654 if (err) {
1655 DPRINTK(PROBE, ERR,
b4617240
PW		 1656 "request_irq failed for MSIX interrupt "
1657 "Error: %d\n", err);
021230d4 1658 goto free_queue_irqs;
9a799d71 1659 }
9a799d71
AK		 1660 }
1661
021230d4
AV		 1662 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1663 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1664 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1665 if (err) {
1666 DPRINTK(PROBE, ERR,
1667 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1668 goto free_queue_irqs;
9a799d71
AK		 1669 }
1670
9a799d71
AK		 1671 return 0;
1672
021230d4
AV		 1673free_queue_irqs:
1674 for (i = vector - 1; i >= 0; i--)
1675 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1676 adapter->q_vector[i]);
021230d4
AV		 1677 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1678 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1679 kfree(adapter->msix_entries);
1680 adapter->msix_entries = NULL;
021230d4 1681out:
9a799d71
AK		 1682 return err;
1683}
1684
f494e8fa
AV		 1685static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1686{
7a921c93 1687 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1688 u8 current_itr;
1689 u32 new_itr = q_vector->eitr;
1690 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1691 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1692
30efa5a3 1693 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1694 q_vector->tx_itr,
1695 tx_ring->total_packets,
1696 tx_ring->total_bytes);
30efa5a3 1697 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1698 q_vector->rx_itr,
1699 rx_ring->total_packets,
1700 rx_ring->total_bytes);
f494e8fa 1701
30efa5a3 1702 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1703
1704 switch (current_itr) {
1705 /* counts and packets in update_itr are dependent on these numbers */
1706 case lowest_latency:
1707 new_itr = 100000;
1708 break;
1709 case low_latency:
1710 new_itr = 20000; /* aka hwitr = ~200 */
1711 break;
1712 case bulk_latency:
1713 new_itr = 8000;
1714 break;
1715 default:
1716 break;
1717 }
1718
1719 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1720 /* do an exponential smoothing */
1721 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1722
1723 /* save the algorithm value here, not the smoothed one */
1724 q_vector->eitr = new_itr;
fe49f04a
AD		 1725
1726 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1727 }
1728
1729 return;
1730}
1731
79aefa45
AD		 1732/**
1733 * ixgbe_irq_enable - Enable default interrupt generation settings
1734 * @adapter: board private structure
1735 **/
1736static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1737{
1738 u32 mask;
835462fc
NS		 1739
1740 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1741 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1742 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1743 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1744 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1745 mask |= IXGBE_EIMS_GPI_SDP1;
1746 mask |= IXGBE_EIMS_GPI_SDP2;
1747 }
c4cf55e5
PWJ		 1748 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1749 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1750 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1751
79aefa45 1752 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1753 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1754 IXGBE_WRITE_FLUSH(&adapter->hw);
1755}
021230d4 1756
9a799d71 1757/**
021230d4 1758 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1759 * @irq: interrupt number
1760 * @data: pointer to a network interface device structure
9a799d71
AK		 1761 **/
1762static irqreturn_t ixgbe_intr(int irq, void *data)
1763{
1764 struct net_device *netdev = data;
1765 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1766 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1767 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1768 u32 eicr;
1769
54037505
DS		 1770 /*
1771 * Workaround for silicon errata. Mask the interrupts
1772 * before the read of EICR.
1773 */
1774 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1775
021230d4
AV		 1776 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1777 * therefore no explict interrupt disable is necessary */
1778 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1779 if (!eicr) {
1780 /* shared interrupt alert!
1781 * make sure interrupts are enabled because the read will
1782 * have disabled interrupts due to EIAM */
1783 ixgbe_irq_enable(adapter);
9a799d71 1784 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1785 }
9a799d71 1786
cf8280ee
JB		 1787 if (eicr & IXGBE_EICR_LSC)
1788 ixgbe_check_lsc(adapter);
021230d4 1789
e8e26350
PW		 1790 if (hw->mac.type == ixgbe_mac_82599EB)
1791 ixgbe_check_sfp_event(adapter, eicr);
1792
0befdb3e
JB		 1793 ixgbe_check_fan_failure(adapter, eicr);
1794
7a921c93 1795 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1796 adapter->tx_ring[0].total_packets = 0;
1797 adapter->tx_ring[0].total_bytes = 0;
1798 adapter->rx_ring[0].total_packets = 0;
1799 adapter->rx_ring[0].total_bytes = 0;
021230d4 1800 /* would disable interrupts here but EIAM disabled it */
7a921c93 1801 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1802 }
1803
1804 return IRQ_HANDLED;
1805}
1806
021230d4
AV		 1807static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1808{
1809 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1810
1811 for (i = 0; i < q_vectors; i++) {
7a921c93 1812 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1813 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1814 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1815 q_vector->rxr_count = 0;
1816 q_vector->txr_count = 0;
1817 }
1818}
1819
9a799d71
AK		 1820/**
1821 * ixgbe_request_irq - initialize interrupts
1822 * @adapter: board private structure
1823 *
1824 * Attempts to configure interrupts using the best available
1825 * capabilities of the hardware and kernel.
1826 **/
021230d4 1827static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1828{
1829 struct net_device *netdev = adapter->netdev;
021230d4 1830 int err;
9a799d71 1831
021230d4
AV		 1832 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1833 err = ixgbe_request_msix_irqs(adapter);
1834 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1835 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1836 netdev->name, netdev);
021230d4
AV		 1837 } else {
1838 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1839 netdev->name, netdev);
9a799d71
AK		 1840 }
1841
9a799d71
AK		 1842 if (err)
1843 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1844
9a799d71
AK		 1845 return err;
1846}
1847
1848static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1849{
1850 struct net_device *netdev = adapter->netdev;
1851
1852 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1853 int i, q_vectors;
9a799d71 1854
021230d4
AV		 1855 q_vectors = adapter->num_msix_vectors;
1856
1857 i = q_vectors - 1;
9a799d71 1858 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1859
021230d4
AV		 1860 i--;
1861 for (; i >= 0; i--) {
1862 free_irq(adapter->msix_entries[i].vector,
7a921c93 1863 adapter->q_vector[i]);
021230d4
AV		 1864 }
1865
1866 ixgbe_reset_q_vectors(adapter);
1867 } else {
1868 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1869 }
1870}
1871
22d5a71b
JB		 1872/**
1873 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1874 * @adapter: board private structure
1875 **/
1876static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1877{
835462fc
NS		 1878 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1879 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1880 } else {
1881 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1883 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1884 }
1885 IXGBE_WRITE_FLUSH(&adapter->hw);
1886 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1887 int i;
1888 for (i = 0; i < adapter->num_msix_vectors; i++)
1889 synchronize_irq(adapter->msix_entries[i].vector);
1890 } else {
1891 synchronize_irq(adapter->pdev->irq);
1892 }
1893}
1894
9a799d71
AK		 1895/**
1896 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1897 *
1898 **/
1899static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1900{
9a799d71
AK		 1901 struct ixgbe_hw *hw = &adapter->hw;
1902
021230d4 1903 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 1904 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 1905
e8e26350
PW		 1906 ixgbe_set_ivar(adapter, 0, 0, 0);
1907 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1908
1909 map_vector_to_rxq(adapter, 0, 0);
1910 map_vector_to_txq(adapter, 0, 0);
1911
1912 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1913}
1914
1915/**
3a581073 1916 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1917 * @adapter: board private structure
1918 *
1919 * Configure the Tx unit of the MAC after a reset.
1920 **/
1921static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1922{
12207e49 1923 u64 tdba;
9a799d71 1924 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1925 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1926
1927 /* Setup the HW Tx Head and Tail descriptor pointers */
1928 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1929 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1930 j = ring->reg_idx;
1931 tdba = ring->dma;
1932 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1933 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1934 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1935 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1936 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1937 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1938 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1939 adapter->tx_ring[i].head = IXGBE_TDH(j);
1940 adapter->tx_ring[i].tail = IXGBE_TDT(j);
84f62d4b
PWJ		 1941 /*
1942 * Disable Tx Head Writeback RO bit, since this hoses
021230d4
AV		 1943 * bookkeeping if things aren't delivered in order.
1944 */
84f62d4b
PWJ		 1945 switch (hw->mac.type) {
1946 case ixgbe_mac_82598EB:
1947 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1948 break;
1949 case ixgbe_mac_82599EB:
1950 default:
1951 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1952 break;
1953 }
021230d4 1954 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
84f62d4b
PWJ		 1955 switch (hw->mac.type) {
1956 case ixgbe_mac_82598EB:
1957 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1958 break;
1959 case ixgbe_mac_82599EB:
1960 default:
1961 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1962 break;
1963 }
9a799d71 1964 }
ee5f784a 1965
e8e26350 1966 if (hw->mac.type == ixgbe_mac_82599EB) {
ee5f784a
DS		 1967 u32 rttdcs;
1968
1969 /* disable the arbiter while setting MTQC */
1970 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
1971 rttdcs |= IXGBE_RTTDCS_ARBDIS;
1972 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1973
e8e26350
PW		 1974 /* We enable 8 traffic classes, DCB only */
1975 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1976 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1977 IXGBE_MTQC_8TC_8TQ));
ee5f784a
DS		 1978 else
1979 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1980
1981 /* re-eable the arbiter */
1982 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
1983 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
e8e26350 1984 }
9a799d71
AK		 1985}
1986
e8e26350 1987#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 1988
a6616b42
YZ		 1989static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1990 struct ixgbe_ring *rx_ring)
cc41ac7c 1991{
cc41ac7c 1992 u32 srrctl;
a6616b42 1993 int index;
0cefafad 1994 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 1995
a6616b42
YZ		 1996 index = rx_ring->reg_idx;
1997 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1998 unsigned long mask;
0cefafad 1999 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2000 index = index & mask;
cc41ac7c 2001 }
cc41ac7c
JB		 2002 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2003
2004 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2005 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2006
afafd5b0
AD		 2007 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2008 IXGBE_SRRCTL_BSIZEHDR_MASK;
2009
6e455b89 2010 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2011#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2012 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2013#else
2014 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2015#endif
cc41ac7c 2016 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2017 } else {
afafd5b0
AD		 2018 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2019 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2020 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2021 }
e8e26350 2022
cc41ac7c
JB		 2023 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2024}
9a799d71 2025
0cefafad
JB		 2026static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2027{
2028 u32 mrqc = 0;
2029 int mask;
2030
2031 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2032 return mrqc;
2033
2034 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2035#ifdef CONFIG_IXGBE_DCB
2036 | IXGBE_FLAG_DCB_ENABLED
2037#endif
2038 );
2039
2040 switch (mask) {
2041 case (IXGBE_FLAG_RSS_ENABLED):
2042 mrqc = IXGBE_MRQC_RSSEN;
2043 break;
2044#ifdef CONFIG_IXGBE_DCB
2045 case (IXGBE_FLAG_DCB_ENABLED):
2046 mrqc = IXGBE_MRQC_RT8TCEN;
2047 break;
2048#endif /* CONFIG_IXGBE_DCB */
2049 default:
2050 break;
2051 }
2052
2053 return mrqc;
2054}
2055
bb5a9ad2
NS		 2056/**
2057 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2058 * @adapter: address of board private structure
2059 * @index: index of ring to set
2060 * @rx_buf_len: rx buffer length
2061 **/
2062static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index,
2063 int rx_buf_len)
2064{
2065 struct ixgbe_ring *rx_ring;
2066 struct ixgbe_hw *hw = &adapter->hw;
2067 int j;
2068 u32 rscctrl;
2069
2070 rx_ring = &adapter->rx_ring[index];
2071 j = rx_ring->reg_idx;
2072 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2073 rscctrl |= IXGBE_RSCCTL_RSCEN;
2074 /*
2075 * we must limit the number of descriptors so that the
2076 * total size of max desc * buf_len is not greater
2077 * than 65535
2078 */
2079 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2080#if (MAX_SKB_FRAGS > 16)
2081 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2082#elif (MAX_SKB_FRAGS > 8)
2083 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2084#elif (MAX_SKB_FRAGS > 4)
2085 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2086#else
2087 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2088#endif
2089 } else {
2090 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2091 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2092 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2093 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2094 else
2095 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2096 }
2097 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2098}
2099
9a799d71 2100/**
3a581073 2101 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 2102 * @adapter: board private structure
2103 *
2104 * Configure the Rx unit of the MAC after a reset.
2105 **/
2106static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2107{
2108 u64 rdba;
2109 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 2110 struct ixgbe_ring *rx_ring;
9a799d71
AK		 2111 struct net_device *netdev = adapter->netdev;
2112 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2113 int i, j;
9a799d71 2114 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 2115 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2116 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2117 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 2118 u32 fctrl, hlreg0;
509ee935 2119 u32 reta = 0, mrqc = 0;
cc41ac7c 2120 u32 rdrxctl;
7c6e0a43 2121 int rx_buf_len;
9a799d71
AK		 2122
2123 /* Decide whether to use packet split mode or not */
762f4c57 2124 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2125
2126 /* Set the RX buffer length according to the mode */
2127 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2128 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2129 if (hw->mac.type == ixgbe_mac_82599EB) {
2130 /* PSRTYPE must be initialized in 82599 */
2131 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2132 IXGBE_PSRTYPE_UDPHDR |
2133 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2134 IXGBE_PSRTYPE_IPV6HDR |
2135 IXGBE_PSRTYPE_L2HDR;
e8e26350
PW		 2136 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2137 }
9a799d71 2138 } else {
0c19d6af 2139 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2140 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2141 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2142 else
7c6e0a43 2143 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2144 }
2145
2146 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2147 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2148 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2149 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2150 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2151
2152 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2153 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2154 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2155 else
2156 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2157#ifdef IXGBE_FCOE
f34c5c82 2158 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2159 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2160#endif
9a799d71
AK		 2161 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2162
9a799d71
AK		 2163 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2164 /* disable receives while setting up the descriptors */
2165 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2166 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2167
0cefafad
JB		 2168 /*
2169 * Setup the HW Rx Head and Tail Descriptor Pointers and
2170 * the Base and Length of the Rx Descriptor Ring
2171 */
9a799d71 2172 for (i = 0; i < adapter->num_rx_queues; i++) {
a6616b42
YZ		 2173 rx_ring = &adapter->rx_ring[i];
2174 rdba = rx_ring->dma;
2175 j = rx_ring->reg_idx;
284901a9 2176 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2177 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2178 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2179 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2180 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2181 rx_ring->head = IXGBE_RDH(j);
2182 rx_ring->tail = IXGBE_RDT(j);
2183 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2184
6e455b89
YZ		 2185 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2186 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2187 else
2188 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2189
63f39bd1 2190#ifdef IXGBE_FCOE
f34c5c82 2191 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2192 struct ixgbe_ring_feature *f;
2193 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2194 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2195 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2196 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2197 rx_ring->rx_buf_len =
2198 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2199 }
63f39bd1
YZ		 2200 }
2201
2202#endif /* IXGBE_FCOE */
a6616b42 2203 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2204 }
2205
e8e26350
PW		 2206 if (hw->mac.type == ixgbe_mac_82598EB) {
2207 /*
2208 * For VMDq support of different descriptor types or
2209 * buffer sizes through the use of multiple SRRCTL
2210 * registers, RDRXCTL.MVMEN must be set to 1
2211 *
2212 * also, the manual doesn't mention it clearly but DCA hints
2213 * will only use queue 0's tags unless this bit is set. Side
2214 * effects of setting this bit are only that SRRCTL must be
2215 * fully programmed [0..15]
2216 */
2a41ff81
JB		 2217 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2218 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2219 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2220 }
177db6ff 2221
e8e26350 2222 /* Program MRQC for the distribution of queues */
0cefafad 2223 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2224
021230d4 2225 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2226 /* Fill out redirection table */
021230d4
AV		 2227 for (i = 0, j = 0; i < 128; i++, j++) {
2228 if (j == adapter->ring_feature[RING_F_RSS].indices)
2229 j = 0;
2230 /* reta = 4-byte sliding window of
2231 * 0x00..(indices-1)(indices-1)00..etc. */
2232 reta = (reta << 8) | (j * 0x11);
2233 if ((i & 3) == 3)
2234 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2235 }
2236
2237 /* Fill out hash function seeds */
2238 for (i = 0; i < 10; i++)
7c6e0a43 2239 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2240
2a41ff81
JB		 2241 if (hw->mac.type == ixgbe_mac_82598EB)
2242 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2243 /* Perform hash on these packet types */
2a41ff81
JB		 2244 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2245 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2246 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2247 | IXGBE_MRQC_RSS_FIELD_IPV6
2248 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2249 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2250 }
2a41ff81 2251 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2252
021230d4
AV		 2253 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2254
2255 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2256 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2257 /* Disable indicating checksum in descriptor, enables
2258 * RSS hash */
9a799d71 2259 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2260 }
021230d4
AV		 2261 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2262 /* Enable IPv4 payload checksum for UDP fragments
2263 * if PCSD is not set */
2264 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2265 }
2266
2267 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2268
2269 if (hw->mac.type == ixgbe_mac_82599EB) {
2270 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2271 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2272 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2273 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2274 }
f8212f97 2275
0c19d6af 2276 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2277 /* Enable 82599 HW-RSC */
bb5a9ad2
NS		 2278 for (i = 0; i < adapter->num_rx_queues; i++)
2279 ixgbe_configure_rscctl(adapter, i, rx_buf_len);
2280
f8212f97
AD		 2281 /* Disable RSC for ACK packets */
2282 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2283 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2284 }
9a799d71
AK		 2285}
2286
068c89b0
DS		 2287static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2288{
2289 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2290 struct ixgbe_hw *hw = &adapter->hw;
2291
2292 /* add VID to filter table */
2293 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2294}
2295
2296static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2297{
2298 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2299 struct ixgbe_hw *hw = &adapter->hw;
2300
2301 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2302 ixgbe_irq_disable(adapter);
2303
2304 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2305
2306 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2307 ixgbe_irq_enable(adapter);
2308
2309 /* remove VID from filter table */
2310 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2311}
2312
9a799d71 2313static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2314 struct vlan_group *grp)
9a799d71
AK		 2315{
2316 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2317 u32 ctrl;
e8e26350 2318 int i, j;
9a799d71 2319
d4f80882
AV		 2320 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2321 ixgbe_irq_disable(adapter);
9a799d71
AK		 2322 adapter->vlgrp = grp;
2323
2f90b865
AD		 2324 /*
2325 * For a DCB driver, always enable VLAN tag stripping so we can
2326 * still receive traffic from a DCB-enabled host even if we're
2327 * not in DCB mode.
2328 */
2329 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 2330 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2331 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2332 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2333 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2334 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2335 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 2336 /* enable VLAN tag insert/strip */
2337 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 2338 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2339 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 2340 for (i = 0; i < adapter->num_rx_queues; i++) {
2341 j = adapter->rx_ring[i].reg_idx;
2342 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2343 ctrl |= IXGBE_RXDCTL_VME;
2344 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2345 }
9a799d71 2346 }
e8e26350 2347 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2348
d4f80882
AV		 2349 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2350 ixgbe_irq_enable(adapter);
9a799d71
AK		 2351}
2352
9a799d71
AK		 2353static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2354{
2355 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2356
2357 if (adapter->vlgrp) {
2358 u16 vid;
2359 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2360 if (!vlan_group_get_device(adapter->vlgrp, vid))
2361 continue;
2362 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2363 }
2364 }
2365}
2366
2c5645cf
CL		 2367static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2368{
2369 struct dev_mc_list *mc_ptr;
2370 u8 *addr = *mc_addr_ptr;
2371 *vmdq = 0;
2372
2373 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2374 if (mc_ptr->next)
2375 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2376 else
2377 *mc_addr_ptr = NULL;
2378
2379 return addr;
2380}
2381
9a799d71 2382/**
2c5645cf 2383 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2384 * @netdev: network interface device structure
2385 *
2c5645cf
CL		 2386 * The set_rx_method entry point is called whenever the unicast/multicast
2387 * address list or the network interface flags are updated. This routine is
2388 * responsible for configuring the hardware for proper unicast, multicast and
2389 * promiscuous mode.
9a799d71 2390 **/
2c5645cf 2391static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2392{
2393 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2394 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2395 u32 fctrl, vlnctrl;
2c5645cf
CL		 2396 u8 *addr_list = NULL;
2397 int addr_count = 0;
9a799d71
AK		 2398
2399 /* Check for Promiscuous and All Multicast modes */
2400
2401 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2402 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2403
2404 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2405 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2406 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2407 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2408 } else {
746b9f02
PM		 2409 if (netdev->flags & IFF_ALLMULTI) {
2410 fctrl |= IXGBE_FCTRL_MPE;
2411 fctrl &= ~IXGBE_FCTRL_UPE;
2412 } else {
2413 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2414 }
3d01625a 2415 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2416 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2417 }
2418
2419 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2420 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2421
2c5645cf 2422 /* reprogram secondary unicast list */
31278e71 2423 hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
9a799d71 2424
2c5645cf
CL		 2425 /* reprogram multicast list */
2426 addr_count = netdev->mc_count;
2427 if (addr_count)
2428 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2429 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2430 ixgbe_addr_list_itr);
9a799d71
AK		 2431}
2432
021230d4
AV		 2433static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2434{
2435 int q_idx;
2436 struct ixgbe_q_vector *q_vector;
2437 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2438
2439 /* legacy and MSI only use one vector */
2440 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2441 q_vectors = 1;
2442
2443 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2444 struct napi_struct *napi;
7a921c93 2445 q_vector = adapter->q_vector[q_idx];
f0848276 2446 napi = &q_vector->napi;
91281fd3
AD		 2447 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2448 if (!q_vector->rxr_count || !q_vector->txr_count) {
2449 if (q_vector->txr_count == 1)
2450 napi->poll = &ixgbe_clean_txonly;
2451 else if (q_vector->rxr_count == 1)
2452 napi->poll = &ixgbe_clean_rxonly;
2453 }
2454 }
f0848276
JB		 2455
2456 napi_enable(napi);
021230d4
AV		 2457 }
2458}
2459
2460static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2461{
2462 int q_idx;
2463 struct ixgbe_q_vector *q_vector;
2464 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2465
2466 /* legacy and MSI only use one vector */
2467 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2468 q_vectors = 1;
2469
2470 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2471 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2472 napi_disable(&q_vector->napi);
2473 }
2474}
2475
7a6b6f51 2476#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2477/*
2478 * ixgbe_configure_dcb - Configure DCB hardware
2479 * @adapter: ixgbe adapter struct
2480 *
2481 * This is called by the driver on open to configure the DCB hardware.
2482 * This is also called by the gennetlink interface when reconfiguring
2483 * the DCB state.
2484 */
2485static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2486{
2487 struct ixgbe_hw *hw = &adapter->hw;
2488 u32 txdctl, vlnctrl;
2489 int i, j;
2490
2491 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2492 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2493 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2494
2495 /* reconfigure the hardware */
2496 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2497
2498 for (i = 0; i < adapter->num_tx_queues; i++) {
2499 j = adapter->tx_ring[i].reg_idx;
2500 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2501 /* PThresh workaround for Tx hang with DFP enabled. */
2502 txdctl |= 32;
2503 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2504 }
2505 /* Enable VLAN tag insert/strip */
2506 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2507 if (hw->mac.type == ixgbe_mac_82598EB) {
2508 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2509 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2510 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2511 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2512 vlnctrl |= IXGBE_VLNCTRL_VFE;
2513 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2514 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2515 for (i = 0; i < adapter->num_rx_queues; i++) {
2516 j = adapter->rx_ring[i].reg_idx;
2517 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2518 vlnctrl |= IXGBE_RXDCTL_VME;
2519 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2520 }
2521 }
2f90b865
AD		 2522 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2523}
2524
2525#endif
9a799d71
AK		 2526static void ixgbe_configure(struct ixgbe_adapter *adapter)
2527{
2528 struct net_device *netdev = adapter->netdev;
c4cf55e5 2529 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2530 int i;
2531
2c5645cf 2532 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2533
2534 ixgbe_restore_vlan(adapter);
7a6b6f51 2535#ifdef CONFIG_IXGBE_DCB
2f90b865 2536 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
b352e40d
YZ		 2537 if (hw->mac.type == ixgbe_mac_82598EB)
2538 netif_set_gso_max_size(netdev, 32768);
2539 else
2540 netif_set_gso_max_size(netdev, 65536);
2f90b865
AD		 2541 ixgbe_configure_dcb(adapter);
2542 } else {
2543 netif_set_gso_max_size(netdev, 65536);
2544 }
2545#else
2546 netif_set_gso_max_size(netdev, 65536);
2547#endif
9a799d71 2548
eacd73f7
YZ		 2549#ifdef IXGBE_FCOE
2550 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2551 ixgbe_configure_fcoe(adapter);
2552
2553#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2554 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2555 for (i = 0; i < adapter->num_tx_queues; i++)
2556 adapter->tx_ring[i].atr_sample_rate =
2557 adapter->atr_sample_rate;
2558 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2559 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2560 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2561 }
2562
9a799d71
AK		 2563 ixgbe_configure_tx(adapter);
2564 ixgbe_configure_rx(adapter);
2565 for (i = 0; i < adapter->num_rx_queues; i++)
2566 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2567 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2568}
2569
e8e26350
PW		 2570static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2571{
2572 switch (hw->phy.type) {
2573 case ixgbe_phy_sfp_avago:
2574 case ixgbe_phy_sfp_ftl:
2575 case ixgbe_phy_sfp_intel:
2576 case ixgbe_phy_sfp_unknown:
2577 case ixgbe_phy_tw_tyco:
2578 case ixgbe_phy_tw_unknown:
2579 return true;
2580 default:
2581 return false;
2582 }
2583}
2584
0ecc061d 2585/**
e8e26350
PW		 2586 * ixgbe_sfp_link_config - set up SFP+ link
2587 * @adapter: pointer to private adapter struct
2588 **/
2589static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2590{
2591 struct ixgbe_hw *hw = &adapter->hw;
2592
2593 if (hw->phy.multispeed_fiber) {
2594 /*
2595 * In multispeed fiber setups, the device may not have
2596 * had a physical connection when the driver loaded.
2597 * If that's the case, the initial link configuration
2598 * couldn't get the MAC into 10G or 1G mode, so we'll
2599 * never have a link status change interrupt fire.
2600 * We need to try and force an autonegotiation
2601 * session, then bring up link.
2602 */
2603 hw->mac.ops.setup_sfp(hw);
2604 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2605 schedule_work(&adapter->multispeed_fiber_task);
2606 } else {
2607 /*
2608 * Direct Attach Cu and non-multispeed fiber modules
2609 * still need to be configured properly prior to
2610 * attempting link.
2611 */
2612 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2613 schedule_work(&adapter->sfp_config_module_task);
2614 }
2615}
2616
2617/**
2618 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2619 * @hw: pointer to private hardware struct
2620 *
2621 * Returns 0 on success, negative on failure
2622 **/
e8e26350 2623static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2624{
2625 u32 autoneg;
8620a103 2626 bool negotiation, link_up = false;
0ecc061d
PWJ		 2627 u32 ret = IXGBE_ERR_LINK_SETUP;
2628
2629 if (hw->mac.ops.check_link)
2630 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2631
2632 if (ret)
2633 goto link_cfg_out;
2634
2635 if (hw->mac.ops.get_link_capabilities)
8620a103 2636 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 2637 if (ret)
2638 goto link_cfg_out;
2639
8620a103
MC		 2640 if (hw->mac.ops.setup_link)
2641 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 2642link_cfg_out:
2643 return ret;
2644}
2645
e8e26350
PW		 2646#define IXGBE_MAX_RX_DESC_POLL 10
2647static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2648 int rxr)
2649{
2650 int j = adapter->rx_ring[rxr].reg_idx;
2651 int k;
2652
2653 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2654 if (IXGBE_READ_REG(&adapter->hw,
2655 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2656 break;
2657 else
2658 msleep(1);
2659 }
2660 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2661 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2662 "not set within the polling period\n", rxr);
2663 }
2664 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2665 (adapter->rx_ring[rxr].count - 1));
2666}
2667
9a799d71
AK		 2668static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2669{
2670 struct net_device *netdev = adapter->netdev;
9a799d71 2671 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2672 int i, j = 0;
e8e26350 2673 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2674 int err;
9a799d71 2675 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2676 u32 txdctl, rxdctl, mhadd;
e8e26350 2677 u32 dmatxctl;
021230d4 2678 u32 gpie;
9a799d71 2679
5eba3699
AV		 2680 ixgbe_get_hw_control(adapter);
2681
021230d4
AV		 2682 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2683 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2684 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2685 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2686 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2687 } else {
2688 /* MSI only */
021230d4 2689 gpie = 0;
9a799d71 2690 }
021230d4
AV		 2691 /* XXX: to interrupt immediately for EICS writes, enable this */
2692 /* gpie |= IXGBE_GPIE_EIMEN; */
2693 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2694 }
2695
021230d4
AV		 2696 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2697 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2698 * specifically only auto mask tx and rx interrupts */
2699 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2700 }
9a799d71 2701
0befdb3e
JB		 2702 /* Enable fan failure interrupt if media type is copper */
2703 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2704 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2705 gpie |= IXGBE_SDP1_GPIEN;
2706 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2707 }
2708
e8e26350
PW		 2709 if (hw->mac.type == ixgbe_mac_82599EB) {
2710 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2711 gpie |= IXGBE_SDP1_GPIEN;
2712 gpie |= IXGBE_SDP2_GPIEN;
2713 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2714 }
2715
63f39bd1
YZ		 2716#ifdef IXGBE_FCOE
2717 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 2718 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 2719 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2720 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2721
2722#endif /* IXGBE_FCOE */
021230d4 2723 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2724 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2725 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2726 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2727
2728 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2729 }
2730
2731 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2732 j = adapter->tx_ring[i].reg_idx;
2733 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2734 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2735 txdctl |= (8 << 16);
e8e26350
PW		 2736 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2737 }
2738
2739 if (hw->mac.type == ixgbe_mac_82599EB) {
2740 /* DMATXCTL.EN must be set after all Tx queue config is done */
2741 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2742 dmatxctl |= IXGBE_DMATXCTL_TE;
2743 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2744 }
2745 for (i = 0; i < adapter->num_tx_queues; i++) {
2746 j = adapter->tx_ring[i].reg_idx;
2747 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2748 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2749 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2750 }
2751
e8e26350 2752 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2753 j = adapter->rx_ring[i].reg_idx;
2754 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2755 /* enable PTHRESH=32 descriptors (half the internal cache)
2756 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2757 * this also removes a pesky rx_no_buffer_count increment */
2758 rxdctl |= 0x0020;
9a799d71 2759 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2760 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2761 if (hw->mac.type == ixgbe_mac_82599EB)
2762 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2763 }
2764 /* enable all receives */
2765 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2766 if (hw->mac.type == ixgbe_mac_82598EB)
2767 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2768 else
2769 rxdctl |= IXGBE_RXCTRL_RXEN;
2770 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2771
2772 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2773 ixgbe_configure_msix(adapter);
2774 else
2775 ixgbe_configure_msi_and_legacy(adapter);
2776
2777 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2778 ixgbe_napi_enable_all(adapter);
2779
2780 /* clear any pending interrupts, may auto mask */
2781 IXGBE_READ_REG(hw, IXGBE_EICR);
2782
9a799d71
AK		 2783 ixgbe_irq_enable(adapter);
2784
bf069c97
DS		 2785 /*
2786 * If this adapter has a fan, check to see if we had a failure
2787 * before we enabled the interrupt.
2788 */
2789 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2790 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2791 if (esdp & IXGBE_ESDP_SDP1)
2792 DPRINTK(DRV, CRIT,
2793 "Fan has stopped, replace the adapter\n");
2794 }
2795
e8e26350
PW		 2796 /*
2797 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 2798 * arrived before interrupts were enabled but after probe. Such
2799 * devices wouldn't have their type identified yet. We need to
2800 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 2801 * If we're not hot-pluggable SFP+, we just need to configure link
2802 * and bring it up.
2803 */
19343de2
DS		 2804 if (hw->phy.type == ixgbe_phy_unknown) {
2805 err = hw->phy.ops.identify(hw);
2806 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 2807 /*
2808 * Take the device down and schedule the sfp tasklet
2809 * which will unregister_netdev and log it.
2810 */
19343de2 2811 ixgbe_down(adapter);
5da43c1a 2812 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 2813 return err;
2814 }
e8e26350
PW		 2815 }
2816
2817 if (ixgbe_is_sfp(hw)) {
2818 ixgbe_sfp_link_config(adapter);
2819 } else {
2820 err = ixgbe_non_sfp_link_config(hw);
2821 if (err)
2822 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2823 }
0ecc061d 2824
c4cf55e5
PWJ		 2825 for (i = 0; i < adapter->num_tx_queues; i++)
2826 set_bit(__IXGBE_FDIR_INIT_DONE,
2827 &(adapter->tx_ring[i].reinit_state));
2828
1da100bb
PWJ		 2829 /* enable transmits */
2830 netif_tx_start_all_queues(netdev);
2831
9a799d71
AK		 2832 /* bring the link up in the watchdog, this could race with our first
2833 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2834 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2835 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2836 mod_timer(&adapter->watchdog_timer, jiffies);
2837 return 0;
2838}
2839
d4f80882
AV		 2840void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2841{
2842 WARN_ON(in_interrupt());
2843 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2844 msleep(1);
2845 ixgbe_down(adapter);
2846 ixgbe_up(adapter);
2847 clear_bit(__IXGBE_RESETTING, &adapter->state);
2848}
2849
9a799d71
AK		 2850int ixgbe_up(struct ixgbe_adapter *adapter)
2851{
2852 /* hardware has been reset, we need to reload some things */
2853 ixgbe_configure(adapter);
2854
2855 return ixgbe_up_complete(adapter);
2856}
2857
2858void ixgbe_reset(struct ixgbe_adapter *adapter)
2859{
c44ade9e 2860 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 2861 int err;
2862
2863 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 2864 switch (err) {
2865 case 0:
2866 case IXGBE_ERR_SFP_NOT_PRESENT:
2867 break;
2868 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2869 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2870 break;
794caeb2
PWJ		 2871 case IXGBE_ERR_EEPROM_VERSION:
2872 /* We are running on a pre-production device, log a warning */
2873 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2874 "adapter/LOM. Please be aware there may be issues "
2875 "associated with your hardware. If you are "
2876 "experiencing problems please contact your Intel or "
2877 "hardware representative who provided you with this "
2878 "hardware.\n");
2879 break;
da4dd0f7
PWJ		 2880 default:
2881 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2882 }
9a799d71
AK		 2883
2884 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2885 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2886}
2887
9a799d71
AK		 2888/**
2889 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2890 * @adapter: board private structure
2891 * @rx_ring: ring to free buffers from
2892 **/
2893static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2894 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2895{
2896 struct pci_dev *pdev = adapter->pdev;
2897 unsigned long size;
2898 unsigned int i;
2899
2900 /* Free all the Rx ring sk_buffs */
2901
2902 for (i = 0; i < rx_ring->count; i++) {
2903 struct ixgbe_rx_buffer *rx_buffer_info;
2904
2905 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2906 if (rx_buffer_info->dma) {
2907 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2908 rx_ring->rx_buf_len,
2909 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2910 rx_buffer_info->dma = 0;
2911 }
2912 if (rx_buffer_info->skb) {
f8212f97 2913 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2914 rx_buffer_info->skb = NULL;
f8212f97
AD		 2915 do {
2916 struct sk_buff *this = skb;
2917 skb = skb->prev;
2918 dev_kfree_skb(this);
2919 } while (skb);
9a799d71
AK		 2920 }
2921 if (!rx_buffer_info->page)
2922 continue;
4f57ca6e
JB		 2923 if (rx_buffer_info->page_dma) {
2924 pci_unmap_page(pdev, rx_buffer_info->page_dma,
2925 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2926 rx_buffer_info->page_dma = 0;
2927 }
9a799d71
AK		 2928 put_page(rx_buffer_info->page);
2929 rx_buffer_info->page = NULL;
762f4c57 2930 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2931 }
2932
2933 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2934 memset(rx_ring->rx_buffer_info, 0, size);
2935
2936 /* Zero out the descriptor ring */
2937 memset(rx_ring->desc, 0, rx_ring->size);
2938
2939 rx_ring->next_to_clean = 0;
2940 rx_ring->next_to_use = 0;
2941
9891ca7c
JB		 2942 if (rx_ring->head)
2943 writel(0, adapter->hw.hw_addr + rx_ring->head);
2944 if (rx_ring->tail)
2945 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2946}
2947
2948/**
2949 * ixgbe_clean_tx_ring - Free Tx Buffers
2950 * @adapter: board private structure
2951 * @tx_ring: ring to be cleaned
2952 **/
2953static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2954 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2955{
2956 struct ixgbe_tx_buffer *tx_buffer_info;
2957 unsigned long size;
2958 unsigned int i;
2959
2960 /* Free all the Tx ring sk_buffs */
2961
2962 for (i = 0; i < tx_ring->count; i++) {
2963 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2964 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2965 }
2966
2967 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2968 memset(tx_ring->tx_buffer_info, 0, size);
2969
2970 /* Zero out the descriptor ring */
2971 memset(tx_ring->desc, 0, tx_ring->size);
2972
2973 tx_ring->next_to_use = 0;
2974 tx_ring->next_to_clean = 0;
2975
9891ca7c
JB		 2976 if (tx_ring->head)
2977 writel(0, adapter->hw.hw_addr + tx_ring->head);
2978 if (tx_ring->tail)
2979 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2980}
2981
2982/**
021230d4 2983 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2984 * @adapter: board private structure
2985 **/
021230d4 2986static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2987{
2988 int i;
2989
021230d4
AV		 2990 for (i = 0; i < adapter->num_rx_queues; i++)
2991 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2992}
2993
2994/**
021230d4 2995 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2996 * @adapter: board private structure
2997 **/
021230d4 2998static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2999{
3000 int i;
3001
021230d4
AV		 3002 for (i = 0; i < adapter->num_tx_queues; i++)
3003 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 3004}
3005
3006void ixgbe_down(struct ixgbe_adapter *adapter)
3007{
3008 struct net_device *netdev = adapter->netdev;
7f821875 3009 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3010 u32 rxctrl;
7f821875
JB		 3011 u32 txdctl;
3012 int i, j;
9a799d71
AK		 3013
3014 /* signal that we are down to the interrupt handler */
3015 set_bit(__IXGBE_DOWN, &adapter->state);
3016
3017 /* disable receives */
7f821875
JB		 3018 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3019 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 3020
3021 netif_tx_disable(netdev);
3022
7f821875 3023 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3024 msleep(10);
3025
7f821875
JB		 3026 netif_tx_stop_all_queues(netdev);
3027
9a799d71
AK		 3028 ixgbe_irq_disable(adapter);
3029
021230d4 3030 ixgbe_napi_disable_all(adapter);
7f821875 3031
0a1f87cb
DS		 3032 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3033 del_timer_sync(&adapter->sfp_timer);
9a799d71 3034 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3035 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3036
c4cf55e5
PWJ		 3037 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3038 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3039 cancel_work_sync(&adapter->fdir_reinit_task);
3040
7f821875
JB		 3041 /* disable transmits in the hardware now that interrupts are off */
3042 for (i = 0; i < adapter->num_tx_queues; i++) {
3043 j = adapter->tx_ring[i].reg_idx;
3044 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3045 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3046 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3047 }
88512539
PW		 3048 /* Disable the Tx DMA engine on 82599 */
3049 if (hw->mac.type == ixgbe_mac_82599EB)
3050 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3051 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3052 ~IXGBE_DMATXCTL_TE));
7f821875 3053
9a799d71 3054 netif_carrier_off(netdev);
9a799d71 3055
6f4a0e45
PL		 3056 if (!pci_channel_offline(adapter->pdev))
3057 ixgbe_reset(adapter);
9a799d71
AK		 3058 ixgbe_clean_all_tx_rings(adapter);
3059 ixgbe_clean_all_rx_rings(adapter);
3060
5dd2d332 3061#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3062 /* since we reset the hardware DCA settings were cleared */
e35ec126 3063 ixgbe_setup_dca(adapter);
96b0e0f6 3064#endif
9a799d71
AK		 3065}
3066
9a799d71 3067/**
021230d4
AV		 3068 * ixgbe_poll - NAPI Rx polling callback
3069 * @napi: structure for representing this polling device
3070 * @budget: how many packets driver is allowed to clean
3071 *
3072 * This function is used for legacy and MSI, NAPI mode
9a799d71 3073 **/
021230d4 3074static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3075{
9a1a69ad
JB		 3076 struct ixgbe_q_vector *q_vector =
3077 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3078 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3079 int tx_clean_complete, work_done = 0;
9a799d71 3080
5dd2d332 3081#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 3082 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3083 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3084 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3085 }
3086#endif
3087
fe49f04a 3088 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
78b6f4ce 3089 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 3090
9a1a69ad 3091 if (!tx_clean_complete)
d2c7ddd6
DM		 3092 work_done = budget;
3093
53e52c72
DM		 3094 /* If budget not fully consumed, exit the polling mode */
3095 if (work_done < budget) {
288379f0 3096 napi_complete(napi);
f7554a2b 3097 if (adapter->rx_itr_setting & 1)
f494e8fa 3098 ixgbe_set_itr(adapter);
d4f80882 3099 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3100 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3101 }
9a799d71
AK		 3102 return work_done;
3103}
3104
3105/**
3106 * ixgbe_tx_timeout - Respond to a Tx Hang
3107 * @netdev: network interface device structure
3108 **/
3109static void ixgbe_tx_timeout(struct net_device *netdev)
3110{
3111 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3112
3113 /* Do the reset outside of interrupt context */
3114 schedule_work(&adapter->reset_task);
3115}
3116
3117static void ixgbe_reset_task(struct work_struct *work)
3118{
3119 struct ixgbe_adapter *adapter;
3120 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3121
2f90b865
AD		 3122 /* If we're already down or resetting, just bail */
3123 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3124 test_bit(__IXGBE_RESETTING, &adapter->state))
3125 return;
3126
9a799d71
AK		 3127 adapter->tx_timeout_count++;
3128
d4f80882 3129 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3130}
3131
bc97114d
PWJ		 3132#ifdef CONFIG_IXGBE_DCB
3133static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3134{
bc97114d 3135 bool ret = false;
0cefafad 3136 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3137
0cefafad
JB		 3138 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3139 return ret;
3140
3141 f->mask = 0x7 << 3;
3142 adapter->num_rx_queues = f->indices;
3143 adapter->num_tx_queues = f->indices;
3144 ret = true;
2f90b865 3145
bc97114d
PWJ		 3146 return ret;
3147}
3148#endif
3149
4df10466
JB		 3150/**
3151 * ixgbe_set_rss_queues: Allocate queues for RSS
3152 * @adapter: board private structure to initialize
3153 *
3154 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3155 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3156 *
3157 **/
bc97114d
PWJ		 3158static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3159{
3160 bool ret = false;
0cefafad 3161 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3162
3163 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3164 f->mask = 0xF;
3165 adapter->num_rx_queues = f->indices;
3166 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3167 ret = true;
3168 } else {
bc97114d 3169 ret = false;
b9804972
JB		 3170 }
3171
bc97114d
PWJ		 3172 return ret;
3173}
3174
c4cf55e5
PWJ		 3175/**
3176 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3177 * @adapter: board private structure to initialize
3178 *
3179 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3180 * to the original CPU that initiated the Tx session. This runs in addition
3181 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3182 * Rx load across CPUs using RSS.
3183 *
3184 **/
3185static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3186{
3187 bool ret = false;
3188 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3189
3190 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3191 f_fdir->mask = 0;
3192
3193 /* Flow Director must have RSS enabled */
3194 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3195 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3196 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3197 adapter->num_tx_queues = f_fdir->indices;
3198 adapter->num_rx_queues = f_fdir->indices;
3199 ret = true;
3200 } else {
3201 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3202 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3203 }
3204 return ret;
3205}
3206
0331a832
YZ		 3207#ifdef IXGBE_FCOE
3208/**
3209 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3210 * @adapter: board private structure to initialize
3211 *
3212 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3213 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3214 * rx queues out of the max number of rx queues, instead, it is used as the
3215 * index of the first rx queue used by FCoE.
3216 *
3217 **/
3218static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3219{
3220 bool ret = false;
3221 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3222
3223 f->indices = min((int)num_online_cpus(), f->indices);
3224 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3225 adapter->num_rx_queues = 1;
3226 adapter->num_tx_queues = 1;
0331a832
YZ		 3227#ifdef CONFIG_IXGBE_DCB
3228 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6 3229 DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
0331a832
YZ		 3230 ixgbe_set_dcb_queues(adapter);
3231 }
3232#endif
3233 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8de8b2e6 3234 DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
8faa2a78
YZ		 3235 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3236 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3237 ixgbe_set_fdir_queues(adapter);
3238 else
3239 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3240 }
3241 /* adding FCoE rx rings to the end */
3242 f->mask = adapter->num_rx_queues;
3243 adapter->num_rx_queues += f->indices;
8de8b2e6 3244 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3245
3246 ret = true;
3247 }
3248
3249 return ret;
3250}
3251
3252#endif /* IXGBE_FCOE */
4df10466
JB		 3253/*
3254 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3255 * @adapter: board private structure to initialize
3256 *
3257 * This is the top level queue allocation routine. The order here is very
3258 * important, starting with the "most" number of features turned on at once,
3259 * and ending with the smallest set of features. This way large combinations
3260 * can be allocated if they're turned on, and smaller combinations are the
3261 * fallthrough conditions.
3262 *
3263 **/
bc97114d
PWJ		 3264static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3265{
0331a832
YZ		 3266#ifdef IXGBE_FCOE
3267 if (ixgbe_set_fcoe_queues(adapter))
3268 goto done;
3269
3270#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3271#ifdef CONFIG_IXGBE_DCB
3272 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3273 goto done;
bc97114d
PWJ		 3274
3275#endif
c4cf55e5
PWJ		 3276 if (ixgbe_set_fdir_queues(adapter))
3277 goto done;
3278
bc97114d 3279 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3280 goto done;
3281
3282 /* fallback to base case */
3283 adapter->num_rx_queues = 1;
3284 adapter->num_tx_queues = 1;
3285
3286done:
3287 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3288 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3289}
3290
021230d4 3291static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3292 int vectors)
021230d4
AV		 3293{
3294 int err, vector_threshold;
3295
3296 /* We'll want at least 3 (vector_threshold):
3297 * 1) TxQ[0] Cleanup
3298 * 2) RxQ[0] Cleanup
3299 * 3) Other (Link Status Change, etc.)
3300 * 4) TCP Timer (optional)
3301 */
3302 vector_threshold = MIN_MSIX_COUNT;
3303
3304 /* The more we get, the more we will assign to Tx/Rx Cleanup
3305 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3306 * Right now, we simply care about how many we'll get; we'll
3307 * set them up later while requesting irq's.
3308 */
3309 while (vectors >= vector_threshold) {
3310 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3311 vectors);
021230d4
AV		 3312 if (!err) /* Success in acquiring all requested vectors. */
3313 break;
3314 else if (err < 0)
3315 vectors = 0; /* Nasty failure, quit now */
3316 else /* err == number of vectors we should try again with */
3317 vectors = err;
3318 }
3319
3320 if (vectors < vector_threshold) {
3321 /* Can't allocate enough MSI-X interrupts? Oh well.
3322 * This just means we'll go with either a single MSI
3323 * vector or fall back to legacy interrupts.
3324 */
3325 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3326 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3327 kfree(adapter->msix_entries);
3328 adapter->msix_entries = NULL;
021230d4
AV		 3329 } else {
3330 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3331 /*
3332 * Adjust for only the vectors we'll use, which is minimum
3333 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3334 * vectors we were allocated.
3335 */
3336 adapter->num_msix_vectors = min(vectors,
3337 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3338 }
3339}
3340
021230d4 3341/**
bc97114d 3342 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3343 * @adapter: board private structure to initialize
3344 *
bc97114d
PWJ		 3345 * Cache the descriptor ring offsets for RSS to the assigned rings.
3346 *
021230d4 3347 **/
bc97114d 3348static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3349{
bc97114d
PWJ		 3350 int i;
3351 bool ret = false;
3352
3353 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3354 for (i = 0; i < adapter->num_rx_queues; i++)
3355 adapter->rx_ring[i].reg_idx = i;
3356 for (i = 0; i < adapter->num_tx_queues; i++)
3357 adapter->tx_ring[i].reg_idx = i;
3358 ret = true;
3359 } else {
3360 ret = false;
3361 }
3362
3363 return ret;
3364}
3365
3366#ifdef CONFIG_IXGBE_DCB
3367/**
3368 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3369 * @adapter: board private structure to initialize
3370 *
3371 * Cache the descriptor ring offsets for DCB to the assigned rings.
3372 *
3373 **/
3374static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3375{
3376 int i;
3377 bool ret = false;
3378 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3379
3380 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3381 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3382 /* the number of queues is assumed to be symmetric */
3383 for (i = 0; i < dcb_i; i++) {
3384 adapter->rx_ring[i].reg_idx = i << 3;
3385 adapter->tx_ring[i].reg_idx = i << 2;
3386 }
bc97114d 3387 ret = true;
e8e26350 3388 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3389 if (dcb_i == 8) {
3390 /*
3391 * Tx TC0 starts at: descriptor queue 0
3392 * Tx TC1 starts at: descriptor queue 32
3393 * Tx TC2 starts at: descriptor queue 64
3394 * Tx TC3 starts at: descriptor queue 80
3395 * Tx TC4 starts at: descriptor queue 96
3396 * Tx TC5 starts at: descriptor queue 104
3397 * Tx TC6 starts at: descriptor queue 112
3398 * Tx TC7 starts at: descriptor queue 120
3399 *
3400 * Rx TC0-TC7 are offset by 16 queues each
3401 */
3402 for (i = 0; i < 3; i++) {
3403 adapter->tx_ring[i].reg_idx = i << 5;
3404 adapter->rx_ring[i].reg_idx = i << 4;
3405 }
3406 for ( ; i < 5; i++) {
3407 adapter->tx_ring[i].reg_idx =
3408 ((i + 2) << 4);
3409 adapter->rx_ring[i].reg_idx = i << 4;
3410 }
3411 for ( ; i < dcb_i; i++) {
3412 adapter->tx_ring[i].reg_idx =
3413 ((i + 8) << 3);
3414 adapter->rx_ring[i].reg_idx = i << 4;
3415 }
3416
3417 ret = true;
3418 } else if (dcb_i == 4) {
3419 /*
3420 * Tx TC0 starts at: descriptor queue 0
3421 * Tx TC1 starts at: descriptor queue 64
3422 * Tx TC2 starts at: descriptor queue 96
3423 * Tx TC3 starts at: descriptor queue 112
3424 *
3425 * Rx TC0-TC3 are offset by 32 queues each
3426 */
3427 adapter->tx_ring[0].reg_idx = 0;
3428 adapter->tx_ring[1].reg_idx = 64;
3429 adapter->tx_ring[2].reg_idx = 96;
3430 adapter->tx_ring[3].reg_idx = 112;
3431 for (i = 0 ; i < dcb_i; i++)
3432 adapter->rx_ring[i].reg_idx = i << 5;
3433
3434 ret = true;
3435 } else {
3436 ret = false;
e8e26350 3437 }
bc97114d
PWJ		 3438 } else {
3439 ret = false;
021230d4 3440 }
bc97114d
PWJ		 3441 } else {
3442 ret = false;
021230d4 3443 }
bc97114d
PWJ		 3444
3445 return ret;
3446}
3447#endif
3448
c4cf55e5
PWJ		 3449/**
3450 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3451 * @adapter: board private structure to initialize
3452 *
3453 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3454 *
3455 **/
3456static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3457{
3458 int i;
3459 bool ret = false;
3460
3461 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3462 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3463 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3464 for (i = 0; i < adapter->num_rx_queues; i++)
3465 adapter->rx_ring[i].reg_idx = i;
3466 for (i = 0; i < adapter->num_tx_queues; i++)
3467 adapter->tx_ring[i].reg_idx = i;
3468 ret = true;
3469 }
3470
3471 return ret;
3472}
3473
0331a832
YZ		 3474#ifdef IXGBE_FCOE
3475/**
3476 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3477 * @adapter: board private structure to initialize
3478 *
3479 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3480 *
3481 */
3482static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3483{
8de8b2e6 3484 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 3485 bool ret = false;
3486 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3487
3488 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3489#ifdef CONFIG_IXGBE_DCB
3490 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 3491 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3492
0331a832 3493 ixgbe_cache_ring_dcb(adapter);
8de8b2e6
YZ		 3494 /* find out queues in TC for FCoE */
3495 fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3496 fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3497 /*
3498 * In 82599, the number of Tx queues for each traffic
3499 * class for both 8-TC and 4-TC modes are:
3500 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3501 * 8 TCs: 32 32 16 16 8 8 8 8
3502 * 4 TCs: 64 64 32 32
3503 * We have max 8 queues for FCoE, where 8 the is
3504 * FCoE redirection table size. If TC for FCoE is
3505 * less than or equal to TC3, we have enough queues
3506 * to add max of 8 queues for FCoE, so we start FCoE
3507 * tx descriptor from the next one, i.e., reg_idx + 1.
3508 * If TC for FCoE is above TC3, implying 8 TC mode,
3509 * and we need 8 for FCoE, we have to take all queues
3510 * in that traffic class for FCoE.
3511 */
3512 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3513 fcoe_tx_i--;
0331a832
YZ		 3514 }
3515#endif /* CONFIG_IXGBE_DCB */
3516 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3517 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3518 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3519 ixgbe_cache_ring_fdir(adapter);
3520 else
3521 ixgbe_cache_ring_rss(adapter);
3522
8de8b2e6
YZ		 3523 fcoe_rx_i = f->mask;
3524 fcoe_tx_i = f->mask;
3525 }
3526 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3527 adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3528 adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
0331a832 3529 }
0331a832
YZ		 3530 ret = true;
3531 }
3532 return ret;
3533}
3534
3535#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3536/**
3537 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3538 * @adapter: board private structure to initialize
3539 *
3540 * Once we know the feature-set enabled for the device, we'll cache
3541 * the register offset the descriptor ring is assigned to.
3542 *
3543 * Note, the order the various feature calls is important. It must start with
3544 * the "most" features enabled at the same time, then trickle down to the
3545 * least amount of features turned on at once.
3546 **/
3547static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3548{
3549 /* start with default case */
3550 adapter->rx_ring[0].reg_idx = 0;
3551 adapter->tx_ring[0].reg_idx = 0;
3552
0331a832
YZ		 3553#ifdef IXGBE_FCOE
3554 if (ixgbe_cache_ring_fcoe(adapter))
3555 return;
3556
3557#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3558#ifdef CONFIG_IXGBE_DCB
3559 if (ixgbe_cache_ring_dcb(adapter))
3560 return;
3561
3562#endif
c4cf55e5
PWJ		 3563 if (ixgbe_cache_ring_fdir(adapter))
3564 return;
3565
bc97114d
PWJ		 3566 if (ixgbe_cache_ring_rss(adapter))
3567 return;
021230d4
AV		 3568}
3569
9a799d71
AK		 3570/**
3571 * ixgbe_alloc_queues - Allocate memory for all rings
3572 * @adapter: board private structure to initialize
3573 *
3574 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3575 * number of queues at compile-time. The polling_netdev array is
3576 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3577 **/
2f90b865 3578static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3579{
3580 int i;
3581
3582 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3583 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3584 if (!adapter->tx_ring)
021230d4 3585 goto err_tx_ring_allocation;
9a799d71
AK		 3586
3587 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3588 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3589 if (!adapter->rx_ring)
3590 goto err_rx_ring_allocation;
9a799d71 3591
021230d4 3592 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3593 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3594 adapter->tx_ring[i].queue_index = i;
3595 }
b9804972 3596
9a799d71 3597 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3598 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3599 adapter->rx_ring[i].queue_index = i;
3600 }
3601
3602 ixgbe_cache_ring_register(adapter);
3603
3604 return 0;
3605
3606err_rx_ring_allocation:
3607 kfree(adapter->tx_ring);
3608err_tx_ring_allocation:
3609 return -ENOMEM;
3610}
3611
3612/**
3613 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3614 * @adapter: board private structure to initialize
3615 *
3616 * Attempt to configure the interrupts using the best available
3617 * capabilities of the hardware and the kernel.
3618 **/
feea6a57 3619static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3620{
8be0e467 3621 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3622 int err = 0;
3623 int vector, v_budget;
3624
3625 /*
3626 * It's easy to be greedy for MSI-X vectors, but it really
3627 * doesn't do us much good if we have a lot more vectors
3628 * than CPU's. So let's be conservative and only ask for
342bde1b 3629 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 3630 */
3631 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 3632 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 3633
3634 /*
3635 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3636 * hw.mac->max_msix_vectors vectors. With features
3637 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3638 * descriptor queues supported by our device. Thus, we cap it off in
3639 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3640 */
8be0e467 3641 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3642
3643 /* A failure in MSI-X entry allocation isn't fatal, but it does
3644 * mean we disable MSI-X capabilities of the adapter. */
3645 adapter->msix_entries = kcalloc(v_budget,
b4617240 3646 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3647 if (adapter->msix_entries) {
3648 for (vector = 0; vector < v_budget; vector++)
3649 adapter->msix_entries[vector].entry = vector;
021230d4 3650
7a921c93 3651 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3652
7a921c93
AD		 3653 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3654 goto out;
3655 }
021230d4 3656
7a921c93
AD		 3657 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3658 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 3659 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3660 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3661 adapter->atr_sample_rate = 0;
7a921c93 3662 ixgbe_set_num_queues(adapter);
021230d4 3663
021230d4
AV		 3664 err = pci_enable_msi(adapter->pdev);
3665 if (!err) {
3666 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3667 } else {
3668 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3669 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3670 /* reset err */
3671 err = 0;
3672 }
3673
3674out:
021230d4
AV		 3675 return err;
3676}
3677
7a921c93
AD		 3678/**
3679 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3680 * @adapter: board private structure to initialize
3681 *
3682 * We allocate one q_vector per queue interrupt. If allocation fails we
3683 * return -ENOMEM.
3684 **/
3685static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3686{
3687 int q_idx, num_q_vectors;
3688 struct ixgbe_q_vector *q_vector;
3689 int napi_vectors;
3690 int (*poll)(struct napi_struct *, int);
3691
3692 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3693 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3694 napi_vectors = adapter->num_rx_queues;
91281fd3 3695 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 3696 } else {
3697 num_q_vectors = 1;
3698 napi_vectors = 1;
3699 poll = &ixgbe_poll;
3700 }
3701
3702 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3703 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3704 if (!q_vector)
3705 goto err_out;
3706 q_vector->adapter = adapter;
f7554a2b
NS		 3707 if (q_vector->txr_count && !q_vector->rxr_count)
3708 q_vector->eitr = adapter->tx_eitr_param;
3709 else
3710 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 3711 q_vector->v_idx = q_idx;
91281fd3 3712 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 3713 adapter->q_vector[q_idx] = q_vector;
3714 }
3715
3716 return 0;
3717
3718err_out:
3719 while (q_idx) {
3720 q_idx--;
3721 q_vector = adapter->q_vector[q_idx];
3722 netif_napi_del(&q_vector->napi);
3723 kfree(q_vector);
3724 adapter->q_vector[q_idx] = NULL;
3725 }
3726 return -ENOMEM;
3727}
3728
3729/**
3730 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3731 * @adapter: board private structure to initialize
3732 *
3733 * This function frees the memory allocated to the q_vectors. In addition if
3734 * NAPI is enabled it will delete any references to the NAPI struct prior
3735 * to freeing the q_vector.
3736 **/
3737static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3738{
3739 int q_idx, num_q_vectors;
7a921c93 3740
91281fd3 3741 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 3742 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 3743 else
7a921c93 3744 num_q_vectors = 1;
7a921c93
AD		 3745
3746 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3747 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 3748 adapter->q_vector[q_idx] = NULL;
91281fd3 3749 netif_napi_del(&q_vector->napi);
7a921c93
AD		 3750 kfree(q_vector);
3751 }
3752}
3753
7b25cdba 3754static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3755{
3756 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3757 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3758 pci_disable_msix(adapter->pdev);
3759 kfree(adapter->msix_entries);
3760 adapter->msix_entries = NULL;
3761 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3762 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3763 pci_disable_msi(adapter->pdev);
3764 }
3765 return;
3766}
3767
3768/**
3769 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3770 * @adapter: board private structure to initialize
3771 *
3772 * We determine which interrupt scheme to use based on...
3773 * - Kernel support (MSI, MSI-X)
3774 * - which can be user-defined (via MODULE_PARAM)
3775 * - Hardware queue count (num_*_queues)
3776 * - defined by miscellaneous hardware support/features (RSS, etc.)
3777 **/
2f90b865 3778int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3779{
3780 int err;
3781
3782 /* Number of supported queues */
3783 ixgbe_set_num_queues(adapter);
3784
021230d4
AV		 3785 err = ixgbe_set_interrupt_capability(adapter);
3786 if (err) {
3787 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3788 goto err_set_interrupt;
9a799d71
AK		 3789 }
3790
7a921c93
AD		 3791 err = ixgbe_alloc_q_vectors(adapter);
3792 if (err) {
3793 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3794 "vectors\n");
3795 goto err_alloc_q_vectors;
3796 }
3797
3798 err = ixgbe_alloc_queues(adapter);
3799 if (err) {
3800 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3801 goto err_alloc_queues;
3802 }
3803
021230d4 3804 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3805 "Tx Queue count = %u\n",
3806 (adapter->num_rx_queues > 1) ? "Enabled" :
3807 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3808
3809 set_bit(__IXGBE_DOWN, &adapter->state);
3810
9a799d71 3811 return 0;
021230d4 3812
7a921c93
AD		 3813err_alloc_queues:
3814 ixgbe_free_q_vectors(adapter);
3815err_alloc_q_vectors:
3816 ixgbe_reset_interrupt_capability(adapter);
021230d4 3817err_set_interrupt:
7a921c93
AD		 3818 return err;
3819}
3820
3821/**
3822 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3823 * @adapter: board private structure to clear interrupt scheme on
3824 *
3825 * We go through and clear interrupt specific resources and reset the structure
3826 * to pre-load conditions
3827 **/
3828void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3829{
021230d4
AV		 3830 kfree(adapter->tx_ring);
3831 kfree(adapter->rx_ring);
7a921c93
AD		 3832 adapter->tx_ring = NULL;
3833 adapter->rx_ring = NULL;
3834
3835 ixgbe_free_q_vectors(adapter);
3836 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3837}
3838
c4900be0
DS		 3839/**
3840 * ixgbe_sfp_timer - worker thread to find a missing module
3841 * @data: pointer to our adapter struct
3842 **/
3843static void ixgbe_sfp_timer(unsigned long data)
3844{
3845 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3846
4df10466
JB		 3847 /*
3848 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3849 * delays that sfp+ detection requires
3850 */
3851 schedule_work(&adapter->sfp_task);
3852}
3853
3854/**
3855 * ixgbe_sfp_task - worker thread to find a missing module
3856 * @work: pointer to work_struct containing our data
3857 **/
3858static void ixgbe_sfp_task(struct work_struct *work)
3859{
3860 struct ixgbe_adapter *adapter = container_of(work,
3861 struct ixgbe_adapter,
3862 sfp_task);
3863 struct ixgbe_hw *hw = &adapter->hw;
3864
3865 if ((hw->phy.type == ixgbe_phy_nl) &&
3866 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3867 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 3868 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 3869 goto reschedule;
3870 ret = hw->phy.ops.reset(hw);
3871 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 3872 dev_err(&adapter->pdev->dev, "failed to initialize "
3873 "because an unsupported SFP+ module type "
3874 "was detected.\n"
3875 "Reload the driver after installing a "
3876 "supported module.\n");
c4900be0
DS		 3877 unregister_netdev(adapter->netdev);
3878 } else {
3879 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3880 hw->phy.sfp_type);
3881 }
3882 /* don't need this routine any more */
3883 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3884 }
3885 return;
3886reschedule:
3887 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3888 mod_timer(&adapter->sfp_timer,
3889 round_jiffies(jiffies + (2 * HZ)));
3890}
3891
9a799d71
AK		 3892/**
3893 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3894 * @adapter: board private structure to initialize
3895 *
3896 * ixgbe_sw_init initializes the Adapter private data structure.
3897 * Fields are initialized based on PCI device information and
3898 * OS network device settings (MTU size).
3899 **/
3900static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3901{
3902 struct ixgbe_hw *hw = &adapter->hw;
3903 struct pci_dev *pdev = adapter->pdev;
021230d4 3904 unsigned int rss;
7a6b6f51 3905#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3906 int j;
3907 struct tc_configuration *tc;
3908#endif
021230d4 3909
c44ade9e
JB		 3910 /* PCI config space info */
3911
3912 hw->vendor_id = pdev->vendor;
3913 hw->device_id = pdev->device;
3914 hw->revision_id = pdev->revision;
3915 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3916 hw->subsystem_device_id = pdev->subsystem_device;
3917
021230d4
AV		 3918 /* Set capability flags */
3919 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3920 adapter->ring_feature[RING_F_RSS].indices = rss;
3921 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3922 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 3923 if (hw->mac.type == ixgbe_mac_82598EB) {
3924 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3925 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 3926 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 3927 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3928 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 3929 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3930 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
c4cf55e5
PWJ		 3931 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3932 adapter->ring_feature[RING_F_FDIR].indices =
3933 IXGBE_MAX_FDIR_INDICES;
3934 adapter->atr_sample_rate = 20;
3935 adapter->fdir_pballoc = 0;
eacd73f7 3936#ifdef IXGBE_FCOE
0d551589
YZ		 3937 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3938 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3939 adapter->ring_feature[RING_F_FCOE].indices = 0;
6ee16520
YZ		 3940 /* Default traffic class to use for FCoE */
3941 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
eacd73f7 3942#endif /* IXGBE_FCOE */
f8212f97 3943 }
2f90b865 3944
7a6b6f51 3945#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3946 /* Configure DCB traffic classes */
3947 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3948 tc = &adapter->dcb_cfg.tc_config[j];
3949 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3950 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3951 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3952 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3953 tc->dcb_pfc = pfc_disabled;
3954 }
3955 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3956 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3957 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 3958 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 3959 adapter->dcb_cfg.round_robin_enable = false;
3960 adapter->dcb_set_bitmap = 0x00;
3961 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3962 adapter->ring_feature[RING_F_DCB].indices);
3963
3964#endif
9a799d71
AK		 3965
3966 /* default flow control settings */
cd7664f6 3967 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3968 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 3969#ifdef CONFIG_DCB
3970 adapter->last_lfc_mode = hw->fc.current_mode;
3971#endif
2b9ade93
JB		 3972 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3973 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3974 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3975 hw->fc.send_xon = true;
71fd570b 3976 hw->fc.disable_fc_autoneg = false;
9a799d71 3977
30efa5a3 3978 /* enable itr by default in dynamic mode */
f7554a2b
NS		 3979 adapter->rx_itr_setting = 1;
3980 adapter->rx_eitr_param = 20000;
3981 adapter->tx_itr_setting = 1;
3982 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 3983
3984 /* set defaults for eitr in MegaBytes */
3985 adapter->eitr_low = 10;
3986 adapter->eitr_high = 20;
3987
3988 /* set default ring sizes */
3989 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3990 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3991
9a799d71 3992 /* initialize eeprom parameters */
c44ade9e 3993 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3994 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3995 return -EIO;
3996 }
3997
021230d4 3998 /* enable rx csum by default */
9a799d71
AK		 3999 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4000
9a799d71
AK		 4001 set_bit(__IXGBE_DOWN, &adapter->state);
4002
4003 return 0;
4004}
4005
4006/**
4007 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4008 * @adapter: board private structure
3a581073 4009 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4010 *
4011 * Return 0 on success, negative on failure
4012 **/
4013int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4014 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4015{
4016 struct pci_dev *pdev = adapter->pdev;
4017 int size;
4018
3a581073
JB		 4019 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4020 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4021 if (!tx_ring->tx_buffer_info)
4022 goto err;
3a581073 4023 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4024
4025 /* round up to nearest 4K */
12207e49 4026 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4027 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4028
3a581073
JB		 4029 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4030 &tx_ring->dma);
e01c31a5
JB		 4031 if (!tx_ring->desc)
4032 goto err;
9a799d71 4033
3a581073
JB		 4034 tx_ring->next_to_use = 0;
4035 tx_ring->next_to_clean = 0;
4036 tx_ring->work_limit = tx_ring->count;
9a799d71 4037 return 0;
e01c31a5
JB		 4038
4039err:
4040 vfree(tx_ring->tx_buffer_info);
4041 tx_ring->tx_buffer_info = NULL;
4042 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4043 "descriptor ring\n");
4044 return -ENOMEM;
9a799d71
AK		 4045}
4046
69888674
AD		 4047/**
4048 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4049 * @adapter: board private structure
4050 *
4051 * If this function returns with an error, then it's possible one or
4052 * more of the rings is populated (while the rest are not). It is the
4053 * callers duty to clean those orphaned rings.
4054 *
4055 * Return 0 on success, negative on failure
4056 **/
4057static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4058{
4059 int i, err = 0;
4060
4061 for (i = 0; i < adapter->num_tx_queues; i++) {
4062 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
4063 if (!err)
4064 continue;
4065 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4066 break;
4067 }
4068
4069 return err;
4070}
4071
9a799d71
AK		 4072/**
4073 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4074 * @adapter: board private structure
3a581073 4075 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4076 *
4077 * Returns 0 on success, negative on failure
4078 **/
4079int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4080 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4081{
4082 struct pci_dev *pdev = adapter->pdev;
021230d4 4083 int size;
9a799d71 4084
3a581073
JB		 4085 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4086 rx_ring->rx_buffer_info = vmalloc(size);
4087 if (!rx_ring->rx_buffer_info) {
9a799d71 4088 DPRINTK(PROBE, ERR,
b4617240 4089 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 4090 goto alloc_failed;
9a799d71 4091 }
3a581073 4092 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4093
9a799d71 4094 /* Round up to nearest 4K */
3a581073
JB		 4095 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4096 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4097
3a581073 4098 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 4099
3a581073 4100 if (!rx_ring->desc) {
9a799d71 4101 DPRINTK(PROBE, ERR,
b4617240 4102 "Memory allocation failed for the rx desc ring\n");
3a581073 4103 vfree(rx_ring->rx_buffer_info);
177db6ff 4104 goto alloc_failed;
9a799d71
AK		 4105 }
4106
3a581073
JB		 4107 rx_ring->next_to_clean = 0;
4108 rx_ring->next_to_use = 0;
9a799d71
AK		 4109
4110 return 0;
177db6ff
MC		 4111
4112alloc_failed:
177db6ff 4113 return -ENOMEM;
9a799d71
AK		 4114}
4115
69888674
AD		 4116/**
4117 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4118 * @adapter: board private structure
4119 *
4120 * If this function returns with an error, then it's possible one or
4121 * more of the rings is populated (while the rest are not). It is the
4122 * callers duty to clean those orphaned rings.
4123 *
4124 * Return 0 on success, negative on failure
4125 **/
4126
4127static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4128{
4129 int i, err = 0;
4130
4131 for (i = 0; i < adapter->num_rx_queues; i++) {
4132 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4133 if (!err)
4134 continue;
4135 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4136 break;
4137 }
4138
4139 return err;
4140}
4141
9a799d71
AK		 4142/**
4143 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4144 * @adapter: board private structure
4145 * @tx_ring: Tx descriptor ring for a specific queue
4146 *
4147 * Free all transmit software resources
4148 **/
c431f97e
JB		 4149void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4150 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4151{
4152 struct pci_dev *pdev = adapter->pdev;
4153
4154 ixgbe_clean_tx_ring(adapter, tx_ring);
4155
4156 vfree(tx_ring->tx_buffer_info);
4157 tx_ring->tx_buffer_info = NULL;
4158
4159 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4160
4161 tx_ring->desc = NULL;
4162}
4163
4164/**
4165 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4166 * @adapter: board private structure
4167 *
4168 * Free all transmit software resources
4169 **/
4170static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4171{
4172 int i;
4173
4174 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 4175 if (adapter->tx_ring[i].desc)
4176 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 4177}
4178
4179/**
b4617240 4180 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4181 * @adapter: board private structure
4182 * @rx_ring: ring to clean the resources from
4183 *
4184 * Free all receive software resources
4185 **/
c431f97e
JB		 4186void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4187 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4188{
4189 struct pci_dev *pdev = adapter->pdev;
4190
4191 ixgbe_clean_rx_ring(adapter, rx_ring);
4192
4193 vfree(rx_ring->rx_buffer_info);
4194 rx_ring->rx_buffer_info = NULL;
4195
4196 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4197
4198 rx_ring->desc = NULL;
4199}
4200
4201/**
4202 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4203 * @adapter: board private structure
4204 *
4205 * Free all receive software resources
4206 **/
4207static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4208{
4209 int i;
4210
4211 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 4212 if (adapter->rx_ring[i].desc)
4213 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 4214}
4215
9a799d71
AK		 4216/**
4217 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4218 * @netdev: network interface device structure
4219 * @new_mtu: new value for maximum frame size
4220 *
4221 * Returns 0 on success, negative on failure
4222 **/
4223static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4224{
4225 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4226 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4227
42c783c5
JB		 4228 /* MTU < 68 is an error and causes problems on some kernels */
4229 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4230 return -EINVAL;
4231
021230d4 4232 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4233 netdev->mtu, new_mtu);
021230d4 4234 /* must set new MTU before calling down or up */
9a799d71
AK		 4235 netdev->mtu = new_mtu;
4236
d4f80882
AV		 4237 if (netif_running(netdev))
4238 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4239
4240 return 0;
4241}
4242
4243/**
4244 * ixgbe_open - Called when a network interface is made active
4245 * @netdev: network interface device structure
4246 *
4247 * Returns 0 on success, negative value on failure
4248 *
4249 * The open entry point is called when a network interface is made
4250 * active by the system (IFF_UP). At this point all resources needed
4251 * for transmit and receive operations are allocated, the interrupt
4252 * handler is registered with the OS, the watchdog timer is started,
4253 * and the stack is notified that the interface is ready.
4254 **/
4255static int ixgbe_open(struct net_device *netdev)
4256{
4257 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4258 int err;
4bebfaa5
AK		 4259
4260 /* disallow open during test */
4261 if (test_bit(__IXGBE_TESTING, &adapter->state))
4262 return -EBUSY;
9a799d71 4263
54386467
JB		 4264 netif_carrier_off(netdev);
4265
9a799d71
AK		 4266 /* allocate transmit descriptors */
4267 err = ixgbe_setup_all_tx_resources(adapter);
4268 if (err)
4269 goto err_setup_tx;
4270
9a799d71
AK		 4271 /* allocate receive descriptors */
4272 err = ixgbe_setup_all_rx_resources(adapter);
4273 if (err)
4274 goto err_setup_rx;
4275
4276 ixgbe_configure(adapter);
4277
021230d4 4278 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4279 if (err)
4280 goto err_req_irq;
4281
9a799d71
AK		 4282 err = ixgbe_up_complete(adapter);
4283 if (err)
4284 goto err_up;
4285
d55b53ff
JK		 4286 netif_tx_start_all_queues(netdev);
4287
9a799d71
AK		 4288 return 0;
4289
4290err_up:
5eba3699 4291 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4292 ixgbe_free_irq(adapter);
4293err_req_irq:
9a799d71 4294err_setup_rx:
a20a1199 4295 ixgbe_free_all_rx_resources(adapter);
9a799d71 4296err_setup_tx:
a20a1199 4297 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4298 ixgbe_reset(adapter);
4299
4300 return err;
4301}
4302
4303/**
4304 * ixgbe_close - Disables a network interface
4305 * @netdev: network interface device structure
4306 *
4307 * Returns 0, this is not allowed to fail
4308 *
4309 * The close entry point is called when an interface is de-activated
4310 * by the OS. The hardware is still under the drivers control, but
4311 * needs to be disabled. A global MAC reset is issued to stop the
4312 * hardware, and all transmit and receive resources are freed.
4313 **/
4314static int ixgbe_close(struct net_device *netdev)
4315{
4316 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4317
4318 ixgbe_down(adapter);
4319 ixgbe_free_irq(adapter);
4320
4321 ixgbe_free_all_tx_resources(adapter);
4322 ixgbe_free_all_rx_resources(adapter);
4323
5eba3699 4324 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4325
4326 return 0;
4327}
4328
b3c8b4ba
AD		 4329#ifdef CONFIG_PM
4330static int ixgbe_resume(struct pci_dev *pdev)
4331{
4332 struct net_device *netdev = pci_get_drvdata(pdev);
4333 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4334 u32 err;
4335
4336 pci_set_power_state(pdev, PCI_D0);
4337 pci_restore_state(pdev);
9ce77666 4338
4339 err = pci_enable_device_mem(pdev);
b3c8b4ba 4340 if (err) {
69888674 4341 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4342 "suspend\n");
4343 return err;
4344 }
4345 pci_set_master(pdev);
4346
dd4d8ca6 4347 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4348
4349 err = ixgbe_init_interrupt_scheme(adapter);
4350 if (err) {
4351 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4352 "device\n");
4353 return err;
4354 }
4355
b3c8b4ba
AD		 4356 ixgbe_reset(adapter);
4357
495dce12
WJP		 4358 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4359
b3c8b4ba
AD		 4360 if (netif_running(netdev)) {
4361 err = ixgbe_open(adapter->netdev);
4362 if (err)
4363 return err;
4364 }
4365
4366 netif_device_attach(netdev);
4367
4368 return 0;
4369}
b3c8b4ba 4370#endif /* CONFIG_PM */
9d8d05ae
RW		 4371
4372static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4373{
4374 struct net_device *netdev = pci_get_drvdata(pdev);
4375 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4376 struct ixgbe_hw *hw = &adapter->hw;
4377 u32 ctrl, fctrl;
4378 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4379#ifdef CONFIG_PM
4380 int retval = 0;
4381#endif
4382
4383 netif_device_detach(netdev);
4384
4385 if (netif_running(netdev)) {
4386 ixgbe_down(adapter);
4387 ixgbe_free_irq(adapter);
4388 ixgbe_free_all_tx_resources(adapter);
4389 ixgbe_free_all_rx_resources(adapter);
4390 }
7a921c93 4391 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4392
4393#ifdef CONFIG_PM
4394 retval = pci_save_state(pdev);
4395 if (retval)
4396 return retval;
4df10466 4397
b3c8b4ba 4398#endif
e8e26350
PW		 4399 if (wufc) {
4400 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4401
e8e26350
PW		 4402 /* turn on all-multi mode if wake on multicast is enabled */
4403 if (wufc & IXGBE_WUFC_MC) {
4404 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4405 fctrl |= IXGBE_FCTRL_MPE;
4406 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4407 }
4408
4409 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4410 ctrl |= IXGBE_CTRL_GIO_DIS;
4411 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4412
4413 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4414 } else {
4415 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4416 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4417 }
4418
dd4d8ca6
DS		 4419 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4420 pci_wake_from_d3(pdev, true);
4421 else
4422 pci_wake_from_d3(pdev, false);
b3c8b4ba 4423
9d8d05ae
RW		 4424 *enable_wake = !!wufc;
4425
b3c8b4ba
AD		 4426 ixgbe_release_hw_control(adapter);
4427
4428 pci_disable_device(pdev);
4429
9d8d05ae
RW		 4430 return 0;
4431}
4432
4433#ifdef CONFIG_PM
4434static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4435{
4436 int retval;
4437 bool wake;
4438
4439 retval = __ixgbe_shutdown(pdev, &wake);
4440 if (retval)
4441 return retval;
4442
4443 if (wake) {
4444 pci_prepare_to_sleep(pdev);
4445 } else {
4446 pci_wake_from_d3(pdev, false);
4447 pci_set_power_state(pdev, PCI_D3hot);
4448 }
b3c8b4ba
AD		 4449
4450 return 0;
4451}
9d8d05ae 4452#endif /* CONFIG_PM */
b3c8b4ba
AD		 4453
4454static void ixgbe_shutdown(struct pci_dev *pdev)
4455{
9d8d05ae
RW		 4456 bool wake;
4457
4458 __ixgbe_shutdown(pdev, &wake);
4459
4460 if (system_state == SYSTEM_POWER_OFF) {
4461 pci_wake_from_d3(pdev, wake);
4462 pci_set_power_state(pdev, PCI_D3hot);
4463 }
b3c8b4ba
AD		 4464}
4465
9a799d71
AK		 4466/**
4467 * ixgbe_update_stats - Update the board statistics counters.
4468 * @adapter: board private structure
4469 **/
4470void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4471{
2d86f139 4472 struct net_device *netdev = adapter->netdev;
9a799d71 4473 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4474 u64 total_mpc = 0;
4475 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 4476
d51019a4 4477 if (hw->mac.type == ixgbe_mac_82599EB) {
f8212f97 4478 u64 rsc_count = 0;
d51019a4
PW		 4479 for (i = 0; i < 16; i++)
4480 adapter->hw_rx_no_dma_resources +=
4481 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
f8212f97
AD		 4482 for (i = 0; i < adapter->num_rx_queues; i++)
4483 rsc_count += adapter->rx_ring[i].rsc_count;
4484 adapter->rsc_count = rsc_count;
d51019a4
PW		 4485 }
4486
9a799d71 4487 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4488 for (i = 0; i < 8; i++) {
4489 /* for packet buffers not used, the register should read 0 */
4490 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4491 missed_rx += mpc;
4492 adapter->stats.mpc[i] += mpc;
4493 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4494 if (hw->mac.type == ixgbe_mac_82598EB)
4495 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4496 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4497 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4498 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4499 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4500 if (hw->mac.type == ixgbe_mac_82599EB) {
4501 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4502 IXGBE_PXONRXCNT(i));
4503 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4504 IXGBE_PXOFFRXCNT(i));
4505 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4506 } else {
4507 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4508 IXGBE_PXONRXC(i));
4509 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4510 IXGBE_PXOFFRXC(i));
4511 }
2f90b865
AD		 4512 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4513 IXGBE_PXONTXC(i));
2f90b865 4514 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4515 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4516 }
4517 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4518 /* work around hardware counting issue */
4519 adapter->stats.gprc -= missed_rx;
4520
4521 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 4522 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 4523 u64 tmp;
e8e26350 4524 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 4525 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4526 adapter->stats.gorc += (tmp << 32);
e8e26350 4527 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 4528 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4529 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 4530 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4531 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4532 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4533 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4534 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4535 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4536#ifdef IXGBE_FCOE
4537 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4538 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4539 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4540 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4541 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4542 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4543#endif /* IXGBE_FCOE */
e8e26350
PW		 4544 } else {
4545 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4546 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4547 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4548 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4549 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4550 }
9a799d71
AK		 4551 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4552 adapter->stats.bprc += bprc;
4553 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4554 if (hw->mac.type == ixgbe_mac_82598EB)
4555 adapter->stats.mprc -= bprc;
9a799d71
AK		 4556 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4557 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4558 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4559 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4560 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4561 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4562 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4563 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4564 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4565 adapter->stats.lxontxc += lxon;
4566 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4567 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4568 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4569 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4570 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4571 /*
4572 * 82598 errata - tx of flow control packets is included in tx counters
4573 */
4574 xon_off_tot = lxon + lxoff;
4575 adapter->stats.gptc -= xon_off_tot;
4576 adapter->stats.mptc -= xon_off_tot;
4577 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4578 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4579 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4580 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4581 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4582 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4583 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4584 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4585 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4586 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4587 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4588 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4589 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4590
4591 /* Fill out the OS statistics structure */
2d86f139 4592 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 4593
4594 /* Rx Errors */
2d86f139 4595 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 4596 adapter->stats.rlec;
2d86f139
AK		 4597 netdev->stats.rx_dropped = 0;
4598 netdev->stats.rx_length_errors = adapter->stats.rlec;
4599 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4600 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4601}
4602
4603/**
4604 * ixgbe_watchdog - Timer Call-back
4605 * @data: pointer to adapter cast into an unsigned long
4606 **/
4607static void ixgbe_watchdog(unsigned long data)
4608{
4609 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 4610 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 4611 u64 eics = 0;
4612 int i;
cf8280ee 4613
fe49f04a
AD		 4614 /*
4615 * Do the watchdog outside of interrupt context due to the lovely
4616 * delays that some of the newer hardware requires
4617 */
22d5a71b 4618
fe49f04a
AD		 4619 if (test_bit(__IXGBE_DOWN, &adapter->state))
4620 goto watchdog_short_circuit;
22d5a71b 4621
fe49f04a
AD		 4622 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4623 /*
4624 * for legacy and MSI interrupts don't set any bits
4625 * that are enabled for EIAM, because this operation
4626 * would set *both* EIMS and EICS for any bit in EIAM
4627 */
4628 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4629 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4630 goto watchdog_reschedule;
4631 }
4632
4633 /* get one bit for every active tx/rx interrupt vector */
4634 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4635 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4636 if (qv->rxr_count || qv->txr_count)
4637 eics |= ((u64)1 << i);
cf8280ee 4638 }
9a799d71 4639
fe49f04a
AD		 4640 /* Cause software interrupt to ensure rx rings are cleaned */
4641 ixgbe_irq_rearm_queues(adapter, eics);
4642
4643watchdog_reschedule:
4644 /* Reset the timer */
4645 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4646
4647watchdog_short_circuit:
cf8280ee
JB		 4648 schedule_work(&adapter->watchdog_task);
4649}
4650
e8e26350
PW		 4651/**
4652 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4653 * @work: pointer to work_struct containing our data
4654 **/
4655static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4656{
4657 struct ixgbe_adapter *adapter = container_of(work,
4658 struct ixgbe_adapter,
4659 multispeed_fiber_task);
4660 struct ixgbe_hw *hw = &adapter->hw;
4661 u32 autoneg;
8620a103 4662 bool negotiation;
e8e26350
PW		 4663
4664 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 4665 autoneg = hw->phy.autoneg_advertised;
4666 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103
MC		 4667 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4668 if (hw->mac.ops.setup_link)
4669 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 4670 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4671 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4672}
4673
4674/**
4675 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4676 * @work: pointer to work_struct containing our data
4677 **/
4678static void ixgbe_sfp_config_module_task(struct work_struct *work)
4679{
4680 struct ixgbe_adapter *adapter = container_of(work,
4681 struct ixgbe_adapter,
4682 sfp_config_module_task);
4683 struct ixgbe_hw *hw = &adapter->hw;
4684 u32 err;
4685
4686 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 4687
4688 /* Time for electrical oscillations to settle down */
4689 msleep(100);
e8e26350 4690 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4691
e8e26350 4692 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4693 dev_err(&adapter->pdev->dev, "failed to initialize because "
4694 "an unsupported SFP+ module type was detected.\n"
4695 "Reload the driver after installing a supported "
4696 "module.\n");
63d6e1d8 4697 unregister_netdev(adapter->netdev);
e8e26350
PW		 4698 return;
4699 }
4700 hw->mac.ops.setup_sfp(hw);
4701
8d1c3c07 4702 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4703 /* This will also work for DA Twinax connections */
4704 schedule_work(&adapter->multispeed_fiber_task);
4705 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4706}
4707
c4cf55e5
PWJ		 4708/**
4709 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4710 * @work: pointer to work_struct containing our data
4711 **/
4712static void ixgbe_fdir_reinit_task(struct work_struct *work)
4713{
4714 struct ixgbe_adapter *adapter = container_of(work,
4715 struct ixgbe_adapter,
4716 fdir_reinit_task);
4717 struct ixgbe_hw *hw = &adapter->hw;
4718 int i;
4719
4720 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4721 for (i = 0; i < adapter->num_tx_queues; i++)
4722 set_bit(__IXGBE_FDIR_INIT_DONE,
4723 &(adapter->tx_ring[i].reinit_state));
4724 } else {
4725 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4726 "ignored adding FDIR ATR filters \n");
4727 }
4728 /* Done FDIR Re-initialization, enable transmits */
4729 netif_tx_start_all_queues(adapter->netdev);
4730}
4731
cf8280ee 4732/**
69888674
AD		 4733 * ixgbe_watchdog_task - worker thread to bring link up
4734 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4735 **/
4736static void ixgbe_watchdog_task(struct work_struct *work)
4737{
4738 struct ixgbe_adapter *adapter = container_of(work,
4739 struct ixgbe_adapter,
4740 watchdog_task);
4741 struct net_device *netdev = adapter->netdev;
4742 struct ixgbe_hw *hw = &adapter->hw;
4743 u32 link_speed = adapter->link_speed;
4744 bool link_up = adapter->link_up;
bc59fcda
NS		 4745 int i;
4746 struct ixgbe_ring *tx_ring;
4747 int some_tx_pending = 0;
cf8280ee
JB		 4748
4749 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4750
4751 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4752 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 4753 if (link_up) {
4754#ifdef CONFIG_DCB
4755 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4756 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 4757 hw->mac.ops.fc_enable(hw, i);
264857b8 4758 } else {
620fa036 4759 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4760 }
4761#else
620fa036 4762 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4763#endif
4764 }
4765
cf8280ee
JB		 4766 if (link_up ||
4767 time_after(jiffies, (adapter->link_check_timeout +
4768 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 4769 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 4770 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 4771 }
4772 adapter->link_up = link_up;
4773 adapter->link_speed = link_speed;
4774 }
9a799d71
AK		 4775
4776 if (link_up) {
4777 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4778 bool flow_rx, flow_tx;
4779
4780 if (hw->mac.type == ixgbe_mac_82599EB) {
4781 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4782 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 4783 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4784 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 4785 } else {
4786 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4787 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 4788 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4789 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 4790 }
4791
a46e534b
JK		 4792 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4793 "Flow Control: %s\n",
4794 netdev->name,
4795 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4796 "10 Gbps" :
4797 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4798 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4799 ((flow_rx && flow_tx) ? "RX/TX" :
4800 (flow_rx ? "RX" :
4801 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4802
4803 netif_carrier_on(netdev);
9a799d71
AK		 4804 } else {
4805 /* Force detection of hung controller */
4806 adapter->detect_tx_hung = true;
4807 }
4808 } else {
cf8280ee
JB		 4809 adapter->link_up = false;
4810 adapter->link_speed = 0;
9a799d71 4811 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4812 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4813 netdev->name);
9a799d71 4814 netif_carrier_off(netdev);
9a799d71
AK		 4815 }
4816 }
4817
bc59fcda
NS		 4818 if (!netif_carrier_ok(netdev)) {
4819 for (i = 0; i < adapter->num_tx_queues; i++) {
4820 tx_ring = &adapter->tx_ring[i];
4821 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4822 some_tx_pending = 1;
4823 break;
4824 }
4825 }
4826
4827 if (some_tx_pending) {
4828 /* We've lost link, so the controller stops DMA,
4829 * but we've got queued Tx work that's never going
4830 * to get done, so reset controller to flush Tx.
4831 * (Do the reset outside of interrupt context).
4832 */
4833 schedule_work(&adapter->reset_task);
4834 }
4835 }
4836
9a799d71 4837 ixgbe_update_stats(adapter);
cf8280ee 4838 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4839}
4840
9a799d71 4841static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4842 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4843 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4844{
4845 struct ixgbe_adv_tx_context_desc *context_desc;
4846 unsigned int i;
4847 int err;
4848 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4849 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4850 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4851
4852 if (skb_is_gso(skb)) {
4853 if (skb_header_cloned(skb)) {
4854 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4855 if (err)
4856 return err;
4857 }
4858 l4len = tcp_hdrlen(skb);
4859 *hdr_len += l4len;
4860
8327d000 4861 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4862 struct iphdr *iph = ip_hdr(skb);
4863 iph->tot_len = 0;
4864 iph->check = 0;
4865 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4866 iph->daddr, 0,
4867 IPPROTO_TCP,
4868 0);
9a799d71
AK		 4869 adapter->hw_tso_ctxt++;
4870 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4871 ipv6_hdr(skb)->payload_len = 0;
4872 tcp_hdr(skb)->check =
4873 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4874 &ipv6_hdr(skb)->daddr,
4875 0, IPPROTO_TCP, 0);
9a799d71
AK		 4876 adapter->hw_tso6_ctxt++;
4877 }
4878
4879 i = tx_ring->next_to_use;
4880
4881 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4882 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4883
4884 /* VLAN MACLEN IPLEN */
4885 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4886 vlan_macip_lens |=
4887 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4888 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4889 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4890 *hdr_len += skb_network_offset(skb);
4891 vlan_macip_lens |=
4892 (skb_transport_header(skb) - skb_network_header(skb));
4893 *hdr_len +=
4894 (skb_transport_header(skb) - skb_network_header(skb));
4895 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4896 context_desc->seqnum_seed = 0;
4897
4898 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4899 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4900 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4901
8327d000 4902 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4903 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4904 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4905 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4906
4907 /* MSS L4LEN IDX */
9f8cdf4f 4908 mss_l4len_idx =
9a799d71
AK		 4909 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4910 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4911 /* use index 1 for TSO */
4912 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4913 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4914
4915 tx_buffer_info->time_stamp = jiffies;
4916 tx_buffer_info->next_to_watch = i;
4917
4918 i++;
4919 if (i == tx_ring->count)
4920 i = 0;
4921 tx_ring->next_to_use = i;
4922
4923 return true;
4924 }
4925 return false;
4926}
4927
4928static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4929 struct ixgbe_ring *tx_ring,
4930 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4931{
4932 struct ixgbe_adv_tx_context_desc *context_desc;
4933 unsigned int i;
4934 struct ixgbe_tx_buffer *tx_buffer_info;
4935 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4936
4937 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4938 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4939 i = tx_ring->next_to_use;
4940 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4941 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4942
4943 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4944 vlan_macip_lens |=
4945 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4946 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4947 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4948 if (skb->ip_summed == CHECKSUM_PARTIAL)
4949 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4950 skb_network_header(skb));
9a799d71
AK		 4951
4952 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4953 context_desc->seqnum_seed = 0;
4954
4955 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4956 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4957
4958 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4959 switch (skb->protocol) {
09640e63 4960 case cpu_to_be16(ETH_P_IP):
9a799d71 4961 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4962 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4963 type_tucmd_mlhl |=
b4617240 4964 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4965 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4966 type_tucmd_mlhl |=
4967 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4968 break;
09640e63 4969 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4970 /* XXX what about other V6 headers?? */
4971 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4972 type_tucmd_mlhl |=
b4617240 4973 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4974 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4975 type_tucmd_mlhl |=
4976 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4977 break;
41825d71
AK		 4978 default:
4979 if (unlikely(net_ratelimit())) {
4980 DPRINTK(PROBE, WARNING,
4981 "partial checksum but proto=%x!\n",
4982 skb->protocol);
4983 }
4984 break;
4985 }
9a799d71
AK		 4986 }
4987
4988 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4989 /* use index zero for tx checksum offload */
9a799d71
AK		 4990 context_desc->mss_l4len_idx = 0;
4991
4992 tx_buffer_info->time_stamp = jiffies;
4993 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4994
9a799d71
AK		 4995 adapter->hw_csum_tx_good++;
4996 i++;
4997 if (i == tx_ring->count)
4998 i = 0;
4999 tx_ring->next_to_use = i;
5000
5001 return true;
5002 }
9f8cdf4f 5003
9a799d71
AK		 5004 return false;
5005}
5006
5007static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5008 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5009 struct sk_buff *skb, u32 tx_flags,
5010 unsigned int first)
9a799d71
AK		 5011{
5012 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5013 unsigned int len;
5014 unsigned int total = skb->len;
9a799d71
AK		 5015 unsigned int offset = 0, size, count = 0, i;
5016 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5017 unsigned int f;
44df32c5 5018 dma_addr_t *map;
9a799d71
AK		 5019
5020 i = tx_ring->next_to_use;
5021
44df32c5
AD		 5022 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
5023 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
5024 return 0;
5025 }
5026
5027 map = skb_shinfo(skb)->dma_maps;
5028
eacd73f7
YZ		 5029 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5030 /* excluding fcoe_crc_eof for FCoE */
5031 total -= sizeof(struct fcoe_crc_eof);
5032
5033 len = min(skb_headlen(skb), total);
9a799d71
AK		 5034 while (len) {
5035 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5036 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5037
5038 tx_buffer_info->length = size;
042a53a9 5039 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
9a799d71
AK		 5040 tx_buffer_info->time_stamp = jiffies;
5041 tx_buffer_info->next_to_watch = i;
5042
5043 len -= size;
eacd73f7 5044 total -= size;
9a799d71
AK		 5045 offset += size;
5046 count++;
44df32c5
AD		 5047
5048 if (len) {
5049 i++;
5050 if (i == tx_ring->count)
5051 i = 0;
5052 }
9a799d71
AK		 5053 }
5054
5055 for (f = 0; f < nr_frags; f++) {
5056 struct skb_frag_struct *frag;
5057
5058 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5059 len = min((unsigned int)frag->size, total);
44df32c5 5060 offset = 0;
9a799d71
AK		 5061
5062 while (len) {
44df32c5
AD		 5063 i++;
5064 if (i == tx_ring->count)
5065 i = 0;
5066
9a799d71
AK		 5067 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5068 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5069
5070 tx_buffer_info->length = size;
042a53a9 5071 tx_buffer_info->dma = map[f] + offset;
9a799d71
AK		 5072 tx_buffer_info->time_stamp = jiffies;
5073 tx_buffer_info->next_to_watch = i;
5074
5075 len -= size;
eacd73f7 5076 total -= size;
9a799d71
AK		 5077 offset += size;
5078 count++;
9a799d71 5079 }
eacd73f7
YZ		 5080 if (total == 0)
5081 break;
9a799d71 5082 }
44df32c5 5083
9a799d71
AK		 5084 tx_ring->tx_buffer_info[i].skb = skb;
5085 tx_ring->tx_buffer_info[first].next_to_watch = i;
5086
5087 return count;
5088}
5089
5090static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 5091 struct ixgbe_ring *tx_ring,
5092 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 5093{
5094 union ixgbe_adv_tx_desc *tx_desc = NULL;
5095 struct ixgbe_tx_buffer *tx_buffer_info;
5096 u32 olinfo_status = 0, cmd_type_len = 0;
5097 unsigned int i;
5098 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5099
5100 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5101
5102 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5103
5104 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5105 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5106
5107 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5108 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5109
5110 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5111 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5112
4eeae6fd
PW		 5113 /* use index 1 context for tso */
5114 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5115 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5116 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 5117 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5118
5119 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5120 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5121 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5122
eacd73f7
YZ		 5123 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5124 olinfo_status |= IXGBE_ADVTXD_CC;
5125 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5126 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5127 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5128 }
5129
9a799d71
AK		 5130 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5131
5132 i = tx_ring->next_to_use;
5133 while (count--) {
5134 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5135 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5136 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5137 tx_desc->read.cmd_type_len =
b4617240 5138 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5139 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5140 i++;
5141 if (i == tx_ring->count)
5142 i = 0;
5143 }
5144
5145 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5146
5147 /*
5148 * Force memory writes to complete before letting h/w
5149 * know there are new descriptors to fetch. (Only
5150 * applicable for weak-ordered memory model archs,
5151 * such as IA-64).
5152 */
5153 wmb();
5154
5155 tx_ring->next_to_use = i;
5156 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5157}
5158
c4cf55e5
PWJ		 5159static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5160 int queue, u32 tx_flags)
5161{
5162 /* Right now, we support IPv4 only */
5163 struct ixgbe_atr_input atr_input;
5164 struct tcphdr *th;
c4cf55e5
PWJ		 5165 struct iphdr *iph = ip_hdr(skb);
5166 struct ethhdr *eth = (struct ethhdr *)skb->data;
5167 u16 vlan_id, src_port, dst_port, flex_bytes;
5168 u32 src_ipv4_addr, dst_ipv4_addr;
5169 u8 l4type = 0;
5170
5171 /* check if we're UDP or TCP */
5172 if (iph->protocol == IPPROTO_TCP) {
5173 th = tcp_hdr(skb);
5174 src_port = th->source;
5175 dst_port = th->dest;
5176 l4type |= IXGBE_ATR_L4TYPE_TCP;
5177 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 5178 } else {
5179 /* Unsupported L4 header, just bail here */
5180 return;
5181 }
5182
5183 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5184
5185 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5186 IXGBE_TX_FLAGS_VLAN_SHIFT;
5187 src_ipv4_addr = iph->saddr;
5188 dst_ipv4_addr = iph->daddr;
5189 flex_bytes = eth->h_proto;
5190
5191 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5192 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5193 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5194 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5195 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5196 /* src and dst are inverted, think how the receiver sees them */
5197 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5198 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5199
5200 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5201 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5202}
5203
e092be60 5204static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5205 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5206{
5207 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5208
30eba97a 5209 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5210 /* Herbert's original patch had:
5211 * smp_mb__after_netif_stop_queue();
5212 * but since that doesn't exist yet, just open code it. */
5213 smp_mb();
5214
5215 /* We need to check again in a case another CPU has just
5216 * made room available. */
5217 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5218 return -EBUSY;
5219
5220 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5221 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5222 ++adapter->restart_queue;
5223 return 0;
5224}
5225
5226static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5227 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5228{
5229 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5230 return 0;
5231 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5232}
5233
09a3b1f8
SH		 5234static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5235{
5236 struct ixgbe_adapter *adapter = netdev_priv(dev);
5237
c4cf55e5
PWJ		 5238 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5239 return smp_processor_id();
5240
09a3b1f8 5241 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
36e89d73 5242 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
09a3b1f8
SH		 5243
5244 return skb_tx_hash(dev, skb);
5245}
5246
3b29a56d
SH		 5247static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5248 struct net_device *netdev)
9a799d71
AK		 5249{
5250 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5251 struct ixgbe_ring *tx_ring;
9a799d71
AK		 5252 unsigned int first;
5253 unsigned int tx_flags = 0;
30eba97a
AV		 5254 u8 hdr_len = 0;
5255 int r_idx = 0, tso;
9a799d71
AK		 5256 int count = 0;
5257 unsigned int f;
9f8cdf4f 5258
9f8cdf4f
JB		 5259 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5260 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5261 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5262 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5263 tx_flags |= (skb->queue_mapping << 13);
5264 }
5265 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5266 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5267 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
60127865
LL		 5268 if (skb->priority != TC_PRIO_CONTROL) {
5269 tx_flags |= (skb->queue_mapping << 13);
5270 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5271 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5272 } else {
5273 skb->queue_mapping =
5274 adapter->ring_feature[RING_F_DCB].indices-1;
5275 }
9a799d71 5276 }
eacd73f7 5277
60127865
LL		 5278 r_idx = skb->queue_mapping;
5279 tx_ring = &adapter->tx_ring[r_idx];
5280
eacd73f7 5281 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
09ad1cc0 5282 (skb->protocol == htons(ETH_P_FCOE))) {
eacd73f7 5283 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0
YZ		 5284#ifdef IXGBE_FCOE
5285 r_idx = smp_processor_id();
5286 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5287 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5288 tx_ring = &adapter->tx_ring[r_idx];
5289#endif
5290 }
eacd73f7 5291 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5292 if (skb_is_gso(skb) ||
5293 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5294 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5295 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5296 count++;
5297
9f8cdf4f
JB		 5298 count += TXD_USE_COUNT(skb_headlen(skb));
5299 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5300 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5301
e092be60 5302 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5303 adapter->tx_busy++;
9a799d71
AK		 5304 return NETDEV_TX_BUSY;
5305 }
9a799d71 5306
9a799d71 5307 first = tx_ring->next_to_use;
eacd73f7
YZ		 5308 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5309#ifdef IXGBE_FCOE
5310 /* setup tx offload for FCoE */
5311 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5312 if (tso < 0) {
5313 dev_kfree_skb_any(skb);
5314 return NETDEV_TX_OK;
5315 }
5316 if (tso)
5317 tx_flags |= IXGBE_TX_FLAGS_FSO;
5318#endif /* IXGBE_FCOE */
5319 } else {
5320 if (skb->protocol == htons(ETH_P_IP))
5321 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5322 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5323 if (tso < 0) {
5324 dev_kfree_skb_any(skb);
5325 return NETDEV_TX_OK;
5326 }
9a799d71 5327
eacd73f7
YZ		 5328 if (tso)
5329 tx_flags |= IXGBE_TX_FLAGS_TSO;
5330 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5331 (skb->ip_summed == CHECKSUM_PARTIAL))
5332 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5333 }
9a799d71 5334
eacd73f7 5335 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5336 if (count) {
c4cf55e5
PWJ		 5337 /* add the ATR filter if ATR is on */
5338 if (tx_ring->atr_sample_rate) {
5339 ++tx_ring->atr_count;
5340 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5341 test_bit(__IXGBE_FDIR_INIT_DONE,
5342 &tx_ring->reinit_state)) {
5343 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5344 tx_flags);
5345 tx_ring->atr_count = 0;
5346 }
5347 }
44df32c5
AD		 5348 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5349 hdr_len);
44df32c5 5350 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5351
44df32c5
AD		 5352 } else {
5353 dev_kfree_skb_any(skb);
5354 tx_ring->tx_buffer_info[first].time_stamp = 0;
5355 tx_ring->next_to_use = first;
5356 }
9a799d71
AK		 5357
5358 return NETDEV_TX_OK;
5359}
5360
5361/**
5362 * ixgbe_get_stats - Get System Network Statistics
5363 * @netdev: network interface device structure
5364 *
5365 * Returns the address of the device statistics structure.
5366 * The statistics are actually updated from the timer callback.
5367 **/
5368static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5369{
9a799d71 5370 /* only return the current stats */
2d86f139 5371 return &netdev->stats;
9a799d71
AK		 5372}
5373
5374/**
5375 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5376 * @netdev: network interface device structure
5377 * @p: pointer to an address structure
5378 *
5379 * Returns 0 on success, negative on failure
5380 **/
5381static int ixgbe_set_mac(struct net_device *netdev, void *p)
5382{
5383 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5384 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5385 struct sockaddr *addr = p;
5386
5387 if (!is_valid_ether_addr(addr->sa_data))
5388 return -EADDRNOTAVAIL;
5389
5390 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5391 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5392
b4617240 5393 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 5394
5395 return 0;
5396}
5397
6b73e10d
BH		 5398static int
5399ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5400{
5401 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5402 struct ixgbe_hw *hw = &adapter->hw;
5403 u16 value;
5404 int rc;
5405
5406 if (prtad != hw->phy.mdio.prtad)
5407 return -EINVAL;
5408 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5409 if (!rc)
5410 rc = value;
5411 return rc;
5412}
5413
5414static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5415 u16 addr, u16 value)
5416{
5417 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5418 struct ixgbe_hw *hw = &adapter->hw;
5419
5420 if (prtad != hw->phy.mdio.prtad)
5421 return -EINVAL;
5422 return hw->phy.ops.write_reg(hw, addr, devad, value);
5423}
5424
5425static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5426{
5427 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5428
5429 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5430}
5431
0365e6e4
PW		 5432/**
5433 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5434 * netdev->dev_addrs
0365e6e4
PW		 5435 * @netdev: network interface device structure
5436 *
5437 * Returns non-zero on failure
5438 **/
5439static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5440{
5441 int err = 0;
5442 struct ixgbe_adapter *adapter = netdev_priv(dev);
5443 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5444
5445 if (is_valid_ether_addr(mac->san_addr)) {
5446 rtnl_lock();
5447 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5448 rtnl_unlock();
5449 }
5450 return err;
5451}
5452
5453/**
5454 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5455 * netdev->dev_addrs
0365e6e4
PW		 5456 * @netdev: network interface device structure
5457 *
5458 * Returns non-zero on failure
5459 **/
5460static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5461{
5462 int err = 0;
5463 struct ixgbe_adapter *adapter = netdev_priv(dev);
5464 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5465
5466 if (is_valid_ether_addr(mac->san_addr)) {
5467 rtnl_lock();
5468 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5469 rtnl_unlock();
5470 }
5471 return err;
5472}
5473
9a799d71
AK		 5474#ifdef CONFIG_NET_POLL_CONTROLLER
5475/*
5476 * Polling 'interrupt' - used by things like netconsole to send skbs
5477 * without having to re-enable interrupts. It's not called while
5478 * the interrupt routine is executing.
5479 */
5480static void ixgbe_netpoll(struct net_device *netdev)
5481{
5482 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5483 int i;
9a799d71 5484
9a799d71 5485 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5486 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5487 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5488 for (i = 0; i < num_q_vectors; i++) {
5489 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5490 ixgbe_msix_clean_many(0, q_vector);
5491 }
5492 } else {
5493 ixgbe_intr(adapter->pdev->irq, netdev);
5494 }
9a799d71 5495 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5496}
5497#endif
5498
0edc3527
SH		 5499static const struct net_device_ops ixgbe_netdev_ops = {
5500 .ndo_open = ixgbe_open,
5501 .ndo_stop = ixgbe_close,
00829823 5502 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5503 .ndo_select_queue = ixgbe_select_queue,
0edc3527 5504 .ndo_get_stats = ixgbe_get_stats,
e90d400c 5505 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5506 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5507 .ndo_validate_addr = eth_validate_addr,
5508 .ndo_set_mac_address = ixgbe_set_mac,
5509 .ndo_change_mtu = ixgbe_change_mtu,
5510 .ndo_tx_timeout = ixgbe_tx_timeout,
5511 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5512 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5513 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5514 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5515#ifdef CONFIG_NET_POLL_CONTROLLER
5516 .ndo_poll_controller = ixgbe_netpoll,
5517#endif
332d4a7d
YZ		 5518#ifdef IXGBE_FCOE
5519 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5520 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 5521 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5522 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 5523 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 5524#endif /* IXGBE_FCOE */
0edc3527
SH		 5525};
5526
9a799d71
AK		 5527/**
5528 * ixgbe_probe - Device Initialization Routine
5529 * @pdev: PCI device information struct
5530 * @ent: entry in ixgbe_pci_tbl
5531 *
5532 * Returns 0 on success, negative on failure
5533 *
5534 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5535 * The OS initialization, configuring of the adapter private structure,
5536 * and a hardware reset occur.
5537 **/
5538static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5539 const struct pci_device_id *ent)
9a799d71
AK		 5540{
5541 struct net_device *netdev;
5542 struct ixgbe_adapter *adapter = NULL;
5543 struct ixgbe_hw *hw;
5544 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5545 static int cards_found;
5546 int i, err, pci_using_dac;
eacd73f7
YZ		 5547#ifdef IXGBE_FCOE
5548 u16 device_caps;
5549#endif
c44ade9e 5550 u32 part_num, eec;
9a799d71 5551
9ce77666 5552 err = pci_enable_device_mem(pdev);
9a799d71
AK		 5553 if (err)
5554 return err;
5555
6a35528a
YH		 5556 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5557 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 5558 pci_using_dac = 1;
5559 } else {
284901a9 5560 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5561 if (err) {
284901a9 5562 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5563 if (err) {
b4617240
PW		 5564 dev_err(&pdev->dev, "No usable DMA "
5565 "configuration, aborting\n");
9a799d71
AK		 5566 goto err_dma;
5567 }
5568 }
5569 pci_using_dac = 0;
5570 }
5571
9ce77666 5572 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5573 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 5574 if (err) {
9ce77666 5575 dev_err(&pdev->dev,
5576 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 5577 goto err_pci_reg;
5578 }
5579
19d5afd4 5580 pci_enable_pcie_error_reporting(pdev);
6fabd715 5581
9a799d71 5582 pci_set_master(pdev);
fb3b27bc 5583 pci_save_state(pdev);
9a799d71 5584
30eba97a 5585 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 5586 if (!netdev) {
5587 err = -ENOMEM;
5588 goto err_alloc_etherdev;
5589 }
5590
9a799d71
AK		 5591 SET_NETDEV_DEV(netdev, &pdev->dev);
5592
5593 pci_set_drvdata(pdev, netdev);
5594 adapter = netdev_priv(netdev);
5595
5596 adapter->netdev = netdev;
5597 adapter->pdev = pdev;
5598 hw = &adapter->hw;
5599 hw->back = adapter;
5600 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5601
05857980
JK		 5602 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5603 pci_resource_len(pdev, 0));
9a799d71
AK		 5604 if (!hw->hw_addr) {
5605 err = -EIO;
5606 goto err_ioremap;
5607 }
5608
5609 for (i = 1; i <= 5; i++) {
5610 if (pci_resource_len(pdev, i) == 0)
5611 continue;
5612 }
5613
0edc3527 5614 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 5615 ixgbe_set_ethtool_ops(netdev);
9a799d71 5616 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 5617 strcpy(netdev->name, pci_name(pdev));
5618
9a799d71
AK		 5619 adapter->bd_number = cards_found;
5620
9a799d71
AK		 5621 /* Setup hw api */
5622 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 5623 hw->mac.type = ii->mac;
9a799d71 5624
c44ade9e
JB		 5625 /* EEPROM */
5626 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5627 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5628 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5629 if (!(eec & (1 << 8)))
5630 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5631
5632 /* PHY */
5633 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 5634 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 5635 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5636 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5637 hw->phy.mdio.mmds = 0;
5638 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5639 hw->phy.mdio.dev = netdev;
5640 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5641 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 5642
5643 /* set up this timer and work struct before calling get_invariants
5644 * which might start the timer
5645 */
5646 init_timer(&adapter->sfp_timer);
5647 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5648 adapter->sfp_timer.data = (unsigned long) adapter;
5649
5650 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 5651
e8e26350
PW		 5652 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5653 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5654
5655 /* a new SFP+ module arrival, called from GPI SDP2 context */
5656 INIT_WORK(&adapter->sfp_config_module_task,
5657 ixgbe_sfp_config_module_task);
5658
8ca783ab 5659 ii->get_invariants(hw);
9a799d71
AK		 5660
5661 /* setup the private structure */
5662 err = ixgbe_sw_init(adapter);
5663 if (err)
5664 goto err_sw_init;
5665
bf069c97
DS		 5666 /*
5667 * If there is a fan on this device and it has failed log the
5668 * failure.
5669 */
5670 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5671 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5672 if (esdp & IXGBE_ESDP_SDP1)
5673 DPRINTK(PROBE, CRIT,
5674 "Fan has stopped, replace the adapter\n");
5675 }
5676
c44ade9e
JB		 5677 /* reset_hw fills in the perm_addr as well */
5678 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 5679 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5680 hw->mac.type == ixgbe_mac_82598EB) {
5681 /*
5682 * Start a kernel thread to watch for a module to arrive.
5683 * Only do this for 82598, since 82599 will generate
5684 * interrupts on module arrival.
5685 */
5686 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5687 mod_timer(&adapter->sfp_timer,
5688 round_jiffies(jiffies + (2 * HZ)));
5689 err = 0;
5690 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5691 dev_err(&adapter->pdev->dev, "failed to initialize because "
5692 "an unsupported SFP+ module type was detected.\n"
5693 "Reload the driver after installing a supported "
5694 "module.\n");
04f165ef
PW		 5695 goto err_sw_init;
5696 } else if (err) {
c44ade9e
JB		 5697 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5698 goto err_sw_init;
5699 }
5700
9a799d71 5701 netdev->features = NETIF_F_SG |
b4617240
PW		 5702 NETIF_F_IP_CSUM |
5703 NETIF_F_HW_VLAN_TX |
5704 NETIF_F_HW_VLAN_RX |
5705 NETIF_F_HW_VLAN_FILTER;
9a799d71 5706
e9990a9c 5707 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 5708 netdev->features |= NETIF_F_TSO;
9a799d71 5709 netdev->features |= NETIF_F_TSO6;
78b6f4ce 5710 netdev->features |= NETIF_F_GRO;
ad31c402 5711
45a5ead0
JB		 5712 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5713 netdev->features |= NETIF_F_SCTP_CSUM;
5714
ad31c402
JK		 5715 netdev->vlan_features |= NETIF_F_TSO;
5716 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 5717 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 5718 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 5719 netdev->vlan_features |= NETIF_F_SG;
5720
2f90b865
AD		 5721 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5722 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5723
7a6b6f51 5724#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5725 netdev->dcbnl_ops = &dcbnl_ops;
5726#endif
5727
eacd73f7 5728#ifdef IXGBE_FCOE
0d551589 5729 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 5730 if (hw->mac.ops.get_device_caps) {
5731 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 5732 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5733 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 5734 }
5735 }
5736#endif /* IXGBE_FCOE */
9a799d71
AK		 5737 if (pci_using_dac)
5738 netdev->features |= NETIF_F_HIGHDMA;
5739
0c19d6af 5740 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 5741 netdev->features |= NETIF_F_LRO;
5742
9a799d71 5743 /* make sure the EEPROM is good */
c44ade9e 5744 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 5745 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5746 err = -EIO;
5747 goto err_eeprom;
5748 }
5749
5750 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5751 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5752
c44ade9e
JB		 5753 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5754 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 5755 err = -EIO;
5756 goto err_eeprom;
5757 }
5758
5759 init_timer(&adapter->watchdog_timer);
5760 adapter->watchdog_timer.function = &ixgbe_watchdog;
5761 adapter->watchdog_timer.data = (unsigned long)adapter;
5762
5763 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 5764 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 5765
021230d4
AV		 5766 err = ixgbe_init_interrupt_scheme(adapter);
5767 if (err)
5768 goto err_sw_init;
9a799d71 5769
e8e26350
PW		 5770 switch (pdev->device) {
5771 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 5772 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5773 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
bdf0a550
PWJ		 5774 /* Enable ACPI wakeup in GRC */
5775 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5776 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
e8e26350
PW		 5777 break;
5778 default:
5779 adapter->wol = 0;
5780 break;
5781 }
e8e26350
PW		 5782 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5783
04f165ef
PW		 5784 /* pick up the PCI bus settings for reporting later */
5785 hw->mac.ops.get_bus_info(hw);
5786
9a799d71 5787 /* print bus type/speed/width info */
7c510e4b 5788 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 5789 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5790 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5791 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5792 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5793 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 5794 "Unknown"),
7c510e4b 5795 netdev->dev_addr);
c44ade9e 5796 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 5797 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5798 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5799 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5800 (part_num >> 8), (part_num & 0xff));
5801 else
5802 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5803 hw->mac.type, hw->phy.type,
5804 (part_num >> 8), (part_num & 0xff));
9a799d71 5805
e8e26350 5806 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 5807 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 5808 "this card is not sufficient for optimal "
5809 "performance.\n");
0c254d86 5810 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 5811 "PCI-Express slot is required.\n");
0c254d86
AK		 5812 }
5813
34b0368c
PWJ		 5814 /* save off EEPROM version number */
5815 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5816
9a799d71 5817 /* reset the hardware with the new settings */
794caeb2 5818 err = hw->mac.ops.start_hw(hw);
c44ade9e 5819
794caeb2
PWJ		 5820 if (err == IXGBE_ERR_EEPROM_VERSION) {
5821 /* We are running on a pre-production device, log a warning */
5822 dev_warn(&pdev->dev, "This device is a pre-production "
5823 "adapter/LOM. Please be aware there may be issues "
5824 "associated with your hardware. If you are "
5825 "experiencing problems please contact your Intel or "
5826 "hardware representative who provided you with this "
5827 "hardware.\n");
5828 }
9a799d71
AK		 5829 strcpy(netdev->name, "eth%d");
5830 err = register_netdev(netdev);
5831 if (err)
5832 goto err_register;
5833
54386467
JB		 5834 /* carrier off reporting is important to ethtool even BEFORE open */
5835 netif_carrier_off(netdev);
5836
c4cf55e5
PWJ		 5837 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5838 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5839 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5840
5dd2d332 5841#ifdef CONFIG_IXGBE_DCA
652f093f 5842 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 5843 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 5844 ixgbe_setup_dca(adapter);
5845 }
5846#endif
0365e6e4
PW		 5847 /* add san mac addr to netdev */
5848 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 5849
5850 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5851 cards_found++;
5852 return 0;
5853
5854err_register:
5eba3699 5855 ixgbe_release_hw_control(adapter);
7a921c93 5856 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 5857err_sw_init:
5858err_eeprom:
c4900be0
DS		 5859 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5860 del_timer_sync(&adapter->sfp_timer);
5861 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5862 cancel_work_sync(&adapter->multispeed_fiber_task);
5863 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5864 iounmap(hw->hw_addr);
5865err_ioremap:
5866 free_netdev(netdev);
5867err_alloc_etherdev:
9ce77666 5868 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5869 IORESOURCE_MEM));
9a799d71
AK		 5870err_pci_reg:
5871err_dma:
5872 pci_disable_device(pdev);
5873 return err;
5874}
5875
5876/**
5877 * ixgbe_remove - Device Removal Routine
5878 * @pdev: PCI device information struct
5879 *
5880 * ixgbe_remove is called by the PCI subsystem to alert the driver
5881 * that it should release a PCI device. The could be caused by a
5882 * Hot-Plug event, or because the driver is going to be removed from
5883 * memory.
5884 **/
5885static void __devexit ixgbe_remove(struct pci_dev *pdev)
5886{
5887 struct net_device *netdev = pci_get_drvdata(pdev);
5888 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5889
5890 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5891 /* clear the module not found bit to make sure the worker won't
5892 * reschedule
5893 */
5894 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5895 del_timer_sync(&adapter->watchdog_timer);
5896
c4900be0
DS		 5897 del_timer_sync(&adapter->sfp_timer);
5898 cancel_work_sync(&adapter->watchdog_task);
5899 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5900 cancel_work_sync(&adapter->multispeed_fiber_task);
5901 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 5902 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5903 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5904 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 5905 flush_scheduled_work();
5906
5dd2d332 5907#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5908 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5909 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5910 dca_remove_requester(&pdev->dev);
5911 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5912 }
5913
5914#endif
332d4a7d
YZ		 5915#ifdef IXGBE_FCOE
5916 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5917 ixgbe_cleanup_fcoe(adapter);
5918
5919#endif /* IXGBE_FCOE */
0365e6e4
PW		 5920
5921 /* remove the added san mac */
5922 ixgbe_del_sanmac_netdev(netdev);
5923
c4900be0
DS		 5924 if (netdev->reg_state == NETREG_REGISTERED)
5925 unregister_netdev(netdev);
9a799d71 5926
7a921c93 5927 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 5928
021230d4 5929 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5930
5931 iounmap(adapter->hw.hw_addr);
9ce77666 5932 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5933 IORESOURCE_MEM));
9a799d71 5934
021230d4 5935 DPRINTK(PROBE, INFO, "complete\n");
021230d4 5936
9a799d71
AK		 5937 free_netdev(netdev);
5938
19d5afd4 5939 pci_disable_pcie_error_reporting(pdev);
6fabd715 5940
9a799d71
AK		 5941 pci_disable_device(pdev);
5942}
5943
5944/**
5945 * ixgbe_io_error_detected - called when PCI error is detected
5946 * @pdev: Pointer to PCI device
5947 * @state: The current pci connection state
5948 *
5949 * This function is called after a PCI bus error affecting
5950 * this device has been detected.
5951 */
5952static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 5953 pci_channel_state_t state)
9a799d71
AK		 5954{
5955 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5956 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5957
5958 netif_device_detach(netdev);
5959
3044b8d1
BL		 5960 if (state == pci_channel_io_perm_failure)
5961 return PCI_ERS_RESULT_DISCONNECT;
5962
9a799d71
AK		 5963 if (netif_running(netdev))
5964 ixgbe_down(adapter);
5965 pci_disable_device(pdev);
5966
b4617240 5967 /* Request a slot reset. */
9a799d71
AK		 5968 return PCI_ERS_RESULT_NEED_RESET;
5969}
5970
5971/**
5972 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5973 * @pdev: Pointer to PCI device
5974 *
5975 * Restart the card from scratch, as if from a cold-boot.
5976 */
5977static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5978{
5979 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5980 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 5981 pci_ers_result_t result;
5982 int err;
9a799d71 5983
9ce77666 5984 if (pci_enable_device_mem(pdev)) {
9a799d71 5985 DPRINTK(PROBE, ERR,
b4617240 5986 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 5987 result = PCI_ERS_RESULT_DISCONNECT;
5988 } else {
5989 pci_set_master(pdev);
5990 pci_restore_state(pdev);
c0e1f68b 5991 pci_save_state(pdev);
9a799d71 5992
dd4d8ca6 5993 pci_wake_from_d3(pdev, false);
9a799d71 5994
6fabd715 5995 ixgbe_reset(adapter);
88512539 5996 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 5997 result = PCI_ERS_RESULT_RECOVERED;
5998 }
5999
6000 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6001 if (err) {
6002 dev_err(&pdev->dev,
6003 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6004 /* non-fatal, continue */
6005 }
9a799d71 6006
6fabd715 6007 return result;
9a799d71
AK		 6008}
6009
6010/**
6011 * ixgbe_io_resume - called when traffic can start flowing again.
6012 * @pdev: Pointer to PCI device
6013 *
6014 * This callback is called when the error recovery driver tells us that
6015 * its OK to resume normal operation.
6016 */
6017static void ixgbe_io_resume(struct pci_dev *pdev)
6018{
6019 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6020 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6021
6022 if (netif_running(netdev)) {
6023 if (ixgbe_up(adapter)) {
6024 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6025 return;
6026 }
6027 }
6028
6029 netif_device_attach(netdev);
9a799d71
AK		 6030}
6031
6032static struct pci_error_handlers ixgbe_err_handler = {
6033 .error_detected = ixgbe_io_error_detected,
6034 .slot_reset = ixgbe_io_slot_reset,
6035 .resume = ixgbe_io_resume,
6036};
6037
6038static struct pci_driver ixgbe_driver = {
6039 .name = ixgbe_driver_name,
6040 .id_table = ixgbe_pci_tbl,
6041 .probe = ixgbe_probe,
6042 .remove = __devexit_p(ixgbe_remove),
6043#ifdef CONFIG_PM
6044 .suspend = ixgbe_suspend,
6045 .resume = ixgbe_resume,
6046#endif
6047 .shutdown = ixgbe_shutdown,
6048 .err_handler = &ixgbe_err_handler
6049};
6050
6051/**
6052 * ixgbe_init_module - Driver Registration Routine
6053 *
6054 * ixgbe_init_module is the first routine called when the driver is
6055 * loaded. All it does is register with the PCI subsystem.
6056 **/
6057static int __init ixgbe_init_module(void)
6058{
6059 int ret;
6060 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6061 ixgbe_driver_string, ixgbe_driver_version);
6062
6063 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6064
5dd2d332 6065#ifdef CONFIG_IXGBE_DCA
bd0362dd 6066 dca_register_notify(&dca_notifier);
bd0362dd 6067#endif
5dd2d332 6068
9a799d71
AK		 6069 ret = pci_register_driver(&ixgbe_driver);
6070 return ret;
6071}
b4617240 6072
9a799d71
AK		 6073module_init(ixgbe_init_module);
6074
6075/**
6076 * ixgbe_exit_module - Driver Exit Cleanup Routine
6077 *
6078 * ixgbe_exit_module is called just before the driver is removed
6079 * from memory.
6080 **/
6081static void __exit ixgbe_exit_module(void)
6082{
5dd2d332 6083#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6084 dca_unregister_notify(&dca_notifier);
6085#endif
9a799d71
AK		 6086 pci_unregister_driver(&ixgbe_driver);
6087}
bd0362dd 6088
5dd2d332 6089#ifdef CONFIG_IXGBE_DCA
bd0362dd 6090static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 6091 void *p)
bd0362dd
JC		 6092{
6093 int ret_val;
6094
6095 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 6096 __ixgbe_notify_dca);
bd0362dd
JC		 6097
6098 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6099}
b453368d 6100
5dd2d332 6101#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 6102#ifdef DEBUG
6103/**
6104 * ixgbe_get_hw_dev_name - return device name string
6105 * used by hardware layer to print debugging information
6106 **/
6107char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6108{
6109 struct ixgbe_adapter *adapter = hw->back;
6110 return adapter->netdev->name;
6111}
bd0362dd 6112
b453368d 6113#endif
9a799d71
AK		 6114module_exit(ixgbe_exit_module);
6115
6116/* ixgbe_main.c */
Linux kernel - Deliverables
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