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ixgbe: Introduce Multiqueue TX
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
43
44#include "ixgbe.h"
45#include "ixgbe_common.h"
46
47char ixgbe_driver_name[] = "ixgbe";
9c8eb720
SH		 48static const char ixgbe_driver_string[] =
49 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71
AK		 50
51#define DRV_VERSION "1.1.18"
9c8eb720
SH		 52const char ixgbe_driver_version[] = DRV_VERSION;
53static const char ixgbe_copyright[] =
54 "Copyright (c) 1999-2007 Intel Corporation.";
9a799d71
AK		 55
56static const struct ixgbe_info *ixgbe_info_tbl[] = {
3957d63d 57 [board_82598] = &ixgbe_82598_info,
9a799d71
AK		 58};
59
60/* ixgbe_pci_tbl - PCI Device ID Table
61 *
62 * Wildcard entries (PCI_ANY_ID) should come last
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static struct pci_device_id ixgbe_pci_tbl[] = {
69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 70 board_82598 },
9a799d71 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT_DUAL_PORT),
3957d63d 74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 76 board_82598 },
9a799d71
AK		 77
78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
82
83MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
84MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
85MODULE_LICENSE("GPL");
86MODULE_VERSION(DRV_VERSION);
87
88#define DEFAULT_DEBUG_LEVEL_SHIFT 3
89
5eba3699
AV		 90static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
91{
92 u32 ctrl_ext;
93
94 /* Let firmware take over control of h/w */
95 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
96 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
97 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
98}
99
100static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
101{
102 u32 ctrl_ext;
103
104 /* Let firmware know the driver has taken over */
105 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
106 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
107 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
108}
9a799d71
AK		 109
110#ifdef DEBUG
111/**
112 * ixgbe_get_hw_dev_name - return device name string
113 * used by hardware layer to print debugging information
114 **/
115char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
116{
117 struct ixgbe_adapter *adapter = hw->back;
118 struct net_device *netdev = adapter->netdev;
119 return netdev->name;
120}
121#endif
122
123static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
124 u8 msix_vector)
125{
126 u32 ivar, index;
127
128 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
129 index = (int_alloc_entry >> 2) & 0x1F;
130 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
131 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
132 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
134}
135
136static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
137 struct ixgbe_tx_buffer
138 *tx_buffer_info)
139{
140 if (tx_buffer_info->dma) {
141 pci_unmap_page(adapter->pdev,
142 tx_buffer_info->dma,
143 tx_buffer_info->length, PCI_DMA_TODEVICE);
144 tx_buffer_info->dma = 0;
145 }
146 if (tx_buffer_info->skb) {
147 dev_kfree_skb_any(tx_buffer_info->skb);
148 tx_buffer_info->skb = NULL;
149 }
150 /* tx_buffer_info must be completely set up in the transmit path */
151}
152
153static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
154 struct ixgbe_ring *tx_ring,
155 unsigned int eop,
156 union ixgbe_adv_tx_desc *eop_desc)
157{
158 /* Detect a transmit hang in hardware, this serializes the
159 * check with the clearing of time_stamp and movement of i */
160 adapter->detect_tx_hung = false;
161 if (tx_ring->tx_buffer_info[eop].dma &&
162 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
163 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
164 /* detected Tx unit hang */
165 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
166 " TDH <%x>\n"
167 " TDT <%x>\n"
168 " next_to_use <%x>\n"
169 " next_to_clean <%x>\n"
170 "tx_buffer_info[next_to_clean]\n"
171 " time_stamp <%lx>\n"
172 " next_to_watch <%x>\n"
173 " jiffies <%lx>\n"
174 " next_to_watch.status <%x>\n",
175 readl(adapter->hw.hw_addr + tx_ring->head),
176 readl(adapter->hw.hw_addr + tx_ring->tail),
177 tx_ring->next_to_use,
178 tx_ring->next_to_clean,
179 tx_ring->tx_buffer_info[eop].time_stamp,
180 eop, jiffies, eop_desc->wb.status);
181 return true;
182 }
183
184 return false;
185}
186
e092be60
AV		 187#define IXGBE_MAX_TXD_PWR 14
188#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
189
190/* Tx Descriptors needed, worst case */
191#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
192 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
193#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
194 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
195
9a799d71
AK		 196/**
197 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
198 * @adapter: board private structure
199 **/
200static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
201 struct ixgbe_ring *tx_ring)
202{
203 struct net_device *netdev = adapter->netdev;
204 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
205 struct ixgbe_tx_buffer *tx_buffer_info;
206 unsigned int i, eop;
207 bool cleaned = false;
e092be60 208 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
9a799d71
AK		 209
210 i = tx_ring->next_to_clean;
211 eop = tx_ring->tx_buffer_info[i].next_to_watch;
212 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
213 while (eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) {
e092be60
AV		 214 cleaned = false;
215 while (!cleaned) {
9a799d71
AK		 216 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
217 tx_buffer_info = &tx_ring->tx_buffer_info[i];
218 cleaned = (i == eop);
219
220 tx_ring->stats.bytes += tx_buffer_info->length;
e092be60
AV		 221 if (cleaned) {
222 struct sk_buff *skb = tx_buffer_info->skb;
e092be60
AV		 223 unsigned int segs, bytecount;
224 segs = skb_shinfo(skb)->gso_segs ?: 1;
225 /* multiply data chunks by size of headers */
226 bytecount = ((segs - 1) * skb_headlen(skb)) +
227 skb->len;
228 total_tx_packets += segs;
229 total_tx_bytes += bytecount;
e092be60 230 }
9a799d71
AK		 231 ixgbe_unmap_and_free_tx_resource(adapter,
232 tx_buffer_info);
233 tx_desc->wb.status = 0;
234
235 i++;
236 if (i == tx_ring->count)
237 i = 0;
238 }
239
240 tx_ring->stats.packets++;
241
242 eop = tx_ring->tx_buffer_info[i].next_to_watch;
243 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
244
245 /* weight of a sort for tx, avoid endless transmit cleanup */
e092be60 246 if (total_tx_packets >= tx_ring->work_limit)
9a799d71
AK		 247 break;
248 }
249
250 tx_ring->next_to_clean = i;
251
e092be60
AV		 252#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
253 if (total_tx_packets && netif_carrier_ok(netdev) &&
254 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD)) {
255 /* Make sure that anybody stopping the queue after this
256 * sees the new next_to_clean.
257 */
258 smp_mb();
30eba97a
AV		 259#ifdef CONFIG_NETDEVICES_MULTIQUEUE
260 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
261 !test_bit(__IXGBE_DOWN, &adapter->state)) {
262 netif_wake_subqueue(netdev, tx_ring->queue_index);
263 adapter->restart_queue++;
264 }
265#else
e092be60
AV		 266 if (netif_queue_stopped(netdev) &&
267 !test_bit(__IXGBE_DOWN, &adapter->state)) {
268 netif_wake_queue(netdev);
269 adapter->restart_queue++;
270 }
30eba97a 271#endif
e092be60 272 }
9a799d71
AK		 273
274 if (adapter->detect_tx_hung)
275 if (ixgbe_check_tx_hang(adapter, tx_ring, eop, eop_desc))
30eba97a
AV		 276#ifdef CONFIG_NETDEVICES_MULTIQUEUE
277 netif_stop_subqueue(netdev, tx_ring->queue_index);
278#else
9a799d71 279 netif_stop_queue(netdev);
30eba97a 280#endif
9a799d71 281
e092be60 282 if (total_tx_packets >= tx_ring->work_limit)
9a799d71
AK		 283 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->eims_value);
284
d2f4fbe2
AV		 285 adapter->net_stats.tx_bytes += total_tx_bytes;
286 adapter->net_stats.tx_packets += total_tx_packets;
e092be60 287 cleaned = total_tx_packets ? true : false;
9a799d71
AK		 288 return cleaned;
289}
290
291/**
292 * ixgbe_receive_skb - Send a completed packet up the stack
293 * @adapter: board private structure
294 * @skb: packet to send up
295 * @is_vlan: packet has a VLAN tag
296 * @tag: VLAN tag from descriptor
297 **/
298static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
299 struct sk_buff *skb, bool is_vlan,
300 u16 tag)
301{
302 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
303 if (adapter->vlgrp && is_vlan)
304 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
305 else
306 netif_receive_skb(skb);
307 } else {
308
309 if (adapter->vlgrp && is_vlan)
310 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
311 else
312 netif_rx(skb);
313 }
314}
315
e59bd25d
AV		 316/**
317 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
318 * @adapter: address of board private structure
319 * @status_err: hardware indication of status of receive
320 * @skb: skb currently being received and modified
321 **/
9a799d71
AK		 322static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
323 u32 status_err,
324 struct sk_buff *skb)
325{
326 skb->ip_summed = CHECKSUM_NONE;
327
e59bd25d 328 /* Ignore Checksum bit is set, or rx csum disabled */
9a799d71 329 if ((status_err & IXGBE_RXD_STAT_IXSM) ||
e59bd25d 330 !(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 331 return;
e59bd25d
AV		 332
333 /* if IP and error */
334 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
335 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 336 adapter->hw_csum_rx_error++;
337 return;
338 }
e59bd25d
AV		 339
340 if (!(status_err & IXGBE_RXD_STAT_L4CS))
341 return;
342
343 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
344 adapter->hw_csum_rx_error++;
345 return;
346 }
347
9a799d71 348 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 349 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 350 adapter->hw_csum_rx_good++;
351}
352
353/**
354 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
355 * @adapter: address of board private structure
356 **/
357static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
358 struct ixgbe_ring *rx_ring,
359 int cleaned_count)
360{
361 struct net_device *netdev = adapter->netdev;
362 struct pci_dev *pdev = adapter->pdev;
363 union ixgbe_adv_rx_desc *rx_desc;
364 struct ixgbe_rx_buffer *rx_buffer_info;
365 struct sk_buff *skb;
366 unsigned int i;
367 unsigned int bufsz = adapter->rx_buf_len + NET_IP_ALIGN;
368
369 i = rx_ring->next_to_use;
370 rx_buffer_info = &rx_ring->rx_buffer_info[i];
371
372 while (cleaned_count--) {
373 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
374
375 if (!rx_buffer_info->page &&
376 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
377 rx_buffer_info->page = alloc_page(GFP_ATOMIC);
378 if (!rx_buffer_info->page) {
379 adapter->alloc_rx_page_failed++;
380 goto no_buffers;
381 }
382 rx_buffer_info->page_dma =
383 pci_map_page(pdev, rx_buffer_info->page,
384 0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
385 }
386
387 if (!rx_buffer_info->skb) {
388 skb = netdev_alloc_skb(netdev, bufsz);
389
390 if (!skb) {
391 adapter->alloc_rx_buff_failed++;
392 goto no_buffers;
393 }
394
395 /*
396 * Make buffer alignment 2 beyond a 16 byte boundary
397 * this will result in a 16 byte aligned IP header after
398 * the 14 byte MAC header is removed
399 */
400 skb_reserve(skb, NET_IP_ALIGN);
401
402 rx_buffer_info->skb = skb;
403 rx_buffer_info->dma = pci_map_single(pdev, skb->data,
404 bufsz,
405 PCI_DMA_FROMDEVICE);
406 }
407 /* Refresh the desc even if buffer_addrs didn't change because
408 * each write-back erases this info. */
409 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
410 rx_desc->read.pkt_addr =
411 cpu_to_le64(rx_buffer_info->page_dma);
412 rx_desc->read.hdr_addr =
413 cpu_to_le64(rx_buffer_info->dma);
414 } else {
415 rx_desc->read.pkt_addr =
416 cpu_to_le64(rx_buffer_info->dma);
417 }
418
419 i++;
420 if (i == rx_ring->count)
421 i = 0;
422 rx_buffer_info = &rx_ring->rx_buffer_info[i];
423 }
424no_buffers:
425 if (rx_ring->next_to_use != i) {
426 rx_ring->next_to_use = i;
427 if (i-- == 0)
428 i = (rx_ring->count - 1);
429
430 /*
431 * Force memory writes to complete before letting h/w
432 * know there are new descriptors to fetch. (Only
433 * applicable for weak-ordered memory model archs,
434 * such as IA-64).
435 */
436 wmb();
437 writel(i, adapter->hw.hw_addr + rx_ring->tail);
438 }
439}
440
441static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
442 struct ixgbe_ring *rx_ring,
443 int *work_done, int work_to_do)
444{
445 struct net_device *netdev = adapter->netdev;
446 struct pci_dev *pdev = adapter->pdev;
447 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
448 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
449 struct sk_buff *skb;
450 unsigned int i;
451 u32 upper_len, len, staterr;
452 u16 hdr_info, vlan_tag;
453 bool is_vlan, cleaned = false;
454 int cleaned_count = 0;
d2f4fbe2 455 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 456
457 i = rx_ring->next_to_clean;
458 upper_len = 0;
459 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
460 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
461 rx_buffer_info = &rx_ring->rx_buffer_info[i];
462 is_vlan = (staterr & IXGBE_RXD_STAT_VP);
463 vlan_tag = le16_to_cpu(rx_desc->wb.upper.vlan);
464
465 while (staterr & IXGBE_RXD_STAT_DD) {
466 if (*work_done >= work_to_do)
467 break;
468 (*work_done)++;
469
470 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
471 hdr_info =
472 le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info);
473 len =
474 ((hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
475 IXGBE_RXDADV_HDRBUFLEN_SHIFT);
476 if (hdr_info & IXGBE_RXDADV_SPH)
477 adapter->rx_hdr_split++;
478 if (len > IXGBE_RX_HDR_SIZE)
479 len = IXGBE_RX_HDR_SIZE;
480 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
481 } else
482 len = le16_to_cpu(rx_desc->wb.upper.length);
483
484 cleaned = true;
485 skb = rx_buffer_info->skb;
486 prefetch(skb->data - NET_IP_ALIGN);
487 rx_buffer_info->skb = NULL;
488
489 if (len && !skb_shinfo(skb)->nr_frags) {
490 pci_unmap_single(pdev, rx_buffer_info->dma,
491 adapter->rx_buf_len + NET_IP_ALIGN,
492 PCI_DMA_FROMDEVICE);
493 skb_put(skb, len);
494 }
495
496 if (upper_len) {
497 pci_unmap_page(pdev, rx_buffer_info->page_dma,
498 PAGE_SIZE, PCI_DMA_FROMDEVICE);
499 rx_buffer_info->page_dma = 0;
500 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
501 rx_buffer_info->page, 0, upper_len);
502 rx_buffer_info->page = NULL;
503
504 skb->len += upper_len;
505 skb->data_len += upper_len;
506 skb->truesize += upper_len;
507 }
508
509 i++;
510 if (i == rx_ring->count)
511 i = 0;
512 next_buffer = &rx_ring->rx_buffer_info[i];
513
514 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
515 prefetch(next_rxd);
516
517 cleaned_count++;
518 if (staterr & IXGBE_RXD_STAT_EOP) {
519 rx_ring->stats.packets++;
520 rx_ring->stats.bytes += skb->len;
521 } else {
522 rx_buffer_info->skb = next_buffer->skb;
523 rx_buffer_info->dma = next_buffer->dma;
524 next_buffer->skb = skb;
525 adapter->non_eop_descs++;
526 goto next_desc;
527 }
528
529 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
530 dev_kfree_skb_irq(skb);
531 goto next_desc;
532 }
533
534 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 535
536 /* probably a little skewed due to removing CRC */
537 total_rx_bytes += skb->len;
538 total_rx_packets++;
539
9a799d71
AK		 540 skb->protocol = eth_type_trans(skb, netdev);
541 ixgbe_receive_skb(adapter, skb, is_vlan, vlan_tag);
542 netdev->last_rx = jiffies;
543
544next_desc:
545 rx_desc->wb.upper.status_error = 0;
546
547 /* return some buffers to hardware, one at a time is too slow */
548 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
549 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
550 cleaned_count = 0;
551 }
552
553 /* use prefetched values */
554 rx_desc = next_rxd;
555 rx_buffer_info = next_buffer;
556
557 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
558 is_vlan = (staterr & IXGBE_RXD_STAT_VP);
559 vlan_tag = le16_to_cpu(rx_desc->wb.upper.vlan);
560 }
561
562 rx_ring->next_to_clean = i;
563 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
564
565 if (cleaned_count)
566 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
567
d2f4fbe2
AV		 568 adapter->net_stats.rx_bytes += total_rx_bytes;
569 adapter->net_stats.rx_packets += total_rx_packets;
570
9a799d71
AK		 571 return cleaned;
572}
573
021230d4 574static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 575/**
576 * ixgbe_configure_msix - Configure MSI-X hardware
577 * @adapter: board private structure
578 *
579 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
580 * interrupts.
581 **/
582static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
583{
021230d4
AV		 584 struct ixgbe_q_vector *q_vector;
585 int i, j, q_vectors, v_idx, r_idx;
586 u32 mask;
9a799d71 587
021230d4 588 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 589
021230d4
AV		 590 /* Populate the IVAR table and set the ITR values to the
591 * corresponding register.
592 */
593 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
594 q_vector = &adapter->q_vector[v_idx];
595 /* XXX for_each_bit(...) */
596 r_idx = find_first_bit(q_vector->rxr_idx,
597 adapter->num_rx_queues);
598
599 for (i = 0; i < q_vector->rxr_count; i++) {
600 j = adapter->rx_ring[r_idx].reg_idx;
601 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
602 r_idx = find_next_bit(q_vector->rxr_idx,
603 adapter->num_rx_queues,
604 r_idx + 1);
605 }
606 r_idx = find_first_bit(q_vector->txr_idx,
607 adapter->num_tx_queues);
608
609 for (i = 0; i < q_vector->txr_count; i++) {
610 j = adapter->tx_ring[r_idx].reg_idx;
611 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
612 r_idx = find_next_bit(q_vector->txr_idx,
613 adapter->num_tx_queues,
614 r_idx + 1);
615 }
616
617 /* if this is a tx only vector use half the irq (tx) rate */
618 if (q_vector->txr_count && !q_vector->rxr_count)
619 q_vector->eitr = adapter->tx_eitr;
620 else
621 /* rx only or mixed */
622 q_vector->eitr = adapter->rx_eitr;
623
624 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
625 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 626 }
627
021230d4
AV		 628 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
629 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
630
631 /* set up to autoclear timer, lsc, and the vectors */
632 mask = IXGBE_EIMS_ENABLE_MASK;
633 mask &= ~IXGBE_EIMS_OTHER;
634 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 635}
636
637static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
638{
639 struct net_device *netdev = data;
640 struct ixgbe_adapter *adapter = netdev_priv(netdev);
641 struct ixgbe_hw *hw = &adapter->hw;
642 u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
643
644 if (eicr & IXGBE_EICR_LSC) {
645 adapter->lsc_int++;
646 if (!test_bit(__IXGBE_DOWN, &adapter->state))
647 mod_timer(&adapter->watchdog_timer, jiffies);
648 }
d4f80882
AV		 649
650 if (!test_bit(__IXGBE_DOWN, &adapter->state))
651 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 652
653 return IRQ_HANDLED;
654}
655
656static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
657{
021230d4
AV		 658 struct ixgbe_q_vector *q_vector = data;
659 struct ixgbe_adapter *adapter = q_vector->adapter;
660 struct ixgbe_ring *txr;
661 int i, r_idx;
662
663 if (!q_vector->txr_count)
664 return IRQ_HANDLED;
665
666 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
667 for (i = 0; i < q_vector->txr_count; i++) {
668 txr = &(adapter->tx_ring[r_idx]);
669 ixgbe_clean_tx_irq(adapter, txr);
670 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
671 r_idx + 1);
672 }
9a799d71 673
9a799d71
AK		 674
675 return IRQ_HANDLED;
676}
677
021230d4
AV		 678/**
679 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
680 * @irq: unused
681 * @data: pointer to our q_vector struct for this interrupt vector
682 **/
9a799d71
AK		 683static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
684{
021230d4
AV		 685 struct ixgbe_q_vector *q_vector = data;
686 struct ixgbe_adapter *adapter = q_vector->adapter;
687 struct ixgbe_ring *rxr;
688 int r_idx;
689
690 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
691 if (!q_vector->rxr_count)
692 return IRQ_HANDLED;
693
694 rxr = &(adapter->rx_ring[r_idx]);
695 /* disable interrupts on this vector only */
696 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rxr->v_idx);
697 netif_rx_schedule(adapter->netdev, &q_vector->napi);
698
699 return IRQ_HANDLED;
700}
701
702static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
703{
704 ixgbe_msix_clean_rx(irq, data);
705 ixgbe_msix_clean_tx(irq, data);
9a799d71 706
9a799d71
AK		 707 return IRQ_HANDLED;
708}
709
021230d4
AV		 710/**
711 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
712 * @napi: napi struct with our devices info in it
713 * @budget: amount of work driver is allowed to do this pass, in packets
714 *
715 **/
9a799d71
AK		 716static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
717{
021230d4
AV		 718 struct ixgbe_q_vector *q_vector =
719 container_of(napi, struct ixgbe_q_vector, napi);
720 struct ixgbe_adapter *adapter = q_vector->adapter;
721 struct ixgbe_ring *rxr;
9a799d71 722 int work_done = 0;
021230d4 723 long r_idx;
9a799d71 724
021230d4
AV		 725 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
726 rxr = &(adapter->rx_ring[r_idx]);
9a799d71
AK		 727
728 ixgbe_clean_rx_irq(adapter, rxr, &work_done, budget);
729
021230d4
AV		 730 /* If all Rx work done, exit the polling mode */
731 if (work_done < budget) {
732 netif_rx_complete(adapter->netdev, napi);
9a799d71 733 if (!test_bit(__IXGBE_DOWN, &adapter->state))
021230d4 734 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rxr->v_idx);
9a799d71
AK		 735 }
736
737 return work_done;
738}
739
021230d4
AV		 740static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
741 int r_idx)
742{
743 a->q_vector[v_idx].adapter = a;
744 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
745 a->q_vector[v_idx].rxr_count++;
746 a->rx_ring[r_idx].v_idx = 1 << v_idx;
747}
748
749static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
750 int r_idx)
751{
752 a->q_vector[v_idx].adapter = a;
753 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
754 a->q_vector[v_idx].txr_count++;
755 a->tx_ring[r_idx].v_idx = 1 << v_idx;
756}
757
9a799d71 758/**
021230d4
AV		 759 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
760 * @adapter: board private structure to initialize
761 * @vectors: allotted vector count for descriptor rings
9a799d71 762 *
021230d4
AV		 763 * This function maps descriptor rings to the queue-specific vectors
764 * we were allotted through the MSI-X enabling code. Ideally, we'd have
765 * one vector per ring/queue, but on a constrained vector budget, we
766 * group the rings as "efficiently" as possible. You would add new
767 * mapping configurations in here.
9a799d71 768 **/
021230d4
AV		 769static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
770 int vectors)
771{
772 int v_start = 0;
773 int rxr_idx = 0, txr_idx = 0;
774 int rxr_remaining = adapter->num_rx_queues;
775 int txr_remaining = adapter->num_tx_queues;
776 int i, j;
777 int rqpv, tqpv;
778 int err = 0;
779
780 /* No mapping required if MSI-X is disabled. */
781 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
782 goto out;
9a799d71 783
021230d4
AV		 784 /*
785 * The ideal configuration...
786 * We have enough vectors to map one per queue.
787 */
788 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
789 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
790 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 791
021230d4
AV		 792 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
793 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 794
9a799d71 795 goto out;
021230d4 796 }
9a799d71 797
021230d4
AV		 798 /*
799 * If we don't have enough vectors for a 1-to-1
800 * mapping, we'll have to group them so there are
801 * multiple queues per vector.
802 */
803 /* Re-adjusting *qpv takes care of the remainder. */
804 for (i = v_start; i < vectors; i++) {
805 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
806 for (j = 0; j < rqpv; j++) {
807 map_vector_to_rxq(adapter, i, rxr_idx);
808 rxr_idx++;
809 rxr_remaining--;
810 }
811 }
812 for (i = v_start; i < vectors; i++) {
813 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
814 for (j = 0; j < tqpv; j++) {
815 map_vector_to_txq(adapter, i, txr_idx);
816 txr_idx++;
817 txr_remaining--;
9a799d71 818 }
9a799d71
AK		 819 }
820
021230d4
AV		 821out:
822 return err;
823}
824
825/**
826 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
827 * @adapter: board private structure
828 *
829 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
830 * interrupts from the kernel.
831 **/
832static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
833{
834 struct net_device *netdev = adapter->netdev;
835 irqreturn_t (*handler)(int, void *);
836 int i, vector, q_vectors, err;
837
838 /* Decrement for Other and TCP Timer vectors */
839 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
840
841 /* Map the Tx/Rx rings to the vectors we were allotted. */
842 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
843 if (err)
844 goto out;
845
846#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
847 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
848 &ixgbe_msix_clean_many)
849 for (vector = 0; vector < q_vectors; vector++) {
850 handler = SET_HANDLER(&adapter->q_vector[vector]);
851 sprintf(adapter->name[vector], "%s:v%d-%s",
852 netdev->name, vector,
853 (handler == &ixgbe_msix_clean_rx) ? "Rx" :
854 ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx"));
855 err = request_irq(adapter->msix_entries[vector].vector,
856 handler, 0, adapter->name[vector],
857 &(adapter->q_vector[vector]));
9a799d71
AK		 858 if (err) {
859 DPRINTK(PROBE, ERR,
860 "request_irq failed for MSIX interrupt "
861 "Error: %d\n", err);
021230d4 862 goto free_queue_irqs;
9a799d71 863 }
9a799d71
AK		 864 }
865
021230d4
AV		 866 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
867 err = request_irq(adapter->msix_entries[vector].vector,
868 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 869 if (err) {
870 DPRINTK(PROBE, ERR,
871 "request_irq for msix_lsc failed: %d\n", err);
021230d4 872 goto free_queue_irqs;
9a799d71
AK		 873 }
874
9a799d71
AK		 875 return 0;
876
021230d4
AV		 877free_queue_irqs:
878 for (i = vector - 1; i >= 0; i--)
879 free_irq(adapter->msix_entries[--vector].vector,
880 &(adapter->q_vector[i]));
881 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
882 pci_disable_msix(adapter->pdev);
9a799d71
AK		 883 kfree(adapter->msix_entries);
884 adapter->msix_entries = NULL;
021230d4 885out:
9a799d71
AK		 886 return err;
887}
888
021230d4
AV		 889static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter);
890
9a799d71 891/**
021230d4 892 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 893 * @irq: interrupt number
894 * @data: pointer to a network interface device structure
895 * @pt_regs: CPU registers structure
896 **/
897static irqreturn_t ixgbe_intr(int irq, void *data)
898{
899 struct net_device *netdev = data;
900 struct ixgbe_adapter *adapter = netdev_priv(netdev);
901 struct ixgbe_hw *hw = &adapter->hw;
902 u32 eicr;
903
9a799d71 904
021230d4
AV		 905 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
906 * therefore no explict interrupt disable is necessary */
907 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
9a799d71
AK		 908 if (!eicr)
909 return IRQ_NONE; /* Not our interrupt */
910
911 if (eicr & IXGBE_EICR_LSC) {
912 adapter->lsc_int++;
913 if (!test_bit(__IXGBE_DOWN, &adapter->state))
914 mod_timer(&adapter->watchdog_timer, jiffies);
915 }
021230d4
AV		 916
917
918 if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) {
919 /* would disable interrupts here but EIAM disabled it */
920 __netif_rx_schedule(netdev, &adapter->q_vector[0].napi);
9a799d71
AK		 921 }
922
923 return IRQ_HANDLED;
924}
925
021230d4
AV		 926static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
927{
928 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
929
930 for (i = 0; i < q_vectors; i++) {
931 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
932 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
933 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
934 q_vector->rxr_count = 0;
935 q_vector->txr_count = 0;
936 }
937}
938
9a799d71
AK		 939/**
940 * ixgbe_request_irq - initialize interrupts
941 * @adapter: board private structure
942 *
943 * Attempts to configure interrupts using the best available
944 * capabilities of the hardware and kernel.
945 **/
021230d4 946static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 947{
948 struct net_device *netdev = adapter->netdev;
021230d4 949 int err;
9a799d71 950
021230d4
AV		 951 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
952 err = ixgbe_request_msix_irqs(adapter);
953 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
954 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
955 netdev->name, netdev);
956 } else {
957 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
958 netdev->name, netdev);
9a799d71
AK		 959 }
960
9a799d71
AK		 961 if (err)
962 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
963
9a799d71
AK		 964 return err;
965}
966
967static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
968{
969 struct net_device *netdev = adapter->netdev;
970
971 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 972 int i, q_vectors;
9a799d71 973
021230d4
AV		 974 q_vectors = adapter->num_msix_vectors;
975
976 i = q_vectors - 1;
9a799d71 977 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 978
021230d4
AV		 979 i--;
980 for (; i >= 0; i--) {
981 free_irq(adapter->msix_entries[i].vector,
982 &(adapter->q_vector[i]));
983 }
984
985 ixgbe_reset_q_vectors(adapter);
986 } else {
987 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 988 }
989}
990
991/**
992 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
993 * @adapter: board private structure
994 **/
995static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
996{
9a799d71
AK		 997 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
998 IXGBE_WRITE_FLUSH(&adapter->hw);
021230d4
AV		 999 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1000 int i;
1001 for (i = 0; i < adapter->num_msix_vectors; i++)
1002 synchronize_irq(adapter->msix_entries[i].vector);
1003 } else {
1004 synchronize_irq(adapter->pdev->irq);
1005 }
9a799d71
AK		 1006}
1007
1008/**
1009 * ixgbe_irq_enable - Enable default interrupt generation settings
1010 * @adapter: board private structure
1011 **/
1012static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1013{
021230d4
AV		 1014 u32 mask;
1015 mask = IXGBE_EIMS_ENABLE_MASK;
1016 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
d4f80882 1017 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1018}
1019
1020/**
1021 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1022 *
1023 **/
1024static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1025{
9a799d71
AK		 1026 struct ixgbe_hw *hw = &adapter->hw;
1027
021230d4
AV		 1028 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1029 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr));
9a799d71
AK		 1030
1031 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
021230d4
AV		 1032 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1033
1034 map_vector_to_rxq(adapter, 0, 0);
1035 map_vector_to_txq(adapter, 0, 0);
1036
1037 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1038}
1039
1040/**
1041 * ixgbe_configure_tx - Configure 8254x Transmit Unit after Reset
1042 * @adapter: board private structure
1043 *
1044 * Configure the Tx unit of the MAC after a reset.
1045 **/
1046static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1047{
1048 u64 tdba;
1049 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1050 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1051
1052 /* Setup the HW Tx Head and Tail descriptor pointers */
1053 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4 1054 j = adapter->tx_ring[i].reg_idx;
9a799d71
AK		 1055 tdba = adapter->tx_ring[i].dma;
1056 tdlen = adapter->tx_ring[i].count *
021230d4
AV		 1057 sizeof(union ixgbe_adv_tx_desc);
1058 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1059 (tdba & DMA_32BIT_MASK));
1060 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1061 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1062 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1063 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1064 adapter->tx_ring[i].head = IXGBE_TDH(j);
1065 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1066 /* Disable Tx Head Writeback RO bit, since this hoses
1067 * bookkeeping if things aren't delivered in order.
1068 */
1069 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
1070 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1071 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), txctrl);
9a799d71 1072 }
9a799d71
AK		 1073}
1074
1075#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1076 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1077
1078#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1079/**
1080 * ixgbe_configure_rx - Configure 8254x Receive Unit after Reset
1081 * @adapter: board private structure
1082 *
1083 * Configure the Rx unit of the MAC after a reset.
1084 **/
1085static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1086{
1087 u64 rdba;
1088 struct ixgbe_hw *hw = &adapter->hw;
1089 struct net_device *netdev = adapter->netdev;
1090 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1091 int i, j;
9a799d71
AK		 1092 u32 rdlen, rxctrl, rxcsum;
1093 u32 random[10];
9a799d71 1094 u32 fctrl, hlreg0;
9a799d71 1095 u32 pages;
021230d4 1096 u32 reta = 0, mrqc, srrctl;
9a799d71
AK		 1097
1098 /* Decide whether to use packet split mode or not */
1099 if (netdev->mtu > ETH_DATA_LEN)
1100 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1101 else
1102 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1103
1104 /* Set the RX buffer length according to the mode */
1105 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1106 adapter->rx_buf_len = IXGBE_RX_HDR_SIZE;
1107 } else {
1108 if (netdev->mtu <= ETH_DATA_LEN)
1109 adapter->rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1110 else
1111 adapter->rx_buf_len = ALIGN(max_frame, 1024);
1112 }
1113
1114 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1115 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1116 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
9a799d71
AK		 1117 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1118
1119 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1120 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1121 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1122 else
1123 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1124 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1125
1126 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1127
1128 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(0));
1129 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1130 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1131
1132 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1133 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1134 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1135 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1136 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1137 IXGBE_SRRCTL_BSIZEHDR_MASK);
1138 } else {
1139 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1140
1141 if (adapter->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1142 srrctl |=
1143 IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1144 else
1145 srrctl |=
1146 adapter->rx_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1147 }
1148 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(0), srrctl);
1149
1150 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1151 /* disable receives while setting up the descriptors */
1152 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1153 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1154
1155 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1156 * the Base and Length of the Rx Descriptor Ring */
1157 for (i = 0; i < adapter->num_rx_queues; i++) {
1158 rdba = adapter->rx_ring[i].dma;
1159 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(i), (rdba & DMA_32BIT_MASK));
1160 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(i), (rdba >> 32));
1161 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(i), rdlen);
1162 IXGBE_WRITE_REG(hw, IXGBE_RDH(i), 0);
1163 IXGBE_WRITE_REG(hw, IXGBE_RDT(i), 0);
1164 adapter->rx_ring[i].head = IXGBE_RDH(i);
1165 adapter->rx_ring[i].tail = IXGBE_RDT(i);
1166 }
1167
021230d4 1168 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1169 /* Fill out redirection table */
021230d4
AV		 1170 for (i = 0, j = 0; i < 128; i++, j++) {
1171 if (j == adapter->ring_feature[RING_F_RSS].indices)
1172 j = 0;
1173 /* reta = 4-byte sliding window of
1174 * 0x00..(indices-1)(indices-1)00..etc. */
1175 reta = (reta << 8) | (j * 0x11);
1176 if ((i & 3) == 3)
1177 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1178 }
1179
1180 /* Fill out hash function seeds */
021230d4
AV		 1181 /* XXX use a random constant here to glue certain flows */
1182 get_random_bytes(&random[0], 40);
9a799d71 1183 for (i = 0; i < 10; i++)
021230d4 1184 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), random[i]);
9a799d71
AK		 1185
1186 mrqc = IXGBE_MRQC_RSSEN
1187 /* Perform hash on these packet types */
1188 | IXGBE_MRQC_RSS_FIELD_IPV4
1189 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1190 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1191 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1192 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1193 | IXGBE_MRQC_RSS_FIELD_IPV6
1194 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1195 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1196 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
1197 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
021230d4 1198 }
9a799d71 1199
021230d4
AV		 1200 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1201
1202 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1203 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1204 /* Disable indicating checksum in descriptor, enables
1205 * RSS hash */
9a799d71 1206 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1207 }
021230d4
AV		 1208 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1209 /* Enable IPv4 payload checksum for UDP fragments
1210 * if PCSD is not set */
1211 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1212 }
1213
1214 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
9a799d71
AK		 1215}
1216
1217static void ixgbe_vlan_rx_register(struct net_device *netdev,
1218 struct vlan_group *grp)
1219{
1220 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1221 u32 ctrl;
1222
d4f80882
AV		 1223 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1224 ixgbe_irq_disable(adapter);
9a799d71
AK		 1225 adapter->vlgrp = grp;
1226
1227 if (grp) {
1228 /* enable VLAN tag insert/strip */
1229 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1230 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1231 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1232 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1233 }
1234
d4f80882
AV		 1235 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1236 ixgbe_irq_enable(adapter);
9a799d71
AK		 1237}
1238
1239static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1240{
1241 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1242
1243 /* add VID to filter table */
1244 ixgbe_set_vfta(&adapter->hw, vid, 0, true);
1245}
1246
1247static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1248{
1249 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1250
d4f80882
AV		 1251 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1252 ixgbe_irq_disable(adapter);
1253
9a799d71 1254 vlan_group_set_device(adapter->vlgrp, vid, NULL);
d4f80882
AV		 1255
1256 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1257 ixgbe_irq_enable(adapter);
9a799d71
AK		 1258
1259 /* remove VID from filter table */
1260 ixgbe_set_vfta(&adapter->hw, vid, 0, false);
1261}
1262
1263static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1264{
1265 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1266
1267 if (adapter->vlgrp) {
1268 u16 vid;
1269 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1270 if (!vlan_group_get_device(adapter->vlgrp, vid))
1271 continue;
1272 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1273 }
1274 }
1275}
1276
1277/**
1278 * ixgbe_set_multi - Multicast and Promiscuous mode set
1279 * @netdev: network interface device structure
1280 *
1281 * The set_multi entry point is called whenever the multicast address
1282 * list or the network interface flags are updated. This routine is
1283 * responsible for configuring the hardware for proper multicast,
1284 * promiscuous mode, and all-multi behavior.
1285 **/
1286static void ixgbe_set_multi(struct net_device *netdev)
1287{
1288 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1289 struct ixgbe_hw *hw = &adapter->hw;
1290 struct dev_mc_list *mc_ptr;
1291 u8 *mta_list;
1292 u32 fctrl;
1293 int i;
1294
1295 /* Check for Promiscuous and All Multicast modes */
1296
1297 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1298
1299 if (netdev->flags & IFF_PROMISC) {
1300 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1301 } else if (netdev->flags & IFF_ALLMULTI) {
1302 fctrl |= IXGBE_FCTRL_MPE;
1303 fctrl &= ~IXGBE_FCTRL_UPE;
1304 } else {
1305 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1306 }
1307
1308 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1309
1310 if (netdev->mc_count) {
1311 mta_list = kcalloc(netdev->mc_count, ETH_ALEN, GFP_ATOMIC);
1312 if (!mta_list)
1313 return;
1314
1315 /* Shared function expects packed array of only addresses. */
1316 mc_ptr = netdev->mc_list;
1317
1318 for (i = 0; i < netdev->mc_count; i++) {
1319 if (!mc_ptr)
1320 break;
1321 memcpy(mta_list + (i * ETH_ALEN), mc_ptr->dmi_addr,
1322 ETH_ALEN);
1323 mc_ptr = mc_ptr->next;
1324 }
1325
1326 ixgbe_update_mc_addr_list(hw, mta_list, i, 0);
1327 kfree(mta_list);
1328 } else {
1329 ixgbe_update_mc_addr_list(hw, NULL, 0, 0);
1330 }
1331
1332}
1333
021230d4
AV		 1334static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1335{
1336 int q_idx;
1337 struct ixgbe_q_vector *q_vector;
1338 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1339
1340 /* legacy and MSI only use one vector */
1341 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1342 q_vectors = 1;
1343
1344 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1345 q_vector = &adapter->q_vector[q_idx];
1346 if (!q_vector->rxr_count)
1347 continue;
1348 napi_enable(&q_vector->napi);
1349 }
1350}
1351
1352static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1353{
1354 int q_idx;
1355 struct ixgbe_q_vector *q_vector;
1356 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1357
1358 /* legacy and MSI only use one vector */
1359 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1360 q_vectors = 1;
1361
1362 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1363 q_vector = &adapter->q_vector[q_idx];
1364 if (!q_vector->rxr_count)
1365 continue;
1366 napi_disable(&q_vector->napi);
1367 }
1368}
1369
1370
9a799d71
AK		 1371static void ixgbe_configure(struct ixgbe_adapter *adapter)
1372{
1373 struct net_device *netdev = adapter->netdev;
1374 int i;
1375
1376 ixgbe_set_multi(netdev);
1377
1378 ixgbe_restore_vlan(adapter);
1379
1380 ixgbe_configure_tx(adapter);
1381 ixgbe_configure_rx(adapter);
1382 for (i = 0; i < adapter->num_rx_queues; i++)
1383 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
1384 (adapter->rx_ring[i].count - 1));
1385}
1386
1387static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1388{
1389 struct net_device *netdev = adapter->netdev;
9a799d71 1390 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1391 int i, j = 0;
9a799d71 1392 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4
AV		 1393 u32 txdctl, rxdctl, mhadd;
1394 u32 gpie;
9a799d71 1395
5eba3699
AV		 1396 ixgbe_get_hw_control(adapter);
1397
021230d4
AV		 1398 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1399 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 1400 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1401 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
1402 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
1403 } else {
1404 /* MSI only */
021230d4 1405 gpie = 0;
9a799d71 1406 }
021230d4
AV		 1407 /* XXX: to interrupt immediately for EICS writes, enable this */
1408 /* gpie |= IXGBE_GPIE_EIMEN; */
1409 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 1410 }
1411
021230d4
AV		 1412 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1413 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1414 * specifically only auto mask tx and rx interrupts */
1415 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1416 }
9a799d71 1417
021230d4 1418 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 1419 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1420 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1421 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
1422
1423 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
1424 }
1425
1426 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 1427 j = adapter->tx_ring[i].reg_idx;
1428 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 1429 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 1430 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 1431 }
1432
1433 for (i = 0; i < adapter->num_rx_queues; i++) {
021230d4
AV		 1434 j = adapter->rx_ring[i].reg_idx;
1435 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
1436 /* enable PTHRESH=32 descriptors (half the internal cache)
1437 * and HTHRESH=0 descriptors (to minimize latency on fetch),
1438 * this also removes a pesky rx_no_buffer_count increment */
1439 rxdctl |= 0x0020;
9a799d71 1440 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 1441 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
9a799d71
AK		 1442 }
1443 /* enable all receives */
1444 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1445 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
1446 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
1447
1448 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1449 ixgbe_configure_msix(adapter);
1450 else
1451 ixgbe_configure_msi_and_legacy(adapter);
1452
1453 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 1454 ixgbe_napi_enable_all(adapter);
1455
1456 /* clear any pending interrupts, may auto mask */
1457 IXGBE_READ_REG(hw, IXGBE_EICR);
1458
9a799d71
AK		 1459 ixgbe_irq_enable(adapter);
1460
1461 /* bring the link up in the watchdog, this could race with our first
1462 * link up interrupt but shouldn't be a problem */
1463 mod_timer(&adapter->watchdog_timer, jiffies);
1464 return 0;
1465}
1466
d4f80882
AV		 1467void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
1468{
1469 WARN_ON(in_interrupt());
1470 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
1471 msleep(1);
1472 ixgbe_down(adapter);
1473 ixgbe_up(adapter);
1474 clear_bit(__IXGBE_RESETTING, &adapter->state);
1475}
1476
9a799d71
AK		 1477int ixgbe_up(struct ixgbe_adapter *adapter)
1478{
1479 /* hardware has been reset, we need to reload some things */
1480 ixgbe_configure(adapter);
1481
1482 return ixgbe_up_complete(adapter);
1483}
1484
1485void ixgbe_reset(struct ixgbe_adapter *adapter)
1486{
1487 if (ixgbe_init_hw(&adapter->hw))
1488 DPRINTK(PROBE, ERR, "Hardware Error\n");
1489
1490 /* reprogram the RAR[0] in case user changed it. */
1491 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
1492
1493}
1494
1495#ifdef CONFIG_PM
1496static int ixgbe_resume(struct pci_dev *pdev)
1497{
1498 struct net_device *netdev = pci_get_drvdata(pdev);
1499 struct ixgbe_adapter *adapter = netdev_priv(netdev);
021230d4 1500 u32 err;
9a799d71
AK		 1501
1502 pci_set_power_state(pdev, PCI_D0);
1503 pci_restore_state(pdev);
1504 err = pci_enable_device(pdev);
1505 if (err) {
1506 printk(KERN_ERR "ixgbe: Cannot enable PCI device from " \
1507 "suspend\n");
1508 return err;
1509 }
1510 pci_set_master(pdev);
1511
1512 pci_enable_wake(pdev, PCI_D3hot, 0);
1513 pci_enable_wake(pdev, PCI_D3cold, 0);
1514
1515 if (netif_running(netdev)) {
021230d4 1516 err = ixgbe_request_irq(adapter);
9a799d71
AK		 1517 if (err)
1518 return err;
1519 }
1520
1521 ixgbe_reset(adapter);
1522
1523 if (netif_running(netdev))
1524 ixgbe_up(adapter);
1525
1526 netif_device_attach(netdev);
1527
1528 return 0;
1529}
1530#endif
1531
1532/**
1533 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
1534 * @adapter: board private structure
1535 * @rx_ring: ring to free buffers from
1536 **/
1537static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
1538 struct ixgbe_ring *rx_ring)
1539{
1540 struct pci_dev *pdev = adapter->pdev;
1541 unsigned long size;
1542 unsigned int i;
1543
1544 /* Free all the Rx ring sk_buffs */
1545
1546 for (i = 0; i < rx_ring->count; i++) {
1547 struct ixgbe_rx_buffer *rx_buffer_info;
1548
1549 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1550 if (rx_buffer_info->dma) {
1551 pci_unmap_single(pdev, rx_buffer_info->dma,
1552 adapter->rx_buf_len,
1553 PCI_DMA_FROMDEVICE);
1554 rx_buffer_info->dma = 0;
1555 }
1556 if (rx_buffer_info->skb) {
1557 dev_kfree_skb(rx_buffer_info->skb);
1558 rx_buffer_info->skb = NULL;
1559 }
1560 if (!rx_buffer_info->page)
1561 continue;
1562 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE,
1563 PCI_DMA_FROMDEVICE);
1564 rx_buffer_info->page_dma = 0;
1565
1566 put_page(rx_buffer_info->page);
1567 rx_buffer_info->page = NULL;
1568 }
1569
1570 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1571 memset(rx_ring->rx_buffer_info, 0, size);
1572
1573 /* Zero out the descriptor ring */
1574 memset(rx_ring->desc, 0, rx_ring->size);
1575
1576 rx_ring->next_to_clean = 0;
1577 rx_ring->next_to_use = 0;
1578
1579 writel(0, adapter->hw.hw_addr + rx_ring->head);
1580 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1581}
1582
1583/**
1584 * ixgbe_clean_tx_ring - Free Tx Buffers
1585 * @adapter: board private structure
1586 * @tx_ring: ring to be cleaned
1587 **/
1588static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
1589 struct ixgbe_ring *tx_ring)
1590{
1591 struct ixgbe_tx_buffer *tx_buffer_info;
1592 unsigned long size;
1593 unsigned int i;
1594
1595 /* Free all the Tx ring sk_buffs */
1596
1597 for (i = 0; i < tx_ring->count; i++) {
1598 tx_buffer_info = &tx_ring->tx_buffer_info[i];
1599 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
1600 }
1601
1602 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
1603 memset(tx_ring->tx_buffer_info, 0, size);
1604
1605 /* Zero out the descriptor ring */
1606 memset(tx_ring->desc, 0, tx_ring->size);
1607
1608 tx_ring->next_to_use = 0;
1609 tx_ring->next_to_clean = 0;
1610
1611 writel(0, adapter->hw.hw_addr + tx_ring->head);
1612 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1613}
1614
1615/**
021230d4 1616 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 1617 * @adapter: board private structure
1618 **/
021230d4 1619static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 1620{
1621 int i;
1622
021230d4
AV		 1623 for (i = 0; i < adapter->num_rx_queues; i++)
1624 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 1625}
1626
1627/**
021230d4 1628 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 1629 * @adapter: board private structure
1630 **/
021230d4 1631static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 1632{
1633 int i;
1634
021230d4
AV		 1635 for (i = 0; i < adapter->num_tx_queues; i++)
1636 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 1637}
1638
1639void ixgbe_down(struct ixgbe_adapter *adapter)
1640{
1641 struct net_device *netdev = adapter->netdev;
1642 u32 rxctrl;
1643
1644 /* signal that we are down to the interrupt handler */
1645 set_bit(__IXGBE_DOWN, &adapter->state);
1646
1647 /* disable receives */
1648 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1649 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL,
1650 rxctrl & ~IXGBE_RXCTRL_RXEN);
1651
1652 netif_tx_disable(netdev);
1653
1654 /* disable transmits in the hardware */
1655
1656 /* flush both disables */
1657 IXGBE_WRITE_FLUSH(&adapter->hw);
1658 msleep(10);
1659
1660 ixgbe_irq_disable(adapter);
1661
021230d4 1662 ixgbe_napi_disable_all(adapter);
9a799d71
AK		 1663 del_timer_sync(&adapter->watchdog_timer);
1664
1665 netif_carrier_off(netdev);
1666 netif_stop_queue(netdev);
1667
1668 ixgbe_reset(adapter);
1669 ixgbe_clean_all_tx_rings(adapter);
1670 ixgbe_clean_all_rx_rings(adapter);
1671
1672}
1673
1674static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
1675{
1676 struct net_device *netdev = pci_get_drvdata(pdev);
1677 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1678#ifdef CONFIG_PM
1679 int retval = 0;
1680#endif
1681
1682 netif_device_detach(netdev);
1683
1684 if (netif_running(netdev)) {
1685 ixgbe_down(adapter);
1686 ixgbe_free_irq(adapter);
1687 }
1688
1689#ifdef CONFIG_PM
1690 retval = pci_save_state(pdev);
1691 if (retval)
1692 return retval;
1693#endif
1694
1695 pci_enable_wake(pdev, PCI_D3hot, 0);
1696 pci_enable_wake(pdev, PCI_D3cold, 0);
1697
5eba3699
AV		 1698 ixgbe_release_hw_control(adapter);
1699
9a799d71
AK		 1700 pci_disable_device(pdev);
1701
1702 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1703
1704 return 0;
1705}
1706
1707static void ixgbe_shutdown(struct pci_dev *pdev)
1708{
1709 ixgbe_suspend(pdev, PMSG_SUSPEND);
1710}
1711
1712/**
021230d4
AV		 1713 * ixgbe_poll - NAPI Rx polling callback
1714 * @napi: structure for representing this polling device
1715 * @budget: how many packets driver is allowed to clean
1716 *
1717 * This function is used for legacy and MSI, NAPI mode
9a799d71 1718 **/
021230d4 1719static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 1720{
021230d4
AV		 1721 struct ixgbe_q_vector *q_vector = container_of(napi,
1722 struct ixgbe_q_vector, napi);
1723 struct ixgbe_adapter *adapter = q_vector->adapter;
d2c7ddd6 1724 int tx_cleaned = 0, work_done = 0;
9a799d71 1725
d2c7ddd6 1726 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
021230d4 1727 ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget);
9a799d71 1728
d2c7ddd6
DM		 1729 if (tx_cleaned)
1730 work_done = budget;
1731
53e52c72
DM		 1732 /* If budget not fully consumed, exit the polling mode */
1733 if (work_done < budget) {
021230d4 1734 netif_rx_complete(adapter->netdev, napi);
d4f80882
AV		 1735 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1736 ixgbe_irq_enable(adapter);
9a799d71
AK		 1737 }
1738
1739 return work_done;
1740}
1741
1742/**
1743 * ixgbe_tx_timeout - Respond to a Tx Hang
1744 * @netdev: network interface device structure
1745 **/
1746static void ixgbe_tx_timeout(struct net_device *netdev)
1747{
1748 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1749
1750 /* Do the reset outside of interrupt context */
1751 schedule_work(&adapter->reset_task);
1752}
1753
1754static void ixgbe_reset_task(struct work_struct *work)
1755{
1756 struct ixgbe_adapter *adapter;
1757 adapter = container_of(work, struct ixgbe_adapter, reset_task);
1758
1759 adapter->tx_timeout_count++;
1760
d4f80882 1761 ixgbe_reinit_locked(adapter);
9a799d71
AK		 1762}
1763
021230d4
AV		 1764static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
1765 int vectors)
1766{
1767 int err, vector_threshold;
1768
1769 /* We'll want at least 3 (vector_threshold):
1770 * 1) TxQ[0] Cleanup
1771 * 2) RxQ[0] Cleanup
1772 * 3) Other (Link Status Change, etc.)
1773 * 4) TCP Timer (optional)
1774 */
1775 vector_threshold = MIN_MSIX_COUNT;
1776
1777 /* The more we get, the more we will assign to Tx/Rx Cleanup
1778 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
1779 * Right now, we simply care about how many we'll get; we'll
1780 * set them up later while requesting irq's.
1781 */
1782 while (vectors >= vector_threshold) {
1783 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
1784 vectors);
1785 if (!err) /* Success in acquiring all requested vectors. */
1786 break;
1787 else if (err < 0)
1788 vectors = 0; /* Nasty failure, quit now */
1789 else /* err == number of vectors we should try again with */
1790 vectors = err;
1791 }
1792
1793 if (vectors < vector_threshold) {
1794 /* Can't allocate enough MSI-X interrupts? Oh well.
1795 * This just means we'll go with either a single MSI
1796 * vector or fall back to legacy interrupts.
1797 */
1798 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
1799 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1800 kfree(adapter->msix_entries);
1801 adapter->msix_entries = NULL;
1802 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
1803 adapter->num_tx_queues = 1;
1804 adapter->num_rx_queues = 1;
1805 } else {
1806 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
1807 adapter->num_msix_vectors = vectors;
1808 }
1809}
1810
1811static void __devinit ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
1812{
1813 int nrq, ntq;
1814 int feature_mask = 0, rss_i, rss_m;
1815
1816 /* Number of supported queues */
1817 switch (adapter->hw.mac.type) {
1818 case ixgbe_mac_82598EB:
1819 rss_i = adapter->ring_feature[RING_F_RSS].indices;
1820 rss_m = 0;
1821 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
1822
1823 switch (adapter->flags & feature_mask) {
1824 case (IXGBE_FLAG_RSS_ENABLED):
1825 rss_m = 0xF;
1826 nrq = rss_i;
30eba97a
AV		 1827#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1828 ntq = rss_i;
1829#else
021230d4 1830 ntq = 1;
30eba97a 1831#endif
021230d4
AV		 1832 break;
1833 case 0:
1834 default:
1835 rss_i = 0;
1836 rss_m = 0;
1837 nrq = 1;
1838 ntq = 1;
1839 break;
1840 }
1841
1842 adapter->ring_feature[RING_F_RSS].indices = rss_i;
1843 adapter->ring_feature[RING_F_RSS].mask = rss_m;
1844 break;
1845 default:
1846 nrq = 1;
1847 ntq = 1;
1848 break;
1849 }
1850
1851 adapter->num_rx_queues = nrq;
1852 adapter->num_tx_queues = ntq;
1853}
1854
1855/**
1856 * ixgbe_cache_ring_register - Descriptor ring to register mapping
1857 * @adapter: board private structure to initialize
1858 *
1859 * Once we know the feature-set enabled for the device, we'll cache
1860 * the register offset the descriptor ring is assigned to.
1861 **/
1862static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
1863{
1864 /* TODO: Remove all uses of the indices in the cases where multiple
1865 * features are OR'd together, if the feature set makes sense.
1866 */
1867 int feature_mask = 0, rss_i;
1868 int i, txr_idx, rxr_idx;
1869
1870 /* Number of supported queues */
1871 switch (adapter->hw.mac.type) {
1872 case ixgbe_mac_82598EB:
1873 rss_i = adapter->ring_feature[RING_F_RSS].indices;
1874 txr_idx = 0;
1875 rxr_idx = 0;
1876 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
1877 switch (adapter->flags & feature_mask) {
1878 case (IXGBE_FLAG_RSS_ENABLED):
1879 for (i = 0; i < adapter->num_rx_queues; i++)
1880 adapter->rx_ring[i].reg_idx = i;
1881 for (i = 0; i < adapter->num_tx_queues; i++)
1882 adapter->tx_ring[i].reg_idx = i;
1883 break;
1884 case 0:
1885 default:
1886 break;
1887 }
1888 break;
1889 default:
1890 break;
1891 }
1892}
1893
9a799d71
AK		 1894/**
1895 * ixgbe_alloc_queues - Allocate memory for all rings
1896 * @adapter: board private structure to initialize
1897 *
1898 * We allocate one ring per queue at run-time since we don't know the
1899 * number of queues at compile-time. The polling_netdev array is
1900 * intended for Multiqueue, but should work fine with a single queue.
1901 **/
1902static int __devinit ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
1903{
1904 int i;
1905
1906 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
1907 sizeof(struct ixgbe_ring), GFP_KERNEL);
1908 if (!adapter->tx_ring)
021230d4 1909 goto err_tx_ring_allocation;
9a799d71
AK		 1910
1911 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
1912 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 1913 if (!adapter->rx_ring)
1914 goto err_rx_ring_allocation;
9a799d71 1915
021230d4
AV		 1916 for (i = 0; i < adapter->num_tx_queues; i++) {
1917 adapter->tx_ring[i].count = IXGBE_DEFAULT_TXD;
1918 adapter->tx_ring[i].queue_index = i;
1919 }
9a799d71 1920 for (i = 0; i < adapter->num_rx_queues; i++) {
9a799d71 1921 adapter->rx_ring[i].count = IXGBE_DEFAULT_RXD;
021230d4
AV		 1922 adapter->rx_ring[i].queue_index = i;
1923 }
1924
1925 ixgbe_cache_ring_register(adapter);
1926
1927 return 0;
1928
1929err_rx_ring_allocation:
1930 kfree(adapter->tx_ring);
1931err_tx_ring_allocation:
1932 return -ENOMEM;
1933}
1934
1935/**
1936 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
1937 * @adapter: board private structure to initialize
1938 *
1939 * Attempt to configure the interrupts using the best available
1940 * capabilities of the hardware and the kernel.
1941 **/
1942static int __devinit ixgbe_set_interrupt_capability(struct ixgbe_adapter
1943 *adapter)
1944{
1945 int err = 0;
1946 int vector, v_budget;
1947
1948 /*
1949 * It's easy to be greedy for MSI-X vectors, but it really
1950 * doesn't do us much good if we have a lot more vectors
1951 * than CPU's. So let's be conservative and only ask for
1952 * (roughly) twice the number of vectors as there are CPU's.
1953 */
1954 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
1955 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
1956
1957 /*
1958 * At the same time, hardware can only support a maximum of
1959 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
1960 * we can easily reach upwards of 64 Rx descriptor queues and
1961 * 32 Tx queues. Thus, we cap it off in those rare cases where
1962 * the cpu count also exceeds our vector limit.
1963 */
1964 v_budget = min(v_budget, MAX_MSIX_COUNT);
1965
1966 /* A failure in MSI-X entry allocation isn't fatal, but it does
1967 * mean we disable MSI-X capabilities of the adapter. */
1968 adapter->msix_entries = kcalloc(v_budget,
1969 sizeof(struct msix_entry), GFP_KERNEL);
1970 if (!adapter->msix_entries) {
1971 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
1972 ixgbe_set_num_queues(adapter);
1973 kfree(adapter->tx_ring);
1974 kfree(adapter->rx_ring);
1975 err = ixgbe_alloc_queues(adapter);
1976 if (err) {
1977 DPRINTK(PROBE, ERR, "Unable to allocate memory "
1978 "for queues\n");
1979 goto out;
1980 }
1981
1982 goto try_msi;
1983 }
1984
1985 for (vector = 0; vector < v_budget; vector++)
1986 adapter->msix_entries[vector].entry = vector;
1987
1988 ixgbe_acquire_msix_vectors(adapter, v_budget);
1989
1990 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1991 goto out;
1992
1993try_msi:
1994 err = pci_enable_msi(adapter->pdev);
1995 if (!err) {
1996 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
1997 } else {
1998 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
1999 "falling back to legacy. Error: %d\n", err);
2000 /* reset err */
2001 err = 0;
2002 }
2003
2004out:
30eba97a
AV		 2005#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2006 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2007 adapter->netdev->egress_subqueue_count = adapter->num_tx_queues;
2008#endif
021230d4
AV		 2009
2010 return err;
2011}
2012
2013static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2014{
2015 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2016 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2017 pci_disable_msix(adapter->pdev);
2018 kfree(adapter->msix_entries);
2019 adapter->msix_entries = NULL;
2020 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2021 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2022 pci_disable_msi(adapter->pdev);
2023 }
2024 return;
2025}
2026
2027/**
2028 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2029 * @adapter: board private structure to initialize
2030 *
2031 * We determine which interrupt scheme to use based on...
2032 * - Kernel support (MSI, MSI-X)
2033 * - which can be user-defined (via MODULE_PARAM)
2034 * - Hardware queue count (num_*_queues)
2035 * - defined by miscellaneous hardware support/features (RSS, etc.)
2036 **/
2037static int __devinit ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2038{
2039 int err;
2040
2041 /* Number of supported queues */
2042 ixgbe_set_num_queues(adapter);
2043
2044 err = ixgbe_alloc_queues(adapter);
2045 if (err) {
2046 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2047 goto err_alloc_queues;
2048 }
2049
2050 err = ixgbe_set_interrupt_capability(adapter);
2051 if (err) {
2052 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2053 goto err_set_interrupt;
9a799d71
AK		 2054 }
2055
021230d4
AV		 2056 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
2057 "Tx Queue count = %u\n",
2058 (adapter->num_rx_queues > 1) ? "Enabled" :
2059 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2060
2061 set_bit(__IXGBE_DOWN, &adapter->state);
2062
9a799d71 2063 return 0;
021230d4
AV		 2064
2065err_set_interrupt:
2066 kfree(adapter->tx_ring);
2067 kfree(adapter->rx_ring);
2068err_alloc_queues:
2069 return err;
9a799d71
AK		 2070}
2071
2072/**
2073 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2074 * @adapter: board private structure to initialize
2075 *
2076 * ixgbe_sw_init initializes the Adapter private data structure.
2077 * Fields are initialized based on PCI device information and
2078 * OS network device settings (MTU size).
2079 **/
2080static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2081{
2082 struct ixgbe_hw *hw = &adapter->hw;
2083 struct pci_dev *pdev = adapter->pdev;
021230d4
AV		 2084 unsigned int rss;
2085
2086 /* Set capability flags */
2087 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2088 adapter->ring_feature[RING_F_RSS].indices = rss;
2089 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
9a799d71
AK		 2090
2091 /* default flow control settings */
2092 hw->fc.original_type = ixgbe_fc_full;
2093 hw->fc.type = ixgbe_fc_full;
2094
021230d4 2095 /* select 10G link by default */
9a799d71
AK		 2096 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2097 if (hw->mac.ops.reset(hw)) {
2098 dev_err(&pdev->dev, "HW Init failed\n");
2099 return -EIO;
2100 }
3957d63d
AK		 2101 if (hw->mac.ops.setup_link_speed(hw, IXGBE_LINK_SPEED_10GB_FULL, true,
2102 false)) {
9a799d71
AK		 2103 dev_err(&pdev->dev, "Link Speed setup failed\n");
2104 return -EIO;
2105 }
2106
2107 /* initialize eeprom parameters */
2108 if (ixgbe_init_eeprom(hw)) {
2109 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2110 return -EIO;
2111 }
2112
021230d4 2113 /* enable rx csum by default */
9a799d71
AK		 2114 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2115
9a799d71
AK		 2116 set_bit(__IXGBE_DOWN, &adapter->state);
2117
2118 return 0;
2119}
2120
2121/**
2122 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2123 * @adapter: board private structure
2124 * @txdr: tx descriptor ring (for a specific queue) to setup
2125 *
2126 * Return 0 on success, negative on failure
2127 **/
2128int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
2129 struct ixgbe_ring *txdr)
2130{
2131 struct pci_dev *pdev = adapter->pdev;
2132 int size;
2133
2134 size = sizeof(struct ixgbe_tx_buffer) * txdr->count;
2135 txdr->tx_buffer_info = vmalloc(size);
2136 if (!txdr->tx_buffer_info) {
2137 DPRINTK(PROBE, ERR,
2138 "Unable to allocate memory for the transmit descriptor ring\n");
2139 return -ENOMEM;
2140 }
2141 memset(txdr->tx_buffer_info, 0, size);
2142
2143 /* round up to nearest 4K */
2144 txdr->size = txdr->count * sizeof(union ixgbe_adv_tx_desc);
2145 txdr->size = ALIGN(txdr->size, 4096);
2146
2147 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2148 if (!txdr->desc) {
2149 vfree(txdr->tx_buffer_info);
2150 DPRINTK(PROBE, ERR,
2151 "Memory allocation failed for the tx desc ring\n");
2152 return -ENOMEM;
2153 }
2154
9a799d71
AK		 2155 txdr->next_to_use = 0;
2156 txdr->next_to_clean = 0;
2157 txdr->work_limit = txdr->count;
9a799d71
AK		 2158
2159 return 0;
2160}
2161
2162/**
2163 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2164 * @adapter: board private structure
2165 * @rxdr: rx descriptor ring (for a specific queue) to setup
2166 *
2167 * Returns 0 on success, negative on failure
2168 **/
2169int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
2170 struct ixgbe_ring *rxdr)
2171{
2172 struct pci_dev *pdev = adapter->pdev;
021230d4 2173 int size;
9a799d71
AK		 2174
2175 size = sizeof(struct ixgbe_rx_buffer) * rxdr->count;
2176 rxdr->rx_buffer_info = vmalloc(size);
2177 if (!rxdr->rx_buffer_info) {
2178 DPRINTK(PROBE, ERR,
2179 "vmalloc allocation failed for the rx desc ring\n");
2180 return -ENOMEM;
2181 }
2182 memset(rxdr->rx_buffer_info, 0, size);
2183
9a799d71 2184 /* Round up to nearest 4K */
021230d4 2185 rxdr->size = rxdr->count * sizeof(union ixgbe_adv_rx_desc);
9a799d71
AK		 2186 rxdr->size = ALIGN(rxdr->size, 4096);
2187
2188 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2189
2190 if (!rxdr->desc) {
2191 DPRINTK(PROBE, ERR,
2192 "Memory allocation failed for the rx desc ring\n");
2193 vfree(rxdr->rx_buffer_info);
2194 return -ENOMEM;
2195 }
2196
2197 rxdr->next_to_clean = 0;
2198 rxdr->next_to_use = 0;
9a799d71
AK		 2199
2200 return 0;
2201}
2202
2203/**
2204 * ixgbe_free_tx_resources - Free Tx Resources per Queue
2205 * @adapter: board private structure
2206 * @tx_ring: Tx descriptor ring for a specific queue
2207 *
2208 * Free all transmit software resources
2209 **/
2210static void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
2211 struct ixgbe_ring *tx_ring)
2212{
2213 struct pci_dev *pdev = adapter->pdev;
2214
2215 ixgbe_clean_tx_ring(adapter, tx_ring);
2216
2217 vfree(tx_ring->tx_buffer_info);
2218 tx_ring->tx_buffer_info = NULL;
2219
2220 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2221
2222 tx_ring->desc = NULL;
2223}
2224
2225/**
2226 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2227 * @adapter: board private structure
2228 *
2229 * Free all transmit software resources
2230 **/
2231static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
2232{
2233 int i;
2234
2235 for (i = 0; i < adapter->num_tx_queues; i++)
2236 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
2237}
2238
2239/**
2240 * ixgbe_free_rx_resources - Free Rx Resources
2241 * @adapter: board private structure
2242 * @rx_ring: ring to clean the resources from
2243 *
2244 * Free all receive software resources
2245 **/
2246static void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2247 struct ixgbe_ring *rx_ring)
2248{
2249 struct pci_dev *pdev = adapter->pdev;
2250
2251 ixgbe_clean_rx_ring(adapter, rx_ring);
2252
2253 vfree(rx_ring->rx_buffer_info);
2254 rx_ring->rx_buffer_info = NULL;
2255
2256 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2257
2258 rx_ring->desc = NULL;
2259}
2260
2261/**
2262 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
2263 * @adapter: board private structure
2264 *
2265 * Free all receive software resources
2266 **/
2267static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
2268{
2269 int i;
2270
2271 for (i = 0; i < adapter->num_rx_queues; i++)
2272 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
2273}
2274
2275/**
021230d4 2276 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
9a799d71
AK		 2277 * @adapter: board private structure
2278 *
2279 * If this function returns with an error, then it's possible one or
2280 * more of the rings is populated (while the rest are not). It is the
2281 * callers duty to clean those orphaned rings.
2282 *
2283 * Return 0 on success, negative on failure
2284 **/
2285static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2286{
2287 int i, err = 0;
2288
2289 for (i = 0; i < adapter->num_tx_queues; i++) {
2290 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2291 if (err) {
2292 DPRINTK(PROBE, ERR,
2293 "Allocation for Tx Queue %u failed\n", i);
2294 break;
2295 }
2296 }
2297
2298 return err;
2299}
2300
2301/**
021230d4 2302 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
9a799d71
AK		 2303 * @adapter: board private structure
2304 *
2305 * If this function returns with an error, then it's possible one or
2306 * more of the rings is populated (while the rest are not). It is the
2307 * callers duty to clean those orphaned rings.
2308 *
2309 * Return 0 on success, negative on failure
2310 **/
2311
2312static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2313{
2314 int i, err = 0;
2315
2316 for (i = 0; i < adapter->num_rx_queues; i++) {
2317 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2318 if (err) {
2319 DPRINTK(PROBE, ERR,
2320 "Allocation for Rx Queue %u failed\n", i);
2321 break;
2322 }
2323 }
2324
2325 return err;
2326}
2327
2328/**
2329 * ixgbe_change_mtu - Change the Maximum Transfer Unit
2330 * @netdev: network interface device structure
2331 * @new_mtu: new value for maximum frame size
2332 *
2333 * Returns 0 on success, negative on failure
2334 **/
2335static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
2336{
2337 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2338 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2339
2340 if ((max_frame < (ETH_ZLEN + ETH_FCS_LEN)) ||
2341 (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
2342 return -EINVAL;
2343
021230d4
AV		 2344 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
2345 netdev->mtu, new_mtu);
2346 /* must set new MTU before calling down or up */
9a799d71
AK		 2347 netdev->mtu = new_mtu;
2348
d4f80882
AV		 2349 if (netif_running(netdev))
2350 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2351
2352 return 0;
2353}
2354
2355/**
2356 * ixgbe_open - Called when a network interface is made active
2357 * @netdev: network interface device structure
2358 *
2359 * Returns 0 on success, negative value on failure
2360 *
2361 * The open entry point is called when a network interface is made
2362 * active by the system (IFF_UP). At this point all resources needed
2363 * for transmit and receive operations are allocated, the interrupt
2364 * handler is registered with the OS, the watchdog timer is started,
2365 * and the stack is notified that the interface is ready.
2366 **/
2367static int ixgbe_open(struct net_device *netdev)
2368{
2369 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2370 int err;
4bebfaa5
AK		 2371
2372 /* disallow open during test */
2373 if (test_bit(__IXGBE_TESTING, &adapter->state))
2374 return -EBUSY;
9a799d71 2375
9a799d71
AK		 2376 /* allocate transmit descriptors */
2377 err = ixgbe_setup_all_tx_resources(adapter);
2378 if (err)
2379 goto err_setup_tx;
2380
9a799d71
AK		 2381 /* allocate receive descriptors */
2382 err = ixgbe_setup_all_rx_resources(adapter);
2383 if (err)
2384 goto err_setup_rx;
2385
2386 ixgbe_configure(adapter);
2387
021230d4 2388 err = ixgbe_request_irq(adapter);
9a799d71
AK		 2389 if (err)
2390 goto err_req_irq;
2391
9a799d71
AK		 2392 err = ixgbe_up_complete(adapter);
2393 if (err)
2394 goto err_up;
2395
2396 return 0;
2397
2398err_up:
5eba3699 2399 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2400 ixgbe_free_irq(adapter);
2401err_req_irq:
2402 ixgbe_free_all_rx_resources(adapter);
2403err_setup_rx:
2404 ixgbe_free_all_tx_resources(adapter);
2405err_setup_tx:
2406 ixgbe_reset(adapter);
2407
2408 return err;
2409}
2410
2411/**
2412 * ixgbe_close - Disables a network interface
2413 * @netdev: network interface device structure
2414 *
2415 * Returns 0, this is not allowed to fail
2416 *
2417 * The close entry point is called when an interface is de-activated
2418 * by the OS. The hardware is still under the drivers control, but
2419 * needs to be disabled. A global MAC reset is issued to stop the
2420 * hardware, and all transmit and receive resources are freed.
2421 **/
2422static int ixgbe_close(struct net_device *netdev)
2423{
2424 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 2425
2426 ixgbe_down(adapter);
2427 ixgbe_free_irq(adapter);
2428
2429 ixgbe_free_all_tx_resources(adapter);
2430 ixgbe_free_all_rx_resources(adapter);
2431
5eba3699 2432 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2433
2434 return 0;
2435}
2436
2437/**
2438 * ixgbe_update_stats - Update the board statistics counters.
2439 * @adapter: board private structure
2440 **/
2441void ixgbe_update_stats(struct ixgbe_adapter *adapter)
2442{
2443 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 2444 u64 total_mpc = 0;
2445 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71
AK		 2446
2447 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 2448 for (i = 0; i < 8; i++) {
2449 /* for packet buffers not used, the register should read 0 */
2450 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2451 missed_rx += mpc;
2452 adapter->stats.mpc[i] += mpc;
2453 total_mpc += adapter->stats.mpc[i];
2454 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2455 }
2456 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2457 /* work around hardware counting issue */
2458 adapter->stats.gprc -= missed_rx;
2459
2460 /* 82598 hardware only has a 32 bit counter in the high register */
9a799d71 2461 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6f11eef7
AV		 2462 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2463 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
9a799d71
AK		 2464 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2465 adapter->stats.bprc += bprc;
2466 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2467 adapter->stats.mprc -= bprc;
2468 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2469 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2470 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2471 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2472 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2473 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2474 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71
AK		 2475 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2476 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
9a799d71 2477 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6f11eef7
AV		 2478 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2479 adapter->stats.lxontxc += lxon;
2480 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2481 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 2482 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2483 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 2484 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2485 /*
2486 * 82598 errata - tx of flow control packets is included in tx counters
2487 */
2488 xon_off_tot = lxon + lxoff;
2489 adapter->stats.gptc -= xon_off_tot;
2490 adapter->stats.mptc -= xon_off_tot;
2491 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 2492 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2493 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2494 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 2495 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2496 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 2497 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 2498 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2499 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2500 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2501 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2502 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 2503 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2504
2505 /* Fill out the OS statistics structure */
9a799d71
AK		 2506 adapter->net_stats.multicast = adapter->stats.mprc;
2507
2508 /* Rx Errors */
2509 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
2510 adapter->stats.rlec;
2511 adapter->net_stats.rx_dropped = 0;
2512 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
2513 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 2514 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 2515}
2516
2517/**
2518 * ixgbe_watchdog - Timer Call-back
2519 * @data: pointer to adapter cast into an unsigned long
2520 **/
2521static void ixgbe_watchdog(unsigned long data)
2522{
2523 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
2524 struct net_device *netdev = adapter->netdev;
2525 bool link_up;
2526 u32 link_speed = 0;
30eba97a
AV		 2527#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2528 int i;
2529#endif
9a799d71 2530
3957d63d 2531 adapter->hw.mac.ops.check_link(&adapter->hw, &(link_speed), &link_up);
9a799d71
AK		 2532
2533 if (link_up) {
2534 if (!netif_carrier_ok(netdev)) {
2535 u32 frctl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2536 u32 rmcs = IXGBE_READ_REG(&adapter->hw, IXGBE_RMCS);
2537#define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
2538#define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
2539 DPRINTK(LINK, INFO, "NIC Link is Up %s, "
2540 "Flow Control: %s\n",
2541 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
2542 "10 Gbps" :
2543 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5a059e9d 2544 "1 Gbps" : "unknown speed")),
9a799d71
AK		 2545 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
2546 (FLOW_RX ? "RX" :
2547 (FLOW_TX ? "TX" : "None"))));
2548
2549 netif_carrier_on(netdev);
2550 netif_wake_queue(netdev);
30eba97a
AV		 2551#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2552 for (i = 0; i < adapter->num_tx_queues; i++)
2553 netif_wake_subqueue(netdev, i);
2554#endif
9a799d71
AK		 2555 } else {
2556 /* Force detection of hung controller */
2557 adapter->detect_tx_hung = true;
2558 }
2559 } else {
2560 if (netif_carrier_ok(netdev)) {
2561 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2562 netif_carrier_off(netdev);
2563 netif_stop_queue(netdev);
2564 }
2565 }
2566
2567 ixgbe_update_stats(adapter);
2568
021230d4
AV		 2569 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2570 /* Cause software interrupt to ensure rx rings are cleaned */
2571 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2572 u32 eics =
2573 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
2574 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, eics);
2575 } else {
2576 /* for legacy and MSI interrupts don't set any bits that
2577 * are enabled for EIAM, because this operation would
2578 * set *both* EIMS and EICS for any bit in EIAM */
2579 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
2580 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
2581 }
2582 /* Reset the timer */
9a799d71
AK		 2583 mod_timer(&adapter->watchdog_timer,
2584 round_jiffies(jiffies + 2 * HZ));
021230d4 2585 }
9a799d71
AK		 2586}
2587
9a799d71
AK		 2588static int ixgbe_tso(struct ixgbe_adapter *adapter,
2589 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
2590 u32 tx_flags, u8 *hdr_len)
2591{
2592 struct ixgbe_adv_tx_context_desc *context_desc;
2593 unsigned int i;
2594 int err;
2595 struct ixgbe_tx_buffer *tx_buffer_info;
2596 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
2597 u32 mss_l4len_idx = 0, l4len;
9a799d71
AK		 2598
2599 if (skb_is_gso(skb)) {
2600 if (skb_header_cloned(skb)) {
2601 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2602 if (err)
2603 return err;
2604 }
2605 l4len = tcp_hdrlen(skb);
2606 *hdr_len += l4len;
2607
8327d000 2608 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 2609 struct iphdr *iph = ip_hdr(skb);
2610 iph->tot_len = 0;
2611 iph->check = 0;
2612 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2613 iph->daddr, 0,
2614 IPPROTO_TCP,
2615 0);
2616 adapter->hw_tso_ctxt++;
2617 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2618 ipv6_hdr(skb)->payload_len = 0;
2619 tcp_hdr(skb)->check =
2620 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2621 &ipv6_hdr(skb)->daddr,
2622 0, IPPROTO_TCP, 0);
2623 adapter->hw_tso6_ctxt++;
2624 }
2625
2626 i = tx_ring->next_to_use;
2627
2628 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2629 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
2630
2631 /* VLAN MACLEN IPLEN */
2632 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2633 vlan_macip_lens |=
2634 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
2635 vlan_macip_lens |= ((skb_network_offset(skb)) <<
2636 IXGBE_ADVTXD_MACLEN_SHIFT);
2637 *hdr_len += skb_network_offset(skb);
2638 vlan_macip_lens |=
2639 (skb_transport_header(skb) - skb_network_header(skb));
2640 *hdr_len +=
2641 (skb_transport_header(skb) - skb_network_header(skb));
2642 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
2643 context_desc->seqnum_seed = 0;
2644
2645 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2646 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
2647 IXGBE_ADVTXD_DTYP_CTXT);
2648
8327d000 2649 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 2650 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
2651 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
2652 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
2653
2654 /* MSS L4LEN IDX */
2655 mss_l4len_idx |=
2656 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
2657 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
2658 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2659
2660 tx_buffer_info->time_stamp = jiffies;
2661 tx_buffer_info->next_to_watch = i;
2662
2663 i++;
2664 if (i == tx_ring->count)
2665 i = 0;
2666 tx_ring->next_to_use = i;
2667
2668 return true;
2669 }
2670 return false;
2671}
2672
2673static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
2674 struct ixgbe_ring *tx_ring,
2675 struct sk_buff *skb, u32 tx_flags)
2676{
2677 struct ixgbe_adv_tx_context_desc *context_desc;
2678 unsigned int i;
2679 struct ixgbe_tx_buffer *tx_buffer_info;
2680 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
2681
2682 if (skb->ip_summed == CHECKSUM_PARTIAL ||
2683 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
2684 i = tx_ring->next_to_use;
2685 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2686 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
2687
2688 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2689 vlan_macip_lens |=
2690 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
2691 vlan_macip_lens |= (skb_network_offset(skb) <<
2692 IXGBE_ADVTXD_MACLEN_SHIFT);
2693 if (skb->ip_summed == CHECKSUM_PARTIAL)
2694 vlan_macip_lens |= (skb_transport_header(skb) -
2695 skb_network_header(skb));
2696
2697 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
2698 context_desc->seqnum_seed = 0;
2699
2700 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
2701 IXGBE_ADVTXD_DTYP_CTXT);
2702
2703 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71
AK		 2704 switch (skb->protocol) {
2705 case __constant_htons(ETH_P_IP):
9a799d71 2706 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 2707 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2708 type_tucmd_mlhl |=
2709 IXGBE_ADVTXD_TUCMD_L4T_TCP;
2710 break;
2711
2712 case __constant_htons(ETH_P_IPV6):
2713 /* XXX what about other V6 headers?? */
2714 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2715 type_tucmd_mlhl |=
2716 IXGBE_ADVTXD_TUCMD_L4T_TCP;
2717 break;
9a799d71 2718
41825d71
AK		 2719 default:
2720 if (unlikely(net_ratelimit())) {
2721 DPRINTK(PROBE, WARNING,
2722 "partial checksum but proto=%x!\n",
2723 skb->protocol);
2724 }
2725 break;
2726 }
9a799d71
AK		 2727 }
2728
2729 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
2730 context_desc->mss_l4len_idx = 0;
2731
2732 tx_buffer_info->time_stamp = jiffies;
2733 tx_buffer_info->next_to_watch = i;
2734 adapter->hw_csum_tx_good++;
2735 i++;
2736 if (i == tx_ring->count)
2737 i = 0;
2738 tx_ring->next_to_use = i;
2739
2740 return true;
2741 }
2742 return false;
2743}
2744
2745static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
2746 struct ixgbe_ring *tx_ring,
2747 struct sk_buff *skb, unsigned int first)
2748{
2749 struct ixgbe_tx_buffer *tx_buffer_info;
2750 unsigned int len = skb->len;
2751 unsigned int offset = 0, size, count = 0, i;
2752 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
2753 unsigned int f;
2754
2755 len -= skb->data_len;
2756
2757 i = tx_ring->next_to_use;
2758
2759 while (len) {
2760 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2761 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
2762
2763 tx_buffer_info->length = size;
2764 tx_buffer_info->dma = pci_map_single(adapter->pdev,
2765 skb->data + offset,
2766 size, PCI_DMA_TODEVICE);
2767 tx_buffer_info->time_stamp = jiffies;
2768 tx_buffer_info->next_to_watch = i;
2769
2770 len -= size;
2771 offset += size;
2772 count++;
2773 i++;
2774 if (i == tx_ring->count)
2775 i = 0;
2776 }
2777
2778 for (f = 0; f < nr_frags; f++) {
2779 struct skb_frag_struct *frag;
2780
2781 frag = &skb_shinfo(skb)->frags[f];
2782 len = frag->size;
2783 offset = frag->page_offset;
2784
2785 while (len) {
2786 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2787 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
2788
2789 tx_buffer_info->length = size;
2790 tx_buffer_info->dma = pci_map_page(adapter->pdev,
2791 frag->page,
2792 offset,
2793 size, PCI_DMA_TODEVICE);
2794 tx_buffer_info->time_stamp = jiffies;
2795 tx_buffer_info->next_to_watch = i;
2796
2797 len -= size;
2798 offset += size;
2799 count++;
2800 i++;
2801 if (i == tx_ring->count)
2802 i = 0;
2803 }
2804 }
2805 if (i == 0)
2806 i = tx_ring->count - 1;
2807 else
2808 i = i - 1;
2809 tx_ring->tx_buffer_info[i].skb = skb;
2810 tx_ring->tx_buffer_info[first].next_to_watch = i;
2811
2812 return count;
2813}
2814
2815static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
2816 struct ixgbe_ring *tx_ring,
2817 int tx_flags, int count, u32 paylen, u8 hdr_len)
2818{
2819 union ixgbe_adv_tx_desc *tx_desc = NULL;
2820 struct ixgbe_tx_buffer *tx_buffer_info;
2821 u32 olinfo_status = 0, cmd_type_len = 0;
2822 unsigned int i;
2823 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
2824
2825 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
2826
2827 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
2828
2829 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2830 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
2831
2832 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
2833 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
2834
2835 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
2836 IXGBE_ADVTXD_POPTS_SHIFT;
2837
2838 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
2839 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
2840 IXGBE_ADVTXD_POPTS_SHIFT;
2841
2842 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
2843 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
2844 IXGBE_ADVTXD_POPTS_SHIFT;
2845
2846 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
2847
2848 i = tx_ring->next_to_use;
2849 while (count--) {
2850 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2851 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
2852 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
2853 tx_desc->read.cmd_type_len =
2854 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
2855 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2856
2857 i++;
2858 if (i == tx_ring->count)
2859 i = 0;
2860 }
2861
2862 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
2863
2864 /*
2865 * Force memory writes to complete before letting h/w
2866 * know there are new descriptors to fetch. (Only
2867 * applicable for weak-ordered memory model archs,
2868 * such as IA-64).
2869 */
2870 wmb();
2871
2872 tx_ring->next_to_use = i;
2873 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2874}
2875
e092be60
AV		 2876static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
2877 struct ixgbe_ring *tx_ring, int size)
2878{
2879 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2880
30eba97a
AV		 2881#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2882 netif_stop_subqueue(netdev, tx_ring->queue_index);
2883#else
e092be60 2884 netif_stop_queue(netdev);
30eba97a 2885#endif
e092be60
AV		 2886 /* Herbert's original patch had:
2887 * smp_mb__after_netif_stop_queue();
2888 * but since that doesn't exist yet, just open code it. */
2889 smp_mb();
2890
2891 /* We need to check again in a case another CPU has just
2892 * made room available. */
2893 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
2894 return -EBUSY;
2895
2896 /* A reprieve! - use start_queue because it doesn't call schedule */
30eba97a
AV		 2897#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2898 netif_wake_subqueue(netdev, tx_ring->queue_index);
2899#else
e092be60 2900 netif_wake_queue(netdev);
30eba97a 2901#endif
e092be60
AV		 2902 ++adapter->restart_queue;
2903 return 0;
2904}
2905
2906static int ixgbe_maybe_stop_tx(struct net_device *netdev,
2907 struct ixgbe_ring *tx_ring, int size)
2908{
2909 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
2910 return 0;
2911 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
2912}
2913
2914
9a799d71
AK		 2915static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2916{
2917 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2918 struct ixgbe_ring *tx_ring;
2919 unsigned int len = skb->len;
2920 unsigned int first;
2921 unsigned int tx_flags = 0;
30eba97a
AV		 2922 u8 hdr_len = 0;
2923 int r_idx = 0, tso;
9a799d71
AK		 2924 unsigned int mss = 0;
2925 int count = 0;
2926 unsigned int f;
2927 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
2928 len -= skb->data_len;
30eba97a
AV		 2929#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2930 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
2931#endif
2932 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 2933
9a799d71
AK		 2934
2935 if (skb->len <= 0) {
2936 dev_kfree_skb(skb);
2937 return NETDEV_TX_OK;
2938 }
2939 mss = skb_shinfo(skb)->gso_size;
2940
2941 if (mss)
2942 count++;
2943 else if (skb->ip_summed == CHECKSUM_PARTIAL)
2944 count++;
2945
2946 count += TXD_USE_COUNT(len);
2947 for (f = 0; f < nr_frags; f++)
2948 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
2949
e092be60 2950 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 2951 adapter->tx_busy++;
9a799d71
AK		 2952 return NETDEV_TX_BUSY;
2953 }
9a799d71
AK		 2954 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2955 tx_flags |= IXGBE_TX_FLAGS_VLAN;
2956 tx_flags |= (vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT);
2957 }
2958
8327d000 2959 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 2960 tx_flags |= IXGBE_TX_FLAGS_IPV4;
2961 first = tx_ring->next_to_use;
2962 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
2963 if (tso < 0) {
2964 dev_kfree_skb_any(skb);
2965 return NETDEV_TX_OK;
2966 }
2967
2968 if (tso)
2969 tx_flags |= IXGBE_TX_FLAGS_TSO;
2970 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
2971 (skb->ip_summed == CHECKSUM_PARTIAL))
2972 tx_flags |= IXGBE_TX_FLAGS_CSUM;
2973
2974 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
2975 ixgbe_tx_map(adapter, tx_ring, skb, first),
2976 skb->len, hdr_len);
2977
2978 netdev->trans_start = jiffies;
2979
e092be60 2980 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71
AK		 2981
2982 return NETDEV_TX_OK;
2983}
2984
2985/**
2986 * ixgbe_get_stats - Get System Network Statistics
2987 * @netdev: network interface device structure
2988 *
2989 * Returns the address of the device statistics structure.
2990 * The statistics are actually updated from the timer callback.
2991 **/
2992static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
2993{
2994 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2995
2996 /* only return the current stats */
2997 return &adapter->net_stats;
2998}
2999
3000/**
3001 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3002 * @netdev: network interface device structure
3003 * @p: pointer to an address structure
3004 *
3005 * Returns 0 on success, negative on failure
3006 **/
3007static int ixgbe_set_mac(struct net_device *netdev, void *p)
3008{
3009 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3010 struct sockaddr *addr = p;
3011
3012 if (!is_valid_ether_addr(addr->sa_data))
3013 return -EADDRNOTAVAIL;
3014
3015 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3016 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
3017
3018 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
3019
3020 return 0;
3021}
3022
3023#ifdef CONFIG_NET_POLL_CONTROLLER
3024/*
3025 * Polling 'interrupt' - used by things like netconsole to send skbs
3026 * without having to re-enable interrupts. It's not called while
3027 * the interrupt routine is executing.
3028 */
3029static void ixgbe_netpoll(struct net_device *netdev)
3030{
3031 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3032
3033 disable_irq(adapter->pdev->irq);
3034 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3035 ixgbe_intr(adapter->pdev->irq, netdev);
3036 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3037 enable_irq(adapter->pdev->irq);
3038}
3039#endif
3040
021230d4
AV		 3041/**
3042 * ixgbe_napi_add_all - prep napi structs for use
3043 * @adapter: private struct
3044 * helper function to napi_add each possible q_vector->napi
3045 */
3046static void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3047{
3048 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3049 int (*poll)(struct napi_struct *, int);
3050
3051 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3052 poll = &ixgbe_clean_rxonly;
3053 } else {
3054 poll = &ixgbe_poll;
3055 /* only one q_vector for legacy modes */
3056 q_vectors = 1;
3057 }
3058
3059 for (i = 0; i < q_vectors; i++) {
3060 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
3061 netif_napi_add(adapter->netdev, &q_vector->napi,
3062 (*poll), 64);
3063 }
3064}
3065
9a799d71
AK		 3066/**
3067 * ixgbe_probe - Device Initialization Routine
3068 * @pdev: PCI device information struct
3069 * @ent: entry in ixgbe_pci_tbl
3070 *
3071 * Returns 0 on success, negative on failure
3072 *
3073 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3074 * The OS initialization, configuring of the adapter private structure,
3075 * and a hardware reset occur.
3076 **/
3077static int __devinit ixgbe_probe(struct pci_dev *pdev,
3078 const struct pci_device_id *ent)
3079{
3080 struct net_device *netdev;
3081 struct ixgbe_adapter *adapter = NULL;
3082 struct ixgbe_hw *hw;
3083 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
3084 unsigned long mmio_start, mmio_len;
3085 static int cards_found;
3086 int i, err, pci_using_dac;
3087 u16 link_status, link_speed, link_width;
3088 u32 part_num;
3089
3090 err = pci_enable_device(pdev);
3091 if (err)
3092 return err;
3093
3094 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3095 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3096 pci_using_dac = 1;
3097 } else {
3098 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3099 if (err) {
3100 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3101 if (err) {
3102 dev_err(&pdev->dev, "No usable DMA "
3103 "configuration, aborting\n");
3104 goto err_dma;
3105 }
3106 }
3107 pci_using_dac = 0;
3108 }
3109
3110 err = pci_request_regions(pdev, ixgbe_driver_name);
3111 if (err) {
3112 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3113 goto err_pci_reg;
3114 }
3115
3116 pci_set_master(pdev);
3117
30eba97a
AV		 3118#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3119 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
3120#else
9a799d71 3121 netdev = alloc_etherdev(sizeof(struct ixgbe_adapter));
30eba97a 3122#endif
9a799d71
AK		 3123 if (!netdev) {
3124 err = -ENOMEM;
3125 goto err_alloc_etherdev;
3126 }
3127
9a799d71
AK		 3128 SET_NETDEV_DEV(netdev, &pdev->dev);
3129
3130 pci_set_drvdata(pdev, netdev);
3131 adapter = netdev_priv(netdev);
3132
3133 adapter->netdev = netdev;
3134 adapter->pdev = pdev;
3135 hw = &adapter->hw;
3136 hw->back = adapter;
3137 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
3138
3139 mmio_start = pci_resource_start(pdev, 0);
3140 mmio_len = pci_resource_len(pdev, 0);
3141
3142 hw->hw_addr = ioremap(mmio_start, mmio_len);
3143 if (!hw->hw_addr) {
3144 err = -EIO;
3145 goto err_ioremap;
3146 }
3147
3148 for (i = 1; i <= 5; i++) {
3149 if (pci_resource_len(pdev, i) == 0)
3150 continue;
3151 }
3152
3153 netdev->open = &ixgbe_open;
3154 netdev->stop = &ixgbe_close;
3155 netdev->hard_start_xmit = &ixgbe_xmit_frame;
3156 netdev->get_stats = &ixgbe_get_stats;
3157 netdev->set_multicast_list = &ixgbe_set_multi;
3158 netdev->set_mac_address = &ixgbe_set_mac;
3159 netdev->change_mtu = &ixgbe_change_mtu;
3160 ixgbe_set_ethtool_ops(netdev);
3161 netdev->tx_timeout = &ixgbe_tx_timeout;
3162 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 3163 netdev->vlan_rx_register = ixgbe_vlan_rx_register;
3164 netdev->vlan_rx_add_vid = ixgbe_vlan_rx_add_vid;
3165 netdev->vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid;
3166#ifdef CONFIG_NET_POLL_CONTROLLER
3167 netdev->poll_controller = ixgbe_netpoll;
3168#endif
3169 strcpy(netdev->name, pci_name(pdev));
3170
3171 netdev->mem_start = mmio_start;
3172 netdev->mem_end = mmio_start + mmio_len;
3173
3174 adapter->bd_number = cards_found;
3175
3176 /* PCI config space info */
3177 hw->vendor_id = pdev->vendor;
3178 hw->device_id = pdev->device;
3179 hw->revision_id = pdev->revision;
3180 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3181 hw->subsystem_device_id = pdev->subsystem_device;
3182
3183 /* Setup hw api */
3184 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 3185 hw->mac.type = ii->mac;
9a799d71
AK		 3186
3187 err = ii->get_invariants(hw);
3188 if (err)
3189 goto err_hw_init;
3190
3191 /* setup the private structure */
3192 err = ixgbe_sw_init(adapter);
3193 if (err)
3194 goto err_sw_init;
3195
3196 netdev->features = NETIF_F_SG |
3197 NETIF_F_HW_CSUM |
3198 NETIF_F_HW_VLAN_TX |
3199 NETIF_F_HW_VLAN_RX |
3200 NETIF_F_HW_VLAN_FILTER;
3201
3202 netdev->features |= NETIF_F_TSO;
3203
3204 netdev->features |= NETIF_F_TSO6;
3205 if (pci_using_dac)
3206 netdev->features |= NETIF_F_HIGHDMA;
3207
30eba97a
AV		 3208#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3209 netdev->features |= NETIF_F_MULTI_QUEUE;
3210#endif
9a799d71
AK		 3211
3212 /* make sure the EEPROM is good */
3213 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) {
3214 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
3215 err = -EIO;
3216 goto err_eeprom;
3217 }
3218
3219 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
3220 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
3221
3222 if (ixgbe_validate_mac_addr(netdev->dev_addr)) {
3223 err = -EIO;
3224 goto err_eeprom;
3225 }
3226
3227 init_timer(&adapter->watchdog_timer);
3228 adapter->watchdog_timer.function = &ixgbe_watchdog;
3229 adapter->watchdog_timer.data = (unsigned long)adapter;
3230
3231 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
3232
3233 /* initialize default flow control settings */
3234 hw->fc.original_type = ixgbe_fc_full;
3235 hw->fc.type = ixgbe_fc_full;
3236 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3237 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3238 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3239
021230d4
AV		 3240 err = ixgbe_init_interrupt_scheme(adapter);
3241 if (err)
3242 goto err_sw_init;
9a799d71
AK		 3243
3244 /* print bus type/speed/width info */
3245 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
3246 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
3247 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
3248 dev_info(&pdev->dev, "(PCI Express:%s:%s) "
3249 "%02x:%02x:%02x:%02x:%02x:%02x\n",
3250 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
3251 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
3252 "Unknown"),
3253 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
3254 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
3255 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
3256 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
3257 "Unknown"),
3258 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
3259 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
3260 ixgbe_read_part_num(hw, &part_num);
3261 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
3262 hw->mac.type, hw->phy.type,
3263 (part_num >> 8), (part_num & 0xff));
3264
0c254d86
AK		 3265 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
3266 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
3267 "this card is not sufficient for optimal "
3268 "performance.\n");
3269 dev_warn(&pdev->dev, "For optimal performance a x8 "
3270 "PCI-Express slot is required.\n");
3271 }
3272
9a799d71
AK		 3273 /* reset the hardware with the new settings */
3274 ixgbe_start_hw(hw);
3275
3276 netif_carrier_off(netdev);
3277 netif_stop_queue(netdev);
30eba97a
AV		 3278#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3279 for (i = 0; i < adapter->num_tx_queues; i++)
3280 netif_stop_subqueue(netdev, i);
3281#endif
9a799d71 3282
021230d4
AV		 3283 ixgbe_napi_add_all(adapter);
3284
9a799d71
AK		 3285 strcpy(netdev->name, "eth%d");
3286 err = register_netdev(netdev);
3287 if (err)
3288 goto err_register;
3289
3290
3291 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
3292 cards_found++;
3293 return 0;
3294
3295err_register:
5eba3699 3296 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3297err_hw_init:
3298err_sw_init:
021230d4 3299 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3300err_eeprom:
3301 iounmap(hw->hw_addr);
3302err_ioremap:
3303 free_netdev(netdev);
3304err_alloc_etherdev:
3305 pci_release_regions(pdev);
3306err_pci_reg:
3307err_dma:
3308 pci_disable_device(pdev);
3309 return err;
3310}
3311
3312/**
3313 * ixgbe_remove - Device Removal Routine
3314 * @pdev: PCI device information struct
3315 *
3316 * ixgbe_remove is called by the PCI subsystem to alert the driver
3317 * that it should release a PCI device. The could be caused by a
3318 * Hot-Plug event, or because the driver is going to be removed from
3319 * memory.
3320 **/
3321static void __devexit ixgbe_remove(struct pci_dev *pdev)
3322{
3323 struct net_device *netdev = pci_get_drvdata(pdev);
3324 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3325
3326 set_bit(__IXGBE_DOWN, &adapter->state);
3327 del_timer_sync(&adapter->watchdog_timer);
3328
3329 flush_scheduled_work();
3330
3331 unregister_netdev(netdev);
3332
021230d4 3333 ixgbe_reset_interrupt_capability(adapter);
5eba3699 3334
021230d4 3335 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3336
3337 iounmap(adapter->hw.hw_addr);
3338 pci_release_regions(pdev);
3339
021230d4
AV		 3340 DPRINTK(PROBE, INFO, "complete\n");
3341 kfree(adapter->tx_ring);
3342 kfree(adapter->rx_ring);
3343
9a799d71
AK		 3344 free_netdev(netdev);
3345
3346 pci_disable_device(pdev);
3347}
3348
3349/**
3350 * ixgbe_io_error_detected - called when PCI error is detected
3351 * @pdev: Pointer to PCI device
3352 * @state: The current pci connection state
3353 *
3354 * This function is called after a PCI bus error affecting
3355 * this device has been detected.
3356 */
3357static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
3358 pci_channel_state_t state)
3359{
3360 struct net_device *netdev = pci_get_drvdata(pdev);
3361 struct ixgbe_adapter *adapter = netdev->priv;
3362
3363 netif_device_detach(netdev);
3364
3365 if (netif_running(netdev))
3366 ixgbe_down(adapter);
3367 pci_disable_device(pdev);
3368
3369 /* Request a slot slot reset. */
3370 return PCI_ERS_RESULT_NEED_RESET;
3371}
3372
3373/**
3374 * ixgbe_io_slot_reset - called after the pci bus has been reset.
3375 * @pdev: Pointer to PCI device
3376 *
3377 * Restart the card from scratch, as if from a cold-boot.
3378 */
3379static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
3380{
3381 struct net_device *netdev = pci_get_drvdata(pdev);
3382 struct ixgbe_adapter *adapter = netdev->priv;
3383
3384 if (pci_enable_device(pdev)) {
3385 DPRINTK(PROBE, ERR,
3386 "Cannot re-enable PCI device after reset.\n");
3387 return PCI_ERS_RESULT_DISCONNECT;
3388 }
3389 pci_set_master(pdev);
3390
3391 pci_enable_wake(pdev, PCI_D3hot, 0);
3392 pci_enable_wake(pdev, PCI_D3cold, 0);
3393
3394 ixgbe_reset(adapter);
3395
3396 return PCI_ERS_RESULT_RECOVERED;
3397}
3398
3399/**
3400 * ixgbe_io_resume - called when traffic can start flowing again.
3401 * @pdev: Pointer to PCI device
3402 *
3403 * This callback is called when the error recovery driver tells us that
3404 * its OK to resume normal operation.
3405 */
3406static void ixgbe_io_resume(struct pci_dev *pdev)
3407{
3408 struct net_device *netdev = pci_get_drvdata(pdev);
3409 struct ixgbe_adapter *adapter = netdev->priv;
3410
3411 if (netif_running(netdev)) {
3412 if (ixgbe_up(adapter)) {
3413 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
3414 return;
3415 }
3416 }
3417
3418 netif_device_attach(netdev);
3419
3420}
3421
3422static struct pci_error_handlers ixgbe_err_handler = {
3423 .error_detected = ixgbe_io_error_detected,
3424 .slot_reset = ixgbe_io_slot_reset,
3425 .resume = ixgbe_io_resume,
3426};
3427
3428static struct pci_driver ixgbe_driver = {
3429 .name = ixgbe_driver_name,
3430 .id_table = ixgbe_pci_tbl,
3431 .probe = ixgbe_probe,
3432 .remove = __devexit_p(ixgbe_remove),
3433#ifdef CONFIG_PM
3434 .suspend = ixgbe_suspend,
3435 .resume = ixgbe_resume,
3436#endif
3437 .shutdown = ixgbe_shutdown,
3438 .err_handler = &ixgbe_err_handler
3439};
3440
3441/**
3442 * ixgbe_init_module - Driver Registration Routine
3443 *
3444 * ixgbe_init_module is the first routine called when the driver is
3445 * loaded. All it does is register with the PCI subsystem.
3446 **/
3447static int __init ixgbe_init_module(void)
3448{
3449 int ret;
3450 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
3451 ixgbe_driver_string, ixgbe_driver_version);
3452
3453 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
3454
3455 ret = pci_register_driver(&ixgbe_driver);
3456 return ret;
3457}
3458module_init(ixgbe_init_module);
3459
3460/**
3461 * ixgbe_exit_module - Driver Exit Cleanup Routine
3462 *
3463 * ixgbe_exit_module is called just before the driver is removed
3464 * from memory.
3465 **/
3466static void __exit ixgbe_exit_module(void)
3467{
3468 pci_unregister_driver(&ixgbe_driver);
3469}
3470module_exit(ixgbe_exit_module);
3471
3472/* ixgbe_main.c */
Linux kernel - Deliverables
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