Commit | Line | Data |
---|---|---|
9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
3efac5a0 | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
37 | #include <linux/ipv6.h> | |
38 | #include <net/checksum.h> | |
39 | #include <net/ip6_checksum.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/if_vlan.h> | |
42 | ||
43 | #include "ixgbe.h" | |
44 | #include "ixgbe_common.h" | |
45 | ||
46 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 47 | static const char ixgbe_driver_string[] = |
b4617240 | 48 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
9a799d71 | 49 | |
e8e26350 | 50 | #define DRV_VERSION "2.0.8-k2" |
9c8eb720 | 51 | const char ixgbe_driver_version[] = DRV_VERSION; |
3efac5a0 | 52 | static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation."; |
9a799d71 AK |
53 | |
54 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 55 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 56 | [board_82599] = &ixgbe_82599_info, |
9a799d71 AK |
57 | }; |
58 | ||
59 | /* ixgbe_pci_tbl - PCI Device ID Table | |
60 | * | |
61 | * Wildcard entries (PCI_ANY_ID) should come last | |
62 | * Last entry must be all 0s | |
63 | * | |
64 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
65 | * Class, Class Mask, private data (not used) } | |
66 | */ | |
67 | static struct pci_device_id ixgbe_pci_tbl[] = { | |
1e336d0f DS |
68 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), |
69 | board_82598 }, | |
9a799d71 | 70 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), |
3957d63d | 71 | board_82598 }, |
9a799d71 | 72 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 73 | board_82598 }, |
0befdb3e JB |
74 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
75 | board_82598 }, | |
9a799d71 | 76 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 77 | board_82598 }, |
8d792cd9 JB |
78 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
79 | board_82598 }, | |
c4900be0 DS |
80 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
81 | board_82598 }, | |
82 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
83 | board_82598 }, | |
b95f5fcb JB |
84 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
85 | board_82598 }, | |
c4900be0 DS |
86 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
87 | board_82598 }, | |
2f21bdd3 DS |
88 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), |
89 | board_82598 }, | |
e8e26350 PW |
90 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), |
91 | board_82599 }, | |
92 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), | |
93 | board_82599 }, | |
9a799d71 AK |
94 | |
95 | /* required last entry */ | |
96 | {0, } | |
97 | }; | |
98 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
99 | ||
5dd2d332 | 100 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 101 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
b4617240 | 102 | void *p); |
bd0362dd JC |
103 | static struct notifier_block dca_notifier = { |
104 | .notifier_call = ixgbe_notify_dca, | |
105 | .next = NULL, | |
106 | .priority = 0 | |
107 | }; | |
108 | #endif | |
109 | ||
9a799d71 AK |
110 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
111 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
112 | MODULE_LICENSE("GPL"); | |
113 | MODULE_VERSION(DRV_VERSION); | |
114 | ||
115 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
116 | ||
5eba3699 AV |
117 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
118 | { | |
119 | u32 ctrl_ext; | |
120 | ||
121 | /* Let firmware take over control of h/w */ | |
122 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
123 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 124 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
125 | } |
126 | ||
127 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
128 | { | |
129 | u32 ctrl_ext; | |
130 | ||
131 | /* Let firmware know the driver has taken over */ | |
132 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
133 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 134 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 135 | } |
9a799d71 | 136 | |
e8e26350 PW |
137 | /* |
138 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
139 | * @adapter: pointer to adapter struct | |
140 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
141 | * @queue: queue to map the corresponding interrupt to | |
142 | * @msix_vector: the vector to map to the corresponding queue | |
143 | * | |
144 | */ | |
145 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
146 | u8 queue, u8 msix_vector) | |
9a799d71 AK |
147 | { |
148 | u32 ivar, index; | |
e8e26350 PW |
149 | struct ixgbe_hw *hw = &adapter->hw; |
150 | switch (hw->mac.type) { | |
151 | case ixgbe_mac_82598EB: | |
152 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
153 | if (direction == -1) | |
154 | direction = 0; | |
155 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
156 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
157 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
158 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
159 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
160 | break; | |
161 | case ixgbe_mac_82599EB: | |
162 | if (direction == -1) { | |
163 | /* other causes */ | |
164 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
165 | index = ((queue & 1) * 8); | |
166 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
167 | ivar &= ~(0xFF << index); | |
168 | ivar |= (msix_vector << index); | |
169 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
170 | break; | |
171 | } else { | |
172 | /* tx or rx causes */ | |
173 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
174 | index = ((16 * (queue & 1)) + (8 * direction)); | |
175 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
176 | ivar &= ~(0xFF << index); | |
177 | ivar |= (msix_vector << index); | |
178 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
179 | break; | |
180 | } | |
181 | default: | |
182 | break; | |
183 | } | |
9a799d71 AK |
184 | } |
185 | ||
186 | static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter, | |
b4617240 PW |
187 | struct ixgbe_tx_buffer |
188 | *tx_buffer_info) | |
9a799d71 AK |
189 | { |
190 | if (tx_buffer_info->dma) { | |
e01c31a5 | 191 | pci_unmap_page(adapter->pdev, tx_buffer_info->dma, |
b4617240 | 192 | tx_buffer_info->length, PCI_DMA_TODEVICE); |
9a799d71 AK |
193 | tx_buffer_info->dma = 0; |
194 | } | |
195 | if (tx_buffer_info->skb) { | |
196 | dev_kfree_skb_any(tx_buffer_info->skb); | |
197 | tx_buffer_info->skb = NULL; | |
198 | } | |
199 | /* tx_buffer_info must be completely set up in the transmit path */ | |
200 | } | |
201 | ||
202 | static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter, | |
b4617240 PW |
203 | struct ixgbe_ring *tx_ring, |
204 | unsigned int eop) | |
9a799d71 | 205 | { |
e01c31a5 JB |
206 | struct ixgbe_hw *hw = &adapter->hw; |
207 | u32 head, tail; | |
208 | ||
9a799d71 | 209 | /* Detect a transmit hang in hardware, this serializes the |
e01c31a5 JB |
210 | * check with the clearing of time_stamp and movement of eop */ |
211 | head = IXGBE_READ_REG(hw, tx_ring->head); | |
212 | tail = IXGBE_READ_REG(hw, tx_ring->tail); | |
9a799d71 | 213 | adapter->detect_tx_hung = false; |
e01c31a5 JB |
214 | if ((head != tail) && |
215 | tx_ring->tx_buffer_info[eop].time_stamp && | |
9a799d71 AK |
216 | time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) && |
217 | !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) { | |
218 | /* detected Tx unit hang */ | |
e01c31a5 JB |
219 | union ixgbe_adv_tx_desc *tx_desc; |
220 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
9a799d71 | 221 | DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n" |
e01c31a5 JB |
222 | " Tx Queue <%d>\n" |
223 | " TDH, TDT <%x>, <%x>\n" | |
9a799d71 AK |
224 | " next_to_use <%x>\n" |
225 | " next_to_clean <%x>\n" | |
226 | "tx_buffer_info[next_to_clean]\n" | |
227 | " time_stamp <%lx>\n" | |
e01c31a5 JB |
228 | " jiffies <%lx>\n", |
229 | tx_ring->queue_index, | |
230 | head, tail, | |
231 | tx_ring->next_to_use, eop, | |
232 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
9a799d71 AK |
233 | return true; |
234 | } | |
235 | ||
236 | return false; | |
237 | } | |
238 | ||
b4617240 PW |
239 | #define IXGBE_MAX_TXD_PWR 14 |
240 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
241 | |
242 | /* Tx Descriptors needed, worst case */ | |
243 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
244 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
245 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 246 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 247 | |
e01c31a5 JB |
248 | static void ixgbe_tx_timeout(struct net_device *netdev); |
249 | ||
9a799d71 AK |
250 | /** |
251 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
252 | * @adapter: board private structure | |
e01c31a5 | 253 | * @tx_ring: tx ring to clean |
9a799d71 AK |
254 | **/ |
255 | static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter, | |
e01c31a5 | 256 | struct ixgbe_ring *tx_ring) |
9a799d71 | 257 | { |
e01c31a5 | 258 | struct net_device *netdev = adapter->netdev; |
12207e49 PWJ |
259 | union ixgbe_adv_tx_desc *tx_desc, *eop_desc; |
260 | struct ixgbe_tx_buffer *tx_buffer_info; | |
261 | unsigned int i, eop, count = 0; | |
e01c31a5 | 262 | unsigned int total_bytes = 0, total_packets = 0; |
9a799d71 AK |
263 | |
264 | i = tx_ring->next_to_clean; | |
12207e49 PWJ |
265 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
266 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
267 | ||
268 | while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && | |
269 | (count < tx_ring->count)) { | |
270 | bool cleaned = false; | |
271 | for ( ; !cleaned; count++) { | |
272 | struct sk_buff *skb; | |
9a799d71 AK |
273 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); |
274 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
12207e49 | 275 | cleaned = (i == eop); |
e01c31a5 | 276 | skb = tx_buffer_info->skb; |
9a799d71 | 277 | |
12207e49 | 278 | if (cleaned && skb) { |
e092be60 | 279 | unsigned int segs, bytecount; |
e01c31a5 JB |
280 | |
281 | /* gso_segs is currently only valid for tcp */ | |
e092be60 AV |
282 | segs = skb_shinfo(skb)->gso_segs ?: 1; |
283 | /* multiply data chunks by size of headers */ | |
284 | bytecount = ((segs - 1) * skb_headlen(skb)) + | |
e01c31a5 JB |
285 | skb->len; |
286 | total_packets += segs; | |
287 | total_bytes += bytecount; | |
e092be60 | 288 | } |
e01c31a5 | 289 | |
9a799d71 | 290 | ixgbe_unmap_and_free_tx_resource(adapter, |
e01c31a5 | 291 | tx_buffer_info); |
9a799d71 | 292 | |
12207e49 PWJ |
293 | tx_desc->wb.status = 0; |
294 | ||
9a799d71 AK |
295 | i++; |
296 | if (i == tx_ring->count) | |
297 | i = 0; | |
e01c31a5 | 298 | } |
12207e49 PWJ |
299 | |
300 | eop = tx_ring->tx_buffer_info[i].next_to_watch; | |
301 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
302 | } | |
303 | ||
9a799d71 AK |
304 | tx_ring->next_to_clean = i; |
305 | ||
e092be60 | 306 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
e01c31a5 JB |
307 | if (unlikely(count && netif_carrier_ok(netdev) && |
308 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
e092be60 AV |
309 | /* Make sure that anybody stopping the queue after this |
310 | * sees the new next_to_clean. | |
311 | */ | |
312 | smp_mb(); | |
30eba97a AV |
313 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
314 | !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
315 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
e01c31a5 | 316 | ++adapter->restart_queue; |
30eba97a | 317 | } |
e092be60 | 318 | } |
9a799d71 | 319 | |
e01c31a5 JB |
320 | if (adapter->detect_tx_hung) { |
321 | if (ixgbe_check_tx_hang(adapter, tx_ring, i)) { | |
322 | /* schedule immediate reset if we believe we hung */ | |
323 | DPRINTK(PROBE, INFO, | |
324 | "tx hang %d detected, resetting adapter\n", | |
325 | adapter->tx_timeout_count + 1); | |
326 | ixgbe_tx_timeout(adapter->netdev); | |
327 | } | |
328 | } | |
9a799d71 | 329 | |
e01c31a5 JB |
330 | /* re-arm the interrupt */ |
331 | if ((total_packets >= tx_ring->work_limit) || | |
332 | (count == tx_ring->count)) | |
333 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx); | |
9a799d71 | 334 | |
e01c31a5 JB |
335 | tx_ring->total_bytes += total_bytes; |
336 | tx_ring->total_packets += total_packets; | |
e01c31a5 | 337 | tx_ring->stats.packets += total_packets; |
12207e49 | 338 | tx_ring->stats.bytes += total_bytes; |
e01c31a5 JB |
339 | adapter->net_stats.tx_bytes += total_bytes; |
340 | adapter->net_stats.tx_packets += total_packets; | |
341 | return (total_packets ? true : false); | |
9a799d71 AK |
342 | } |
343 | ||
5dd2d332 | 344 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 345 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
b4617240 | 346 | struct ixgbe_ring *rx_ring) |
bd0362dd JC |
347 | { |
348 | u32 rxctrl; | |
349 | int cpu = get_cpu(); | |
3a581073 | 350 | int q = rx_ring - adapter->rx_ring; |
bd0362dd | 351 | |
3a581073 | 352 | if (rx_ring->cpu != cpu) { |
bd0362dd | 353 | rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q)); |
e8e26350 PW |
354 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
355 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
356 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
357 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
358 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; | |
359 | rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
360 | IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); | |
361 | } | |
bd0362dd JC |
362 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
363 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
15005a32 DS |
364 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); |
365 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | | |
e8e26350 | 366 | IXGBE_DCA_RXCTRL_DESC_HSRO_EN); |
bd0362dd | 367 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); |
3a581073 | 368 | rx_ring->cpu = cpu; |
bd0362dd JC |
369 | } |
370 | put_cpu(); | |
371 | } | |
372 | ||
373 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
b4617240 | 374 | struct ixgbe_ring *tx_ring) |
bd0362dd JC |
375 | { |
376 | u32 txctrl; | |
377 | int cpu = get_cpu(); | |
3a581073 | 378 | int q = tx_ring - adapter->tx_ring; |
bd0362dd | 379 | |
3a581073 | 380 | if (tx_ring->cpu != cpu) { |
bd0362dd | 381 | txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q)); |
e8e26350 PW |
382 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
383 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; | |
384 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
385 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
386 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; | |
387 | txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
388 | IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); | |
389 | } | |
bd0362dd JC |
390 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
391 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl); | |
3a581073 | 392 | tx_ring->cpu = cpu; |
bd0362dd JC |
393 | } |
394 | put_cpu(); | |
395 | } | |
396 | ||
397 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
398 | { | |
399 | int i; | |
400 | ||
401 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
402 | return; | |
403 | ||
404 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
405 | adapter->tx_ring[i].cpu = -1; | |
406 | ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]); | |
407 | } | |
408 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
409 | adapter->rx_ring[i].cpu = -1; | |
410 | ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]); | |
411 | } | |
412 | } | |
413 | ||
414 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
415 | { | |
416 | struct net_device *netdev = dev_get_drvdata(dev); | |
417 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
418 | unsigned long event = *(unsigned long *)data; | |
419 | ||
420 | switch (event) { | |
421 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
422 | /* if we're already enabled, don't do it again */ |
423 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
424 | break; | |
bd0362dd JC |
425 | /* Always use CB2 mode, difference is masked |
426 | * in the CB driver. */ | |
427 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
652f093f | 428 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 429 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
430 | ixgbe_setup_dca(adapter); |
431 | break; | |
432 | } | |
433 | /* Fall Through since DCA is disabled. */ | |
434 | case DCA_PROVIDER_REMOVE: | |
435 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
436 | dca_remove_requester(dev); | |
437 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
438 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
439 | } | |
440 | break; | |
441 | } | |
442 | ||
652f093f | 443 | return 0; |
bd0362dd JC |
444 | } |
445 | ||
5dd2d332 | 446 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
447 | /** |
448 | * ixgbe_receive_skb - Send a completed packet up the stack | |
449 | * @adapter: board private structure | |
450 | * @skb: packet to send up | |
177db6ff MC |
451 | * @status: hardware indication of status of receive |
452 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
453 | * @rx_desc: rx descriptor | |
9a799d71 | 454 | **/ |
78b6f4ce | 455 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
b4617240 | 456 | struct sk_buff *skb, u8 status, |
177db6ff | 457 | union ixgbe_adv_rx_desc *rx_desc) |
9a799d71 | 458 | { |
78b6f4ce HX |
459 | struct ixgbe_adapter *adapter = q_vector->adapter; |
460 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
461 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
462 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 463 | |
0c8dfc83 | 464 | skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]); |
78b6f4ce | 465 | if (skb->ip_summed == CHECKSUM_UNNECESSARY) { |
2f90b865 | 466 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
78b6f4ce | 467 | vlan_gro_receive(napi, adapter->vlgrp, tag, skb); |
9a799d71 | 468 | else |
78b6f4ce | 469 | napi_gro_receive(napi, skb); |
177db6ff MC |
470 | } else { |
471 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { | |
2f90b865 | 472 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
177db6ff MC |
473 | vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag); |
474 | else | |
475 | netif_receive_skb(skb); | |
476 | } else { | |
2f90b865 | 477 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
177db6ff MC |
478 | vlan_hwaccel_rx(skb, adapter->vlgrp, tag); |
479 | else | |
480 | netif_rx(skb); | |
481 | } | |
9a799d71 AK |
482 | } |
483 | } | |
484 | ||
e59bd25d AV |
485 | /** |
486 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
487 | * @adapter: address of board private structure | |
488 | * @status_err: hardware indication of status of receive | |
489 | * @skb: skb currently being received and modified | |
490 | **/ | |
9a799d71 | 491 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
712744be | 492 | u32 status_err, struct sk_buff *skb) |
9a799d71 AK |
493 | { |
494 | skb->ip_summed = CHECKSUM_NONE; | |
495 | ||
712744be JB |
496 | /* Rx csum disabled */ |
497 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 498 | return; |
e59bd25d AV |
499 | |
500 | /* if IP and error */ | |
501 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
502 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
503 | adapter->hw_csum_rx_error++; |
504 | return; | |
505 | } | |
e59bd25d AV |
506 | |
507 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
508 | return; | |
509 | ||
510 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
511 | adapter->hw_csum_rx_error++; | |
512 | return; | |
513 | } | |
514 | ||
9a799d71 | 515 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 516 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
517 | adapter->hw_csum_rx_good++; |
518 | } | |
519 | ||
e8e26350 PW |
520 | static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw, |
521 | struct ixgbe_ring *rx_ring, u32 val) | |
522 | { | |
523 | /* | |
524 | * Force memory writes to complete before letting h/w | |
525 | * know there are new descriptors to fetch. (Only | |
526 | * applicable for weak-ordered memory model archs, | |
527 | * such as IA-64). | |
528 | */ | |
529 | wmb(); | |
530 | IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val); | |
531 | } | |
532 | ||
9a799d71 AK |
533 | /** |
534 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
535 | * @adapter: address of board private structure | |
536 | **/ | |
537 | static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter, | |
7c6e0a43 JB |
538 | struct ixgbe_ring *rx_ring, |
539 | int cleaned_count) | |
9a799d71 | 540 | { |
9a799d71 AK |
541 | struct pci_dev *pdev = adapter->pdev; |
542 | union ixgbe_adv_rx_desc *rx_desc; | |
3a581073 | 543 | struct ixgbe_rx_buffer *bi; |
9a799d71 | 544 | unsigned int i; |
e8e26350 | 545 | unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN; |
9a799d71 AK |
546 | |
547 | i = rx_ring->next_to_use; | |
3a581073 | 548 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
549 | |
550 | while (cleaned_count--) { | |
551 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
552 | ||
762f4c57 | 553 | if (!bi->page_dma && |
3a581073 | 554 | (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) { |
3a581073 | 555 | if (!bi->page) { |
762f4c57 JB |
556 | bi->page = alloc_page(GFP_ATOMIC); |
557 | if (!bi->page) { | |
558 | adapter->alloc_rx_page_failed++; | |
559 | goto no_buffers; | |
560 | } | |
561 | bi->page_offset = 0; | |
562 | } else { | |
563 | /* use a half page if we're re-using */ | |
564 | bi->page_offset ^= (PAGE_SIZE / 2); | |
9a799d71 | 565 | } |
762f4c57 JB |
566 | |
567 | bi->page_dma = pci_map_page(pdev, bi->page, | |
568 | bi->page_offset, | |
569 | (PAGE_SIZE / 2), | |
570 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
571 | } |
572 | ||
3a581073 | 573 | if (!bi->skb) { |
5ecc3614 | 574 | struct sk_buff *skb; |
e8e26350 | 575 | skb = netdev_alloc_skb(adapter->netdev, bufsz); |
9a799d71 AK |
576 | |
577 | if (!skb) { | |
578 | adapter->alloc_rx_buff_failed++; | |
579 | goto no_buffers; | |
580 | } | |
581 | ||
582 | /* | |
583 | * Make buffer alignment 2 beyond a 16 byte boundary | |
584 | * this will result in a 16 byte aligned IP header after | |
585 | * the 14 byte MAC header is removed | |
586 | */ | |
587 | skb_reserve(skb, NET_IP_ALIGN); | |
588 | ||
3a581073 | 589 | bi->skb = skb; |
e8e26350 | 590 | bi->dma = pci_map_single(pdev, skb->data, bufsz, |
3a581073 | 591 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
592 | } |
593 | /* Refresh the desc even if buffer_addrs didn't change because | |
594 | * each write-back erases this info. */ | |
595 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
3a581073 JB |
596 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
597 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 598 | } else { |
3a581073 | 599 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
9a799d71 AK |
600 | } |
601 | ||
602 | i++; | |
603 | if (i == rx_ring->count) | |
604 | i = 0; | |
3a581073 | 605 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 | 606 | } |
7c6e0a43 | 607 | |
9a799d71 AK |
608 | no_buffers: |
609 | if (rx_ring->next_to_use != i) { | |
610 | rx_ring->next_to_use = i; | |
611 | if (i-- == 0) | |
612 | i = (rx_ring->count - 1); | |
613 | ||
e8e26350 | 614 | ixgbe_release_rx_desc(&adapter->hw, rx_ring, i); |
9a799d71 AK |
615 | } |
616 | } | |
617 | ||
7c6e0a43 JB |
618 | static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc) |
619 | { | |
620 | return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
621 | } | |
622 | ||
623 | static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc) | |
624 | { | |
625 | return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
626 | } | |
627 | ||
78b6f4ce | 628 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
b4617240 PW |
629 | struct ixgbe_ring *rx_ring, |
630 | int *work_done, int work_to_do) | |
9a799d71 | 631 | { |
78b6f4ce | 632 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a799d71 AK |
633 | struct pci_dev *pdev = adapter->pdev; |
634 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; | |
635 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
636 | struct sk_buff *skb; | |
637 | unsigned int i; | |
7c6e0a43 | 638 | u32 len, staterr; |
177db6ff MC |
639 | u16 hdr_info; |
640 | bool cleaned = false; | |
9a799d71 | 641 | int cleaned_count = 0; |
d2f4fbe2 | 642 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
9a799d71 AK |
643 | |
644 | i = rx_ring->next_to_clean; | |
9a799d71 AK |
645 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); |
646 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
647 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
9a799d71 AK |
648 | |
649 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 650 | u32 upper_len = 0; |
9a799d71 AK |
651 | if (*work_done >= work_to_do) |
652 | break; | |
653 | (*work_done)++; | |
654 | ||
655 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 JB |
656 | hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); |
657 | len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
762f4c57 | 658 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; |
9a799d71 AK |
659 | if (hdr_info & IXGBE_RXDADV_SPH) |
660 | adapter->rx_hdr_split++; | |
661 | if (len > IXGBE_RX_HDR_SIZE) | |
662 | len = IXGBE_RX_HDR_SIZE; | |
663 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
7c6e0a43 | 664 | } else { |
9a799d71 | 665 | len = le16_to_cpu(rx_desc->wb.upper.length); |
7c6e0a43 | 666 | } |
9a799d71 AK |
667 | |
668 | cleaned = true; | |
669 | skb = rx_buffer_info->skb; | |
670 | prefetch(skb->data - NET_IP_ALIGN); | |
671 | rx_buffer_info->skb = NULL; | |
672 | ||
673 | if (len && !skb_shinfo(skb)->nr_frags) { | |
674 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
5ecc3614 | 675 | rx_ring->rx_buf_len, |
b4617240 | 676 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
677 | skb_put(skb, len); |
678 | } | |
679 | ||
680 | if (upper_len) { | |
681 | pci_unmap_page(pdev, rx_buffer_info->page_dma, | |
762f4c57 | 682 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9a799d71 AK |
683 | rx_buffer_info->page_dma = 0; |
684 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
762f4c57 JB |
685 | rx_buffer_info->page, |
686 | rx_buffer_info->page_offset, | |
687 | upper_len); | |
688 | ||
689 | if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) || | |
690 | (page_count(rx_buffer_info->page) != 1)) | |
691 | rx_buffer_info->page = NULL; | |
692 | else | |
693 | get_page(rx_buffer_info->page); | |
9a799d71 AK |
694 | |
695 | skb->len += upper_len; | |
696 | skb->data_len += upper_len; | |
697 | skb->truesize += upper_len; | |
698 | } | |
699 | ||
700 | i++; | |
701 | if (i == rx_ring->count) | |
702 | i = 0; | |
703 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
704 | ||
705 | next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
706 | prefetch(next_rxd); | |
707 | ||
708 | cleaned_count++; | |
709 | if (staterr & IXGBE_RXD_STAT_EOP) { | |
710 | rx_ring->stats.packets++; | |
711 | rx_ring->stats.bytes += skb->len; | |
712 | } else { | |
713 | rx_buffer_info->skb = next_buffer->skb; | |
714 | rx_buffer_info->dma = next_buffer->dma; | |
715 | next_buffer->skb = skb; | |
762f4c57 | 716 | next_buffer->dma = 0; |
9a799d71 AK |
717 | adapter->non_eop_descs++; |
718 | goto next_desc; | |
719 | } | |
720 | ||
721 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { | |
722 | dev_kfree_skb_irq(skb); | |
723 | goto next_desc; | |
724 | } | |
725 | ||
726 | ixgbe_rx_checksum(adapter, staterr, skb); | |
d2f4fbe2 AV |
727 | |
728 | /* probably a little skewed due to removing CRC */ | |
729 | total_rx_bytes += skb->len; | |
730 | total_rx_packets++; | |
731 | ||
74ce8dd2 | 732 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
78b6f4ce | 733 | ixgbe_receive_skb(q_vector, skb, staterr, rx_desc); |
9a799d71 AK |
734 | |
735 | next_desc: | |
736 | rx_desc->wb.upper.status_error = 0; | |
737 | ||
738 | /* return some buffers to hardware, one at a time is too slow */ | |
739 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
740 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
741 | cleaned_count = 0; | |
742 | } | |
743 | ||
744 | /* use prefetched values */ | |
745 | rx_desc = next_rxd; | |
746 | rx_buffer_info = next_buffer; | |
747 | ||
748 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
177db6ff MC |
749 | } |
750 | ||
9a799d71 AK |
751 | rx_ring->next_to_clean = i; |
752 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
753 | ||
754 | if (cleaned_count) | |
755 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
756 | ||
f494e8fa AV |
757 | rx_ring->total_packets += total_rx_packets; |
758 | rx_ring->total_bytes += total_rx_bytes; | |
759 | adapter->net_stats.rx_bytes += total_rx_bytes; | |
760 | adapter->net_stats.rx_packets += total_rx_packets; | |
761 | ||
9a799d71 AK |
762 | return cleaned; |
763 | } | |
764 | ||
021230d4 | 765 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
766 | /** |
767 | * ixgbe_configure_msix - Configure MSI-X hardware | |
768 | * @adapter: board private structure | |
769 | * | |
770 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
771 | * interrupts. | |
772 | **/ | |
773 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
774 | { | |
021230d4 AV |
775 | struct ixgbe_q_vector *q_vector; |
776 | int i, j, q_vectors, v_idx, r_idx; | |
777 | u32 mask; | |
9a799d71 | 778 | |
021230d4 | 779 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 780 | |
021230d4 AV |
781 | /* Populate the IVAR table and set the ITR values to the |
782 | * corresponding register. | |
783 | */ | |
784 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
785 | q_vector = &adapter->q_vector[v_idx]; | |
786 | /* XXX for_each_bit(...) */ | |
787 | r_idx = find_first_bit(q_vector->rxr_idx, | |
b4617240 | 788 | adapter->num_rx_queues); |
021230d4 AV |
789 | |
790 | for (i = 0; i < q_vector->rxr_count; i++) { | |
791 | j = adapter->rx_ring[r_idx].reg_idx; | |
e8e26350 | 792 | ixgbe_set_ivar(adapter, 0, j, v_idx); |
021230d4 | 793 | r_idx = find_next_bit(q_vector->rxr_idx, |
b4617240 PW |
794 | adapter->num_rx_queues, |
795 | r_idx + 1); | |
021230d4 AV |
796 | } |
797 | r_idx = find_first_bit(q_vector->txr_idx, | |
b4617240 | 798 | adapter->num_tx_queues); |
021230d4 AV |
799 | |
800 | for (i = 0; i < q_vector->txr_count; i++) { | |
801 | j = adapter->tx_ring[r_idx].reg_idx; | |
e8e26350 | 802 | ixgbe_set_ivar(adapter, 1, j, v_idx); |
021230d4 | 803 | r_idx = find_next_bit(q_vector->txr_idx, |
b4617240 PW |
804 | adapter->num_tx_queues, |
805 | r_idx + 1); | |
021230d4 AV |
806 | } |
807 | ||
30efa5a3 | 808 | /* if this is a tx only vector halve the interrupt rate */ |
021230d4 | 809 | if (q_vector->txr_count && !q_vector->rxr_count) |
30efa5a3 | 810 | q_vector->eitr = (adapter->eitr_param >> 1); |
021230d4 | 811 | else |
30efa5a3 JB |
812 | /* rx only */ |
813 | q_vector->eitr = adapter->eitr_param; | |
021230d4 AV |
814 | |
815 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), | |
b4617240 | 816 | EITR_INTS_PER_SEC_TO_REG(q_vector->eitr)); |
9a799d71 AK |
817 | } |
818 | ||
e8e26350 PW |
819 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
820 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, | |
821 | v_idx); | |
822 | else if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
823 | ixgbe_set_ivar(adapter, -1, 1, v_idx); | |
021230d4 AV |
824 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
825 | ||
41fb9248 | 826 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 827 | mask = IXGBE_EIMS_ENABLE_MASK; |
41fb9248 | 828 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); |
021230d4 | 829 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
830 | } |
831 | ||
f494e8fa AV |
832 | enum latency_range { |
833 | lowest_latency = 0, | |
834 | low_latency = 1, | |
835 | bulk_latency = 2, | |
836 | latency_invalid = 255 | |
837 | }; | |
838 | ||
839 | /** | |
840 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
841 | * @adapter: pointer to adapter | |
842 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
843 | * @itr_setting: current throttle rate in ints/second | |
844 | * @packets: the number of packets during this measurement interval | |
845 | * @bytes: the number of bytes during this measurement interval | |
846 | * | |
847 | * Stores a new ITR value based on packets and byte | |
848 | * counts during the last interrupt. The advantage of per interrupt | |
849 | * computation is faster updates and more accurate ITR for the current | |
850 | * traffic pattern. Constants in this function were computed | |
851 | * based on theoretical maximum wire speed and thresholds were set based | |
852 | * on testing data as well as attempting to minimize response time | |
853 | * while increasing bulk throughput. | |
854 | * this functionality is controlled by the InterruptThrottleRate module | |
855 | * parameter (see ixgbe_param.c) | |
856 | **/ | |
857 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
b4617240 PW |
858 | u32 eitr, u8 itr_setting, |
859 | int packets, int bytes) | |
f494e8fa AV |
860 | { |
861 | unsigned int retval = itr_setting; | |
862 | u32 timepassed_us; | |
863 | u64 bytes_perint; | |
864 | ||
865 | if (packets == 0) | |
866 | goto update_itr_done; | |
867 | ||
868 | ||
869 | /* simple throttlerate management | |
870 | * 0-20MB/s lowest (100000 ints/s) | |
871 | * 20-100MB/s low (20000 ints/s) | |
872 | * 100-1249MB/s bulk (8000 ints/s) | |
873 | */ | |
874 | /* what was last interrupt timeslice? */ | |
875 | timepassed_us = 1000000/eitr; | |
876 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
877 | ||
878 | switch (itr_setting) { | |
879 | case lowest_latency: | |
880 | if (bytes_perint > adapter->eitr_low) | |
881 | retval = low_latency; | |
882 | break; | |
883 | case low_latency: | |
884 | if (bytes_perint > adapter->eitr_high) | |
885 | retval = bulk_latency; | |
886 | else if (bytes_perint <= adapter->eitr_low) | |
887 | retval = lowest_latency; | |
888 | break; | |
889 | case bulk_latency: | |
890 | if (bytes_perint <= adapter->eitr_high) | |
891 | retval = low_latency; | |
892 | break; | |
893 | } | |
894 | ||
895 | update_itr_done: | |
896 | return retval; | |
897 | } | |
898 | ||
899 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) | |
900 | { | |
901 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
902 | struct ixgbe_hw *hw = &adapter->hw; | |
903 | u32 new_itr; | |
904 | u8 current_itr, ret_itr; | |
905 | int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) / | |
b4617240 | 906 | sizeof(struct ixgbe_q_vector); |
f494e8fa AV |
907 | struct ixgbe_ring *rx_ring, *tx_ring; |
908 | ||
909 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
910 | for (i = 0; i < q_vector->txr_count; i++) { | |
911 | tx_ring = &(adapter->tx_ring[r_idx]); | |
912 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
913 | q_vector->tx_itr, |
914 | tx_ring->total_packets, | |
915 | tx_ring->total_bytes); | |
f494e8fa AV |
916 | /* if the result for this queue would decrease interrupt |
917 | * rate for this vector then use that result */ | |
30efa5a3 | 918 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
b4617240 | 919 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 920 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 921 | r_idx + 1); |
f494e8fa AV |
922 | } |
923 | ||
924 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
925 | for (i = 0; i < q_vector->rxr_count; i++) { | |
926 | rx_ring = &(adapter->rx_ring[r_idx]); | |
927 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
928 | q_vector->rx_itr, |
929 | rx_ring->total_packets, | |
930 | rx_ring->total_bytes); | |
f494e8fa AV |
931 | /* if the result for this queue would decrease interrupt |
932 | * rate for this vector then use that result */ | |
30efa5a3 | 933 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
b4617240 | 934 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 935 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
b4617240 | 936 | r_idx + 1); |
f494e8fa AV |
937 | } |
938 | ||
30efa5a3 | 939 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
940 | |
941 | switch (current_itr) { | |
942 | /* counts and packets in update_itr are dependent on these numbers */ | |
943 | case lowest_latency: | |
944 | new_itr = 100000; | |
945 | break; | |
946 | case low_latency: | |
947 | new_itr = 20000; /* aka hwitr = ~200 */ | |
948 | break; | |
949 | case bulk_latency: | |
950 | default: | |
951 | new_itr = 8000; | |
952 | break; | |
953 | } | |
954 | ||
955 | if (new_itr != q_vector->eitr) { | |
956 | u32 itr_reg; | |
957 | /* do an exponential smoothing */ | |
958 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
959 | q_vector->eitr = new_itr; | |
960 | itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); | |
e8e26350 PW |
961 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
962 | /* Resolution is 2 usec on 82599, so halve the rate */ | |
963 | itr_reg >>= 1; | |
f494e8fa AV |
964 | /* must write high and low 16 bits to reset counter */ |
965 | DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx, | |
b4617240 | 966 | itr_reg); |
f494e8fa AV |
967 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16); |
968 | } | |
969 | ||
970 | return; | |
971 | } | |
972 | ||
0befdb3e JB |
973 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
974 | { | |
975 | struct ixgbe_hw *hw = &adapter->hw; | |
976 | ||
977 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
978 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
979 | DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n"); | |
980 | /* write to clear the interrupt */ | |
981 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
982 | } | |
983 | } | |
cf8280ee | 984 | |
e8e26350 PW |
985 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
986 | { | |
987 | struct ixgbe_hw *hw = &adapter->hw; | |
988 | ||
989 | if (eicr & IXGBE_EICR_GPI_SDP1) { | |
990 | /* Clear the interrupt */ | |
991 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
992 | schedule_work(&adapter->multispeed_fiber_task); | |
993 | } else if (eicr & IXGBE_EICR_GPI_SDP2) { | |
994 | /* Clear the interrupt */ | |
995 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
996 | schedule_work(&adapter->sfp_config_module_task); | |
997 | } else { | |
998 | /* Interrupt isn't for us... */ | |
999 | return; | |
1000 | } | |
1001 | } | |
1002 | ||
cf8280ee JB |
1003 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
1004 | { | |
1005 | struct ixgbe_hw *hw = &adapter->hw; | |
1006 | ||
1007 | adapter->lsc_int++; | |
1008 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
1009 | adapter->link_check_timeout = jiffies; | |
1010 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1011 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
1012 | schedule_work(&adapter->watchdog_task); | |
1013 | } | |
1014 | } | |
1015 | ||
9a799d71 AK |
1016 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
1017 | { | |
1018 | struct net_device *netdev = data; | |
1019 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1020 | struct ixgbe_hw *hw = &adapter->hw; | |
54037505 DS |
1021 | u32 eicr; |
1022 | ||
1023 | /* | |
1024 | * Workaround for Silicon errata. Use clear-by-write instead | |
1025 | * of clear-by-read. Reading with EICS will return the | |
1026 | * interrupt causes without clearing, which later be done | |
1027 | * with the write to EICR. | |
1028 | */ | |
1029 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
1030 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
9a799d71 | 1031 | |
cf8280ee JB |
1032 | if (eicr & IXGBE_EICR_LSC) |
1033 | ixgbe_check_lsc(adapter); | |
d4f80882 | 1034 | |
e8e26350 PW |
1035 | if (hw->mac.type == ixgbe_mac_82598EB) |
1036 | ixgbe_check_fan_failure(adapter, eicr); | |
0befdb3e | 1037 | |
e8e26350 PW |
1038 | if (hw->mac.type == ixgbe_mac_82599EB) |
1039 | ixgbe_check_sfp_event(adapter, eicr); | |
d4f80882 AV |
1040 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1041 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
1042 | |
1043 | return IRQ_HANDLED; | |
1044 | } | |
1045 | ||
1046 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) | |
1047 | { | |
021230d4 AV |
1048 | struct ixgbe_q_vector *q_vector = data; |
1049 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1050 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
1051 | int i, r_idx; |
1052 | ||
1053 | if (!q_vector->txr_count) | |
1054 | return IRQ_HANDLED; | |
1055 | ||
1056 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1057 | for (i = 0; i < q_vector->txr_count; i++) { | |
3a581073 | 1058 | tx_ring = &(adapter->tx_ring[r_idx]); |
5dd2d332 | 1059 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1060 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1061 | ixgbe_update_tx_dca(adapter, tx_ring); |
bd0362dd | 1062 | #endif |
3a581073 JB |
1063 | tx_ring->total_bytes = 0; |
1064 | tx_ring->total_packets = 0; | |
1065 | ixgbe_clean_tx_irq(adapter, tx_ring); | |
021230d4 | 1066 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1067 | r_idx + 1); |
021230d4 | 1068 | } |
9a799d71 | 1069 | |
9a799d71 AK |
1070 | return IRQ_HANDLED; |
1071 | } | |
1072 | ||
021230d4 AV |
1073 | /** |
1074 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
1075 | * @irq: unused | |
1076 | * @data: pointer to our q_vector struct for this interrupt vector | |
1077 | **/ | |
9a799d71 AK |
1078 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
1079 | { | |
021230d4 AV |
1080 | struct ixgbe_q_vector *q_vector = data; |
1081 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1082 | struct ixgbe_ring *rx_ring; |
021230d4 | 1083 | int r_idx; |
30efa5a3 | 1084 | int i; |
021230d4 AV |
1085 | |
1086 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
30efa5a3 JB |
1087 | for (i = 0; i < q_vector->rxr_count; i++) { |
1088 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1089 | rx_ring->total_bytes = 0; | |
1090 | rx_ring->total_packets = 0; | |
1091 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1092 | r_idx + 1); | |
1093 | } | |
1094 | ||
021230d4 AV |
1095 | if (!q_vector->rxr_count) |
1096 | return IRQ_HANDLED; | |
1097 | ||
30efa5a3 | 1098 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1099 | rx_ring = &(adapter->rx_ring[r_idx]); |
021230d4 | 1100 | /* disable interrupts on this vector only */ |
3a581073 | 1101 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx); |
288379f0 | 1102 | napi_schedule(&q_vector->napi); |
021230d4 AV |
1103 | |
1104 | return IRQ_HANDLED; | |
1105 | } | |
1106 | ||
1107 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
1108 | { | |
1109 | ixgbe_msix_clean_rx(irq, data); | |
1110 | ixgbe_msix_clean_tx(irq, data); | |
9a799d71 | 1111 | |
9a799d71 AK |
1112 | return IRQ_HANDLED; |
1113 | } | |
1114 | ||
021230d4 AV |
1115 | /** |
1116 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
1117 | * @napi: napi struct with our devices info in it | |
1118 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1119 | * | |
f0848276 JB |
1120 | * This function is optimized for cleaning one queue only on a single |
1121 | * q_vector!!! | |
021230d4 | 1122 | **/ |
9a799d71 AK |
1123 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
1124 | { | |
021230d4 | 1125 | struct ixgbe_q_vector *q_vector = |
b4617240 | 1126 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 1127 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 1128 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 1129 | int work_done = 0; |
021230d4 | 1130 | long r_idx; |
9a799d71 | 1131 | |
021230d4 | 1132 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1133 | rx_ring = &(adapter->rx_ring[r_idx]); |
5dd2d332 | 1134 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1135 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1136 | ixgbe_update_rx_dca(adapter, rx_ring); |
bd0362dd | 1137 | #endif |
9a799d71 | 1138 | |
78b6f4ce | 1139 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
9a799d71 | 1140 | |
021230d4 AV |
1141 | /* If all Rx work done, exit the polling mode */ |
1142 | if (work_done < budget) { | |
288379f0 | 1143 | napi_complete(napi); |
30efa5a3 | 1144 | if (adapter->itr_setting & 3) |
f494e8fa | 1145 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 1146 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
3a581073 | 1147 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx); |
9a799d71 AK |
1148 | } |
1149 | ||
1150 | return work_done; | |
1151 | } | |
1152 | ||
f0848276 JB |
1153 | /** |
1154 | * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine | |
1155 | * @napi: napi struct with our devices info in it | |
1156 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1157 | * | |
1158 | * This function will clean more than one rx queue associated with a | |
1159 | * q_vector. | |
1160 | **/ | |
1161 | static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget) | |
1162 | { | |
1163 | struct ixgbe_q_vector *q_vector = | |
1164 | container_of(napi, struct ixgbe_q_vector, napi); | |
1165 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f0848276 JB |
1166 | struct ixgbe_ring *rx_ring = NULL; |
1167 | int work_done = 0, i; | |
1168 | long r_idx; | |
1169 | u16 enable_mask = 0; | |
1170 | ||
1171 | /* attempt to distribute budget to each queue fairly, but don't allow | |
1172 | * the budget to go below 1 because we'll exit polling */ | |
1173 | budget /= (q_vector->rxr_count ?: 1); | |
1174 | budget = max(budget, 1); | |
1175 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1176 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1177 | rx_ring = &(adapter->rx_ring[r_idx]); | |
5dd2d332 | 1178 | #ifdef CONFIG_IXGBE_DCA |
f0848276 JB |
1179 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1180 | ixgbe_update_rx_dca(adapter, rx_ring); | |
1181 | #endif | |
78b6f4ce | 1182 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
f0848276 JB |
1183 | enable_mask |= rx_ring->v_idx; |
1184 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1185 | r_idx + 1); | |
1186 | } | |
1187 | ||
1188 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1189 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1190 | /* If all Rx work done, exit the polling mode */ | |
7f821875 | 1191 | if (work_done < budget) { |
288379f0 | 1192 | napi_complete(napi); |
f0848276 JB |
1193 | if (adapter->itr_setting & 3) |
1194 | ixgbe_set_itr_msix(q_vector); | |
1195 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1196 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask); | |
1197 | return 0; | |
1198 | } | |
1199 | ||
1200 | return work_done; | |
1201 | } | |
021230d4 | 1202 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
b4617240 | 1203 | int r_idx) |
021230d4 AV |
1204 | { |
1205 | a->q_vector[v_idx].adapter = a; | |
1206 | set_bit(r_idx, a->q_vector[v_idx].rxr_idx); | |
1207 | a->q_vector[v_idx].rxr_count++; | |
1208 | a->rx_ring[r_idx].v_idx = 1 << v_idx; | |
1209 | } | |
1210 | ||
1211 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
b4617240 | 1212 | int r_idx) |
021230d4 AV |
1213 | { |
1214 | a->q_vector[v_idx].adapter = a; | |
1215 | set_bit(r_idx, a->q_vector[v_idx].txr_idx); | |
1216 | a->q_vector[v_idx].txr_count++; | |
1217 | a->tx_ring[r_idx].v_idx = 1 << v_idx; | |
1218 | } | |
1219 | ||
9a799d71 | 1220 | /** |
021230d4 AV |
1221 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
1222 | * @adapter: board private structure to initialize | |
1223 | * @vectors: allotted vector count for descriptor rings | |
9a799d71 | 1224 | * |
021230d4 AV |
1225 | * This function maps descriptor rings to the queue-specific vectors |
1226 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
1227 | * one vector per ring/queue, but on a constrained vector budget, we | |
1228 | * group the rings as "efficiently" as possible. You would add new | |
1229 | * mapping configurations in here. | |
9a799d71 | 1230 | **/ |
021230d4 | 1231 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 1232 | int vectors) |
021230d4 AV |
1233 | { |
1234 | int v_start = 0; | |
1235 | int rxr_idx = 0, txr_idx = 0; | |
1236 | int rxr_remaining = adapter->num_rx_queues; | |
1237 | int txr_remaining = adapter->num_tx_queues; | |
1238 | int i, j; | |
1239 | int rqpv, tqpv; | |
1240 | int err = 0; | |
1241 | ||
1242 | /* No mapping required if MSI-X is disabled. */ | |
1243 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1244 | goto out; | |
9a799d71 | 1245 | |
021230d4 AV |
1246 | /* |
1247 | * The ideal configuration... | |
1248 | * We have enough vectors to map one per queue. | |
1249 | */ | |
1250 | if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) { | |
1251 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) | |
1252 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 1253 | |
021230d4 AV |
1254 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
1255 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 1256 | |
9a799d71 | 1257 | goto out; |
021230d4 | 1258 | } |
9a799d71 | 1259 | |
021230d4 AV |
1260 | /* |
1261 | * If we don't have enough vectors for a 1-to-1 | |
1262 | * mapping, we'll have to group them so there are | |
1263 | * multiple queues per vector. | |
1264 | */ | |
1265 | /* Re-adjusting *qpv takes care of the remainder. */ | |
1266 | for (i = v_start; i < vectors; i++) { | |
1267 | rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i); | |
1268 | for (j = 0; j < rqpv; j++) { | |
1269 | map_vector_to_rxq(adapter, i, rxr_idx); | |
1270 | rxr_idx++; | |
1271 | rxr_remaining--; | |
1272 | } | |
1273 | } | |
1274 | for (i = v_start; i < vectors; i++) { | |
1275 | tqpv = DIV_ROUND_UP(txr_remaining, vectors - i); | |
1276 | for (j = 0; j < tqpv; j++) { | |
1277 | map_vector_to_txq(adapter, i, txr_idx); | |
1278 | txr_idx++; | |
1279 | txr_remaining--; | |
9a799d71 | 1280 | } |
9a799d71 AK |
1281 | } |
1282 | ||
021230d4 AV |
1283 | out: |
1284 | return err; | |
1285 | } | |
1286 | ||
1287 | /** | |
1288 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
1289 | * @adapter: board private structure | |
1290 | * | |
1291 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
1292 | * interrupts from the kernel. | |
1293 | **/ | |
1294 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
1295 | { | |
1296 | struct net_device *netdev = adapter->netdev; | |
1297 | irqreturn_t (*handler)(int, void *); | |
1298 | int i, vector, q_vectors, err; | |
cb13fc20 | 1299 | int ri=0, ti=0; |
021230d4 AV |
1300 | |
1301 | /* Decrement for Other and TCP Timer vectors */ | |
1302 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1303 | ||
1304 | /* Map the Tx/Rx rings to the vectors we were allotted. */ | |
1305 | err = ixgbe_map_rings_to_vectors(adapter, q_vectors); | |
1306 | if (err) | |
1307 | goto out; | |
1308 | ||
1309 | #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \ | |
b4617240 PW |
1310 | (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \ |
1311 | &ixgbe_msix_clean_many) | |
021230d4 AV |
1312 | for (vector = 0; vector < q_vectors; vector++) { |
1313 | handler = SET_HANDLER(&adapter->q_vector[vector]); | |
cb13fc20 RO |
1314 | |
1315 | if(handler == &ixgbe_msix_clean_rx) { | |
1316 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1317 | netdev->name, "rx", ri++); | |
1318 | } | |
1319 | else if(handler == &ixgbe_msix_clean_tx) { | |
1320 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1321 | netdev->name, "tx", ti++); | |
1322 | } | |
1323 | else | |
1324 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1325 | netdev->name, "TxRx", vector); | |
1326 | ||
021230d4 | 1327 | err = request_irq(adapter->msix_entries[vector].vector, |
b4617240 PW |
1328 | handler, 0, adapter->name[vector], |
1329 | &(adapter->q_vector[vector])); | |
9a799d71 AK |
1330 | if (err) { |
1331 | DPRINTK(PROBE, ERR, | |
b4617240 PW |
1332 | "request_irq failed for MSIX interrupt " |
1333 | "Error: %d\n", err); | |
021230d4 | 1334 | goto free_queue_irqs; |
9a799d71 | 1335 | } |
9a799d71 AK |
1336 | } |
1337 | ||
021230d4 AV |
1338 | sprintf(adapter->name[vector], "%s:lsc", netdev->name); |
1339 | err = request_irq(adapter->msix_entries[vector].vector, | |
b4617240 | 1340 | &ixgbe_msix_lsc, 0, adapter->name[vector], netdev); |
9a799d71 AK |
1341 | if (err) { |
1342 | DPRINTK(PROBE, ERR, | |
1343 | "request_irq for msix_lsc failed: %d\n", err); | |
021230d4 | 1344 | goto free_queue_irqs; |
9a799d71 AK |
1345 | } |
1346 | ||
9a799d71 AK |
1347 | return 0; |
1348 | ||
021230d4 AV |
1349 | free_queue_irqs: |
1350 | for (i = vector - 1; i >= 0; i--) | |
1351 | free_irq(adapter->msix_entries[--vector].vector, | |
b4617240 | 1352 | &(adapter->q_vector[i])); |
021230d4 AV |
1353 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
1354 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
1355 | kfree(adapter->msix_entries); |
1356 | adapter->msix_entries = NULL; | |
021230d4 | 1357 | out: |
9a799d71 AK |
1358 | return err; |
1359 | } | |
1360 | ||
f494e8fa AV |
1361 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
1362 | { | |
1363 | struct ixgbe_hw *hw = &adapter->hw; | |
1364 | struct ixgbe_q_vector *q_vector = adapter->q_vector; | |
1365 | u8 current_itr; | |
1366 | u32 new_itr = q_vector->eitr; | |
1367 | struct ixgbe_ring *rx_ring = &adapter->rx_ring[0]; | |
1368 | struct ixgbe_ring *tx_ring = &adapter->tx_ring[0]; | |
1369 | ||
30efa5a3 | 1370 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1371 | q_vector->tx_itr, |
1372 | tx_ring->total_packets, | |
1373 | tx_ring->total_bytes); | |
30efa5a3 | 1374 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1375 | q_vector->rx_itr, |
1376 | rx_ring->total_packets, | |
1377 | rx_ring->total_bytes); | |
f494e8fa | 1378 | |
30efa5a3 | 1379 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1380 | |
1381 | switch (current_itr) { | |
1382 | /* counts and packets in update_itr are dependent on these numbers */ | |
1383 | case lowest_latency: | |
1384 | new_itr = 100000; | |
1385 | break; | |
1386 | case low_latency: | |
1387 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1388 | break; | |
1389 | case bulk_latency: | |
1390 | new_itr = 8000; | |
1391 | break; | |
1392 | default: | |
1393 | break; | |
1394 | } | |
1395 | ||
1396 | if (new_itr != q_vector->eitr) { | |
1397 | u32 itr_reg; | |
1398 | /* do an exponential smoothing */ | |
1399 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
1400 | q_vector->eitr = new_itr; | |
1401 | itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); | |
e8e26350 PW |
1402 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
1403 | /* Resolution is 2 usec on 82599, so halve the rate */ | |
1404 | itr_reg >>= 1; | |
f494e8fa AV |
1405 | /* must write high and low 16 bits to reset counter */ |
1406 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16); | |
1407 | } | |
1408 | ||
1409 | return; | |
1410 | } | |
1411 | ||
79aefa45 AD |
1412 | /** |
1413 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
1414 | * @adapter: board private structure | |
1415 | **/ | |
1416 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
1417 | { | |
1418 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); | |
e8e26350 PW |
1419 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
1420 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); | |
1421 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(2), ~0); | |
1422 | } | |
79aefa45 AD |
1423 | IXGBE_WRITE_FLUSH(&adapter->hw); |
1424 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
1425 | int i; | |
1426 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
1427 | synchronize_irq(adapter->msix_entries[i].vector); | |
1428 | } else { | |
1429 | synchronize_irq(adapter->pdev->irq); | |
1430 | } | |
1431 | } | |
1432 | ||
1433 | /** | |
1434 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
1435 | * @adapter: board private structure | |
1436 | **/ | |
1437 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) | |
1438 | { | |
1439 | u32 mask; | |
1440 | mask = IXGBE_EIMS_ENABLE_MASK; | |
6ab33d51 DM |
1441 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
1442 | mask |= IXGBE_EIMS_GPI_SDP1; | |
e8e26350 PW |
1443 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
1444 | mask |= IXGBE_EIMS_GPI_SDP1; | |
1445 | mask |= IXGBE_EIMS_GPI_SDP2; | |
1446 | } | |
1447 | ||
79aefa45 | 1448 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
e8e26350 PW |
1449 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
1450 | /* enable the rest of the queue vectors */ | |
1451 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), | |
1452 | (IXGBE_EIMS_RTX_QUEUE << 16)); | |
1453 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(2), | |
1454 | ((IXGBE_EIMS_RTX_QUEUE << 16) | | |
1455 | IXGBE_EIMS_RTX_QUEUE)); | |
1456 | } | |
79aefa45 AD |
1457 | IXGBE_WRITE_FLUSH(&adapter->hw); |
1458 | } | |
021230d4 | 1459 | |
9a799d71 | 1460 | /** |
021230d4 | 1461 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
1462 | * @irq: interrupt number |
1463 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
1464 | **/ |
1465 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
1466 | { | |
1467 | struct net_device *netdev = data; | |
1468 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1469 | struct ixgbe_hw *hw = &adapter->hw; | |
1470 | u32 eicr; | |
1471 | ||
54037505 DS |
1472 | /* |
1473 | * Workaround for silicon errata. Mask the interrupts | |
1474 | * before the read of EICR. | |
1475 | */ | |
1476 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
1477 | ||
021230d4 AV |
1478 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
1479 | * therefore no explict interrupt disable is necessary */ | |
1480 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e JB |
1481 | if (!eicr) { |
1482 | /* shared interrupt alert! | |
1483 | * make sure interrupts are enabled because the read will | |
1484 | * have disabled interrupts due to EIAM */ | |
1485 | ixgbe_irq_enable(adapter); | |
9a799d71 | 1486 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 1487 | } |
9a799d71 | 1488 | |
cf8280ee JB |
1489 | if (eicr & IXGBE_EICR_LSC) |
1490 | ixgbe_check_lsc(adapter); | |
021230d4 | 1491 | |
e8e26350 PW |
1492 | if (hw->mac.type == ixgbe_mac_82599EB) |
1493 | ixgbe_check_sfp_event(adapter, eicr); | |
1494 | ||
0befdb3e JB |
1495 | ixgbe_check_fan_failure(adapter, eicr); |
1496 | ||
288379f0 | 1497 | if (napi_schedule_prep(&adapter->q_vector[0].napi)) { |
f494e8fa AV |
1498 | adapter->tx_ring[0].total_packets = 0; |
1499 | adapter->tx_ring[0].total_bytes = 0; | |
1500 | adapter->rx_ring[0].total_packets = 0; | |
1501 | adapter->rx_ring[0].total_bytes = 0; | |
021230d4 | 1502 | /* would disable interrupts here but EIAM disabled it */ |
288379f0 | 1503 | __napi_schedule(&adapter->q_vector[0].napi); |
9a799d71 AK |
1504 | } |
1505 | ||
1506 | return IRQ_HANDLED; | |
1507 | } | |
1508 | ||
021230d4 AV |
1509 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
1510 | { | |
1511 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1512 | ||
1513 | for (i = 0; i < q_vectors; i++) { | |
1514 | struct ixgbe_q_vector *q_vector = &adapter->q_vector[i]; | |
1515 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); | |
1516 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
1517 | q_vector->rxr_count = 0; | |
1518 | q_vector->txr_count = 0; | |
1519 | } | |
1520 | } | |
1521 | ||
9a799d71 AK |
1522 | /** |
1523 | * ixgbe_request_irq - initialize interrupts | |
1524 | * @adapter: board private structure | |
1525 | * | |
1526 | * Attempts to configure interrupts using the best available | |
1527 | * capabilities of the hardware and kernel. | |
1528 | **/ | |
021230d4 | 1529 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
1530 | { |
1531 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 1532 | int err; |
9a799d71 | 1533 | |
021230d4 AV |
1534 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
1535 | err = ixgbe_request_msix_irqs(adapter); | |
1536 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
1537 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0, | |
b4617240 | 1538 | netdev->name, netdev); |
021230d4 AV |
1539 | } else { |
1540 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED, | |
b4617240 | 1541 | netdev->name, netdev); |
9a799d71 AK |
1542 | } |
1543 | ||
9a799d71 AK |
1544 | if (err) |
1545 | DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err); | |
1546 | ||
9a799d71 AK |
1547 | return err; |
1548 | } | |
1549 | ||
1550 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
1551 | { | |
1552 | struct net_device *netdev = adapter->netdev; | |
1553 | ||
1554 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 1555 | int i, q_vectors; |
9a799d71 | 1556 | |
021230d4 AV |
1557 | q_vectors = adapter->num_msix_vectors; |
1558 | ||
1559 | i = q_vectors - 1; | |
9a799d71 | 1560 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 1561 | |
021230d4 AV |
1562 | i--; |
1563 | for (; i >= 0; i--) { | |
1564 | free_irq(adapter->msix_entries[i].vector, | |
b4617240 | 1565 | &(adapter->q_vector[i])); |
021230d4 AV |
1566 | } |
1567 | ||
1568 | ixgbe_reset_q_vectors(adapter); | |
1569 | } else { | |
1570 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
1571 | } |
1572 | } | |
1573 | ||
9a799d71 AK |
1574 | /** |
1575 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
1576 | * | |
1577 | **/ | |
1578 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
1579 | { | |
9a799d71 AK |
1580 | struct ixgbe_hw *hw = &adapter->hw; |
1581 | ||
021230d4 | 1582 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
30efa5a3 | 1583 | EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param)); |
9a799d71 | 1584 | |
e8e26350 PW |
1585 | ixgbe_set_ivar(adapter, 0, 0, 0); |
1586 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 AV |
1587 | |
1588 | map_vector_to_rxq(adapter, 0, 0); | |
1589 | map_vector_to_txq(adapter, 0, 0); | |
1590 | ||
1591 | DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n"); | |
9a799d71 AK |
1592 | } |
1593 | ||
1594 | /** | |
3a581073 | 1595 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
1596 | * @adapter: board private structure |
1597 | * | |
1598 | * Configure the Tx unit of the MAC after a reset. | |
1599 | **/ | |
1600 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
1601 | { | |
12207e49 | 1602 | u64 tdba; |
9a799d71 | 1603 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 1604 | u32 i, j, tdlen, txctrl; |
9a799d71 AK |
1605 | |
1606 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
1607 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
e01c31a5 JB |
1608 | struct ixgbe_ring *ring = &adapter->tx_ring[i]; |
1609 | j = ring->reg_idx; | |
1610 | tdba = ring->dma; | |
1611 | tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc); | |
021230d4 | 1612 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), |
e01c31a5 | 1613 | (tdba & DMA_32BIT_MASK)); |
021230d4 AV |
1614 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); |
1615 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen); | |
1616 | IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); | |
1617 | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | |
1618 | adapter->tx_ring[i].head = IXGBE_TDH(j); | |
1619 | adapter->tx_ring[i].tail = IXGBE_TDT(j); | |
1620 | /* Disable Tx Head Writeback RO bit, since this hoses | |
1621 | * bookkeeping if things aren't delivered in order. | |
1622 | */ | |
e01c31a5 | 1623 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); |
021230d4 | 1624 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; |
e01c31a5 | 1625 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); |
9a799d71 | 1626 | } |
e8e26350 PW |
1627 | if (hw->mac.type == ixgbe_mac_82599EB) { |
1628 | /* We enable 8 traffic classes, DCB only */ | |
1629 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
1630 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA | | |
1631 | IXGBE_MTQC_8TC_8TQ)); | |
1632 | } | |
9a799d71 AK |
1633 | } |
1634 | ||
e8e26350 | 1635 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c JB |
1636 | |
1637 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index) | |
1638 | { | |
1639 | struct ixgbe_ring *rx_ring; | |
1640 | u32 srrctl; | |
e8e26350 | 1641 | int queue0 = 0; |
3be1adfb AD |
1642 | unsigned long mask; |
1643 | ||
e8e26350 PW |
1644 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
1645 | queue0 = index; | |
cc41ac7c | 1646 | } else { |
3be1adfb AD |
1647 | mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask; |
1648 | queue0 = index & mask; | |
1649 | index = index & mask; | |
cc41ac7c | 1650 | } |
3be1adfb | 1651 | |
cc41ac7c JB |
1652 | rx_ring = &adapter->rx_ring[queue0]; |
1653 | ||
1654 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index)); | |
1655 | ||
1656 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
1657 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
1658 | ||
1659 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
32344a39 JB |
1660 | u16 bufsz = IXGBE_RXBUFFER_2048; |
1661 | /* grow the amount we can receive on large page machines */ | |
1662 | if (bufsz < (PAGE_SIZE / 2)) | |
1663 | bufsz = (PAGE_SIZE / 2); | |
1664 | /* cap the bufsz at our largest descriptor size */ | |
1665 | bufsz = min((u16)IXGBE_MAX_RXBUFFER, bufsz); | |
1666 | ||
1667 | srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
cc41ac7c JB |
1668 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
1669 | srrctl |= ((IXGBE_RX_HDR_SIZE << | |
b4617240 PW |
1670 | IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
1671 | IXGBE_SRRCTL_BSIZEHDR_MASK); | |
cc41ac7c JB |
1672 | } else { |
1673 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; | |
1674 | ||
1675 | if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE) | |
1676 | srrctl |= IXGBE_RXBUFFER_2048 >> | |
1677 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1678 | else | |
1679 | srrctl |= rx_ring->rx_buf_len >> | |
1680 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1681 | } | |
e8e26350 | 1682 | |
cc41ac7c JB |
1683 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl); |
1684 | } | |
9a799d71 | 1685 | |
9a799d71 | 1686 | /** |
3a581073 | 1687 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset |
9a799d71 AK |
1688 | * @adapter: board private structure |
1689 | * | |
1690 | * Configure the Rx unit of the MAC after a reset. | |
1691 | **/ | |
1692 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
1693 | { | |
1694 | u64 rdba; | |
1695 | struct ixgbe_hw *hw = &adapter->hw; | |
1696 | struct net_device *netdev = adapter->netdev; | |
1697 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
021230d4 | 1698 | int i, j; |
9a799d71 | 1699 | u32 rdlen, rxctrl, rxcsum; |
7c6e0a43 JB |
1700 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, |
1701 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, | |
1702 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
9a799d71 | 1703 | u32 fctrl, hlreg0; |
cc41ac7c JB |
1704 | u32 reta = 0, mrqc; |
1705 | u32 rdrxctl; | |
7c6e0a43 | 1706 | int rx_buf_len; |
9a799d71 AK |
1707 | |
1708 | /* Decide whether to use packet split mode or not */ | |
762f4c57 | 1709 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; |
9a799d71 AK |
1710 | |
1711 | /* Set the RX buffer length according to the mode */ | |
1712 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 1713 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
e8e26350 PW |
1714 | if (hw->mac.type == ixgbe_mac_82599EB) { |
1715 | /* PSRTYPE must be initialized in 82599 */ | |
1716 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
1717 | IXGBE_PSRTYPE_UDPHDR | | |
1718 | IXGBE_PSRTYPE_IPV4HDR | | |
1719 | IXGBE_PSRTYPE_IPV6HDR; | |
1720 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype); | |
1721 | } | |
9a799d71 AK |
1722 | } else { |
1723 | if (netdev->mtu <= ETH_DATA_LEN) | |
7c6e0a43 | 1724 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 1725 | else |
7c6e0a43 | 1726 | rx_buf_len = ALIGN(max_frame, 1024); |
9a799d71 AK |
1727 | } |
1728 | ||
1729 | fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); | |
1730 | fctrl |= IXGBE_FCTRL_BAM; | |
021230d4 | 1731 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ |
e8e26350 | 1732 | fctrl |= IXGBE_FCTRL_PMCF; |
9a799d71 AK |
1733 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl); |
1734 | ||
1735 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
1736 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
1737 | hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; | |
1738 | else | |
1739 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
1740 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
1741 | ||
9a799d71 AK |
1742 | rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc); |
1743 | /* disable receives while setting up the descriptors */ | |
1744 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
1745 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
1746 | ||
1747 | /* Setup the HW Rx Head and Tail Descriptor Pointers and | |
1748 | * the Base and Length of the Rx Descriptor Ring */ | |
1749 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1750 | rdba = adapter->rx_ring[i].dma; | |
7c6e0a43 JB |
1751 | j = adapter->rx_ring[i].reg_idx; |
1752 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK)); | |
1753 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); | |
1754 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen); | |
1755 | IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); | |
1756 | IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); | |
1757 | adapter->rx_ring[i].head = IXGBE_RDH(j); | |
1758 | adapter->rx_ring[i].tail = IXGBE_RDT(j); | |
1759 | adapter->rx_ring[i].rx_buf_len = rx_buf_len; | |
cc41ac7c JB |
1760 | |
1761 | ixgbe_configure_srrctl(adapter, j); | |
9a799d71 AK |
1762 | } |
1763 | ||
e8e26350 PW |
1764 | if (hw->mac.type == ixgbe_mac_82598EB) { |
1765 | /* | |
1766 | * For VMDq support of different descriptor types or | |
1767 | * buffer sizes through the use of multiple SRRCTL | |
1768 | * registers, RDRXCTL.MVMEN must be set to 1 | |
1769 | * | |
1770 | * also, the manual doesn't mention it clearly but DCA hints | |
1771 | * will only use queue 0's tags unless this bit is set. Side | |
1772 | * effects of setting this bit are only that SRRCTL must be | |
1773 | * fully programmed [0..15] | |
1774 | */ | |
1775 | if (adapter->flags & | |
1776 | (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED)) { | |
1777 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
1778 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
1779 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
1780 | } | |
2f90b865 | 1781 | } |
177db6ff | 1782 | |
e8e26350 PW |
1783 | /* Program MRQC for the distribution of queues */ |
1784 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
1785 | int mask = adapter->flags & ( | |
1786 | IXGBE_FLAG_RSS_ENABLED | |
1787 | | IXGBE_FLAG_DCB_ENABLED | |
1788 | ); | |
1789 | ||
1790 | switch (mask) { | |
1791 | case (IXGBE_FLAG_RSS_ENABLED): | |
1792 | mrqc = IXGBE_MRQC_RSSEN; | |
1793 | break; | |
1794 | case (IXGBE_FLAG_DCB_ENABLED): | |
1795 | mrqc = IXGBE_MRQC_RT8TCEN; | |
1796 | break; | |
1797 | default: | |
1798 | break; | |
1799 | } | |
1800 | } | |
021230d4 | 1801 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
9a799d71 | 1802 | /* Fill out redirection table */ |
021230d4 AV |
1803 | for (i = 0, j = 0; i < 128; i++, j++) { |
1804 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
1805 | j = 0; | |
1806 | /* reta = 4-byte sliding window of | |
1807 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
1808 | reta = (reta << 8) | (j * 0x11); | |
1809 | if ((i & 3) == 3) | |
1810 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
9a799d71 AK |
1811 | } |
1812 | ||
1813 | /* Fill out hash function seeds */ | |
1814 | for (i = 0; i < 10; i++) | |
7c6e0a43 | 1815 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); |
9a799d71 AK |
1816 | |
1817 | mrqc = IXGBE_MRQC_RSSEN | |
1818 | /* Perform hash on these packet types */ | |
7c6e0a43 JB |
1819 | | IXGBE_MRQC_RSS_FIELD_IPV4 |
1820 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
1821 | | IXGBE_MRQC_RSS_FIELD_IPV4_UDP | |
7c6e0a43 JB |
1822 | | IXGBE_MRQC_RSS_FIELD_IPV6 |
1823 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP | |
e8e26350 | 1824 | | IXGBE_MRQC_RSS_FIELD_IPV6_UDP; |
9a799d71 | 1825 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
021230d4 | 1826 | } |
9a799d71 | 1827 | |
021230d4 AV |
1828 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); |
1829 | ||
1830 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED || | |
1831 | adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) { | |
1832 | /* Disable indicating checksum in descriptor, enables | |
1833 | * RSS hash */ | |
9a799d71 | 1834 | rxcsum |= IXGBE_RXCSUM_PCSD; |
9a799d71 | 1835 | } |
021230d4 AV |
1836 | if (!(rxcsum & IXGBE_RXCSUM_PCSD)) { |
1837 | /* Enable IPv4 payload checksum for UDP fragments | |
1838 | * if PCSD is not set */ | |
1839 | rxcsum |= IXGBE_RXCSUM_IPPCSE; | |
1840 | } | |
1841 | ||
1842 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
e8e26350 PW |
1843 | |
1844 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
1845 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
1846 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
1847 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
1848 | } | |
9a799d71 AK |
1849 | } |
1850 | ||
068c89b0 DS |
1851 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
1852 | { | |
1853 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1854 | struct ixgbe_hw *hw = &adapter->hw; | |
1855 | ||
1856 | /* add VID to filter table */ | |
1857 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true); | |
1858 | } | |
1859 | ||
1860 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
1861 | { | |
1862 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1863 | struct ixgbe_hw *hw = &adapter->hw; | |
1864 | ||
1865 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1866 | ixgbe_irq_disable(adapter); | |
1867 | ||
1868 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
1869 | ||
1870 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1871 | ixgbe_irq_enable(adapter); | |
1872 | ||
1873 | /* remove VID from filter table */ | |
1874 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false); | |
1875 | } | |
1876 | ||
9a799d71 | 1877 | static void ixgbe_vlan_rx_register(struct net_device *netdev, |
b4617240 | 1878 | struct vlan_group *grp) |
9a799d71 AK |
1879 | { |
1880 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1881 | u32 ctrl; | |
e8e26350 | 1882 | int i, j; |
9a799d71 | 1883 | |
d4f80882 AV |
1884 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1885 | ixgbe_irq_disable(adapter); | |
9a799d71 AK |
1886 | adapter->vlgrp = grp; |
1887 | ||
2f90b865 AD |
1888 | /* |
1889 | * For a DCB driver, always enable VLAN tag stripping so we can | |
1890 | * still receive traffic from a DCB-enabled host even if we're | |
1891 | * not in DCB mode. | |
1892 | */ | |
1893 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
1894 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
1895 | ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
1896 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
1897 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
1898 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
1899 | ctrl |= IXGBE_VLNCTRL_VFE; | |
9a799d71 AK |
1900 | /* enable VLAN tag insert/strip */ |
1901 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
9a799d71 AK |
1902 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; |
1903 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
e8e26350 PW |
1904 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1905 | j = adapter->rx_ring[i].reg_idx; | |
1906 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j)); | |
1907 | ctrl |= IXGBE_RXDCTL_VME; | |
1908 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl); | |
1909 | } | |
9a799d71 | 1910 | } |
e8e26350 | 1911 | ixgbe_vlan_rx_add_vid(netdev, 0); |
9a799d71 | 1912 | |
d4f80882 AV |
1913 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1914 | ixgbe_irq_enable(adapter); | |
9a799d71 AK |
1915 | } |
1916 | ||
9a799d71 AK |
1917 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
1918 | { | |
1919 | ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
1920 | ||
1921 | if (adapter->vlgrp) { | |
1922 | u16 vid; | |
1923 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
1924 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
1925 | continue; | |
1926 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
1927 | } | |
1928 | } | |
1929 | } | |
1930 | ||
2c5645cf CL |
1931 | static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq) |
1932 | { | |
1933 | struct dev_mc_list *mc_ptr; | |
1934 | u8 *addr = *mc_addr_ptr; | |
1935 | *vmdq = 0; | |
1936 | ||
1937 | mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]); | |
1938 | if (mc_ptr->next) | |
1939 | *mc_addr_ptr = mc_ptr->next->dmi_addr; | |
1940 | else | |
1941 | *mc_addr_ptr = NULL; | |
1942 | ||
1943 | return addr; | |
1944 | } | |
1945 | ||
9a799d71 | 1946 | /** |
2c5645cf | 1947 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
1948 | * @netdev: network interface device structure |
1949 | * | |
2c5645cf CL |
1950 | * The set_rx_method entry point is called whenever the unicast/multicast |
1951 | * address list or the network interface flags are updated. This routine is | |
1952 | * responsible for configuring the hardware for proper unicast, multicast and | |
1953 | * promiscuous mode. | |
9a799d71 | 1954 | **/ |
2c5645cf | 1955 | static void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
1956 | { |
1957 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1958 | struct ixgbe_hw *hw = &adapter->hw; | |
3d01625a | 1959 | u32 fctrl, vlnctrl; |
2c5645cf CL |
1960 | u8 *addr_list = NULL; |
1961 | int addr_count = 0; | |
9a799d71 AK |
1962 | |
1963 | /* Check for Promiscuous and All Multicast modes */ | |
1964 | ||
1965 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3d01625a | 1966 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
9a799d71 AK |
1967 | |
1968 | if (netdev->flags & IFF_PROMISC) { | |
2c5645cf | 1969 | hw->addr_ctrl.user_set_promisc = 1; |
9a799d71 | 1970 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
3d01625a | 1971 | vlnctrl &= ~IXGBE_VLNCTRL_VFE; |
9a799d71 | 1972 | } else { |
746b9f02 PM |
1973 | if (netdev->flags & IFF_ALLMULTI) { |
1974 | fctrl |= IXGBE_FCTRL_MPE; | |
1975 | fctrl &= ~IXGBE_FCTRL_UPE; | |
1976 | } else { | |
1977 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
1978 | } | |
3d01625a | 1979 | vlnctrl |= IXGBE_VLNCTRL_VFE; |
2c5645cf | 1980 | hw->addr_ctrl.user_set_promisc = 0; |
9a799d71 AK |
1981 | } |
1982 | ||
1983 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3d01625a | 1984 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
9a799d71 | 1985 | |
2c5645cf CL |
1986 | /* reprogram secondary unicast list */ |
1987 | addr_count = netdev->uc_count; | |
1988 | if (addr_count) | |
1989 | addr_list = netdev->uc_list->dmi_addr; | |
c44ade9e JB |
1990 | hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count, |
1991 | ixgbe_addr_list_itr); | |
9a799d71 | 1992 | |
2c5645cf CL |
1993 | /* reprogram multicast list */ |
1994 | addr_count = netdev->mc_count; | |
1995 | if (addr_count) | |
1996 | addr_list = netdev->mc_list->dmi_addr; | |
c44ade9e JB |
1997 | hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count, |
1998 | ixgbe_addr_list_itr); | |
9a799d71 AK |
1999 | } |
2000 | ||
021230d4 AV |
2001 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
2002 | { | |
2003 | int q_idx; | |
2004 | struct ixgbe_q_vector *q_vector; | |
2005 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2006 | ||
2007 | /* legacy and MSI only use one vector */ | |
2008 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2009 | q_vectors = 1; | |
2010 | ||
2011 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 2012 | struct napi_struct *napi; |
021230d4 AV |
2013 | q_vector = &adapter->q_vector[q_idx]; |
2014 | if (!q_vector->rxr_count) | |
2015 | continue; | |
f0848276 JB |
2016 | napi = &q_vector->napi; |
2017 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) && | |
2018 | (q_vector->rxr_count > 1)) | |
2019 | napi->poll = &ixgbe_clean_rxonly_many; | |
2020 | ||
2021 | napi_enable(napi); | |
021230d4 AV |
2022 | } |
2023 | } | |
2024 | ||
2025 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
2026 | { | |
2027 | int q_idx; | |
2028 | struct ixgbe_q_vector *q_vector; | |
2029 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2030 | ||
2031 | /* legacy and MSI only use one vector */ | |
2032 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2033 | q_vectors = 1; | |
2034 | ||
2035 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
2036 | q_vector = &adapter->q_vector[q_idx]; | |
2037 | if (!q_vector->rxr_count) | |
2038 | continue; | |
2039 | napi_disable(&q_vector->napi); | |
2040 | } | |
2041 | } | |
2042 | ||
7a6b6f51 | 2043 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2044 | /* |
2045 | * ixgbe_configure_dcb - Configure DCB hardware | |
2046 | * @adapter: ixgbe adapter struct | |
2047 | * | |
2048 | * This is called by the driver on open to configure the DCB hardware. | |
2049 | * This is also called by the gennetlink interface when reconfiguring | |
2050 | * the DCB state. | |
2051 | */ | |
2052 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
2053 | { | |
2054 | struct ixgbe_hw *hw = &adapter->hw; | |
2055 | u32 txdctl, vlnctrl; | |
2056 | int i, j; | |
2057 | ||
2058 | ixgbe_dcb_check_config(&adapter->dcb_cfg); | |
2059 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG); | |
2060 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG); | |
2061 | ||
2062 | /* reconfigure the hardware */ | |
2063 | ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg); | |
2064 | ||
2065 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2066 | j = adapter->tx_ring[i].reg_idx; | |
2067 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2068 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
2069 | txdctl |= 32; | |
2070 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); | |
2071 | } | |
2072 | /* Enable VLAN tag insert/strip */ | |
2073 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
2074 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2075 | vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2076 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2077 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2078 | } else if (hw->mac.type == ixgbe_mac_82599EB) { | |
2079 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
2080 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2081 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2082 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2083 | j = adapter->rx_ring[i].reg_idx; | |
2084 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2085 | vlnctrl |= IXGBE_RXDCTL_VME; | |
2086 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
2087 | } | |
2088 | } | |
2f90b865 AD |
2089 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
2090 | } | |
2091 | ||
2092 | #endif | |
9a799d71 AK |
2093 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
2094 | { | |
2095 | struct net_device *netdev = adapter->netdev; | |
2096 | int i; | |
2097 | ||
2c5645cf | 2098 | ixgbe_set_rx_mode(netdev); |
9a799d71 AK |
2099 | |
2100 | ixgbe_restore_vlan(adapter); | |
7a6b6f51 | 2101 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2102 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
2103 | netif_set_gso_max_size(netdev, 32768); | |
2104 | ixgbe_configure_dcb(adapter); | |
2105 | } else { | |
2106 | netif_set_gso_max_size(netdev, 65536); | |
2107 | } | |
2108 | #else | |
2109 | netif_set_gso_max_size(netdev, 65536); | |
2110 | #endif | |
9a799d71 AK |
2111 | |
2112 | ixgbe_configure_tx(adapter); | |
2113 | ixgbe_configure_rx(adapter); | |
2114 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2115 | ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i], | |
b4617240 | 2116 | (adapter->rx_ring[i].count - 1)); |
9a799d71 AK |
2117 | } |
2118 | ||
e8e26350 PW |
2119 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
2120 | { | |
2121 | switch (hw->phy.type) { | |
2122 | case ixgbe_phy_sfp_avago: | |
2123 | case ixgbe_phy_sfp_ftl: | |
2124 | case ixgbe_phy_sfp_intel: | |
2125 | case ixgbe_phy_sfp_unknown: | |
2126 | case ixgbe_phy_tw_tyco: | |
2127 | case ixgbe_phy_tw_unknown: | |
2128 | return true; | |
2129 | default: | |
2130 | return false; | |
2131 | } | |
2132 | } | |
2133 | ||
0ecc061d | 2134 | /** |
e8e26350 PW |
2135 | * ixgbe_sfp_link_config - set up SFP+ link |
2136 | * @adapter: pointer to private adapter struct | |
2137 | **/ | |
2138 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
2139 | { | |
2140 | struct ixgbe_hw *hw = &adapter->hw; | |
2141 | ||
2142 | if (hw->phy.multispeed_fiber) { | |
2143 | /* | |
2144 | * In multispeed fiber setups, the device may not have | |
2145 | * had a physical connection when the driver loaded. | |
2146 | * If that's the case, the initial link configuration | |
2147 | * couldn't get the MAC into 10G or 1G mode, so we'll | |
2148 | * never have a link status change interrupt fire. | |
2149 | * We need to try and force an autonegotiation | |
2150 | * session, then bring up link. | |
2151 | */ | |
2152 | hw->mac.ops.setup_sfp(hw); | |
2153 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) | |
2154 | schedule_work(&adapter->multispeed_fiber_task); | |
2155 | } else { | |
2156 | /* | |
2157 | * Direct Attach Cu and non-multispeed fiber modules | |
2158 | * still need to be configured properly prior to | |
2159 | * attempting link. | |
2160 | */ | |
2161 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK)) | |
2162 | schedule_work(&adapter->sfp_config_module_task); | |
2163 | } | |
2164 | } | |
2165 | ||
2166 | /** | |
2167 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
2168 | * @hw: pointer to private hardware struct |
2169 | * | |
2170 | * Returns 0 on success, negative on failure | |
2171 | **/ | |
e8e26350 | 2172 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
2173 | { |
2174 | u32 autoneg; | |
2175 | bool link_up = false; | |
2176 | u32 ret = IXGBE_ERR_LINK_SETUP; | |
2177 | ||
2178 | if (hw->mac.ops.check_link) | |
2179 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
2180 | ||
2181 | if (ret) | |
2182 | goto link_cfg_out; | |
2183 | ||
2184 | if (hw->mac.ops.get_link_capabilities) | |
2185 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, | |
2186 | &hw->mac.autoneg); | |
2187 | if (ret) | |
2188 | goto link_cfg_out; | |
2189 | ||
2190 | if (hw->mac.ops.setup_link_speed) | |
2191 | ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up); | |
0ecc061d PWJ |
2192 | link_cfg_out: |
2193 | return ret; | |
2194 | } | |
2195 | ||
e8e26350 PW |
2196 | #define IXGBE_MAX_RX_DESC_POLL 10 |
2197 | static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2198 | int rxr) | |
2199 | { | |
2200 | int j = adapter->rx_ring[rxr].reg_idx; | |
2201 | int k; | |
2202 | ||
2203 | for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) { | |
2204 | if (IXGBE_READ_REG(&adapter->hw, | |
2205 | IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE) | |
2206 | break; | |
2207 | else | |
2208 | msleep(1); | |
2209 | } | |
2210 | if (k >= IXGBE_MAX_RX_DESC_POLL) { | |
2211 | DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d " | |
2212 | "not set within the polling period\n", rxr); | |
2213 | } | |
2214 | ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr], | |
2215 | (adapter->rx_ring[rxr].count - 1)); | |
2216 | } | |
2217 | ||
9a799d71 AK |
2218 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) |
2219 | { | |
2220 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 2221 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 2222 | int i, j = 0; |
e8e26350 | 2223 | int num_rx_rings = adapter->num_rx_queues; |
0ecc061d | 2224 | int err; |
9a799d71 | 2225 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 | 2226 | u32 txdctl, rxdctl, mhadd; |
e8e26350 | 2227 | u32 dmatxctl; |
021230d4 | 2228 | u32 gpie; |
9a799d71 | 2229 | |
5eba3699 AV |
2230 | ixgbe_get_hw_control(adapter); |
2231 | ||
021230d4 AV |
2232 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) || |
2233 | (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) { | |
9a799d71 AK |
2234 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2235 | gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME | | |
b4617240 | 2236 | IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD); |
9a799d71 AK |
2237 | } else { |
2238 | /* MSI only */ | |
021230d4 | 2239 | gpie = 0; |
9a799d71 | 2240 | } |
021230d4 AV |
2241 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
2242 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
2243 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
9a799d71 AK |
2244 | } |
2245 | ||
021230d4 AV |
2246 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
2247 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, | |
2248 | * specifically only auto mask tx and rx interrupts */ | |
2249 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
2250 | } | |
9a799d71 | 2251 | |
0befdb3e JB |
2252 | /* Enable fan failure interrupt if media type is copper */ |
2253 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2254 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2255 | gpie |= IXGBE_SDP1_GPIEN; | |
2256 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2257 | } | |
2258 | ||
e8e26350 PW |
2259 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2260 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2261 | gpie |= IXGBE_SDP1_GPIEN; | |
2262 | gpie |= IXGBE_SDP2_GPIEN; | |
2263 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2264 | } | |
2265 | ||
021230d4 | 2266 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
9a799d71 AK |
2267 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { |
2268 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
2269 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
2270 | ||
2271 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
2272 | } | |
2273 | ||
2274 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
021230d4 AV |
2275 | j = adapter->tx_ring[i].reg_idx; |
2276 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
e01c31a5 JB |
2277 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ |
2278 | txdctl |= (8 << 16); | |
e8e26350 PW |
2279 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
2280 | } | |
2281 | ||
2282 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2283 | /* DMATXCTL.EN must be set after all Tx queue config is done */ | |
2284 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2285 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2286 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2287 | } | |
2288 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2289 | j = adapter->tx_ring[i].reg_idx; | |
2290 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
9a799d71 | 2291 | txdctl |= IXGBE_TXDCTL_ENABLE; |
021230d4 | 2292 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
9a799d71 AK |
2293 | } |
2294 | ||
e8e26350 | 2295 | for (i = 0; i < num_rx_rings; i++) { |
021230d4 AV |
2296 | j = adapter->rx_ring[i].reg_idx; |
2297 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2298 | /* enable PTHRESH=32 descriptors (half the internal cache) | |
2299 | * and HTHRESH=0 descriptors (to minimize latency on fetch), | |
2300 | * this also removes a pesky rx_no_buffer_count increment */ | |
2301 | rxdctl |= 0x0020; | |
9a799d71 | 2302 | rxdctl |= IXGBE_RXDCTL_ENABLE; |
021230d4 | 2303 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl); |
e8e26350 PW |
2304 | if (hw->mac.type == ixgbe_mac_82599EB) |
2305 | ixgbe_rx_desc_queue_enable(adapter, i); | |
9a799d71 AK |
2306 | } |
2307 | /* enable all receives */ | |
2308 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
e8e26350 PW |
2309 | if (hw->mac.type == ixgbe_mac_82598EB) |
2310 | rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN); | |
2311 | else | |
2312 | rxdctl |= IXGBE_RXCTRL_RXEN; | |
2313 | hw->mac.ops.enable_rx_dma(hw, rxdctl); | |
9a799d71 AK |
2314 | |
2315 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
2316 | ixgbe_configure_msix(adapter); | |
2317 | else | |
2318 | ixgbe_configure_msi_and_legacy(adapter); | |
2319 | ||
7adf1525 PWJ |
2320 | ixgbe_napi_add_all(adapter); |
2321 | ||
9a799d71 | 2322 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
2323 | ixgbe_napi_enable_all(adapter); |
2324 | ||
2325 | /* clear any pending interrupts, may auto mask */ | |
2326 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
2327 | ||
9a799d71 AK |
2328 | ixgbe_irq_enable(adapter); |
2329 | ||
e8e26350 PW |
2330 | /* |
2331 | * For hot-pluggable SFP+ devices, a new SFP+ module may have | |
2332 | * arrived before interrupts were enabled. We need to kick off | |
2333 | * the SFP+ module setup first, then try to bring up link. | |
2334 | * If we're not hot-pluggable SFP+, we just need to configure link | |
2335 | * and bring it up. | |
2336 | */ | |
2337 | err = hw->phy.ops.identify(hw); | |
2338 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
2339 | DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err); | |
2340 | ixgbe_down(adapter); | |
2341 | return err; | |
2342 | } | |
2343 | ||
2344 | if (ixgbe_is_sfp(hw)) { | |
2345 | ixgbe_sfp_link_config(adapter); | |
2346 | } else { | |
2347 | err = ixgbe_non_sfp_link_config(hw); | |
2348 | if (err) | |
2349 | DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err); | |
2350 | } | |
0ecc061d | 2351 | |
1da100bb PWJ |
2352 | /* enable transmits */ |
2353 | netif_tx_start_all_queues(netdev); | |
2354 | ||
9a799d71 AK |
2355 | /* bring the link up in the watchdog, this could race with our first |
2356 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
2357 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
2358 | adapter->link_check_timeout = jiffies; | |
9a799d71 AK |
2359 | mod_timer(&adapter->watchdog_timer, jiffies); |
2360 | return 0; | |
2361 | } | |
2362 | ||
d4f80882 AV |
2363 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
2364 | { | |
2365 | WARN_ON(in_interrupt()); | |
2366 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
2367 | msleep(1); | |
2368 | ixgbe_down(adapter); | |
2369 | ixgbe_up(adapter); | |
2370 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
2371 | } | |
2372 | ||
9a799d71 AK |
2373 | int ixgbe_up(struct ixgbe_adapter *adapter) |
2374 | { | |
2375 | /* hardware has been reset, we need to reload some things */ | |
2376 | ixgbe_configure(adapter); | |
2377 | ||
2378 | return ixgbe_up_complete(adapter); | |
2379 | } | |
2380 | ||
2381 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
2382 | { | |
c44ade9e JB |
2383 | struct ixgbe_hw *hw = &adapter->hw; |
2384 | if (hw->mac.ops.init_hw(hw)) | |
2385 | dev_err(&adapter->pdev->dev, "Hardware Error\n"); | |
9a799d71 AK |
2386 | |
2387 | /* reprogram the RAR[0] in case user changed it. */ | |
c44ade9e | 2388 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
2389 | |
2390 | } | |
2391 | ||
9a799d71 AK |
2392 | /** |
2393 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
2394 | * @adapter: board private structure | |
2395 | * @rx_ring: ring to free buffers from | |
2396 | **/ | |
2397 | static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2398 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
2399 | { |
2400 | struct pci_dev *pdev = adapter->pdev; | |
2401 | unsigned long size; | |
2402 | unsigned int i; | |
2403 | ||
2404 | /* Free all the Rx ring sk_buffs */ | |
2405 | ||
2406 | for (i = 0; i < rx_ring->count; i++) { | |
2407 | struct ixgbe_rx_buffer *rx_buffer_info; | |
2408 | ||
2409 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
2410 | if (rx_buffer_info->dma) { | |
2411 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
b4617240 PW |
2412 | rx_ring->rx_buf_len, |
2413 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
2414 | rx_buffer_info->dma = 0; |
2415 | } | |
2416 | if (rx_buffer_info->skb) { | |
2417 | dev_kfree_skb(rx_buffer_info->skb); | |
2418 | rx_buffer_info->skb = NULL; | |
2419 | } | |
2420 | if (!rx_buffer_info->page) | |
2421 | continue; | |
762f4c57 JB |
2422 | pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2, |
2423 | PCI_DMA_FROMDEVICE); | |
9a799d71 | 2424 | rx_buffer_info->page_dma = 0; |
9a799d71 AK |
2425 | put_page(rx_buffer_info->page); |
2426 | rx_buffer_info->page = NULL; | |
762f4c57 | 2427 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
2428 | } |
2429 | ||
2430 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
2431 | memset(rx_ring->rx_buffer_info, 0, size); | |
2432 | ||
2433 | /* Zero out the descriptor ring */ | |
2434 | memset(rx_ring->desc, 0, rx_ring->size); | |
2435 | ||
2436 | rx_ring->next_to_clean = 0; | |
2437 | rx_ring->next_to_use = 0; | |
2438 | ||
2439 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
2440 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
2441 | } | |
2442 | ||
2443 | /** | |
2444 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
2445 | * @adapter: board private structure | |
2446 | * @tx_ring: ring to be cleaned | |
2447 | **/ | |
2448 | static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2449 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
2450 | { |
2451 | struct ixgbe_tx_buffer *tx_buffer_info; | |
2452 | unsigned long size; | |
2453 | unsigned int i; | |
2454 | ||
2455 | /* Free all the Tx ring sk_buffs */ | |
2456 | ||
2457 | for (i = 0; i < tx_ring->count; i++) { | |
2458 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
2459 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
2460 | } | |
2461 | ||
2462 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
2463 | memset(tx_ring->tx_buffer_info, 0, size); | |
2464 | ||
2465 | /* Zero out the descriptor ring */ | |
2466 | memset(tx_ring->desc, 0, tx_ring->size); | |
2467 | ||
2468 | tx_ring->next_to_use = 0; | |
2469 | tx_ring->next_to_clean = 0; | |
2470 | ||
2471 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
2472 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
2473 | } | |
2474 | ||
2475 | /** | |
021230d4 | 2476 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
2477 | * @adapter: board private structure |
2478 | **/ | |
021230d4 | 2479 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2480 | { |
2481 | int i; | |
2482 | ||
021230d4 AV |
2483 | for (i = 0; i < adapter->num_rx_queues; i++) |
2484 | ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
2485 | } |
2486 | ||
2487 | /** | |
021230d4 | 2488 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
2489 | * @adapter: board private structure |
2490 | **/ | |
021230d4 | 2491 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2492 | { |
2493 | int i; | |
2494 | ||
021230d4 AV |
2495 | for (i = 0; i < adapter->num_tx_queues; i++) |
2496 | ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
2497 | } |
2498 | ||
2499 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
2500 | { | |
2501 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 2502 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 2503 | u32 rxctrl; |
7f821875 JB |
2504 | u32 txdctl; |
2505 | int i, j; | |
9a799d71 AK |
2506 | |
2507 | /* signal that we are down to the interrupt handler */ | |
2508 | set_bit(__IXGBE_DOWN, &adapter->state); | |
2509 | ||
2510 | /* disable receives */ | |
7f821875 JB |
2511 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
2512 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 AK |
2513 | |
2514 | netif_tx_disable(netdev); | |
2515 | ||
7f821875 | 2516 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
2517 | msleep(10); |
2518 | ||
7f821875 JB |
2519 | netif_tx_stop_all_queues(netdev); |
2520 | ||
9a799d71 AK |
2521 | ixgbe_irq_disable(adapter); |
2522 | ||
021230d4 | 2523 | ixgbe_napi_disable_all(adapter); |
7f821875 | 2524 | |
9a799d71 | 2525 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 2526 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 2527 | |
7f821875 JB |
2528 | /* disable transmits in the hardware now that interrupts are off */ |
2529 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2530 | j = adapter->tx_ring[i].reg_idx; | |
2531 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2532 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), | |
2533 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); | |
2534 | } | |
2535 | ||
9a799d71 | 2536 | netif_carrier_off(netdev); |
9a799d71 | 2537 | |
5dd2d332 | 2538 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 JB |
2539 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2540 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
2541 | dca_remove_requester(&adapter->pdev->dev); | |
2542 | } | |
2543 | ||
2544 | #endif | |
6f4a0e45 PL |
2545 | if (!pci_channel_offline(adapter->pdev)) |
2546 | ixgbe_reset(adapter); | |
9a799d71 AK |
2547 | ixgbe_clean_all_tx_rings(adapter); |
2548 | ixgbe_clean_all_rx_rings(adapter); | |
2549 | ||
5dd2d332 | 2550 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 JB |
2551 | /* since we reset the hardware DCA settings were cleared */ |
2552 | if (dca_add_requester(&adapter->pdev->dev) == 0) { | |
2553 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; | |
2554 | /* always use CB2 mode, difference is masked | |
2555 | * in the CB driver */ | |
b4617240 | 2556 | IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2); |
96b0e0f6 JB |
2557 | ixgbe_setup_dca(adapter); |
2558 | } | |
2559 | #endif | |
9a799d71 AK |
2560 | } |
2561 | ||
9a799d71 | 2562 | /** |
021230d4 AV |
2563 | * ixgbe_poll - NAPI Rx polling callback |
2564 | * @napi: structure for representing this polling device | |
2565 | * @budget: how many packets driver is allowed to clean | |
2566 | * | |
2567 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 2568 | **/ |
021230d4 | 2569 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 2570 | { |
021230d4 | 2571 | struct ixgbe_q_vector *q_vector = container_of(napi, |
b4617240 | 2572 | struct ixgbe_q_vector, napi); |
021230d4 | 2573 | struct ixgbe_adapter *adapter = q_vector->adapter; |
74ce8dd2 | 2574 | int tx_cleaned, work_done = 0; |
9a799d71 | 2575 | |
5dd2d332 | 2576 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
2577 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2578 | ixgbe_update_tx_dca(adapter, adapter->tx_ring); | |
2579 | ixgbe_update_rx_dca(adapter, adapter->rx_ring); | |
2580 | } | |
2581 | #endif | |
2582 | ||
d2c7ddd6 | 2583 | tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring); |
78b6f4ce | 2584 | ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget); |
9a799d71 | 2585 | |
d2c7ddd6 DM |
2586 | if (tx_cleaned) |
2587 | work_done = budget; | |
2588 | ||
53e52c72 DM |
2589 | /* If budget not fully consumed, exit the polling mode */ |
2590 | if (work_done < budget) { | |
288379f0 | 2591 | napi_complete(napi); |
30efa5a3 | 2592 | if (adapter->itr_setting & 3) |
f494e8fa | 2593 | ixgbe_set_itr(adapter); |
d4f80882 AV |
2594 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2595 | ixgbe_irq_enable(adapter); | |
9a799d71 | 2596 | } |
9a799d71 AK |
2597 | return work_done; |
2598 | } | |
2599 | ||
2600 | /** | |
2601 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
2602 | * @netdev: network interface device structure | |
2603 | **/ | |
2604 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
2605 | { | |
2606 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2607 | ||
2608 | /* Do the reset outside of interrupt context */ | |
2609 | schedule_work(&adapter->reset_task); | |
2610 | } | |
2611 | ||
2612 | static void ixgbe_reset_task(struct work_struct *work) | |
2613 | { | |
2614 | struct ixgbe_adapter *adapter; | |
2615 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
2616 | ||
2f90b865 AD |
2617 | /* If we're already down or resetting, just bail */ |
2618 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
2619 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
2620 | return; | |
2621 | ||
9a799d71 AK |
2622 | adapter->tx_timeout_count++; |
2623 | ||
d4f80882 | 2624 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
2625 | } |
2626 | ||
bc97114d PWJ |
2627 | #ifdef CONFIG_IXGBE_DCB |
2628 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
b9804972 | 2629 | { |
bc97114d | 2630 | bool ret = false; |
b9804972 | 2631 | |
bc97114d PWJ |
2632 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
2633 | adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3; | |
2634 | adapter->num_rx_queues = | |
2635 | adapter->ring_feature[RING_F_DCB].indices; | |
2636 | adapter->num_tx_queues = | |
2637 | adapter->ring_feature[RING_F_DCB].indices; | |
2638 | ret = true; | |
2639 | } else { | |
bc97114d PWJ |
2640 | ret = false; |
2641 | } | |
2f90b865 | 2642 | |
bc97114d PWJ |
2643 | return ret; |
2644 | } | |
2645 | #endif | |
2646 | ||
2647 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) | |
2648 | { | |
2649 | bool ret = false; | |
2650 | ||
2651 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
2652 | adapter->ring_feature[RING_F_RSS].mask = 0xF; | |
2653 | adapter->num_rx_queues = | |
2654 | adapter->ring_feature[RING_F_RSS].indices; | |
2655 | adapter->num_tx_queues = | |
2656 | adapter->ring_feature[RING_F_RSS].indices; | |
2657 | ret = true; | |
2658 | } else { | |
bc97114d | 2659 | ret = false; |
b9804972 JB |
2660 | } |
2661 | ||
bc97114d PWJ |
2662 | return ret; |
2663 | } | |
2664 | ||
2665 | static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) | |
2666 | { | |
2667 | /* Start with base case */ | |
2668 | adapter->num_rx_queues = 1; | |
2669 | adapter->num_tx_queues = 1; | |
2670 | ||
2671 | #ifdef CONFIG_IXGBE_DCB | |
2672 | if (ixgbe_set_dcb_queues(adapter)) | |
2673 | return; | |
2674 | ||
2675 | #endif | |
2676 | if (ixgbe_set_rss_queues(adapter)) | |
2677 | return; | |
b9804972 JB |
2678 | } |
2679 | ||
021230d4 | 2680 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 2681 | int vectors) |
021230d4 AV |
2682 | { |
2683 | int err, vector_threshold; | |
2684 | ||
2685 | /* We'll want at least 3 (vector_threshold): | |
2686 | * 1) TxQ[0] Cleanup | |
2687 | * 2) RxQ[0] Cleanup | |
2688 | * 3) Other (Link Status Change, etc.) | |
2689 | * 4) TCP Timer (optional) | |
2690 | */ | |
2691 | vector_threshold = MIN_MSIX_COUNT; | |
2692 | ||
2693 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
2694 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
2695 | * Right now, we simply care about how many we'll get; we'll | |
2696 | * set them up later while requesting irq's. | |
2697 | */ | |
2698 | while (vectors >= vector_threshold) { | |
2699 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
b4617240 | 2700 | vectors); |
021230d4 AV |
2701 | if (!err) /* Success in acquiring all requested vectors. */ |
2702 | break; | |
2703 | else if (err < 0) | |
2704 | vectors = 0; /* Nasty failure, quit now */ | |
2705 | else /* err == number of vectors we should try again with */ | |
2706 | vectors = err; | |
2707 | } | |
2708 | ||
2709 | if (vectors < vector_threshold) { | |
2710 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
2711 | * This just means we'll go with either a single MSI | |
2712 | * vector or fall back to legacy interrupts. | |
2713 | */ | |
2714 | DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n"); | |
2715 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
2716 | kfree(adapter->msix_entries); | |
2717 | adapter->msix_entries = NULL; | |
2f90b865 | 2718 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
021230d4 | 2719 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; |
b9804972 | 2720 | ixgbe_set_num_queues(adapter); |
021230d4 AV |
2721 | } else { |
2722 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
2723 | /* |
2724 | * Adjust for only the vectors we'll use, which is minimum | |
2725 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
2726 | * vectors we were allocated. | |
2727 | */ | |
2728 | adapter->num_msix_vectors = min(vectors, | |
2729 | adapter->max_msix_q_vectors + NON_Q_VECTORS); | |
021230d4 AV |
2730 | } |
2731 | } | |
2732 | ||
021230d4 | 2733 | /** |
bc97114d | 2734 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
2735 | * @adapter: board private structure to initialize |
2736 | * | |
bc97114d PWJ |
2737 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
2738 | * | |
021230d4 | 2739 | **/ |
bc97114d | 2740 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 2741 | { |
bc97114d PWJ |
2742 | int i; |
2743 | bool ret = false; | |
2744 | ||
2745 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
2746 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2747 | adapter->rx_ring[i].reg_idx = i; | |
2748 | for (i = 0; i < adapter->num_tx_queues; i++) | |
2749 | adapter->tx_ring[i].reg_idx = i; | |
2750 | ret = true; | |
2751 | } else { | |
2752 | ret = false; | |
2753 | } | |
2754 | ||
2755 | return ret; | |
2756 | } | |
2757 | ||
2758 | #ifdef CONFIG_IXGBE_DCB | |
2759 | /** | |
2760 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
2761 | * @adapter: board private structure to initialize | |
2762 | * | |
2763 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
2764 | * | |
2765 | **/ | |
2766 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
2767 | { | |
2768 | int i; | |
2769 | bool ret = false; | |
2770 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
2771 | ||
2772 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
2773 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2f90b865 AD |
2774 | /* the number of queues is assumed to be symmetric */ |
2775 | for (i = 0; i < dcb_i; i++) { | |
2776 | adapter->rx_ring[i].reg_idx = i << 3; | |
2777 | adapter->tx_ring[i].reg_idx = i << 2; | |
2778 | } | |
bc97114d | 2779 | ret = true; |
e8e26350 PW |
2780 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
2781 | for (i = 0; i < dcb_i; i++) { | |
2782 | adapter->rx_ring[i].reg_idx = i << 4; | |
2783 | adapter->tx_ring[i].reg_idx = i << 4; | |
2784 | } | |
2785 | ret = true; | |
bc97114d PWJ |
2786 | } else { |
2787 | ret = false; | |
021230d4 | 2788 | } |
bc97114d PWJ |
2789 | } else { |
2790 | ret = false; | |
021230d4 | 2791 | } |
bc97114d PWJ |
2792 | |
2793 | return ret; | |
2794 | } | |
2795 | #endif | |
2796 | ||
2797 | /** | |
2798 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
2799 | * @adapter: board private structure to initialize | |
2800 | * | |
2801 | * Once we know the feature-set enabled for the device, we'll cache | |
2802 | * the register offset the descriptor ring is assigned to. | |
2803 | * | |
2804 | * Note, the order the various feature calls is important. It must start with | |
2805 | * the "most" features enabled at the same time, then trickle down to the | |
2806 | * least amount of features turned on at once. | |
2807 | **/ | |
2808 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
2809 | { | |
2810 | /* start with default case */ | |
2811 | adapter->rx_ring[0].reg_idx = 0; | |
2812 | adapter->tx_ring[0].reg_idx = 0; | |
2813 | ||
2814 | #ifdef CONFIG_IXGBE_DCB | |
2815 | if (ixgbe_cache_ring_dcb(adapter)) | |
2816 | return; | |
2817 | ||
2818 | #endif | |
2819 | if (ixgbe_cache_ring_rss(adapter)) | |
2820 | return; | |
021230d4 AV |
2821 | } |
2822 | ||
9a799d71 AK |
2823 | /** |
2824 | * ixgbe_alloc_queues - Allocate memory for all rings | |
2825 | * @adapter: board private structure to initialize | |
2826 | * | |
2827 | * We allocate one ring per queue at run-time since we don't know the | |
a4d2f34b | 2828 | * number of queues at compile-time. |
9a799d71 | 2829 | **/ |
2f90b865 | 2830 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2831 | { |
2832 | int i; | |
2833 | ||
2834 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
b4617240 | 2835 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
9a799d71 | 2836 | if (!adapter->tx_ring) |
021230d4 | 2837 | goto err_tx_ring_allocation; |
9a799d71 AK |
2838 | |
2839 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
b4617240 | 2840 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
021230d4 AV |
2841 | if (!adapter->rx_ring) |
2842 | goto err_rx_ring_allocation; | |
9a799d71 | 2843 | |
021230d4 | 2844 | for (i = 0; i < adapter->num_tx_queues; i++) { |
b9804972 | 2845 | adapter->tx_ring[i].count = adapter->tx_ring_count; |
021230d4 AV |
2846 | adapter->tx_ring[i].queue_index = i; |
2847 | } | |
b9804972 | 2848 | |
9a799d71 | 2849 | for (i = 0; i < adapter->num_rx_queues; i++) { |
b9804972 | 2850 | adapter->rx_ring[i].count = adapter->rx_ring_count; |
021230d4 AV |
2851 | adapter->rx_ring[i].queue_index = i; |
2852 | } | |
2853 | ||
2854 | ixgbe_cache_ring_register(adapter); | |
2855 | ||
2856 | return 0; | |
2857 | ||
2858 | err_rx_ring_allocation: | |
2859 | kfree(adapter->tx_ring); | |
2860 | err_tx_ring_allocation: | |
2861 | return -ENOMEM; | |
2862 | } | |
2863 | ||
2864 | /** | |
2865 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
2866 | * @adapter: board private structure to initialize | |
2867 | * | |
2868 | * Attempt to configure the interrupts using the best available | |
2869 | * capabilities of the hardware and the kernel. | |
2870 | **/ | |
feea6a57 | 2871 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
2872 | { |
2873 | int err = 0; | |
2874 | int vector, v_budget; | |
2875 | ||
2876 | /* | |
2877 | * It's easy to be greedy for MSI-X vectors, but it really | |
2878 | * doesn't do us much good if we have a lot more vectors | |
2879 | * than CPU's. So let's be conservative and only ask for | |
2880 | * (roughly) twice the number of vectors as there are CPU's. | |
2881 | */ | |
2882 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
b4617240 | 2883 | (int)(num_online_cpus() * 2)) + NON_Q_VECTORS; |
021230d4 AV |
2884 | |
2885 | /* | |
2886 | * At the same time, hardware can only support a maximum of | |
2887 | * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq, | |
2888 | * we can easily reach upwards of 64 Rx descriptor queues and | |
2889 | * 32 Tx queues. Thus, we cap it off in those rare cases where | |
2890 | * the cpu count also exceeds our vector limit. | |
2891 | */ | |
2892 | v_budget = min(v_budget, MAX_MSIX_COUNT); | |
2893 | ||
2894 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
2895 | * mean we disable MSI-X capabilities of the adapter. */ | |
2896 | adapter->msix_entries = kcalloc(v_budget, | |
b4617240 | 2897 | sizeof(struct msix_entry), GFP_KERNEL); |
021230d4 | 2898 | if (!adapter->msix_entries) { |
2f90b865 | 2899 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
021230d4 AV |
2900 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; |
2901 | ixgbe_set_num_queues(adapter); | |
2902 | kfree(adapter->tx_ring); | |
2903 | kfree(adapter->rx_ring); | |
2904 | err = ixgbe_alloc_queues(adapter); | |
2905 | if (err) { | |
2906 | DPRINTK(PROBE, ERR, "Unable to allocate memory " | |
b4617240 | 2907 | "for queues\n"); |
021230d4 AV |
2908 | goto out; |
2909 | } | |
2910 | ||
2911 | goto try_msi; | |
2912 | } | |
2913 | ||
2914 | for (vector = 0; vector < v_budget; vector++) | |
2915 | adapter->msix_entries[vector].entry = vector; | |
2916 | ||
2917 | ixgbe_acquire_msix_vectors(adapter, v_budget); | |
2918 | ||
2919 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
2920 | goto out; | |
2921 | ||
2922 | try_msi: | |
2923 | err = pci_enable_msi(adapter->pdev); | |
2924 | if (!err) { | |
2925 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
2926 | } else { | |
2927 | DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, " | |
b4617240 | 2928 | "falling back to legacy. Error: %d\n", err); |
021230d4 AV |
2929 | /* reset err */ |
2930 | err = 0; | |
2931 | } | |
2932 | ||
2933 | out: | |
30eba97a | 2934 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ |
fd2ea0a7 | 2935 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; |
021230d4 AV |
2936 | |
2937 | return err; | |
2938 | } | |
2939 | ||
2f90b865 | 2940 | void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
2941 | { |
2942 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
2943 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
2944 | pci_disable_msix(adapter->pdev); | |
2945 | kfree(adapter->msix_entries); | |
2946 | adapter->msix_entries = NULL; | |
2947 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
2948 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
2949 | pci_disable_msi(adapter->pdev); | |
2950 | } | |
2951 | return; | |
2952 | } | |
2953 | ||
2954 | /** | |
2955 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
2956 | * @adapter: board private structure to initialize | |
2957 | * | |
2958 | * We determine which interrupt scheme to use based on... | |
2959 | * - Kernel support (MSI, MSI-X) | |
2960 | * - which can be user-defined (via MODULE_PARAM) | |
2961 | * - Hardware queue count (num_*_queues) | |
2962 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
2963 | **/ | |
2f90b865 | 2964 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
2965 | { |
2966 | int err; | |
2967 | ||
2968 | /* Number of supported queues */ | |
2969 | ixgbe_set_num_queues(adapter); | |
2970 | ||
2971 | err = ixgbe_alloc_queues(adapter); | |
2972 | if (err) { | |
2973 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); | |
2974 | goto err_alloc_queues; | |
2975 | } | |
2976 | ||
2977 | err = ixgbe_set_interrupt_capability(adapter); | |
2978 | if (err) { | |
2979 | DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n"); | |
2980 | goto err_set_interrupt; | |
9a799d71 AK |
2981 | } |
2982 | ||
021230d4 | 2983 | DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, " |
b4617240 PW |
2984 | "Tx Queue count = %u\n", |
2985 | (adapter->num_rx_queues > 1) ? "Enabled" : | |
2986 | "Disabled", adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
2987 | |
2988 | set_bit(__IXGBE_DOWN, &adapter->state); | |
2989 | ||
9a799d71 | 2990 | return 0; |
021230d4 AV |
2991 | |
2992 | err_set_interrupt: | |
2993 | kfree(adapter->tx_ring); | |
2994 | kfree(adapter->rx_ring); | |
2995 | err_alloc_queues: | |
2996 | return err; | |
9a799d71 AK |
2997 | } |
2998 | ||
c4900be0 DS |
2999 | /** |
3000 | * ixgbe_sfp_timer - worker thread to find a missing module | |
3001 | * @data: pointer to our adapter struct | |
3002 | **/ | |
3003 | static void ixgbe_sfp_timer(unsigned long data) | |
3004 | { | |
3005 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
3006 | ||
3007 | /* Do the sfp_timer outside of interrupt context due to the | |
3008 | * delays that sfp+ detection requires | |
3009 | */ | |
3010 | schedule_work(&adapter->sfp_task); | |
3011 | } | |
3012 | ||
3013 | /** | |
3014 | * ixgbe_sfp_task - worker thread to find a missing module | |
3015 | * @work: pointer to work_struct containing our data | |
3016 | **/ | |
3017 | static void ixgbe_sfp_task(struct work_struct *work) | |
3018 | { | |
3019 | struct ixgbe_adapter *adapter = container_of(work, | |
3020 | struct ixgbe_adapter, | |
3021 | sfp_task); | |
3022 | struct ixgbe_hw *hw = &adapter->hw; | |
3023 | ||
3024 | if ((hw->phy.type == ixgbe_phy_nl) && | |
3025 | (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { | |
3026 | s32 ret = hw->phy.ops.identify_sfp(hw); | |
3027 | if (ret) | |
3028 | goto reschedule; | |
3029 | ret = hw->phy.ops.reset(hw); | |
3030 | if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
3031 | DPRINTK(PROBE, ERR, "failed to initialize because an " | |
3032 | "unsupported SFP+ module type was detected.\n" | |
3033 | "Reload the driver after installing a " | |
3034 | "supported module.\n"); | |
3035 | unregister_netdev(adapter->netdev); | |
3036 | } else { | |
3037 | DPRINTK(PROBE, INFO, "detected SFP+: %d\n", | |
3038 | hw->phy.sfp_type); | |
3039 | } | |
3040 | /* don't need this routine any more */ | |
3041 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
3042 | } | |
3043 | return; | |
3044 | reschedule: | |
3045 | if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) | |
3046 | mod_timer(&adapter->sfp_timer, | |
3047 | round_jiffies(jiffies + (2 * HZ))); | |
3048 | } | |
3049 | ||
9a799d71 AK |
3050 | /** |
3051 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
3052 | * @adapter: board private structure to initialize | |
3053 | * | |
3054 | * ixgbe_sw_init initializes the Adapter private data structure. | |
3055 | * Fields are initialized based on PCI device information and | |
3056 | * OS network device settings (MTU size). | |
3057 | **/ | |
3058 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
3059 | { | |
3060 | struct ixgbe_hw *hw = &adapter->hw; | |
3061 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 3062 | unsigned int rss; |
7a6b6f51 | 3063 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3064 | int j; |
3065 | struct tc_configuration *tc; | |
3066 | #endif | |
021230d4 | 3067 | |
c44ade9e JB |
3068 | /* PCI config space info */ |
3069 | ||
3070 | hw->vendor_id = pdev->vendor; | |
3071 | hw->device_id = pdev->device; | |
3072 | hw->revision_id = pdev->revision; | |
3073 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
3074 | hw->subsystem_device_id = pdev->subsystem_device; | |
3075 | ||
021230d4 AV |
3076 | /* Set capability flags */ |
3077 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
3078 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
3079 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 3080 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
e8e26350 PW |
3081 | if (hw->mac.type == ixgbe_mac_82598EB) |
3082 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; | |
3083 | else if (hw->mac.type == ixgbe_mac_82599EB) | |
3084 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; | |
2f90b865 | 3085 | |
7a6b6f51 | 3086 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3087 | /* Configure DCB traffic classes */ |
3088 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
3089 | tc = &adapter->dcb_cfg.tc_config[j]; | |
3090 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
3091 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
3092 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
3093 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
3094 | tc->dcb_pfc = pfc_disabled; | |
3095 | } | |
3096 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
3097 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
3098 | adapter->dcb_cfg.rx_pba_cfg = pba_equal; | |
3099 | adapter->dcb_cfg.round_robin_enable = false; | |
3100 | adapter->dcb_set_bitmap = 0x00; | |
3101 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, | |
3102 | adapter->ring_feature[RING_F_DCB].indices); | |
3103 | ||
3104 | #endif | |
9a799d71 AK |
3105 | |
3106 | /* default flow control settings */ | |
0ecc061d | 3107 | hw->fc.requested_mode = ixgbe_fc_none; |
2b9ade93 JB |
3108 | hw->fc.high_water = IXGBE_DEFAULT_FCRTH; |
3109 | hw->fc.low_water = IXGBE_DEFAULT_FCRTL; | |
3110 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; | |
3111 | hw->fc.send_xon = true; | |
9a799d71 | 3112 | |
30efa5a3 JB |
3113 | /* enable itr by default in dynamic mode */ |
3114 | adapter->itr_setting = 1; | |
3115 | adapter->eitr_param = 20000; | |
3116 | ||
3117 | /* set defaults for eitr in MegaBytes */ | |
3118 | adapter->eitr_low = 10; | |
3119 | adapter->eitr_high = 20; | |
3120 | ||
3121 | /* set default ring sizes */ | |
3122 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
3123 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
3124 | ||
9a799d71 | 3125 | /* initialize eeprom parameters */ |
c44ade9e | 3126 | if (ixgbe_init_eeprom_params_generic(hw)) { |
9a799d71 AK |
3127 | dev_err(&pdev->dev, "EEPROM initialization failed\n"); |
3128 | return -EIO; | |
3129 | } | |
3130 | ||
021230d4 | 3131 | /* enable rx csum by default */ |
9a799d71 AK |
3132 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
3133 | ||
9a799d71 AK |
3134 | set_bit(__IXGBE_DOWN, &adapter->state); |
3135 | ||
3136 | return 0; | |
3137 | } | |
3138 | ||
3139 | /** | |
3140 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3141 | * @adapter: board private structure | |
3a581073 | 3142 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
3143 | * |
3144 | * Return 0 on success, negative on failure | |
3145 | **/ | |
3146 | int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter, | |
e01c31a5 | 3147 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
3148 | { |
3149 | struct pci_dev *pdev = adapter->pdev; | |
3150 | int size; | |
3151 | ||
3a581073 JB |
3152 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
3153 | tx_ring->tx_buffer_info = vmalloc(size); | |
e01c31a5 JB |
3154 | if (!tx_ring->tx_buffer_info) |
3155 | goto err; | |
3a581073 | 3156 | memset(tx_ring->tx_buffer_info, 0, size); |
9a799d71 AK |
3157 | |
3158 | /* round up to nearest 4K */ | |
12207e49 | 3159 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 3160 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 3161 | |
3a581073 JB |
3162 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, |
3163 | &tx_ring->dma); | |
e01c31a5 JB |
3164 | if (!tx_ring->desc) |
3165 | goto err; | |
9a799d71 | 3166 | |
3a581073 JB |
3167 | tx_ring->next_to_use = 0; |
3168 | tx_ring->next_to_clean = 0; | |
3169 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 3170 | return 0; |
e01c31a5 JB |
3171 | |
3172 | err: | |
3173 | vfree(tx_ring->tx_buffer_info); | |
3174 | tx_ring->tx_buffer_info = NULL; | |
3175 | DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit " | |
3176 | "descriptor ring\n"); | |
3177 | return -ENOMEM; | |
9a799d71 AK |
3178 | } |
3179 | ||
69888674 AD |
3180 | /** |
3181 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
3182 | * @adapter: board private structure | |
3183 | * | |
3184 | * If this function returns with an error, then it's possible one or | |
3185 | * more of the rings is populated (while the rest are not). It is the | |
3186 | * callers duty to clean those orphaned rings. | |
3187 | * | |
3188 | * Return 0 on success, negative on failure | |
3189 | **/ | |
3190 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
3191 | { | |
3192 | int i, err = 0; | |
3193 | ||
3194 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3195 | err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]); | |
3196 | if (!err) | |
3197 | continue; | |
3198 | DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i); | |
3199 | break; | |
3200 | } | |
3201 | ||
3202 | return err; | |
3203 | } | |
3204 | ||
9a799d71 AK |
3205 | /** |
3206 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3207 | * @adapter: board private structure | |
3a581073 | 3208 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
3209 | * |
3210 | * Returns 0 on success, negative on failure | |
3211 | **/ | |
3212 | int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, | |
b4617240 | 3213 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
3214 | { |
3215 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 3216 | int size; |
9a799d71 | 3217 | |
3a581073 JB |
3218 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
3219 | rx_ring->rx_buffer_info = vmalloc(size); | |
3220 | if (!rx_ring->rx_buffer_info) { | |
9a799d71 | 3221 | DPRINTK(PROBE, ERR, |
b4617240 | 3222 | "vmalloc allocation failed for the rx desc ring\n"); |
177db6ff | 3223 | goto alloc_failed; |
9a799d71 | 3224 | } |
3a581073 | 3225 | memset(rx_ring->rx_buffer_info, 0, size); |
9a799d71 | 3226 | |
9a799d71 | 3227 | /* Round up to nearest 4K */ |
3a581073 JB |
3228 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
3229 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 3230 | |
3a581073 | 3231 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma); |
9a799d71 | 3232 | |
3a581073 | 3233 | if (!rx_ring->desc) { |
9a799d71 | 3234 | DPRINTK(PROBE, ERR, |
b4617240 | 3235 | "Memory allocation failed for the rx desc ring\n"); |
3a581073 | 3236 | vfree(rx_ring->rx_buffer_info); |
177db6ff | 3237 | goto alloc_failed; |
9a799d71 AK |
3238 | } |
3239 | ||
3a581073 JB |
3240 | rx_ring->next_to_clean = 0; |
3241 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
3242 | |
3243 | return 0; | |
177db6ff MC |
3244 | |
3245 | alloc_failed: | |
177db6ff | 3246 | return -ENOMEM; |
9a799d71 AK |
3247 | } |
3248 | ||
69888674 AD |
3249 | /** |
3250 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
3251 | * @adapter: board private structure | |
3252 | * | |
3253 | * If this function returns with an error, then it's possible one or | |
3254 | * more of the rings is populated (while the rest are not). It is the | |
3255 | * callers duty to clean those orphaned rings. | |
3256 | * | |
3257 | * Return 0 on success, negative on failure | |
3258 | **/ | |
3259 | ||
3260 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) | |
3261 | { | |
3262 | int i, err = 0; | |
3263 | ||
3264 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3265 | err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]); | |
3266 | if (!err) | |
3267 | continue; | |
3268 | DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i); | |
3269 | break; | |
3270 | } | |
3271 | ||
3272 | return err; | |
3273 | } | |
3274 | ||
9a799d71 AK |
3275 | /** |
3276 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
3277 | * @adapter: board private structure | |
3278 | * @tx_ring: Tx descriptor ring for a specific queue | |
3279 | * | |
3280 | * Free all transmit software resources | |
3281 | **/ | |
c431f97e JB |
3282 | void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter, |
3283 | struct ixgbe_ring *tx_ring) | |
9a799d71 AK |
3284 | { |
3285 | struct pci_dev *pdev = adapter->pdev; | |
3286 | ||
3287 | ixgbe_clean_tx_ring(adapter, tx_ring); | |
3288 | ||
3289 | vfree(tx_ring->tx_buffer_info); | |
3290 | tx_ring->tx_buffer_info = NULL; | |
3291 | ||
3292 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
3293 | ||
3294 | tx_ring->desc = NULL; | |
3295 | } | |
3296 | ||
3297 | /** | |
3298 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
3299 | * @adapter: board private structure | |
3300 | * | |
3301 | * Free all transmit software resources | |
3302 | **/ | |
3303 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
3304 | { | |
3305 | int i; | |
3306 | ||
3307 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3308 | ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]); | |
3309 | } | |
3310 | ||
3311 | /** | |
b4617240 | 3312 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
3313 | * @adapter: board private structure |
3314 | * @rx_ring: ring to clean the resources from | |
3315 | * | |
3316 | * Free all receive software resources | |
3317 | **/ | |
c431f97e JB |
3318 | void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter, |
3319 | struct ixgbe_ring *rx_ring) | |
9a799d71 AK |
3320 | { |
3321 | struct pci_dev *pdev = adapter->pdev; | |
3322 | ||
3323 | ixgbe_clean_rx_ring(adapter, rx_ring); | |
3324 | ||
3325 | vfree(rx_ring->rx_buffer_info); | |
3326 | rx_ring->rx_buffer_info = NULL; | |
3327 | ||
3328 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
3329 | ||
3330 | rx_ring->desc = NULL; | |
3331 | } | |
3332 | ||
3333 | /** | |
3334 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
3335 | * @adapter: board private structure | |
3336 | * | |
3337 | * Free all receive software resources | |
3338 | **/ | |
3339 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
3340 | { | |
3341 | int i; | |
3342 | ||
3343 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3344 | ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]); | |
3345 | } | |
3346 | ||
9a799d71 AK |
3347 | /** |
3348 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
3349 | * @netdev: network interface device structure | |
3350 | * @new_mtu: new value for maximum frame size | |
3351 | * | |
3352 | * Returns 0 on success, negative on failure | |
3353 | **/ | |
3354 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
3355 | { | |
3356 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3357 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
3358 | ||
42c783c5 JB |
3359 | /* MTU < 68 is an error and causes problems on some kernels */ |
3360 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
9a799d71 AK |
3361 | return -EINVAL; |
3362 | ||
021230d4 | 3363 | DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n", |
b4617240 | 3364 | netdev->mtu, new_mtu); |
021230d4 | 3365 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
3366 | netdev->mtu = new_mtu; |
3367 | ||
d4f80882 AV |
3368 | if (netif_running(netdev)) |
3369 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
3370 | |
3371 | return 0; | |
3372 | } | |
3373 | ||
3374 | /** | |
3375 | * ixgbe_open - Called when a network interface is made active | |
3376 | * @netdev: network interface device structure | |
3377 | * | |
3378 | * Returns 0 on success, negative value on failure | |
3379 | * | |
3380 | * The open entry point is called when a network interface is made | |
3381 | * active by the system (IFF_UP). At this point all resources needed | |
3382 | * for transmit and receive operations are allocated, the interrupt | |
3383 | * handler is registered with the OS, the watchdog timer is started, | |
3384 | * and the stack is notified that the interface is ready. | |
3385 | **/ | |
3386 | static int ixgbe_open(struct net_device *netdev) | |
3387 | { | |
3388 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3389 | int err; | |
4bebfaa5 AK |
3390 | |
3391 | /* disallow open during test */ | |
3392 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
3393 | return -EBUSY; | |
9a799d71 | 3394 | |
9a799d71 AK |
3395 | /* allocate transmit descriptors */ |
3396 | err = ixgbe_setup_all_tx_resources(adapter); | |
3397 | if (err) | |
3398 | goto err_setup_tx; | |
3399 | ||
9a799d71 AK |
3400 | /* allocate receive descriptors */ |
3401 | err = ixgbe_setup_all_rx_resources(adapter); | |
3402 | if (err) | |
3403 | goto err_setup_rx; | |
3404 | ||
3405 | ixgbe_configure(adapter); | |
3406 | ||
021230d4 | 3407 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
3408 | if (err) |
3409 | goto err_req_irq; | |
3410 | ||
9a799d71 AK |
3411 | err = ixgbe_up_complete(adapter); |
3412 | if (err) | |
3413 | goto err_up; | |
3414 | ||
d55b53ff JK |
3415 | netif_tx_start_all_queues(netdev); |
3416 | ||
9a799d71 AK |
3417 | return 0; |
3418 | ||
3419 | err_up: | |
5eba3699 | 3420 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
3421 | ixgbe_free_irq(adapter); |
3422 | err_req_irq: | |
3423 | ixgbe_free_all_rx_resources(adapter); | |
3424 | err_setup_rx: | |
3425 | ixgbe_free_all_tx_resources(adapter); | |
3426 | err_setup_tx: | |
3427 | ixgbe_reset(adapter); | |
3428 | ||
3429 | return err; | |
3430 | } | |
3431 | ||
3432 | /** | |
3433 | * ixgbe_close - Disables a network interface | |
3434 | * @netdev: network interface device structure | |
3435 | * | |
3436 | * Returns 0, this is not allowed to fail | |
3437 | * | |
3438 | * The close entry point is called when an interface is de-activated | |
3439 | * by the OS. The hardware is still under the drivers control, but | |
3440 | * needs to be disabled. A global MAC reset is issued to stop the | |
3441 | * hardware, and all transmit and receive resources are freed. | |
3442 | **/ | |
3443 | static int ixgbe_close(struct net_device *netdev) | |
3444 | { | |
3445 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
3446 | |
3447 | ixgbe_down(adapter); | |
3448 | ixgbe_free_irq(adapter); | |
3449 | ||
3450 | ixgbe_free_all_tx_resources(adapter); | |
3451 | ixgbe_free_all_rx_resources(adapter); | |
3452 | ||
5eba3699 | 3453 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
3454 | |
3455 | return 0; | |
3456 | } | |
3457 | ||
b3c8b4ba AD |
3458 | /** |
3459 | * ixgbe_napi_add_all - prep napi structs for use | |
3460 | * @adapter: private struct | |
3461 | * helper function to napi_add each possible q_vector->napi | |
3462 | */ | |
2f90b865 | 3463 | void ixgbe_napi_add_all(struct ixgbe_adapter *adapter) |
b3c8b4ba AD |
3464 | { |
3465 | int q_idx, q_vectors; | |
7adf1525 | 3466 | struct net_device *netdev = adapter->netdev; |
b3c8b4ba AD |
3467 | int (*poll)(struct napi_struct *, int); |
3468 | ||
7adf1525 PWJ |
3469 | /* check if we already have our netdev->napi_list populated */ |
3470 | if (&netdev->napi_list != netdev->napi_list.next) | |
3471 | return; | |
3472 | ||
b3c8b4ba AD |
3473 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
3474 | poll = &ixgbe_clean_rxonly; | |
3475 | /* Only enable as many vectors as we have rx queues. */ | |
3476 | q_vectors = adapter->num_rx_queues; | |
3477 | } else { | |
3478 | poll = &ixgbe_poll; | |
3479 | /* only one q_vector for legacy modes */ | |
3480 | q_vectors = 1; | |
3481 | } | |
3482 | ||
3483 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
3484 | struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx]; | |
3485 | netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64); | |
3486 | } | |
3487 | } | |
3488 | ||
2f90b865 | 3489 | void ixgbe_napi_del_all(struct ixgbe_adapter *adapter) |
b3c8b4ba AD |
3490 | { |
3491 | int q_idx; | |
3492 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3493 | ||
3494 | /* legacy and MSI only use one vector */ | |
3495 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3496 | q_vectors = 1; | |
3497 | ||
3498 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
3499 | struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx]; | |
3500 | if (!q_vector->rxr_count) | |
3501 | continue; | |
3502 | netif_napi_del(&q_vector->napi); | |
3503 | } | |
3504 | } | |
3505 | ||
3506 | #ifdef CONFIG_PM | |
3507 | static int ixgbe_resume(struct pci_dev *pdev) | |
3508 | { | |
3509 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3510 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3511 | u32 err; | |
3512 | ||
3513 | pci_set_power_state(pdev, PCI_D0); | |
3514 | pci_restore_state(pdev); | |
3515 | err = pci_enable_device(pdev); | |
3516 | if (err) { | |
69888674 | 3517 | printk(KERN_ERR "ixgbe: Cannot enable PCI device from " |
b3c8b4ba AD |
3518 | "suspend\n"); |
3519 | return err; | |
3520 | } | |
3521 | pci_set_master(pdev); | |
3522 | ||
3523 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
3524 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
3525 | ||
3526 | err = ixgbe_init_interrupt_scheme(adapter); | |
3527 | if (err) { | |
3528 | printk(KERN_ERR "ixgbe: Cannot initialize interrupts for " | |
3529 | "device\n"); | |
3530 | return err; | |
3531 | } | |
3532 | ||
3533 | ixgbe_napi_add_all(adapter); | |
3534 | ixgbe_reset(adapter); | |
3535 | ||
3536 | if (netif_running(netdev)) { | |
3537 | err = ixgbe_open(adapter->netdev); | |
3538 | if (err) | |
3539 | return err; | |
3540 | } | |
3541 | ||
3542 | netif_device_attach(netdev); | |
3543 | ||
3544 | return 0; | |
3545 | } | |
3546 | ||
3547 | #endif /* CONFIG_PM */ | |
3548 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
3549 | { | |
3550 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3551 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
e8e26350 PW |
3552 | struct ixgbe_hw *hw = &adapter->hw; |
3553 | u32 ctrl, fctrl; | |
3554 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
3555 | #ifdef CONFIG_PM |
3556 | int retval = 0; | |
3557 | #endif | |
3558 | ||
3559 | netif_device_detach(netdev); | |
3560 | ||
3561 | if (netif_running(netdev)) { | |
3562 | ixgbe_down(adapter); | |
3563 | ixgbe_free_irq(adapter); | |
3564 | ixgbe_free_all_tx_resources(adapter); | |
3565 | ixgbe_free_all_rx_resources(adapter); | |
3566 | } | |
3567 | ixgbe_reset_interrupt_capability(adapter); | |
3568 | ixgbe_napi_del_all(adapter); | |
7adf1525 | 3569 | INIT_LIST_HEAD(&netdev->napi_list); |
b3c8b4ba AD |
3570 | kfree(adapter->tx_ring); |
3571 | kfree(adapter->rx_ring); | |
3572 | ||
3573 | #ifdef CONFIG_PM | |
3574 | retval = pci_save_state(pdev); | |
3575 | if (retval) | |
3576 | return retval; | |
3577 | #endif | |
e8e26350 PW |
3578 | if (wufc) { |
3579 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 3580 | |
e8e26350 PW |
3581 | /* turn on all-multi mode if wake on multicast is enabled */ |
3582 | if (wufc & IXGBE_WUFC_MC) { | |
3583 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3584 | fctrl |= IXGBE_FCTRL_MPE; | |
3585 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3586 | } | |
3587 | ||
3588 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
3589 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
3590 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
3591 | ||
3592 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
3593 | } else { | |
3594 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
3595 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
3596 | } | |
3597 | ||
3598 | if (wufc && hw->mac.type == ixgbe_mac_82599EB) { | |
3599 | pci_enable_wake(pdev, PCI_D3hot, 1); | |
3600 | pci_enable_wake(pdev, PCI_D3cold, 1); | |
3601 | } else { | |
3602 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
3603 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
3604 | } | |
b3c8b4ba AD |
3605 | |
3606 | ixgbe_release_hw_control(adapter); | |
3607 | ||
3608 | pci_disable_device(pdev); | |
3609 | ||
3610 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
3611 | ||
3612 | return 0; | |
3613 | } | |
3614 | ||
3615 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
3616 | { | |
3617 | ixgbe_suspend(pdev, PMSG_SUSPEND); | |
3618 | } | |
3619 | ||
9a799d71 AK |
3620 | /** |
3621 | * ixgbe_update_stats - Update the board statistics counters. | |
3622 | * @adapter: board private structure | |
3623 | **/ | |
3624 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
3625 | { | |
3626 | struct ixgbe_hw *hw = &adapter->hw; | |
6f11eef7 AV |
3627 | u64 total_mpc = 0; |
3628 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
9a799d71 | 3629 | |
d51019a4 PW |
3630 | if (hw->mac.type == ixgbe_mac_82599EB) { |
3631 | for (i = 0; i < 16; i++) | |
3632 | adapter->hw_rx_no_dma_resources += | |
3633 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
3634 | } | |
3635 | ||
9a799d71 | 3636 | adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
6f11eef7 AV |
3637 | for (i = 0; i < 8; i++) { |
3638 | /* for packet buffers not used, the register should read 0 */ | |
3639 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
3640 | missed_rx += mpc; | |
3641 | adapter->stats.mpc[i] += mpc; | |
3642 | total_mpc += adapter->stats.mpc[i]; | |
e8e26350 PW |
3643 | if (hw->mac.type == ixgbe_mac_82598EB) |
3644 | adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
2f90b865 AD |
3645 | adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); |
3646 | adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
3647 | adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
3648 | adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
e8e26350 PW |
3649 | if (hw->mac.type == ixgbe_mac_82599EB) { |
3650 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
3651 | IXGBE_PXONRXCNT(i)); | |
3652 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
3653 | IXGBE_PXOFFRXCNT(i)); | |
3654 | adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
e8e26350 PW |
3655 | } else { |
3656 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
3657 | IXGBE_PXONRXC(i)); | |
3658 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
3659 | IXGBE_PXOFFRXC(i)); | |
3660 | } | |
2f90b865 AD |
3661 | adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw, |
3662 | IXGBE_PXONTXC(i)); | |
2f90b865 | 3663 | adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw, |
e8e26350 | 3664 | IXGBE_PXOFFTXC(i)); |
6f11eef7 AV |
3665 | } |
3666 | adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); | |
3667 | /* work around hardware counting issue */ | |
3668 | adapter->stats.gprc -= missed_rx; | |
3669 | ||
3670 | /* 82598 hardware only has a 32 bit counter in the high register */ | |
e8e26350 PW |
3671 | if (hw->mac.type == ixgbe_mac_82599EB) { |
3672 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); | |
3673 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ | |
3674 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); | |
3675 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ | |
3676 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL); | |
3677 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ | |
3678 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); | |
3679 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
3680 | } else { | |
3681 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
3682 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
3683 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); | |
3684 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
3685 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
3686 | } | |
9a799d71 AK |
3687 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
3688 | adapter->stats.bprc += bprc; | |
3689 | adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 PW |
3690 | if (hw->mac.type == ixgbe_mac_82598EB) |
3691 | adapter->stats.mprc -= bprc; | |
9a799d71 AK |
3692 | adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC); |
3693 | adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
3694 | adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
3695 | adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
3696 | adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
3697 | adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
3698 | adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
9a799d71 | 3699 | adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); |
6f11eef7 AV |
3700 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
3701 | adapter->stats.lxontxc += lxon; | |
3702 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
3703 | adapter->stats.lxofftxc += lxoff; | |
9a799d71 AK |
3704 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
3705 | adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
6f11eef7 AV |
3706 | adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); |
3707 | /* | |
3708 | * 82598 errata - tx of flow control packets is included in tx counters | |
3709 | */ | |
3710 | xon_off_tot = lxon + lxoff; | |
3711 | adapter->stats.gptc -= xon_off_tot; | |
3712 | adapter->stats.mptc -= xon_off_tot; | |
3713 | adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
9a799d71 AK |
3714 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
3715 | adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
3716 | adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
9a799d71 AK |
3717 | adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR); |
3718 | adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6f11eef7 | 3719 | adapter->stats.ptc64 -= xon_off_tot; |
9a799d71 AK |
3720 | adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); |
3721 | adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
3722 | adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
3723 | adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
3724 | adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
9a799d71 AK |
3725 | adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); |
3726 | ||
3727 | /* Fill out the OS statistics structure */ | |
9a799d71 AK |
3728 | adapter->net_stats.multicast = adapter->stats.mprc; |
3729 | ||
3730 | /* Rx Errors */ | |
3731 | adapter->net_stats.rx_errors = adapter->stats.crcerrs + | |
b4617240 | 3732 | adapter->stats.rlec; |
9a799d71 AK |
3733 | adapter->net_stats.rx_dropped = 0; |
3734 | adapter->net_stats.rx_length_errors = adapter->stats.rlec; | |
3735 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; | |
6f11eef7 | 3736 | adapter->net_stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
3737 | } |
3738 | ||
3739 | /** | |
3740 | * ixgbe_watchdog - Timer Call-back | |
3741 | * @data: pointer to adapter cast into an unsigned long | |
3742 | **/ | |
3743 | static void ixgbe_watchdog(unsigned long data) | |
3744 | { | |
3745 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee JB |
3746 | struct ixgbe_hw *hw = &adapter->hw; |
3747 | ||
3748 | /* Do the watchdog outside of interrupt context due to the lovely | |
3749 | * delays that some of the newer hardware requires */ | |
3750 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
3751 | /* Cause software interrupt to ensure rx rings are cleaned */ | |
3752 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3753 | u32 eics = | |
3754 | (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1; | |
3755 | IXGBE_WRITE_REG(hw, IXGBE_EICS, eics); | |
3756 | } else { | |
3757 | /* For legacy and MSI interrupts don't set any bits that | |
3758 | * are enabled for EIAM, because this operation would | |
3759 | * set *both* EIMS and EICS for any bit in EIAM */ | |
3760 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
3761 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
3762 | } | |
3763 | /* Reset the timer */ | |
3764 | mod_timer(&adapter->watchdog_timer, | |
3765 | round_jiffies(jiffies + 2 * HZ)); | |
3766 | } | |
9a799d71 | 3767 | |
cf8280ee JB |
3768 | schedule_work(&adapter->watchdog_task); |
3769 | } | |
3770 | ||
e8e26350 PW |
3771 | /** |
3772 | * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber | |
3773 | * @work: pointer to work_struct containing our data | |
3774 | **/ | |
3775 | static void ixgbe_multispeed_fiber_task(struct work_struct *work) | |
3776 | { | |
3777 | struct ixgbe_adapter *adapter = container_of(work, | |
3778 | struct ixgbe_adapter, | |
3779 | multispeed_fiber_task); | |
3780 | struct ixgbe_hw *hw = &adapter->hw; | |
3781 | u32 autoneg; | |
3782 | ||
3783 | adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK; | |
3784 | if (hw->mac.ops.get_link_capabilities) | |
3785 | hw->mac.ops.get_link_capabilities(hw, &autoneg, | |
3786 | &hw->mac.autoneg); | |
3787 | if (hw->mac.ops.setup_link_speed) | |
3788 | hw->mac.ops.setup_link_speed(hw, autoneg, true, true); | |
3789 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
3790 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK; | |
3791 | } | |
3792 | ||
3793 | /** | |
3794 | * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module | |
3795 | * @work: pointer to work_struct containing our data | |
3796 | **/ | |
3797 | static void ixgbe_sfp_config_module_task(struct work_struct *work) | |
3798 | { | |
3799 | struct ixgbe_adapter *adapter = container_of(work, | |
3800 | struct ixgbe_adapter, | |
3801 | sfp_config_module_task); | |
3802 | struct ixgbe_hw *hw = &adapter->hw; | |
3803 | u32 err; | |
3804 | ||
3805 | adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK; | |
3806 | err = hw->phy.ops.identify_sfp(hw); | |
3807 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
3808 | DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err); | |
3809 | ixgbe_down(adapter); | |
3810 | return; | |
3811 | } | |
3812 | hw->mac.ops.setup_sfp(hw); | |
3813 | ||
3814 | if (!adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK) | |
3815 | /* This will also work for DA Twinax connections */ | |
3816 | schedule_work(&adapter->multispeed_fiber_task); | |
3817 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK; | |
3818 | } | |
3819 | ||
cf8280ee | 3820 | /** |
69888674 AD |
3821 | * ixgbe_watchdog_task - worker thread to bring link up |
3822 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
3823 | **/ |
3824 | static void ixgbe_watchdog_task(struct work_struct *work) | |
3825 | { | |
3826 | struct ixgbe_adapter *adapter = container_of(work, | |
3827 | struct ixgbe_adapter, | |
3828 | watchdog_task); | |
3829 | struct net_device *netdev = adapter->netdev; | |
3830 | struct ixgbe_hw *hw = &adapter->hw; | |
3831 | u32 link_speed = adapter->link_speed; | |
3832 | bool link_up = adapter->link_up; | |
3833 | ||
3834 | adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK; | |
3835 | ||
3836 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
3837 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
3838 | if (link_up || | |
3839 | time_after(jiffies, (adapter->link_check_timeout + | |
3840 | IXGBE_TRY_LINK_TIMEOUT))) { | |
3841 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
3842 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
3843 | } | |
3844 | adapter->link_up = link_up; | |
3845 | adapter->link_speed = link_speed; | |
3846 | } | |
9a799d71 AK |
3847 | |
3848 | if (link_up) { | |
3849 | if (!netif_carrier_ok(netdev)) { | |
e8e26350 PW |
3850 | bool flow_rx, flow_tx; |
3851 | ||
3852 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
3853 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
3854 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
3855 | flow_rx = (mflcn & IXGBE_MFLCN_RFCE); | |
3856 | flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
3857 | } else { | |
3858 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3859 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
3860 | flow_rx = (frctl & IXGBE_FCTRL_RFCE); | |
3861 | flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X); | |
3862 | } | |
3863 | ||
a46e534b JK |
3864 | printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, " |
3865 | "Flow Control: %s\n", | |
3866 | netdev->name, | |
3867 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
3868 | "10 Gbps" : | |
3869 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
3870 | "1 Gbps" : "unknown speed")), | |
e8e26350 PW |
3871 | ((flow_rx && flow_tx) ? "RX/TX" : |
3872 | (flow_rx ? "RX" : | |
3873 | (flow_tx ? "TX" : "None")))); | |
9a799d71 AK |
3874 | |
3875 | netif_carrier_on(netdev); | |
9a799d71 AK |
3876 | } else { |
3877 | /* Force detection of hung controller */ | |
3878 | adapter->detect_tx_hung = true; | |
3879 | } | |
3880 | } else { | |
cf8280ee JB |
3881 | adapter->link_up = false; |
3882 | adapter->link_speed = 0; | |
9a799d71 | 3883 | if (netif_carrier_ok(netdev)) { |
a46e534b JK |
3884 | printk(KERN_INFO "ixgbe: %s NIC Link is Down\n", |
3885 | netdev->name); | |
9a799d71 | 3886 | netif_carrier_off(netdev); |
9a799d71 AK |
3887 | } |
3888 | } | |
3889 | ||
3890 | ixgbe_update_stats(adapter); | |
cf8280ee | 3891 | adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK; |
9a799d71 AK |
3892 | } |
3893 | ||
9a799d71 | 3894 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
b4617240 PW |
3895 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
3896 | u32 tx_flags, u8 *hdr_len) | |
9a799d71 AK |
3897 | { |
3898 | struct ixgbe_adv_tx_context_desc *context_desc; | |
3899 | unsigned int i; | |
3900 | int err; | |
3901 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
3902 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
3903 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
3904 | |
3905 | if (skb_is_gso(skb)) { | |
3906 | if (skb_header_cloned(skb)) { | |
3907 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
3908 | if (err) | |
3909 | return err; | |
3910 | } | |
3911 | l4len = tcp_hdrlen(skb); | |
3912 | *hdr_len += l4len; | |
3913 | ||
8327d000 | 3914 | if (skb->protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
3915 | struct iphdr *iph = ip_hdr(skb); |
3916 | iph->tot_len = 0; | |
3917 | iph->check = 0; | |
3918 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
b4617240 PW |
3919 | iph->daddr, 0, |
3920 | IPPROTO_TCP, | |
3921 | 0); | |
9a799d71 AK |
3922 | adapter->hw_tso_ctxt++; |
3923 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { | |
3924 | ipv6_hdr(skb)->payload_len = 0; | |
3925 | tcp_hdr(skb)->check = | |
3926 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
b4617240 PW |
3927 | &ipv6_hdr(skb)->daddr, |
3928 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
3929 | adapter->hw_tso6_ctxt++; |
3930 | } | |
3931 | ||
3932 | i = tx_ring->next_to_use; | |
3933 | ||
3934 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3935 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
3936 | ||
3937 | /* VLAN MACLEN IPLEN */ | |
3938 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
3939 | vlan_macip_lens |= | |
3940 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
3941 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
b4617240 | 3942 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
3943 | *hdr_len += skb_network_offset(skb); |
3944 | vlan_macip_lens |= | |
3945 | (skb_transport_header(skb) - skb_network_header(skb)); | |
3946 | *hdr_len += | |
3947 | (skb_transport_header(skb) - skb_network_header(skb)); | |
3948 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
3949 | context_desc->seqnum_seed = 0; | |
3950 | ||
3951 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 3952 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
b4617240 | 3953 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 3954 | |
8327d000 | 3955 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
3956 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
3957 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
3958 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
3959 | ||
3960 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 3961 | mss_l4len_idx = |
9a799d71 AK |
3962 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
3963 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
3964 | /* use index 1 for TSO */ |
3965 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
3966 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
3967 | ||
3968 | tx_buffer_info->time_stamp = jiffies; | |
3969 | tx_buffer_info->next_to_watch = i; | |
3970 | ||
3971 | i++; | |
3972 | if (i == tx_ring->count) | |
3973 | i = 0; | |
3974 | tx_ring->next_to_use = i; | |
3975 | ||
3976 | return true; | |
3977 | } | |
3978 | return false; | |
3979 | } | |
3980 | ||
3981 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, | |
b4617240 PW |
3982 | struct ixgbe_ring *tx_ring, |
3983 | struct sk_buff *skb, u32 tx_flags) | |
9a799d71 AK |
3984 | { |
3985 | struct ixgbe_adv_tx_context_desc *context_desc; | |
3986 | unsigned int i; | |
3987 | struct ixgbe_tx_buffer *tx_buffer_info; | |
3988 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
3989 | ||
3990 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
3991 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
3992 | i = tx_ring->next_to_use; | |
3993 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3994 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
3995 | ||
3996 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
3997 | vlan_macip_lens |= | |
3998 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
3999 | vlan_macip_lens |= (skb_network_offset(skb) << | |
b4617240 | 4000 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
4001 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
4002 | vlan_macip_lens |= (skb_transport_header(skb) - | |
b4617240 | 4003 | skb_network_header(skb)); |
9a799d71 AK |
4004 | |
4005 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4006 | context_desc->seqnum_seed = 0; | |
4007 | ||
4008 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
b4617240 | 4009 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 AK |
4010 | |
4011 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
41825d71 | 4012 | switch (skb->protocol) { |
09640e63 | 4013 | case cpu_to_be16(ETH_P_IP): |
9a799d71 | 4014 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
41825d71 AK |
4015 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
4016 | type_tucmd_mlhl |= | |
b4617240 | 4017 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
41825d71 | 4018 | break; |
09640e63 | 4019 | case cpu_to_be16(ETH_P_IPV6): |
41825d71 AK |
4020 | /* XXX what about other V6 headers?? */ |
4021 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
4022 | type_tucmd_mlhl |= | |
b4617240 | 4023 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
41825d71 | 4024 | break; |
41825d71 AK |
4025 | default: |
4026 | if (unlikely(net_ratelimit())) { | |
4027 | DPRINTK(PROBE, WARNING, | |
4028 | "partial checksum but proto=%x!\n", | |
4029 | skb->protocol); | |
4030 | } | |
4031 | break; | |
4032 | } | |
9a799d71 AK |
4033 | } |
4034 | ||
4035 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 4036 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
4037 | context_desc->mss_l4len_idx = 0; |
4038 | ||
4039 | tx_buffer_info->time_stamp = jiffies; | |
4040 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 4041 | |
9a799d71 AK |
4042 | adapter->hw_csum_tx_good++; |
4043 | i++; | |
4044 | if (i == tx_ring->count) | |
4045 | i = 0; | |
4046 | tx_ring->next_to_use = i; | |
4047 | ||
4048 | return true; | |
4049 | } | |
9f8cdf4f | 4050 | |
9a799d71 AK |
4051 | return false; |
4052 | } | |
4053 | ||
4054 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
b4617240 PW |
4055 | struct ixgbe_ring *tx_ring, |
4056 | struct sk_buff *skb, unsigned int first) | |
9a799d71 AK |
4057 | { |
4058 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4059 | unsigned int len = skb->len; | |
4060 | unsigned int offset = 0, size, count = 0, i; | |
4061 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
4062 | unsigned int f; | |
4063 | ||
4064 | len -= skb->data_len; | |
4065 | ||
4066 | i = tx_ring->next_to_use; | |
4067 | ||
4068 | while (len) { | |
4069 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4070 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
4071 | ||
4072 | tx_buffer_info->length = size; | |
4073 | tx_buffer_info->dma = pci_map_single(adapter->pdev, | |
b4617240 PW |
4074 | skb->data + offset, |
4075 | size, PCI_DMA_TODEVICE); | |
9a799d71 AK |
4076 | tx_buffer_info->time_stamp = jiffies; |
4077 | tx_buffer_info->next_to_watch = i; | |
4078 | ||
4079 | len -= size; | |
4080 | offset += size; | |
4081 | count++; | |
4082 | i++; | |
4083 | if (i == tx_ring->count) | |
4084 | i = 0; | |
4085 | } | |
4086 | ||
4087 | for (f = 0; f < nr_frags; f++) { | |
4088 | struct skb_frag_struct *frag; | |
4089 | ||
4090 | frag = &skb_shinfo(skb)->frags[f]; | |
4091 | len = frag->size; | |
4092 | offset = frag->page_offset; | |
4093 | ||
4094 | while (len) { | |
4095 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4096 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
4097 | ||
4098 | tx_buffer_info->length = size; | |
4099 | tx_buffer_info->dma = pci_map_page(adapter->pdev, | |
b4617240 PW |
4100 | frag->page, |
4101 | offset, | |
4102 | size, | |
4103 | PCI_DMA_TODEVICE); | |
9a799d71 AK |
4104 | tx_buffer_info->time_stamp = jiffies; |
4105 | tx_buffer_info->next_to_watch = i; | |
4106 | ||
4107 | len -= size; | |
4108 | offset += size; | |
4109 | count++; | |
4110 | i++; | |
4111 | if (i == tx_ring->count) | |
4112 | i = 0; | |
4113 | } | |
4114 | } | |
4115 | if (i == 0) | |
4116 | i = tx_ring->count - 1; | |
4117 | else | |
4118 | i = i - 1; | |
4119 | tx_ring->tx_buffer_info[i].skb = skb; | |
4120 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
4121 | ||
4122 | return count; | |
4123 | } | |
4124 | ||
4125 | static void ixgbe_tx_queue(struct ixgbe_adapter *adapter, | |
b4617240 PW |
4126 | struct ixgbe_ring *tx_ring, |
4127 | int tx_flags, int count, u32 paylen, u8 hdr_len) | |
9a799d71 AK |
4128 | { |
4129 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
4130 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4131 | u32 olinfo_status = 0, cmd_type_len = 0; | |
4132 | unsigned int i; | |
4133 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
4134 | ||
4135 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
4136 | ||
4137 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
4138 | ||
4139 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4140 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
4141 | ||
4142 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
4143 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
4144 | ||
4145 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 4146 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 4147 | |
4eeae6fd PW |
4148 | /* use index 1 context for tso */ |
4149 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
4150 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
4151 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
b4617240 | 4152 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
4153 | |
4154 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
4155 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 4156 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
4157 | |
4158 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); | |
4159 | ||
4160 | i = tx_ring->next_to_use; | |
4161 | while (count--) { | |
4162 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4163 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); | |
4164 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); | |
4165 | tx_desc->read.cmd_type_len = | |
b4617240 | 4166 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 4167 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
4168 | i++; |
4169 | if (i == tx_ring->count) | |
4170 | i = 0; | |
4171 | } | |
4172 | ||
4173 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
4174 | ||
4175 | /* | |
4176 | * Force memory writes to complete before letting h/w | |
4177 | * know there are new descriptors to fetch. (Only | |
4178 | * applicable for weak-ordered memory model archs, | |
4179 | * such as IA-64). | |
4180 | */ | |
4181 | wmb(); | |
4182 | ||
4183 | tx_ring->next_to_use = i; | |
4184 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
4185 | } | |
4186 | ||
e092be60 | 4187 | static int __ixgbe_maybe_stop_tx(struct net_device *netdev, |
b4617240 | 4188 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
4189 | { |
4190 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4191 | ||
30eba97a | 4192 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
4193 | /* Herbert's original patch had: |
4194 | * smp_mb__after_netif_stop_queue(); | |
4195 | * but since that doesn't exist yet, just open code it. */ | |
4196 | smp_mb(); | |
4197 | ||
4198 | /* We need to check again in a case another CPU has just | |
4199 | * made room available. */ | |
4200 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
4201 | return -EBUSY; | |
4202 | ||
4203 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
af72166f | 4204 | netif_start_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
4205 | ++adapter->restart_queue; |
4206 | return 0; | |
4207 | } | |
4208 | ||
4209 | static int ixgbe_maybe_stop_tx(struct net_device *netdev, | |
b4617240 | 4210 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
4211 | { |
4212 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
4213 | return 0; | |
4214 | return __ixgbe_maybe_stop_tx(netdev, tx_ring, size); | |
4215 | } | |
4216 | ||
9a799d71 AK |
4217 | static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
4218 | { | |
4219 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4220 | struct ixgbe_ring *tx_ring; | |
9a799d71 AK |
4221 | unsigned int first; |
4222 | unsigned int tx_flags = 0; | |
30eba97a AV |
4223 | u8 hdr_len = 0; |
4224 | int r_idx = 0, tso; | |
9a799d71 AK |
4225 | int count = 0; |
4226 | unsigned int f; | |
9f8cdf4f | 4227 | |
30eba97a | 4228 | r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping; |
30eba97a | 4229 | tx_ring = &adapter->tx_ring[r_idx]; |
9a799d71 | 4230 | |
9f8cdf4f JB |
4231 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { |
4232 | tx_flags |= vlan_tx_tag_get(skb); | |
2f90b865 AD |
4233 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
4234 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
4235 | tx_flags |= (skb->queue_mapping << 13); | |
4236 | } | |
4237 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
4238 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
4239 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
4240 | tx_flags |= (skb->queue_mapping << 13); | |
9f8cdf4f JB |
4241 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; |
4242 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 4243 | } |
9f8cdf4f JB |
4244 | /* three things can cause us to need a context descriptor */ |
4245 | if (skb_is_gso(skb) || | |
4246 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
4247 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) | |
9a799d71 AK |
4248 | count++; |
4249 | ||
9f8cdf4f JB |
4250 | count += TXD_USE_COUNT(skb_headlen(skb)); |
4251 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
4252 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
4253 | ||
e092be60 | 4254 | if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) { |
9a799d71 | 4255 | adapter->tx_busy++; |
9a799d71 AK |
4256 | return NETDEV_TX_BUSY; |
4257 | } | |
9a799d71 | 4258 | |
8327d000 | 4259 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
4260 | tx_flags |= IXGBE_TX_FLAGS_IPV4; |
4261 | first = tx_ring->next_to_use; | |
4262 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
4263 | if (tso < 0) { | |
4264 | dev_kfree_skb_any(skb); | |
4265 | return NETDEV_TX_OK; | |
4266 | } | |
4267 | ||
4268 | if (tso) | |
4269 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
4270 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) && | |
b4617240 | 4271 | (skb->ip_summed == CHECKSUM_PARTIAL)) |
9a799d71 AK |
4272 | tx_flags |= IXGBE_TX_FLAGS_CSUM; |
4273 | ||
4274 | ixgbe_tx_queue(adapter, tx_ring, tx_flags, | |
b4617240 PW |
4275 | ixgbe_tx_map(adapter, tx_ring, skb, first), |
4276 | skb->len, hdr_len); | |
9a799d71 AK |
4277 | |
4278 | netdev->trans_start = jiffies; | |
4279 | ||
e092be60 | 4280 | ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED); |
9a799d71 AK |
4281 | |
4282 | return NETDEV_TX_OK; | |
4283 | } | |
4284 | ||
4285 | /** | |
4286 | * ixgbe_get_stats - Get System Network Statistics | |
4287 | * @netdev: network interface device structure | |
4288 | * | |
4289 | * Returns the address of the device statistics structure. | |
4290 | * The statistics are actually updated from the timer callback. | |
4291 | **/ | |
4292 | static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev) | |
4293 | { | |
4294 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4295 | ||
4296 | /* only return the current stats */ | |
4297 | return &adapter->net_stats; | |
4298 | } | |
4299 | ||
4300 | /** | |
4301 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
4302 | * @netdev: network interface device structure | |
4303 | * @p: pointer to an address structure | |
4304 | * | |
4305 | * Returns 0 on success, negative on failure | |
4306 | **/ | |
4307 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
4308 | { | |
4309 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 4310 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
4311 | struct sockaddr *addr = p; |
4312 | ||
4313 | if (!is_valid_ether_addr(addr->sa_data)) | |
4314 | return -EADDRNOTAVAIL; | |
4315 | ||
4316 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 4317 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 4318 | |
b4617240 | 4319 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
4320 | |
4321 | return 0; | |
4322 | } | |
4323 | ||
4324 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
4325 | /* | |
4326 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
4327 | * without having to re-enable interrupts. It's not called while | |
4328 | * the interrupt routine is executing. | |
4329 | */ | |
4330 | static void ixgbe_netpoll(struct net_device *netdev) | |
4331 | { | |
4332 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4333 | ||
4334 | disable_irq(adapter->pdev->irq); | |
4335 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; | |
4336 | ixgbe_intr(adapter->pdev->irq, netdev); | |
4337 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; | |
4338 | enable_irq(adapter->pdev->irq); | |
4339 | } | |
4340 | #endif | |
4341 | ||
0edc3527 SH |
4342 | static const struct net_device_ops ixgbe_netdev_ops = { |
4343 | .ndo_open = ixgbe_open, | |
4344 | .ndo_stop = ixgbe_close, | |
00829823 | 4345 | .ndo_start_xmit = ixgbe_xmit_frame, |
0edc3527 SH |
4346 | .ndo_get_stats = ixgbe_get_stats, |
4347 | .ndo_set_multicast_list = ixgbe_set_rx_mode, | |
4348 | .ndo_validate_addr = eth_validate_addr, | |
4349 | .ndo_set_mac_address = ixgbe_set_mac, | |
4350 | .ndo_change_mtu = ixgbe_change_mtu, | |
4351 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
4352 | .ndo_vlan_rx_register = ixgbe_vlan_rx_register, | |
4353 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, | |
4354 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
4355 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
4356 | .ndo_poll_controller = ixgbe_netpoll, | |
4357 | #endif | |
4358 | }; | |
4359 | ||
9a799d71 AK |
4360 | /** |
4361 | * ixgbe_probe - Device Initialization Routine | |
4362 | * @pdev: PCI device information struct | |
4363 | * @ent: entry in ixgbe_pci_tbl | |
4364 | * | |
4365 | * Returns 0 on success, negative on failure | |
4366 | * | |
4367 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
4368 | * The OS initialization, configuring of the adapter private structure, | |
4369 | * and a hardware reset occur. | |
4370 | **/ | |
4371 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
b4617240 | 4372 | const struct pci_device_id *ent) |
9a799d71 AK |
4373 | { |
4374 | struct net_device *netdev; | |
4375 | struct ixgbe_adapter *adapter = NULL; | |
4376 | struct ixgbe_hw *hw; | |
4377 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
4378 | static int cards_found; |
4379 | int i, err, pci_using_dac; | |
e8e26350 | 4380 | u16 pm_value = 0; |
c44ade9e | 4381 | u32 part_num, eec; |
9a799d71 AK |
4382 | |
4383 | err = pci_enable_device(pdev); | |
4384 | if (err) | |
4385 | return err; | |
4386 | ||
4387 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) && | |
4388 | !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) { | |
4389 | pci_using_dac = 1; | |
4390 | } else { | |
4391 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
4392 | if (err) { | |
4393 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
4394 | if (err) { | |
b4617240 PW |
4395 | dev_err(&pdev->dev, "No usable DMA " |
4396 | "configuration, aborting\n"); | |
9a799d71 AK |
4397 | goto err_dma; |
4398 | } | |
4399 | } | |
4400 | pci_using_dac = 0; | |
4401 | } | |
4402 | ||
4403 | err = pci_request_regions(pdev, ixgbe_driver_name); | |
4404 | if (err) { | |
4405 | dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err); | |
4406 | goto err_pci_reg; | |
4407 | } | |
4408 | ||
6fabd715 PWJ |
4409 | err = pci_enable_pcie_error_reporting(pdev); |
4410 | if (err) { | |
4411 | dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " | |
4412 | "0x%x\n", err); | |
4413 | /* non-fatal, continue */ | |
4414 | } | |
4415 | ||
9a799d71 | 4416 | pci_set_master(pdev); |
fb3b27bc | 4417 | pci_save_state(pdev); |
9a799d71 | 4418 | |
30eba97a | 4419 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES); |
9a799d71 AK |
4420 | if (!netdev) { |
4421 | err = -ENOMEM; | |
4422 | goto err_alloc_etherdev; | |
4423 | } | |
4424 | ||
9a799d71 AK |
4425 | SET_NETDEV_DEV(netdev, &pdev->dev); |
4426 | ||
4427 | pci_set_drvdata(pdev, netdev); | |
4428 | adapter = netdev_priv(netdev); | |
4429 | ||
4430 | adapter->netdev = netdev; | |
4431 | adapter->pdev = pdev; | |
4432 | hw = &adapter->hw; | |
4433 | hw->back = adapter; | |
4434 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
4435 | ||
05857980 JK |
4436 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
4437 | pci_resource_len(pdev, 0)); | |
9a799d71 AK |
4438 | if (!hw->hw_addr) { |
4439 | err = -EIO; | |
4440 | goto err_ioremap; | |
4441 | } | |
4442 | ||
4443 | for (i = 1; i <= 5; i++) { | |
4444 | if (pci_resource_len(pdev, i) == 0) | |
4445 | continue; | |
4446 | } | |
4447 | ||
0edc3527 | 4448 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 4449 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 4450 | netdev->watchdog_timeo = 5 * HZ; |
9a799d71 AK |
4451 | strcpy(netdev->name, pci_name(pdev)); |
4452 | ||
9a799d71 AK |
4453 | adapter->bd_number = cards_found; |
4454 | ||
9a799d71 AK |
4455 | /* Setup hw api */ |
4456 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 4457 | hw->mac.type = ii->mac; |
9a799d71 | 4458 | |
c44ade9e JB |
4459 | /* EEPROM */ |
4460 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
4461 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
4462 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
4463 | if (!(eec & (1 << 8))) | |
4464 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
4465 | ||
4466 | /* PHY */ | |
4467 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 DS |
4468 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
4469 | ||
4470 | /* set up this timer and work struct before calling get_invariants | |
4471 | * which might start the timer | |
4472 | */ | |
4473 | init_timer(&adapter->sfp_timer); | |
4474 | adapter->sfp_timer.function = &ixgbe_sfp_timer; | |
4475 | adapter->sfp_timer.data = (unsigned long) adapter; | |
4476 | ||
4477 | INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); | |
c44ade9e | 4478 | |
e8e26350 PW |
4479 | /* multispeed fiber has its own tasklet, called from GPI SDP1 context */ |
4480 | INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task); | |
4481 | ||
4482 | /* a new SFP+ module arrival, called from GPI SDP2 context */ | |
4483 | INIT_WORK(&adapter->sfp_config_module_task, | |
4484 | ixgbe_sfp_config_module_task); | |
4485 | ||
9a799d71 | 4486 | err = ii->get_invariants(hw); |
c4900be0 DS |
4487 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
4488 | /* start a kernel thread to watch for a module to arrive */ | |
4489 | set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
4490 | mod_timer(&adapter->sfp_timer, | |
4491 | round_jiffies(jiffies + (2 * HZ))); | |
4492 | err = 0; | |
4493 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
4494 | DPRINTK(PROBE, ERR, "failed to load because an " | |
4495 | "unsupported SFP+ module type was detected.\n"); | |
9a799d71 | 4496 | goto err_hw_init; |
c4900be0 DS |
4497 | } else if (err) { |
4498 | goto err_hw_init; | |
4499 | } | |
9a799d71 AK |
4500 | |
4501 | /* setup the private structure */ | |
4502 | err = ixgbe_sw_init(adapter); | |
4503 | if (err) | |
4504 | goto err_sw_init; | |
4505 | ||
c44ade9e JB |
4506 | /* reset_hw fills in the perm_addr as well */ |
4507 | err = hw->mac.ops.reset_hw(hw); | |
4508 | if (err) { | |
4509 | dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err); | |
4510 | goto err_sw_init; | |
4511 | } | |
4512 | ||
9a799d71 | 4513 | netdev->features = NETIF_F_SG | |
b4617240 PW |
4514 | NETIF_F_IP_CSUM | |
4515 | NETIF_F_HW_VLAN_TX | | |
4516 | NETIF_F_HW_VLAN_RX | | |
4517 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 4518 | |
e9990a9c | 4519 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 4520 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 4521 | netdev->features |= NETIF_F_TSO6; |
78b6f4ce | 4522 | netdev->features |= NETIF_F_GRO; |
ad31c402 JK |
4523 | |
4524 | netdev->vlan_features |= NETIF_F_TSO; | |
4525 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 4526 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
ad31c402 JK |
4527 | netdev->vlan_features |= NETIF_F_SG; |
4528 | ||
2f90b865 AD |
4529 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
4530 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
4531 | ||
7a6b6f51 | 4532 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4533 | netdev->dcbnl_ops = &dcbnl_ops; |
4534 | #endif | |
4535 | ||
9a799d71 AK |
4536 | if (pci_using_dac) |
4537 | netdev->features |= NETIF_F_HIGHDMA; | |
4538 | ||
9a799d71 | 4539 | /* make sure the EEPROM is good */ |
c44ade9e | 4540 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
9a799d71 AK |
4541 | dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); |
4542 | err = -EIO; | |
4543 | goto err_eeprom; | |
4544 | } | |
4545 | ||
4546 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
4547 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
4548 | ||
c44ade9e JB |
4549 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
4550 | dev_err(&pdev->dev, "invalid MAC address\n"); | |
9a799d71 AK |
4551 | err = -EIO; |
4552 | goto err_eeprom; | |
4553 | } | |
4554 | ||
4555 | init_timer(&adapter->watchdog_timer); | |
4556 | adapter->watchdog_timer.function = &ixgbe_watchdog; | |
4557 | adapter->watchdog_timer.data = (unsigned long)adapter; | |
4558 | ||
4559 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 4560 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 4561 | |
021230d4 AV |
4562 | err = ixgbe_init_interrupt_scheme(adapter); |
4563 | if (err) | |
4564 | goto err_sw_init; | |
9a799d71 | 4565 | |
e8e26350 PW |
4566 | switch (pdev->device) { |
4567 | case IXGBE_DEV_ID_82599_KX4: | |
4568 | #define IXGBE_PCIE_PMCSR 0x44 | |
4569 | adapter->wol = IXGBE_WUFC_MAG; | |
4570 | pci_read_config_word(pdev, IXGBE_PCIE_PMCSR, &pm_value); | |
4571 | pci_write_config_word(pdev, IXGBE_PCIE_PMCSR, | |
4572 | (pm_value | (1 << 8))); | |
4573 | break; | |
4574 | default: | |
4575 | adapter->wol = 0; | |
4576 | break; | |
4577 | } | |
4578 | device_init_wakeup(&adapter->pdev->dev, true); | |
4579 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); | |
4580 | ||
9a799d71 | 4581 | /* print bus type/speed/width info */ |
7c510e4b | 4582 | dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n", |
e8e26350 PW |
4583 | ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s": |
4584 | (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"), | |
4585 | ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" : | |
4586 | (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" : | |
4587 | (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" : | |
b4617240 | 4588 | "Unknown"), |
7c510e4b | 4589 | netdev->dev_addr); |
c44ade9e | 4590 | ixgbe_read_pba_num_generic(hw, &part_num); |
e8e26350 PW |
4591 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
4592 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n", | |
4593 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, | |
4594 | (part_num >> 8), (part_num & 0xff)); | |
4595 | else | |
4596 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", | |
4597 | hw->mac.type, hw->phy.type, | |
4598 | (part_num >> 8), (part_num & 0xff)); | |
9a799d71 | 4599 | |
e8e26350 | 4600 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
0c254d86 | 4601 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for " |
b4617240 PW |
4602 | "this card is not sufficient for optimal " |
4603 | "performance.\n"); | |
0c254d86 | 4604 | dev_warn(&pdev->dev, "For optimal performance a x8 " |
b4617240 | 4605 | "PCI-Express slot is required.\n"); |
0c254d86 AK |
4606 | } |
4607 | ||
34b0368c PWJ |
4608 | /* save off EEPROM version number */ |
4609 | hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version); | |
4610 | ||
9a799d71 | 4611 | /* reset the hardware with the new settings */ |
c44ade9e JB |
4612 | hw->mac.ops.start_hw(hw); |
4613 | ||
9a799d71 | 4614 | netif_carrier_off(netdev); |
9a799d71 AK |
4615 | |
4616 | strcpy(netdev->name, "eth%d"); | |
4617 | err = register_netdev(netdev); | |
4618 | if (err) | |
4619 | goto err_register; | |
4620 | ||
5dd2d332 | 4621 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 4622 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd JC |
4623 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
4624 | /* always use CB2 mode, difference is masked | |
4625 | * in the CB driver */ | |
4626 | IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2); | |
4627 | ixgbe_setup_dca(adapter); | |
4628 | } | |
4629 | #endif | |
9a799d71 AK |
4630 | |
4631 | dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n"); | |
4632 | cards_found++; | |
4633 | return 0; | |
4634 | ||
4635 | err_register: | |
5eba3699 | 4636 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4637 | err_hw_init: |
4638 | err_sw_init: | |
021230d4 | 4639 | ixgbe_reset_interrupt_capability(adapter); |
9a799d71 | 4640 | err_eeprom: |
c4900be0 DS |
4641 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
4642 | del_timer_sync(&adapter->sfp_timer); | |
4643 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
4644 | cancel_work_sync(&adapter->multispeed_fiber_task); |
4645 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
4646 | iounmap(hw->hw_addr); |
4647 | err_ioremap: | |
4648 | free_netdev(netdev); | |
4649 | err_alloc_etherdev: | |
4650 | pci_release_regions(pdev); | |
4651 | err_pci_reg: | |
4652 | err_dma: | |
4653 | pci_disable_device(pdev); | |
4654 | return err; | |
4655 | } | |
4656 | ||
4657 | /** | |
4658 | * ixgbe_remove - Device Removal Routine | |
4659 | * @pdev: PCI device information struct | |
4660 | * | |
4661 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
4662 | * that it should release a PCI device. The could be caused by a | |
4663 | * Hot-Plug event, or because the driver is going to be removed from | |
4664 | * memory. | |
4665 | **/ | |
4666 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
4667 | { | |
4668 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4669 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6fabd715 | 4670 | int err; |
9a799d71 AK |
4671 | |
4672 | set_bit(__IXGBE_DOWN, &adapter->state); | |
c4900be0 DS |
4673 | /* clear the module not found bit to make sure the worker won't |
4674 | * reschedule | |
4675 | */ | |
4676 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
9a799d71 AK |
4677 | del_timer_sync(&adapter->watchdog_timer); |
4678 | ||
c4900be0 DS |
4679 | del_timer_sync(&adapter->sfp_timer); |
4680 | cancel_work_sync(&adapter->watchdog_task); | |
4681 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
4682 | cancel_work_sync(&adapter->multispeed_fiber_task); |
4683 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
4684 | flush_scheduled_work(); |
4685 | ||
5dd2d332 | 4686 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
4687 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
4688 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
4689 | dca_remove_requester(&pdev->dev); | |
4690 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
4691 | } | |
4692 | ||
4693 | #endif | |
c4900be0 DS |
4694 | if (netdev->reg_state == NETREG_REGISTERED) |
4695 | unregister_netdev(netdev); | |
9a799d71 | 4696 | |
021230d4 | 4697 | ixgbe_reset_interrupt_capability(adapter); |
5eba3699 | 4698 | |
021230d4 | 4699 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4700 | |
4701 | iounmap(adapter->hw.hw_addr); | |
4702 | pci_release_regions(pdev); | |
4703 | ||
021230d4 AV |
4704 | DPRINTK(PROBE, INFO, "complete\n"); |
4705 | kfree(adapter->tx_ring); | |
4706 | kfree(adapter->rx_ring); | |
4707 | ||
9a799d71 AK |
4708 | free_netdev(netdev); |
4709 | ||
6fabd715 PWJ |
4710 | err = pci_disable_pcie_error_reporting(pdev); |
4711 | if (err) | |
4712 | dev_err(&pdev->dev, | |
4713 | "pci_disable_pcie_error_reporting failed 0x%x\n", err); | |
4714 | ||
9a799d71 AK |
4715 | pci_disable_device(pdev); |
4716 | } | |
4717 | ||
4718 | /** | |
4719 | * ixgbe_io_error_detected - called when PCI error is detected | |
4720 | * @pdev: Pointer to PCI device | |
4721 | * @state: The current pci connection state | |
4722 | * | |
4723 | * This function is called after a PCI bus error affecting | |
4724 | * this device has been detected. | |
4725 | */ | |
4726 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
b4617240 | 4727 | pci_channel_state_t state) |
9a799d71 AK |
4728 | { |
4729 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 4730 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
4731 | |
4732 | netif_device_detach(netdev); | |
4733 | ||
4734 | if (netif_running(netdev)) | |
4735 | ixgbe_down(adapter); | |
4736 | pci_disable_device(pdev); | |
4737 | ||
b4617240 | 4738 | /* Request a slot reset. */ |
9a799d71 AK |
4739 | return PCI_ERS_RESULT_NEED_RESET; |
4740 | } | |
4741 | ||
4742 | /** | |
4743 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
4744 | * @pdev: Pointer to PCI device | |
4745 | * | |
4746 | * Restart the card from scratch, as if from a cold-boot. | |
4747 | */ | |
4748 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
4749 | { | |
4750 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 4751 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
6fabd715 PWJ |
4752 | pci_ers_result_t result; |
4753 | int err; | |
9a799d71 AK |
4754 | |
4755 | if (pci_enable_device(pdev)) { | |
4756 | DPRINTK(PROBE, ERR, | |
b4617240 | 4757 | "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
4758 | result = PCI_ERS_RESULT_DISCONNECT; |
4759 | } else { | |
4760 | pci_set_master(pdev); | |
4761 | pci_restore_state(pdev); | |
9a799d71 | 4762 | |
6fabd715 PWJ |
4763 | pci_enable_wake(pdev, PCI_D3hot, 0); |
4764 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
9a799d71 | 4765 | |
6fabd715 PWJ |
4766 | ixgbe_reset(adapter); |
4767 | ||
4768 | result = PCI_ERS_RESULT_RECOVERED; | |
4769 | } | |
4770 | ||
4771 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
4772 | if (err) { | |
4773 | dev_err(&pdev->dev, | |
4774 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err); | |
4775 | /* non-fatal, continue */ | |
4776 | } | |
9a799d71 | 4777 | |
6fabd715 | 4778 | return result; |
9a799d71 AK |
4779 | } |
4780 | ||
4781 | /** | |
4782 | * ixgbe_io_resume - called when traffic can start flowing again. | |
4783 | * @pdev: Pointer to PCI device | |
4784 | * | |
4785 | * This callback is called when the error recovery driver tells us that | |
4786 | * its OK to resume normal operation. | |
4787 | */ | |
4788 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
4789 | { | |
4790 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 4791 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
4792 | |
4793 | if (netif_running(netdev)) { | |
4794 | if (ixgbe_up(adapter)) { | |
4795 | DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n"); | |
4796 | return; | |
4797 | } | |
4798 | } | |
4799 | ||
4800 | netif_device_attach(netdev); | |
9a799d71 AK |
4801 | } |
4802 | ||
4803 | static struct pci_error_handlers ixgbe_err_handler = { | |
4804 | .error_detected = ixgbe_io_error_detected, | |
4805 | .slot_reset = ixgbe_io_slot_reset, | |
4806 | .resume = ixgbe_io_resume, | |
4807 | }; | |
4808 | ||
4809 | static struct pci_driver ixgbe_driver = { | |
4810 | .name = ixgbe_driver_name, | |
4811 | .id_table = ixgbe_pci_tbl, | |
4812 | .probe = ixgbe_probe, | |
4813 | .remove = __devexit_p(ixgbe_remove), | |
4814 | #ifdef CONFIG_PM | |
4815 | .suspend = ixgbe_suspend, | |
4816 | .resume = ixgbe_resume, | |
4817 | #endif | |
4818 | .shutdown = ixgbe_shutdown, | |
4819 | .err_handler = &ixgbe_err_handler | |
4820 | }; | |
4821 | ||
4822 | /** | |
4823 | * ixgbe_init_module - Driver Registration Routine | |
4824 | * | |
4825 | * ixgbe_init_module is the first routine called when the driver is | |
4826 | * loaded. All it does is register with the PCI subsystem. | |
4827 | **/ | |
4828 | static int __init ixgbe_init_module(void) | |
4829 | { | |
4830 | int ret; | |
4831 | printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name, | |
4832 | ixgbe_driver_string, ixgbe_driver_version); | |
4833 | ||
4834 | printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright); | |
4835 | ||
5dd2d332 | 4836 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 4837 | dca_register_notify(&dca_notifier); |
bd0362dd | 4838 | #endif |
5dd2d332 | 4839 | |
9a799d71 AK |
4840 | ret = pci_register_driver(&ixgbe_driver); |
4841 | return ret; | |
4842 | } | |
b4617240 | 4843 | |
9a799d71 AK |
4844 | module_init(ixgbe_init_module); |
4845 | ||
4846 | /** | |
4847 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
4848 | * | |
4849 | * ixgbe_exit_module is called just before the driver is removed | |
4850 | * from memory. | |
4851 | **/ | |
4852 | static void __exit ixgbe_exit_module(void) | |
4853 | { | |
5dd2d332 | 4854 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
4855 | dca_unregister_notify(&dca_notifier); |
4856 | #endif | |
9a799d71 AK |
4857 | pci_unregister_driver(&ixgbe_driver); |
4858 | } | |
bd0362dd | 4859 | |
5dd2d332 | 4860 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 4861 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
b4617240 | 4862 | void *p) |
bd0362dd JC |
4863 | { |
4864 | int ret_val; | |
4865 | ||
4866 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
b4617240 | 4867 | __ixgbe_notify_dca); |
bd0362dd JC |
4868 | |
4869 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
4870 | } | |
5dd2d332 | 4871 | #endif /* CONFIG_IXGBE_DCA */ |
bd0362dd | 4872 | |
9a799d71 AK |
4873 | module_exit(ixgbe_exit_module); |
4874 | ||
4875 | /* ixgbe_main.c */ |