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ixgbe: remove some redundant code in setting FCoE FIP filter
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
b4617240 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
92eb879f 55#define DRV_VERSION "2.0.62-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
312eb931
DS		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
112 board_82599 },
9a799d71
AK		 113
114 /* required last entry */
115 {0, }
116};
117MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
118
5dd2d332 119#ifdef CONFIG_IXGBE_DCA
bd0362dd 120static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 121 void *p);
bd0362dd
JC		 122static struct notifier_block dca_notifier = {
123 .notifier_call = ixgbe_notify_dca,
124 .next = NULL,
125 .priority = 0
126};
127#endif
128
1cdd1ec8
GR		 129#ifdef CONFIG_PCI_IOV
130static unsigned int max_vfs;
131module_param(max_vfs, uint, 0);
132MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
133 "per physical function");
134#endif /* CONFIG_PCI_IOV */
135
9a799d71
AK		 136MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
137MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
138MODULE_LICENSE("GPL");
139MODULE_VERSION(DRV_VERSION);
140
141#define DEFAULT_DEBUG_LEVEL_SHIFT 3
142
1cdd1ec8
GR		 143static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
144{
145 struct ixgbe_hw *hw = &adapter->hw;
146 u32 gcr;
147 u32 gpie;
148 u32 vmdctl;
149
150#ifdef CONFIG_PCI_IOV
151 /* disable iov and allow time for transactions to clear */
152 pci_disable_sriov(adapter->pdev);
153#endif
154
155 /* turn off device IOV mode */
156 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
157 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
158 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
159 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
160 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
161 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
162
163 /* set default pool back to 0 */
164 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
165 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
166 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
167
168 /* take a breather then clean up driver data */
169 msleep(100);
170 if (adapter->vfinfo)
171 kfree(adapter->vfinfo);
172 adapter->vfinfo = NULL;
173
174 adapter->num_vfs = 0;
175 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
176}
177
dcd79aeb
TI		 178struct ixgbe_reg_info {
179 u32 ofs;
180 char *name;
181};
182
183static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
184
185 /* General Registers */
186 {IXGBE_CTRL, "CTRL"},
187 {IXGBE_STATUS, "STATUS"},
188 {IXGBE_CTRL_EXT, "CTRL_EXT"},
189
190 /* Interrupt Registers */
191 {IXGBE_EICR, "EICR"},
192
193 /* RX Registers */
194 {IXGBE_SRRCTL(0), "SRRCTL"},
195 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
196 {IXGBE_RDLEN(0), "RDLEN"},
197 {IXGBE_RDH(0), "RDH"},
198 {IXGBE_RDT(0), "RDT"},
199 {IXGBE_RXDCTL(0), "RXDCTL"},
200 {IXGBE_RDBAL(0), "RDBAL"},
201 {IXGBE_RDBAH(0), "RDBAH"},
202
203 /* TX Registers */
204 {IXGBE_TDBAL(0), "TDBAL"},
205 {IXGBE_TDBAH(0), "TDBAH"},
206 {IXGBE_TDLEN(0), "TDLEN"},
207 {IXGBE_TDH(0), "TDH"},
208 {IXGBE_TDT(0), "TDT"},
209 {IXGBE_TXDCTL(0), "TXDCTL"},
210
211 /* List Terminator */
212 {}
213};
214
215
216/*
217 * ixgbe_regdump - register printout routine
218 */
219static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
220{
221 int i = 0, j = 0;
222 char rname[16];
223 u32 regs[64];
224
225 switch (reginfo->ofs) {
226 case IXGBE_SRRCTL(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
229 break;
230 case IXGBE_DCA_RXCTRL(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
233 break;
234 case IXGBE_RDLEN(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
237 break;
238 case IXGBE_RDH(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
241 break;
242 case IXGBE_RDT(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
245 break;
246 case IXGBE_RXDCTL(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
249 break;
250 case IXGBE_RDBAL(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
253 break;
254 case IXGBE_RDBAH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
257 break;
258 case IXGBE_TDBAL(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
261 break;
262 case IXGBE_TDBAH(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
265 break;
266 case IXGBE_TDLEN(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
269 break;
270 case IXGBE_TDH(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
273 break;
274 case IXGBE_TDT(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
277 break;
278 case IXGBE_TXDCTL(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
281 break;
282 default:
283 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
284 IXGBE_READ_REG(hw, reginfo->ofs));
285 return;
286 }
287
288 for (i = 0; i < 8; i++) {
289 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
290 printk(KERN_ERR "%-15s ", rname);
291 for (j = 0; j < 8; j++)
292 printk(KERN_CONT "%08x ", regs[i*8+j]);
293 printk(KERN_CONT "\n");
294 }
295
296}
297
298/*
299 * ixgbe_dump - Print registers, tx-rings and rx-rings
300 */
301static void ixgbe_dump(struct ixgbe_adapter *adapter)
302{
303 struct net_device *netdev = adapter->netdev;
304 struct ixgbe_hw *hw = &adapter->hw;
305 struct ixgbe_reg_info *reginfo;
306 int n = 0;
307 struct ixgbe_ring *tx_ring;
308 struct ixgbe_tx_buffer *tx_buffer_info;
309 union ixgbe_adv_tx_desc *tx_desc;
310 struct my_u0 { u64 a; u64 b; } *u0;
311 struct ixgbe_ring *rx_ring;
312 union ixgbe_adv_rx_desc *rx_desc;
313 struct ixgbe_rx_buffer *rx_buffer_info;
314 u32 staterr;
315 int i = 0;
316
317 if (!netif_msg_hw(adapter))
318 return;
319
320 /* Print netdevice Info */
321 if (netdev) {
322 dev_info(&adapter->pdev->dev, "Net device Info\n");
323 printk(KERN_INFO "Device Name state "
324 "trans_start last_rx\n");
325 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
326 netdev->name,
327 netdev->state,
328 netdev->trans_start,
329 netdev->last_rx);
330 }
331
332 /* Print Registers */
333 dev_info(&adapter->pdev->dev, "Register Dump\n");
334 printk(KERN_INFO " Register Name Value\n");
335 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
336 reginfo->name; reginfo++) {
337 ixgbe_regdump(hw, reginfo);
338 }
339
340 /* Print TX Ring Summary */
341 if (!netdev || !netif_running(netdev))
342 goto exit;
343
344 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
345 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ] "
346 "leng ntw timestamp\n");
347 for (n = 0; n < adapter->num_tx_queues; n++) {
348 tx_ring = adapter->tx_ring[n];
349 tx_buffer_info =
350 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
351 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
352 n, tx_ring->next_to_use, tx_ring->next_to_clean,
353 (u64)tx_buffer_info->dma,
354 tx_buffer_info->length,
355 tx_buffer_info->next_to_watch,
356 (u64)tx_buffer_info->time_stamp);
357 }
358
359 /* Print TX Rings */
360 if (!netif_msg_tx_done(adapter))
361 goto rx_ring_summary;
362
363 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
364
365 /* Transmit Descriptor Formats
366 *
367 * Advanced Transmit Descriptor
368 * +--------------------------------------------------------------+
369 * 0 | Buffer Address [63:0] |
370 * +--------------------------------------------------------------+
371 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
372 * +--------------------------------------------------------------+
373 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
374 */
375
376 for (n = 0; n < adapter->num_tx_queues; n++) {
377 tx_ring = adapter->tx_ring[n];
378 printk(KERN_INFO "------------------------------------\n");
379 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
380 printk(KERN_INFO "------------------------------------\n");
381 printk(KERN_INFO "T [desc] [address 63:0 ] "
382 "[PlPOIdStDDt Ln] [bi->dma ] "
383 "leng ntw timestamp bi->skb\n");
384
385 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
386 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
387 tx_buffer_info = &tx_ring->tx_buffer_info[i];
388 u0 = (struct my_u0 *)tx_desc;
389 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
390 " %04X %3X %016llX %p", i,
391 le64_to_cpu(u0->a),
392 le64_to_cpu(u0->b),
393 (u64)tx_buffer_info->dma,
394 tx_buffer_info->length,
395 tx_buffer_info->next_to_watch,
396 (u64)tx_buffer_info->time_stamp,
397 tx_buffer_info->skb);
398 if (i == tx_ring->next_to_use &&
399 i == tx_ring->next_to_clean)
400 printk(KERN_CONT " NTC/U\n");
401 else if (i == tx_ring->next_to_use)
402 printk(KERN_CONT " NTU\n");
403 else if (i == tx_ring->next_to_clean)
404 printk(KERN_CONT " NTC\n");
405 else
406 printk(KERN_CONT "\n");
407
408 if (netif_msg_pktdata(adapter) &&
409 tx_buffer_info->dma != 0)
410 print_hex_dump(KERN_INFO, "",
411 DUMP_PREFIX_ADDRESS, 16, 1,
412 phys_to_virt(tx_buffer_info->dma),
413 tx_buffer_info->length, true);
414 }
415 }
416
417 /* Print RX Rings Summary */
418rx_ring_summary:
419 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
420 printk(KERN_INFO "Queue [NTU] [NTC]\n");
421 for (n = 0; n < adapter->num_rx_queues; n++) {
422 rx_ring = adapter->rx_ring[n];
423 printk(KERN_INFO "%5d %5X %5X\n", n,
424 rx_ring->next_to_use, rx_ring->next_to_clean);
425 }
426
427 /* Print RX Rings */
428 if (!netif_msg_rx_status(adapter))
429 goto exit;
430
431 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
432
433 /* Advanced Receive Descriptor (Read) Format
434 * 63 1 0
435 * +-----------------------------------------------------+
436 * 0 | Packet Buffer Address [63:1] |A0/NSE|
437 * +----------------------------------------------+------+
438 * 8 | Header Buffer Address [63:1] | DD |
439 * +-----------------------------------------------------+
440 *
441 *
442 * Advanced Receive Descriptor (Write-Back) Format
443 *
444 * 63 48 47 32 31 30 21 20 16 15 4 3 0
445 * +------------------------------------------------------+
446 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
447 * | Checksum Ident | | | | Type | Type |
448 * +------------------------------------------------------+
449 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
450 * +------------------------------------------------------+
451 * 63 48 47 32 31 20 19 0
452 */
453 for (n = 0; n < adapter->num_rx_queues; n++) {
454 rx_ring = adapter->rx_ring[n];
455 printk(KERN_INFO "------------------------------------\n");
456 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
457 printk(KERN_INFO "------------------------------------\n");
458 printk(KERN_INFO "R [desc] [ PktBuf A0] "
459 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
460 "<-- Adv Rx Read format\n");
461 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
462 "[vl er S cks ln] ---------------- [bi->skb] "
463 "<-- Adv Rx Write-Back format\n");
464
465 for (i = 0; i < rx_ring->count; i++) {
466 rx_buffer_info = &rx_ring->rx_buffer_info[i];
467 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
468 u0 = (struct my_u0 *)rx_desc;
469 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
470 if (staterr & IXGBE_RXD_STAT_DD) {
471 /* Descriptor Done */
472 printk(KERN_INFO "RWB[0x%03X] %016llX "
473 "%016llX ---------------- %p", i,
474 le64_to_cpu(u0->a),
475 le64_to_cpu(u0->b),
476 rx_buffer_info->skb);
477 } else {
478 printk(KERN_INFO "R [0x%03X] %016llX "
479 "%016llX %016llX %p", i,
480 le64_to_cpu(u0->a),
481 le64_to_cpu(u0->b),
482 (u64)rx_buffer_info->dma,
483 rx_buffer_info->skb);
484
485 if (netif_msg_pktdata(adapter)) {
486 print_hex_dump(KERN_INFO, "",
487 DUMP_PREFIX_ADDRESS, 16, 1,
488 phys_to_virt(rx_buffer_info->dma),
489 rx_ring->rx_buf_len, true);
490
491 if (rx_ring->rx_buf_len
492 < IXGBE_RXBUFFER_2048)
493 print_hex_dump(KERN_INFO, "",
494 DUMP_PREFIX_ADDRESS, 16, 1,
495 phys_to_virt(
496 rx_buffer_info->page_dma +
497 rx_buffer_info->page_offset
498 ),
499 PAGE_SIZE/2, true);
500 }
501 }
502
503 if (i == rx_ring->next_to_use)
504 printk(KERN_CONT " NTU\n");
505 else if (i == rx_ring->next_to_clean)
506 printk(KERN_CONT " NTC\n");
507 else
508 printk(KERN_CONT "\n");
509
510 }
511 }
512
513exit:
514 return;
515}
516
5eba3699
AV		 517static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
518{
519 u32 ctrl_ext;
520
521 /* Let firmware take over control of h/w */
522 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
523 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 524 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 525}
526
527static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
528{
529 u32 ctrl_ext;
530
531 /* Let firmware know the driver has taken over */
532 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
533 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 534 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 535}
9a799d71 536
e8e26350
PW		 537/*
538 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
539 * @adapter: pointer to adapter struct
540 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
541 * @queue: queue to map the corresponding interrupt to
542 * @msix_vector: the vector to map to the corresponding queue
543 *
544 */
545static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
546 u8 queue, u8 msix_vector)
9a799d71
AK		 547{
548 u32 ivar, index;
e8e26350
PW		 549 struct ixgbe_hw *hw = &adapter->hw;
550 switch (hw->mac.type) {
551 case ixgbe_mac_82598EB:
552 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
553 if (direction == -1)
554 direction = 0;
555 index = (((direction * 64) + queue) >> 2) & 0x1F;
556 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
557 ivar &= ~(0xFF << (8 * (queue & 0x3)));
558 ivar |= (msix_vector << (8 * (queue & 0x3)));
559 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
560 break;
561 case ixgbe_mac_82599EB:
562 if (direction == -1) {
563 /* other causes */
564 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
565 index = ((queue & 1) * 8);
566 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
567 ivar &= ~(0xFF << index);
568 ivar |= (msix_vector << index);
569 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
570 break;
571 } else {
572 /* tx or rx causes */
573 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
574 index = ((16 * (queue & 1)) + (8 * direction));
575 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
576 ivar &= ~(0xFF << index);
577 ivar |= (msix_vector << index);
578 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
579 break;
580 }
581 default:
582 break;
583 }
9a799d71
AK		 584}
585
fe49f04a
AD		 586static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
587 u64 qmask)
588{
589 u32 mask;
590
591 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
592 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
593 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
594 } else {
595 mask = (qmask & 0xFFFFFFFF);
596 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
597 mask = (qmask >> 32);
598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
599 }
600}
601
9a799d71 602static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 603 struct ixgbe_tx_buffer
604 *tx_buffer_info)
9a799d71 605{
e5a43549
AD		 606 if (tx_buffer_info->dma) {
607 if (tx_buffer_info->mapped_as_page)
1b507730 608 dma_unmap_page(&adapter->pdev->dev,
e5a43549
AD		 609 tx_buffer_info->dma,
610 tx_buffer_info->length,
1b507730 611 DMA_TO_DEVICE);
e5a43549 612 else
1b507730 613 dma_unmap_single(&adapter->pdev->dev,
e5a43549
AD		 614 tx_buffer_info->dma,
615 tx_buffer_info->length,
1b507730 616 DMA_TO_DEVICE);
e5a43549
AD		 617 tx_buffer_info->dma = 0;
618 }
9a799d71
AK		 619 if (tx_buffer_info->skb) {
620 dev_kfree_skb_any(tx_buffer_info->skb);
621 tx_buffer_info->skb = NULL;
622 }
44df32c5 623 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 624 /* tx_buffer_info must be completely set up in the transmit path */
625}
626
26f23d82
YZ		 627/**
628 * ixgbe_tx_is_paused - check if the tx ring is paused
629 * @adapter: the ixgbe adapter
630 * @tx_ring: the corresponding tx_ring
631 *
632 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
633 * corresponding TC of this tx_ring when checking TFCS.
634 *
635 * Returns : true if paused
636 */
637static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
638 struct ixgbe_ring *tx_ring)
639{
26f23d82
YZ		 640 u32 txoff = IXGBE_TFCS_TXOFF;
641
642#ifdef CONFIG_IXGBE_DCB
643 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
30b76832 644 int tc;
26f23d82
YZ		 645 int reg_idx = tx_ring->reg_idx;
646 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
647
6837e895
PW		 648 switch (adapter->hw.mac.type) {
649 case ixgbe_mac_82598EB:
26f23d82
YZ		 650 tc = reg_idx >> 2;
651 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 652 break;
653 case ixgbe_mac_82599EB:
26f23d82
YZ		 654 tc = 0;
655 txoff = IXGBE_TFCS_TXOFF;
656 if (dcb_i == 8) {
657 /* TC0, TC1 */
658 tc = reg_idx >> 5;
659 if (tc == 2) /* TC2, TC3 */
660 tc += (reg_idx - 64) >> 4;
661 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
662 tc += 1 + ((reg_idx - 96) >> 3);
663 } else if (dcb_i == 4) {
664 /* TC0, TC1 */
665 tc = reg_idx >> 6;
666 if (tc == 1) {
667 tc += (reg_idx - 64) >> 5;
668 if (tc == 2) /* TC2, TC3 */
669 tc += (reg_idx - 96) >> 4;
670 }
671 }
6837e895
PW		 672 break;
673 default:
674 tc = 0;
26f23d82
YZ		 675 }
676 txoff <<= tc;
677 }
678#endif
679 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
680}
681
9a799d71 682static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 683 struct ixgbe_ring *tx_ring,
684 unsigned int eop)
9a799d71 685{
e01c31a5 686 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 687
9a799d71 688 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 689 * check with the clearing of time_stamp and movement of eop */
9a799d71 690 adapter->detect_tx_hung = false;
44df32c5 691 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 692 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
26f23d82 693 !ixgbe_tx_is_paused(adapter, tx_ring)) {
9a799d71 694 /* detected Tx unit hang */
e01c31a5
JB		 695 union ixgbe_adv_tx_desc *tx_desc;
696 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 697 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 698 " Tx Queue <%d>\n"
699 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 700 " next_to_use <%x>\n"
701 " next_to_clean <%x>\n"
702 "tx_buffer_info[next_to_clean]\n"
703 " time_stamp <%lx>\n"
e01c31a5
JB		 704 " jiffies <%lx>\n",
705 tx_ring->queue_index,
44df32c5
AD		 706 IXGBE_READ_REG(hw, tx_ring->head),
707 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 708 tx_ring->next_to_use, eop,
709 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 710 return true;
711 }
712
713 return false;
714}
715
b4617240
PW		 716#define IXGBE_MAX_TXD_PWR 14
717#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 718
719/* Tx Descriptors needed, worst case */
720#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
721 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
722#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 723 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 724
e01c31a5
JB		 725static void ixgbe_tx_timeout(struct net_device *netdev);
726
9a799d71
AK		 727/**
728 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 729 * @q_vector: structure containing interrupt and ring information
e01c31a5 730 * @tx_ring: tx ring to clean
9a799d71 731 **/
fe49f04a 732static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 733 struct ixgbe_ring *tx_ring)
9a799d71 734{
fe49f04a 735 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 736 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 737 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
738 struct ixgbe_tx_buffer *tx_buffer_info;
739 unsigned int i, eop, count = 0;
e01c31a5 740 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 741
742 i = tx_ring->next_to_clean;
12207e49
PWJ		 743 eop = tx_ring->tx_buffer_info[i].next_to_watch;
744 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
745
746 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 747 (count < tx_ring->work_limit)) {
12207e49
PWJ		 748 bool cleaned = false;
749 for ( ; !cleaned; count++) {
750 struct sk_buff *skb;
9a799d71
AK		 751 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
752 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 753 cleaned = (i == eop);
e01c31a5 754 skb = tx_buffer_info->skb;
9a799d71 755
12207e49 756 if (cleaned && skb) {
e092be60 757 unsigned int segs, bytecount;
3d8fd385 758 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 759
760 /* gso_segs is currently only valid for tcp */
e092be60 761 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 762#ifdef IXGBE_FCOE
763 /* adjust for FCoE Sequence Offload */
764 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
765 && (skb->protocol == htons(ETH_P_FCOE)) &&
766 skb_is_gso(skb)) {
767 hlen = skb_transport_offset(skb) +
768 sizeof(struct fc_frame_header) +
769 sizeof(struct fcoe_crc_eof);
770 segs = DIV_ROUND_UP(skb->len - hlen,
771 skb_shinfo(skb)->gso_size);
772 }
773#endif /* IXGBE_FCOE */
e092be60 774 /* multiply data chunks by size of headers */
3d8fd385 775 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 776 total_packets += segs;
777 total_bytes += bytecount;
e092be60 778 }
e01c31a5 779
9a799d71 780 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 781 tx_buffer_info);
9a799d71 782
12207e49
PWJ		 783 tx_desc->wb.status = 0;
784
9a799d71
AK		 785 i++;
786 if (i == tx_ring->count)
787 i = 0;
e01c31a5 788 }
12207e49
PWJ		 789
790 eop = tx_ring->tx_buffer_info[i].next_to_watch;
791 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
792 }
793
9a799d71
AK		 794 tx_ring->next_to_clean = i;
795
e092be60 796#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 797 if (unlikely(count && netif_carrier_ok(netdev) &&
798 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 799 /* Make sure that anybody stopping the queue after this
800 * sees the new next_to_clean.
801 */
802 smp_mb();
30eba97a
AV		 803 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
804 !test_bit(__IXGBE_DOWN, &adapter->state)) {
805 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 806 ++tx_ring->restart_queue;
30eba97a 807 }
e092be60 808 }
9a799d71 809
e01c31a5
JB		 810 if (adapter->detect_tx_hung) {
811 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
812 /* schedule immediate reset if we believe we hung */
813 DPRINTK(PROBE, INFO,
814 "tx hang %d detected, resetting adapter\n",
815 adapter->tx_timeout_count + 1);
816 ixgbe_tx_timeout(adapter->netdev);
817 }
818 }
9a799d71 819
e01c31a5 820 /* re-arm the interrupt */
fe49f04a
AD		 821 if (count >= tx_ring->work_limit)
822 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 823
e01c31a5
JB		 824 tx_ring->total_bytes += total_bytes;
825 tx_ring->total_packets += total_packets;
e01c31a5 826 tx_ring->stats.packets += total_packets;
12207e49 827 tx_ring->stats.bytes += total_bytes;
9a1a69ad 828 return (count < tx_ring->work_limit);
9a799d71
AK		 829}
830
5dd2d332 831#ifdef CONFIG_IXGBE_DCA
bd0362dd 832static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 833 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 834{
835 u32 rxctrl;
836 int cpu = get_cpu();
4a0b9ca0 837 int q = rx_ring->reg_idx;
bd0362dd 838
3a581073 839 if (rx_ring->cpu != cpu) {
bd0362dd 840 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 841 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
842 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
843 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
844 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
845 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
846 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
847 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
848 }
bd0362dd
JC		 849 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
850 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 851 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
852 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 853 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 854 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 855 rx_ring->cpu = cpu;
bd0362dd
JC		 856 }
857 put_cpu();
858}
859
860static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 861 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 862{
863 u32 txctrl;
864 int cpu = get_cpu();
4a0b9ca0 865 int q = tx_ring->reg_idx;
ee5f784a 866 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 867
3a581073 868 if (tx_ring->cpu != cpu) {
e8e26350 869 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 870 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 871 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
872 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 873 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
874 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 875 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 876 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 877 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
878 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 879 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
880 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
881 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 882 }
3a581073 883 tx_ring->cpu = cpu;
bd0362dd
JC		 884 }
885 put_cpu();
886}
887
888static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
889{
890 int i;
891
892 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
893 return;
894
e35ec126
AD		 895 /* always use CB2 mode, difference is masked in the CB driver */
896 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
897
bd0362dd 898 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 899 adapter->tx_ring[i]->cpu = -1;
900 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 901 }
902 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 903 adapter->rx_ring[i]->cpu = -1;
904 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 905 }
906}
907
908static int __ixgbe_notify_dca(struct device *dev, void *data)
909{
910 struct net_device *netdev = dev_get_drvdata(dev);
911 struct ixgbe_adapter *adapter = netdev_priv(netdev);
912 unsigned long event = *(unsigned long *)data;
913
914 switch (event) {
915 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 916 /* if we're already enabled, don't do it again */
917 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
918 break;
652f093f 919 if (dca_add_requester(dev) == 0) {
96b0e0f6 920 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 921 ixgbe_setup_dca(adapter);
922 break;
923 }
924 /* Fall Through since DCA is disabled. */
925 case DCA_PROVIDER_REMOVE:
926 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
927 dca_remove_requester(dev);
928 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
929 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
930 }
931 break;
932 }
933
652f093f 934 return 0;
bd0362dd
JC		 935}
936
5dd2d332 937#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 938/**
939 * ixgbe_receive_skb - Send a completed packet up the stack
940 * @adapter: board private structure
941 * @skb: packet to send up
177db6ff
MC		 942 * @status: hardware indication of status of receive
943 * @rx_ring: rx descriptor ring (for a specific queue) to setup
944 * @rx_desc: rx descriptor
9a799d71 945 **/
78b6f4ce 946static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 947 struct sk_buff *skb, u8 status,
fdaff1ce 948 struct ixgbe_ring *ring,
177db6ff 949 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 950{
78b6f4ce
HX		 951 struct ixgbe_adapter *adapter = q_vector->adapter;
952 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 953 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
954 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 955
fdaff1ce 956 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 957 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 958 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 959 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 960 else
78b6f4ce 961 napi_gro_receive(napi, skb);
177db6ff 962 } else {
8a62babf 963 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 964 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
965 else
966 netif_rx(skb);
9a799d71
AK		 967 }
968}
969
e59bd25d
AV		 970/**
971 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
972 * @adapter: address of board private structure
973 * @status_err: hardware indication of status of receive
974 * @skb: skb currently being received and modified
975 **/
9a799d71 976static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 977 union ixgbe_adv_rx_desc *rx_desc,
978 struct sk_buff *skb)
9a799d71 979{
8bae1b2b
DS		 980 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
981
9a799d71
AK		 982 skb->ip_summed = CHECKSUM_NONE;
983
712744be
JB		 984 /* Rx csum disabled */
985 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 986 return;
e59bd25d
AV		 987
988 /* if IP and error */
989 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
990 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 991 adapter->hw_csum_rx_error++;
992 return;
993 }
e59bd25d
AV		 994
995 if (!(status_err & IXGBE_RXD_STAT_L4CS))
996 return;
997
998 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 999 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1000
1001 /*
1002 * 82599 errata, UDP frames with a 0 checksum can be marked as
1003 * checksum errors.
1004 */
1005 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1006 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1007 return;
1008
e59bd25d
AV		 1009 adapter->hw_csum_rx_error++;
1010 return;
1011 }
1012
9a799d71 1013 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1014 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1015}
1016
e8e26350
PW		 1017static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1018 struct ixgbe_ring *rx_ring, u32 val)
1019{
1020 /*
1021 * Force memory writes to complete before letting h/w
1022 * know there are new descriptors to fetch. (Only
1023 * applicable for weak-ordered memory model archs,
1024 * such as IA-64).
1025 */
1026 wmb();
1027 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1028}
1029
9a799d71
AK		 1030/**
1031 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1032 * @adapter: address of board private structure
1033 **/
1034static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 1035 struct ixgbe_ring *rx_ring,
1036 int cleaned_count)
9a799d71 1037{
9a799d71
AK		 1038 struct pci_dev *pdev = adapter->pdev;
1039 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1040 struct ixgbe_rx_buffer *bi;
9a799d71 1041 unsigned int i;
9a799d71
AK		 1042
1043 i = rx_ring->next_to_use;
3a581073 1044 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1045
1046 while (cleaned_count--) {
1047 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1048
762f4c57 1049 if (!bi->page_dma &&
6e455b89 1050 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 1051 if (!bi->page) {
762f4c57
JB		 1052 bi->page = alloc_page(GFP_ATOMIC);
1053 if (!bi->page) {
1054 adapter->alloc_rx_page_failed++;
1055 goto no_buffers;
1056 }
1057 bi->page_offset = 0;
1058 } else {
1059 /* use a half page if we're re-using */
1060 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 1061 }
762f4c57 1062
1b507730 1063 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
762f4c57
JB		 1064 bi->page_offset,
1065 (PAGE_SIZE / 2),
1b507730 1066 DMA_FROM_DEVICE);
9a799d71
AK		 1067 }
1068
3a581073 1069 if (!bi->skb) {
5ecc3614 1070 struct sk_buff *skb;
7ca3bc58
JB		 1071 /* netdev_alloc_skb reserves 32 bytes up front!! */
1072 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
1073 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 1074
1075 if (!skb) {
1076 adapter->alloc_rx_buff_failed++;
1077 goto no_buffers;
1078 }
1079
7ca3bc58
JB		 1080 /* advance the data pointer to the next cache line */
1081 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
1082 - skb->data));
1083
3a581073 1084 bi->skb = skb;
1b507730 1085 bi->dma = dma_map_single(&pdev->dev, skb->data,
4f57ca6e 1086 rx_ring->rx_buf_len,
1b507730 1087 DMA_FROM_DEVICE);
9a799d71
AK		 1088 }
1089 /* Refresh the desc even if buffer_addrs didn't change because
1090 * each write-back erases this info. */
6e455b89 1091 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 1092 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1093 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1094 } else {
3a581073 1095 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 1096 }
1097
1098 i++;
1099 if (i == rx_ring->count)
1100 i = 0;
3a581073 1101 bi = &rx_ring->rx_buffer_info[i];
9a799d71 1102 }
7c6e0a43 1103
9a799d71
AK		 1104no_buffers:
1105 if (rx_ring->next_to_use != i) {
1106 rx_ring->next_to_use = i;
1107 if (i-- == 0)
1108 i = (rx_ring->count - 1);
1109
e8e26350 1110 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 1111 }
1112}
1113
7c6e0a43
JB		 1114static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1115{
1116 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1117}
1118
1119static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1120{
1121 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1122}
1123
f8212f97
AD		 1124static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1125{
1126 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1127 IXGBE_RXDADV_RSCCNT_MASK) >>
1128 IXGBE_RXDADV_RSCCNT_SHIFT;
1129}
1130
1131/**
1132 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1133 * @skb: pointer to the last skb in the rsc queue
94b982b2 1134 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 1135 *
1136 * This function changes a queue full of hw rsc buffers into a completed
1137 * packet. It uses the ->prev pointers to find the first packet and then
1138 * turns it into the frag list owner.
1139 **/
94b982b2
MC		 1140static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1141 u64 *count)
f8212f97
AD		 1142{
1143 unsigned int frag_list_size = 0;
1144
1145 while (skb->prev) {
1146 struct sk_buff *prev = skb->prev;
1147 frag_list_size += skb->len;
1148 skb->prev = NULL;
1149 skb = prev;
94b982b2 1150 *count += 1;
f8212f97
AD		 1151 }
1152
1153 skb_shinfo(skb)->frag_list = skb->next;
1154 skb->next = NULL;
1155 skb->len += frag_list_size;
1156 skb->data_len += frag_list_size;
1157 skb->truesize += frag_list_size;
1158 return skb;
1159}
1160
43634e82
MC		 1161struct ixgbe_rsc_cb {
1162 dma_addr_t dma;
e8171aaa 1163 bool delay_unmap;
43634e82
MC		 1164};
1165
1166#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1167
78b6f4ce 1168static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 1169 struct ixgbe_ring *rx_ring,
1170 int *work_done, int work_to_do)
9a799d71 1171{
78b6f4ce 1172 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 1173 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1174 struct pci_dev *pdev = adapter->pdev;
1175 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1176 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1177 struct sk_buff *skb;
f8212f97 1178 unsigned int i, rsc_count = 0;
7c6e0a43 1179 u32 len, staterr;
177db6ff
MC		 1180 u16 hdr_info;
1181 bool cleaned = false;
9a799d71 1182 int cleaned_count = 0;
d2f4fbe2 1183 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 1184#ifdef IXGBE_FCOE
1185 int ddp_bytes = 0;
1186#endif /* IXGBE_FCOE */
9a799d71
AK		 1187
1188 i = rx_ring->next_to_clean;
9a799d71
AK		 1189 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1190 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1191 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1192
1193 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1194 u32 upper_len = 0;
9a799d71
AK		 1195 if (*work_done >= work_to_do)
1196 break;
1197 (*work_done)++;
1198
3c945e5b 1199 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 1200 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 1201 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1202 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 1203 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71 1204 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
0b746e08
SN		 1205 if ((len > IXGBE_RX_HDR_SIZE) ||
1206 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1207 len = IXGBE_RX_HDR_SIZE;
7c6e0a43 1208 } else {
9a799d71 1209 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 1210 }
9a799d71
AK		 1211
1212 cleaned = true;
1213 skb = rx_buffer_info->skb;
7ca3bc58 1214 prefetch(skb->data);
9a799d71
AK		 1215 rx_buffer_info->skb = NULL;
1216
21fa4e66 1217 if (rx_buffer_info->dma) {
43634e82
MC		 1218 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1219 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
e8171aaa 1220 (!(skb->prev))) {
43634e82
MC		 1221 /*
1222 * When HWRSC is enabled, delay unmapping
1223 * of the first packet. It carries the
1224 * header information, HW may still
1225 * access the header after the writeback.
1226 * Only unmap it when EOP is reached
1227 */
e8171aaa 1228 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1229 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1230 } else {
1b507730 1231 dma_unmap_single(&pdev->dev,
e8171aaa 1232 rx_buffer_info->dma,
43634e82 1233 rx_ring->rx_buf_len,
e8171aaa
MC		 1234 DMA_FROM_DEVICE);
1235 }
4f57ca6e 1236 rx_buffer_info->dma = 0;
9a799d71
AK		 1237 skb_put(skb, len);
1238 }
1239
1240 if (upper_len) {
1b507730
NN		 1241 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1242 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9a799d71
AK		 1243 rx_buffer_info->page_dma = 0;
1244 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 1245 rx_buffer_info->page,
1246 rx_buffer_info->page_offset,
1247 upper_len);
1248
1249 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1250 (page_count(rx_buffer_info->page) != 1))
1251 rx_buffer_info->page = NULL;
1252 else
1253 get_page(rx_buffer_info->page);
9a799d71
AK		 1254
1255 skb->len += upper_len;
1256 skb->data_len += upper_len;
1257 skb->truesize += upper_len;
1258 }
1259
1260 i++;
1261 if (i == rx_ring->count)
1262 i = 0;
9a799d71
AK		 1263
1264 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1265 prefetch(next_rxd);
9a799d71 1266 cleaned_count++;
f8212f97 1267
0c19d6af 1268 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 1269 rsc_count = ixgbe_get_rsc_count(rx_desc);
1270
1271 if (rsc_count) {
1272 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1273 IXGBE_RXDADV_NEXTP_SHIFT;
1274 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1275 } else {
1276 next_buffer = &rx_ring->rx_buffer_info[i];
1277 }
1278
9a799d71 1279 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 1280 if (skb->prev)
94b982b2
MC		 1281 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1282 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
e8171aaa 1283 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1b507730
NN		 1284 dma_unmap_single(&pdev->dev,
1285 IXGBE_RSC_CB(skb)->dma,
43634e82 1286 rx_ring->rx_buf_len,
1b507730 1287 DMA_FROM_DEVICE);
fd3686a8 1288 IXGBE_RSC_CB(skb)->dma = 0;
e8171aaa 1289 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 1290 }
94b982b2
MC		 1291 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1292 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1293 else
1294 rx_ring->rsc_count++;
1295 rx_ring->rsc_flush++;
1296 }
9a799d71
AK		 1297 rx_ring->stats.packets++;
1298 rx_ring->stats.bytes += skb->len;
1299 } else {
6e455b89 1300 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 1301 rx_buffer_info->skb = next_buffer->skb;
1302 rx_buffer_info->dma = next_buffer->dma;
1303 next_buffer->skb = skb;
1304 next_buffer->dma = 0;
1305 } else {
1306 skb->next = next_buffer->skb;
1307 skb->next->prev = skb;
1308 }
7ca3bc58 1309 rx_ring->non_eop_descs++;
9a799d71
AK		 1310 goto next_desc;
1311 }
1312
1313 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1314 dev_kfree_skb_irq(skb);
1315 goto next_desc;
1316 }
1317
8bae1b2b 1318 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1319
1320 /* probably a little skewed due to removing CRC */
1321 total_rx_bytes += skb->len;
1322 total_rx_packets++;
1323
74ce8dd2 1324 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 1325#ifdef IXGBE_FCOE
1326 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1327 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1328 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1329 if (!ddp_bytes)
332d4a7d 1330 goto next_desc;
3d8fd385 1331 }
332d4a7d 1332#endif /* IXGBE_FCOE */
fdaff1ce 1333 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1334
1335next_desc:
1336 rx_desc->wb.upper.status_error = 0;
1337
1338 /* return some buffers to hardware, one at a time is too slow */
1339 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1340 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1341 cleaned_count = 0;
1342 }
1343
1344 /* use prefetched values */
1345 rx_desc = next_rxd;
f8212f97 1346 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1347
1348 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1349 }
1350
9a799d71
AK		 1351 rx_ring->next_to_clean = i;
1352 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1353
1354 if (cleaned_count)
1355 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1356
3d8fd385
YZ		 1357#ifdef IXGBE_FCOE
1358 /* include DDPed FCoE data */
1359 if (ddp_bytes > 0) {
1360 unsigned int mss;
1361
1362 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1363 sizeof(struct fc_frame_header) -
1364 sizeof(struct fcoe_crc_eof);
1365 if (mss > 512)
1366 mss &= ~511;
1367 total_rx_bytes += ddp_bytes;
1368 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1369 }
1370#endif /* IXGBE_FCOE */
1371
f494e8fa
AV		 1372 rx_ring->total_packets += total_rx_packets;
1373 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 1374 netdev->stats.rx_bytes += total_rx_bytes;
1375 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 1376
9a799d71
AK		 1377 return cleaned;
1378}
1379
021230d4 1380static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1381/**
1382 * ixgbe_configure_msix - Configure MSI-X hardware
1383 * @adapter: board private structure
1384 *
1385 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1386 * interrupts.
1387 **/
1388static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1389{
021230d4
AV		 1390 struct ixgbe_q_vector *q_vector;
1391 int i, j, q_vectors, v_idx, r_idx;
1392 u32 mask;
9a799d71 1393
021230d4 1394 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1395
4df10466
JB		 1396 /*
1397 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1398 * corresponding register.
1399 */
1400 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1401 q_vector = adapter->q_vector[v_idx];
984b3f57 1402 /* XXX for_each_set_bit(...) */
021230d4 1403 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 1404 adapter->num_rx_queues);
021230d4
AV		 1405
1406 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1407 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1408 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1409 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 1410 adapter->num_rx_queues,
1411 r_idx + 1);
021230d4
AV		 1412 }
1413 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 1414 adapter->num_tx_queues);
021230d4
AV		 1415
1416 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1417 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1418 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1419 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 1420 adapter->num_tx_queues,
1421 r_idx + 1);
021230d4
AV		 1422 }
1423
021230d4 1424 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1425 /* tx only */
1426 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1427 else if (q_vector->rxr_count)
f7554a2b
NS		 1428 /* rx or mixed */
1429 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1430
fe49f04a 1431 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1432 }
1433
e8e26350
PW		 1434 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1435 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1436 v_idx);
1437 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1438 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1439 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1440
41fb9248 1441 /* set up to autoclear timer, and the vectors */
021230d4 1442 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1443 if (adapter->num_vfs)
1444 mask &= ~(IXGBE_EIMS_OTHER |
1445 IXGBE_EIMS_MAILBOX |
1446 IXGBE_EIMS_LSC);
1447 else
1448 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1449 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1450}
1451
f494e8fa
AV		 1452enum latency_range {
1453 lowest_latency = 0,
1454 low_latency = 1,
1455 bulk_latency = 2,
1456 latency_invalid = 255
1457};
1458
1459/**
1460 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1461 * @adapter: pointer to adapter
1462 * @eitr: eitr setting (ints per sec) to give last timeslice
1463 * @itr_setting: current throttle rate in ints/second
1464 * @packets: the number of packets during this measurement interval
1465 * @bytes: the number of bytes during this measurement interval
1466 *
1467 * Stores a new ITR value based on packets and byte
1468 * counts during the last interrupt. The advantage of per interrupt
1469 * computation is faster updates and more accurate ITR for the current
1470 * traffic pattern. Constants in this function were computed
1471 * based on theoretical maximum wire speed and thresholds were set based
1472 * on testing data as well as attempting to minimize response time
1473 * while increasing bulk throughput.
1474 * this functionality is controlled by the InterruptThrottleRate module
1475 * parameter (see ixgbe_param.c)
1476 **/
1477static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1478 u32 eitr, u8 itr_setting,
1479 int packets, int bytes)
f494e8fa
AV		 1480{
1481 unsigned int retval = itr_setting;
1482 u32 timepassed_us;
1483 u64 bytes_perint;
1484
1485 if (packets == 0)
1486 goto update_itr_done;
1487
1488
1489 /* simple throttlerate management
1490 * 0-20MB/s lowest (100000 ints/s)
1491 * 20-100MB/s low (20000 ints/s)
1492 * 100-1249MB/s bulk (8000 ints/s)
1493 */
1494 /* what was last interrupt timeslice? */
1495 timepassed_us = 1000000/eitr;
1496 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1497
1498 switch (itr_setting) {
1499 case lowest_latency:
1500 if (bytes_perint > adapter->eitr_low)
1501 retval = low_latency;
1502 break;
1503 case low_latency:
1504 if (bytes_perint > adapter->eitr_high)
1505 retval = bulk_latency;
1506 else if (bytes_perint <= adapter->eitr_low)
1507 retval = lowest_latency;
1508 break;
1509 case bulk_latency:
1510 if (bytes_perint <= adapter->eitr_high)
1511 retval = low_latency;
1512 break;
1513 }
1514
1515update_itr_done:
1516 return retval;
1517}
1518
509ee935
JB		 1519/**
1520 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1521 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1522 *
1523 * This function is made to be called by ethtool and by the driver
1524 * when it needs to update EITR registers at runtime. Hardware
1525 * specific quirks/differences are taken care of here.
1526 */
fe49f04a 1527void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1528{
fe49f04a 1529 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1530 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1531 int v_idx = q_vector->v_idx;
1532 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1533
509ee935
JB		 1534 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1535 /* must write high and low 16 bits to reset counter */
1536 itr_reg |= (itr_reg << 16);
1537 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f8d1dcaf
JB		 1538 /*
1539 * 82599 can support a value of zero, so allow it for
1540 * max interrupt rate, but there is an errata where it can
1541 * not be zero with RSC
1542 */
1543 if (itr_reg == 8 &&
1544 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1545 itr_reg = 0;
1546
509ee935
JB		 1547 /*
1548 * set the WDIS bit to not clear the timer bits and cause an
1549 * immediate assertion of the interrupt
1550 */
1551 itr_reg |= IXGBE_EITR_CNT_WDIS;
1552 }
1553 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1554}
1555
f494e8fa
AV		 1556static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1557{
1558 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1559 u32 new_itr;
1560 u8 current_itr, ret_itr;
fe49f04a 1561 int i, r_idx;
f494e8fa
AV		 1562 struct ixgbe_ring *rx_ring, *tx_ring;
1563
1564 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1565 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1566 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1567 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1568 q_vector->tx_itr,
1569 tx_ring->total_packets,
1570 tx_ring->total_bytes);
f494e8fa
AV		 1571 /* if the result for this queue would decrease interrupt
1572 * rate for this vector then use that result */
30efa5a3 1573 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1574 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1575 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1576 r_idx + 1);
f494e8fa
AV		 1577 }
1578
1579 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1580 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1581 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1582 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1583 q_vector->rx_itr,
1584 rx_ring->total_packets,
1585 rx_ring->total_bytes);
f494e8fa
AV		 1586 /* if the result for this queue would decrease interrupt
1587 * rate for this vector then use that result */
30efa5a3 1588 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1589 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1590 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1591 r_idx + 1);
f494e8fa
AV		 1592 }
1593
30efa5a3 1594 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1595
1596 switch (current_itr) {
1597 /* counts and packets in update_itr are dependent on these numbers */
1598 case lowest_latency:
1599 new_itr = 100000;
1600 break;
1601 case low_latency:
1602 new_itr = 20000; /* aka hwitr = ~200 */
1603 break;
1604 case bulk_latency:
1605 default:
1606 new_itr = 8000;
1607 break;
1608 }
1609
1610 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1611 /* do an exponential smoothing */
1612 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1613
1614 /* save the algorithm value here, not the smoothed one */
1615 q_vector->eitr = new_itr;
fe49f04a
AD		 1616
1617 ixgbe_write_eitr(q_vector);
f494e8fa 1618 }
f494e8fa
AV		 1619}
1620
0befdb3e
JB		 1621static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1622{
1623 struct ixgbe_hw *hw = &adapter->hw;
1624
1625 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1626 (eicr & IXGBE_EICR_GPI_SDP1)) {
1627 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1628 /* write to clear the interrupt */
1629 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1630 }
1631}
cf8280ee 1632
e8e26350
PW		 1633static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1634{
1635 struct ixgbe_hw *hw = &adapter->hw;
1636
1637 if (eicr & IXGBE_EICR_GPI_SDP1) {
1638 /* Clear the interrupt */
1639 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1640 schedule_work(&adapter->multispeed_fiber_task);
1641 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1642 /* Clear the interrupt */
1643 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1644 schedule_work(&adapter->sfp_config_module_task);
1645 } else {
1646 /* Interrupt isn't for us... */
1647 return;
1648 }
1649}
1650
cf8280ee
JB		 1651static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1652{
1653 struct ixgbe_hw *hw = &adapter->hw;
1654
1655 adapter->lsc_int++;
1656 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1657 adapter->link_check_timeout = jiffies;
1658 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1659 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1660 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1661 schedule_work(&adapter->watchdog_task);
1662 }
1663}
1664
9a799d71
AK		 1665static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1666{
1667 struct net_device *netdev = data;
1668 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1669 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1670 u32 eicr;
1671
1672 /*
1673 * Workaround for Silicon errata. Use clear-by-write instead
1674 * of clear-by-read. Reading with EICS will return the
1675 * interrupt causes without clearing, which later be done
1676 * with the write to EICR.
1677 */
1678 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1679 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1680
cf8280ee
JB		 1681 if (eicr & IXGBE_EICR_LSC)
1682 ixgbe_check_lsc(adapter);
d4f80882 1683
1cdd1ec8
GR		 1684 if (eicr & IXGBE_EICR_MAILBOX)
1685 ixgbe_msg_task(adapter);
1686
e8e26350
PW		 1687 if (hw->mac.type == ixgbe_mac_82598EB)
1688 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1689
c4cf55e5 1690 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1691 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1692
1693 /* Handle Flow Director Full threshold interrupt */
1694 if (eicr & IXGBE_EICR_FLOW_DIR) {
1695 int i;
1696 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1697 /* Disable transmits before FDIR Re-initialization */
1698 netif_tx_stop_all_queues(netdev);
1699 for (i = 0; i < adapter->num_tx_queues; i++) {
1700 struct ixgbe_ring *tx_ring =
4a0b9ca0 1701 adapter->tx_ring[i];
c4cf55e5
PWJ		 1702 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1703 &tx_ring->reinit_state))
1704 schedule_work(&adapter->fdir_reinit_task);
1705 }
1706 }
1707 }
d4f80882
AV		 1708 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1709 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1710
1711 return IRQ_HANDLED;
1712}
1713
fe49f04a
AD		 1714static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1715 u64 qmask)
1716{
1717 u32 mask;
1718
1719 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1720 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1721 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1722 } else {
1723 mask = (qmask & 0xFFFFFFFF);
1724 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1725 mask = (qmask >> 32);
1726 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1727 }
1728 /* skip the flush */
1729}
1730
1731static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1732 u64 qmask)
1733{
1734 u32 mask;
1735
1736 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1737 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1738 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1739 } else {
1740 mask = (qmask & 0xFFFFFFFF);
1741 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1742 mask = (qmask >> 32);
1743 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1744 }
1745 /* skip the flush */
1746}
1747
9a799d71
AK		 1748static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1749{
021230d4
AV		 1750 struct ixgbe_q_vector *q_vector = data;
1751 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1752 struct ixgbe_ring *tx_ring;
021230d4
AV		 1753 int i, r_idx;
1754
1755 if (!q_vector->txr_count)
1756 return IRQ_HANDLED;
1757
1758 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1759 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1760 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1761 tx_ring->total_bytes = 0;
1762 tx_ring->total_packets = 0;
021230d4 1763 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1764 r_idx + 1);
021230d4 1765 }
9a799d71 1766
9b471446 1767 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1768 napi_schedule(&q_vector->napi);
1769
9a799d71
AK		 1770 return IRQ_HANDLED;
1771}
1772
021230d4
AV		 1773/**
1774 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1775 * @irq: unused
1776 * @data: pointer to our q_vector struct for this interrupt vector
1777 **/
9a799d71
AK		 1778static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1779{
021230d4
AV		 1780 struct ixgbe_q_vector *q_vector = data;
1781 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1782 struct ixgbe_ring *rx_ring;
021230d4 1783 int r_idx;
30efa5a3 1784 int i;
021230d4
AV		 1785
1786 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1787 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1788 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1789 rx_ring->total_bytes = 0;
1790 rx_ring->total_packets = 0;
1791 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1792 r_idx + 1);
1793 }
1794
021230d4
AV		 1795 if (!q_vector->rxr_count)
1796 return IRQ_HANDLED;
1797
021230d4 1798 /* disable interrupts on this vector only */
9b471446 1799 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1800 napi_schedule(&q_vector->napi);
021230d4
AV		 1801
1802 return IRQ_HANDLED;
1803}
1804
1805static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1806{
91281fd3
AD		 1807 struct ixgbe_q_vector *q_vector = data;
1808 struct ixgbe_adapter *adapter = q_vector->adapter;
1809 struct ixgbe_ring *ring;
1810 int r_idx;
1811 int i;
1812
1813 if (!q_vector->txr_count && !q_vector->rxr_count)
1814 return IRQ_HANDLED;
1815
1816 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1817 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1818 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1819 ring->total_bytes = 0;
1820 ring->total_packets = 0;
1821 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1822 r_idx + 1);
1823 }
1824
1825 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1826 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1827 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1828 ring->total_bytes = 0;
1829 ring->total_packets = 0;
1830 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1831 r_idx + 1);
1832 }
1833
9b471446 1834 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1835 napi_schedule(&q_vector->napi);
9a799d71 1836
9a799d71
AK		 1837 return IRQ_HANDLED;
1838}
1839
021230d4
AV		 1840/**
1841 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1842 * @napi: napi struct with our devices info in it
1843 * @budget: amount of work driver is allowed to do this pass, in packets
1844 *
f0848276
JB		 1845 * This function is optimized for cleaning one queue only on a single
1846 * q_vector!!!
021230d4 1847 **/
9a799d71
AK		 1848static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1849{
021230d4 1850 struct ixgbe_q_vector *q_vector =
b4617240 1851 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1852 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1853 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1854 int work_done = 0;
021230d4 1855 long r_idx;
9a799d71 1856
021230d4 1857 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1858 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1859#ifdef CONFIG_IXGBE_DCA
bd0362dd 1860 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1861 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1862#endif
9a799d71 1863
78b6f4ce 1864 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1865
021230d4
AV		 1866 /* If all Rx work done, exit the polling mode */
1867 if (work_done < budget) {
288379f0 1868 napi_complete(napi);
f7554a2b 1869 if (adapter->rx_itr_setting & 1)
f494e8fa 1870 ixgbe_set_itr_msix(q_vector);
9a799d71 1871 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1872 ixgbe_irq_enable_queues(adapter,
1873 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1874 }
1875
1876 return work_done;
1877}
1878
f0848276 1879/**
91281fd3 1880 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1881 * @napi: napi struct with our devices info in it
1882 * @budget: amount of work driver is allowed to do this pass, in packets
1883 *
1884 * This function will clean more than one rx queue associated with a
1885 * q_vector.
1886 **/
91281fd3 1887static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1888{
1889 struct ixgbe_q_vector *q_vector =
1890 container_of(napi, struct ixgbe_q_vector, napi);
1891 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1892 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1893 int work_done = 0, i;
1894 long r_idx;
91281fd3
AD		 1895 bool tx_clean_complete = true;
1896
1897 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1898 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1899 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1900#ifdef CONFIG_IXGBE_DCA
1901 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1902 ixgbe_update_tx_dca(adapter, ring);
1903#endif
1904 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1905 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1906 r_idx + 1);
1907 }
f0848276
JB		 1908
1909 /* attempt to distribute budget to each queue fairly, but don't allow
1910 * the budget to go below 1 because we'll exit polling */
1911 budget /= (q_vector->rxr_count ?: 1);
1912 budget = max(budget, 1);
1913 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1914 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1915 ring = adapter->rx_ring[r_idx];
5dd2d332 1916#ifdef CONFIG_IXGBE_DCA
f0848276 1917 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1918 ixgbe_update_rx_dca(adapter, ring);
f0848276 1919#endif
91281fd3 1920 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1921 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1922 r_idx + 1);
1923 }
1924
1925 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1926 ring = adapter->rx_ring[r_idx];
f0848276 1927 /* If all Rx work done, exit the polling mode */
7f821875 1928 if (work_done < budget) {
288379f0 1929 napi_complete(napi);
f7554a2b 1930 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1931 ixgbe_set_itr_msix(q_vector);
1932 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1933 ixgbe_irq_enable_queues(adapter,
1934 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1935 return 0;
1936 }
1937
1938 return work_done;
1939}
91281fd3
AD		 1940
1941/**
1942 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1943 * @napi: napi struct with our devices info in it
1944 * @budget: amount of work driver is allowed to do this pass, in packets
1945 *
1946 * This function is optimized for cleaning one queue only on a single
1947 * q_vector!!!
1948 **/
1949static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1950{
1951 struct ixgbe_q_vector *q_vector =
1952 container_of(napi, struct ixgbe_q_vector, napi);
1953 struct ixgbe_adapter *adapter = q_vector->adapter;
1954 struct ixgbe_ring *tx_ring = NULL;
1955 int work_done = 0;
1956 long r_idx;
1957
1958 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 1959 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1960#ifdef CONFIG_IXGBE_DCA
1961 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1962 ixgbe_update_tx_dca(adapter, tx_ring);
1963#endif
1964
1965 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1966 work_done = budget;
1967
f7554a2b 1968 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 1969 if (work_done < budget) {
1970 napi_complete(napi);
f7554a2b 1971 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 1972 ixgbe_set_itr_msix(q_vector);
1973 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1974 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1975 }
1976
1977 return work_done;
1978}
1979
021230d4 1980static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1981 int r_idx)
021230d4 1982{
7a921c93
AD		 1983 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1984
1985 set_bit(r_idx, q_vector->rxr_idx);
1986 q_vector->rxr_count++;
021230d4
AV		 1987}
1988
1989static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1990 int t_idx)
021230d4 1991{
7a921c93
AD		 1992 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1993
1994 set_bit(t_idx, q_vector->txr_idx);
1995 q_vector->txr_count++;
021230d4
AV		 1996}
1997
9a799d71 1998/**
021230d4
AV		 1999 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2000 * @adapter: board private structure to initialize
2001 * @vectors: allotted vector count for descriptor rings
9a799d71 2002 *
021230d4
AV		 2003 * This function maps descriptor rings to the queue-specific vectors
2004 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2005 * one vector per ring/queue, but on a constrained vector budget, we
2006 * group the rings as "efficiently" as possible. You would add new
2007 * mapping configurations in here.
9a799d71 2008 **/
021230d4 2009static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 2010 int vectors)
021230d4
AV		 2011{
2012 int v_start = 0;
2013 int rxr_idx = 0, txr_idx = 0;
2014 int rxr_remaining = adapter->num_rx_queues;
2015 int txr_remaining = adapter->num_tx_queues;
2016 int i, j;
2017 int rqpv, tqpv;
2018 int err = 0;
2019
2020 /* No mapping required if MSI-X is disabled. */
2021 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2022 goto out;
9a799d71 2023
021230d4
AV		 2024 /*
2025 * The ideal configuration...
2026 * We have enough vectors to map one per queue.
2027 */
2028 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2029 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2030 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2031
021230d4
AV		 2032 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2033 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2034
9a799d71 2035 goto out;
021230d4 2036 }
9a799d71 2037
021230d4
AV		 2038 /*
2039 * If we don't have enough vectors for a 1-to-1
2040 * mapping, we'll have to group them so there are
2041 * multiple queues per vector.
2042 */
2043 /* Re-adjusting *qpv takes care of the remainder. */
2044 for (i = v_start; i < vectors; i++) {
2045 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2046 for (j = 0; j < rqpv; j++) {
2047 map_vector_to_rxq(adapter, i, rxr_idx);
2048 rxr_idx++;
2049 rxr_remaining--;
2050 }
2051 }
2052 for (i = v_start; i < vectors; i++) {
2053 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2054 for (j = 0; j < tqpv; j++) {
2055 map_vector_to_txq(adapter, i, txr_idx);
2056 txr_idx++;
2057 txr_remaining--;
9a799d71 2058 }
9a799d71
AK		 2059 }
2060
021230d4
AV		 2061out:
2062 return err;
2063}
2064
2065/**
2066 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2067 * @adapter: board private structure
2068 *
2069 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2070 * interrupts from the kernel.
2071 **/
2072static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2073{
2074 struct net_device *netdev = adapter->netdev;
2075 irqreturn_t (*handler)(int, void *);
2076 int i, vector, q_vectors, err;
cb13fc20 2077 int ri=0, ti=0;
021230d4
AV		 2078
2079 /* Decrement for Other and TCP Timer vectors */
2080 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2081
2082 /* Map the Tx/Rx rings to the vectors we were allotted. */
2083 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2084 if (err)
2085 goto out;
2086
2087#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 2088 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2089 &ixgbe_msix_clean_many)
021230d4 2090 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 2091 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 2092
2093 if(handler == &ixgbe_msix_clean_rx) {
2094 sprintf(adapter->name[vector], "%s-%s-%d",
2095 netdev->name, "rx", ri++);
2096 }
2097 else if(handler == &ixgbe_msix_clean_tx) {
2098 sprintf(adapter->name[vector], "%s-%s-%d",
2099 netdev->name, "tx", ti++);
2100 }
2101 else
2102 sprintf(adapter->name[vector], "%s-%s-%d",
2103 netdev->name, "TxRx", vector);
2104
021230d4 2105 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 2106 handler, 0, adapter->name[vector],
7a921c93 2107 adapter->q_vector[vector]);
9a799d71
AK		 2108 if (err) {
2109 DPRINTK(PROBE, ERR,
b4617240
PW		 2110 "request_irq failed for MSIX interrupt "
2111 "Error: %d\n", err);
021230d4 2112 goto free_queue_irqs;
9a799d71 2113 }
9a799d71
AK		 2114 }
2115
021230d4
AV		 2116 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2117 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2118 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 2119 if (err) {
2120 DPRINTK(PROBE, ERR,
2121 "request_irq for msix_lsc failed: %d\n", err);
021230d4 2122 goto free_queue_irqs;
9a799d71
AK		 2123 }
2124
9a799d71
AK		 2125 return 0;
2126
021230d4
AV		 2127free_queue_irqs:
2128 for (i = vector - 1; i >= 0; i--)
2129 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 2130 adapter->q_vector[i]);
021230d4
AV		 2131 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2132 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2133 kfree(adapter->msix_entries);
2134 adapter->msix_entries = NULL;
021230d4 2135out:
9a799d71
AK		 2136 return err;
2137}
2138
f494e8fa
AV		 2139static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2140{
7a921c93 2141 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 2142 u8 current_itr;
2143 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 2144 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2145 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 2146
30efa5a3 2147 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 2148 q_vector->tx_itr,
2149 tx_ring->total_packets,
2150 tx_ring->total_bytes);
30efa5a3 2151 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 2152 q_vector->rx_itr,
2153 rx_ring->total_packets,
2154 rx_ring->total_bytes);
f494e8fa 2155
30efa5a3 2156 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2157
2158 switch (current_itr) {
2159 /* counts and packets in update_itr are dependent on these numbers */
2160 case lowest_latency:
2161 new_itr = 100000;
2162 break;
2163 case low_latency:
2164 new_itr = 20000; /* aka hwitr = ~200 */
2165 break;
2166 case bulk_latency:
2167 new_itr = 8000;
2168 break;
2169 default:
2170 break;
2171 }
2172
2173 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 2174 /* do an exponential smoothing */
2175 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 2176
2177 /* save the algorithm value here, not the smoothed one */
2178 q_vector->eitr = new_itr;
fe49f04a
AD		 2179
2180 ixgbe_write_eitr(q_vector);
f494e8fa 2181 }
f494e8fa
AV		 2182}
2183
79aefa45
AD		 2184/**
2185 * ixgbe_irq_enable - Enable default interrupt generation settings
2186 * @adapter: board private structure
2187 **/
2188static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2189{
2190 u32 mask;
835462fc
NS		 2191
2192 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 2193 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2194 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 2195 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 2196 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2197 mask |= IXGBE_EIMS_GPI_SDP1;
2198 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2199 if (adapter->num_vfs)
2200 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 2201 }
c4cf55e5
PWJ		 2202 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2203 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2204 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2205
79aefa45 2206 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 2207 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45 2208 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2209
2210 if (adapter->num_vfs > 32) {
2211 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2212 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2213 }
79aefa45 2214}
021230d4 2215
9a799d71 2216/**
021230d4 2217 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2218 * @irq: interrupt number
2219 * @data: pointer to a network interface device structure
9a799d71
AK		 2220 **/
2221static irqreturn_t ixgbe_intr(int irq, void *data)
2222{
2223 struct net_device *netdev = data;
2224 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2225 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2226 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2227 u32 eicr;
2228
54037505
DS		 2229 /*
2230 * Workaround for silicon errata. Mask the interrupts
2231 * before the read of EICR.
2232 */
2233 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2234
021230d4
AV		 2235 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2236 * therefore no explict interrupt disable is necessary */
2237 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 2238 if (!eicr) {
2239 /* shared interrupt alert!
2240 * make sure interrupts are enabled because the read will
2241 * have disabled interrupts due to EIAM */
2242 ixgbe_irq_enable(adapter);
9a799d71 2243 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2244 }
9a799d71 2245
cf8280ee
JB		 2246 if (eicr & IXGBE_EICR_LSC)
2247 ixgbe_check_lsc(adapter);
021230d4 2248
e8e26350
PW		 2249 if (hw->mac.type == ixgbe_mac_82599EB)
2250 ixgbe_check_sfp_event(adapter, eicr);
2251
0befdb3e
JB		 2252 ixgbe_check_fan_failure(adapter, eicr);
2253
7a921c93 2254 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2255 adapter->tx_ring[0]->total_packets = 0;
2256 adapter->tx_ring[0]->total_bytes = 0;
2257 adapter->rx_ring[0]->total_packets = 0;
2258 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2259 /* would disable interrupts here but EIAM disabled it */
7a921c93 2260 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2261 }
2262
2263 return IRQ_HANDLED;
2264}
2265
021230d4
AV		 2266static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2267{
2268 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2269
2270 for (i = 0; i < q_vectors; i++) {
7a921c93 2271 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2272 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2273 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2274 q_vector->rxr_count = 0;
2275 q_vector->txr_count = 0;
2276 }
2277}
2278
9a799d71
AK		 2279/**
2280 * ixgbe_request_irq - initialize interrupts
2281 * @adapter: board private structure
2282 *
2283 * Attempts to configure interrupts using the best available
2284 * capabilities of the hardware and kernel.
2285 **/
021230d4 2286static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2287{
2288 struct net_device *netdev = adapter->netdev;
021230d4 2289 int err;
9a799d71 2290
021230d4
AV		 2291 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2292 err = ixgbe_request_msix_irqs(adapter);
2293 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2294 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
b4617240 2295 netdev->name, netdev);
021230d4 2296 } else {
a0607fd3 2297 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
b4617240 2298 netdev->name, netdev);
9a799d71
AK		 2299 }
2300
9a799d71
AK		 2301 if (err)
2302 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
2303
9a799d71
AK		 2304 return err;
2305}
2306
2307static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2308{
2309 struct net_device *netdev = adapter->netdev;
2310
2311 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2312 int i, q_vectors;
9a799d71 2313
021230d4
AV		 2314 q_vectors = adapter->num_msix_vectors;
2315
2316 i = q_vectors - 1;
9a799d71 2317 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2318
021230d4
AV		 2319 i--;
2320 for (; i >= 0; i--) {
2321 free_irq(adapter->msix_entries[i].vector,
7a921c93 2322 adapter->q_vector[i]);
021230d4
AV		 2323 }
2324
2325 ixgbe_reset_q_vectors(adapter);
2326 } else {
2327 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2328 }
2329}
2330
22d5a71b
JB		 2331/**
2332 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2333 * @adapter: board private structure
2334 **/
2335static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2336{
835462fc
NS		 2337 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2338 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2339 } else {
2340 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2341 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2342 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2343 if (adapter->num_vfs > 32)
2344 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 2345 }
2346 IXGBE_WRITE_FLUSH(&adapter->hw);
2347 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2348 int i;
2349 for (i = 0; i < adapter->num_msix_vectors; i++)
2350 synchronize_irq(adapter->msix_entries[i].vector);
2351 } else {
2352 synchronize_irq(adapter->pdev->irq);
2353 }
2354}
2355
9a799d71
AK		 2356/**
2357 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2358 *
2359 **/
2360static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2361{
9a799d71
AK		 2362 struct ixgbe_hw *hw = &adapter->hw;
2363
021230d4 2364 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 2365 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2366
e8e26350
PW		 2367 ixgbe_set_ivar(adapter, 0, 0, 0);
2368 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2369
2370 map_vector_to_rxq(adapter, 0, 0);
2371 map_vector_to_txq(adapter, 0, 0);
2372
2373 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2374}
2375
2376/**
3a581073 2377 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2378 * @adapter: board private structure
2379 *
2380 * Configure the Tx unit of the MAC after a reset.
2381 **/
2382static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2383{
12207e49 2384 u64 tdba;
9a799d71 2385 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2386 u32 i, j, tdlen, txctrl;
9a799d71
AK		 2387
2388 /* Setup the HW Tx Head and Tail descriptor pointers */
2389 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2390 struct ixgbe_ring *ring = adapter->tx_ring[i];
e01c31a5
JB		 2391 j = ring->reg_idx;
2392 tdba = ring->dma;
2393 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 2394 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 2395 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 2396 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2397 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2398 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2399 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
4a0b9ca0
PW		 2400 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2401 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
84f62d4b
PWJ		 2402 /*
2403 * Disable Tx Head Writeback RO bit, since this hoses
021230d4
AV		 2404 * bookkeeping if things aren't delivered in order.
2405 */
84f62d4b
PWJ		 2406 switch (hw->mac.type) {
2407 case ixgbe_mac_82598EB:
2408 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2409 break;
2410 case ixgbe_mac_82599EB:
2411 default:
2412 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2413 break;
2414 }
021230d4 2415 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
84f62d4b
PWJ		 2416 switch (hw->mac.type) {
2417 case ixgbe_mac_82598EB:
2418 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2419 break;
2420 case ixgbe_mac_82599EB:
2421 default:
2422 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2423 break;
2424 }
9a799d71 2425 }
ee5f784a 2426
e8e26350 2427 if (hw->mac.type == ixgbe_mac_82599EB) {
ee5f784a 2428 u32 rttdcs;
1cdd1ec8 2429 u32 mask;
ee5f784a
DS		 2430
2431 /* disable the arbiter while setting MTQC */
2432 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2433 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2434 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2435
1cdd1ec8
GR		 2436 /* set transmit pool layout */
2437 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2438 switch (adapter->flags & mask) {
2439
2440 case (IXGBE_FLAG_SRIOV_ENABLED):
2441 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2442 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2443 break;
2444
2445 case (IXGBE_FLAG_DCB_ENABLED):
2446 /* We enable 8 traffic classes, DCB only */
2447 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2448 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2449 break;
2450
2451 default:
ee5f784a 2452 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1cdd1ec8
GR		 2453 break;
2454 }
ee5f784a
DS		 2455
2456 /* re-eable the arbiter */
2457 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2458 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
e8e26350 2459 }
9a799d71
AK		 2460}
2461
e8e26350 2462#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2463
a6616b42
YZ		 2464static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2465 struct ixgbe_ring *rx_ring)
cc41ac7c 2466{
cc41ac7c 2467 u32 srrctl;
a6616b42 2468 int index;
0cefafad 2469 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2470
a6616b42
YZ		 2471 index = rx_ring->reg_idx;
2472 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2473 unsigned long mask;
0cefafad 2474 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2475 index = index & mask;
cc41ac7c 2476 }
cc41ac7c
JB		 2477 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2478
2479 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2480 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2481
afafd5b0
AD		 2482 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2483 IXGBE_SRRCTL_BSIZEHDR_MASK;
2484
6e455b89 2485 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2486#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2487 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2488#else
2489 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2490#endif
cc41ac7c 2491 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2492 } else {
afafd5b0
AD		 2493 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2494 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2495 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2496 }
e8e26350 2497
cc41ac7c
JB		 2498 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2499}
9a799d71 2500
0cefafad
JB		 2501static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2502{
2503 u32 mrqc = 0;
2504 int mask;
2505
2506 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2507 return mrqc;
2508
2509 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2510#ifdef CONFIG_IXGBE_DCB
2511 | IXGBE_FLAG_DCB_ENABLED
2512#endif
1cdd1ec8 2513 | IXGBE_FLAG_SRIOV_ENABLED
0cefafad
JB		 2514 );
2515
2516 switch (mask) {
2517 case (IXGBE_FLAG_RSS_ENABLED):
2518 mrqc = IXGBE_MRQC_RSSEN;
2519 break;
1cdd1ec8
GR		 2520 case (IXGBE_FLAG_SRIOV_ENABLED):
2521 mrqc = IXGBE_MRQC_VMDQEN;
2522 break;
0cefafad
JB		 2523#ifdef CONFIG_IXGBE_DCB
2524 case (IXGBE_FLAG_DCB_ENABLED):
2525 mrqc = IXGBE_MRQC_RT8TCEN;
2526 break;
2527#endif /* CONFIG_IXGBE_DCB */
2528 default:
2529 break;
2530 }
2531
2532 return mrqc;
2533}
2534
bb5a9ad2
NS		 2535/**
2536 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2537 * @adapter: address of board private structure
2538 * @index: index of ring to set
bb5a9ad2 2539 **/
edd2ea55 2540static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
bb5a9ad2
NS		 2541{
2542 struct ixgbe_ring *rx_ring;
2543 struct ixgbe_hw *hw = &adapter->hw;
2544 int j;
2545 u32 rscctrl;
edd2ea55 2546 int rx_buf_len;
bb5a9ad2 2547
4a0b9ca0 2548 rx_ring = adapter->rx_ring[index];
bb5a9ad2 2549 j = rx_ring->reg_idx;
edd2ea55 2550 rx_buf_len = rx_ring->rx_buf_len;
bb5a9ad2
NS		 2551 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2552 rscctrl |= IXGBE_RSCCTL_RSCEN;
2553 /*
2554 * we must limit the number of descriptors so that the
2555 * total size of max desc * buf_len is not greater
2556 * than 65535
2557 */
2558 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2559#if (MAX_SKB_FRAGS > 16)
2560 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2561#elif (MAX_SKB_FRAGS > 8)
2562 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2563#elif (MAX_SKB_FRAGS > 4)
2564 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2565#else
2566 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2567#endif
2568 } else {
2569 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2570 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2571 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2572 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2573 else
2574 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2575 }
2576 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2577}
2578
9a799d71 2579/**
3a581073 2580 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 2581 * @adapter: board private structure
2582 *
2583 * Configure the Rx unit of the MAC after a reset.
2584 **/
2585static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2586{
2587 u64 rdba;
2588 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 2589 struct ixgbe_ring *rx_ring;
9a799d71
AK		 2590 struct net_device *netdev = adapter->netdev;
2591 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2592 int i, j;
9a799d71 2593 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 2594 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2595 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2596 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 2597 u32 fctrl, hlreg0;
509ee935 2598 u32 reta = 0, mrqc = 0;
cc41ac7c 2599 u32 rdrxctl;
7c6e0a43 2600 int rx_buf_len;
9a799d71
AK		 2601
2602 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2603 /* Do not use packet split if we're in SR-IOV Mode */
2604 if (!adapter->num_vfs)
2605 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2606
2607 /* Set the RX buffer length according to the mode */
2608 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2609 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2610 if (hw->mac.type == ixgbe_mac_82599EB) {
2611 /* PSRTYPE must be initialized in 82599 */
2612 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2613 IXGBE_PSRTYPE_UDPHDR |
2614 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2615 IXGBE_PSRTYPE_IPV6HDR |
2616 IXGBE_PSRTYPE_L2HDR;
1cdd1ec8
GR		 2617 IXGBE_WRITE_REG(hw,
2618 IXGBE_PSRTYPE(adapter->num_vfs),
2619 psrtype);
e8e26350 2620 }
9a799d71 2621 } else {
0c19d6af 2622 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2623 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2624 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2625 else
7c6e0a43 2626 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2627 }
2628
2629 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2630 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2631 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2632 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2633 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2634
2635 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2636 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2637 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2638 else
2639 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2640#ifdef IXGBE_FCOE
f34c5c82 2641 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2642 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2643#endif
9a799d71
AK		 2644 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2645
4a0b9ca0 2646 rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
9a799d71
AK		 2647 /* disable receives while setting up the descriptors */
2648 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2649 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2650
0cefafad
JB		 2651 /*
2652 * Setup the HW Rx Head and Tail Descriptor Pointers and
2653 * the Base and Length of the Rx Descriptor Ring
2654 */
9a799d71 2655 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2656 rx_ring = adapter->rx_ring[i];
a6616b42
YZ		 2657 rdba = rx_ring->dma;
2658 j = rx_ring->reg_idx;
284901a9 2659 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2660 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2661 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2662 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2663 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2664 rx_ring->head = IXGBE_RDH(j);
2665 rx_ring->tail = IXGBE_RDT(j);
2666 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2667
6e455b89
YZ		 2668 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2669 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2670 else
2671 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2672
63f39bd1 2673#ifdef IXGBE_FCOE
f34c5c82 2674 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2675 struct ixgbe_ring_feature *f;
2676 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2677 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2678 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2679 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2680 rx_ring->rx_buf_len =
2681 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2682 }
63f39bd1
YZ		 2683 }
2684
2685#endif /* IXGBE_FCOE */
a6616b42 2686 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2687 }
2688
e8e26350
PW		 2689 if (hw->mac.type == ixgbe_mac_82598EB) {
2690 /*
2691 * For VMDq support of different descriptor types or
2692 * buffer sizes through the use of multiple SRRCTL
2693 * registers, RDRXCTL.MVMEN must be set to 1
2694 *
2695 * also, the manual doesn't mention it clearly but DCA hints
2696 * will only use queue 0's tags unless this bit is set. Side
2697 * effects of setting this bit are only that SRRCTL must be
2698 * fully programmed [0..15]
2699 */
2a41ff81
JB		 2700 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2701 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2702 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2703 }
177db6ff 2704
1cdd1ec8
GR		 2705 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2706 u32 vt_reg_bits;
2707 u32 reg_offset, vf_shift;
2708 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2709 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2710 | IXGBE_VT_CTL_REPLEN;
2711 vt_reg_bits |= (adapter->num_vfs <<
2712 IXGBE_VT_CTL_POOL_SHIFT);
2713 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2714 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2715
2716 vf_shift = adapter->num_vfs % 32;
2717 reg_offset = adapter->num_vfs / 32;
2718 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2719 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2720 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2721 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2722 /* Enable only the PF's pool for Tx/Rx */
2723 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2724 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2725 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f0412776 2726 ixgbe_set_vmolr(hw, adapter->num_vfs, true);
1cdd1ec8
GR		 2727 }
2728
e8e26350 2729 /* Program MRQC for the distribution of queues */
0cefafad 2730 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2731
021230d4 2732 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2733 /* Fill out redirection table */
021230d4
AV		 2734 for (i = 0, j = 0; i < 128; i++, j++) {
2735 if (j == adapter->ring_feature[RING_F_RSS].indices)
2736 j = 0;
2737 /* reta = 4-byte sliding window of
2738 * 0x00..(indices-1)(indices-1)00..etc. */
2739 reta = (reta << 8) | (j * 0x11);
2740 if ((i & 3) == 3)
2741 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2742 }
2743
2744 /* Fill out hash function seeds */
2745 for (i = 0; i < 10; i++)
7c6e0a43 2746 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2747
2a41ff81
JB		 2748 if (hw->mac.type == ixgbe_mac_82598EB)
2749 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2750 /* Perform hash on these packet types */
2a41ff81
JB		 2751 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2752 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2753 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2754 | IXGBE_MRQC_RSS_FIELD_IPV6
2755 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2756 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2757 }
2a41ff81 2758 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2759
1cdd1ec8
GR		 2760 if (adapter->num_vfs) {
2761 u32 reg;
2762
2763 /* Map PF MAC address in RAR Entry 0 to first pool
2764 * following VFs */
2765 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2766
2767 /* Set up VF register offsets for selected VT Mode, i.e.
2768 * 64 VFs for SR-IOV */
2769 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2770 reg |= IXGBE_GCR_EXT_SRIOV;
2771 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2772 }
2773
021230d4
AV		 2774 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2775
2776 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2777 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2778 /* Disable indicating checksum in descriptor, enables
2779 * RSS hash */
9a799d71 2780 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2781 }
021230d4
AV		 2782 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2783 /* Enable IPv4 payload checksum for UDP fragments
2784 * if PCSD is not set */
2785 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2786 }
2787
2788 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2789
2790 if (hw->mac.type == ixgbe_mac_82599EB) {
2791 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2792 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2793 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2794 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2795 }
f8212f97 2796
0c19d6af 2797 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2798 /* Enable 82599 HW-RSC */
bb5a9ad2 2799 for (i = 0; i < adapter->num_rx_queues; i++)
edd2ea55 2800 ixgbe_configure_rscctl(adapter, i);
bb5a9ad2 2801
f8212f97
AD		 2802 /* Disable RSC for ACK packets */
2803 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2804 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2805 }
9a799d71
AK		 2806}
2807
068c89b0
DS		 2808static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2809{
2810 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2811 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2812 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2813
2814 /* add VID to filter table */
1ada1b1b 2815 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
068c89b0
DS		 2816}
2817
2818static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2819{
2820 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2821 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2822 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2823
2824 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2825 ixgbe_irq_disable(adapter);
2826
2827 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2828
2829 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2830 ixgbe_irq_enable(adapter);
2831
2832 /* remove VID from filter table */
1ada1b1b 2833 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
068c89b0
DS		 2834}
2835
5f6c0181
JB		 2836/**
2837 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2838 * @adapter: driver data
2839 */
2840static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2841{
2842 struct ixgbe_hw *hw = &adapter->hw;
2843 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2844 int i, j;
2845
2846 switch (hw->mac.type) {
2847 case ixgbe_mac_82598EB:
2848 vlnctrl &= ~(IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE);
2849 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2850 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2851 break;
2852 case ixgbe_mac_82599EB:
2853 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2854 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2855 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2856 for (i = 0; i < adapter->num_rx_queues; i++) {
2857 j = adapter->rx_ring[i]->reg_idx;
2858 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2859 vlnctrl &= ~IXGBE_RXDCTL_VME;
2860 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2861 }
2862 break;
2863 default:
2864 break;
2865 }
2866}
2867
2868/**
2869 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2870 * @adapter: driver data
2871 */
2872static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2873{
2874 struct ixgbe_hw *hw = &adapter->hw;
2875 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2876 int i, j;
2877
2878 switch (hw->mac.type) {
2879 case ixgbe_mac_82598EB:
2880 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2881 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2882 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2883 break;
2884 case ixgbe_mac_82599EB:
2885 vlnctrl |= IXGBE_VLNCTRL_VFE;
2886 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2887 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2888 for (i = 0; i < adapter->num_rx_queues; i++) {
2889 j = adapter->rx_ring[i]->reg_idx;
2890 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2891 vlnctrl |= IXGBE_RXDCTL_VME;
2892 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2893 }
2894 break;
2895 default:
2896 break;
2897 }
2898}
2899
9a799d71 2900static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2901 struct vlan_group *grp)
9a799d71
AK		 2902{
2903 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 2904
d4f80882
AV		 2905 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2906 ixgbe_irq_disable(adapter);
9a799d71
AK		 2907 adapter->vlgrp = grp;
2908
2f90b865
AD		 2909 /*
2910 * For a DCB driver, always enable VLAN tag stripping so we can
2911 * still receive traffic from a DCB-enabled host even if we're
2912 * not in DCB mode.
2913 */
5f6c0181 2914 ixgbe_vlan_filter_enable(adapter);
dc63d377 2915
e8e26350 2916 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2917
d4f80882
AV		 2918 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2919 ixgbe_irq_enable(adapter);
9a799d71
AK		 2920}
2921
9a799d71
AK		 2922static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2923{
2924 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2925
2926 if (adapter->vlgrp) {
2927 u16 vid;
2928 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2929 if (!vlan_group_get_device(adapter->vlgrp, vid))
2930 continue;
2931 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2932 }
2933 }
2934}
2935
2936/**
2c5645cf 2937 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2938 * @netdev: network interface device structure
2939 *
2c5645cf
CL		 2940 * The set_rx_method entry point is called whenever the unicast/multicast
2941 * address list or the network interface flags are updated. This routine is
2942 * responsible for configuring the hardware for proper unicast, multicast and
2943 * promiscuous mode.
9a799d71 2944 **/
7f870475 2945void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2946{
2947 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2948 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 2949 u32 fctrl;
9a799d71
AK		 2950
2951 /* Check for Promiscuous and All Multicast modes */
2952
2953 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2954
2955 if (netdev->flags & IFF_PROMISC) {
e433ea1f 2956 hw->addr_ctrl.user_set_promisc = true;
9a799d71 2957 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
5f6c0181
JB		 2958 /* don't hardware filter vlans in promisc mode */
2959 ixgbe_vlan_filter_disable(adapter);
9a799d71 2960 } else {
746b9f02
PM		 2961 if (netdev->flags & IFF_ALLMULTI) {
2962 fctrl |= IXGBE_FCTRL_MPE;
2963 fctrl &= ~IXGBE_FCTRL_UPE;
e433ea1f 2964 } else if (!hw->addr_ctrl.uc_set_promisc) {
746b9f02
PM		 2965 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2966 }
5f6c0181 2967 ixgbe_vlan_filter_enable(adapter);
e433ea1f 2968 hw->addr_ctrl.user_set_promisc = false;
9a799d71
AK		 2969 }
2970
2971 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2972
2c5645cf 2973 /* reprogram secondary unicast list */
32e7bfc4 2974 hw->mac.ops.update_uc_addr_list(hw, netdev);
9a799d71 2975
2c5645cf 2976 /* reprogram multicast list */
2853eb89
JP		 2977 hw->mac.ops.update_mc_addr_list(hw, netdev);
2978
1cdd1ec8
GR		 2979 if (adapter->num_vfs)
2980 ixgbe_restore_vf_multicasts(adapter);
9a799d71
AK		 2981}
2982
021230d4
AV		 2983static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2984{
2985 int q_idx;
2986 struct ixgbe_q_vector *q_vector;
2987 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2988
2989 /* legacy and MSI only use one vector */
2990 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2991 q_vectors = 1;
2992
2993 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2994 struct napi_struct *napi;
7a921c93 2995 q_vector = adapter->q_vector[q_idx];
f0848276 2996 napi = &q_vector->napi;
91281fd3
AD		 2997 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2998 if (!q_vector->rxr_count || !q_vector->txr_count) {
2999 if (q_vector->txr_count == 1)
3000 napi->poll = &ixgbe_clean_txonly;
3001 else if (q_vector->rxr_count == 1)
3002 napi->poll = &ixgbe_clean_rxonly;
3003 }
3004 }
f0848276
JB		 3005
3006 napi_enable(napi);
021230d4
AV		 3007 }
3008}
3009
3010static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3011{
3012 int q_idx;
3013 struct ixgbe_q_vector *q_vector;
3014 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3015
3016 /* legacy and MSI only use one vector */
3017 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3018 q_vectors = 1;
3019
3020 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3021 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3022 napi_disable(&q_vector->napi);
3023 }
3024}
3025
7a6b6f51 3026#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3027/*
3028 * ixgbe_configure_dcb - Configure DCB hardware
3029 * @adapter: ixgbe adapter struct
3030 *
3031 * This is called by the driver on open to configure the DCB hardware.
3032 * This is also called by the gennetlink interface when reconfiguring
3033 * the DCB state.
3034 */
3035static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3036{
3037 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 3038 u32 txdctl;
2f90b865
AD		 3039 int i, j;
3040
3041 ixgbe_dcb_check_config(&adapter->dcb_cfg);
3042 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3043 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3044
3045 /* reconfigure the hardware */
3046 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3047
3048 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3049 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 3050 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3051 /* PThresh workaround for Tx hang with DFP enabled. */
3052 txdctl |= 32;
3053 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3054 }
3055 /* Enable VLAN tag insert/strip */
5f6c0181
JB		 3056 ixgbe_vlan_filter_enable(adapter);
3057
2f90b865
AD		 3058 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3059}
3060
3061#endif
9a799d71
AK		 3062static void ixgbe_configure(struct ixgbe_adapter *adapter)
3063{
3064 struct net_device *netdev = adapter->netdev;
c4cf55e5 3065 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3066 int i;
3067
2c5645cf 3068 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 3069
3070 ixgbe_restore_vlan(adapter);
7a6b6f51 3071#ifdef CONFIG_IXGBE_DCB
2f90b865 3072 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
b352e40d
YZ		 3073 if (hw->mac.type == ixgbe_mac_82598EB)
3074 netif_set_gso_max_size(netdev, 32768);
3075 else
3076 netif_set_gso_max_size(netdev, 65536);
2f90b865
AD		 3077 ixgbe_configure_dcb(adapter);
3078 } else {
3079 netif_set_gso_max_size(netdev, 65536);
3080 }
3081#else
3082 netif_set_gso_max_size(netdev, 65536);
3083#endif
9a799d71 3084
eacd73f7
YZ		 3085#ifdef IXGBE_FCOE
3086 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3087 ixgbe_configure_fcoe(adapter);
3088
3089#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3090 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3091 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3092 adapter->tx_ring[i]->atr_sample_rate =
c4cf55e5
PWJ		 3093 adapter->atr_sample_rate;
3094 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3095 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3096 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3097 }
3098
9a799d71
AK		 3099 ixgbe_configure_tx(adapter);
3100 ixgbe_configure_rx(adapter);
3101 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 3102 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3103 (adapter->rx_ring[i]->count - 1));
9a799d71
AK		 3104}
3105
e8e26350
PW		 3106static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3107{
3108 switch (hw->phy.type) {
3109 case ixgbe_phy_sfp_avago:
3110 case ixgbe_phy_sfp_ftl:
3111 case ixgbe_phy_sfp_intel:
3112 case ixgbe_phy_sfp_unknown:
3113 case ixgbe_phy_tw_tyco:
3114 case ixgbe_phy_tw_unknown:
3115 return true;
3116 default:
3117 return false;
3118 }
3119}
3120
0ecc061d 3121/**
e8e26350
PW		 3122 * ixgbe_sfp_link_config - set up SFP+ link
3123 * @adapter: pointer to private adapter struct
3124 **/
3125static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3126{
3127 struct ixgbe_hw *hw = &adapter->hw;
3128
3129 if (hw->phy.multispeed_fiber) {
3130 /*
3131 * In multispeed fiber setups, the device may not have
3132 * had a physical connection when the driver loaded.
3133 * If that's the case, the initial link configuration
3134 * couldn't get the MAC into 10G or 1G mode, so we'll
3135 * never have a link status change interrupt fire.
3136 * We need to try and force an autonegotiation
3137 * session, then bring up link.
3138 */
3139 hw->mac.ops.setup_sfp(hw);
3140 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3141 schedule_work(&adapter->multispeed_fiber_task);
3142 } else {
3143 /*
3144 * Direct Attach Cu and non-multispeed fiber modules
3145 * still need to be configured properly prior to
3146 * attempting link.
3147 */
3148 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3149 schedule_work(&adapter->sfp_config_module_task);
3150 }
3151}
3152
3153/**
3154 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3155 * @hw: pointer to private hardware struct
3156 *
3157 * Returns 0 on success, negative on failure
3158 **/
e8e26350 3159static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3160{
3161 u32 autoneg;
8620a103 3162 bool negotiation, link_up = false;
0ecc061d
PWJ		 3163 u32 ret = IXGBE_ERR_LINK_SETUP;
3164
3165 if (hw->mac.ops.check_link)
3166 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3167
3168 if (ret)
3169 goto link_cfg_out;
3170
3171 if (hw->mac.ops.get_link_capabilities)
8620a103 3172 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 3173 if (ret)
3174 goto link_cfg_out;
3175
8620a103
MC		 3176 if (hw->mac.ops.setup_link)
3177 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3178link_cfg_out:
3179 return ret;
3180}
3181
e8e26350
PW		 3182#define IXGBE_MAX_RX_DESC_POLL 10
3183static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3184 int rxr)
3185{
4a0b9ca0 3186 int j = adapter->rx_ring[rxr]->reg_idx;
e8e26350
PW		 3187 int k;
3188
3189 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3190 if (IXGBE_READ_REG(&adapter->hw,
3191 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3192 break;
3193 else
3194 msleep(1);
3195 }
3196 if (k >= IXGBE_MAX_RX_DESC_POLL) {
3197 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
3198 "not set within the polling period\n", rxr);
3199 }
4a0b9ca0
PW		 3200 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3201 (adapter->rx_ring[rxr]->count - 1));
e8e26350
PW		 3202}
3203
9a799d71
AK		 3204static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3205{
3206 struct net_device *netdev = adapter->netdev;
9a799d71 3207 struct ixgbe_hw *hw = &adapter->hw;
021230d4 3208 int i, j = 0;
e8e26350 3209 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 3210 int err;
9a799d71 3211 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 3212 u32 txdctl, rxdctl, mhadd;
e8e26350 3213 u32 dmatxctl;
021230d4 3214 u32 gpie;
c9205697 3215 u32 ctrl_ext;
9a799d71 3216
5eba3699
AV		 3217 ixgbe_get_hw_control(adapter);
3218
021230d4
AV		 3219 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
3220 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 3221 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3222 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 3223 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 3224 } else {
3225 /* MSI only */
021230d4 3226 gpie = 0;
9a799d71 3227 }
1cdd1ec8
GR		 3228 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3229 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3230 gpie |= IXGBE_GPIE_VTMODE_64;
3231 }
021230d4
AV		 3232 /* XXX: to interrupt immediately for EICS writes, enable this */
3233 /* gpie |= IXGBE_GPIE_EIMEN; */
3234 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 3235 }
3236
9b471446
JB		 3237 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3238 /*
3239 * use EIAM to auto-mask when MSI-X interrupt is asserted
3240 * this saves a register write for every interrupt
3241 */
3242 switch (hw->mac.type) {
3243 case ixgbe_mac_82598EB:
3244 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3245 break;
3246 default:
3247 case ixgbe_mac_82599EB:
3248 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3249 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3250 break;
3251 }
3252 } else {
021230d4
AV		 3253 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3254 * specifically only auto mask tx and rx interrupts */
3255 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3256 }
9a799d71 3257
0befdb3e
JB		 3258 /* Enable fan failure interrupt if media type is copper */
3259 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3260 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3261 gpie |= IXGBE_SDP1_GPIEN;
3262 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3263 }
3264
e8e26350
PW		 3265 if (hw->mac.type == ixgbe_mac_82599EB) {
3266 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3267 gpie |= IXGBE_SDP1_GPIEN;
3268 gpie |= IXGBE_SDP2_GPIEN;
3269 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3270 }
3271
63f39bd1
YZ		 3272#ifdef IXGBE_FCOE
3273 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 3274 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 3275 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3276 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3277
3278#endif /* IXGBE_FCOE */
021230d4 3279 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 3280 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3281 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3282 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3283
3284 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3285 }
3286
3287 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3288 j = adapter->tx_ring[i]->reg_idx;
021230d4 3289 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
ef021194
JB		 3290 if (adapter->rx_itr_setting == 0) {
3291 /* cannot set wthresh when itr==0 */
3292 txdctl &= ~0x007F0000;
3293 } else {
3294 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3295 txdctl |= (8 << 16);
3296 }
e8e26350
PW		 3297 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3298 }
3299
3300 if (hw->mac.type == ixgbe_mac_82599EB) {
3301 /* DMATXCTL.EN must be set after all Tx queue config is done */
3302 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3303 dmatxctl |= IXGBE_DMATXCTL_TE;
3304 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3305 }
3306 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3307 j = adapter->tx_ring[i]->reg_idx;
e8e26350 3308 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 3309 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 3310 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1cdd1ec8
GR		 3311 if (hw->mac.type == ixgbe_mac_82599EB) {
3312 int wait_loop = 10;
3313 /* poll for Tx Enable ready */
3314 do {
3315 msleep(1);
3316 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3317 } while (--wait_loop &&
3318 !(txdctl & IXGBE_TXDCTL_ENABLE));
3319 if (!wait_loop)
3320 DPRINTK(DRV, ERR, "Could not enable "
3321 "Tx Queue %d\n", j);
3322 }
9a799d71
AK		 3323 }
3324
e8e26350 3325 for (i = 0; i < num_rx_rings; i++) {
4a0b9ca0 3326 j = adapter->rx_ring[i]->reg_idx;
021230d4
AV		 3327 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3328 /* enable PTHRESH=32 descriptors (half the internal cache)
3329 * and HTHRESH=0 descriptors (to minimize latency on fetch),
3330 * this also removes a pesky rx_no_buffer_count increment */
3331 rxdctl |= 0x0020;
9a799d71 3332 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 3333 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 3334 if (hw->mac.type == ixgbe_mac_82599EB)
3335 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 3336 }
3337 /* enable all receives */
3338 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 3339 if (hw->mac.type == ixgbe_mac_82598EB)
3340 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3341 else
3342 rxdctl |= IXGBE_RXCTRL_RXEN;
3343 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 3344
3345 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3346 ixgbe_configure_msix(adapter);
3347 else
3348 ixgbe_configure_msi_and_legacy(adapter);
3349
61fac744
PW		 3350 /* enable the optics */
3351 if (hw->phy.multispeed_fiber)
3352 hw->mac.ops.enable_tx_laser(hw);
3353
9a799d71 3354 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3355 ixgbe_napi_enable_all(adapter);
3356
3357 /* clear any pending interrupts, may auto mask */
3358 IXGBE_READ_REG(hw, IXGBE_EICR);
3359
9a799d71
AK		 3360 ixgbe_irq_enable(adapter);
3361
bf069c97
DS		 3362 /*
3363 * If this adapter has a fan, check to see if we had a failure
3364 * before we enabled the interrupt.
3365 */
3366 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3367 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3368 if (esdp & IXGBE_ESDP_SDP1)
3369 DPRINTK(DRV, CRIT,
3370 "Fan has stopped, replace the adapter\n");
3371 }
3372
e8e26350
PW		 3373 /*
3374 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3375 * arrived before interrupts were enabled but after probe. Such
3376 * devices wouldn't have their type identified yet. We need to
3377 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3378 * If we're not hot-pluggable SFP+, we just need to configure link
3379 * and bring it up.
3380 */
19343de2
DS		 3381 if (hw->phy.type == ixgbe_phy_unknown) {
3382 err = hw->phy.ops.identify(hw);
3383 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3384 /*
3385 * Take the device down and schedule the sfp tasklet
3386 * which will unregister_netdev and log it.
3387 */
19343de2 3388 ixgbe_down(adapter);
5da43c1a 3389 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3390 return err;
3391 }
e8e26350
PW		 3392 }
3393
3394 if (ixgbe_is_sfp(hw)) {
3395 ixgbe_sfp_link_config(adapter);
3396 } else {
3397 err = ixgbe_non_sfp_link_config(hw);
3398 if (err)
3399 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3400 }
0ecc061d 3401
c4cf55e5
PWJ		 3402 for (i = 0; i < adapter->num_tx_queues; i++)
3403 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 3404 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 3405
1da100bb
PWJ		 3406 /* enable transmits */
3407 netif_tx_start_all_queues(netdev);
3408
9a799d71
AK		 3409 /* bring the link up in the watchdog, this could race with our first
3410 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3411 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3412 adapter->link_check_timeout = jiffies;
9a799d71 3413 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3414
3415 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3416 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3417 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3418 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3419
9a799d71
AK		 3420 return 0;
3421}
3422
d4f80882
AV		 3423void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3424{
3425 WARN_ON(in_interrupt());
3426 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3427 msleep(1);
3428 ixgbe_down(adapter);
5809a1ae
GR		 3429 /*
3430 * If SR-IOV enabled then wait a bit before bringing the adapter
3431 * back up to give the VFs time to respond to the reset. The
3432 * two second wait is based upon the watchdog timer cycle in
3433 * the VF driver.
3434 */
3435 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3436 msleep(2000);
d4f80882
AV		 3437 ixgbe_up(adapter);
3438 clear_bit(__IXGBE_RESETTING, &adapter->state);
3439}
3440
9a799d71
AK		 3441int ixgbe_up(struct ixgbe_adapter *adapter)
3442{
3443 /* hardware has been reset, we need to reload some things */
3444 ixgbe_configure(adapter);
3445
3446 return ixgbe_up_complete(adapter);
3447}
3448
3449void ixgbe_reset(struct ixgbe_adapter *adapter)
3450{
c44ade9e 3451 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3452 int err;
3453
3454 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3455 switch (err) {
3456 case 0:
3457 case IXGBE_ERR_SFP_NOT_PRESENT:
3458 break;
3459 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3460 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3461 break;
794caeb2
PWJ		 3462 case IXGBE_ERR_EEPROM_VERSION:
3463 /* We are running on a pre-production device, log a warning */
3464 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3465 "adapter/LOM. Please be aware there may be issues "
3466 "associated with your hardware. If you are "
3467 "experiencing problems please contact your Intel or "
3468 "hardware representative who provided you with this "
3469 "hardware.\n");
3470 break;
da4dd0f7
PWJ		 3471 default:
3472 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3473 }
9a799d71
AK		 3474
3475 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3476 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3477 IXGBE_RAH_AV);
9a799d71
AK		 3478}
3479
9a799d71
AK		 3480/**
3481 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3482 * @adapter: board private structure
3483 * @rx_ring: ring to free buffers from
3484 **/
3485static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 3486 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3487{
3488 struct pci_dev *pdev = adapter->pdev;
3489 unsigned long size;
3490 unsigned int i;
3491
3492 /* Free all the Rx ring sk_buffs */
3493
3494 for (i = 0; i < rx_ring->count; i++) {
3495 struct ixgbe_rx_buffer *rx_buffer_info;
3496
3497 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3498 if (rx_buffer_info->dma) {
1b507730 3499 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
b4617240 3500 rx_ring->rx_buf_len,
1b507730 3501 DMA_FROM_DEVICE);
9a799d71
AK		 3502 rx_buffer_info->dma = 0;
3503 }
3504 if (rx_buffer_info->skb) {
f8212f97 3505 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3506 rx_buffer_info->skb = NULL;
f8212f97
AD		 3507 do {
3508 struct sk_buff *this = skb;
e8171aaa 3509 if (IXGBE_RSC_CB(this)->delay_unmap) {
1b507730
NN		 3510 dma_unmap_single(&pdev->dev,
3511 IXGBE_RSC_CB(this)->dma,
43634e82 3512 rx_ring->rx_buf_len,
1b507730 3513 DMA_FROM_DEVICE);
fd3686a8 3514 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3515 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3516 }
f8212f97
AD		 3517 skb = skb->prev;
3518 dev_kfree_skb(this);
3519 } while (skb);
9a799d71
AK		 3520 }
3521 if (!rx_buffer_info->page)
3522 continue;
4f57ca6e 3523 if (rx_buffer_info->page_dma) {
1b507730
NN		 3524 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3525 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3526 rx_buffer_info->page_dma = 0;
3527 }
9a799d71
AK		 3528 put_page(rx_buffer_info->page);
3529 rx_buffer_info->page = NULL;
762f4c57 3530 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3531 }
3532
3533 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3534 memset(rx_ring->rx_buffer_info, 0, size);
3535
3536 /* Zero out the descriptor ring */
3537 memset(rx_ring->desc, 0, rx_ring->size);
3538
3539 rx_ring->next_to_clean = 0;
3540 rx_ring->next_to_use = 0;
3541
9891ca7c
JB		 3542 if (rx_ring->head)
3543 writel(0, adapter->hw.hw_addr + rx_ring->head);
3544 if (rx_ring->tail)
3545 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3546}
3547
3548/**
3549 * ixgbe_clean_tx_ring - Free Tx Buffers
3550 * @adapter: board private structure
3551 * @tx_ring: ring to be cleaned
3552 **/
3553static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 3554 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3555{
3556 struct ixgbe_tx_buffer *tx_buffer_info;
3557 unsigned long size;
3558 unsigned int i;
3559
3560 /* Free all the Tx ring sk_buffs */
3561
3562 for (i = 0; i < tx_ring->count; i++) {
3563 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3564 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3565 }
3566
3567 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3568 memset(tx_ring->tx_buffer_info, 0, size);
3569
3570 /* Zero out the descriptor ring */
3571 memset(tx_ring->desc, 0, tx_ring->size);
3572
3573 tx_ring->next_to_use = 0;
3574 tx_ring->next_to_clean = 0;
3575
9891ca7c
JB		 3576 if (tx_ring->head)
3577 writel(0, adapter->hw.hw_addr + tx_ring->head);
3578 if (tx_ring->tail)
3579 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3580}
3581
3582/**
021230d4 3583 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3584 * @adapter: board private structure
3585 **/
021230d4 3586static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3587{
3588 int i;
3589
021230d4 3590 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3591 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3592}
3593
3594/**
021230d4 3595 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3596 * @adapter: board private structure
3597 **/
021230d4 3598static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3599{
3600 int i;
3601
021230d4 3602 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3603 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3604}
3605
3606void ixgbe_down(struct ixgbe_adapter *adapter)
3607{
3608 struct net_device *netdev = adapter->netdev;
7f821875 3609 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3610 u32 rxctrl;
7f821875
JB		 3611 u32 txdctl;
3612 int i, j;
9a799d71
AK		 3613
3614 /* signal that we are down to the interrupt handler */
3615 set_bit(__IXGBE_DOWN, &adapter->state);
3616
61fac744
PW		 3617 /* power down the optics */
3618 if (hw->phy.multispeed_fiber)
3619 hw->mac.ops.disable_tx_laser(hw);
3620
767081ad
GR		 3621 /* disable receive for all VFs and wait one second */
3622 if (adapter->num_vfs) {
767081ad
GR		 3623 /* ping all the active vfs to let them know we are going down */
3624 ixgbe_ping_all_vfs(adapter);
581d1aa7 3625
767081ad
GR		 3626 /* Disable all VFTE/VFRE TX/RX */
3627 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3628
3629 /* Mark all the VFs as inactive */
3630 for (i = 0 ; i < adapter->num_vfs; i++)
3631 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3632 }
3633
9a799d71 3634 /* disable receives */
7f821875
JB		 3635 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3636 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3637
7f821875 3638 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3639 msleep(10);
3640
7f821875
JB		 3641 netif_tx_stop_all_queues(netdev);
3642
0a1f87cb
DS		 3643 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3644 del_timer_sync(&adapter->sfp_timer);
9a799d71 3645 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3646 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3647
c0dfb90e
JF		 3648 netif_carrier_off(netdev);
3649 netif_tx_disable(netdev);
3650
3651 ixgbe_irq_disable(adapter);
3652
3653 ixgbe_napi_disable_all(adapter);
3654
c4cf55e5
PWJ		 3655 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3656 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3657 cancel_work_sync(&adapter->fdir_reinit_task);
3658
7f821875
JB		 3659 /* disable transmits in the hardware now that interrupts are off */
3660 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3661 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3662 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3663 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3664 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3665 }
88512539
PW		 3666 /* Disable the Tx DMA engine on 82599 */
3667 if (hw->mac.type == ixgbe_mac_82599EB)
3668 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3669 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3670 ~IXGBE_DMATXCTL_TE));
7f821875 3671
9a713e7c
PW		 3672 /* clear n-tuple filters that are cached */
3673 ethtool_ntuple_flush(netdev);
3674
6f4a0e45
PL		 3675 if (!pci_channel_offline(adapter->pdev))
3676 ixgbe_reset(adapter);
9a799d71
AK		 3677 ixgbe_clean_all_tx_rings(adapter);
3678 ixgbe_clean_all_rx_rings(adapter);
3679
5dd2d332 3680#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3681 /* since we reset the hardware DCA settings were cleared */
e35ec126 3682 ixgbe_setup_dca(adapter);
96b0e0f6 3683#endif
9a799d71
AK		 3684}
3685
9a799d71 3686/**
021230d4
AV		 3687 * ixgbe_poll - NAPI Rx polling callback
3688 * @napi: structure for representing this polling device
3689 * @budget: how many packets driver is allowed to clean
3690 *
3691 * This function is used for legacy and MSI, NAPI mode
9a799d71 3692 **/
021230d4 3693static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3694{
9a1a69ad
JB		 3695 struct ixgbe_q_vector *q_vector =
3696 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3697 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3698 int tx_clean_complete, work_done = 0;
9a799d71 3699
5dd2d332 3700#ifdef CONFIG_IXGBE_DCA
bd0362dd 3701 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3702 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3703 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3704 }
3705#endif
3706
4a0b9ca0
PW		 3707 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3708 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3709
9a1a69ad 3710 if (!tx_clean_complete)
d2c7ddd6
DM		 3711 work_done = budget;
3712
53e52c72
DM		 3713 /* If budget not fully consumed, exit the polling mode */
3714 if (work_done < budget) {
288379f0 3715 napi_complete(napi);
f7554a2b 3716 if (adapter->rx_itr_setting & 1)
f494e8fa 3717 ixgbe_set_itr(adapter);
d4f80882 3718 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3719 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3720 }
9a799d71
AK		 3721 return work_done;
3722}
3723
3724/**
3725 * ixgbe_tx_timeout - Respond to a Tx Hang
3726 * @netdev: network interface device structure
3727 **/
3728static void ixgbe_tx_timeout(struct net_device *netdev)
3729{
3730 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3731
3732 /* Do the reset outside of interrupt context */
3733 schedule_work(&adapter->reset_task);
3734}
3735
3736static void ixgbe_reset_task(struct work_struct *work)
3737{
3738 struct ixgbe_adapter *adapter;
3739 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3740
2f90b865
AD		 3741 /* If we're already down or resetting, just bail */
3742 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3743 test_bit(__IXGBE_RESETTING, &adapter->state))
3744 return;
3745
9a799d71
AK		 3746 adapter->tx_timeout_count++;
3747
dcd79aeb
TI		 3748 ixgbe_dump(adapter);
3749 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 3750 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3751}
3752
bc97114d
PWJ		 3753#ifdef CONFIG_IXGBE_DCB
3754static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3755{
bc97114d 3756 bool ret = false;
0cefafad 3757 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3758
0cefafad
JB		 3759 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3760 return ret;
3761
3762 f->mask = 0x7 << 3;
3763 adapter->num_rx_queues = f->indices;
3764 adapter->num_tx_queues = f->indices;
3765 ret = true;
2f90b865 3766
bc97114d
PWJ		 3767 return ret;
3768}
3769#endif
3770
4df10466
JB		 3771/**
3772 * ixgbe_set_rss_queues: Allocate queues for RSS
3773 * @adapter: board private structure to initialize
3774 *
3775 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3776 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3777 *
3778 **/
bc97114d
PWJ		 3779static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3780{
3781 bool ret = false;
0cefafad 3782 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3783
3784 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3785 f->mask = 0xF;
3786 adapter->num_rx_queues = f->indices;
3787 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3788 ret = true;
3789 } else {
bc97114d 3790 ret = false;
b9804972
JB		 3791 }
3792
bc97114d
PWJ		 3793 return ret;
3794}
3795
c4cf55e5
PWJ		 3796/**
3797 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3798 * @adapter: board private structure to initialize
3799 *
3800 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3801 * to the original CPU that initiated the Tx session. This runs in addition
3802 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3803 * Rx load across CPUs using RSS.
3804 *
3805 **/
3806static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3807{
3808 bool ret = false;
3809 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3810
3811 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3812 f_fdir->mask = 0;
3813
3814 /* Flow Director must have RSS enabled */
3815 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3816 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3817 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3818 adapter->num_tx_queues = f_fdir->indices;
3819 adapter->num_rx_queues = f_fdir->indices;
3820 ret = true;
3821 } else {
3822 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3823 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3824 }
3825 return ret;
3826}
3827
0331a832
YZ		 3828#ifdef IXGBE_FCOE
3829/**
3830 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3831 * @adapter: board private structure to initialize
3832 *
3833 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3834 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3835 * rx queues out of the max number of rx queues, instead, it is used as the
3836 * index of the first rx queue used by FCoE.
3837 *
3838 **/
3839static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3840{
3841 bool ret = false;
3842 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3843
3844 f->indices = min((int)num_online_cpus(), f->indices);
3845 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3846 adapter->num_rx_queues = 1;
3847 adapter->num_tx_queues = 1;
0331a832
YZ		 3848#ifdef CONFIG_IXGBE_DCB
3849 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
d6dbee86 3850 DPRINTK(PROBE, INFO, "FCoE enabled with DCB\n");
0331a832
YZ		 3851 ixgbe_set_dcb_queues(adapter);
3852 }
3853#endif
3854 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
d6dbee86 3855 DPRINTK(PROBE, INFO, "FCoE enabled with RSS\n");
8faa2a78
YZ		 3856 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3857 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3858 ixgbe_set_fdir_queues(adapter);
3859 else
3860 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3861 }
3862 /* adding FCoE rx rings to the end */
3863 f->mask = adapter->num_rx_queues;
3864 adapter->num_rx_queues += f->indices;
8de8b2e6 3865 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3866
3867 ret = true;
3868 }
3869
3870 return ret;
3871}
3872
3873#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3874/**
3875 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3876 * @adapter: board private structure to initialize
3877 *
3878 * IOV doesn't actually use anything, so just NAK the
3879 * request for now and let the other queue routines
3880 * figure out what to do.
3881 */
3882static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3883{
3884 return false;
3885}
3886
4df10466
JB		 3887/*
3888 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3889 * @adapter: board private structure to initialize
3890 *
3891 * This is the top level queue allocation routine. The order here is very
3892 * important, starting with the "most" number of features turned on at once,
3893 * and ending with the smallest set of features. This way large combinations
3894 * can be allocated if they're turned on, and smaller combinations are the
3895 * fallthrough conditions.
3896 *
3897 **/
bc97114d
PWJ		 3898static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3899{
1cdd1ec8
GR		 3900 /* Start with base case */
3901 adapter->num_rx_queues = 1;
3902 adapter->num_tx_queues = 1;
3903 adapter->num_rx_pools = adapter->num_rx_queues;
3904 adapter->num_rx_queues_per_pool = 1;
3905
3906 if (ixgbe_set_sriov_queues(adapter))
3907 return;
3908
0331a832
YZ		 3909#ifdef IXGBE_FCOE
3910 if (ixgbe_set_fcoe_queues(adapter))
3911 goto done;
3912
3913#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3914#ifdef CONFIG_IXGBE_DCB
3915 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3916 goto done;
bc97114d
PWJ		 3917
3918#endif
c4cf55e5
PWJ		 3919 if (ixgbe_set_fdir_queues(adapter))
3920 goto done;
3921
bc97114d 3922 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3923 goto done;
3924
3925 /* fallback to base case */
3926 adapter->num_rx_queues = 1;
3927 adapter->num_tx_queues = 1;
3928
3929done:
3930 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3931 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3932}
3933
021230d4 3934static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3935 int vectors)
021230d4
AV		 3936{
3937 int err, vector_threshold;
3938
3939 /* We'll want at least 3 (vector_threshold):
3940 * 1) TxQ[0] Cleanup
3941 * 2) RxQ[0] Cleanup
3942 * 3) Other (Link Status Change, etc.)
3943 * 4) TCP Timer (optional)
3944 */
3945 vector_threshold = MIN_MSIX_COUNT;
3946
3947 /* The more we get, the more we will assign to Tx/Rx Cleanup
3948 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3949 * Right now, we simply care about how many we'll get; we'll
3950 * set them up later while requesting irq's.
3951 */
3952 while (vectors >= vector_threshold) {
3953 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3954 vectors);
021230d4
AV		 3955 if (!err) /* Success in acquiring all requested vectors. */
3956 break;
3957 else if (err < 0)
3958 vectors = 0; /* Nasty failure, quit now */
3959 else /* err == number of vectors we should try again with */
3960 vectors = err;
3961 }
3962
3963 if (vectors < vector_threshold) {
3964 /* Can't allocate enough MSI-X interrupts? Oh well.
3965 * This just means we'll go with either a single MSI
3966 * vector or fall back to legacy interrupts.
3967 */
3968 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3969 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3970 kfree(adapter->msix_entries);
3971 adapter->msix_entries = NULL;
021230d4
AV		 3972 } else {
3973 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3974 /*
3975 * Adjust for only the vectors we'll use, which is minimum
3976 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3977 * vectors we were allocated.
3978 */
3979 adapter->num_msix_vectors = min(vectors,
3980 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3981 }
3982}
3983
021230d4 3984/**
bc97114d 3985 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3986 * @adapter: board private structure to initialize
3987 *
bc97114d
PWJ		 3988 * Cache the descriptor ring offsets for RSS to the assigned rings.
3989 *
021230d4 3990 **/
bc97114d 3991static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3992{
bc97114d
PWJ		 3993 int i;
3994 bool ret = false;
3995
3996 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3997 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3998 adapter->rx_ring[i]->reg_idx = i;
bc97114d 3999 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4000 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 4001 ret = true;
4002 } else {
4003 ret = false;
4004 }
4005
4006 return ret;
4007}
4008
4009#ifdef CONFIG_IXGBE_DCB
4010/**
4011 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4012 * @adapter: board private structure to initialize
4013 *
4014 * Cache the descriptor ring offsets for DCB to the assigned rings.
4015 *
4016 **/
4017static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4018{
4019 int i;
4020 bool ret = false;
4021 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4022
4023 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4024 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 4025 /* the number of queues is assumed to be symmetric */
4026 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 4027 adapter->rx_ring[i]->reg_idx = i << 3;
4028 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 4029 }
bc97114d 4030 ret = true;
e8e26350 4031 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 4032 if (dcb_i == 8) {
4033 /*
4034 * Tx TC0 starts at: descriptor queue 0
4035 * Tx TC1 starts at: descriptor queue 32
4036 * Tx TC2 starts at: descriptor queue 64
4037 * Tx TC3 starts at: descriptor queue 80
4038 * Tx TC4 starts at: descriptor queue 96
4039 * Tx TC5 starts at: descriptor queue 104
4040 * Tx TC6 starts at: descriptor queue 112
4041 * Tx TC7 starts at: descriptor queue 120
4042 *
4043 * Rx TC0-TC7 are offset by 16 queues each
4044 */
4045 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 4046 adapter->tx_ring[i]->reg_idx = i << 5;
4047 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4048 }
4049 for ( ; i < 5; i++) {
4a0b9ca0 4050 adapter->tx_ring[i]->reg_idx =
f92ef202 4051 ((i + 2) << 4);
4a0b9ca0 4052 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4053 }
4054 for ( ; i < dcb_i; i++) {
4a0b9ca0 4055 adapter->tx_ring[i]->reg_idx =
f92ef202 4056 ((i + 8) << 3);
4a0b9ca0 4057 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4058 }
4059
4060 ret = true;
4061 } else if (dcb_i == 4) {
4062 /*
4063 * Tx TC0 starts at: descriptor queue 0
4064 * Tx TC1 starts at: descriptor queue 64
4065 * Tx TC2 starts at: descriptor queue 96
4066 * Tx TC3 starts at: descriptor queue 112
4067 *
4068 * Rx TC0-TC3 are offset by 32 queues each
4069 */
4a0b9ca0
PW		 4070 adapter->tx_ring[0]->reg_idx = 0;
4071 adapter->tx_ring[1]->reg_idx = 64;
4072 adapter->tx_ring[2]->reg_idx = 96;
4073 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 4074 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 4075 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 4076
4077 ret = true;
4078 } else {
4079 ret = false;
e8e26350 4080 }
bc97114d
PWJ		 4081 } else {
4082 ret = false;
021230d4 4083 }
bc97114d
PWJ		 4084 } else {
4085 ret = false;
021230d4 4086 }
bc97114d
PWJ		 4087
4088 return ret;
4089}
4090#endif
4091
c4cf55e5
PWJ		 4092/**
4093 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4094 * @adapter: board private structure to initialize
4095 *
4096 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4097 *
4098 **/
4099static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4100{
4101 int i;
4102 bool ret = false;
4103
4104 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4105 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4106 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4107 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4108 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4109 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4110 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4111 ret = true;
4112 }
4113
4114 return ret;
4115}
4116
0331a832
YZ		 4117#ifdef IXGBE_FCOE
4118/**
4119 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4120 * @adapter: board private structure to initialize
4121 *
4122 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4123 *
4124 */
4125static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4126{
8de8b2e6 4127 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 4128 bool ret = false;
4129 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4130
4131 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4132#ifdef CONFIG_IXGBE_DCB
4133 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 4134 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4135
0331a832 4136 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 4137 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 4138 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4139 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 4140 /*
4141 * In 82599, the number of Tx queues for each traffic
4142 * class for both 8-TC and 4-TC modes are:
4143 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4144 * 8 TCs: 32 32 16 16 8 8 8 8
4145 * 4 TCs: 64 64 32 32
4146 * We have max 8 queues for FCoE, where 8 the is
4147 * FCoE redirection table size. If TC for FCoE is
4148 * less than or equal to TC3, we have enough queues
4149 * to add max of 8 queues for FCoE, so we start FCoE
4150 * tx descriptor from the next one, i.e., reg_idx + 1.
4151 * If TC for FCoE is above TC3, implying 8 TC mode,
4152 * and we need 8 for FCoE, we have to take all queues
4153 * in that traffic class for FCoE.
4154 */
4155 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4156 fcoe_tx_i--;
0331a832
YZ		 4157 }
4158#endif /* CONFIG_IXGBE_DCB */
4159 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 4160 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4161 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4162 ixgbe_cache_ring_fdir(adapter);
4163 else
4164 ixgbe_cache_ring_rss(adapter);
4165
8de8b2e6
YZ		 4166 fcoe_rx_i = f->mask;
4167 fcoe_tx_i = f->mask;
4168 }
4169 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 4170 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4171 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 4172 }
0331a832
YZ		 4173 ret = true;
4174 }
4175 return ret;
4176}
4177
4178#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4179/**
4180 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4181 * @adapter: board private structure to initialize
4182 *
4183 * SR-IOV doesn't use any descriptor rings but changes the default if
4184 * no other mapping is used.
4185 *
4186 */
4187static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4188{
4a0b9ca0
PW		 4189 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4190 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4191 if (adapter->num_vfs)
4192 return true;
4193 else
4194 return false;
4195}
4196
bc97114d
PWJ		 4197/**
4198 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4199 * @adapter: board private structure to initialize
4200 *
4201 * Once we know the feature-set enabled for the device, we'll cache
4202 * the register offset the descriptor ring is assigned to.
4203 *
4204 * Note, the order the various feature calls is important. It must start with
4205 * the "most" features enabled at the same time, then trickle down to the
4206 * least amount of features turned on at once.
4207 **/
4208static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4209{
4210 /* start with default case */
4a0b9ca0
PW		 4211 adapter->rx_ring[0]->reg_idx = 0;
4212 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4213
1cdd1ec8
GR		 4214 if (ixgbe_cache_ring_sriov(adapter))
4215 return;
4216
0331a832
YZ		 4217#ifdef IXGBE_FCOE
4218 if (ixgbe_cache_ring_fcoe(adapter))
4219 return;
4220
4221#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4222#ifdef CONFIG_IXGBE_DCB
4223 if (ixgbe_cache_ring_dcb(adapter))
4224 return;
4225
4226#endif
c4cf55e5
PWJ		 4227 if (ixgbe_cache_ring_fdir(adapter))
4228 return;
4229
bc97114d
PWJ		 4230 if (ixgbe_cache_ring_rss(adapter))
4231 return;
021230d4
AV		 4232}
4233
9a799d71
AK		 4234/**
4235 * ixgbe_alloc_queues - Allocate memory for all rings
4236 * @adapter: board private structure to initialize
4237 *
4238 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4239 * number of queues at compile-time. The polling_netdev array is
4240 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4241 **/
2f90b865 4242static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 4243{
4244 int i;
4a0b9ca0 4245 int orig_node = adapter->node;
9a799d71 4246
021230d4 4247 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 4248 struct ixgbe_ring *ring = adapter->tx_ring[i];
4249 if (orig_node == -1) {
4250 int cur_node = next_online_node(adapter->node);
4251 if (cur_node == MAX_NUMNODES)
4252 cur_node = first_online_node;
4253 adapter->node = cur_node;
4254 }
4255 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4256 adapter->node);
4257 if (!ring)
4258 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4259 if (!ring)
4260 goto err_tx_ring_allocation;
4261 ring->count = adapter->tx_ring_count;
4262 ring->queue_index = i;
4263 ring->numa_node = adapter->node;
4264
4265 adapter->tx_ring[i] = ring;
021230d4 4266 }
b9804972 4267
4a0b9ca0
PW		 4268 /* Restore the adapter's original node */
4269 adapter->node = orig_node;
4270
9a799d71 4271 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4272 struct ixgbe_ring *ring = adapter->rx_ring[i];
4273 if (orig_node == -1) {
4274 int cur_node = next_online_node(adapter->node);
4275 if (cur_node == MAX_NUMNODES)
4276 cur_node = first_online_node;
4277 adapter->node = cur_node;
4278 }
4279 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4280 adapter->node);
4281 if (!ring)
4282 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4283 if (!ring)
4284 goto err_rx_ring_allocation;
4285 ring->count = adapter->rx_ring_count;
4286 ring->queue_index = i;
4287 ring->numa_node = adapter->node;
4288
4289 adapter->rx_ring[i] = ring;
021230d4
AV		 4290 }
4291
4a0b9ca0
PW		 4292 /* Restore the adapter's original node */
4293 adapter->node = orig_node;
4294
021230d4
AV		 4295 ixgbe_cache_ring_register(adapter);
4296
4297 return 0;
4298
4299err_rx_ring_allocation:
4a0b9ca0
PW		 4300 for (i = 0; i < adapter->num_tx_queues; i++)
4301 kfree(adapter->tx_ring[i]);
021230d4
AV		 4302err_tx_ring_allocation:
4303 return -ENOMEM;
4304}
4305
4306/**
4307 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4308 * @adapter: board private structure to initialize
4309 *
4310 * Attempt to configure the interrupts using the best available
4311 * capabilities of the hardware and the kernel.
4312 **/
feea6a57 4313static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4314{
8be0e467 4315 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4316 int err = 0;
4317 int vector, v_budget;
4318
4319 /*
4320 * It's easy to be greedy for MSI-X vectors, but it really
4321 * doesn't do us much good if we have a lot more vectors
4322 * than CPU's. So let's be conservative and only ask for
342bde1b 4323 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4324 */
4325 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 4326 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4327
4328 /*
4329 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4330 * hw.mac->max_msix_vectors vectors. With features
4331 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4332 * descriptor queues supported by our device. Thus, we cap it off in
4333 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4334 */
8be0e467 4335 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4336
4337 /* A failure in MSI-X entry allocation isn't fatal, but it does
4338 * mean we disable MSI-X capabilities of the adapter. */
4339 adapter->msix_entries = kcalloc(v_budget,
b4617240 4340 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4341 if (adapter->msix_entries) {
4342 for (vector = 0; vector < v_budget; vector++)
4343 adapter->msix_entries[vector].entry = vector;
021230d4 4344
7a921c93 4345 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4346
7a921c93
AD		 4347 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4348 goto out;
4349 }
26d27844 4350
7a921c93
AD		 4351 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4352 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4353 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4354 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4355 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4356 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4357 ixgbe_disable_sriov(adapter);
4358
7a921c93 4359 ixgbe_set_num_queues(adapter);
021230d4 4360
021230d4
AV		 4361 err = pci_enable_msi(adapter->pdev);
4362 if (!err) {
4363 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4364 } else {
4365 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 4366 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4367 /* reset err */
4368 err = 0;
4369 }
4370
4371out:
021230d4
AV		 4372 return err;
4373}
4374
7a921c93
AD		 4375/**
4376 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4377 * @adapter: board private structure to initialize
4378 *
4379 * We allocate one q_vector per queue interrupt. If allocation fails we
4380 * return -ENOMEM.
4381 **/
4382static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4383{
4384 int q_idx, num_q_vectors;
4385 struct ixgbe_q_vector *q_vector;
4386 int napi_vectors;
4387 int (*poll)(struct napi_struct *, int);
4388
4389 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4390 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4391 napi_vectors = adapter->num_rx_queues;
91281fd3 4392 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4393 } else {
4394 num_q_vectors = 1;
4395 napi_vectors = 1;
4396 poll = &ixgbe_poll;
4397 }
4398
4399 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2
JB		 4400 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4401 GFP_KERNEL, adapter->node);
4402 if (!q_vector)
4403 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4404 GFP_KERNEL);
7a921c93
AD		 4405 if (!q_vector)
4406 goto err_out;
4407 q_vector->adapter = adapter;
f7554a2b
NS		 4408 if (q_vector->txr_count && !q_vector->rxr_count)
4409 q_vector->eitr = adapter->tx_eitr_param;
4410 else
4411 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4412 q_vector->v_idx = q_idx;
91281fd3 4413 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4414 adapter->q_vector[q_idx] = q_vector;
4415 }
4416
4417 return 0;
4418
4419err_out:
4420 while (q_idx) {
4421 q_idx--;
4422 q_vector = adapter->q_vector[q_idx];
4423 netif_napi_del(&q_vector->napi);
4424 kfree(q_vector);
4425 adapter->q_vector[q_idx] = NULL;
4426 }
4427 return -ENOMEM;
4428}
4429
4430/**
4431 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4432 * @adapter: board private structure to initialize
4433 *
4434 * This function frees the memory allocated to the q_vectors. In addition if
4435 * NAPI is enabled it will delete any references to the NAPI struct prior
4436 * to freeing the q_vector.
4437 **/
4438static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4439{
4440 int q_idx, num_q_vectors;
7a921c93 4441
91281fd3 4442 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4443 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4444 else
7a921c93 4445 num_q_vectors = 1;
7a921c93
AD		 4446
4447 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4448 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4449 adapter->q_vector[q_idx] = NULL;
91281fd3 4450 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4451 kfree(q_vector);
4452 }
4453}
4454
7b25cdba 4455static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4456{
4457 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4458 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4459 pci_disable_msix(adapter->pdev);
4460 kfree(adapter->msix_entries);
4461 adapter->msix_entries = NULL;
4462 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4463 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4464 pci_disable_msi(adapter->pdev);
4465 }
021230d4
AV		 4466}
4467
4468/**
4469 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4470 * @adapter: board private structure to initialize
4471 *
4472 * We determine which interrupt scheme to use based on...
4473 * - Kernel support (MSI, MSI-X)
4474 * - which can be user-defined (via MODULE_PARAM)
4475 * - Hardware queue count (num_*_queues)
4476 * - defined by miscellaneous hardware support/features (RSS, etc.)
4477 **/
2f90b865 4478int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4479{
4480 int err;
4481
4482 /* Number of supported queues */
4483 ixgbe_set_num_queues(adapter);
4484
021230d4
AV		 4485 err = ixgbe_set_interrupt_capability(adapter);
4486 if (err) {
4487 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4488 goto err_set_interrupt;
9a799d71
AK		 4489 }
4490
7a921c93
AD		 4491 err = ixgbe_alloc_q_vectors(adapter);
4492 if (err) {
4493 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4494 "vectors\n");
4495 goto err_alloc_q_vectors;
4496 }
4497
4498 err = ixgbe_alloc_queues(adapter);
4499 if (err) {
4500 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4501 goto err_alloc_queues;
4502 }
4503
021230d4 4504 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 4505 "Tx Queue count = %u\n",
4506 (adapter->num_rx_queues > 1) ? "Enabled" :
4507 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4508
4509 set_bit(__IXGBE_DOWN, &adapter->state);
4510
9a799d71 4511 return 0;
021230d4 4512
7a921c93
AD		 4513err_alloc_queues:
4514 ixgbe_free_q_vectors(adapter);
4515err_alloc_q_vectors:
4516 ixgbe_reset_interrupt_capability(adapter);
021230d4 4517err_set_interrupt:
7a921c93
AD		 4518 return err;
4519}
4520
4521/**
4522 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4523 * @adapter: board private structure to clear interrupt scheme on
4524 *
4525 * We go through and clear interrupt specific resources and reset the structure
4526 * to pre-load conditions
4527 **/
4528void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4529{
4a0b9ca0
PW		 4530 int i;
4531
4532 for (i = 0; i < adapter->num_tx_queues; i++) {
4533 kfree(adapter->tx_ring[i]);
4534 adapter->tx_ring[i] = NULL;
4535 }
4536 for (i = 0; i < adapter->num_rx_queues; i++) {
4537 kfree(adapter->rx_ring[i]);
4538 adapter->rx_ring[i] = NULL;
4539 }
7a921c93
AD		 4540
4541 ixgbe_free_q_vectors(adapter);
4542 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4543}
4544
c4900be0
DS		 4545/**
4546 * ixgbe_sfp_timer - worker thread to find a missing module
4547 * @data: pointer to our adapter struct
4548 **/
4549static void ixgbe_sfp_timer(unsigned long data)
4550{
4551 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4552
4df10466
JB		 4553 /*
4554 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4555 * delays that sfp+ detection requires
4556 */
4557 schedule_work(&adapter->sfp_task);
4558}
4559
4560/**
4561 * ixgbe_sfp_task - worker thread to find a missing module
4562 * @work: pointer to work_struct containing our data
4563 **/
4564static void ixgbe_sfp_task(struct work_struct *work)
4565{
4566 struct ixgbe_adapter *adapter = container_of(work,
4567 struct ixgbe_adapter,
4568 sfp_task);
4569 struct ixgbe_hw *hw = &adapter->hw;
4570
4571 if ((hw->phy.type == ixgbe_phy_nl) &&
4572 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4573 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4574 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4575 goto reschedule;
4576 ret = hw->phy.ops.reset(hw);
4577 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4578 dev_err(&adapter->pdev->dev, "failed to initialize "
4579 "because an unsupported SFP+ module type "
4580 "was detected.\n"
4581 "Reload the driver after installing a "
4582 "supported module.\n");
c4900be0
DS		 4583 unregister_netdev(adapter->netdev);
4584 } else {
4585 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4586 hw->phy.sfp_type);
4587 }
4588 /* don't need this routine any more */
4589 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4590 }
4591 return;
4592reschedule:
4593 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4594 mod_timer(&adapter->sfp_timer,
4595 round_jiffies(jiffies + (2 * HZ)));
4596}
4597
9a799d71
AK		 4598/**
4599 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4600 * @adapter: board private structure to initialize
4601 *
4602 * ixgbe_sw_init initializes the Adapter private data structure.
4603 * Fields are initialized based on PCI device information and
4604 * OS network device settings (MTU size).
4605 **/
4606static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4607{
4608 struct ixgbe_hw *hw = &adapter->hw;
4609 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4610 struct net_device *dev = adapter->netdev;
021230d4 4611 unsigned int rss;
7a6b6f51 4612#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4613 int j;
4614 struct tc_configuration *tc;
4615#endif
021230d4 4616
c44ade9e
JB		 4617 /* PCI config space info */
4618
4619 hw->vendor_id = pdev->vendor;
4620 hw->device_id = pdev->device;
4621 hw->revision_id = pdev->revision;
4622 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4623 hw->subsystem_device_id = pdev->subsystem_device;
4624
021230d4
AV		 4625 /* Set capability flags */
4626 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4627 adapter->ring_feature[RING_F_RSS].indices = rss;
4628 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4629 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4630 if (hw->mac.type == ixgbe_mac_82598EB) {
4631 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4632 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4633 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4634 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4635 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4636 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4637 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9a713e7c
PW		 4638 if (dev->features & NETIF_F_NTUPLE) {
4639 /* Flow Director perfect filter enabled */
4640 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4641 adapter->atr_sample_rate = 0;
4642 spin_lock_init(&adapter->fdir_perfect_lock);
4643 } else {
4644 /* Flow Director hash filters enabled */
4645 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4646 adapter->atr_sample_rate = 20;
4647 }
c4cf55e5
PWJ		 4648 adapter->ring_feature[RING_F_FDIR].indices =
4649 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4650 adapter->fdir_pballoc = 0;
eacd73f7 4651#ifdef IXGBE_FCOE
0d551589
YZ		 4652 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4653 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4654 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4655#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4656 /* Default traffic class to use for FCoE */
4657 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
61a0f421 4658#endif
eacd73f7 4659#endif /* IXGBE_FCOE */
f8212f97 4660 }
2f90b865 4661
7a6b6f51 4662#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4663 /* Configure DCB traffic classes */
4664 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4665 tc = &adapter->dcb_cfg.tc_config[j];
4666 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4667 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4668 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4669 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4670 tc->dcb_pfc = pfc_disabled;
4671 }
4672 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4673 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4674 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4675 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4676 adapter->dcb_cfg.round_robin_enable = false;
4677 adapter->dcb_set_bitmap = 0x00;
4678 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4679 adapter->ring_feature[RING_F_DCB].indices);
4680
4681#endif
9a799d71
AK		 4682
4683 /* default flow control settings */
cd7664f6 4684 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4685 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4686#ifdef CONFIG_DCB
4687 adapter->last_lfc_mode = hw->fc.current_mode;
4688#endif
2b9ade93
JB		 4689 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4690 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4691 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4692 hw->fc.send_xon = true;
71fd570b 4693 hw->fc.disable_fc_autoneg = false;
9a799d71 4694
30efa5a3 4695 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4696 adapter->rx_itr_setting = 1;
4697 adapter->rx_eitr_param = 20000;
4698 adapter->tx_itr_setting = 1;
4699 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4700
4701 /* set defaults for eitr in MegaBytes */
4702 adapter->eitr_low = 10;
4703 adapter->eitr_high = 20;
4704
4705 /* set default ring sizes */
4706 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4707 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4708
9a799d71 4709 /* initialize eeprom parameters */
c44ade9e 4710 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 4711 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4712 return -EIO;
4713 }
4714
021230d4 4715 /* enable rx csum by default */
9a799d71
AK		 4716 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4717
1a6c14a2
JB		 4718 /* get assigned NUMA node */
4719 adapter->node = dev_to_node(&pdev->dev);
4720
9a799d71
AK		 4721 set_bit(__IXGBE_DOWN, &adapter->state);
4722
4723 return 0;
4724}
4725
4726/**
4727 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4728 * @adapter: board private structure
3a581073 4729 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4730 *
4731 * Return 0 on success, negative on failure
4732 **/
4733int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4734 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4735{
4736 struct pci_dev *pdev = adapter->pdev;
4737 int size;
4738
3a581073 4739 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4740 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4741 if (!tx_ring->tx_buffer_info)
4742 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4743 if (!tx_ring->tx_buffer_info)
4744 goto err;
3a581073 4745 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4746
4747 /* round up to nearest 4K */
12207e49 4748 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4749 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4750
1b507730
NN		 4751 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4752 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4753 if (!tx_ring->desc)
4754 goto err;
9a799d71 4755
3a581073
JB		 4756 tx_ring->next_to_use = 0;
4757 tx_ring->next_to_clean = 0;
4758 tx_ring->work_limit = tx_ring->count;
9a799d71 4759 return 0;
e01c31a5
JB		 4760
4761err:
4762 vfree(tx_ring->tx_buffer_info);
4763 tx_ring->tx_buffer_info = NULL;
4764 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4765 "descriptor ring\n");
4766 return -ENOMEM;
9a799d71
AK		 4767}
4768
69888674
AD		 4769/**
4770 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4771 * @adapter: board private structure
4772 *
4773 * If this function returns with an error, then it's possible one or
4774 * more of the rings is populated (while the rest are not). It is the
4775 * callers duty to clean those orphaned rings.
4776 *
4777 * Return 0 on success, negative on failure
4778 **/
4779static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4780{
4781 int i, err = 0;
4782
4783 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 4784 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 4785 if (!err)
4786 continue;
4787 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4788 break;
4789 }
4790
4791 return err;
4792}
4793
9a799d71
AK		 4794/**
4795 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4796 * @adapter: board private structure
3a581073 4797 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4798 *
4799 * Returns 0 on success, negative on failure
4800 **/
4801int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4802 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4803{
4804 struct pci_dev *pdev = adapter->pdev;
021230d4 4805 int size;
9a799d71 4806
3a581073 4807 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 4808 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4809 if (!rx_ring->rx_buffer_info)
4810 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 4811 if (!rx_ring->rx_buffer_info) {
9a799d71 4812 DPRINTK(PROBE, ERR,
b4617240 4813 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 4814 goto alloc_failed;
9a799d71 4815 }
3a581073 4816 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4817
9a799d71 4818 /* Round up to nearest 4K */
3a581073
JB		 4819 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4820 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4821
1b507730
NN		 4822 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4823 &rx_ring->dma, GFP_KERNEL);
9a799d71 4824
3a581073 4825 if (!rx_ring->desc) {
9a799d71 4826 DPRINTK(PROBE, ERR,
b4617240 4827 "Memory allocation failed for the rx desc ring\n");
3a581073 4828 vfree(rx_ring->rx_buffer_info);
177db6ff 4829 goto alloc_failed;
9a799d71
AK		 4830 }
4831
3a581073
JB		 4832 rx_ring->next_to_clean = 0;
4833 rx_ring->next_to_use = 0;
9a799d71
AK		 4834
4835 return 0;
177db6ff
MC		 4836
4837alloc_failed:
177db6ff 4838 return -ENOMEM;
9a799d71
AK		 4839}
4840
69888674
AD		 4841/**
4842 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4843 * @adapter: board private structure
4844 *
4845 * If this function returns with an error, then it's possible one or
4846 * more of the rings is populated (while the rest are not). It is the
4847 * callers duty to clean those orphaned rings.
4848 *
4849 * Return 0 on success, negative on failure
4850 **/
4851
4852static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4853{
4854 int i, err = 0;
4855
4856 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 4857 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 4858 if (!err)
4859 continue;
4860 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4861 break;
4862 }
4863
4864 return err;
4865}
4866
9a799d71
AK		 4867/**
4868 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4869 * @adapter: board private structure
4870 * @tx_ring: Tx descriptor ring for a specific queue
4871 *
4872 * Free all transmit software resources
4873 **/
c431f97e
JB		 4874void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4875 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4876{
4877 struct pci_dev *pdev = adapter->pdev;
4878
4879 ixgbe_clean_tx_ring(adapter, tx_ring);
4880
4881 vfree(tx_ring->tx_buffer_info);
4882 tx_ring->tx_buffer_info = NULL;
4883
1b507730
NN		 4884 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
4885 tx_ring->dma);
9a799d71
AK		 4886
4887 tx_ring->desc = NULL;
4888}
4889
4890/**
4891 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4892 * @adapter: board private structure
4893 *
4894 * Free all transmit software resources
4895 **/
4896static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4897{
4898 int i;
4899
4900 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 4901 if (adapter->tx_ring[i]->desc)
4902 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 4903}
4904
4905/**
b4617240 4906 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4907 * @adapter: board private structure
4908 * @rx_ring: ring to clean the resources from
4909 *
4910 * Free all receive software resources
4911 **/
c431f97e
JB		 4912void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4913 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4914{
4915 struct pci_dev *pdev = adapter->pdev;
4916
4917 ixgbe_clean_rx_ring(adapter, rx_ring);
4918
4919 vfree(rx_ring->rx_buffer_info);
4920 rx_ring->rx_buffer_info = NULL;
4921
1b507730
NN		 4922 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
4923 rx_ring->dma);
9a799d71
AK		 4924
4925 rx_ring->desc = NULL;
4926}
4927
4928/**
4929 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4930 * @adapter: board private structure
4931 *
4932 * Free all receive software resources
4933 **/
4934static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4935{
4936 int i;
4937
4938 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 4939 if (adapter->rx_ring[i]->desc)
4940 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 4941}
4942
9a799d71
AK		 4943/**
4944 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4945 * @netdev: network interface device structure
4946 * @new_mtu: new value for maximum frame size
4947 *
4948 * Returns 0 on success, negative on failure
4949 **/
4950static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4951{
4952 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4953 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4954
42c783c5
JB		 4955 /* MTU < 68 is an error and causes problems on some kernels */
4956 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4957 return -EINVAL;
4958
021230d4 4959 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4960 netdev->mtu, new_mtu);
021230d4 4961 /* must set new MTU before calling down or up */
9a799d71
AK		 4962 netdev->mtu = new_mtu;
4963
d4f80882
AV		 4964 if (netif_running(netdev))
4965 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4966
4967 return 0;
4968}
4969
4970/**
4971 * ixgbe_open - Called when a network interface is made active
4972 * @netdev: network interface device structure
4973 *
4974 * Returns 0 on success, negative value on failure
4975 *
4976 * The open entry point is called when a network interface is made
4977 * active by the system (IFF_UP). At this point all resources needed
4978 * for transmit and receive operations are allocated, the interrupt
4979 * handler is registered with the OS, the watchdog timer is started,
4980 * and the stack is notified that the interface is ready.
4981 **/
4982static int ixgbe_open(struct net_device *netdev)
4983{
4984 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4985 int err;
4bebfaa5
AK		 4986
4987 /* disallow open during test */
4988 if (test_bit(__IXGBE_TESTING, &adapter->state))
4989 return -EBUSY;
9a799d71 4990
54386467
JB		 4991 netif_carrier_off(netdev);
4992
9a799d71
AK		 4993 /* allocate transmit descriptors */
4994 err = ixgbe_setup_all_tx_resources(adapter);
4995 if (err)
4996 goto err_setup_tx;
4997
9a799d71
AK		 4998 /* allocate receive descriptors */
4999 err = ixgbe_setup_all_rx_resources(adapter);
5000 if (err)
5001 goto err_setup_rx;
5002
5003 ixgbe_configure(adapter);
5004
021230d4 5005 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5006 if (err)
5007 goto err_req_irq;
5008
9a799d71
AK		 5009 err = ixgbe_up_complete(adapter);
5010 if (err)
5011 goto err_up;
5012
d55b53ff
JK		 5013 netif_tx_start_all_queues(netdev);
5014
9a799d71
AK		 5015 return 0;
5016
5017err_up:
5eba3699 5018 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5019 ixgbe_free_irq(adapter);
5020err_req_irq:
9a799d71 5021err_setup_rx:
a20a1199 5022 ixgbe_free_all_rx_resources(adapter);
9a799d71 5023err_setup_tx:
a20a1199 5024 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5025 ixgbe_reset(adapter);
5026
5027 return err;
5028}
5029
5030/**
5031 * ixgbe_close - Disables a network interface
5032 * @netdev: network interface device structure
5033 *
5034 * Returns 0, this is not allowed to fail
5035 *
5036 * The close entry point is called when an interface is de-activated
5037 * by the OS. The hardware is still under the drivers control, but
5038 * needs to be disabled. A global MAC reset is issued to stop the
5039 * hardware, and all transmit and receive resources are freed.
5040 **/
5041static int ixgbe_close(struct net_device *netdev)
5042{
5043 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5044
5045 ixgbe_down(adapter);
5046 ixgbe_free_irq(adapter);
5047
5048 ixgbe_free_all_tx_resources(adapter);
5049 ixgbe_free_all_rx_resources(adapter);
5050
5eba3699 5051 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5052
5053 return 0;
5054}
5055
b3c8b4ba
AD		 5056#ifdef CONFIG_PM
5057static int ixgbe_resume(struct pci_dev *pdev)
5058{
5059 struct net_device *netdev = pci_get_drvdata(pdev);
5060 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5061 u32 err;
5062
5063 pci_set_power_state(pdev, PCI_D0);
5064 pci_restore_state(pdev);
656ab817
DS		 5065 /*
5066 * pci_restore_state clears dev->state_saved so call
5067 * pci_save_state to restore it.
5068 */
5069 pci_save_state(pdev);
9ce77666 5070
5071 err = pci_enable_device_mem(pdev);
b3c8b4ba 5072 if (err) {
69888674 5073 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 5074 "suspend\n");
5075 return err;
5076 }
5077 pci_set_master(pdev);
5078
dd4d8ca6 5079 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5080
5081 err = ixgbe_init_interrupt_scheme(adapter);
5082 if (err) {
5083 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
5084 "device\n");
5085 return err;
5086 }
5087
b3c8b4ba
AD		 5088 ixgbe_reset(adapter);
5089
495dce12
WJP		 5090 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5091
b3c8b4ba
AD		 5092 if (netif_running(netdev)) {
5093 err = ixgbe_open(adapter->netdev);
5094 if (err)
5095 return err;
5096 }
5097
5098 netif_device_attach(netdev);
5099
5100 return 0;
5101}
b3c8b4ba 5102#endif /* CONFIG_PM */
9d8d05ae
RW		 5103
5104static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 5105{
5106 struct net_device *netdev = pci_get_drvdata(pdev);
5107 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 5108 struct ixgbe_hw *hw = &adapter->hw;
5109 u32 ctrl, fctrl;
5110 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5111#ifdef CONFIG_PM
5112 int retval = 0;
5113#endif
5114
5115 netif_device_detach(netdev);
5116
5117 if (netif_running(netdev)) {
5118 ixgbe_down(adapter);
5119 ixgbe_free_irq(adapter);
5120 ixgbe_free_all_tx_resources(adapter);
5121 ixgbe_free_all_rx_resources(adapter);
5122 }
7a921c93 5123 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 5124
5125#ifdef CONFIG_PM
5126 retval = pci_save_state(pdev);
5127 if (retval)
5128 return retval;
4df10466 5129
b3c8b4ba 5130#endif
e8e26350
PW		 5131 if (wufc) {
5132 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5133
e8e26350
PW		 5134 /* turn on all-multi mode if wake on multicast is enabled */
5135 if (wufc & IXGBE_WUFC_MC) {
5136 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5137 fctrl |= IXGBE_FCTRL_MPE;
5138 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5139 }
5140
5141 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5142 ctrl |= IXGBE_CTRL_GIO_DIS;
5143 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5144
5145 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5146 } else {
5147 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5148 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5149 }
5150
dd4d8ca6
DS		 5151 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5152 pci_wake_from_d3(pdev, true);
5153 else
5154 pci_wake_from_d3(pdev, false);
b3c8b4ba 5155
9d8d05ae
RW		 5156 *enable_wake = !!wufc;
5157
b3c8b4ba
AD		 5158 ixgbe_release_hw_control(adapter);
5159
5160 pci_disable_device(pdev);
5161
9d8d05ae
RW		 5162 return 0;
5163}
5164
5165#ifdef CONFIG_PM
5166static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5167{
5168 int retval;
5169 bool wake;
5170
5171 retval = __ixgbe_shutdown(pdev, &wake);
5172 if (retval)
5173 return retval;
5174
5175 if (wake) {
5176 pci_prepare_to_sleep(pdev);
5177 } else {
5178 pci_wake_from_d3(pdev, false);
5179 pci_set_power_state(pdev, PCI_D3hot);
5180 }
b3c8b4ba
AD		 5181
5182 return 0;
5183}
9d8d05ae 5184#endif /* CONFIG_PM */
b3c8b4ba
AD		 5185
5186static void ixgbe_shutdown(struct pci_dev *pdev)
5187{
9d8d05ae
RW		 5188 bool wake;
5189
5190 __ixgbe_shutdown(pdev, &wake);
5191
5192 if (system_state == SYSTEM_POWER_OFF) {
5193 pci_wake_from_d3(pdev, wake);
5194 pci_set_power_state(pdev, PCI_D3hot);
5195 }
b3c8b4ba
AD		 5196}
5197
9a799d71
AK		 5198/**
5199 * ixgbe_update_stats - Update the board statistics counters.
5200 * @adapter: board private structure
5201 **/
5202void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5203{
2d86f139 5204 struct net_device *netdev = adapter->netdev;
9a799d71 5205 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 5206 u64 total_mpc = 0;
5207 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 5208 u64 non_eop_descs = 0, restart_queue = 0;
9a799d71 5209
94b982b2 5210 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5211 u64 rsc_count = 0;
94b982b2 5212 u64 rsc_flush = 0;
d51019a4
PW		 5213 for (i = 0; i < 16; i++)
5214 adapter->hw_rx_no_dma_resources +=
5215 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5216 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 5217 rsc_count += adapter->rx_ring[i]->rsc_count;
5218 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 5219 }
5220 adapter->rsc_total_count = rsc_count;
5221 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5222 }
5223
7ca3bc58
JB		 5224 /* gather some stats to the adapter struct that are per queue */
5225 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5226 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 5227 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 5228
5229 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5230 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 5231 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 5232
9a799d71 5233 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5234 for (i = 0; i < 8; i++) {
5235 /* for packet buffers not used, the register should read 0 */
5236 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5237 missed_rx += mpc;
5238 adapter->stats.mpc[i] += mpc;
5239 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 5240 if (hw->mac.type == ixgbe_mac_82598EB)
5241 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 5242 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5243 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5244 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5245 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 5246 if (hw->mac.type == ixgbe_mac_82599EB) {
5247 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5248 IXGBE_PXONRXCNT(i));
5249 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5250 IXGBE_PXOFFRXCNT(i));
5251 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 5252 } else {
5253 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5254 IXGBE_PXONRXC(i));
5255 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5256 IXGBE_PXOFFRXC(i));
5257 }
2f90b865
AD		 5258 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5259 IXGBE_PXONTXC(i));
2f90b865 5260 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 5261 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 5262 }
5263 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5264 /* work around hardware counting issue */
5265 adapter->stats.gprc -= missed_rx;
5266
5267 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 5268 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 5269 u64 tmp;
e8e26350 5270 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 5271 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5272 adapter->stats.gorc += (tmp << 32);
e8e26350 5273 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 5274 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5275 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 5276 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5277 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5278 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5279 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 5280 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5281 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 5282#ifdef IXGBE_FCOE
5283 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5284 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5285 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5286 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5287 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5288 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5289#endif /* IXGBE_FCOE */
e8e26350
PW		 5290 } else {
5291 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5292 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5293 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5294 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5295 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5296 }
9a799d71
AK		 5297 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5298 adapter->stats.bprc += bprc;
5299 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 5300 if (hw->mac.type == ixgbe_mac_82598EB)
5301 adapter->stats.mprc -= bprc;
9a799d71
AK		 5302 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5303 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5304 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5305 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5306 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5307 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5308 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 5309 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 5310 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5311 adapter->stats.lxontxc += lxon;
5312 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5313 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 5314 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5315 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 5316 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5317 /*
5318 * 82598 errata - tx of flow control packets is included in tx counters
5319 */
5320 xon_off_tot = lxon + lxoff;
5321 adapter->stats.gptc -= xon_off_tot;
5322 adapter->stats.mptc -= xon_off_tot;
5323 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 5324 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5325 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5326 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 5327 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5328 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 5329 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 5330 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5331 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5332 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5333 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5334 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 5335 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5336
5337 /* Fill out the OS statistics structure */
2d86f139 5338 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 5339
5340 /* Rx Errors */
2d86f139 5341 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 5342 adapter->stats.rlec;
2d86f139
AK		 5343 netdev->stats.rx_dropped = 0;
5344 netdev->stats.rx_length_errors = adapter->stats.rlec;
5345 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5346 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5347}
5348
5349/**
5350 * ixgbe_watchdog - Timer Call-back
5351 * @data: pointer to adapter cast into an unsigned long
5352 **/
5353static void ixgbe_watchdog(unsigned long data)
5354{
5355 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5356 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5357 u64 eics = 0;
5358 int i;
cf8280ee 5359
fe49f04a
AD		 5360 /*
5361 * Do the watchdog outside of interrupt context due to the lovely
5362 * delays that some of the newer hardware requires
5363 */
22d5a71b 5364
fe49f04a
AD		 5365 if (test_bit(__IXGBE_DOWN, &adapter->state))
5366 goto watchdog_short_circuit;
22d5a71b 5367
fe49f04a
AD		 5368 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5369 /*
5370 * for legacy and MSI interrupts don't set any bits
5371 * that are enabled for EIAM, because this operation
5372 * would set *both* EIMS and EICS for any bit in EIAM
5373 */
5374 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5375 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5376 goto watchdog_reschedule;
5377 }
5378
5379 /* get one bit for every active tx/rx interrupt vector */
5380 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5381 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5382 if (qv->rxr_count || qv->txr_count)
5383 eics |= ((u64)1 << i);
cf8280ee 5384 }
9a799d71 5385
fe49f04a
AD		 5386 /* Cause software interrupt to ensure rx rings are cleaned */
5387 ixgbe_irq_rearm_queues(adapter, eics);
5388
5389watchdog_reschedule:
5390 /* Reset the timer */
5391 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5392
5393watchdog_short_circuit:
cf8280ee
JB		 5394 schedule_work(&adapter->watchdog_task);
5395}
5396
e8e26350
PW		 5397/**
5398 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5399 * @work: pointer to work_struct containing our data
5400 **/
5401static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5402{
5403 struct ixgbe_adapter *adapter = container_of(work,
5404 struct ixgbe_adapter,
5405 multispeed_fiber_task);
5406 struct ixgbe_hw *hw = &adapter->hw;
5407 u32 autoneg;
8620a103 5408 bool negotiation;
e8e26350
PW		 5409
5410 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5411 autoneg = hw->phy.autoneg_advertised;
5412 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5413 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5414 hw->mac.autotry_restart = false;
8620a103
MC		 5415 if (hw->mac.ops.setup_link)
5416 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5417 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5418 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5419}
5420
5421/**
5422 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5423 * @work: pointer to work_struct containing our data
5424 **/
5425static void ixgbe_sfp_config_module_task(struct work_struct *work)
5426{
5427 struct ixgbe_adapter *adapter = container_of(work,
5428 struct ixgbe_adapter,
5429 sfp_config_module_task);
5430 struct ixgbe_hw *hw = &adapter->hw;
5431 u32 err;
5432
5433 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5434
5435 /* Time for electrical oscillations to settle down */
5436 msleep(100);
e8e26350 5437 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5438
e8e26350 5439 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5440 dev_err(&adapter->pdev->dev, "failed to initialize because "
5441 "an unsupported SFP+ module type was detected.\n"
5442 "Reload the driver after installing a supported "
5443 "module.\n");
63d6e1d8 5444 unregister_netdev(adapter->netdev);
e8e26350
PW		 5445 return;
5446 }
5447 hw->mac.ops.setup_sfp(hw);
5448
8d1c3c07 5449 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5450 /* This will also work for DA Twinax connections */
5451 schedule_work(&adapter->multispeed_fiber_task);
5452 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5453}
5454
c4cf55e5
PWJ		 5455/**
5456 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5457 * @work: pointer to work_struct containing our data
5458 **/
5459static void ixgbe_fdir_reinit_task(struct work_struct *work)
5460{
5461 struct ixgbe_adapter *adapter = container_of(work,
5462 struct ixgbe_adapter,
5463 fdir_reinit_task);
5464 struct ixgbe_hw *hw = &adapter->hw;
5465 int i;
5466
5467 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5468 for (i = 0; i < adapter->num_tx_queues; i++)
5469 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 5470 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5
PWJ		 5471 } else {
5472 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
d6dbee86 5473 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5474 }
5475 /* Done FDIR Re-initialization, enable transmits */
5476 netif_tx_start_all_queues(adapter->netdev);
5477}
5478
10eec955
JF		 5479static DEFINE_MUTEX(ixgbe_watchdog_lock);
5480
cf8280ee 5481/**
69888674
AD		 5482 * ixgbe_watchdog_task - worker thread to bring link up
5483 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5484 **/
5485static void ixgbe_watchdog_task(struct work_struct *work)
5486{
5487 struct ixgbe_adapter *adapter = container_of(work,
5488 struct ixgbe_adapter,
5489 watchdog_task);
5490 struct net_device *netdev = adapter->netdev;
5491 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5492 u32 link_speed;
5493 bool link_up;
bc59fcda
NS		 5494 int i;
5495 struct ixgbe_ring *tx_ring;
5496 int some_tx_pending = 0;
cf8280ee 5497
10eec955
JF		 5498 mutex_lock(&ixgbe_watchdog_lock);
5499
5500 link_up = adapter->link_up;
5501 link_speed = adapter->link_speed;
cf8280ee
JB		 5502
5503 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5504 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5505 if (link_up) {
5506#ifdef CONFIG_DCB
5507 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5508 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5509 hw->mac.ops.fc_enable(hw, i);
264857b8 5510 } else {
620fa036 5511 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5512 }
5513#else
620fa036 5514 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5515#endif
5516 }
5517
cf8280ee
JB		 5518 if (link_up ||
5519 time_after(jiffies, (adapter->link_check_timeout +
5520 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5521 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5522 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5523 }
5524 adapter->link_up = link_up;
5525 adapter->link_speed = link_speed;
5526 }
9a799d71
AK		 5527
5528 if (link_up) {
5529 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5530 bool flow_rx, flow_tx;
5531
5532 if (hw->mac.type == ixgbe_mac_82599EB) {
5533 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5534 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5535 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5536 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5537 } else {
5538 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5539 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5540 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5541 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5542 }
5543
a46e534b
JK		 5544 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5545 "Flow Control: %s\n",
5546 netdev->name,
5547 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5548 "10 Gbps" :
5549 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5550 "1 Gbps" : "unknown speed")),
e8e26350
PW		 5551 ((flow_rx && flow_tx) ? "RX/TX" :
5552 (flow_rx ? "RX" :
5553 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5554
5555 netif_carrier_on(netdev);
9a799d71
AK		 5556 } else {
5557 /* Force detection of hung controller */
5558 adapter->detect_tx_hung = true;
5559 }
5560 } else {
cf8280ee
JB		 5561 adapter->link_up = false;
5562 adapter->link_speed = 0;
9a799d71 5563 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 5564 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5565 netdev->name);
9a799d71 5566 netif_carrier_off(netdev);
9a799d71
AK		 5567 }
5568 }
5569
bc59fcda
NS		 5570 if (!netif_carrier_ok(netdev)) {
5571 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5572 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5573 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5574 some_tx_pending = 1;
5575 break;
5576 }
5577 }
5578
5579 if (some_tx_pending) {
5580 /* We've lost link, so the controller stops DMA,
5581 * but we've got queued Tx work that's never going
5582 * to get done, so reset controller to flush Tx.
5583 * (Do the reset outside of interrupt context).
5584 */
5585 schedule_work(&adapter->reset_task);
5586 }
5587 }
5588
9a799d71 5589 ixgbe_update_stats(adapter);
10eec955 5590 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5591}
5592
9a799d71 5593static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 5594 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5595 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5596{
5597 struct ixgbe_adv_tx_context_desc *context_desc;
5598 unsigned int i;
5599 int err;
5600 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5601 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5602 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5603
5604 if (skb_is_gso(skb)) {
5605 if (skb_header_cloned(skb)) {
5606 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5607 if (err)
5608 return err;
5609 }
5610 l4len = tcp_hdrlen(skb);
5611 *hdr_len += l4len;
5612
8327d000 5613 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5614 struct iphdr *iph = ip_hdr(skb);
5615 iph->tot_len = 0;
5616 iph->check = 0;
5617 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 5618 iph->daddr, 0,
5619 IPPROTO_TCP,
5620 0);
8e1e8a47 5621 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5622 ipv6_hdr(skb)->payload_len = 0;
5623 tcp_hdr(skb)->check =
5624 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 5625 &ipv6_hdr(skb)->daddr,
5626 0, IPPROTO_TCP, 0);
9a799d71
AK		 5627 }
5628
5629 i = tx_ring->next_to_use;
5630
5631 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5632 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5633
5634 /* VLAN MACLEN IPLEN */
5635 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5636 vlan_macip_lens |=
5637 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5638 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 5639 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5640 *hdr_len += skb_network_offset(skb);
5641 vlan_macip_lens |=
5642 (skb_transport_header(skb) - skb_network_header(skb));
5643 *hdr_len +=
5644 (skb_transport_header(skb) - skb_network_header(skb));
5645 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5646 context_desc->seqnum_seed = 0;
5647
5648 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5649 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 5650 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5651
8327d000 5652 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5653 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5654 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5655 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5656
5657 /* MSS L4LEN IDX */
9f8cdf4f 5658 mss_l4len_idx =
9a799d71
AK		 5659 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5660 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5661 /* use index 1 for TSO */
5662 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5663 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5664
5665 tx_buffer_info->time_stamp = jiffies;
5666 tx_buffer_info->next_to_watch = i;
5667
5668 i++;
5669 if (i == tx_ring->count)
5670 i = 0;
5671 tx_ring->next_to_use = i;
5672
5673 return true;
5674 }
5675 return false;
5676}
5677
5678static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 5679 struct ixgbe_ring *tx_ring,
5680 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5681{
5682 struct ixgbe_adv_tx_context_desc *context_desc;
5683 unsigned int i;
5684 struct ixgbe_tx_buffer *tx_buffer_info;
5685 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5686
5687 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5688 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5689 i = tx_ring->next_to_use;
5690 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5691 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5692
5693 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5694 vlan_macip_lens |=
5695 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5696 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 5697 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5698 if (skb->ip_summed == CHECKSUM_PARTIAL)
5699 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 5700 skb_network_header(skb));
9a799d71
AK		 5701
5702 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5703 context_desc->seqnum_seed = 0;
5704
5705 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 5706 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 5707
5708 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ca553980
GS		 5709 __be16 protocol;
5710
5711 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5712 const struct vlan_ethhdr *vhdr =
5713 (const struct vlan_ethhdr *)skb->data;
5714
5715 protocol = vhdr->h_vlan_encapsulated_proto;
5716 } else {
5717 protocol = skb->protocol;
5718 }
5719
5720 switch (protocol) {
09640e63 5721 case cpu_to_be16(ETH_P_IP):
9a799d71 5722 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 5723 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5724 type_tucmd_mlhl |=
b4617240 5725 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5726 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5727 type_tucmd_mlhl |=
5728 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5729 break;
09640e63 5730 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5731 /* XXX what about other V6 headers?? */
5732 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5733 type_tucmd_mlhl |=
b4617240 5734 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5735 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5736 type_tucmd_mlhl |=
5737 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5738 break;
41825d71
AK		 5739 default:
5740 if (unlikely(net_ratelimit())) {
5741 DPRINTK(PROBE, WARNING,
5742 "partial checksum but proto=%x!\n",
5743 skb->protocol);
5744 }
5745 break;
5746 }
9a799d71
AK		 5747 }
5748
5749 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5750 /* use index zero for tx checksum offload */
9a799d71
AK		 5751 context_desc->mss_l4len_idx = 0;
5752
5753 tx_buffer_info->time_stamp = jiffies;
5754 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5755
9a799d71
AK		 5756 i++;
5757 if (i == tx_ring->count)
5758 i = 0;
5759 tx_ring->next_to_use = i;
5760
5761 return true;
5762 }
9f8cdf4f 5763
9a799d71
AK		 5764 return false;
5765}
5766
5767static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5768 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5769 struct sk_buff *skb, u32 tx_flags,
5770 unsigned int first)
9a799d71 5771{
e5a43549 5772 struct pci_dev *pdev = adapter->pdev;
9a799d71 5773 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5774 unsigned int len;
5775 unsigned int total = skb->len;
9a799d71
AK		 5776 unsigned int offset = 0, size, count = 0, i;
5777 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5778 unsigned int f;
9a799d71
AK		 5779
5780 i = tx_ring->next_to_use;
5781
eacd73f7
YZ		 5782 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5783 /* excluding fcoe_crc_eof for FCoE */
5784 total -= sizeof(struct fcoe_crc_eof);
5785
5786 len = min(skb_headlen(skb), total);
9a799d71
AK		 5787 while (len) {
5788 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5789 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5790
5791 tx_buffer_info->length = size;
e5a43549 5792 tx_buffer_info->mapped_as_page = false;
1b507730 5793 tx_buffer_info->dma = dma_map_single(&pdev->dev,
e5a43549 5794 skb->data + offset,
1b507730
NN		 5795 size, DMA_TO_DEVICE);
5796 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 5797 goto dma_error;
9a799d71
AK		 5798 tx_buffer_info->time_stamp = jiffies;
5799 tx_buffer_info->next_to_watch = i;
5800
5801 len -= size;
eacd73f7 5802 total -= size;
9a799d71
AK		 5803 offset += size;
5804 count++;
44df32c5
AD		 5805
5806 if (len) {
5807 i++;
5808 if (i == tx_ring->count)
5809 i = 0;
5810 }
9a799d71
AK		 5811 }
5812
5813 for (f = 0; f < nr_frags; f++) {
5814 struct skb_frag_struct *frag;
5815
5816 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5817 len = min((unsigned int)frag->size, total);
e5a43549 5818 offset = frag->page_offset;
9a799d71
AK		 5819
5820 while (len) {
44df32c5
AD		 5821 i++;
5822 if (i == tx_ring->count)
5823 i = 0;
5824
9a799d71
AK		 5825 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5826 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5827
5828 tx_buffer_info->length = size;
1b507730 5829 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
e5a43549
AD		 5830 frag->page,
5831 offset, size,
1b507730 5832 DMA_TO_DEVICE);
e5a43549 5833 tx_buffer_info->mapped_as_page = true;
1b507730 5834 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 5835 goto dma_error;
9a799d71
AK		 5836 tx_buffer_info->time_stamp = jiffies;
5837 tx_buffer_info->next_to_watch = i;
5838
5839 len -= size;
eacd73f7 5840 total -= size;
9a799d71
AK		 5841 offset += size;
5842 count++;
9a799d71 5843 }
eacd73f7
YZ		 5844 if (total == 0)
5845 break;
9a799d71 5846 }
44df32c5 5847
9a799d71
AK		 5848 tx_ring->tx_buffer_info[i].skb = skb;
5849 tx_ring->tx_buffer_info[first].next_to_watch = i;
5850
e5a43549
AD		 5851 return count;
5852
5853dma_error:
5854 dev_err(&pdev->dev, "TX DMA map failed\n");
5855
5856 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5857 tx_buffer_info->dma = 0;
5858 tx_buffer_info->time_stamp = 0;
5859 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 5860 if (count)
5861 count--;
e5a43549
AD		 5862
5863 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f
RK		 5864 while (count--) {
5865 if (i==0)
e5a43549 5866 i += tx_ring->count;
c1fa347f 5867 i--;
e5a43549
AD		 5868 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5869 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5870 }
5871
e44d38e1 5872 return 0;
9a799d71
AK		 5873}
5874
5875static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 5876 struct ixgbe_ring *tx_ring,
5877 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 5878{
5879 union ixgbe_adv_tx_desc *tx_desc = NULL;
5880 struct ixgbe_tx_buffer *tx_buffer_info;
5881 u32 olinfo_status = 0, cmd_type_len = 0;
5882 unsigned int i;
5883 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5884
5885 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5886
5887 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5888
5889 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5890 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5891
5892 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5893 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5894
5895 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5896 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5897
4eeae6fd
PW		 5898 /* use index 1 context for tso */
5899 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5900 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5901 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 5902 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5903
5904 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5905 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5906 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5907
eacd73f7
YZ		 5908 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5909 olinfo_status |= IXGBE_ADVTXD_CC;
5910 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5911 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5912 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5913 }
5914
9a799d71
AK		 5915 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5916
5917 i = tx_ring->next_to_use;
5918 while (count--) {
5919 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5920 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5921 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5922 tx_desc->read.cmd_type_len =
b4617240 5923 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5924 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5925 i++;
5926 if (i == tx_ring->count)
5927 i = 0;
5928 }
5929
5930 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5931
5932 /*
5933 * Force memory writes to complete before letting h/w
5934 * know there are new descriptors to fetch. (Only
5935 * applicable for weak-ordered memory model archs,
5936 * such as IA-64).
5937 */
5938 wmb();
5939
5940 tx_ring->next_to_use = i;
5941 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5942}
5943
c4cf55e5
PWJ		 5944static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5945 int queue, u32 tx_flags)
5946{
5947 /* Right now, we support IPv4 only */
5948 struct ixgbe_atr_input atr_input;
5949 struct tcphdr *th;
c4cf55e5
PWJ		 5950 struct iphdr *iph = ip_hdr(skb);
5951 struct ethhdr *eth = (struct ethhdr *)skb->data;
5952 u16 vlan_id, src_port, dst_port, flex_bytes;
5953 u32 src_ipv4_addr, dst_ipv4_addr;
5954 u8 l4type = 0;
5955
5956 /* check if we're UDP or TCP */
5957 if (iph->protocol == IPPROTO_TCP) {
5958 th = tcp_hdr(skb);
5959 src_port = th->source;
5960 dst_port = th->dest;
5961 l4type |= IXGBE_ATR_L4TYPE_TCP;
5962 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 5963 } else {
5964 /* Unsupported L4 header, just bail here */
5965 return;
5966 }
5967
5968 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5969
5970 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5971 IXGBE_TX_FLAGS_VLAN_SHIFT;
5972 src_ipv4_addr = iph->saddr;
5973 dst_ipv4_addr = iph->daddr;
5974 flex_bytes = eth->h_proto;
5975
5976 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5977 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5978 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5979 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5980 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5981 /* src and dst are inverted, think how the receiver sees them */
5982 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5983 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5984
5985 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5986 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5987}
5988
e092be60 5989static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5990 struct ixgbe_ring *tx_ring, int size)
e092be60 5991{
30eba97a 5992 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5993 /* Herbert's original patch had:
5994 * smp_mb__after_netif_stop_queue();
5995 * but since that doesn't exist yet, just open code it. */
5996 smp_mb();
5997
5998 /* We need to check again in a case another CPU has just
5999 * made room available. */
6000 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6001 return -EBUSY;
6002
6003 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 6004 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 6005 ++tx_ring->restart_queue;
e092be60
AV		 6006 return 0;
6007}
6008
6009static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 6010 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6011{
6012 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6013 return 0;
6014 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6015}
6016
09a3b1f8
SH		 6017static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6018{
6019 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6020 int txq = smp_processor_id();
09a3b1f8 6021
fdd3d631
KK		 6022 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6023 while (unlikely(txq >= dev->real_num_tx_queues))
6024 txq -= dev->real_num_tx_queues;
5f715823 6025 return txq;
fdd3d631 6026 }
c4cf55e5 6027
5f715823
YZ		 6028#ifdef IXGBE_FCOE
6029 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
ca77cd59
RL		 6030 ((skb->protocol == htons(ETH_P_FCOE)) ||
6031 (skb->protocol == htons(ETH_P_FIP)))) {
5f715823
YZ		 6032 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6033 txq += adapter->ring_feature[RING_F_FCOE].mask;
6034 return txq;
6035 }
6036#endif
2ea186ae
JF		 6037 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6038 if (skb->priority == TC_PRIO_CONTROL)
6039 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6040 else
6041 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6042 >> 13;
6043 return txq;
6044 }
09a3b1f8
SH		 6045
6046 return skb_tx_hash(dev, skb);
6047}
6048
3b29a56d
SH		 6049static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6050 struct net_device *netdev)
9a799d71
AK		 6051{
6052 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6053 struct ixgbe_ring *tx_ring;
60d51134 6054 struct netdev_queue *txq;
9a799d71
AK		 6055 unsigned int first;
6056 unsigned int tx_flags = 0;
30eba97a 6057 u8 hdr_len = 0;
5f715823 6058 int tso;
9a799d71
AK		 6059 int count = 0;
6060 unsigned int f;
9f8cdf4f 6061
9f8cdf4f
JB		 6062 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6063 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6064 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6065 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 6066 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 6067 }
6068 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6069 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6070 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2ea186ae
JF		 6071 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6072 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6073 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6074 }
eacd73f7 6075
4a0b9ca0 6076 tx_ring = adapter->tx_ring[skb->queue_mapping];
60127865 6077
09ad1cc0 6078#ifdef IXGBE_FCOE
ca77cd59 6079 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
61a0f421 6080#ifdef CONFIG_IXGBE_DCB
ca77cd59
RL		 6081 /* for FCoE with DCB, we force the priority to what
6082 * was specified by the switch */
6083 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6084 (skb->protocol == htons(ETH_P_FIP))) {
6085 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6086 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6087 tx_flags |= ((adapter->fcoe.up << 13)
6088 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6089 }
09ad1cc0 6090#endif
ca77cd59
RL		 6091 /* flag for FCoE offloads */
6092 if (skb->protocol == htons(ETH_P_FCOE))
6093 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 6094 }
ca77cd59
RL		 6095#endif
6096
eacd73f7 6097 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6098 if (skb_is_gso(skb) ||
6099 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6100 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6101 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6102 count++;
6103
9f8cdf4f
JB		 6104 count += TXD_USE_COUNT(skb_headlen(skb));
6105 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6106 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6107
e092be60 6108 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 6109 adapter->tx_busy++;
9a799d71
AK		 6110 return NETDEV_TX_BUSY;
6111 }
9a799d71 6112
9a799d71 6113 first = tx_ring->next_to_use;
eacd73f7
YZ		 6114 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6115#ifdef IXGBE_FCOE
6116 /* setup tx offload for FCoE */
6117 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6118 if (tso < 0) {
6119 dev_kfree_skb_any(skb);
6120 return NETDEV_TX_OK;
6121 }
6122 if (tso)
6123 tx_flags |= IXGBE_TX_FLAGS_FSO;
6124#endif /* IXGBE_FCOE */
6125 } else {
6126 if (skb->protocol == htons(ETH_P_IP))
6127 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6128 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6129 if (tso < 0) {
6130 dev_kfree_skb_any(skb);
6131 return NETDEV_TX_OK;
6132 }
9a799d71 6133
eacd73f7
YZ		 6134 if (tso)
6135 tx_flags |= IXGBE_TX_FLAGS_TSO;
6136 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6137 (skb->ip_summed == CHECKSUM_PARTIAL))
6138 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6139 }
9a799d71 6140
eacd73f7 6141 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 6142 if (count) {
c4cf55e5
PWJ		 6143 /* add the ATR filter if ATR is on */
6144 if (tx_ring->atr_sample_rate) {
6145 ++tx_ring->atr_count;
6146 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6147 test_bit(__IXGBE_FDIR_INIT_DONE,
6148 &tx_ring->reinit_state)) {
6149 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6150 tx_flags);
6151 tx_ring->atr_count = 0;
6152 }
6153 }
60d51134
ED		 6154 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6155 txq->tx_bytes += skb->len;
6156 txq->tx_packets++;
44df32c5
AD		 6157 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6158 hdr_len);
44df32c5 6159 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 6160
44df32c5
AD		 6161 } else {
6162 dev_kfree_skb_any(skb);
6163 tx_ring->tx_buffer_info[first].time_stamp = 0;
6164 tx_ring->next_to_use = first;
6165 }
9a799d71
AK		 6166
6167 return NETDEV_TX_OK;
6168}
6169
9a799d71
AK		 6170/**
6171 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6172 * @netdev: network interface device structure
6173 * @p: pointer to an address structure
6174 *
6175 * Returns 0 on success, negative on failure
6176 **/
6177static int ixgbe_set_mac(struct net_device *netdev, void *p)
6178{
6179 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6180 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6181 struct sockaddr *addr = p;
6182
6183 if (!is_valid_ether_addr(addr->sa_data))
6184 return -EADDRNOTAVAIL;
6185
6186 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6187 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6188
1cdd1ec8
GR		 6189 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6190 IXGBE_RAH_AV);
9a799d71
AK		 6191
6192 return 0;
6193}
6194
6b73e10d
BH		 6195static int
6196ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6197{
6198 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6199 struct ixgbe_hw *hw = &adapter->hw;
6200 u16 value;
6201 int rc;
6202
6203 if (prtad != hw->phy.mdio.prtad)
6204 return -EINVAL;
6205 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6206 if (!rc)
6207 rc = value;
6208 return rc;
6209}
6210
6211static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6212 u16 addr, u16 value)
6213{
6214 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6215 struct ixgbe_hw *hw = &adapter->hw;
6216
6217 if (prtad != hw->phy.mdio.prtad)
6218 return -EINVAL;
6219 return hw->phy.ops.write_reg(hw, addr, devad, value);
6220}
6221
6222static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6223{
6224 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6225
6226 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6227}
6228
0365e6e4
PW		 6229/**
6230 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6231 * netdev->dev_addrs
0365e6e4
PW		 6232 * @netdev: network interface device structure
6233 *
6234 * Returns non-zero on failure
6235 **/
6236static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6237{
6238 int err = 0;
6239 struct ixgbe_adapter *adapter = netdev_priv(dev);
6240 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6241
6242 if (is_valid_ether_addr(mac->san_addr)) {
6243 rtnl_lock();
6244 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6245 rtnl_unlock();
6246 }
6247 return err;
6248}
6249
6250/**
6251 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6252 * netdev->dev_addrs
0365e6e4
PW		 6253 * @netdev: network interface device structure
6254 *
6255 * Returns non-zero on failure
6256 **/
6257static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6258{
6259 int err = 0;
6260 struct ixgbe_adapter *adapter = netdev_priv(dev);
6261 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6262
6263 if (is_valid_ether_addr(mac->san_addr)) {
6264 rtnl_lock();
6265 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6266 rtnl_unlock();
6267 }
6268 return err;
6269}
6270
9a799d71
AK		 6271#ifdef CONFIG_NET_POLL_CONTROLLER
6272/*
6273 * Polling 'interrupt' - used by things like netconsole to send skbs
6274 * without having to re-enable interrupts. It's not called while
6275 * the interrupt routine is executing.
6276 */
6277static void ixgbe_netpoll(struct net_device *netdev)
6278{
6279 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6280 int i;
9a799d71 6281
1a647bd2
AD		 6282 /* if interface is down do nothing */
6283 if (test_bit(__IXGBE_DOWN, &adapter->state))
6284 return;
6285
9a799d71 6286 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6287 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6288 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6289 for (i = 0; i < num_q_vectors; i++) {
6290 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6291 ixgbe_msix_clean_many(0, q_vector);
6292 }
6293 } else {
6294 ixgbe_intr(adapter->pdev->irq, netdev);
6295 }
9a799d71 6296 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6297}
6298#endif
6299
0edc3527
SH		 6300static const struct net_device_ops ixgbe_netdev_ops = {
6301 .ndo_open = ixgbe_open,
6302 .ndo_stop = ixgbe_close,
00829823 6303 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6304 .ndo_select_queue = ixgbe_select_queue,
e90d400c 6305 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6306 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6307 .ndo_validate_addr = eth_validate_addr,
6308 .ndo_set_mac_address = ixgbe_set_mac,
6309 .ndo_change_mtu = ixgbe_change_mtu,
6310 .ndo_tx_timeout = ixgbe_tx_timeout,
6311 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
6312 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6313 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6314 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6315 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6316 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6317 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6318 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
0edc3527
SH		 6319#ifdef CONFIG_NET_POLL_CONTROLLER
6320 .ndo_poll_controller = ixgbe_netpoll,
6321#endif
332d4a7d
YZ		 6322#ifdef IXGBE_FCOE
6323 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6324 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6325 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6326 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6327 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 6328#endif /* IXGBE_FCOE */
0edc3527
SH		 6329};
6330
1cdd1ec8
GR		 6331static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6332 const struct ixgbe_info *ii)
6333{
6334#ifdef CONFIG_PCI_IOV
6335 struct ixgbe_hw *hw = &adapter->hw;
6336 int err;
6337
6338 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6339 return;
6340
6341 /* The 82599 supports up to 64 VFs per physical function
6342 * but this implementation limits allocation to 63 so that
6343 * basic networking resources are still available to the
6344 * physical function
6345 */
6346 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6347 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6348 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6349 if (err) {
6350 DPRINTK(PROBE, ERR,
6351 "Failed to enable PCI sriov: %d\n", err);
6352 goto err_novfs;
6353 }
6354 /* If call to enable VFs succeeded then allocate memory
6355 * for per VF control structures.
6356 */
6357 adapter->vfinfo =
6358 kcalloc(adapter->num_vfs,
6359 sizeof(struct vf_data_storage), GFP_KERNEL);
6360 if (adapter->vfinfo) {
6361 /* Now that we're sure SR-IOV is enabled
6362 * and memory allocated set up the mailbox parameters
6363 */
6364 ixgbe_init_mbx_params_pf(hw);
6365 memcpy(&hw->mbx.ops, ii->mbx_ops,
6366 sizeof(hw->mbx.ops));
6367
6368 /* Disable RSC when in SR-IOV mode */
6369 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6370 IXGBE_FLAG2_RSC_ENABLED);
6371 return;
6372 }
6373
6374 /* Oh oh */
6375 DPRINTK(PROBE, ERR,
6376 "Unable to allocate memory for VF "
6377 "Data Storage - SRIOV disabled\n");
6378 pci_disable_sriov(adapter->pdev);
6379
6380err_novfs:
6381 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6382 adapter->num_vfs = 0;
6383#endif /* CONFIG_PCI_IOV */
6384}
6385
9a799d71
AK		 6386/**
6387 * ixgbe_probe - Device Initialization Routine
6388 * @pdev: PCI device information struct
6389 * @ent: entry in ixgbe_pci_tbl
6390 *
6391 * Returns 0 on success, negative on failure
6392 *
6393 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6394 * The OS initialization, configuring of the adapter private structure,
6395 * and a hardware reset occur.
6396 **/
6397static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 6398 const struct pci_device_id *ent)
9a799d71
AK		 6399{
6400 struct net_device *netdev;
6401 struct ixgbe_adapter *adapter = NULL;
6402 struct ixgbe_hw *hw;
6403 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6404 static int cards_found;
6405 int i, err, pci_using_dac;
c85a2618 6406 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6407#ifdef IXGBE_FCOE
6408 u16 device_caps;
6409#endif
c44ade9e 6410 u32 part_num, eec;
9a799d71 6411
9ce77666 6412 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6413 if (err)
6414 return err;
6415
1b507730
NN		 6416 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6417 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6418 pci_using_dac = 1;
6419 } else {
1b507730 6420 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6421 if (err) {
1b507730
NN		 6422 err = dma_set_coherent_mask(&pdev->dev,
6423 DMA_BIT_MASK(32));
9a799d71 6424 if (err) {
b4617240
PW		 6425 dev_err(&pdev->dev, "No usable DMA "
6426 "configuration, aborting\n");
9a799d71
AK		 6427 goto err_dma;
6428 }
6429 }
6430 pci_using_dac = 0;
6431 }
6432
9ce77666 6433 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6434 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6435 if (err) {
9ce77666 6436 dev_err(&pdev->dev,
6437 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6438 goto err_pci_reg;
6439 }
6440
19d5afd4 6441 pci_enable_pcie_error_reporting(pdev);
6fabd715 6442
9a799d71 6443 pci_set_master(pdev);
fb3b27bc 6444 pci_save_state(pdev);
9a799d71 6445
c85a2618
JF		 6446 if (ii->mac == ixgbe_mac_82598EB)
6447 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6448 else
6449 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6450
6451 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6452#ifdef IXGBE_FCOE
6453 indices += min_t(unsigned int, num_possible_cpus(),
6454 IXGBE_MAX_FCOE_INDICES);
6455#endif
c85a2618 6456 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6457 if (!netdev) {
6458 err = -ENOMEM;
6459 goto err_alloc_etherdev;
6460 }
6461
9a799d71
AK		 6462 SET_NETDEV_DEV(netdev, &pdev->dev);
6463
6464 pci_set_drvdata(pdev, netdev);
6465 adapter = netdev_priv(netdev);
6466
6467 adapter->netdev = netdev;
6468 adapter->pdev = pdev;
6469 hw = &adapter->hw;
6470 hw->back = adapter;
6471 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6472
05857980
JK		 6473 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6474 pci_resource_len(pdev, 0));
9a799d71
AK		 6475 if (!hw->hw_addr) {
6476 err = -EIO;
6477 goto err_ioremap;
6478 }
6479
6480 for (i = 1; i <= 5; i++) {
6481 if (pci_resource_len(pdev, i) == 0)
6482 continue;
6483 }
6484
0edc3527 6485 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6486 ixgbe_set_ethtool_ops(netdev);
9a799d71 6487 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6488 strcpy(netdev->name, pci_name(pdev));
6489
9a799d71
AK		 6490 adapter->bd_number = cards_found;
6491
9a799d71
AK		 6492 /* Setup hw api */
6493 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6494 hw->mac.type = ii->mac;
9a799d71 6495
c44ade9e
JB		 6496 /* EEPROM */
6497 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6498 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6499 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6500 if (!(eec & (1 << 8)))
6501 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6502
6503 /* PHY */
6504 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6505 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6506 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6507 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6508 hw->phy.mdio.mmds = 0;
6509 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6510 hw->phy.mdio.dev = netdev;
6511 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6512 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6513
6514 /* set up this timer and work struct before calling get_invariants
6515 * which might start the timer
6516 */
6517 init_timer(&adapter->sfp_timer);
6518 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6519 adapter->sfp_timer.data = (unsigned long) adapter;
6520
6521 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6522
e8e26350
PW		 6523 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6524 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6525
6526 /* a new SFP+ module arrival, called from GPI SDP2 context */
6527 INIT_WORK(&adapter->sfp_config_module_task,
6528 ixgbe_sfp_config_module_task);
6529
8ca783ab 6530 ii->get_invariants(hw);
9a799d71
AK		 6531
6532 /* setup the private structure */
6533 err = ixgbe_sw_init(adapter);
6534 if (err)
6535 goto err_sw_init;
6536
e86bff0e
DS		 6537 /* Make it possible the adapter to be woken up via WOL */
6538 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6539 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6540
bf069c97
DS		 6541 /*
6542 * If there is a fan on this device and it has failed log the
6543 * failure.
6544 */
6545 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6546 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6547 if (esdp & IXGBE_ESDP_SDP1)
6548 DPRINTK(PROBE, CRIT,
6549 "Fan has stopped, replace the adapter\n");
6550 }
6551
c44ade9e
JB		 6552 /* reset_hw fills in the perm_addr as well */
6553 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 6554 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6555 hw->mac.type == ixgbe_mac_82598EB) {
6556 /*
6557 * Start a kernel thread to watch for a module to arrive.
6558 * Only do this for 82598, since 82599 will generate
6559 * interrupts on module arrival.
6560 */
6561 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6562 mod_timer(&adapter->sfp_timer,
6563 round_jiffies(jiffies + (2 * HZ)));
6564 err = 0;
6565 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 6566 dev_err(&adapter->pdev->dev, "failed to initialize because "
6567 "an unsupported SFP+ module type was detected.\n"
6568 "Reload the driver after installing a supported "
6569 "module.\n");
04f165ef
PW		 6570 goto err_sw_init;
6571 } else if (err) {
c44ade9e
JB		 6572 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6573 goto err_sw_init;
6574 }
6575
1cdd1ec8
GR		 6576 ixgbe_probe_vf(adapter, ii);
6577
9a799d71 6578 netdev->features = NETIF_F_SG |
b4617240
PW		 6579 NETIF_F_IP_CSUM |
6580 NETIF_F_HW_VLAN_TX |
6581 NETIF_F_HW_VLAN_RX |
6582 NETIF_F_HW_VLAN_FILTER;
9a799d71 6583
e9990a9c 6584 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6585 netdev->features |= NETIF_F_TSO;
9a799d71 6586 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6587 netdev->features |= NETIF_F_GRO;
ad31c402 6588
45a5ead0
JB		 6589 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6590 netdev->features |= NETIF_F_SCTP_CSUM;
6591
ad31c402
JK		 6592 netdev->vlan_features |= NETIF_F_TSO;
6593 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6594 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6595 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6596 netdev->vlan_features |= NETIF_F_SG;
6597
1cdd1ec8
GR		 6598 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6599 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6600 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6601 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6602 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6603
7a6b6f51 6604#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6605 netdev->dcbnl_ops = &dcbnl_ops;
6606#endif
6607
eacd73f7 6608#ifdef IXGBE_FCOE
0d551589 6609 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6610 if (hw->mac.ops.get_device_caps) {
6611 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6612 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6613 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6614 }
6615 }
6616#endif /* IXGBE_FCOE */
9a799d71
AK		 6617 if (pci_using_dac)
6618 netdev->features |= NETIF_F_HIGHDMA;
6619
0c19d6af 6620 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6621 netdev->features |= NETIF_F_LRO;
6622
9a799d71 6623 /* make sure the EEPROM is good */
c44ade9e 6624 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 6625 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6626 err = -EIO;
6627 goto err_eeprom;
6628 }
6629
6630 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6631 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6632
c44ade9e
JB		 6633 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6634 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 6635 err = -EIO;
6636 goto err_eeprom;
6637 }
6638
61fac744
PW		 6639 /* power down the optics */
6640 if (hw->phy.multispeed_fiber)
6641 hw->mac.ops.disable_tx_laser(hw);
6642
9a799d71
AK		 6643 init_timer(&adapter->watchdog_timer);
6644 adapter->watchdog_timer.function = &ixgbe_watchdog;
6645 adapter->watchdog_timer.data = (unsigned long)adapter;
6646
6647 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6648 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6649
021230d4
AV		 6650 err = ixgbe_init_interrupt_scheme(adapter);
6651 if (err)
6652 goto err_sw_init;
9a799d71 6653
e8e26350
PW		 6654 switch (pdev->device) {
6655 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 6656 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6657 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6658 break;
6659 default:
6660 adapter->wol = 0;
6661 break;
6662 }
e8e26350
PW		 6663 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6664
04f165ef
PW		 6665 /* pick up the PCI bus settings for reporting later */
6666 hw->mac.ops.get_bus_info(hw);
6667
9a799d71 6668 /* print bus type/speed/width info */
7c510e4b 6669 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 6670 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6671 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6672 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6673 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6674 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 6675 "Unknown"),
7c510e4b 6676 netdev->dev_addr);
c44ade9e 6677 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 6678 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6679 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6680 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6681 (part_num >> 8), (part_num & 0xff));
6682 else
6683 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6684 hw->mac.type, hw->phy.type,
6685 (part_num >> 8), (part_num & 0xff));
9a799d71 6686
e8e26350 6687 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 6688 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 6689 "this card is not sufficient for optimal "
6690 "performance.\n");
0c254d86 6691 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 6692 "PCI-Express slot is required.\n");
0c254d86
AK		 6693 }
6694
34b0368c
PWJ		 6695 /* save off EEPROM version number */
6696 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6697
9a799d71 6698 /* reset the hardware with the new settings */
794caeb2 6699 err = hw->mac.ops.start_hw(hw);
c44ade9e 6700
794caeb2
PWJ		 6701 if (err == IXGBE_ERR_EEPROM_VERSION) {
6702 /* We are running on a pre-production device, log a warning */
6703 dev_warn(&pdev->dev, "This device is a pre-production "
6704 "adapter/LOM. Please be aware there may be issues "
6705 "associated with your hardware. If you are "
6706 "experiencing problems please contact your Intel or "
6707 "hardware representative who provided you with this "
6708 "hardware.\n");
6709 }
9a799d71
AK		 6710 strcpy(netdev->name, "eth%d");
6711 err = register_netdev(netdev);
6712 if (err)
6713 goto err_register;
6714
54386467
JB		 6715 /* carrier off reporting is important to ethtool even BEFORE open */
6716 netif_carrier_off(netdev);
6717
c4cf55e5
PWJ		 6718 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6719 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6720 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6721
5dd2d332 6722#ifdef CONFIG_IXGBE_DCA
652f093f 6723 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 6724 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 6725 ixgbe_setup_dca(adapter);
6726 }
6727#endif
1cdd1ec8
GR		 6728 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6729 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6730 adapter->num_vfs);
6731 for (i = 0; i < adapter->num_vfs; i++)
6732 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6733 }
6734
0365e6e4
PW		 6735 /* add san mac addr to netdev */
6736 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 6737
6738 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6739 cards_found++;
6740 return 0;
6741
6742err_register:
5eba3699 6743 ixgbe_release_hw_control(adapter);
7a921c93 6744 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 6745err_sw_init:
6746err_eeprom:
1cdd1ec8
GR		 6747 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6748 ixgbe_disable_sriov(adapter);
c4900be0
DS		 6749 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6750 del_timer_sync(&adapter->sfp_timer);
6751 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6752 cancel_work_sync(&adapter->multispeed_fiber_task);
6753 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 6754 iounmap(hw->hw_addr);
6755err_ioremap:
6756 free_netdev(netdev);
6757err_alloc_etherdev:
9ce77666 6758 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6759 IORESOURCE_MEM));
9a799d71
AK		 6760err_pci_reg:
6761err_dma:
6762 pci_disable_device(pdev);
6763 return err;
6764}
6765
6766/**
6767 * ixgbe_remove - Device Removal Routine
6768 * @pdev: PCI device information struct
6769 *
6770 * ixgbe_remove is called by the PCI subsystem to alert the driver
6771 * that it should release a PCI device. The could be caused by a
6772 * Hot-Plug event, or because the driver is going to be removed from
6773 * memory.
6774 **/
6775static void __devexit ixgbe_remove(struct pci_dev *pdev)
6776{
6777 struct net_device *netdev = pci_get_drvdata(pdev);
6778 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6779
6780 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 6781 /* clear the module not found bit to make sure the worker won't
6782 * reschedule
6783 */
6784 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 6785 del_timer_sync(&adapter->watchdog_timer);
6786
c4900be0
DS		 6787 del_timer_sync(&adapter->sfp_timer);
6788 cancel_work_sync(&adapter->watchdog_task);
6789 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6790 cancel_work_sync(&adapter->multispeed_fiber_task);
6791 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 6792 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6793 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6794 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 6795 flush_scheduled_work();
6796
5dd2d332 6797#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6798 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6799 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6800 dca_remove_requester(&pdev->dev);
6801 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6802 }
6803
6804#endif
332d4a7d
YZ		 6805#ifdef IXGBE_FCOE
6806 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6807 ixgbe_cleanup_fcoe(adapter);
6808
6809#endif /* IXGBE_FCOE */
0365e6e4
PW		 6810
6811 /* remove the added san mac */
6812 ixgbe_del_sanmac_netdev(netdev);
6813
c4900be0
DS		 6814 if (netdev->reg_state == NETREG_REGISTERED)
6815 unregister_netdev(netdev);
9a799d71 6816
1cdd1ec8
GR		 6817 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6818 ixgbe_disable_sriov(adapter);
6819
7a921c93 6820 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 6821
021230d4 6822 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6823
6824 iounmap(adapter->hw.hw_addr);
9ce77666 6825 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6826 IORESOURCE_MEM));
9a799d71 6827
021230d4 6828 DPRINTK(PROBE, INFO, "complete\n");
021230d4 6829
9a799d71
AK		 6830 free_netdev(netdev);
6831
19d5afd4 6832 pci_disable_pcie_error_reporting(pdev);
6fabd715 6833
9a799d71
AK		 6834 pci_disable_device(pdev);
6835}
6836
6837/**
6838 * ixgbe_io_error_detected - called when PCI error is detected
6839 * @pdev: Pointer to PCI device
6840 * @state: The current pci connection state
6841 *
6842 * This function is called after a PCI bus error affecting
6843 * this device has been detected.
6844 */
6845static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 6846 pci_channel_state_t state)
9a799d71
AK		 6847{
6848 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6849 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6850
6851 netif_device_detach(netdev);
6852
3044b8d1
BL		 6853 if (state == pci_channel_io_perm_failure)
6854 return PCI_ERS_RESULT_DISCONNECT;
6855
9a799d71
AK		 6856 if (netif_running(netdev))
6857 ixgbe_down(adapter);
6858 pci_disable_device(pdev);
6859
b4617240 6860 /* Request a slot reset. */
9a799d71
AK		 6861 return PCI_ERS_RESULT_NEED_RESET;
6862}
6863
6864/**
6865 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6866 * @pdev: Pointer to PCI device
6867 *
6868 * Restart the card from scratch, as if from a cold-boot.
6869 */
6870static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6871{
6872 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6873 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 6874 pci_ers_result_t result;
6875 int err;
9a799d71 6876
9ce77666 6877 if (pci_enable_device_mem(pdev)) {
9a799d71 6878 DPRINTK(PROBE, ERR,
b4617240 6879 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 6880 result = PCI_ERS_RESULT_DISCONNECT;
6881 } else {
6882 pci_set_master(pdev);
6883 pci_restore_state(pdev);
c0e1f68b 6884 pci_save_state(pdev);
9a799d71 6885
dd4d8ca6 6886 pci_wake_from_d3(pdev, false);
9a799d71 6887
6fabd715 6888 ixgbe_reset(adapter);
88512539 6889 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 6890 result = PCI_ERS_RESULT_RECOVERED;
6891 }
6892
6893 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6894 if (err) {
6895 dev_err(&pdev->dev,
6896 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6897 /* non-fatal, continue */
6898 }
9a799d71 6899
6fabd715 6900 return result;
9a799d71
AK		 6901}
6902
6903/**
6904 * ixgbe_io_resume - called when traffic can start flowing again.
6905 * @pdev: Pointer to PCI device
6906 *
6907 * This callback is called when the error recovery driver tells us that
6908 * its OK to resume normal operation.
6909 */
6910static void ixgbe_io_resume(struct pci_dev *pdev)
6911{
6912 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6913 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6914
6915 if (netif_running(netdev)) {
6916 if (ixgbe_up(adapter)) {
6917 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6918 return;
6919 }
6920 }
6921
6922 netif_device_attach(netdev);
9a799d71
AK		 6923}
6924
6925static struct pci_error_handlers ixgbe_err_handler = {
6926 .error_detected = ixgbe_io_error_detected,
6927 .slot_reset = ixgbe_io_slot_reset,
6928 .resume = ixgbe_io_resume,
6929};
6930
6931static struct pci_driver ixgbe_driver = {
6932 .name = ixgbe_driver_name,
6933 .id_table = ixgbe_pci_tbl,
6934 .probe = ixgbe_probe,
6935 .remove = __devexit_p(ixgbe_remove),
6936#ifdef CONFIG_PM
6937 .suspend = ixgbe_suspend,
6938 .resume = ixgbe_resume,
6939#endif
6940 .shutdown = ixgbe_shutdown,
6941 .err_handler = &ixgbe_err_handler
6942};
6943
6944/**
6945 * ixgbe_init_module - Driver Registration Routine
6946 *
6947 * ixgbe_init_module is the first routine called when the driver is
6948 * loaded. All it does is register with the PCI subsystem.
6949 **/
6950static int __init ixgbe_init_module(void)
6951{
6952 int ret;
6953 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6954 ixgbe_driver_string, ixgbe_driver_version);
6955
6956 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6957
5dd2d332 6958#ifdef CONFIG_IXGBE_DCA
bd0362dd 6959 dca_register_notify(&dca_notifier);
bd0362dd 6960#endif
5dd2d332 6961
9a799d71
AK		 6962 ret = pci_register_driver(&ixgbe_driver);
6963 return ret;
6964}
b4617240 6965
9a799d71
AK		 6966module_init(ixgbe_init_module);
6967
6968/**
6969 * ixgbe_exit_module - Driver Exit Cleanup Routine
6970 *
6971 * ixgbe_exit_module is called just before the driver is removed
6972 * from memory.
6973 **/
6974static void __exit ixgbe_exit_module(void)
6975{
5dd2d332 6976#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6977 dca_unregister_notify(&dca_notifier);
6978#endif
9a799d71
AK		 6979 pci_unregister_driver(&ixgbe_driver);
6980}
bd0362dd 6981
5dd2d332 6982#ifdef CONFIG_IXGBE_DCA
bd0362dd 6983static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 6984 void *p)
bd0362dd
JC		 6985{
6986 int ret_val;
6987
6988 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 6989 __ixgbe_notify_dca);
bd0362dd
JC		 6990
6991 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6992}
b453368d 6993
5dd2d332 6994#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 6995#ifdef DEBUG
6996/**
6997 * ixgbe_get_hw_dev_name - return device name string
6998 * used by hardware layer to print debugging information
6999 **/
7000char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
7001{
7002 struct ixgbe_adapter *adapter = hw->back;
7003 return adapter->netdev->name;
7004}
bd0362dd 7005
b453368d 7006#endif
9a799d71
AK		 7007module_exit(ixgbe_exit_module);
7008
7009/* ixgbe_main.c */
Linux kernel - Deliverables
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