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ixgbe: Move all values that deal with count, next_to_use, next_to_clean to u16
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
60127865 38#include <linux/pkt_sched.h>
9a799d71 39#include <linux/ipv6.h>
5a0e3ad6 40#include <linux/slab.h>
9a799d71
AK		 41#include <net/checksum.h>
42#include <net/ip6_checksum.h>
43#include <linux/ethtool.h>
44#include <linux/if_vlan.h>
70c71606 45#include <linux/prefetch.h>
eacd73f7 46#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 47
48#include "ixgbe.h"
49#include "ixgbe_common.h"
ee5f784a 50#include "ixgbe_dcb_82599.h"
1cdd1ec8 51#include "ixgbe_sriov.h"
9a799d71
AK		 52
53char ixgbe_driver_name[] = "ixgbe";
9c8eb720 54static const char ixgbe_driver_string[] =
e8e9f696 55 "Intel(R) 10 Gigabit PCI Express Network Driver";
75e3d3c6 56#define MAJ 3
a38a104d 57#define MIN 4
c89c7112 58#define BUILD 8
75e3d3c6 59#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 60 __stringify(BUILD) "-k"
9c8eb720 61const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 62static const char ixgbe_copyright[] =
63 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 64
65static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 66 [board_82598] = &ixgbe_82598_info,
e8e26350 67 [board_82599] = &ixgbe_82599_info,
fe15e8e1 68 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 69};
70
71/* ixgbe_pci_tbl - PCI Device ID Table
72 *
73 * Wildcard entries (PCI_ANY_ID) should come last
74 * Last entry must be all 0s
75 *
76 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
77 * Class, Class Mask, private data (not used) }
78 */
a3aa1884 79static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
81 board_82598 },
9a799d71 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 83 board_82598 },
9a799d71 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 85 board_82598 },
0befdb3e
JB		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
87 board_82598 },
3845bec0
PWJ		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
89 board_82598 },
9a799d71 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 91 board_82598 },
8d792cd9
JB		 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
93 board_82598 },
c4900be0
DS		 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
95 board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
97 board_82598 },
b95f5fcb
JB		 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
99 board_82598 },
c4900be0
DS		 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
101 board_82598 },
2f21bdd3
DS		 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
103 board_82598 },
e8e26350
PW		 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
105 board_82599 },
1fcf03e6
PWJ		 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
107 board_82599 },
74757d49
DS		 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
109 board_82599 },
e8e26350
PW		 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
111 board_82599 },
38ad1c8e
DS		 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
113 board_82599 },
dbfec662
DS		 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
115 board_82599 },
8911184f
PWJ		 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
117 board_82599 },
dbffcb21
DS		 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
119 board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
121 board_82599 },
119fc60a
MC		 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
123 board_82599 },
312eb931
DS		 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
125 board_82599 },
b93a2226 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
d994653d 127 board_X540 },
4c40ef02
ET		 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
129 board_82599 },
4f6290cf
DS		 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
131 board_82599 },
9a799d71
AK		 132
133 /* required last entry */
134 {0, }
135};
136MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
137
5dd2d332 138#ifdef CONFIG_IXGBE_DCA
bd0362dd 139static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 140 void *p);
bd0362dd
JC		 141static struct notifier_block dca_notifier = {
142 .notifier_call = ixgbe_notify_dca,
143 .next = NULL,
144 .priority = 0
145};
146#endif
147
1cdd1ec8
GR		 148#ifdef CONFIG_PCI_IOV
149static unsigned int max_vfs;
150module_param(max_vfs, uint, 0);
e8e9f696
JP		 151MODULE_PARM_DESC(max_vfs,
152 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 153#endif /* CONFIG_PCI_IOV */
154
9a799d71
AK		 155MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
156MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
157MODULE_LICENSE("GPL");
158MODULE_VERSION(DRV_VERSION);
159
160#define DEFAULT_DEBUG_LEVEL_SHIFT 3
161
1cdd1ec8
GR		 162static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
163{
164 struct ixgbe_hw *hw = &adapter->hw;
165 u32 gcr;
166 u32 gpie;
167 u32 vmdctl;
168
169#ifdef CONFIG_PCI_IOV
170 /* disable iov and allow time for transactions to clear */
171 pci_disable_sriov(adapter->pdev);
172#endif
173
174 /* turn off device IOV mode */
175 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
176 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
177 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
178 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
179 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
180 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
181
182 /* set default pool back to 0 */
183 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
184 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
185 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
186
187 /* take a breather then clean up driver data */
188 msleep(100);
e8e9f696
JP		 189
190 kfree(adapter->vfinfo);
1cdd1ec8
GR		 191 adapter->vfinfo = NULL;
192
193 adapter->num_vfs = 0;
194 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
195}
196
7086400d
AD		 197static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
198{
199 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
200 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
201 schedule_work(&adapter->service_task);
202}
203
204static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
205{
206 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
207
208 /* flush memory to make sure state is correct before next watchog */
209 smp_mb__before_clear_bit();
210 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
211}
212
dcd79aeb
TI		 213struct ixgbe_reg_info {
214 u32 ofs;
215 char *name;
216};
217
218static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
219
220 /* General Registers */
221 {IXGBE_CTRL, "CTRL"},
222 {IXGBE_STATUS, "STATUS"},
223 {IXGBE_CTRL_EXT, "CTRL_EXT"},
224
225 /* Interrupt Registers */
226 {IXGBE_EICR, "EICR"},
227
228 /* RX Registers */
229 {IXGBE_SRRCTL(0), "SRRCTL"},
230 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
231 {IXGBE_RDLEN(0), "RDLEN"},
232 {IXGBE_RDH(0), "RDH"},
233 {IXGBE_RDT(0), "RDT"},
234 {IXGBE_RXDCTL(0), "RXDCTL"},
235 {IXGBE_RDBAL(0), "RDBAL"},
236 {IXGBE_RDBAH(0), "RDBAH"},
237
238 /* TX Registers */
239 {IXGBE_TDBAL(0), "TDBAL"},
240 {IXGBE_TDBAH(0), "TDBAH"},
241 {IXGBE_TDLEN(0), "TDLEN"},
242 {IXGBE_TDH(0), "TDH"},
243 {IXGBE_TDT(0), "TDT"},
244 {IXGBE_TXDCTL(0), "TXDCTL"},
245
246 /* List Terminator */
247 {}
248};
249
250
251/*
252 * ixgbe_regdump - register printout routine
253 */
254static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
255{
256 int i = 0, j = 0;
257 char rname[16];
258 u32 regs[64];
259
260 switch (reginfo->ofs) {
261 case IXGBE_SRRCTL(0):
262 for (i = 0; i < 64; i++)
263 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
264 break;
265 case IXGBE_DCA_RXCTRL(0):
266 for (i = 0; i < 64; i++)
267 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
268 break;
269 case IXGBE_RDLEN(0):
270 for (i = 0; i < 64; i++)
271 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
272 break;
273 case IXGBE_RDH(0):
274 for (i = 0; i < 64; i++)
275 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
276 break;
277 case IXGBE_RDT(0):
278 for (i = 0; i < 64; i++)
279 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
280 break;
281 case IXGBE_RXDCTL(0):
282 for (i = 0; i < 64; i++)
283 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
284 break;
285 case IXGBE_RDBAL(0):
286 for (i = 0; i < 64; i++)
287 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
288 break;
289 case IXGBE_RDBAH(0):
290 for (i = 0; i < 64; i++)
291 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
292 break;
293 case IXGBE_TDBAL(0):
294 for (i = 0; i < 64; i++)
295 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
296 break;
297 case IXGBE_TDBAH(0):
298 for (i = 0; i < 64; i++)
299 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
300 break;
301 case IXGBE_TDLEN(0):
302 for (i = 0; i < 64; i++)
303 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
304 break;
305 case IXGBE_TDH(0):
306 for (i = 0; i < 64; i++)
307 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
308 break;
309 case IXGBE_TDT(0):
310 for (i = 0; i < 64; i++)
311 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
312 break;
313 case IXGBE_TXDCTL(0):
314 for (i = 0; i < 64; i++)
315 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
316 break;
317 default:
c7689578 318 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 319 IXGBE_READ_REG(hw, reginfo->ofs));
320 return;
321 }
322
323 for (i = 0; i < 8; i++) {
324 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 325 pr_err("%-15s", rname);
dcd79aeb 326 for (j = 0; j < 8; j++)
c7689578
JP		 327 pr_cont(" %08x", regs[i*8+j]);
328 pr_cont("\n");
dcd79aeb
TI		 329 }
330
331}
332
333/*
334 * ixgbe_dump - Print registers, tx-rings and rx-rings
335 */
336static void ixgbe_dump(struct ixgbe_adapter *adapter)
337{
338 struct net_device *netdev = adapter->netdev;
339 struct ixgbe_hw *hw = &adapter->hw;
340 struct ixgbe_reg_info *reginfo;
341 int n = 0;
342 struct ixgbe_ring *tx_ring;
343 struct ixgbe_tx_buffer *tx_buffer_info;
344 union ixgbe_adv_tx_desc *tx_desc;
345 struct my_u0 { u64 a; u64 b; } *u0;
346 struct ixgbe_ring *rx_ring;
347 union ixgbe_adv_rx_desc *rx_desc;
348 struct ixgbe_rx_buffer *rx_buffer_info;
349 u32 staterr;
350 int i = 0;
351
352 if (!netif_msg_hw(adapter))
353 return;
354
355 /* Print netdevice Info */
356 if (netdev) {
357 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 358 pr_info("Device Name state "
dcd79aeb 359 "trans_start last_rx\n");
c7689578
JP		 360 pr_info("%-15s %016lX %016lX %016lX\n",
361 netdev->name,
362 netdev->state,
363 netdev->trans_start,
364 netdev->last_rx);
dcd79aeb
TI		 365 }
366
367 /* Print Registers */
368 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 369 pr_info(" Register Name Value\n");
dcd79aeb
TI		 370 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
371 reginfo->name; reginfo++) {
372 ixgbe_regdump(hw, reginfo);
373 }
374
375 /* Print TX Ring Summary */
376 if (!netdev || !netif_running(netdev))
377 goto exit;
378
379 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 380 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 381 for (n = 0; n < adapter->num_tx_queues; n++) {
382 tx_ring = adapter->tx_ring[n];
383 tx_buffer_info =
384 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 385 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 386 n, tx_ring->next_to_use, tx_ring->next_to_clean,
387 (u64)tx_buffer_info->dma,
388 tx_buffer_info->length,
389 tx_buffer_info->next_to_watch,
390 (u64)tx_buffer_info->time_stamp);
391 }
392
393 /* Print TX Rings */
394 if (!netif_msg_tx_done(adapter))
395 goto rx_ring_summary;
396
397 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
398
399 /* Transmit Descriptor Formats
400 *
401 * Advanced Transmit Descriptor
402 * +--------------------------------------------------------------+
403 * 0 | Buffer Address [63:0] |
404 * +--------------------------------------------------------------+
405 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
406 * +--------------------------------------------------------------+
407 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
408 */
409
410 for (n = 0; n < adapter->num_tx_queues; n++) {
411 tx_ring = adapter->tx_ring[n];
c7689578
JP		 412 pr_info("------------------------------------\n");
413 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
414 pr_info("------------------------------------\n");
415 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 416 "[PlPOIdStDDt Ln] [bi->dma ] "
417 "leng ntw timestamp bi->skb\n");
418
419 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 420 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 421 tx_buffer_info = &tx_ring->tx_buffer_info[i];
422 u0 = (struct my_u0 *)tx_desc;
c7689578 423 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 424 " %04X %3X %016llX %p", i,
425 le64_to_cpu(u0->a),
426 le64_to_cpu(u0->b),
427 (u64)tx_buffer_info->dma,
428 tx_buffer_info->length,
429 tx_buffer_info->next_to_watch,
430 (u64)tx_buffer_info->time_stamp,
431 tx_buffer_info->skb);
432 if (i == tx_ring->next_to_use &&
433 i == tx_ring->next_to_clean)
c7689578 434 pr_cont(" NTC/U\n");
dcd79aeb 435 else if (i == tx_ring->next_to_use)
c7689578 436 pr_cont(" NTU\n");
dcd79aeb 437 else if (i == tx_ring->next_to_clean)
c7689578 438 pr_cont(" NTC\n");
dcd79aeb 439 else
c7689578 440 pr_cont("\n");
dcd79aeb
TI		 441
442 if (netif_msg_pktdata(adapter) &&
443 tx_buffer_info->dma != 0)
444 print_hex_dump(KERN_INFO, "",
445 DUMP_PREFIX_ADDRESS, 16, 1,
446 phys_to_virt(tx_buffer_info->dma),
447 tx_buffer_info->length, true);
448 }
449 }
450
451 /* Print RX Rings Summary */
452rx_ring_summary:
453 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 454 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 455 for (n = 0; n < adapter->num_rx_queues; n++) {
456 rx_ring = adapter->rx_ring[n];
c7689578
JP		 457 pr_info("%5d %5X %5X\n",
458 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 459 }
460
461 /* Print RX Rings */
462 if (!netif_msg_rx_status(adapter))
463 goto exit;
464
465 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
466
467 /* Advanced Receive Descriptor (Read) Format
468 * 63 1 0
469 * +-----------------------------------------------------+
470 * 0 | Packet Buffer Address [63:1] |A0/NSE|
471 * +----------------------------------------------+------+
472 * 8 | Header Buffer Address [63:1] | DD |
473 * +-----------------------------------------------------+
474 *
475 *
476 * Advanced Receive Descriptor (Write-Back) Format
477 *
478 * 63 48 47 32 31 30 21 20 16 15 4 3 0
479 * +------------------------------------------------------+
480 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
481 * | Checksum Ident | | | | Type | Type |
482 * +------------------------------------------------------+
483 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
484 * +------------------------------------------------------+
485 * 63 48 47 32 31 20 19 0
486 */
487 for (n = 0; n < adapter->num_rx_queues; n++) {
488 rx_ring = adapter->rx_ring[n];
c7689578
JP		 489 pr_info("------------------------------------\n");
490 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
491 pr_info("------------------------------------\n");
492 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 493 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
494 "<-- Adv Rx Read format\n");
c7689578 495 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 496 "[vl er S cks ln] ---------------- [bi->skb] "
497 "<-- Adv Rx Write-Back format\n");
498
499 for (i = 0; i < rx_ring->count; i++) {
500 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 501 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 502 u0 = (struct my_u0 *)rx_desc;
503 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
504 if (staterr & IXGBE_RXD_STAT_DD) {
505 /* Descriptor Done */
c7689578 506 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 507 "%016llX ---------------- %p", i,
508 le64_to_cpu(u0->a),
509 le64_to_cpu(u0->b),
510 rx_buffer_info->skb);
511 } else {
c7689578 512 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 513 "%016llX %016llX %p", i,
514 le64_to_cpu(u0->a),
515 le64_to_cpu(u0->b),
516 (u64)rx_buffer_info->dma,
517 rx_buffer_info->skb);
518
519 if (netif_msg_pktdata(adapter)) {
520 print_hex_dump(KERN_INFO, "",
521 DUMP_PREFIX_ADDRESS, 16, 1,
522 phys_to_virt(rx_buffer_info->dma),
523 rx_ring->rx_buf_len, true);
524
525 if (rx_ring->rx_buf_len
526 < IXGBE_RXBUFFER_2048)
527 print_hex_dump(KERN_INFO, "",
528 DUMP_PREFIX_ADDRESS, 16, 1,
529 phys_to_virt(
530 rx_buffer_info->page_dma +
531 rx_buffer_info->page_offset
532 ),
533 PAGE_SIZE/2, true);
534 }
535 }
536
537 if (i == rx_ring->next_to_use)
c7689578 538 pr_cont(" NTU\n");
dcd79aeb 539 else if (i == rx_ring->next_to_clean)
c7689578 540 pr_cont(" NTC\n");
dcd79aeb 541 else
c7689578 542 pr_cont("\n");
dcd79aeb
TI		 543
544 }
545 }
546
547exit:
548 return;
549}
550
5eba3699
AV		 551static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
552{
553 u32 ctrl_ext;
554
555 /* Let firmware take over control of h/w */
556 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
557 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 558 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 559}
560
561static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
562{
563 u32 ctrl_ext;
564
565 /* Let firmware know the driver has taken over */
566 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
567 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 568 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 569}
9a799d71 570
e8e26350
PW		 571/*
572 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
573 * @adapter: pointer to adapter struct
574 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
575 * @queue: queue to map the corresponding interrupt to
576 * @msix_vector: the vector to map to the corresponding queue
577 *
578 */
579static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 580 u8 queue, u8 msix_vector)
9a799d71
AK		 581{
582 u32 ivar, index;
e8e26350
PW		 583 struct ixgbe_hw *hw = &adapter->hw;
584 switch (hw->mac.type) {
585 case ixgbe_mac_82598EB:
586 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
587 if (direction == -1)
588 direction = 0;
589 index = (((direction * 64) + queue) >> 2) & 0x1F;
590 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
591 ivar &= ~(0xFF << (8 * (queue & 0x3)));
592 ivar |= (msix_vector << (8 * (queue & 0x3)));
593 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
594 break;
595 case ixgbe_mac_82599EB:
b93a2226 596 case ixgbe_mac_X540:
e8e26350
PW		 597 if (direction == -1) {
598 /* other causes */
599 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
600 index = ((queue & 1) * 8);
601 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
602 ivar &= ~(0xFF << index);
603 ivar |= (msix_vector << index);
604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
605 break;
606 } else {
607 /* tx or rx causes */
608 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
609 index = ((16 * (queue & 1)) + (8 * direction));
610 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
611 ivar &= ~(0xFF << index);
612 ivar |= (msix_vector << index);
613 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
614 break;
615 }
616 default:
617 break;
618 }
9a799d71
AK		 619}
620
fe49f04a 621static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 622 u64 qmask)
fe49f04a
AD		 623{
624 u32 mask;
625
bd508178
AD		 626 switch (adapter->hw.mac.type) {
627 case ixgbe_mac_82598EB:
fe49f04a
AD		 628 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
629 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 630 break;
631 case ixgbe_mac_82599EB:
b93a2226 632 case ixgbe_mac_X540:
fe49f04a
AD		 633 mask = (qmask & 0xFFFFFFFF);
634 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
635 mask = (qmask >> 32);
636 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 637 break;
638 default:
639 break;
fe49f04a
AD		 640 }
641}
642
b6ec895e
AD		 643void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
644 struct ixgbe_tx_buffer *tx_buffer_info)
9a799d71 645{
e5a43549
AD		 646 if (tx_buffer_info->dma) {
647 if (tx_buffer_info->mapped_as_page)
b6ec895e 648 dma_unmap_page(tx_ring->dev,
e5a43549
AD		 649 tx_buffer_info->dma,
650 tx_buffer_info->length,
1b507730 651 DMA_TO_DEVICE);
e5a43549 652 else
b6ec895e 653 dma_unmap_single(tx_ring->dev,
e5a43549
AD		 654 tx_buffer_info->dma,
655 tx_buffer_info->length,
1b507730 656 DMA_TO_DEVICE);
e5a43549
AD		 657 tx_buffer_info->dma = 0;
658 }
9a799d71
AK		 659 if (tx_buffer_info->skb) {
660 dev_kfree_skb_any(tx_buffer_info->skb);
661 tx_buffer_info->skb = NULL;
662 }
44df32c5 663 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 664 /* tx_buffer_info must be completely set up in the transmit path */
665}
666
c84d324c
JF		 667static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
668{
669 struct ixgbe_hw *hw = &adapter->hw;
670 struct ixgbe_hw_stats *hwstats = &adapter->stats;
671 u32 data = 0;
672 u32 xoff[8] = {0};
673 int i;
674
675 if ((hw->fc.current_mode == ixgbe_fc_full) ||
676 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
677 switch (hw->mac.type) {
678 case ixgbe_mac_82598EB:
679 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 680 break;
681 default:
c84d324c
JF		 682 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
683 }
684 hwstats->lxoffrxc += data;
685
686 /* refill credits (no tx hang) if we received xoff */
687 if (!data)
688 return;
689
690 for (i = 0; i < adapter->num_tx_queues; i++)
691 clear_bit(__IXGBE_HANG_CHECK_ARMED,
692 &adapter->tx_ring[i]->state);
693 return;
694 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
695 return;
696
697 /* update stats for each tc, only valid with PFC enabled */
698 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
699 switch (hw->mac.type) {
700 case ixgbe_mac_82598EB:
701 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 702 break;
c84d324c
JF		 703 default:
704 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 705 }
c84d324c
JF		 706 hwstats->pxoffrxc[i] += xoff[i];
707 }
708
709 /* disarm tx queues that have received xoff frames */
710 for (i = 0; i < adapter->num_tx_queues; i++) {
711 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 712 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 713
714 if (xoff[tc])
715 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 716 }
26f23d82
YZ		 717}
718
c84d324c 719static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 720{
c84d324c
JF		 721 return ring->tx_stats.completed;
722}
723
724static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
725{
726 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 727 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 728
c84d324c
JF		 729 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
730 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
731
732 if (head != tail)
733 return (head < tail) ?
734 tail - head : (tail + ring->count - head);
735
736 return 0;
737}
738
739static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
740{
741 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
742 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
743 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
744 bool ret = false;
745
7d637bcc 746 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 747
748 /*
749 * Check for a hung queue, but be thorough. This verifies
750 * that a transmit has been completed since the previous
751 * check AND there is at least one packet pending. The
752 * ARMED bit is set to indicate a potential hang. The
753 * bit is cleared if a pause frame is received to remove
754 * false hang detection due to PFC or 802.3x frames. By
755 * requiring this to fail twice we avoid races with
756 * pfc clearing the ARMED bit and conditions where we
757 * run the check_tx_hang logic with a transmit completion
758 * pending but without time to complete it yet.
759 */
760 if ((tx_done_old == tx_done) && tx_pending) {
761 /* make sure it is true for two checks in a row */
762 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
763 &tx_ring->state);
764 } else {
765 /* update completed stats and continue */
766 tx_ring->tx_stats.tx_done_old = tx_done;
767 /* reset the countdown */
768 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 769 }
770
c84d324c 771 return ret;
9a799d71
AK		 772}
773
b4617240
PW		 774#define IXGBE_MAX_TXD_PWR 14
775#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 776
777/* Tx Descriptors needed, worst case */
778#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
779 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
780#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 781 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 782
c83c6cbd
AD		 783/**
784 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
785 * @adapter: driver private struct
786 **/
787static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
788{
789
790 /* Do the reset outside of interrupt context */
791 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
792 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
793 ixgbe_service_event_schedule(adapter);
794 }
795}
e01c31a5 796
9a799d71
AK		 797/**
798 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 799 * @q_vector: structure containing interrupt and ring information
e01c31a5 800 * @tx_ring: tx ring to clean
9a799d71 801 **/
fe49f04a 802static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 803 struct ixgbe_ring *tx_ring)
9a799d71 804{
fe49f04a 805 struct ixgbe_adapter *adapter = q_vector->adapter;
12207e49
PWJ		 806 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
807 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5 808 unsigned int total_bytes = 0, total_packets = 0;
b953799e 809 u16 i, eop, count = 0;
9a799d71
AK		 810
811 i = tx_ring->next_to_clean;
12207e49 812 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 813 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 814
815 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 816 (count < tx_ring->work_limit)) {
12207e49 817 bool cleaned = false;
2d0bb1c1 818 rmb(); /* read buffer_info after eop_desc */
12207e49 819 for ( ; !cleaned; count++) {
31f05a2d 820 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 821 tx_buffer_info = &tx_ring->tx_buffer_info[i];
8ad494b0
AD		 822
823 tx_desc->wb.status = 0;
12207e49 824 cleaned = (i == eop);
9a799d71 825
8ad494b0
AD		 826 i++;
827 if (i == tx_ring->count)
828 i = 0;
e01c31a5 829
8ad494b0
AD		 830 if (cleaned && tx_buffer_info->skb) {
831 total_bytes += tx_buffer_info->bytecount;
832 total_packets += tx_buffer_info->gso_segs;
e092be60 833 }
e01c31a5 834
b6ec895e 835 ixgbe_unmap_and_free_tx_resource(tx_ring,
e8e9f696 836 tx_buffer_info);
e01c31a5 837 }
12207e49 838
c84d324c 839 tx_ring->tx_stats.completed++;
12207e49 840 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 841 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 842 }
843
9a799d71 844 tx_ring->next_to_clean = i;
b953799e
AD		 845 tx_ring->total_bytes += total_bytes;
846 tx_ring->total_packets += total_packets;
847 u64_stats_update_begin(&tx_ring->syncp);
848 tx_ring->stats.packets += total_packets;
849 tx_ring->stats.bytes += total_bytes;
850 u64_stats_update_end(&tx_ring->syncp);
851
c84d324c
JF		 852 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
853 /* schedule immediate reset if we believe we hung */
854 struct ixgbe_hw *hw = &adapter->hw;
855 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
856 e_err(drv, "Detected Tx Unit Hang\n"
857 " Tx Queue <%d>\n"
858 " TDH, TDT <%x>, <%x>\n"
859 " next_to_use <%x>\n"
860 " next_to_clean <%x>\n"
861 "tx_buffer_info[next_to_clean]\n"
862 " time_stamp <%lx>\n"
863 " jiffies <%lx>\n",
864 tx_ring->queue_index,
865 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
866 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
867 tx_ring->next_to_use, eop,
868 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
869
870 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
871
872 e_info(probe,
873 "tx hang %d detected on queue %d, resetting adapter\n",
874 adapter->tx_timeout_count + 1, tx_ring->queue_index);
875
b953799e 876 /* schedule immediate reset if we believe we hung */
c83c6cbd 877 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 878
879 /* the adapter is about to reset, no point in enabling stuff */
880 return true;
881 }
9a799d71 882
e092be60 883#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
fc77dc3c 884 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 885 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 886 /* Make sure that anybody stopping the queue after this
887 * sees the new next_to_clean.
888 */
889 smp_mb();
fc77dc3c 890 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 891 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 892 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 893 ++tx_ring->tx_stats.restart_queue;
30eba97a 894 }
e092be60 895 }
9a799d71 896
807540ba 897 return count < tx_ring->work_limit;
9a799d71
AK		 898}
899
5dd2d332 900#ifdef CONFIG_IXGBE_DCA
bd0362dd 901static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 902 struct ixgbe_ring *rx_ring,
903 int cpu)
bd0362dd 904{
33cf09c9 905 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 906 u32 rxctrl;
33cf09c9
AD		 907 u8 reg_idx = rx_ring->reg_idx;
908
909 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
910 switch (hw->mac.type) {
911 case ixgbe_mac_82598EB:
912 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
913 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
914 break;
915 case ixgbe_mac_82599EB:
b93a2226 916 case ixgbe_mac_X540:
33cf09c9
AD		 917 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
918 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
919 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
920 break;
921 default:
922 break;
bd0362dd 923 }
33cf09c9
AD		 924 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
925 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
926 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 927 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 928}
929
930static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 931 struct ixgbe_ring *tx_ring,
932 int cpu)
bd0362dd 933{
33cf09c9 934 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 935 u32 txctrl;
33cf09c9
AD		 936 u8 reg_idx = tx_ring->reg_idx;
937
938 switch (hw->mac.type) {
939 case ixgbe_mac_82598EB:
940 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
941 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
942 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
943 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 944 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
945 break;
946 case ixgbe_mac_82599EB:
b93a2226 947 case ixgbe_mac_X540:
33cf09c9
AD		 948 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
949 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
950 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
951 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
952 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 953 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
954 break;
955 default:
956 break;
957 }
958}
959
960static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
961{
962 struct ixgbe_adapter *adapter = q_vector->adapter;
bd0362dd 963 int cpu = get_cpu();
33cf09c9
AD		 964 long r_idx;
965 int i;
bd0362dd 966
33cf09c9
AD		 967 if (q_vector->cpu == cpu)
968 goto out_no_update;
969
970 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
971 for (i = 0; i < q_vector->txr_count; i++) {
972 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
973 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
974 r_idx + 1);
bd0362dd 975 }
33cf09c9
AD		 976
977 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
978 for (i = 0; i < q_vector->rxr_count; i++) {
979 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
980 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
981 r_idx + 1);
982 }
983
984 q_vector->cpu = cpu;
985out_no_update:
bd0362dd
JC		 986 put_cpu();
987}
988
989static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
990{
33cf09c9 991 int num_q_vectors;
bd0362dd
JC		 992 int i;
993
994 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
995 return;
996
e35ec126
AD		 997 /* always use CB2 mode, difference is masked in the CB driver */
998 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
999
33cf09c9
AD		 1000 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1001 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1002 else
1003 num_q_vectors = 1;
1004
1005 for (i = 0; i < num_q_vectors; i++) {
1006 adapter->q_vector[i]->cpu = -1;
1007 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1008 }
1009}
1010
1011static int __ixgbe_notify_dca(struct device *dev, void *data)
1012{
c60fbb00 1013 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1014 unsigned long event = *(unsigned long *)data;
1015
33cf09c9
AD		 1016 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1017 return 0;
1018
bd0362dd
JC		 1019 switch (event) {
1020 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1021 /* if we're already enabled, don't do it again */
1022 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1023 break;
652f093f 1024 if (dca_add_requester(dev) == 0) {
96b0e0f6 1025 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1026 ixgbe_setup_dca(adapter);
1027 break;
1028 }
1029 /* Fall Through since DCA is disabled. */
1030 case DCA_PROVIDER_REMOVE:
1031 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1032 dca_remove_requester(dev);
1033 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1034 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1035 }
1036 break;
1037 }
1038
652f093f 1039 return 0;
bd0362dd 1040}
5dd2d332 1041#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 1042
1043static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1044 struct sk_buff *skb)
1045{
1046 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1047}
1048
9a799d71
AK		 1049/**
1050 * ixgbe_receive_skb - Send a completed packet up the stack
1051 * @adapter: board private structure
1052 * @skb: packet to send up
177db6ff
MC		 1053 * @status: hardware indication of status of receive
1054 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1055 * @rx_desc: rx descriptor
9a799d71 1056 **/
78b6f4ce 1057static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1058 struct sk_buff *skb, u8 status,
1059 struct ixgbe_ring *ring,
1060 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1061{
78b6f4ce
HX		 1062 struct ixgbe_adapter *adapter = q_vector->adapter;
1063 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1064 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1065 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1066
f62bbb5e
JG		 1067 if (is_vlan && (tag & VLAN_VID_MASK))
1068 __vlan_hwaccel_put_tag(skb, tag);
1069
1070 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1071 napi_gro_receive(napi, skb);
1072 else
1073 netif_rx(skb);
9a799d71
AK		 1074}
1075
e59bd25d
AV		 1076/**
1077 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1078 * @adapter: address of board private structure
1079 * @status_err: hardware indication of status of receive
1080 * @skb: skb currently being received and modified
1081 **/
9a799d71 1082static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 1083 union ixgbe_adv_rx_desc *rx_desc,
1084 struct sk_buff *skb)
9a799d71 1085{
8bae1b2b
DS		 1086 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1087
bc8acf2c 1088 skb_checksum_none_assert(skb);
9a799d71 1089
712744be
JB		 1090 /* Rx csum disabled */
1091 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1092 return;
e59bd25d
AV		 1093
1094 /* if IP and error */
1095 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1096 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1097 adapter->hw_csum_rx_error++;
1098 return;
1099 }
e59bd25d
AV		 1100
1101 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1102 return;
1103
1104 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1105 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1106
1107 /*
1108 * 82599 errata, UDP frames with a 0 checksum can be marked as
1109 * checksum errors.
1110 */
1111 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1112 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1113 return;
1114
e59bd25d
AV		 1115 adapter->hw_csum_rx_error++;
1116 return;
1117 }
1118
9a799d71 1119 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1120 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1121}
1122
84ea2591 1123static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1124{
1125 /*
1126 * Force memory writes to complete before letting h/w
1127 * know there are new descriptors to fetch. (Only
1128 * applicable for weak-ordered memory model archs,
1129 * such as IA-64).
1130 */
1131 wmb();
84ea2591 1132 writel(val, rx_ring->tail);
e8e26350
PW		 1133}
1134
9a799d71
AK		 1135/**
1136 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1137 * @rx_ring: ring to place buffers on
1138 * @cleaned_count: number of buffers to replace
9a799d71 1139 **/
fc77dc3c 1140void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1141{
9a799d71 1142 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1143 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1144 struct sk_buff *skb;
1145 u16 i = rx_ring->next_to_use;
9a799d71 1146
fc77dc3c
AD		 1147 /* do nothing if no valid netdev defined */
1148 if (!rx_ring->netdev)
1149 return;
1150
9a799d71 1151 while (cleaned_count--) {
31f05a2d 1152 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1153 bi = &rx_ring->rx_buffer_info[i];
1154 skb = bi->skb;
9a799d71 1155
d5f398ed 1156 if (!skb) {
fc77dc3c 1157 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1158 rx_ring->rx_buf_len);
9a799d71 1159 if (!skb) {
5b7da515 1160 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1161 goto no_buffers;
1162 }
d716a7d8
AD		 1163 /* initialize queue mapping */
1164 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1165 bi->skb = skb;
d716a7d8 1166 }
9a799d71 1167
d716a7d8 1168 if (!bi->dma) {
b6ec895e 1169 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1170 skb->data,
e8e9f696 1171 rx_ring->rx_buf_len,
1b507730 1172 DMA_FROM_DEVICE);
b6ec895e 1173 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1174 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1175 bi->dma = 0;
1176 goto no_buffers;
1177 }
9a799d71 1178 }
d5f398ed 1179
7d637bcc 1180 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1181 if (!bi->page) {
fc77dc3c 1182 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1183 if (!bi->page) {
5b7da515 1184 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1185 goto no_buffers;
1186 }
1187 }
1188
1189 if (!bi->page_dma) {
1190 /* use a half page if we're re-using */
1191 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1192 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1193 bi->page,
1194 bi->page_offset,
1195 PAGE_SIZE / 2,
1196 DMA_FROM_DEVICE);
b6ec895e 1197 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1198 bi->page_dma)) {
5b7da515 1199 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1200 bi->page_dma = 0;
1201 goto no_buffers;
1202 }
1203 }
1204
1205 /* Refresh the desc even if buffer_addrs didn't change
1206 * because each write-back erases this info. */
3a581073
JB		 1207 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1208 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1209 } else {
3a581073 1210 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1211 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1212 }
1213
1214 i++;
1215 if (i == rx_ring->count)
1216 i = 0;
9a799d71 1217 }
7c6e0a43 1218
9a799d71
AK		 1219no_buffers:
1220 if (rx_ring->next_to_use != i) {
1221 rx_ring->next_to_use = i;
84ea2591 1222 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1223 }
1224}
1225
c267fc16 1226static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1227{
c267fc16
AD		 1228 /* HW will not DMA in data larger than the given buffer, even if it
1229 * parses the (NFS, of course) header to be larger. In that case, it
1230 * fills the header buffer and spills the rest into the page.
1231 */
1232 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1233 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1234 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1235 if (hlen > IXGBE_RX_HDR_SIZE)
1236 hlen = IXGBE_RX_HDR_SIZE;
1237 return hlen;
7c6e0a43
JB		 1238}
1239
f8212f97
AD		 1240/**
1241 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1242 * @skb: pointer to the last skb in the rsc queue
1243 *
1244 * This function changes a queue full of hw rsc buffers into a completed
1245 * packet. It uses the ->prev pointers to find the first packet and then
1246 * turns it into the frag list owner.
1247 **/
aa80175a 1248static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1249{
1250 unsigned int frag_list_size = 0;
aa80175a 1251 unsigned int skb_cnt = 1;
f8212f97
AD		 1252
1253 while (skb->prev) {
1254 struct sk_buff *prev = skb->prev;
1255 frag_list_size += skb->len;
1256 skb->prev = NULL;
1257 skb = prev;
aa80175a 1258 skb_cnt++;
f8212f97
AD		 1259 }
1260
1261 skb_shinfo(skb)->frag_list = skb->next;
1262 skb->next = NULL;
1263 skb->len += frag_list_size;
1264 skb->data_len += frag_list_size;
1265 skb->truesize += frag_list_size;
aa80175a
AD		 1266 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1267
f8212f97
AD		 1268 return skb;
1269}
1270
aa80175a
AD		 1271static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1272{
1273 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1274 IXGBE_RXDADV_RSCCNT_MASK);
1275}
43634e82 1276
c267fc16 1277static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1278 struct ixgbe_ring *rx_ring,
1279 int *work_done, int work_to_do)
9a799d71 1280{
78b6f4ce 1281 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1282 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1283 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1284 struct sk_buff *skb;
d2f4fbe2 1285 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1286 const int current_node = numa_node_id();
3d8fd385
YZ		 1287#ifdef IXGBE_FCOE
1288 int ddp_bytes = 0;
1289#endif /* IXGBE_FCOE */
c267fc16
AD		 1290 u32 staterr;
1291 u16 i;
1292 u16 cleaned_count = 0;
aa80175a 1293 bool pkt_is_rsc = false;
9a799d71
AK		 1294
1295 i = rx_ring->next_to_clean;
31f05a2d 1296 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1297 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1298
1299 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1300 u32 upper_len = 0;
9a799d71 1301
3c945e5b 1302 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1303
c267fc16
AD		 1304 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1305
9a799d71 1306 skb = rx_buffer_info->skb;
9a799d71 1307 rx_buffer_info->skb = NULL;
c267fc16 1308 prefetch(skb->data);
9a799d71 1309
c267fc16 1310 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1311 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16
AD		 1312
1313 /* if this is a skb from previous receive DMA will be 0 */
21fa4e66 1314 if (rx_buffer_info->dma) {
c267fc16 1315 u16 hlen;
aa80175a 1316 if (pkt_is_rsc &&
c267fc16
AD		 1317 !(staterr & IXGBE_RXD_STAT_EOP) &&
1318 !skb->prev) {
43634e82
MC		 1319 /*
1320 * When HWRSC is enabled, delay unmapping
1321 * of the first packet. It carries the
1322 * header information, HW may still
1323 * access the header after the writeback.
1324 * Only unmap it when EOP is reached
1325 */
e8171aaa 1326 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1327 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1328 } else {
b6ec895e 1329 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1330 rx_buffer_info->dma,
1331 rx_ring->rx_buf_len,
1332 DMA_FROM_DEVICE);
e8171aaa 1333 }
4f57ca6e 1334 rx_buffer_info->dma = 0;
c267fc16
AD		 1335
1336 if (ring_is_ps_enabled(rx_ring)) {
1337 hlen = ixgbe_get_hlen(rx_desc);
1338 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1339 } else {
1340 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1341 }
1342
1343 skb_put(skb, hlen);
1344 } else {
1345 /* assume packet split since header is unmapped */
1346 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1347 }
1348
1349 if (upper_len) {
b6ec895e
AD		 1350 dma_unmap_page(rx_ring->dev,
1351 rx_buffer_info->page_dma,
1352 PAGE_SIZE / 2,
1353 DMA_FROM_DEVICE);
9a799d71
AK		 1354 rx_buffer_info->page_dma = 0;
1355 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1356 rx_buffer_info->page,
1357 rx_buffer_info->page_offset,
1358 upper_len);
762f4c57 1359
c267fc16
AD		 1360 if ((page_count(rx_buffer_info->page) == 1) &&
1361 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1362 get_page(rx_buffer_info->page);
c267fc16
AD		 1363 else
1364 rx_buffer_info->page = NULL;
9a799d71
AK		 1365
1366 skb->len += upper_len;
1367 skb->data_len += upper_len;
1368 skb->truesize += upper_len;
1369 }
1370
1371 i++;
1372 if (i == rx_ring->count)
1373 i = 0;
9a799d71 1374
31f05a2d 1375 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1376 prefetch(next_rxd);
9a799d71 1377 cleaned_count++;
f8212f97 1378
aa80175a 1379 if (pkt_is_rsc) {
f8212f97
AD		 1380 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1381 IXGBE_RXDADV_NEXTP_SHIFT;
1382 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1383 } else {
1384 next_buffer = &rx_ring->rx_buffer_info[i];
1385 }
1386
c267fc16 1387 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1388 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1389 rx_buffer_info->skb = next_buffer->skb;
1390 rx_buffer_info->dma = next_buffer->dma;
1391 next_buffer->skb = skb;
1392 next_buffer->dma = 0;
1393 } else {
1394 skb->next = next_buffer->skb;
1395 skb->next->prev = skb;
1396 }
5b7da515 1397 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1398 goto next_desc;
1399 }
1400
aa80175a
AD		 1401 if (skb->prev) {
1402 skb = ixgbe_transform_rsc_queue(skb);
1403 /* if we got here without RSC the packet is invalid */
1404 if (!pkt_is_rsc) {
1405 __pskb_trim(skb, 0);
1406 rx_buffer_info->skb = skb;
1407 goto next_desc;
1408 }
1409 }
c267fc16
AD		 1410
1411 if (ring_is_rsc_enabled(rx_ring)) {
1412 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1413 dma_unmap_single(rx_ring->dev,
1414 IXGBE_RSC_CB(skb)->dma,
1415 rx_ring->rx_buf_len,
1416 DMA_FROM_DEVICE);
1417 IXGBE_RSC_CB(skb)->dma = 0;
1418 IXGBE_RSC_CB(skb)->delay_unmap = false;
1419 }
aa80175a
AD		 1420 }
1421 if (pkt_is_rsc) {
c267fc16
AD		 1422 if (ring_is_ps_enabled(rx_ring))
1423 rx_ring->rx_stats.rsc_count +=
aa80175a 1424 skb_shinfo(skb)->nr_frags;
c267fc16 1425 else
aa80175a
AD		 1426 rx_ring->rx_stats.rsc_count +=
1427 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1428 rx_ring->rx_stats.rsc_flush++;
1429 }
1430
1431 /* ERR_MASK will only have valid bits if EOP set */
9a799d71 1432 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
c267fc16
AD		 1433 /* trim packet back to size 0 and recycle it */
1434 __pskb_trim(skb, 0);
1435 rx_buffer_info->skb = skb;
9a799d71
AK		 1436 goto next_desc;
1437 }
1438
8bae1b2b 1439 ixgbe_rx_checksum(adapter, rx_desc, skb);
67a74ee2
ET		 1440 if (adapter->netdev->features & NETIF_F_RXHASH)
1441 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1442
1443 /* probably a little skewed due to removing CRC */
1444 total_rx_bytes += skb->len;
1445 total_rx_packets++;
1446
fc77dc3c 1447 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1448#ifdef IXGBE_FCOE
1449 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1450 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1451 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1452 if (!ddp_bytes)
332d4a7d 1453 goto next_desc;
3d8fd385 1454 }
332d4a7d 1455#endif /* IXGBE_FCOE */
fdaff1ce 1456 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1457
1458next_desc:
1459 rx_desc->wb.upper.status_error = 0;
1460
c267fc16
AD		 1461 (*work_done)++;
1462 if (*work_done >= work_to_do)
1463 break;
1464
9a799d71
AK		 1465 /* return some buffers to hardware, one at a time is too slow */
1466 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1467 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1468 cleaned_count = 0;
1469 }
1470
1471 /* use prefetched values */
1472 rx_desc = next_rxd;
9a799d71 1473 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1474 }
1475
9a799d71 1476 rx_ring->next_to_clean = i;
7d4987de 1477 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1478
1479 if (cleaned_count)
fc77dc3c 1480 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1481
3d8fd385
YZ		 1482#ifdef IXGBE_FCOE
1483 /* include DDPed FCoE data */
1484 if (ddp_bytes > 0) {
1485 unsigned int mss;
1486
fc77dc3c 1487 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1488 sizeof(struct fc_frame_header) -
1489 sizeof(struct fcoe_crc_eof);
1490 if (mss > 512)
1491 mss &= ~511;
1492 total_rx_bytes += ddp_bytes;
1493 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1494 }
1495#endif /* IXGBE_FCOE */
1496
f494e8fa
AV		 1497 rx_ring->total_packets += total_rx_packets;
1498 rx_ring->total_bytes += total_rx_bytes;
c267fc16
AD		 1499 u64_stats_update_begin(&rx_ring->syncp);
1500 rx_ring->stats.packets += total_rx_packets;
1501 rx_ring->stats.bytes += total_rx_bytes;
1502 u64_stats_update_end(&rx_ring->syncp);
9a799d71
AK		 1503}
1504
021230d4 1505static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1506/**
1507 * ixgbe_configure_msix - Configure MSI-X hardware
1508 * @adapter: board private structure
1509 *
1510 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1511 * interrupts.
1512 **/
1513static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1514{
021230d4 1515 struct ixgbe_q_vector *q_vector;
bf29ee6c 1516 int i, q_vectors, v_idx, r_idx;
021230d4 1517 u32 mask;
9a799d71 1518
021230d4 1519 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1520
4df10466
JB		 1521 /*
1522 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1523 * corresponding register.
1524 */
1525 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1526 q_vector = adapter->q_vector[v_idx];
984b3f57 1527 /* XXX for_each_set_bit(...) */
021230d4 1528 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1529 adapter->num_rx_queues);
021230d4
AV		 1530
1531 for (i = 0; i < q_vector->rxr_count; i++) {
bf29ee6c
AD		 1532 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1533 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
021230d4 1534 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1535 adapter->num_rx_queues,
1536 r_idx + 1);
021230d4
AV		 1537 }
1538 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1539 adapter->num_tx_queues);
021230d4
AV		 1540
1541 for (i = 0; i < q_vector->txr_count; i++) {
bf29ee6c
AD		 1542 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1543 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
021230d4 1544 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1545 adapter->num_tx_queues,
1546 r_idx + 1);
021230d4
AV		 1547 }
1548
021230d4 1549 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1550 /* tx only */
1551 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1552 else if (q_vector->rxr_count)
f7554a2b
NS		 1553 /* rx or mixed */
1554 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1555
fe49f04a 1556 ixgbe_write_eitr(q_vector);
03ecf91a
AD		 1557 /* If ATR is enabled, set interrupt affinity */
1558 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
b25ebfd2
PW		 1559 /*
1560 * Allocate the affinity_hint cpumask, assign the mask
1561 * for this vector, and set our affinity_hint for
1562 * this irq.
1563 */
1564 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1565 GFP_KERNEL))
1566 return;
1567 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1568 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1569 q_vector->affinity_mask);
1570 }
9a799d71
AK		 1571 }
1572
bd508178
AD		 1573 switch (adapter->hw.mac.type) {
1574 case ixgbe_mac_82598EB:
e8e26350 1575 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1576 v_idx);
bd508178
AD		 1577 break;
1578 case ixgbe_mac_82599EB:
b93a2226 1579 case ixgbe_mac_X540:
e8e26350 1580 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178
AD		 1581 break;
1582
1583 default:
1584 break;
1585 }
021230d4
AV		 1586 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1587
41fb9248 1588 /* set up to autoclear timer, and the vectors */
021230d4 1589 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1590 if (adapter->num_vfs)
1591 mask &= ~(IXGBE_EIMS_OTHER |
1592 IXGBE_EIMS_MAILBOX |
1593 IXGBE_EIMS_LSC);
1594 else
1595 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1596 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1597}
1598
f494e8fa
AV		 1599enum latency_range {
1600 lowest_latency = 0,
1601 low_latency = 1,
1602 bulk_latency = 2,
1603 latency_invalid = 255
1604};
1605
1606/**
1607 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1608 * @adapter: pointer to adapter
1609 * @eitr: eitr setting (ints per sec) to give last timeslice
1610 * @itr_setting: current throttle rate in ints/second
1611 * @packets: the number of packets during this measurement interval
1612 * @bytes: the number of bytes during this measurement interval
1613 *
1614 * Stores a new ITR value based on packets and byte
1615 * counts during the last interrupt. The advantage of per interrupt
1616 * computation is faster updates and more accurate ITR for the current
1617 * traffic pattern. Constants in this function were computed
1618 * based on theoretical maximum wire speed and thresholds were set based
1619 * on testing data as well as attempting to minimize response time
1620 * while increasing bulk throughput.
1621 * this functionality is controlled by the InterruptThrottleRate module
1622 * parameter (see ixgbe_param.c)
1623 **/
1624static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1625 u32 eitr, u8 itr_setting,
1626 int packets, int bytes)
f494e8fa
AV		 1627{
1628 unsigned int retval = itr_setting;
1629 u32 timepassed_us;
1630 u64 bytes_perint;
1631
1632 if (packets == 0)
1633 goto update_itr_done;
1634
1635
1636 /* simple throttlerate management
1637 * 0-20MB/s lowest (100000 ints/s)
1638 * 20-100MB/s low (20000 ints/s)
1639 * 100-1249MB/s bulk (8000 ints/s)
1640 */
1641 /* what was last interrupt timeslice? */
1642 timepassed_us = 1000000/eitr;
1643 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1644
1645 switch (itr_setting) {
1646 case lowest_latency:
1647 if (bytes_perint > adapter->eitr_low)
1648 retval = low_latency;
1649 break;
1650 case low_latency:
1651 if (bytes_perint > adapter->eitr_high)
1652 retval = bulk_latency;
1653 else if (bytes_perint <= adapter->eitr_low)
1654 retval = lowest_latency;
1655 break;
1656 case bulk_latency:
1657 if (bytes_perint <= adapter->eitr_high)
1658 retval = low_latency;
1659 break;
1660 }
1661
1662update_itr_done:
1663 return retval;
1664}
1665
509ee935
JB		 1666/**
1667 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1668 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1669 *
1670 * This function is made to be called by ethtool and by the driver
1671 * when it needs to update EITR registers at runtime. Hardware
1672 * specific quirks/differences are taken care of here.
1673 */
fe49f04a 1674void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1675{
fe49f04a 1676 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1677 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1678 int v_idx = q_vector->v_idx;
1679 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1680
bd508178
AD		 1681 switch (adapter->hw.mac.type) {
1682 case ixgbe_mac_82598EB:
509ee935
JB		 1683 /* must write high and low 16 bits to reset counter */
1684 itr_reg |= (itr_reg << 16);
bd508178
AD		 1685 break;
1686 case ixgbe_mac_82599EB:
b93a2226 1687 case ixgbe_mac_X540:
f8d1dcaf 1688 /*
b93a2226 1689 * 82599 and X540 can support a value of zero, so allow it for
f8d1dcaf
JB		 1690 * max interrupt rate, but there is an errata where it can
1691 * not be zero with RSC
1692 */
1693 if (itr_reg == 8 &&
1694 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1695 itr_reg = 0;
1696
509ee935
JB		 1697 /*
1698 * set the WDIS bit to not clear the timer bits and cause an
1699 * immediate assertion of the interrupt
1700 */
1701 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1702 break;
1703 default:
1704 break;
509ee935
JB		 1705 }
1706 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1707}
1708
f494e8fa
AV		 1709static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1710{
1711 struct ixgbe_adapter *adapter = q_vector->adapter;
125601bf 1712 int i, r_idx;
f494e8fa
AV		 1713 u32 new_itr;
1714 u8 current_itr, ret_itr;
f494e8fa
AV		 1715
1716 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1717 for (i = 0; i < q_vector->txr_count; i++) {
125601bf 1718 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1719 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1720 q_vector->tx_itr,
1721 tx_ring->total_packets,
1722 tx_ring->total_bytes);
f494e8fa
AV		 1723 /* if the result for this queue would decrease interrupt
1724 * rate for this vector then use that result */
30efa5a3 1725 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1726 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1727 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1728 r_idx + 1);
f494e8fa
AV		 1729 }
1730
1731 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1732 for (i = 0; i < q_vector->rxr_count; i++) {
125601bf 1733 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1734 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1735 q_vector->rx_itr,
1736 rx_ring->total_packets,
1737 rx_ring->total_bytes);
f494e8fa
AV		 1738 /* if the result for this queue would decrease interrupt
1739 * rate for this vector then use that result */
30efa5a3 1740 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1741 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1742 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1743 r_idx + 1);
f494e8fa
AV		 1744 }
1745
30efa5a3 1746 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1747
1748 switch (current_itr) {
1749 /* counts and packets in update_itr are dependent on these numbers */
1750 case lowest_latency:
1751 new_itr = 100000;
1752 break;
1753 case low_latency:
1754 new_itr = 20000; /* aka hwitr = ~200 */
1755 break;
1756 case bulk_latency:
1757 default:
1758 new_itr = 8000;
1759 break;
1760 }
1761
1762 if (new_itr != q_vector->eitr) {
fe49f04a 1763 /* do an exponential smoothing */
125601bf 1764 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935
JB		 1765
1766 /* save the algorithm value here, not the smoothed one */
1767 q_vector->eitr = new_itr;
fe49f04a
AD		 1768
1769 ixgbe_write_eitr(q_vector);
f494e8fa 1770 }
f494e8fa
AV		 1771}
1772
119fc60a 1773/**
f0f9778d
AD		 1774 * ixgbe_check_overtemp_subtask - check for over tempurature
1775 * @adapter: pointer to adapter
119fc60a 1776 **/
f0f9778d 1777static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1778{
119fc60a
MC		 1779 struct ixgbe_hw *hw = &adapter->hw;
1780 u32 eicr = adapter->interrupt_event;
1781
f0f9778d 1782 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1783 return;
1784
f0f9778d
AD		 1785 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1786 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1787 return;
1788
1789 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1790
7ca647bd 1791 switch (hw->device_id) {
f0f9778d
AD		 1792 case IXGBE_DEV_ID_82599_T3_LOM:
1793 /*
1794 * Since the warning interrupt is for both ports
1795 * we don't have to check if:
1796 * - This interrupt wasn't for our port.
1797 * - We may have missed the interrupt so always have to
1798 * check if we got a LSC
1799 */
1800 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1801 !(eicr & IXGBE_EICR_LSC))
1802 return;
1803
1804 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1805 u32 autoneg;
1806 bool link_up = false;
7ca647bd 1807
7ca647bd
JP		 1808 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1809
f0f9778d
AD		 1810 if (link_up)
1811 return;
1812 }
1813
1814 /* Check if this is not due to overtemp */
1815 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1816 return;
1817
1818 break;
7ca647bd
JP		 1819 default:
1820 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1821 return;
7ca647bd 1822 break;
119fc60a 1823 }
7ca647bd
JP		 1824 e_crit(drv,
1825 "Network adapter has been stopped because it has over heated. "
1826 "Restart the computer. If the problem persists, "
1827 "power off the system and replace the adapter\n");
f0f9778d
AD		 1828
1829 adapter->interrupt_event = 0;
119fc60a
MC		 1830}
1831
0befdb3e
JB		 1832static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1833{
1834 struct ixgbe_hw *hw = &adapter->hw;
1835
1836 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1837 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1838 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1839 /* write to clear the interrupt */
1840 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1841 }
1842}
cf8280ee 1843
e8e26350
PW		 1844static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1845{
1846 struct ixgbe_hw *hw = &adapter->hw;
1847
73c4b7cd
AD		 1848 if (eicr & IXGBE_EICR_GPI_SDP2) {
1849 /* Clear the interrupt */
1850 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 1851 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1852 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1853 ixgbe_service_event_schedule(adapter);
1854 }
73c4b7cd
AD		 1855 }
1856
e8e26350
PW		 1857 if (eicr & IXGBE_EICR_GPI_SDP1) {
1858 /* Clear the interrupt */
1859 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 1860 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1861 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1862 ixgbe_service_event_schedule(adapter);
1863 }
e8e26350
PW		 1864 }
1865}
1866
cf8280ee
JB		 1867static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1868{
1869 struct ixgbe_hw *hw = &adapter->hw;
1870
1871 adapter->lsc_int++;
1872 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1873 adapter->link_check_timeout = jiffies;
1874 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1875 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1876 IXGBE_WRITE_FLUSH(hw);
93c52dd0 1877 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 1878 }
1879}
1880
9a799d71
AK		 1881static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1882{
a65151ba 1883 struct ixgbe_adapter *adapter = data;
9a799d71 1884 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1885 u32 eicr;
1886
1887 /*
1888 * Workaround for Silicon errata. Use clear-by-write instead
1889 * of clear-by-read. Reading with EICS will return the
1890 * interrupt causes without clearing, which later be done
1891 * with the write to EICR.
1892 */
1893 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1894 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1895
cf8280ee
JB		 1896 if (eicr & IXGBE_EICR_LSC)
1897 ixgbe_check_lsc(adapter);
d4f80882 1898
1cdd1ec8
GR		 1899 if (eicr & IXGBE_EICR_MAILBOX)
1900 ixgbe_msg_task(adapter);
1901
bd508178
AD		 1902 switch (hw->mac.type) {
1903 case ixgbe_mac_82599EB:
b93a2226 1904 case ixgbe_mac_X540:
c4cf55e5
PWJ		 1905 /* Handle Flow Director Full threshold interrupt */
1906 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 1907 int reinit_count = 0;
c4cf55e5 1908 int i;
c4cf55e5 1909 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 1910 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 1911 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 1912 &ring->state))
1913 reinit_count++;
1914 }
1915 if (reinit_count) {
1916 /* no more flow director interrupts until after init */
1917 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1918 eicr &= ~IXGBE_EICR_FLOW_DIR;
1919 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1920 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1921 }
1922 }
f0f9778d
AD		 1923 ixgbe_check_sfp_event(adapter, eicr);
1924 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1925 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1926 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1927 adapter->interrupt_event = eicr;
1928 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1929 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1930 }
1931 }
bd508178
AD		 1932 break;
1933 default:
1934 break;
c4cf55e5 1935 }
bd508178
AD		 1936
1937 ixgbe_check_fan_failure(adapter, eicr);
1938
7086400d 1939 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 1940 if (!test_bit(__IXGBE_DOWN, &adapter->state))
7086400d
AD		 1941 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1942 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
9a799d71
AK		 1943
1944 return IRQ_HANDLED;
1945}
1946
fe49f04a
AD		 1947static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1948 u64 qmask)
1949{
1950 u32 mask;
bd508178 1951 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1952
bd508178
AD		 1953 switch (hw->mac.type) {
1954 case ixgbe_mac_82598EB:
fe49f04a 1955 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1956 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1957 break;
1958 case ixgbe_mac_82599EB:
b93a2226 1959 case ixgbe_mac_X540:
fe49f04a 1960 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1961 if (mask)
1962 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1963 mask = (qmask >> 32);
bd508178
AD		 1964 if (mask)
1965 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1966 break;
1967 default:
1968 break;
fe49f04a
AD		 1969 }
1970 /* skip the flush */
1971}
1972
1973static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1974 u64 qmask)
fe49f04a
AD		 1975{
1976 u32 mask;
bd508178 1977 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1978
bd508178
AD		 1979 switch (hw->mac.type) {
1980 case ixgbe_mac_82598EB:
fe49f04a 1981 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1982 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1983 break;
1984 case ixgbe_mac_82599EB:
b93a2226 1985 case ixgbe_mac_X540:
fe49f04a 1986 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1987 if (mask)
1988 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1989 mask = (qmask >> 32);
bd508178
AD		 1990 if (mask)
1991 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1992 break;
1993 default:
1994 break;
fe49f04a
AD		 1995 }
1996 /* skip the flush */
1997}
1998
9a799d71
AK		 1999static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
2000{
021230d4
AV		 2001 struct ixgbe_q_vector *q_vector = data;
2002 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2003 struct ixgbe_ring *tx_ring;
021230d4
AV		 2004 int i, r_idx;
2005
2006 if (!q_vector->txr_count)
2007 return IRQ_HANDLED;
2008
2009 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2010 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2011 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 2012 tx_ring->total_bytes = 0;
2013 tx_ring->total_packets = 0;
021230d4 2014 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2015 r_idx + 1);
021230d4 2016 }
9a799d71 2017
9b471446 2018 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 2019 napi_schedule(&q_vector->napi);
2020
9a799d71
AK		 2021 return IRQ_HANDLED;
2022}
2023
021230d4
AV		 2024/**
2025 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2026 * @irq: unused
2027 * @data: pointer to our q_vector struct for this interrupt vector
2028 **/
9a799d71
AK		 2029static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2030{
021230d4
AV		 2031 struct ixgbe_q_vector *q_vector = data;
2032 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2033 struct ixgbe_ring *rx_ring;
021230d4 2034 int r_idx;
30efa5a3 2035 int i;
021230d4 2036
33cf09c9
AD		 2037#ifdef CONFIG_IXGBE_DCA
2038 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2039 ixgbe_update_dca(q_vector);
2040#endif
2041
021230d4 2042 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
33cf09c9 2043 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2044 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 2045 rx_ring->total_bytes = 0;
2046 rx_ring->total_packets = 0;
2047 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2048 r_idx + 1);
30efa5a3
JB		 2049 }
2050
021230d4
AV		 2051 if (!q_vector->rxr_count)
2052 return IRQ_HANDLED;
2053
9b471446 2054 /* EIAM disabled interrupts (on this vector) for us */
288379f0 2055 napi_schedule(&q_vector->napi);
021230d4
AV		 2056
2057 return IRQ_HANDLED;
2058}
2059
2060static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2061{
91281fd3
AD		 2062 struct ixgbe_q_vector *q_vector = data;
2063 struct ixgbe_adapter *adapter = q_vector->adapter;
2064 struct ixgbe_ring *ring;
2065 int r_idx;
2066 int i;
2067
2068 if (!q_vector->txr_count && !q_vector->rxr_count)
2069 return IRQ_HANDLED;
2070
2071 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2072 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2073 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2074 ring->total_bytes = 0;
2075 ring->total_packets = 0;
2076 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2077 r_idx + 1);
91281fd3
AD		 2078 }
2079
2080 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2081 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2082 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 2083 ring->total_bytes = 0;
2084 ring->total_packets = 0;
2085 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2086 r_idx + 1);
91281fd3
AD		 2087 }
2088
9b471446 2089 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2090 napi_schedule(&q_vector->napi);
9a799d71 2091
9a799d71
AK		 2092 return IRQ_HANDLED;
2093}
2094
021230d4
AV		 2095/**
2096 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2097 * @napi: napi struct with our devices info in it
2098 * @budget: amount of work driver is allowed to do this pass, in packets
2099 *
f0848276
JB		 2100 * This function is optimized for cleaning one queue only on a single
2101 * q_vector!!!
021230d4 2102 **/
9a799d71
AK		 2103static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2104{
021230d4 2105 struct ixgbe_q_vector *q_vector =
e8e9f696 2106 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2107 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 2108 struct ixgbe_ring *rx_ring = NULL;
9a799d71 2109 int work_done = 0;
021230d4 2110 long r_idx;
9a799d71 2111
5dd2d332 2112#ifdef CONFIG_IXGBE_DCA
bd0362dd 2113 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2114 ixgbe_update_dca(q_vector);
bd0362dd 2115#endif
9a799d71 2116
33cf09c9
AD		 2117 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2118 rx_ring = adapter->rx_ring[r_idx];
2119
78b6f4ce 2120 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 2121
021230d4
AV		 2122 /* If all Rx work done, exit the polling mode */
2123 if (work_done < budget) {
288379f0 2124 napi_complete(napi);
f7554a2b 2125 if (adapter->rx_itr_setting & 1)
f494e8fa 2126 ixgbe_set_itr_msix(q_vector);
9a799d71 2127 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2128 ixgbe_irq_enable_queues(adapter,
e8e9f696 2129 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 2130 }
2131
2132 return work_done;
2133}
2134
f0848276 2135/**
91281fd3 2136 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 2137 * @napi: napi struct with our devices info in it
2138 * @budget: amount of work driver is allowed to do this pass, in packets
2139 *
2140 * This function will clean more than one rx queue associated with a
2141 * q_vector.
2142 **/
91281fd3 2143static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 2144{
2145 struct ixgbe_q_vector *q_vector =
e8e9f696 2146 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 2147 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 2148 struct ixgbe_ring *ring = NULL;
f0848276
JB		 2149 int work_done = 0, i;
2150 long r_idx;
91281fd3
AD		 2151 bool tx_clean_complete = true;
2152
33cf09c9
AD		 2153#ifdef CONFIG_IXGBE_DCA
2154 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2155 ixgbe_update_dca(q_vector);
2156#endif
2157
91281fd3
AD		 2158 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2159 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2160 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2161 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2162 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2163 r_idx + 1);
91281fd3 2164 }
f0848276
JB		 2165
2166 /* attempt to distribute budget to each queue fairly, but don't allow
2167 * the budget to go below 1 because we'll exit polling */
2168 budget /= (q_vector->rxr_count ?: 1);
2169 budget = max(budget, 1);
2170 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2171 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2172 ring = adapter->rx_ring[r_idx];
91281fd3 2173 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 2174 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2175 r_idx + 1);
f0848276
JB		 2176 }
2177
2178 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 2179 ring = adapter->rx_ring[r_idx];
f0848276 2180 /* If all Rx work done, exit the polling mode */
7f821875 2181 if (work_done < budget) {
288379f0 2182 napi_complete(napi);
f7554a2b 2183 if (adapter->rx_itr_setting & 1)
f0848276
JB		 2184 ixgbe_set_itr_msix(q_vector);
2185 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2186 ixgbe_irq_enable_queues(adapter,
e8e9f696 2187 ((u64)1 << q_vector->v_idx));
f0848276
JB		 2188 return 0;
2189 }
2190
2191 return work_done;
2192}
91281fd3
AD		 2193
2194/**
2195 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2196 * @napi: napi struct with our devices info in it
2197 * @budget: amount of work driver is allowed to do this pass, in packets
2198 *
2199 * This function is optimized for cleaning one queue only on a single
2200 * q_vector!!!
2201 **/
2202static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2203{
2204 struct ixgbe_q_vector *q_vector =
e8e9f696 2205 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2206 struct ixgbe_adapter *adapter = q_vector->adapter;
2207 struct ixgbe_ring *tx_ring = NULL;
2208 int work_done = 0;
2209 long r_idx;
2210
91281fd3
AD		 2211#ifdef CONFIG_IXGBE_DCA
2212 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2213 ixgbe_update_dca(q_vector);
91281fd3
AD		 2214#endif
2215
33cf09c9
AD		 2216 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2217 tx_ring = adapter->tx_ring[r_idx];
2218
91281fd3
AD		 2219 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2220 work_done = budget;
2221
f7554a2b 2222 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2223 if (work_done < budget) {
2224 napi_complete(napi);
f7554a2b 2225 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2226 ixgbe_set_itr_msix(q_vector);
2227 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2228 ixgbe_irq_enable_queues(adapter,
2229 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2230 }
2231
2232 return work_done;
2233}
2234
021230d4 2235static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2236 int r_idx)
021230d4 2237{
7a921c93 2238 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2239 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93
AD		 2240
2241 set_bit(r_idx, q_vector->rxr_idx);
2242 q_vector->rxr_count++;
2274543f 2243 rx_ring->q_vector = q_vector;
021230d4
AV		 2244}
2245
2246static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2247 int t_idx)
021230d4 2248{
7a921c93 2249 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2250 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93
AD		 2251
2252 set_bit(t_idx, q_vector->txr_idx);
2253 q_vector->txr_count++;
2274543f 2254 tx_ring->q_vector = q_vector;
021230d4
AV		 2255}
2256
9a799d71 2257/**
021230d4
AV		 2258 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2259 * @adapter: board private structure to initialize
9a799d71 2260 *
021230d4
AV		 2261 * This function maps descriptor rings to the queue-specific vectors
2262 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2263 * one vector per ring/queue, but on a constrained vector budget, we
2264 * group the rings as "efficiently" as possible. You would add new
2265 * mapping configurations in here.
9a799d71 2266 **/
d0759ebb 2267static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2268{
d0759ebb 2269 int q_vectors;
021230d4
AV		 2270 int v_start = 0;
2271 int rxr_idx = 0, txr_idx = 0;
2272 int rxr_remaining = adapter->num_rx_queues;
2273 int txr_remaining = adapter->num_tx_queues;
2274 int i, j;
2275 int rqpv, tqpv;
2276 int err = 0;
2277
2278 /* No mapping required if MSI-X is disabled. */
2279 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2280 goto out;
9a799d71 2281
d0759ebb
AD		 2282 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2283
021230d4
AV		 2284 /*
2285 * The ideal configuration...
2286 * We have enough vectors to map one per queue.
2287 */
d0759ebb 2288 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
021230d4
AV		 2289 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2290 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2291
021230d4
AV		 2292 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2293 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2294
9a799d71 2295 goto out;
021230d4 2296 }
9a799d71 2297
021230d4
AV		 2298 /*
2299 * If we don't have enough vectors for a 1-to-1
2300 * mapping, we'll have to group them so there are
2301 * multiple queues per vector.
2302 */
2303 /* Re-adjusting *qpv takes care of the remainder. */
d0759ebb
AD		 2304 for (i = v_start; i < q_vectors; i++) {
2305 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
021230d4
AV		 2306 for (j = 0; j < rqpv; j++) {
2307 map_vector_to_rxq(adapter, i, rxr_idx);
2308 rxr_idx++;
2309 rxr_remaining--;
2310 }
d0759ebb 2311 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
021230d4
AV		 2312 for (j = 0; j < tqpv; j++) {
2313 map_vector_to_txq(adapter, i, txr_idx);
2314 txr_idx++;
2315 txr_remaining--;
9a799d71 2316 }
9a799d71 2317 }
021230d4
AV		 2318out:
2319 return err;
2320}
2321
2322/**
2323 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2324 * @adapter: board private structure
2325 *
2326 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2327 * interrupts from the kernel.
2328 **/
2329static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2330{
2331 struct net_device *netdev = adapter->netdev;
2332 irqreturn_t (*handler)(int, void *);
2333 int i, vector, q_vectors, err;
e8e9f696 2334 int ri = 0, ti = 0;
021230d4
AV		 2335
2336 /* Decrement for Other and TCP Timer vectors */
2337 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2338
d0759ebb 2339 err = ixgbe_map_rings_to_vectors(adapter);
021230d4 2340 if (err)
d0759ebb 2341 return err;
021230d4 2342
d0759ebb
AD		 2343#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2344 ? &ixgbe_msix_clean_many : \
2345 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2346 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2347 NULL)
021230d4 2348 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb
AD		 2349 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2350 handler = SET_HANDLER(q_vector);
cb13fc20 2351
e8e9f696 2352 if (handler == &ixgbe_msix_clean_rx) {
9fe93afd
DS		 2353 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2354 "%s-%s-%d", netdev->name, "rx", ri++);
e8e9f696 2355 } else if (handler == &ixgbe_msix_clean_tx) {
9fe93afd
DS		 2356 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2357 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb 2358 } else if (handler == &ixgbe_msix_clean_many) {
9fe93afd
DS		 2359 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2360 "%s-%s-%d", netdev->name, "TxRx", ri++);
32aa77a4 2361 ti++;
d0759ebb
AD		 2362 } else {
2363 /* skip this unused q_vector */
2364 continue;
32aa77a4 2365 }
021230d4 2366 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb
AD		 2367 handler, 0, q_vector->name,
2368 q_vector);
9a799d71 2369 if (err) {
396e799c 2370 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2371 "Error: %d\n", err);
021230d4 2372 goto free_queue_irqs;
9a799d71 2373 }
9a799d71
AK		 2374 }
2375
d0759ebb 2376 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
021230d4 2377 err = request_irq(adapter->msix_entries[vector].vector,
a65151ba 2378 ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
9a799d71 2379 if (err) {
396e799c 2380 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2381 goto free_queue_irqs;
9a799d71
AK		 2382 }
2383
9a799d71
AK		 2384 return 0;
2385
021230d4
AV		 2386free_queue_irqs:
2387 for (i = vector - 1; i >= 0; i--)
2388 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2389 adapter->q_vector[i]);
021230d4
AV		 2390 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2391 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2392 kfree(adapter->msix_entries);
2393 adapter->msix_entries = NULL;
9a799d71
AK		 2394 return err;
2395}
2396
f494e8fa
AV		 2397static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2398{
7a921c93 2399 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
4a0b9ca0
PW		 2400 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2401 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
125601bf
AD		 2402 u32 new_itr = q_vector->eitr;
2403 u8 current_itr;
f494e8fa 2404
30efa5a3 2405 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2406 q_vector->tx_itr,
2407 tx_ring->total_packets,
2408 tx_ring->total_bytes);
30efa5a3 2409 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2410 q_vector->rx_itr,
2411 rx_ring->total_packets,
2412 rx_ring->total_bytes);
f494e8fa 2413
30efa5a3 2414 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2415
2416 switch (current_itr) {
2417 /* counts and packets in update_itr are dependent on these numbers */
2418 case lowest_latency:
2419 new_itr = 100000;
2420 break;
2421 case low_latency:
2422 new_itr = 20000; /* aka hwitr = ~200 */
2423 break;
2424 case bulk_latency:
2425 new_itr = 8000;
2426 break;
2427 default:
2428 break;
2429 }
2430
2431 if (new_itr != q_vector->eitr) {
fe49f04a 2432 /* do an exponential smoothing */
125601bf 2433 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935 2434
125601bf 2435 /* save the algorithm value here */
509ee935 2436 q_vector->eitr = new_itr;
fe49f04a
AD		 2437
2438 ixgbe_write_eitr(q_vector);
f494e8fa 2439 }
f494e8fa
AV		 2440}
2441
79aefa45
AD		 2442/**
2443 * ixgbe_irq_enable - Enable default interrupt generation settings
2444 * @adapter: board private structure
2445 **/
6af3b9eb
ET		 2446static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2447 bool flush)
79aefa45
AD		 2448{
2449 u32 mask;
835462fc
NS		 2450
2451 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2452 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2453 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2454 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2455 mask |= IXGBE_EIMS_GPI_SDP1;
bd508178
AD		 2456 switch (adapter->hw.mac.type) {
2457 case ixgbe_mac_82599EB:
b93a2226 2458 case ixgbe_mac_X540:
2a41ff81 2459 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2460 mask |= IXGBE_EIMS_GPI_SDP1;
2461 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2462 if (adapter->num_vfs)
2463 mask |= IXGBE_EIMS_MAILBOX;
bd508178
AD		 2464 break;
2465 default:
2466 break;
e8e26350 2467 }
03ecf91a 2468 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
c4cf55e5 2469 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2470
79aefa45 2471 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2472 if (queues)
2473 ixgbe_irq_enable_queues(adapter, ~0);
2474 if (flush)
2475 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2476
2477 if (adapter->num_vfs > 32) {
2478 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2479 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2480 }
79aefa45 2481}
021230d4 2482
9a799d71 2483/**
021230d4 2484 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2485 * @irq: interrupt number
2486 * @data: pointer to a network interface device structure
9a799d71
AK		 2487 **/
2488static irqreturn_t ixgbe_intr(int irq, void *data)
2489{
a65151ba 2490 struct ixgbe_adapter *adapter = data;
9a799d71 2491 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2492 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2493 u32 eicr;
2494
54037505 2495 /*
6af3b9eb 2496 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2497 * before the read of EICR.
2498 */
2499 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2500
021230d4
AV		 2501 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2502 * therefore no explict interrupt disable is necessary */
2503 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2504 if (!eicr) {
6af3b9eb
ET		 2505 /*
2506 * shared interrupt alert!
f47cf66e 2507 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2508 * have disabled interrupts due to EIAM
2509 * finish the workaround of silicon errata on 82598. Unmask
2510 * the interrupt that we masked before the EICR read.
2511 */
2512 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2513 ixgbe_irq_enable(adapter, true, true);
9a799d71 2514 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2515 }
9a799d71 2516
cf8280ee
JB		 2517 if (eicr & IXGBE_EICR_LSC)
2518 ixgbe_check_lsc(adapter);
021230d4 2519
bd508178
AD		 2520 switch (hw->mac.type) {
2521 case ixgbe_mac_82599EB:
e8e26350 2522 ixgbe_check_sfp_event(adapter, eicr);
bd508178
AD		 2523 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2524 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
f0f9778d
AD		 2525 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2526 adapter->interrupt_event = eicr;
2527 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2528 ixgbe_service_event_schedule(adapter);
2529 }
bd508178
AD		 2530 }
2531 break;
2532 default:
2533 break;
2534 }
e8e26350 2535
0befdb3e
JB		 2536 ixgbe_check_fan_failure(adapter, eicr);
2537
7a921c93 2538 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2539 adapter->tx_ring[0]->total_packets = 0;
2540 adapter->tx_ring[0]->total_bytes = 0;
2541 adapter->rx_ring[0]->total_packets = 0;
2542 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2543 /* would disable interrupts here but EIAM disabled it */
7a921c93 2544 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2545 }
2546
6af3b9eb
ET		 2547 /*
2548 * re-enable link(maybe) and non-queue interrupts, no flush.
2549 * ixgbe_poll will re-enable the queue interrupts
2550 */
2551
2552 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2553 ixgbe_irq_enable(adapter, false, false);
2554
9a799d71
AK		 2555 return IRQ_HANDLED;
2556}
2557
021230d4
AV		 2558static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2559{
2560 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2561
2562 for (i = 0; i < q_vectors; i++) {
7a921c93 2563 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2564 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2565 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2566 q_vector->rxr_count = 0;
2567 q_vector->txr_count = 0;
2568 }
2569}
2570
9a799d71
AK		 2571/**
2572 * ixgbe_request_irq - initialize interrupts
2573 * @adapter: board private structure
2574 *
2575 * Attempts to configure interrupts using the best available
2576 * capabilities of the hardware and kernel.
2577 **/
021230d4 2578static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2579{
2580 struct net_device *netdev = adapter->netdev;
021230d4 2581 int err;
9a799d71 2582
021230d4
AV		 2583 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2584 err = ixgbe_request_msix_irqs(adapter);
2585 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2586 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2587 netdev->name, adapter);
021230d4 2588 } else {
a0607fd3 2589 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2590 netdev->name, adapter);
9a799d71
AK		 2591 }
2592
9a799d71 2593 if (err)
396e799c 2594 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2595
9a799d71
AK		 2596 return err;
2597}
2598
2599static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2600{
9a799d71 2601 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2602 int i, q_vectors;
9a799d71 2603
021230d4
AV		 2604 q_vectors = adapter->num_msix_vectors;
2605
2606 i = q_vectors - 1;
a65151ba 2607 free_irq(adapter->msix_entries[i].vector, adapter);
9a799d71 2608
021230d4
AV		 2609 i--;
2610 for (; i >= 0; i--) {
894ff7cf
AD		 2611 /* free only the irqs that were actually requested */
2612 if (!adapter->q_vector[i]->rxr_count &&
2613 !adapter->q_vector[i]->txr_count)
2614 continue;
2615
021230d4 2616 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2617 adapter->q_vector[i]);
021230d4
AV		 2618 }
2619
2620 ixgbe_reset_q_vectors(adapter);
2621 } else {
a65151ba 2622 free_irq(adapter->pdev->irq, adapter);
9a799d71
AK		 2623 }
2624}
2625
22d5a71b
JB		 2626/**
2627 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2628 * @adapter: board private structure
2629 **/
2630static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2631{
bd508178
AD		 2632 switch (adapter->hw.mac.type) {
2633 case ixgbe_mac_82598EB:
835462fc 2634 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2635 break;
2636 case ixgbe_mac_82599EB:
b93a2226 2637 case ixgbe_mac_X540:
835462fc
NS		 2638 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2640 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2641 if (adapter->num_vfs > 32)
2642 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
bd508178
AD		 2643 break;
2644 default:
2645 break;
22d5a71b
JB		 2646 }
2647 IXGBE_WRITE_FLUSH(&adapter->hw);
2648 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2649 int i;
2650 for (i = 0; i < adapter->num_msix_vectors; i++)
2651 synchronize_irq(adapter->msix_entries[i].vector);
2652 } else {
2653 synchronize_irq(adapter->pdev->irq);
2654 }
2655}
2656
9a799d71
AK		 2657/**
2658 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2659 *
2660 **/
2661static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2662{
9a799d71
AK		 2663 struct ixgbe_hw *hw = &adapter->hw;
2664
021230d4 2665 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2666 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2667
e8e26350
PW		 2668 ixgbe_set_ivar(adapter, 0, 0, 0);
2669 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2670
2671 map_vector_to_rxq(adapter, 0, 0);
2672 map_vector_to_txq(adapter, 0, 0);
2673
396e799c 2674 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2675}
2676
43e69bf0
AD		 2677/**
2678 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2679 * @adapter: board private structure
2680 * @ring: structure containing ring specific data
2681 *
2682 * Configure the Tx descriptor ring after a reset.
2683 **/
84418e3b
AD		 2684void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2685 struct ixgbe_ring *ring)
43e69bf0
AD		 2686{
2687 struct ixgbe_hw *hw = &adapter->hw;
2688 u64 tdba = ring->dma;
2f1860b8
AD		 2689 int wait_loop = 10;
2690 u32 txdctl;
bf29ee6c 2691 u8 reg_idx = ring->reg_idx;
43e69bf0 2692
2f1860b8
AD		 2693 /* disable queue to avoid issues while updating state */
2694 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2695 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2696 txdctl & ~IXGBE_TXDCTL_ENABLE);
2697 IXGBE_WRITE_FLUSH(hw);
2698
43e69bf0 2699 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2700 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2701 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2702 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2703 ring->count * sizeof(union ixgbe_adv_tx_desc));
2704 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2705 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2706 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2707
2f1860b8
AD		 2708 /* configure fetching thresholds */
2709 if (adapter->rx_itr_setting == 0) {
2710 /* cannot set wthresh when itr==0 */
2711 txdctl &= ~0x007F0000;
2712 } else {
2713 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2714 txdctl |= (8 << 16);
2715 }
2716 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2717 /* PThresh workaround for Tx hang with DFP enabled. */
2718 txdctl |= 32;
2719 }
2720
2721 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2722 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2723 adapter->atr_sample_rate) {
2724 ring->atr_sample_rate = adapter->atr_sample_rate;
2725 ring->atr_count = 0;
2726 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2727 } else {
2728 ring->atr_sample_rate = 0;
2729 }
2f1860b8 2730
c84d324c
JF		 2731 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2732
2f1860b8
AD		 2733 /* enable queue */
2734 txdctl |= IXGBE_TXDCTL_ENABLE;
2735 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2736
2737 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2738 if (hw->mac.type == ixgbe_mac_82598EB &&
2739 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2740 return;
2741
2742 /* poll to verify queue is enabled */
2743 do {
032b4325 2744 usleep_range(1000, 2000);
2f1860b8
AD		 2745 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2746 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2747 if (!wait_loop)
2748 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2749}
2750
120ff942
AD		 2751static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2752{
2753 struct ixgbe_hw *hw = &adapter->hw;
2754 u32 rttdcs;
72a32f1f 2755 u32 reg;
8b1c0b24 2756 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2757
2758 if (hw->mac.type == ixgbe_mac_82598EB)
2759 return;
2760
2761 /* disable the arbiter while setting MTQC */
2762 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2763 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2764 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2765
2766 /* set transmit pool layout */
8b1c0b24 2767 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2768 case (IXGBE_FLAG_SRIOV_ENABLED):
2769 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2770 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2771 break;
8b1c0b24
JF		 2772 default:
2773 if (!tcs)
2774 reg = IXGBE_MTQC_64Q_1PB;
2775 else if (tcs <= 4)
2776 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2777 else
2778 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2779
8b1c0b24 2780 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2781
8b1c0b24
JF		 2782 /* Enable Security TX Buffer IFG for multiple pb */
2783 if (tcs) {
2784 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2785 reg |= IXGBE_SECTX_DCB;
2786 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2787 }
120ff942
AD		 2788 break;
2789 }
2790
2791 /* re-enable the arbiter */
2792 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2793 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2794}
2795
9a799d71 2796/**
3a581073 2797 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2798 * @adapter: board private structure
2799 *
2800 * Configure the Tx unit of the MAC after a reset.
2801 **/
2802static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2803{
2f1860b8
AD		 2804 struct ixgbe_hw *hw = &adapter->hw;
2805 u32 dmatxctl;
43e69bf0 2806 u32 i;
9a799d71 2807
2f1860b8
AD		 2808 ixgbe_setup_mtqc(adapter);
2809
2810 if (hw->mac.type != ixgbe_mac_82598EB) {
2811 /* DMATXCTL.EN must be before Tx queues are enabled */
2812 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2813 dmatxctl |= IXGBE_DMATXCTL_TE;
2814 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2815 }
2816
9a799d71 2817 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2818 for (i = 0; i < adapter->num_tx_queues; i++)
2819 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2820}
2821
e8e26350 2822#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2823
a6616b42 2824static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2825 struct ixgbe_ring *rx_ring)
cc41ac7c 2826{
cc41ac7c 2827 u32 srrctl;
bf29ee6c 2828 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2829
bd508178
AD		 2830 switch (adapter->hw.mac.type) {
2831 case ixgbe_mac_82598EB: {
2832 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2833 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2834 reg_idx = reg_idx & mask;
cc41ac7c 2835 }
bd508178
AD		 2836 break;
2837 case ixgbe_mac_82599EB:
b93a2226 2838 case ixgbe_mac_X540:
bd508178
AD		 2839 default:
2840 break;
2841 }
2842
bf29ee6c 2843 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2844
2845 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2846 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2847 if (adapter->num_vfs)
2848 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2849
afafd5b0
AD		 2850 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2851 IXGBE_SRRCTL_BSIZEHDR_MASK;
2852
7d637bcc 2853 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2854#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2855 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2856#else
2857 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2858#endif
cc41ac7c 2859 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2860 } else {
afafd5b0
AD		 2861 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2862 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2863 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2864 }
e8e26350 2865
bf29ee6c 2866 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2867}
9a799d71 2868
05abb126 2869static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2870{
05abb126
AD		 2871 struct ixgbe_hw *hw = &adapter->hw;
2872 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2873 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2874 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2875 u32 mrqc = 0, reta = 0;
2876 u32 rxcsum;
2877 int i, j;
8b1c0b24 2878 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2879 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2880
2881 if (tcs)
2882 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2883
05abb126
AD		 2884 /* Fill out hash function seeds */
2885 for (i = 0; i < 10; i++)
2886 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2887
2888 /* Fill out redirection table */
2889 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2890 if (j == maxq)
05abb126
AD		 2891 j = 0;
2892 /* reta = 4-byte sliding window of
2893 * 0x00..(indices-1)(indices-1)00..etc. */
2894 reta = (reta << 8) | (j * 0x11);
2895 if ((i & 3) == 3)
2896 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2897 }
0cefafad 2898
05abb126
AD		 2899 /* Disable indicating checksum in descriptor, enables RSS hash */
2900 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2901 rxcsum |= IXGBE_RXCSUM_PCSD;
2902 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2903
8b1c0b24
JF		 2904 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2905 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2906 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2907 } else {
2908 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2909 | IXGBE_FLAG_SRIOV_ENABLED);
2910
2911 switch (mask) {
2912 case (IXGBE_FLAG_RSS_ENABLED):
2913 if (!tcs)
2914 mrqc = IXGBE_MRQC_RSSEN;
2915 else if (tcs <= 4)
2916 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2917 else
2918 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2919 break;
2920 case (IXGBE_FLAG_SRIOV_ENABLED):
2921 mrqc = IXGBE_MRQC_VMDQEN;
2922 break;
2923 default:
2924 break;
2925 }
0cefafad
JB		 2926 }
2927
05abb126
AD		 2928 /* Perform hash on these packet types */
2929 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2930 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2931 | IXGBE_MRQC_RSS_FIELD_IPV6
2932 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2933
2934 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2935}
2936
b93a2226
DS		 2937/**
2938 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2939 * @adapter: address of board private structure
2940 * @ring: structure containing ring specific data
2941 **/
2942void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2943 struct ixgbe_ring *ring)
2944{
2945 struct ixgbe_hw *hw = &adapter->hw;
2946 u32 rscctrl;
2947 u8 reg_idx = ring->reg_idx;
2948
2949 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2950 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2951 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2952}
2953
bb5a9ad2
NS		 2954/**
2955 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2956 * @adapter: address of board private structure
2957 * @index: index of ring to set
bb5a9ad2 2958 **/
b93a2226 2959void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2960 struct ixgbe_ring *ring)
bb5a9ad2 2961{
bb5a9ad2 2962 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2963 u32 rscctrl;
edd2ea55 2964 int rx_buf_len;
bf29ee6c 2965 u8 reg_idx = ring->reg_idx;
7367096a 2966
7d637bcc 2967 if (!ring_is_rsc_enabled(ring))
7367096a 2968 return;
bb5a9ad2 2969
7367096a
AD		 2970 rx_buf_len = ring->rx_buf_len;
2971 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2972 rscctrl |= IXGBE_RSCCTL_RSCEN;
2973 /*
2974 * we must limit the number of descriptors so that the
2975 * total size of max desc * buf_len is not greater
2976 * than 65535
2977 */
7d637bcc 2978 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2979#if (MAX_SKB_FRAGS > 16)
2980 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2981#elif (MAX_SKB_FRAGS > 8)
2982 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2983#elif (MAX_SKB_FRAGS > 4)
2984 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2985#else
2986 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2987#endif
2988 } else {
2989 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2990 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2991 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2992 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2993 else
2994 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2995 }
7367096a 2996 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2997}
2998
9e10e045
AD		 2999/**
3000 * ixgbe_set_uta - Set unicast filter table address
3001 * @adapter: board private structure
3002 *
3003 * The unicast table address is a register array of 32-bit registers.
3004 * The table is meant to be used in a way similar to how the MTA is used
3005 * however due to certain limitations in the hardware it is necessary to
3006 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
3007 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
3008 **/
3009static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
3010{
3011 struct ixgbe_hw *hw = &adapter->hw;
3012 int i;
3013
3014 /* The UTA table only exists on 82599 hardware and newer */
3015 if (hw->mac.type < ixgbe_mac_82599EB)
3016 return;
3017
3018 /* we only need to do this if VMDq is enabled */
3019 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3020 return;
3021
3022 for (i = 0; i < 128; i++)
3023 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3024}
3025
3026#define IXGBE_MAX_RX_DESC_POLL 10
3027static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3028 struct ixgbe_ring *ring)
3029{
3030 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3031 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3032 u32 rxdctl;
bf29ee6c 3033 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3034
3035 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3036 if (hw->mac.type == ixgbe_mac_82598EB &&
3037 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3038 return;
3039
3040 do {
032b4325 3041 usleep_range(1000, 2000);
9e10e045
AD		 3042 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3043 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3044
3045 if (!wait_loop) {
3046 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3047 "the polling period\n", reg_idx);
3048 }
3049}
3050
2d39d576
YZ		 3051void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3052 struct ixgbe_ring *ring)
3053{
3054 struct ixgbe_hw *hw = &adapter->hw;
3055 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3056 u32 rxdctl;
3057 u8 reg_idx = ring->reg_idx;
3058
3059 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3060 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3061
3062 /* write value back with RXDCTL.ENABLE bit cleared */
3063 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3064
3065 if (hw->mac.type == ixgbe_mac_82598EB &&
3066 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3067 return;
3068
3069 /* the hardware may take up to 100us to really disable the rx queue */
3070 do {
3071 udelay(10);
3072 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3073 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3074
3075 if (!wait_loop) {
3076 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3077 "the polling period\n", reg_idx);
3078 }
3079}
3080
84418e3b
AD		 3081void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3082 struct ixgbe_ring *ring)
acd37177
AD		 3083{
3084 struct ixgbe_hw *hw = &adapter->hw;
3085 u64 rdba = ring->dma;
9e10e045 3086 u32 rxdctl;
bf29ee6c 3087 u8 reg_idx = ring->reg_idx;
acd37177 3088
9e10e045
AD		 3089 /* disable queue to avoid issues while updating state */
3090 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3091 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3092
acd37177
AD		 3093 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3094 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3095 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3096 ring->count * sizeof(union ixgbe_adv_rx_desc));
3097 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3098 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3099 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3100
3101 ixgbe_configure_srrctl(adapter, ring);
3102 ixgbe_configure_rscctl(adapter, ring);
3103
e9f98072
GR		 3104 /* If operating in IOV mode set RLPML for X540 */
3105 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3106 hw->mac.type == ixgbe_mac_X540) {
3107 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3108 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3109 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3110 }
3111
9e10e045
AD		 3112 if (hw->mac.type == ixgbe_mac_82598EB) {
3113 /*
3114 * enable cache line friendly hardware writes:
3115 * PTHRESH=32 descriptors (half the internal cache),
3116 * this also removes ugly rx_no_buffer_count increment
3117 * HTHRESH=4 descriptors (to minimize latency on fetch)
3118 * WTHRESH=8 burst writeback up to two cache lines
3119 */
3120 rxdctl &= ~0x3FFFFF;
3121 rxdctl |= 0x080420;
3122 }
3123
3124 /* enable receive descriptor ring */
3125 rxdctl |= IXGBE_RXDCTL_ENABLE;
3126 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3127
3128 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3129 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3130}
3131
48654521
AD		 3132static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3133{
3134 struct ixgbe_hw *hw = &adapter->hw;
3135 int p;
3136
3137 /* PSRTYPE must be initialized in non 82598 adapters */
3138 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3139 IXGBE_PSRTYPE_UDPHDR |
3140 IXGBE_PSRTYPE_IPV4HDR |
48654521 3141 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3142 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3143
3144 if (hw->mac.type == ixgbe_mac_82598EB)
3145 return;
3146
3147 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3148 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3149
3150 for (p = 0; p < adapter->num_rx_pools; p++)
3151 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3152 psrtype);
3153}
3154
f5b4a52e
AD		 3155static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3156{
3157 struct ixgbe_hw *hw = &adapter->hw;
3158 u32 gcr_ext;
3159 u32 vt_reg_bits;
3160 u32 reg_offset, vf_shift;
3161 u32 vmdctl;
3162
3163 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3164 return;
3165
3166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3167 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3168 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3169 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3170
3171 vf_shift = adapter->num_vfs % 32;
3172 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3173
3174 /* Enable only the PF's pool for Tx/Rx */
3175 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3176 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3177 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3178 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3179 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3180
3181 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3182 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3183
3184 /*
3185 * Set up VF register offsets for selected VT Mode,
3186 * i.e. 32 or 64 VFs for SR-IOV
3187 */
3188 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3189 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3190 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3191 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3192
3193 /* enable Tx loopback for VF/PF communication */
3194 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 3195 /* Enable MAC Anti-Spoofing */
a1cbb15c
GR		 3196 hw->mac.ops.set_mac_anti_spoofing(hw,
3197 (adapter->antispoofing_enabled =
3198 (adapter->num_vfs != 0)),
a985b6c3 3199 adapter->num_vfs);
f5b4a52e
AD		 3200}
3201
477de6ed 3202static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3203{
9a799d71
AK		 3204 struct ixgbe_hw *hw = &adapter->hw;
3205 struct net_device *netdev = adapter->netdev;
3206 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3207 int rx_buf_len;
477de6ed
AD		 3208 struct ixgbe_ring *rx_ring;
3209 int i;
3210 u32 mhadd, hlreg0;
48654521 3211
9a799d71 3212 /* Decide whether to use packet split mode or not */
a124339a
DS		 3213 /* On by default */
3214 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3215
1cdd1ec8 3216 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 3217 if (adapter->num_vfs)
3218 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3219
3220 /* Disable packet split due to 82599 erratum #45 */
3221 if (hw->mac.type == ixgbe_mac_82599EB)
3222 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 3223
3224 /* Set the RX buffer length according to the mode */
3225 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 3226 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 3227 } else {
0c19d6af 3228 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 3229 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 3230 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 3231 else
477de6ed 3232 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 3233 }
3234
63f39bd1 3235#ifdef IXGBE_FCOE
477de6ed
AD		 3236 /* adjust max frame to be able to do baby jumbo for FCoE */
3237 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3238 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3239 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3240
477de6ed
AD		 3241#endif /* IXGBE_FCOE */
3242 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3243 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3244 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3245 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3246
3247 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3248 }
3249
3250 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3251 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3252 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3253 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3254
0cefafad
JB		 3255 /*
3256 * Setup the HW Rx Head and Tail Descriptor Pointers and
3257 * the Base and Length of the Rx Descriptor Ring
3258 */
9a799d71 3259 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3260 rx_ring = adapter->rx_ring[i];
a6616b42 3261 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3262
6e455b89 3263 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3264 set_ring_ps_enabled(rx_ring);
3265 else
3266 clear_ring_ps_enabled(rx_ring);
3267
3268 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3269 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3270 else
7d637bcc 3271 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3272
63f39bd1 3273#ifdef IXGBE_FCOE
e8e9f696 3274 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3275 struct ixgbe_ring_feature *f;
3276 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3277 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3278 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3279 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3280 rx_ring->rx_buf_len =
e8e9f696 3281 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3282 } else if (!ring_is_rsc_enabled(rx_ring) &&
3283 !ring_is_ps_enabled(rx_ring)) {
3284 rx_ring->rx_buf_len =
3285 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3286 }
63f39bd1 3287 }
63f39bd1 3288#endif /* IXGBE_FCOE */
477de6ed 3289 }
477de6ed
AD		 3290}
3291
7367096a
AD		 3292static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3293{
3294 struct ixgbe_hw *hw = &adapter->hw;
3295 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3296
3297 switch (hw->mac.type) {
3298 case ixgbe_mac_82598EB:
3299 /*
3300 * For VMDq support of different descriptor types or
3301 * buffer sizes through the use of multiple SRRCTL
3302 * registers, RDRXCTL.MVMEN must be set to 1
3303 *
3304 * also, the manual doesn't mention it clearly but DCA hints
3305 * will only use queue 0's tags unless this bit is set. Side
3306 * effects of setting this bit are only that SRRCTL must be
3307 * fully programmed [0..15]
3308 */
3309 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3310 break;
3311 case ixgbe_mac_82599EB:
b93a2226 3312 case ixgbe_mac_X540:
7367096a
AD		 3313 /* Disable RSC for ACK packets */
3314 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3315 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3316 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3317 /* hardware requires some bits to be set by default */
3318 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3319 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3320 break;
3321 default:
3322 /* We should do nothing since we don't know this hardware */
3323 return;
3324 }
3325
3326 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3327}
3328
477de6ed
AD		 3329/**
3330 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3331 * @adapter: board private structure
3332 *
3333 * Configure the Rx unit of the MAC after a reset.
3334 **/
3335static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3336{
3337 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3338 int i;
3339 u32 rxctrl;
477de6ed
AD		 3340
3341 /* disable receives while setting up the descriptors */
3342 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3343 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3344
3345 ixgbe_setup_psrtype(adapter);
7367096a 3346 ixgbe_setup_rdrxctl(adapter);
477de6ed 3347
9e10e045 3348 /* Program registers for the distribution of queues */
f5b4a52e 3349 ixgbe_setup_mrqc(adapter);
f5b4a52e 3350
9e10e045
AD		 3351 ixgbe_set_uta(adapter);
3352
477de6ed
AD		 3353 /* set_rx_buffer_len must be called before ring initialization */
3354 ixgbe_set_rx_buffer_len(adapter);
3355
3356 /*
3357 * Setup the HW Rx Head and Tail Descriptor Pointers and
3358 * the Base and Length of the Rx Descriptor Ring
3359 */
9e10e045
AD		 3360 for (i = 0; i < adapter->num_rx_queues; i++)
3361 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3362
9e10e045
AD		 3363 /* disable drop enable for 82598 parts */
3364 if (hw->mac.type == ixgbe_mac_82598EB)
3365 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3366
3367 /* enable all receives */
3368 rxctrl |= IXGBE_RXCTRL_RXEN;
3369 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3370}
3371
068c89b0
DS		 3372static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3373{
3374 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3375 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3376 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3377
3378 /* add VID to filter table */
1ada1b1b 3379 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3380 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3381}
3382
3383static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3384{
3385 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3386 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3387 int pool_ndx = adapter->num_vfs;
068c89b0 3388
068c89b0 3389 /* remove VID from filter table */
1ada1b1b 3390 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3391 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3392}
3393
5f6c0181
JB		 3394/**
3395 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3396 * @adapter: driver data
3397 */
3398static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3399{
3400 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3401 u32 vlnctrl;
3402
3403 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3404 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3405 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3406}
3407
3408/**
3409 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3410 * @adapter: driver data
3411 */
3412static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3413{
3414 struct ixgbe_hw *hw = &adapter->hw;
3415 u32 vlnctrl;
3416
3417 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3418 vlnctrl |= IXGBE_VLNCTRL_VFE;
3419 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3420 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3421}
3422
3423/**
3424 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3425 * @adapter: driver data
3426 */
3427static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3428{
3429 struct ixgbe_hw *hw = &adapter->hw;
3430 u32 vlnctrl;
5f6c0181
JB		 3431 int i, j;
3432
3433 switch (hw->mac.type) {
3434 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3435 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3436 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3437 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3438 break;
3439 case ixgbe_mac_82599EB:
b93a2226 3440 case ixgbe_mac_X540:
5f6c0181
JB		 3441 for (i = 0; i < adapter->num_rx_queues; i++) {
3442 j = adapter->rx_ring[i]->reg_idx;
3443 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3444 vlnctrl &= ~IXGBE_RXDCTL_VME;
3445 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3446 }
3447 break;
3448 default:
3449 break;
3450 }
3451}
3452
3453/**
f62bbb5e 3454 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3455 * @adapter: driver data
3456 */
f62bbb5e 3457static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3458{
3459 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3460 u32 vlnctrl;
5f6c0181
JB		 3461 int i, j;
3462
3463 switch (hw->mac.type) {
3464 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3465 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3466 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3467 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3468 break;
3469 case ixgbe_mac_82599EB:
b93a2226 3470 case ixgbe_mac_X540:
5f6c0181
JB		 3471 for (i = 0; i < adapter->num_rx_queues; i++) {
3472 j = adapter->rx_ring[i]->reg_idx;
3473 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3474 vlnctrl |= IXGBE_RXDCTL_VME;
3475 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3476 }
3477 break;
3478 default:
3479 break;
3480 }
3481}
3482
9a799d71
AK		 3483static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3484{
f62bbb5e 3485 u16 vid;
9a799d71 3486
f62bbb5e
JG		 3487 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3488
3489 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3490 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3491}
3492
2850062a
AD		 3493/**
3494 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3495 * @netdev: network interface device structure
3496 *
3497 * Writes unicast address list to the RAR table.
3498 * Returns: -ENOMEM on failure/insufficient address space
3499 * 0 on no addresses written
3500 * X on writing X addresses to the RAR table
3501 **/
3502static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3503{
3504 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3505 struct ixgbe_hw *hw = &adapter->hw;
3506 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3507 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3508 int count = 0;
3509
3510 /* return ENOMEM indicating insufficient memory for addresses */
3511 if (netdev_uc_count(netdev) > rar_entries)
3512 return -ENOMEM;
3513
3514 if (!netdev_uc_empty(netdev) && rar_entries) {
3515 struct netdev_hw_addr *ha;
3516 /* return error if we do not support writing to RAR table */
3517 if (!hw->mac.ops.set_rar)
3518 return -ENOMEM;
3519
3520 netdev_for_each_uc_addr(ha, netdev) {
3521 if (!rar_entries)
3522 break;
3523 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3524 vfn, IXGBE_RAH_AV);
3525 count++;
3526 }
3527 }
3528 /* write the addresses in reverse order to avoid write combining */
3529 for (; rar_entries > 0 ; rar_entries--)
3530 hw->mac.ops.clear_rar(hw, rar_entries);
3531
3532 return count;
3533}
3534
9a799d71 3535/**
2c5645cf 3536 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3537 * @netdev: network interface device structure
3538 *
2c5645cf
CL		 3539 * The set_rx_method entry point is called whenever the unicast/multicast
3540 * address list or the network interface flags are updated. This routine is
3541 * responsible for configuring the hardware for proper unicast, multicast and
3542 * promiscuous mode.
9a799d71 3543 **/
7f870475 3544void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3545{
3546 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3547 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3548 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3549 int count;
9a799d71
AK		 3550
3551 /* Check for Promiscuous and All Multicast modes */
3552
3553 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3554
f5dc442b
AD		 3555 /* set all bits that we expect to always be set */
3556 fctrl |= IXGBE_FCTRL_BAM;
3557 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3558 fctrl |= IXGBE_FCTRL_PMCF;
3559
2850062a
AD		 3560 /* clear the bits we are changing the status of */
3561 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3562
9a799d71 3563 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3564 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3565 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3566 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3567 /* don't hardware filter vlans in promisc mode */
3568 ixgbe_vlan_filter_disable(adapter);
9a799d71 3569 } else {
746b9f02
PM		 3570 if (netdev->flags & IFF_ALLMULTI) {
3571 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3572 vmolr |= IXGBE_VMOLR_MPE;
3573 } else {
3574 /*
3575 * Write addresses to the MTA, if the attempt fails
25985edc 3576 * then we should just turn on promiscuous mode so
2850062a
AD		 3577 * that we can at least receive multicast traffic
3578 */
3579 hw->mac.ops.update_mc_addr_list(hw, netdev);
3580 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3581 }
5f6c0181 3582 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3583 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3584 /*
3585 * Write addresses to available RAR registers, if there is not
3586 * sufficient space to store all the addresses then enable
25985edc 3587 * unicast promiscuous mode
2850062a
AD		 3588 */
3589 count = ixgbe_write_uc_addr_list(netdev);
3590 if (count < 0) {
3591 fctrl |= IXGBE_FCTRL_UPE;
3592 vmolr |= IXGBE_VMOLR_ROPE;
3593 }
9a799d71
AK		 3594 }
3595
2850062a 3596 if (adapter->num_vfs) {
1cdd1ec8 3597 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3598 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3599 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3600 IXGBE_VMOLR_ROPE);
3601 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3602 }
3603
3604 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3605
3606 if (netdev->features & NETIF_F_HW_VLAN_RX)
3607 ixgbe_vlan_strip_enable(adapter);
3608 else
3609 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3610}
3611
021230d4
AV		 3612static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3613{
3614 int q_idx;
3615 struct ixgbe_q_vector *q_vector;
3616 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3617
3618 /* legacy and MSI only use one vector */
3619 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3620 q_vectors = 1;
3621
3622 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3623 struct napi_struct *napi;
7a921c93 3624 q_vector = adapter->q_vector[q_idx];
f0848276 3625 napi = &q_vector->napi;
91281fd3
AD		 3626 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3627 if (!q_vector->rxr_count || !q_vector->txr_count) {
3628 if (q_vector->txr_count == 1)
3629 napi->poll = &ixgbe_clean_txonly;
3630 else if (q_vector->rxr_count == 1)
3631 napi->poll = &ixgbe_clean_rxonly;
3632 }
3633 }
f0848276
JB		 3634
3635 napi_enable(napi);
021230d4
AV		 3636 }
3637}
3638
3639static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3640{
3641 int q_idx;
3642 struct ixgbe_q_vector *q_vector;
3643 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3644
3645 /* legacy and MSI only use one vector */
3646 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3647 q_vectors = 1;
3648
3649 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3650 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3651 napi_disable(&q_vector->napi);
3652 }
3653}
3654
7a6b6f51 3655#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3656/*
3657 * ixgbe_configure_dcb - Configure DCB hardware
3658 * @adapter: ixgbe adapter struct
3659 *
3660 * This is called by the driver on open to configure the DCB hardware.
3661 * This is also called by the gennetlink interface when reconfiguring
3662 * the DCB state.
3663 */
3664static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3665{
3666 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3667 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3668
67ebd791
AD		 3669 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3670 if (hw->mac.type == ixgbe_mac_82598EB)
3671 netif_set_gso_max_size(adapter->netdev, 65536);
3672 return;
3673 }
3674
3675 if (hw->mac.type == ixgbe_mac_82598EB)
3676 netif_set_gso_max_size(adapter->netdev, 32768);
3677
2f90b865 3678
2f90b865 3679 /* Enable VLAN tag insert/strip */
f62bbb5e 3680 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3681
2f90b865 3682 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3683
3684 /* reconfigure the hardware */
6f70f6ac 3685 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3686#ifdef CONFIG_FCOE
3687 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3688 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3689#endif
3690 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3691 DCB_TX_CONFIG);
3692 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3693 DCB_RX_CONFIG);
3694 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3695 } else {
3696 struct net_device *dev = adapter->netdev;
3697
3698 if (adapter->ixgbe_ieee_ets)
3699 dev->dcbnl_ops->ieee_setets(dev,
3700 adapter->ixgbe_ieee_ets);
3701 if (adapter->ixgbe_ieee_pfc)
3702 dev->dcbnl_ops->ieee_setpfc(dev,
3703 adapter->ixgbe_ieee_pfc);
3704 }
8187cd48
JF		 3705
3706 /* Enable RSS Hash per TC */
3707 if (hw->mac.type != ixgbe_mac_82598EB) {
3708 int i;
3709 u32 reg = 0;
3710
3711 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3712 u8 msb = 0;
3713 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3714
3715 while (cnt >>= 1)
3716 msb++;
3717
3718 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3719 }
3720 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3721 }
2f90b865
AD		 3722}
3723
3724#endif
80605c65
JF		 3725
3726static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3727{
3728 int hdrm = 0;
3729 int num_tc = netdev_get_num_tc(adapter->netdev);
3730 struct ixgbe_hw *hw = &adapter->hw;
3731
3732 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3733 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3734 hdrm = 64 << adapter->fdir_pballoc;
3735
3736 hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3737}
3738
e4911d57
AD		 3739static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3740{
3741 struct ixgbe_hw *hw = &adapter->hw;
3742 struct hlist_node *node, *node2;
3743 struct ixgbe_fdir_filter *filter;
3744
3745 spin_lock(&adapter->fdir_perfect_lock);
3746
3747 if (!hlist_empty(&adapter->fdir_filter_list))
3748 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3749
3750 hlist_for_each_entry_safe(filter, node, node2,
3751 &adapter->fdir_filter_list, fdir_node) {
3752 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3753 &filter->filter,
3754 filter->sw_idx,
3755 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3756 IXGBE_FDIR_DROP_QUEUE :
3757 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3758 }
3759
3760 spin_unlock(&adapter->fdir_perfect_lock);
3761}
3762
9a799d71
AK		 3763static void ixgbe_configure(struct ixgbe_adapter *adapter)
3764{
3765 struct net_device *netdev = adapter->netdev;
c4cf55e5 3766 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3767 int i;
3768
80605c65 3769 ixgbe_configure_pb(adapter);
7a6b6f51 3770#ifdef CONFIG_IXGBE_DCB
67ebd791 3771 ixgbe_configure_dcb(adapter);
2f90b865 3772#endif
9a799d71 3773
f62bbb5e
JG		 3774 ixgbe_set_rx_mode(netdev);
3775 ixgbe_restore_vlan(adapter);
3776
eacd73f7
YZ		 3777#ifdef IXGBE_FCOE
3778 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3779 ixgbe_configure_fcoe(adapter);
3780
3781#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3782 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3783 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3784 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3785 adapter->atr_sample_rate;
c4cf55e5 3786 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
e4911d57
AD		 3787 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3788 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3789 adapter->fdir_pballoc);
3790 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3791 }
933d41f1 3792 ixgbe_configure_virtualization(adapter);
c4cf55e5 3793
9a799d71
AK		 3794 ixgbe_configure_tx(adapter);
3795 ixgbe_configure_rx(adapter);
9a799d71
AK		 3796}
3797
e8e26350
PW		 3798static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3799{
3800 switch (hw->phy.type) {
3801 case ixgbe_phy_sfp_avago:
3802 case ixgbe_phy_sfp_ftl:
3803 case ixgbe_phy_sfp_intel:
3804 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3805 case ixgbe_phy_sfp_passive_tyco:
3806 case ixgbe_phy_sfp_passive_unknown:
3807 case ixgbe_phy_sfp_active_unknown:
3808 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3809 return true;
3810 default:
3811 return false;
3812 }
3813}
3814
0ecc061d 3815/**
e8e26350
PW		 3816 * ixgbe_sfp_link_config - set up SFP+ link
3817 * @adapter: pointer to private adapter struct
3818 **/
3819static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3820{
7086400d
AD		 3821 /*
3822 * We are assuming the worst case scenerio here, and that
3823 * is that an SFP was inserted/removed after the reset
3824 * but before SFP detection was enabled. As such the best
3825 * solution is to just start searching as soon as we start
3826 */
3827 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3828 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3829
7086400d 3830 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3831}
3832
3833/**
3834 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3835 * @hw: pointer to private hardware struct
3836 *
3837 * Returns 0 on success, negative on failure
3838 **/
e8e26350 3839static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3840{
3841 u32 autoneg;
8620a103 3842 bool negotiation, link_up = false;
0ecc061d
PWJ		 3843 u32 ret = IXGBE_ERR_LINK_SETUP;
3844
3845 if (hw->mac.ops.check_link)
3846 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3847
3848 if (ret)
3849 goto link_cfg_out;
3850
0b0c2b31
ET		 3851 autoneg = hw->phy.autoneg_advertised;
3852 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3853 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3854 &negotiation);
0ecc061d
PWJ		 3855 if (ret)
3856 goto link_cfg_out;
3857
8620a103
MC		 3858 if (hw->mac.ops.setup_link)
3859 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3860link_cfg_out:
3861 return ret;
3862}
3863
a34bcfff 3864static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3865{
9a799d71 3866 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3867 u32 gpie = 0;
9a799d71 3868
9b471446 3869 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3870 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3871 IXGBE_GPIE_OCD;
3872 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3873 /*
3874 * use EIAM to auto-mask when MSI-X interrupt is asserted
3875 * this saves a register write for every interrupt
3876 */
3877 switch (hw->mac.type) {
3878 case ixgbe_mac_82598EB:
3879 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3880 break;
9b471446 3881 case ixgbe_mac_82599EB:
b93a2226
DS		 3882 case ixgbe_mac_X540:
3883 default:
9b471446
JB		 3884 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3885 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3886 break;
3887 }
3888 } else {
021230d4
AV		 3889 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3890 * specifically only auto mask tx and rx interrupts */
3891 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3892 }
9a799d71 3893
a34bcfff
AD		 3894 /* XXX: to interrupt immediately for EICS writes, enable this */
3895 /* gpie |= IXGBE_GPIE_EIMEN; */
3896
3897 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3898 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3899 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3900 }
3901
a34bcfff
AD		 3902 /* Enable fan failure interrupt */
3903 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3904 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3905
2698b208 3906 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3907 gpie |= IXGBE_SDP1_GPIEN;
3908 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3909 }
a34bcfff
AD		 3910
3911 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3912}
3913
3914static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3915{
3916 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3917 int err;
a34bcfff
AD		 3918 u32 ctrl_ext;
3919
3920 ixgbe_get_hw_control(adapter);
3921 ixgbe_setup_gpie(adapter);
e8e26350 3922
9a799d71
AK		 3923 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3924 ixgbe_configure_msix(adapter);
3925 else
3926 ixgbe_configure_msi_and_legacy(adapter);
3927
c6ecf39a
DS		 3928 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3929 if (hw->mac.ops.enable_tx_laser &&
3930 ((hw->phy.multispeed_fiber) ||
9f911707 3931 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3932 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3933 hw->mac.ops.enable_tx_laser(hw);
3934
9a799d71 3935 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3936 ixgbe_napi_enable_all(adapter);
3937
73c4b7cd
AD		 3938 if (ixgbe_is_sfp(hw)) {
3939 ixgbe_sfp_link_config(adapter);
3940 } else {
3941 err = ixgbe_non_sfp_link_config(hw);
3942 if (err)
3943 e_err(probe, "link_config FAILED %d\n", err);
3944 }
3945
021230d4
AV		 3946 /* clear any pending interrupts, may auto mask */
3947 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3948 ixgbe_irq_enable(adapter, true, true);
9a799d71 3949
bf069c97
DS		 3950 /*
3951 * If this adapter has a fan, check to see if we had a failure
3952 * before we enabled the interrupt.
3953 */
3954 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3955 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3956 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3957 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3958 }
3959
1da100bb 3960 /* enable transmits */
477de6ed 3961 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3962
9a799d71
AK		 3963 /* bring the link up in the watchdog, this could race with our first
3964 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3965 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3966 adapter->link_check_timeout = jiffies;
7086400d 3967 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3968
3969 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3970 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3971 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3972 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3973
9a799d71
AK		 3974 return 0;
3975}
3976
d4f80882
AV		 3977void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3978{
3979 WARN_ON(in_interrupt());
7086400d
AD		 3980 /* put off any impending NetWatchDogTimeout */
3981 adapter->netdev->trans_start = jiffies;
3982
d4f80882 3983 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3984 usleep_range(1000, 2000);
d4f80882 3985 ixgbe_down(adapter);
5809a1ae
GR		 3986 /*
3987 * If SR-IOV enabled then wait a bit before bringing the adapter
3988 * back up to give the VFs time to respond to the reset. The
3989 * two second wait is based upon the watchdog timer cycle in
3990 * the VF driver.
3991 */
3992 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3993 msleep(2000);
d4f80882
AV		 3994 ixgbe_up(adapter);
3995 clear_bit(__IXGBE_RESETTING, &adapter->state);
3996}
3997
9a799d71
AK		 3998int ixgbe_up(struct ixgbe_adapter *adapter)
3999{
4000 /* hardware has been reset, we need to reload some things */
4001 ixgbe_configure(adapter);
4002
4003 return ixgbe_up_complete(adapter);
4004}
4005
4006void ixgbe_reset(struct ixgbe_adapter *adapter)
4007{
c44ade9e 4008 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4009 int err;
4010
7086400d
AD		 4011 /* lock SFP init bit to prevent race conditions with the watchdog */
4012 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4013 usleep_range(1000, 2000);
4014
4015 /* clear all SFP and link config related flags while holding SFP_INIT */
4016 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4017 IXGBE_FLAG2_SFP_NEEDS_RESET);
4018 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4019
8ca783ab 4020 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4021 switch (err) {
4022 case 0:
4023 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4024 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4025 break;
4026 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4027 e_dev_err("master disable timed out\n");
da4dd0f7 4028 break;
794caeb2
PWJ		 4029 case IXGBE_ERR_EEPROM_VERSION:
4030 /* We are running on a pre-production device, log a warning */
849c4542
ET		 4031 e_dev_warn("This device is a pre-production adapter/LOM. "
4032 "Please be aware there may be issuesassociated with "
4033 "your hardware. If you are experiencing problems "
4034 "please contact your Intel or hardware "
4035 "representative who provided you with this "
4036 "hardware.\n");
794caeb2 4037 break;
da4dd0f7 4038 default:
849c4542 4039 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4040 }
9a799d71 4041
7086400d
AD		 4042 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4043
9a799d71 4044 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 4045 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4046 IXGBE_RAH_AV);
9a799d71
AK		 4047}
4048
9a799d71
AK		 4049/**
4050 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4051 * @rx_ring: ring to free buffers from
4052 **/
b6ec895e 4053static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4054{
b6ec895e 4055 struct device *dev = rx_ring->dev;
9a799d71 4056 unsigned long size;
b6ec895e 4057 u16 i;
9a799d71 4058
84418e3b
AD		 4059 /* ring already cleared, nothing to do */
4060 if (!rx_ring->rx_buffer_info)
4061 return;
9a799d71 4062
84418e3b 4063 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 4064 for (i = 0; i < rx_ring->count; i++) {
4065 struct ixgbe_rx_buffer *rx_buffer_info;
4066
4067 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4068 if (rx_buffer_info->dma) {
b6ec895e 4069 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 4070 rx_ring->rx_buf_len,
1b507730 4071 DMA_FROM_DEVICE);
9a799d71
AK		 4072 rx_buffer_info->dma = 0;
4073 }
4074 if (rx_buffer_info->skb) {
f8212f97 4075 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 4076 rx_buffer_info->skb = NULL;
f8212f97
AD		 4077 do {
4078 struct sk_buff *this = skb;
e8171aaa 4079 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 4080 dma_unmap_single(dev,
1b507730 4081 IXGBE_RSC_CB(this)->dma,
e8e9f696 4082 rx_ring->rx_buf_len,
1b507730 4083 DMA_FROM_DEVICE);
fd3686a8 4084 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 4085 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 4086 }
f8212f97
AD		 4087 skb = skb->prev;
4088 dev_kfree_skb(this);
4089 } while (skb);
9a799d71
AK		 4090 }
4091 if (!rx_buffer_info->page)
4092 continue;
4f57ca6e 4093 if (rx_buffer_info->page_dma) {
b6ec895e 4094 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 4095 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 4096 rx_buffer_info->page_dma = 0;
4097 }
9a799d71
AK		 4098 put_page(rx_buffer_info->page);
4099 rx_buffer_info->page = NULL;
762f4c57 4100 rx_buffer_info->page_offset = 0;
9a799d71
AK		 4101 }
4102
4103 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4104 memset(rx_ring->rx_buffer_info, 0, size);
4105
4106 /* Zero out the descriptor ring */
4107 memset(rx_ring->desc, 0, rx_ring->size);
4108
4109 rx_ring->next_to_clean = 0;
4110 rx_ring->next_to_use = 0;
9a799d71
AK		 4111}
4112
4113/**
4114 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4115 * @tx_ring: ring to be cleaned
4116 **/
b6ec895e 4117static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4118{
4119 struct ixgbe_tx_buffer *tx_buffer_info;
4120 unsigned long size;
b6ec895e 4121 u16 i;
9a799d71 4122
84418e3b
AD		 4123 /* ring already cleared, nothing to do */
4124 if (!tx_ring->tx_buffer_info)
4125 return;
9a799d71 4126
84418e3b 4127 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4128 for (i = 0; i < tx_ring->count; i++) {
4129 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4130 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4131 }
4132
4133 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4134 memset(tx_ring->tx_buffer_info, 0, size);
4135
4136 /* Zero out the descriptor ring */
4137 memset(tx_ring->desc, 0, tx_ring->size);
4138
4139 tx_ring->next_to_use = 0;
4140 tx_ring->next_to_clean = 0;
9a799d71
AK		 4141}
4142
4143/**
021230d4 4144 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4145 * @adapter: board private structure
4146 **/
021230d4 4147static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4148{
4149 int i;
4150
021230d4 4151 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4152 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4153}
4154
4155/**
021230d4 4156 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4157 * @adapter: board private structure
4158 **/
021230d4 4159static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4160{
4161 int i;
4162
021230d4 4163 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4164 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4165}
4166
e4911d57
AD		 4167static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4168{
4169 struct hlist_node *node, *node2;
4170 struct ixgbe_fdir_filter *filter;
4171
4172 spin_lock(&adapter->fdir_perfect_lock);
4173
4174 hlist_for_each_entry_safe(filter, node, node2,
4175 &adapter->fdir_filter_list, fdir_node) {
4176 hlist_del(&filter->fdir_node);
4177 kfree(filter);
4178 }
4179 adapter->fdir_filter_count = 0;
4180
4181 spin_unlock(&adapter->fdir_perfect_lock);
4182}
4183
9a799d71
AK		 4184void ixgbe_down(struct ixgbe_adapter *adapter)
4185{
4186 struct net_device *netdev = adapter->netdev;
7f821875 4187 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4188 u32 rxctrl;
bf29ee6c 4189 int i;
b25ebfd2 4190 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 4191
4192 /* signal that we are down to the interrupt handler */
4193 set_bit(__IXGBE_DOWN, &adapter->state);
4194
4195 /* disable receives */
7f821875
JB		 4196 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4197 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4198
2d39d576
YZ		 4199 /* disable all enabled rx queues */
4200 for (i = 0; i < adapter->num_rx_queues; i++)
4201 /* this call also flushes the previous write */
4202 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4203
032b4325 4204 usleep_range(10000, 20000);
9a799d71 4205
7f821875
JB		 4206 netif_tx_stop_all_queues(netdev);
4207
7086400d 4208 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4209 netif_carrier_off(netdev);
4210 netif_tx_disable(netdev);
4211
4212 ixgbe_irq_disable(adapter);
4213
4214 ixgbe_napi_disable_all(adapter);
4215
d034acf1
AD		 4216 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4217 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4218 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4219
4220 del_timer_sync(&adapter->service_timer);
4221
34cecbbf
AD		 4222 /* disable receive for all VFs and wait one second */
4223 if (adapter->num_vfs) {
4224 /* ping all the active vfs to let them know we are going down */
4225 ixgbe_ping_all_vfs(adapter);
4226
4227 /* Disable all VFTE/VFRE TX/RX */
4228 ixgbe_disable_tx_rx(adapter);
4229
4230 /* Mark all the VFs as inactive */
4231 for (i = 0 ; i < adapter->num_vfs; i++)
4232 adapter->vfinfo[i].clear_to_send = 0;
4233 }
4234
b25ebfd2
PW		 4235 /* Cleanup the affinity_hint CPU mask memory and callback */
4236 for (i = 0; i < num_q_vectors; i++) {
4237 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4238 /* clear the affinity_mask in the IRQ descriptor */
4239 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4240 /* release the CPU mask memory */
4241 free_cpumask_var(q_vector->affinity_mask);
4242 }
4243
7f821875
JB		 4244 /* disable transmits in the hardware now that interrupts are off */
4245 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4246 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4247 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4248 }
34cecbbf
AD		 4249
4250 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4251 switch (hw->mac.type) {
4252 case ixgbe_mac_82599EB:
b93a2226 4253 case ixgbe_mac_X540:
88512539 4254 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4255 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4256 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4257 break;
4258 default:
4259 break;
4260 }
7f821875 4261
6f4a0e45
PL		 4262 if (!pci_channel_offline(adapter->pdev))
4263 ixgbe_reset(adapter);
c6ecf39a
DS		 4264
4265 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4266 if (hw->mac.ops.disable_tx_laser &&
4267 ((hw->phy.multispeed_fiber) ||
9f911707 4268 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4269 (hw->mac.type == ixgbe_mac_82599EB))))
4270 hw->mac.ops.disable_tx_laser(hw);
4271
9a799d71
AK		 4272 ixgbe_clean_all_tx_rings(adapter);
4273 ixgbe_clean_all_rx_rings(adapter);
4274
5dd2d332 4275#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4276 /* since we reset the hardware DCA settings were cleared */
e35ec126 4277 ixgbe_setup_dca(adapter);
96b0e0f6 4278#endif
9a799d71
AK		 4279}
4280
9a799d71 4281/**
021230d4
AV		 4282 * ixgbe_poll - NAPI Rx polling callback
4283 * @napi: structure for representing this polling device
4284 * @budget: how many packets driver is allowed to clean
4285 *
4286 * This function is used for legacy and MSI, NAPI mode
9a799d71 4287 **/
021230d4 4288static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4289{
9a1a69ad 4290 struct ixgbe_q_vector *q_vector =
e8e9f696 4291 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4292 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 4293 int tx_clean_complete, work_done = 0;
9a799d71 4294
5dd2d332 4295#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4296 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4297 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4298#endif
4299
4a0b9ca0
PW		 4300 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4301 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 4302
9a1a69ad 4303 if (!tx_clean_complete)
d2c7ddd6
DM		 4304 work_done = budget;
4305
53e52c72
DM		 4306 /* If budget not fully consumed, exit the polling mode */
4307 if (work_done < budget) {
288379f0 4308 napi_complete(napi);
f7554a2b 4309 if (adapter->rx_itr_setting & 1)
f494e8fa 4310 ixgbe_set_itr(adapter);
d4f80882 4311 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 4312 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 4313 }
9a799d71
AK		 4314 return work_done;
4315}
4316
4317/**
4318 * ixgbe_tx_timeout - Respond to a Tx Hang
4319 * @netdev: network interface device structure
4320 **/
4321static void ixgbe_tx_timeout(struct net_device *netdev)
4322{
4323 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4324
4325 /* Do the reset outside of interrupt context */
c83c6cbd 4326 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4327}
4328
4df10466
JB		 4329/**
4330 * ixgbe_set_rss_queues: Allocate queues for RSS
4331 * @adapter: board private structure to initialize
4332 *
4333 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4334 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4335 *
4336 **/
bc97114d
PWJ		 4337static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4338{
4339 bool ret = false;
0cefafad 4340 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4341
4342 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4343 f->mask = 0xF;
4344 adapter->num_rx_queues = f->indices;
4345 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4346 ret = true;
4347 } else {
bc97114d 4348 ret = false;
b9804972
JB		 4349 }
4350
bc97114d
PWJ		 4351 return ret;
4352}
4353
c4cf55e5
PWJ		 4354/**
4355 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4356 * @adapter: board private structure to initialize
4357 *
4358 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4359 * to the original CPU that initiated the Tx session. This runs in addition
4360 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4361 * Rx load across CPUs using RSS.
4362 *
4363 **/
e8e9f696 4364static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4365{
4366 bool ret = false;
4367 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4368
4369 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4370 f_fdir->mask = 0;
4371
4372 /* Flow Director must have RSS enabled */
03ecf91a
AD		 4373 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4374 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4375 adapter->num_tx_queues = f_fdir->indices;
4376 adapter->num_rx_queues = f_fdir->indices;
4377 ret = true;
4378 } else {
4379 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4380 }
4381 return ret;
4382}
4383
0331a832
YZ		 4384#ifdef IXGBE_FCOE
4385/**
4386 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4387 * @adapter: board private structure to initialize
4388 *
4389 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4390 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4391 * rx queues out of the max number of rx queues, instead, it is used as the
4392 * index of the first rx queue used by FCoE.
4393 *
4394 **/
4395static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4396{
0331a832
YZ		 4397 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4398
e5b64635
JF		 4399 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4400 return false;
4401
e901acd6 4402 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4403
e901acd6
JF		 4404 adapter->num_rx_queues = 1;
4405 adapter->num_tx_queues = 1;
e5b64635 4406
e901acd6
JF		 4407 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4408 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4409 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4410 ixgbe_set_fdir_queues(adapter);
4411 else
4412 ixgbe_set_rss_queues(adapter);
e5b64635 4413 }
03ecf91a 4414
e901acd6
JF		 4415 /* adding FCoE rx rings to the end */
4416 f->mask = adapter->num_rx_queues;
4417 adapter->num_rx_queues += f->indices;
4418 adapter->num_tx_queues += f->indices;
0331a832 4419
e5b64635
JF		 4420 return true;
4421}
4422#endif /* IXGBE_FCOE */
4423
e901acd6
JF		 4424/* Artificial max queue cap per traffic class in DCB mode */
4425#define DCB_QUEUE_CAP 8
4426
e5b64635
JF		 4427#ifdef CONFIG_IXGBE_DCB
4428static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4429{
e901acd6
JF		 4430 int per_tc_q, q, i, offset = 0;
4431 struct net_device *dev = adapter->netdev;
4432 int tcs = netdev_get_num_tc(dev);
e5b64635 4433
e901acd6
JF		 4434 if (!tcs)
4435 return false;
e5b64635 4436
e901acd6
JF		 4437 /* Map queue offset and counts onto allocated tx queues */
4438 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4439 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4440
8b1c0b24 4441 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4442 netdev_set_prio_tc_map(dev, i, i);
4443 netdev_set_tc_queue(dev, i, q, offset);
4444 offset += q;
0331a832
YZ		 4445 }
4446
e901acd6
JF		 4447 adapter->num_tx_queues = q * tcs;
4448 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4449
4450#ifdef IXGBE_FCOE
e901acd6
JF		 4451 /* FCoE enabled queues require special configuration indexed
4452 * by feature specific indices and mask. Here we map FCoE
4453 * indices onto the DCB queue pairs allowing FCoE to own
4454 * configuration later.
e5b64635 4455 */
e901acd6
JF		 4456 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4457 int tc;
4458 struct ixgbe_ring_feature *f =
4459 &adapter->ring_feature[RING_F_FCOE];
4460
4461 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4462 f->indices = dev->tc_to_txq[tc].count;
4463 f->mask = dev->tc_to_txq[tc].offset;
4464 }
e5b64635
JF		 4465#endif
4466
e901acd6 4467 return true;
0331a832 4468}
e5b64635 4469#endif
0331a832 4470
1cdd1ec8
GR		 4471/**
4472 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4473 * @adapter: board private structure to initialize
4474 *
4475 * IOV doesn't actually use anything, so just NAK the
4476 * request for now and let the other queue routines
4477 * figure out what to do.
4478 */
4479static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4480{
4481 return false;
4482}
4483
4df10466 4484/*
25985edc 4485 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4486 * @adapter: board private structure to initialize
4487 *
4488 * This is the top level queue allocation routine. The order here is very
4489 * important, starting with the "most" number of features turned on at once,
4490 * and ending with the smallest set of features. This way large combinations
4491 * can be allocated if they're turned on, and smaller combinations are the
4492 * fallthrough conditions.
4493 *
4494 **/
847f53ff 4495static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4496{
1cdd1ec8
GR		 4497 /* Start with base case */
4498 adapter->num_rx_queues = 1;
4499 adapter->num_tx_queues = 1;
4500 adapter->num_rx_pools = adapter->num_rx_queues;
4501 adapter->num_rx_queues_per_pool = 1;
4502
4503 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4504 goto done;
1cdd1ec8 4505
bc97114d
PWJ		 4506#ifdef CONFIG_IXGBE_DCB
4507 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4508 goto done;
bc97114d
PWJ		 4509
4510#endif
e5b64635
JF		 4511#ifdef IXGBE_FCOE
4512 if (ixgbe_set_fcoe_queues(adapter))
4513 goto done;
4514
4515#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4516 if (ixgbe_set_fdir_queues(adapter))
4517 goto done;
4518
bc97114d 4519 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4520 goto done;
4521
4522 /* fallback to base case */
4523 adapter->num_rx_queues = 1;
4524 adapter->num_tx_queues = 1;
4525
4526done:
847f53ff 4527 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4528 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4529 return netif_set_real_num_rx_queues(adapter->netdev,
4530 adapter->num_rx_queues);
b9804972
JB		 4531}
4532
021230d4 4533static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4534 int vectors)
021230d4
AV		 4535{
4536 int err, vector_threshold;
4537
4538 /* We'll want at least 3 (vector_threshold):
4539 * 1) TxQ[0] Cleanup
4540 * 2) RxQ[0] Cleanup
4541 * 3) Other (Link Status Change, etc.)
4542 * 4) TCP Timer (optional)
4543 */
4544 vector_threshold = MIN_MSIX_COUNT;
4545
4546 /* The more we get, the more we will assign to Tx/Rx Cleanup
4547 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4548 * Right now, we simply care about how many we'll get; we'll
4549 * set them up later while requesting irq's.
4550 */
4551 while (vectors >= vector_threshold) {
4552 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4553 vectors);
021230d4
AV		 4554 if (!err) /* Success in acquiring all requested vectors. */
4555 break;
4556 else if (err < 0)
4557 vectors = 0; /* Nasty failure, quit now */
4558 else /* err == number of vectors we should try again with */
4559 vectors = err;
4560 }
4561
4562 if (vectors < vector_threshold) {
4563 /* Can't allocate enough MSI-X interrupts? Oh well.
4564 * This just means we'll go with either a single MSI
4565 * vector or fall back to legacy interrupts.
4566 */
849c4542
ET		 4567 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4568 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4569 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4570 kfree(adapter->msix_entries);
4571 adapter->msix_entries = NULL;
021230d4
AV		 4572 } else {
4573 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4574 /*
4575 * Adjust for only the vectors we'll use, which is minimum
4576 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4577 * vectors we were allocated.
4578 */
4579 adapter->num_msix_vectors = min(vectors,
e8e9f696 4580 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4581 }
4582}
4583
021230d4 4584/**
bc97114d 4585 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4586 * @adapter: board private structure to initialize
4587 *
bc97114d
PWJ		 4588 * Cache the descriptor ring offsets for RSS to the assigned rings.
4589 *
021230d4 4590 **/
bc97114d 4591static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4592{
bc97114d 4593 int i;
bc97114d 4594
9d6b758f
AD		 4595 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4596 return false;
bc97114d 4597
9d6b758f
AD		 4598 for (i = 0; i < adapter->num_rx_queues; i++)
4599 adapter->rx_ring[i]->reg_idx = i;
4600 for (i = 0; i < adapter->num_tx_queues; i++)
4601 adapter->tx_ring[i]->reg_idx = i;
4602
4603 return true;
bc97114d
PWJ		 4604}
4605
4606#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4607
4608/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4609static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4610 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4611{
4612 struct net_device *dev = adapter->netdev;
4613 struct ixgbe_hw *hw = &adapter->hw;
4614 u8 num_tcs = netdev_get_num_tc(dev);
4615
4616 *tx = 0;
4617 *rx = 0;
4618
4619 switch (hw->mac.type) {
4620 case ixgbe_mac_82598EB:
aba70d5e
JF		 4621 *tx = tc << 2;
4622 *rx = tc << 3;
e5b64635
JF		 4623 break;
4624 case ixgbe_mac_82599EB:
4625 case ixgbe_mac_X540:
4626 if (num_tcs == 8) {
4627 if (tc < 3) {
4628 *tx = tc << 5;
4629 *rx = tc << 4;
4630 } else if (tc < 5) {
4631 *tx = ((tc + 2) << 4);
4632 *rx = tc << 4;
4633 } else if (tc < num_tcs) {
4634 *tx = ((tc + 8) << 3);
4635 *rx = tc << 4;
4636 }
4637 } else if (num_tcs == 4) {
4638 *rx = tc << 5;
4639 switch (tc) {
4640 case 0:
4641 *tx = 0;
4642 break;
4643 case 1:
4644 *tx = 64;
4645 break;
4646 case 2:
4647 *tx = 96;
4648 break;
4649 case 3:
4650 *tx = 112;
4651 break;
4652 default:
4653 break;
4654 }
4655 }
4656 break;
4657 default:
4658 break;
4659 }
4660}
4661
bc97114d
PWJ		 4662/**
4663 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4664 * @adapter: board private structure to initialize
4665 *
4666 * Cache the descriptor ring offsets for DCB to the assigned rings.
4667 *
4668 **/
4669static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4670{
e5b64635
JF		 4671 struct net_device *dev = adapter->netdev;
4672 int i, j, k;
4673 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4674
8b1c0b24 4675 if (!num_tcs)
bd508178 4676 return false;
f92ef202 4677
e5b64635
JF		 4678 for (i = 0, k = 0; i < num_tcs; i++) {
4679 unsigned int tx_s, rx_s;
4680 u16 count = dev->tc_to_txq[i].count;
4681
4682 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4683 for (j = 0; j < count; j++, k++) {
4684 adapter->tx_ring[k]->reg_idx = tx_s + j;
4685 adapter->rx_ring[k]->reg_idx = rx_s + j;
4686 adapter->tx_ring[k]->dcb_tc = i;
4687 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4688 }
021230d4 4689 }
e5b64635
JF		 4690
4691 return true;
bc97114d
PWJ		 4692}
4693#endif
4694
c4cf55e5
PWJ		 4695/**
4696 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4697 * @adapter: board private structure to initialize
4698 *
4699 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4700 *
4701 **/
e8e9f696 4702static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4703{
4704 int i;
4705 bool ret = false;
4706
03ecf91a
AD		 4707 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4708 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4709 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4710 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4711 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4712 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4713 ret = true;
4714 }
4715
4716 return ret;
4717}
4718
0331a832
YZ		 4719#ifdef IXGBE_FCOE
4720/**
4721 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4722 * @adapter: board private structure to initialize
4723 *
4724 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4725 *
4726 */
4727static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4728{
0331a832 4729 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4730 int i;
4731 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4732
4733 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4734 return false;
0331a832 4735
bf29ee6c 4736 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4737 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4738 ixgbe_cache_ring_fdir(adapter);
4739 else
4740 ixgbe_cache_ring_rss(adapter);
8faa2a78 4741
bf29ee6c
AD		 4742 fcoe_rx_i = f->mask;
4743 fcoe_tx_i = f->mask;
0331a832 4744 }
bf29ee6c
AD		 4745 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4746 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4747 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4748 }
4749 return true;
0331a832
YZ		 4750}
4751
4752#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4753/**
4754 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4755 * @adapter: board private structure to initialize
4756 *
4757 * SR-IOV doesn't use any descriptor rings but changes the default if
4758 * no other mapping is used.
4759 *
4760 */
4761static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4762{
4a0b9ca0
PW		 4763 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4764 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4765 if (adapter->num_vfs)
4766 return true;
4767 else
4768 return false;
4769}
4770
bc97114d
PWJ		 4771/**
4772 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4773 * @adapter: board private structure to initialize
4774 *
4775 * Once we know the feature-set enabled for the device, we'll cache
4776 * the register offset the descriptor ring is assigned to.
4777 *
4778 * Note, the order the various feature calls is important. It must start with
4779 * the "most" features enabled at the same time, then trickle down to the
4780 * least amount of features turned on at once.
4781 **/
4782static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4783{
4784 /* start with default case */
4a0b9ca0
PW		 4785 adapter->rx_ring[0]->reg_idx = 0;
4786 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4787
1cdd1ec8
GR		 4788 if (ixgbe_cache_ring_sriov(adapter))
4789 return;
4790
e5b64635
JF		 4791#ifdef CONFIG_IXGBE_DCB
4792 if (ixgbe_cache_ring_dcb(adapter))
4793 return;
4794#endif
4795
0331a832
YZ		 4796#ifdef IXGBE_FCOE
4797 if (ixgbe_cache_ring_fcoe(adapter))
4798 return;
0331a832 4799#endif /* IXGBE_FCOE */
bc97114d 4800
c4cf55e5
PWJ		 4801 if (ixgbe_cache_ring_fdir(adapter))
4802 return;
4803
bc97114d
PWJ		 4804 if (ixgbe_cache_ring_rss(adapter))
4805 return;
021230d4
AV		 4806}
4807
9a799d71
AK		 4808/**
4809 * ixgbe_alloc_queues - Allocate memory for all rings
4810 * @adapter: board private structure to initialize
4811 *
4812 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4813 * number of queues at compile-time. The polling_netdev array is
4814 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4815 **/
2f90b865 4816static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4817{
e2ddeba9 4818 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4819
e2ddeba9
ED		 4820 if (nid < 0 || !node_online(nid))
4821 nid = first_online_node;
4822
4823 for (; tx < adapter->num_tx_queues; tx++) {
4824 struct ixgbe_ring *ring;
4825
4826 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4827 if (!ring)
e2ddeba9 4828 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4829 if (!ring)
e2ddeba9 4830 goto err_allocation;
4a0b9ca0 4831 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4832 ring->queue_index = tx;
4833 ring->numa_node = nid;
b6ec895e 4834 ring->dev = &adapter->pdev->dev;
fc77dc3c 4835 ring->netdev = adapter->netdev;
4a0b9ca0 4836
e2ddeba9 4837 adapter->tx_ring[tx] = ring;
021230d4 4838 }
b9804972 4839
e2ddeba9
ED		 4840 for (; rx < adapter->num_rx_queues; rx++) {
4841 struct ixgbe_ring *ring;
4a0b9ca0 4842
e2ddeba9 4843 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4844 if (!ring)
e2ddeba9 4845 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4846 if (!ring)
e2ddeba9
ED		 4847 goto err_allocation;
4848 ring->count = adapter->rx_ring_count;
4849 ring->queue_index = rx;
4850 ring->numa_node = nid;
b6ec895e 4851 ring->dev = &adapter->pdev->dev;
fc77dc3c 4852 ring->netdev = adapter->netdev;
4a0b9ca0 4853
e2ddeba9 4854 adapter->rx_ring[rx] = ring;
021230d4
AV		 4855 }
4856
4857 ixgbe_cache_ring_register(adapter);
4858
4859 return 0;
4860
e2ddeba9
ED		 4861err_allocation:
4862 while (tx)
4863 kfree(adapter->tx_ring[--tx]);
4864
4865 while (rx)
4866 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4867 return -ENOMEM;
4868}
4869
4870/**
4871 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4872 * @adapter: board private structure to initialize
4873 *
4874 * Attempt to configure the interrupts using the best available
4875 * capabilities of the hardware and the kernel.
4876 **/
feea6a57 4877static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4878{
8be0e467 4879 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4880 int err = 0;
4881 int vector, v_budget;
4882
4883 /*
4884 * It's easy to be greedy for MSI-X vectors, but it really
4885 * doesn't do us much good if we have a lot more vectors
4886 * than CPU's. So let's be conservative and only ask for
342bde1b 4887 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4888 */
4889 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4890 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4891
4892 /*
4893 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4894 * hw.mac->max_msix_vectors vectors. With features
4895 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4896 * descriptor queues supported by our device. Thus, we cap it off in
4897 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4898 */
8be0e467 4899 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4900
4901 /* A failure in MSI-X entry allocation isn't fatal, but it does
4902 * mean we disable MSI-X capabilities of the adapter. */
4903 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4904 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4905 if (adapter->msix_entries) {
4906 for (vector = 0; vector < v_budget; vector++)
4907 adapter->msix_entries[vector].entry = vector;
021230d4 4908
7a921c93 4909 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4910
7a921c93
AD		 4911 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4912 goto out;
4913 }
26d27844 4914
7a921c93
AD		 4915 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4916 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4917 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4918 e_err(probe,
03ecf91a 4919 "ATR is not supported while multiple "
45b9f509
AD		 4920 "queues are disabled. Disabling Flow Director\n");
4921 }
c4cf55e5 4922 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4923 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4924 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4925 ixgbe_disable_sriov(adapter);
4926
847f53ff
BH		 4927 err = ixgbe_set_num_queues(adapter);
4928 if (err)
4929 return err;
021230d4 4930
021230d4
AV		 4931 err = pci_enable_msi(adapter->pdev);
4932 if (!err) {
4933 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4934 } else {
849c4542
ET		 4935 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4936 "Unable to allocate MSI interrupt, "
4937 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4938 /* reset err */
4939 err = 0;
4940 }
4941
4942out:
021230d4
AV		 4943 return err;
4944}
4945
7a921c93
AD		 4946/**
4947 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4948 * @adapter: board private structure to initialize
4949 *
4950 * We allocate one q_vector per queue interrupt. If allocation fails we
4951 * return -ENOMEM.
4952 **/
4953static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4954{
4955 int q_idx, num_q_vectors;
4956 struct ixgbe_q_vector *q_vector;
7a921c93
AD		 4957 int (*poll)(struct napi_struct *, int);
4958
4959 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4960 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4961 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4962 } else {
4963 num_q_vectors = 1;
7a921c93
AD		 4964 poll = &ixgbe_poll;
4965 }
4966
4967 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4968 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4969 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4970 if (!q_vector)
4971 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4972 GFP_KERNEL);
7a921c93
AD		 4973 if (!q_vector)
4974 goto err_out;
4975 q_vector->adapter = adapter;
f7554a2b
NS		 4976 if (q_vector->txr_count && !q_vector->rxr_count)
4977 q_vector->eitr = adapter->tx_eitr_param;
4978 else
4979 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4980 q_vector->v_idx = q_idx;
91281fd3 4981 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4982 adapter->q_vector[q_idx] = q_vector;
4983 }
4984
4985 return 0;
4986
4987err_out:
4988 while (q_idx) {
4989 q_idx--;
4990 q_vector = adapter->q_vector[q_idx];
4991 netif_napi_del(&q_vector->napi);
4992 kfree(q_vector);
4993 adapter->q_vector[q_idx] = NULL;
4994 }
4995 return -ENOMEM;
4996}
4997
4998/**
4999 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5000 * @adapter: board private structure to initialize
5001 *
5002 * This function frees the memory allocated to the q_vectors. In addition if
5003 * NAPI is enabled it will delete any references to the NAPI struct prior
5004 * to freeing the q_vector.
5005 **/
5006static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5007{
5008 int q_idx, num_q_vectors;
7a921c93 5009
91281fd3 5010 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 5011 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 5012 else
7a921c93 5013 num_q_vectors = 1;
7a921c93
AD		 5014
5015 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5016 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 5017 adapter->q_vector[q_idx] = NULL;
91281fd3 5018 netif_napi_del(&q_vector->napi);
7a921c93
AD		 5019 kfree(q_vector);
5020 }
5021}
5022
7b25cdba 5023static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 5024{
5025 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5026 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5027 pci_disable_msix(adapter->pdev);
5028 kfree(adapter->msix_entries);
5029 adapter->msix_entries = NULL;
5030 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5031 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5032 pci_disable_msi(adapter->pdev);
5033 }
021230d4
AV		 5034}
5035
5036/**
5037 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5038 * @adapter: board private structure to initialize
5039 *
5040 * We determine which interrupt scheme to use based on...
5041 * - Kernel support (MSI, MSI-X)
5042 * - which can be user-defined (via MODULE_PARAM)
5043 * - Hardware queue count (num_*_queues)
5044 * - defined by miscellaneous hardware support/features (RSS, etc.)
5045 **/
2f90b865 5046int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 5047{
5048 int err;
5049
5050 /* Number of supported queues */
847f53ff
BH		 5051 err = ixgbe_set_num_queues(adapter);
5052 if (err)
5053 return err;
021230d4 5054
021230d4
AV		 5055 err = ixgbe_set_interrupt_capability(adapter);
5056 if (err) {
849c4542 5057 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 5058 goto err_set_interrupt;
9a799d71
AK		 5059 }
5060
7a921c93
AD		 5061 err = ixgbe_alloc_q_vectors(adapter);
5062 if (err) {
849c4542 5063 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 5064 goto err_alloc_q_vectors;
5065 }
5066
5067 err = ixgbe_alloc_queues(adapter);
5068 if (err) {
849c4542 5069 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 5070 goto err_alloc_queues;
5071 }
5072
849c4542 5073 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 5074 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5075 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 5076
5077 set_bit(__IXGBE_DOWN, &adapter->state);
5078
9a799d71 5079 return 0;
021230d4 5080
7a921c93
AD		 5081err_alloc_queues:
5082 ixgbe_free_q_vectors(adapter);
5083err_alloc_q_vectors:
5084 ixgbe_reset_interrupt_capability(adapter);
021230d4 5085err_set_interrupt:
7a921c93
AD		 5086 return err;
5087}
5088
5089/**
5090 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5091 * @adapter: board private structure to clear interrupt scheme on
5092 *
5093 * We go through and clear interrupt specific resources and reset the structure
5094 * to pre-load conditions
5095 **/
5096void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5097{
4a0b9ca0
PW		 5098 int i;
5099
5100 for (i = 0; i < adapter->num_tx_queues; i++) {
5101 kfree(adapter->tx_ring[i]);
5102 adapter->tx_ring[i] = NULL;
5103 }
5104 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 5105 struct ixgbe_ring *ring = adapter->rx_ring[i];
5106
5107 /* ixgbe_get_stats64() might access this ring, we must wait
5108 * a grace period before freeing it.
5109 */
bcec8b65 5110 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 5111 adapter->rx_ring[i] = NULL;
5112 }
7a921c93 5113
b8eb3a10
DS		 5114 adapter->num_tx_queues = 0;
5115 adapter->num_rx_queues = 0;
5116
7a921c93
AD		 5117 ixgbe_free_q_vectors(adapter);
5118 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5119}
5120
5121/**
5122 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5123 * @adapter: board private structure to initialize
5124 *
5125 * ixgbe_sw_init initializes the Adapter private data structure.
5126 * Fields are initialized based on PCI device information and
5127 * OS network device settings (MTU size).
5128 **/
5129static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5130{
5131 struct ixgbe_hw *hw = &adapter->hw;
5132 struct pci_dev *pdev = adapter->pdev;
9a713e7c 5133 struct net_device *dev = adapter->netdev;
021230d4 5134 unsigned int rss;
7a6b6f51 5135#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5136 int j;
5137 struct tc_configuration *tc;
5138#endif
16b61beb 5139 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 5140
c44ade9e
JB		 5141 /* PCI config space info */
5142
5143 hw->vendor_id = pdev->vendor;
5144 hw->device_id = pdev->device;
5145 hw->revision_id = pdev->revision;
5146 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5147 hw->subsystem_device_id = pdev->subsystem_device;
5148
021230d4
AV		 5149 /* Set capability flags */
5150 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5151 adapter->ring_feature[RING_F_RSS].indices = rss;
5152 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 5153 switch (hw->mac.type) {
5154 case ixgbe_mac_82598EB:
bf069c97
DS		 5155 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5156 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5157 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178
AD		 5158 break;
5159 case ixgbe_mac_82599EB:
b93a2226 5160 case ixgbe_mac_X540:
e8e26350 5161 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5162 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5163 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5164 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5165 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5166 /* n-tuple support exists, always init our spinlock */
5167 spin_lock_init(&adapter->fdir_perfect_lock);
5168 /* Flow Director hash filters enabled */
5169 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5170 adapter->atr_sample_rate = 20;
c4cf55e5 5171 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5172 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 5173 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 5174#ifdef IXGBE_FCOE
0d551589
YZ		 5175 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5176 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5177 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5178#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 5179 /* Default traffic class to use for FCoE */
5180 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 5181 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5182#endif
eacd73f7 5183#endif /* IXGBE_FCOE */
bd508178
AD		 5184 break;
5185 default:
5186 break;
f8212f97 5187 }
2f90b865 5188
7a6b6f51 5189#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5190 /* Configure DCB traffic classes */
5191 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5192 tc = &adapter->dcb_cfg.tc_config[j];
5193 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5194 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5195 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5196 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5197 tc->dcb_pfc = pfc_disabled;
5198 }
5199 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5200 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5201 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5202 adapter->dcb_set_bitmap = 0x00;
3032309b 5203 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5204 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5205 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5206
5207#endif
9a799d71
AK		 5208
5209 /* default flow control settings */
cd7664f6 5210 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5211 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5212#ifdef CONFIG_DCB
5213 adapter->last_lfc_mode = hw->fc.current_mode;
5214#endif
16b61beb
JF		 5215 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5216 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 5217 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5218 hw->fc.send_xon = true;
71fd570b 5219 hw->fc.disable_fc_autoneg = false;
9a799d71 5220
30efa5a3 5221 /* enable itr by default in dynamic mode */
f7554a2b
NS		 5222 adapter->rx_itr_setting = 1;
5223 adapter->rx_eitr_param = 20000;
5224 adapter->tx_itr_setting = 1;
5225 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 5226
5227 /* set defaults for eitr in MegaBytes */
5228 adapter->eitr_low = 10;
5229 adapter->eitr_high = 20;
5230
5231 /* set default ring sizes */
5232 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5233 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5234
9a799d71 5235 /* initialize eeprom parameters */
c44ade9e 5236 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5237 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5238 return -EIO;
5239 }
5240
021230d4 5241 /* enable rx csum by default */
9a799d71
AK		 5242 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5243
1a6c14a2
JB		 5244 /* get assigned NUMA node */
5245 adapter->node = dev_to_node(&pdev->dev);
5246
9a799d71
AK		 5247 set_bit(__IXGBE_DOWN, &adapter->state);
5248
5249 return 0;
5250}
5251
5252/**
5253 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5254 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5255 *
5256 * Return 0 on success, negative on failure
5257 **/
b6ec895e 5258int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5259{
b6ec895e 5260 struct device *dev = tx_ring->dev;
9a799d71
AK		 5261 int size;
5262
3a581073 5263 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5264 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5265 if (!tx_ring->tx_buffer_info)
89bf67f1 5266 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5267 if (!tx_ring->tx_buffer_info)
5268 goto err;
9a799d71
AK		 5269
5270 /* round up to nearest 4K */
12207e49 5271 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5272 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5273
b6ec895e 5274 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5275 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5276 if (!tx_ring->desc)
5277 goto err;
9a799d71 5278
3a581073
JB		 5279 tx_ring->next_to_use = 0;
5280 tx_ring->next_to_clean = 0;
5281 tx_ring->work_limit = tx_ring->count;
9a799d71 5282 return 0;
e01c31a5
JB		 5283
5284err:
5285 vfree(tx_ring->tx_buffer_info);
5286 tx_ring->tx_buffer_info = NULL;
b6ec895e 5287 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5288 return -ENOMEM;
9a799d71
AK		 5289}
5290
69888674
AD		 5291/**
5292 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5293 * @adapter: board private structure
5294 *
5295 * If this function returns with an error, then it's possible one or
5296 * more of the rings is populated (while the rest are not). It is the
5297 * callers duty to clean those orphaned rings.
5298 *
5299 * Return 0 on success, negative on failure
5300 **/
5301static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5302{
5303 int i, err = 0;
5304
5305 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5306 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5307 if (!err)
5308 continue;
396e799c 5309 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5310 break;
5311 }
5312
5313 return err;
5314}
5315
9a799d71
AK		 5316/**
5317 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5318 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5319 *
5320 * Returns 0 on success, negative on failure
5321 **/
b6ec895e 5322int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5323{
b6ec895e 5324 struct device *dev = rx_ring->dev;
021230d4 5325 int size;
9a799d71 5326
3a581073 5327 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5328 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5329 if (!rx_ring->rx_buffer_info)
89bf67f1 5330 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5331 if (!rx_ring->rx_buffer_info)
5332 goto err;
9a799d71 5333
9a799d71 5334 /* Round up to nearest 4K */
3a581073
JB		 5335 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5336 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5337
b6ec895e 5338 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5339 &rx_ring->dma, GFP_KERNEL);
9a799d71 5340
b6ec895e
AD		 5341 if (!rx_ring->desc)
5342 goto err;
9a799d71 5343
3a581073
JB		 5344 rx_ring->next_to_clean = 0;
5345 rx_ring->next_to_use = 0;
9a799d71
AK		 5346
5347 return 0;
b6ec895e
AD		 5348err:
5349 vfree(rx_ring->rx_buffer_info);
5350 rx_ring->rx_buffer_info = NULL;
5351 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5352 return -ENOMEM;
9a799d71
AK		 5353}
5354
69888674
AD		 5355/**
5356 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5357 * @adapter: board private structure
5358 *
5359 * If this function returns with an error, then it's possible one or
5360 * more of the rings is populated (while the rest are not). It is the
5361 * callers duty to clean those orphaned rings.
5362 *
5363 * Return 0 on success, negative on failure
5364 **/
69888674
AD		 5365static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5366{
5367 int i, err = 0;
5368
5369 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5370 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5371 if (!err)
5372 continue;
396e799c 5373 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5374 break;
5375 }
5376
5377 return err;
5378}
5379
9a799d71
AK		 5380/**
5381 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5382 * @tx_ring: Tx descriptor ring for a specific queue
5383 *
5384 * Free all transmit software resources
5385 **/
b6ec895e 5386void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5387{
b6ec895e 5388 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5389
5390 vfree(tx_ring->tx_buffer_info);
5391 tx_ring->tx_buffer_info = NULL;
5392
b6ec895e
AD		 5393 /* if not set, then don't free */
5394 if (!tx_ring->desc)
5395 return;
5396
5397 dma_free_coherent(tx_ring->dev, tx_ring->size,
5398 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5399
5400 tx_ring->desc = NULL;
5401}
5402
5403/**
5404 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5405 * @adapter: board private structure
5406 *
5407 * Free all transmit software resources
5408 **/
5409static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5410{
5411 int i;
5412
5413 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5414 if (adapter->tx_ring[i]->desc)
b6ec895e 5415 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5416}
5417
5418/**
b4617240 5419 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5420 * @rx_ring: ring to clean the resources from
5421 *
5422 * Free all receive software resources
5423 **/
b6ec895e 5424void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5425{
b6ec895e 5426 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5427
5428 vfree(rx_ring->rx_buffer_info);
5429 rx_ring->rx_buffer_info = NULL;
5430
b6ec895e
AD		 5431 /* if not set, then don't free */
5432 if (!rx_ring->desc)
5433 return;
5434
5435 dma_free_coherent(rx_ring->dev, rx_ring->size,
5436 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5437
5438 rx_ring->desc = NULL;
5439}
5440
5441/**
5442 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5443 * @adapter: board private structure
5444 *
5445 * Free all receive software resources
5446 **/
5447static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5448{
5449 int i;
5450
5451 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5452 if (adapter->rx_ring[i]->desc)
b6ec895e 5453 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5454}
5455
9a799d71
AK		 5456/**
5457 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5458 * @netdev: network interface device structure
5459 * @new_mtu: new value for maximum frame size
5460 *
5461 * Returns 0 on success, negative on failure
5462 **/
5463static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5464{
5465 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5466 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5467 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5468
42c783c5 5469 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5470 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5471 hw->mac.type != ixgbe_mac_X540) {
5472 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5473 return -EINVAL;
5474 } else {
5475 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5476 return -EINVAL;
5477 }
9a799d71 5478
396e799c 5479 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5480 /* must set new MTU before calling down or up */
9a799d71
AK		 5481 netdev->mtu = new_mtu;
5482
16b61beb
JF		 5483 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5484 hw->fc.low_water = FC_LOW_WATER(max_frame);
5485
d4f80882
AV		 5486 if (netif_running(netdev))
5487 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5488
5489 return 0;
5490}
5491
5492/**
5493 * ixgbe_open - Called when a network interface is made active
5494 * @netdev: network interface device structure
5495 *
5496 * Returns 0 on success, negative value on failure
5497 *
5498 * The open entry point is called when a network interface is made
5499 * active by the system (IFF_UP). At this point all resources needed
5500 * for transmit and receive operations are allocated, the interrupt
5501 * handler is registered with the OS, the watchdog timer is started,
5502 * and the stack is notified that the interface is ready.
5503 **/
5504static int ixgbe_open(struct net_device *netdev)
5505{
5506 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5507 int err;
4bebfaa5
AK		 5508
5509 /* disallow open during test */
5510 if (test_bit(__IXGBE_TESTING, &adapter->state))
5511 return -EBUSY;
9a799d71 5512
54386467
JB		 5513 netif_carrier_off(netdev);
5514
9a799d71
AK		 5515 /* allocate transmit descriptors */
5516 err = ixgbe_setup_all_tx_resources(adapter);
5517 if (err)
5518 goto err_setup_tx;
5519
9a799d71
AK		 5520 /* allocate receive descriptors */
5521 err = ixgbe_setup_all_rx_resources(adapter);
5522 if (err)
5523 goto err_setup_rx;
5524
5525 ixgbe_configure(adapter);
5526
021230d4 5527 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5528 if (err)
5529 goto err_req_irq;
5530
9a799d71
AK		 5531 err = ixgbe_up_complete(adapter);
5532 if (err)
5533 goto err_up;
5534
d55b53ff
JK		 5535 netif_tx_start_all_queues(netdev);
5536
9a799d71
AK		 5537 return 0;
5538
5539err_up:
5eba3699 5540 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5541 ixgbe_free_irq(adapter);
5542err_req_irq:
9a799d71 5543err_setup_rx:
a20a1199 5544 ixgbe_free_all_rx_resources(adapter);
9a799d71 5545err_setup_tx:
a20a1199 5546 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5547 ixgbe_reset(adapter);
5548
5549 return err;
5550}
5551
5552/**
5553 * ixgbe_close - Disables a network interface
5554 * @netdev: network interface device structure
5555 *
5556 * Returns 0, this is not allowed to fail
5557 *
5558 * The close entry point is called when an interface is de-activated
5559 * by the OS. The hardware is still under the drivers control, but
5560 * needs to be disabled. A global MAC reset is issued to stop the
5561 * hardware, and all transmit and receive resources are freed.
5562 **/
5563static int ixgbe_close(struct net_device *netdev)
5564{
5565 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5566
5567 ixgbe_down(adapter);
5568 ixgbe_free_irq(adapter);
5569
e4911d57
AD		 5570 ixgbe_fdir_filter_exit(adapter);
5571
9a799d71
AK		 5572 ixgbe_free_all_tx_resources(adapter);
5573 ixgbe_free_all_rx_resources(adapter);
5574
5eba3699 5575 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5576
5577 return 0;
5578}
5579
b3c8b4ba
AD		 5580#ifdef CONFIG_PM
5581static int ixgbe_resume(struct pci_dev *pdev)
5582{
c60fbb00
AD		 5583 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5584 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5585 u32 err;
5586
5587 pci_set_power_state(pdev, PCI_D0);
5588 pci_restore_state(pdev);
656ab817
DS		 5589 /*
5590 * pci_restore_state clears dev->state_saved so call
5591 * pci_save_state to restore it.
5592 */
5593 pci_save_state(pdev);
9ce77666 5594
5595 err = pci_enable_device_mem(pdev);
b3c8b4ba 5596 if (err) {
849c4542 5597 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5598 return err;
5599 }
5600 pci_set_master(pdev);
5601
dd4d8ca6 5602 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5603
5604 err = ixgbe_init_interrupt_scheme(adapter);
5605 if (err) {
849c4542 5606 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5607 return err;
5608 }
5609
b3c8b4ba
AD		 5610 ixgbe_reset(adapter);
5611
495dce12
WJP		 5612 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5613
b3c8b4ba 5614 if (netif_running(netdev)) {
c60fbb00 5615 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5616 if (err)
5617 return err;
5618 }
5619
5620 netif_device_attach(netdev);
5621
5622 return 0;
5623}
b3c8b4ba 5624#endif /* CONFIG_PM */
9d8d05ae
RW		 5625
5626static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5627{
c60fbb00
AD		 5628 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5629 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5630 struct ixgbe_hw *hw = &adapter->hw;
5631 u32 ctrl, fctrl;
5632 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5633#ifdef CONFIG_PM
5634 int retval = 0;
5635#endif
5636
5637 netif_device_detach(netdev);
5638
5639 if (netif_running(netdev)) {
5640 ixgbe_down(adapter);
5641 ixgbe_free_irq(adapter);
5642 ixgbe_free_all_tx_resources(adapter);
5643 ixgbe_free_all_rx_resources(adapter);
5644 }
b3c8b4ba 5645
5f5ae6fc 5646 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5647#ifdef CONFIG_DCB
5648 kfree(adapter->ixgbe_ieee_pfc);
5649 kfree(adapter->ixgbe_ieee_ets);
5650#endif
5f5ae6fc 5651
b3c8b4ba
AD		 5652#ifdef CONFIG_PM
5653 retval = pci_save_state(pdev);
5654 if (retval)
5655 return retval;
4df10466 5656
b3c8b4ba 5657#endif
e8e26350
PW		 5658 if (wufc) {
5659 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5660
e8e26350
PW		 5661 /* turn on all-multi mode if wake on multicast is enabled */
5662 if (wufc & IXGBE_WUFC_MC) {
5663 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5664 fctrl |= IXGBE_FCTRL_MPE;
5665 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5666 }
5667
5668 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5669 ctrl |= IXGBE_CTRL_GIO_DIS;
5670 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5671
5672 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5673 } else {
5674 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5675 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5676 }
5677
bd508178
AD		 5678 switch (hw->mac.type) {
5679 case ixgbe_mac_82598EB:
dd4d8ca6 5680 pci_wake_from_d3(pdev, false);
bd508178
AD		 5681 break;
5682 case ixgbe_mac_82599EB:
b93a2226 5683 case ixgbe_mac_X540:
bd508178
AD		 5684 pci_wake_from_d3(pdev, !!wufc);
5685 break;
5686 default:
5687 break;
5688 }
b3c8b4ba 5689
9d8d05ae
RW		 5690 *enable_wake = !!wufc;
5691
b3c8b4ba
AD		 5692 ixgbe_release_hw_control(adapter);
5693
5694 pci_disable_device(pdev);
5695
9d8d05ae
RW		 5696 return 0;
5697}
5698
5699#ifdef CONFIG_PM
5700static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5701{
5702 int retval;
5703 bool wake;
5704
5705 retval = __ixgbe_shutdown(pdev, &wake);
5706 if (retval)
5707 return retval;
5708
5709 if (wake) {
5710 pci_prepare_to_sleep(pdev);
5711 } else {
5712 pci_wake_from_d3(pdev, false);
5713 pci_set_power_state(pdev, PCI_D3hot);
5714 }
b3c8b4ba
AD		 5715
5716 return 0;
5717}
9d8d05ae 5718#endif /* CONFIG_PM */
b3c8b4ba
AD		 5719
5720static void ixgbe_shutdown(struct pci_dev *pdev)
5721{
9d8d05ae
RW		 5722 bool wake;
5723
5724 __ixgbe_shutdown(pdev, &wake);
5725
5726 if (system_state == SYSTEM_POWER_OFF) {
5727 pci_wake_from_d3(pdev, wake);
5728 pci_set_power_state(pdev, PCI_D3hot);
5729 }
b3c8b4ba
AD		 5730}
5731
9a799d71
AK		 5732/**
5733 * ixgbe_update_stats - Update the board statistics counters.
5734 * @adapter: board private structure
5735 **/
5736void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5737{
2d86f139 5738 struct net_device *netdev = adapter->netdev;
9a799d71 5739 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5740 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5741 u64 total_mpc = 0;
5742 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5743 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5744 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5745 u64 bytes = 0, packets = 0;
9a799d71 5746
d08935c2
DS		 5747 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5748 test_bit(__IXGBE_RESETTING, &adapter->state))
5749 return;
5750
94b982b2 5751 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5752 u64 rsc_count = 0;
94b982b2 5753 u64 rsc_flush = 0;
d51019a4
PW		 5754 for (i = 0; i < 16; i++)
5755 adapter->hw_rx_no_dma_resources +=
7ca647bd 5756 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5757 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5758 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5759 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5760 }
5761 adapter->rsc_total_count = rsc_count;
5762 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5763 }
5764
5b7da515
AD		 5765 for (i = 0; i < adapter->num_rx_queues; i++) {
5766 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5767 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5768 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5769 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5770 bytes += rx_ring->stats.bytes;
5771 packets += rx_ring->stats.packets;
5772 }
5773 adapter->non_eop_descs = non_eop_descs;
5774 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5775 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5776 netdev->stats.rx_bytes = bytes;
5777 netdev->stats.rx_packets = packets;
5778
5779 bytes = 0;
5780 packets = 0;
7ca3bc58 5781 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5782 for (i = 0; i < adapter->num_tx_queues; i++) {
5783 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5784 restart_queue += tx_ring->tx_stats.restart_queue;
5785 tx_busy += tx_ring->tx_stats.tx_busy;
5786 bytes += tx_ring->stats.bytes;
5787 packets += tx_ring->stats.packets;
5788 }
eb985f09 5789 adapter->restart_queue = restart_queue;
5b7da515
AD		 5790 adapter->tx_busy = tx_busy;
5791 netdev->stats.tx_bytes = bytes;
5792 netdev->stats.tx_packets = packets;
7ca3bc58 5793
7ca647bd 5794 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5795 for (i = 0; i < 8; i++) {
5796 /* for packet buffers not used, the register should read 0 */
5797 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5798 missed_rx += mpc;
7ca647bd
JP		 5799 hwstats->mpc[i] += mpc;
5800 total_mpc += hwstats->mpc[i];
e8e26350 5801 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5802 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5803 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5804 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5805 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5806 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
bd508178
AD		 5807 switch (hw->mac.type) {
5808 case ixgbe_mac_82598EB:
7ca647bd
JP		 5809 hwstats->pxonrxc[i] +=
5810 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5811 break;
5812 case ixgbe_mac_82599EB:
b93a2226 5813 case ixgbe_mac_X540:
bd508178
AD		 5814 hwstats->pxonrxc[i] +=
5815 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5816 break;
5817 default:
5818 break;
e8e26350 5819 }
7ca647bd
JP		 5820 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5821 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5822 }
7ca647bd 5823 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5824 /* work around hardware counting issue */
7ca647bd 5825 hwstats->gprc -= missed_rx;
6f11eef7 5826
c84d324c
JF		 5827 ixgbe_update_xoff_received(adapter);
5828
6f11eef7 5829 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5830 switch (hw->mac.type) {
5831 case ixgbe_mac_82598EB:
5832 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5833 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5834 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5835 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5836 break;
b93a2226 5837 case ixgbe_mac_X540:
58f6bcf9
ET		 5838 /* OS2BMC stats are X540 only*/
5839 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5840 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5841 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5842 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5843 case ixgbe_mac_82599EB:
7ca647bd 5844 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5845 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5846 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5847 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5848 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5849 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5850 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5851 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5852 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5853#ifdef IXGBE_FCOE
7ca647bd
JP		 5854 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5855 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5856 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5857 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5858 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5859 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5860#endif /* IXGBE_FCOE */
bd508178
AD		 5861 break;
5862 default:
5863 break;
e8e26350 5864 }
9a799d71 5865 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5866 hwstats->bprc += bprc;
5867 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5868 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5869 hwstats->mprc -= bprc;
5870 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5871 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5872 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5873 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5874 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5875 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5876 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5877 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5878 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5879 hwstats->lxontxc += lxon;
6f11eef7 5880 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5881 hwstats->lxofftxc += lxoff;
5882 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5883 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5884 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5885 /*
5886 * 82598 errata - tx of flow control packets is included in tx counters
5887 */
5888 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5889 hwstats->gptc -= xon_off_tot;
5890 hwstats->mptc -= xon_off_tot;
5891 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5892 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5893 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5894 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5895 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5896 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5897 hwstats->ptc64 -= xon_off_tot;
5898 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5899 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5900 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5901 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5902 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5903 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5904
5905 /* Fill out the OS statistics structure */
7ca647bd 5906 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5907
5908 /* Rx Errors */
7ca647bd 5909 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5910 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5911 netdev->stats.rx_length_errors = hwstats->rlec;
5912 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5913 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5914}
5915
5916/**
d034acf1
AD		 5917 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5918 * @adapter - pointer to the device adapter structure
9a799d71 5919 **/
d034acf1 5920static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5921{
cf8280ee 5922 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5923 int i;
cf8280ee 5924
d034acf1
AD		 5925 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5926 return;
5927
5928 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5929
d034acf1 5930 /* if interface is down do nothing */
fe49f04a 5931 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5932 return;
5933
5934 /* do nothing if we are not using signature filters */
5935 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5936 return;
5937
5938 adapter->fdir_overflow++;
5939
93c52dd0
AD		 5940 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5941 for (i = 0; i < adapter->num_tx_queues; i++)
5942 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5943 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5944 /* re-enable flow director interrupts */
5945 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5946 } else {
5947 e_err(probe, "failed to finish FDIR re-initialization, "
5948 "ignored adding FDIR ATR filters\n");
5949 }
93c52dd0
AD		 5950}
5951
5952/**
5953 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5954 * @adapter - pointer to the device adapter structure
5955 *
5956 * This function serves two purposes. First it strobes the interrupt lines
5957 * in order to make certain interrupts are occuring. Secondly it sets the
5958 * bits needed to check for TX hangs. As a result we should immediately
5959 * determine if a hang has occured.
5960 */
5961static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5962{
cf8280ee 5963 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5964 u64 eics = 0;
5965 int i;
cf8280ee 5966
93c52dd0
AD		 5967 /* If we're down or resetting, just bail */
5968 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5969 test_bit(__IXGBE_RESETTING, &adapter->state))
5970 return;
22d5a71b 5971
93c52dd0
AD		 5972 /* Force detection of hung controller */
5973 if (netif_carrier_ok(adapter->netdev)) {
5974 for (i = 0; i < adapter->num_tx_queues; i++)
5975 set_check_for_tx_hang(adapter->tx_ring[i]);
5976 }
22d5a71b 5977
fe49f04a
AD		 5978 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5979 /*
5980 * for legacy and MSI interrupts don't set any bits
5981 * that are enabled for EIAM, because this operation
5982 * would set *both* EIMS and EICS for any bit in EIAM
5983 */
5984 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5985 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5986 } else {
5987 /* get one bit for every active tx/rx interrupt vector */
5988 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5989 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5990 if (qv->rxr_count || qv->txr_count)
5991 eics |= ((u64)1 << i);
5992 }
cf8280ee 5993 }
9a799d71 5994
93c52dd0 5995 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5996 ixgbe_irq_rearm_queues(adapter, eics);
5997
cf8280ee
JB		 5998}
5999
e8e26350 6000/**
93c52dd0
AD		 6001 * ixgbe_watchdog_update_link - update the link status
6002 * @adapter - pointer to the device adapter structure
6003 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 6004 **/
93c52dd0 6005static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6006{
e8e26350 6007 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6008 u32 link_speed = adapter->link_speed;
6009 bool link_up = adapter->link_up;
c4cf55e5 6010 int i;
e8e26350 6011
93c52dd0
AD		 6012 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6013 return;
6014
6015 if (hw->mac.ops.check_link) {
6016 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6017 } else {
93c52dd0
AD		 6018 /* always assume link is up, if no check link function */
6019 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6020 link_up = true;
c4cf55e5 6021 }
93c52dd0
AD		 6022 if (link_up) {
6023 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6024 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6025 hw->mac.ops.fc_enable(hw, i);
6026 } else {
6027 hw->mac.ops.fc_enable(hw, 0);
6028 }
6029 }
6030
6031 if (link_up ||
6032 time_after(jiffies, (adapter->link_check_timeout +
6033 IXGBE_TRY_LINK_TIMEOUT))) {
6034 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6035 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6036 IXGBE_WRITE_FLUSH(hw);
6037 }
6038
6039 adapter->link_up = link_up;
6040 adapter->link_speed = link_speed;
e8e26350
PW		 6041}
6042
6043/**
93c52dd0
AD		 6044 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6045 * print link up message
6046 * @adapter - pointer to the device adapter structure
e8e26350 6047 **/
93c52dd0 6048static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6049{
93c52dd0 6050 struct net_device *netdev = adapter->netdev;
e8e26350 6051 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6052 u32 link_speed = adapter->link_speed;
6053 bool flow_rx, flow_tx;
e8e26350 6054
93c52dd0
AD		 6055 /* only continue if link was previously down */
6056 if (netif_carrier_ok(netdev))
a985b6c3 6057 return;
63d6e1d8 6058
93c52dd0 6059 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6060
93c52dd0
AD		 6061 switch (hw->mac.type) {
6062 case ixgbe_mac_82598EB: {
6063 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6064 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6065 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6066 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6067 }
6068 break;
6069 case ixgbe_mac_X540:
6070 case ixgbe_mac_82599EB: {
6071 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6072 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6073 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6074 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6075 }
6076 break;
6077 default:
6078 flow_tx = false;
6079 flow_rx = false;
6080 break;
e8e26350 6081 }
93c52dd0
AD		 6082 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6083 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6084 "10 Gbps" :
6085 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6086 "1 Gbps" :
6087 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6088 "100 Mbps" :
6089 "unknown speed"))),
6090 ((flow_rx && flow_tx) ? "RX/TX" :
6091 (flow_rx ? "RX" :
6092 (flow_tx ? "TX" : "None"))));
e8e26350 6093
93c52dd0
AD		 6094 netif_carrier_on(netdev);
6095#ifdef HAVE_IPLINK_VF_CONFIG
6096 ixgbe_check_vf_rate_limit(adapter);
6097#endif /* HAVE_IPLINK_VF_CONFIG */
e8e26350
PW		 6098}
6099
c4cf55e5 6100/**
93c52dd0
AD		 6101 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6102 * print link down message
6103 * @adapter - pointer to the adapter structure
c4cf55e5 6104 **/
93c52dd0 6105static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 6106{
cf8280ee 6107 struct net_device *netdev = adapter->netdev;
c4cf55e5 6108 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6109
93c52dd0
AD		 6110 adapter->link_up = false;
6111 adapter->link_speed = 0;
cf8280ee 6112
93c52dd0
AD		 6113 /* only continue if link was up previously */
6114 if (!netif_carrier_ok(netdev))
6115 return;
264857b8 6116
93c52dd0
AD		 6117 /* poll for SFP+ cable when link is down */
6118 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6119 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6120
93c52dd0
AD		 6121 e_info(drv, "NIC Link is Down\n");
6122 netif_carrier_off(netdev);
6123}
e8e26350 6124
93c52dd0
AD		 6125/**
6126 * ixgbe_watchdog_flush_tx - flush queues on link down
6127 * @adapter - pointer to the device adapter structure
6128 **/
6129static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6130{
c4cf55e5 6131 int i;
93c52dd0 6132 int some_tx_pending = 0;
c4cf55e5 6133
93c52dd0 6134 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6135 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6136 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6137 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6138 some_tx_pending = 1;
6139 break;
6140 }
6141 }
6142
6143 if (some_tx_pending) {
6144 /* We've lost link, so the controller stops DMA,
6145 * but we've got queued Tx work that's never going
6146 * to get done, so reset controller to flush Tx.
6147 * (Do the reset outside of interrupt context).
6148 */
c83c6cbd 6149 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6150 }
c4cf55e5 6151 }
c4cf55e5
PWJ		 6152}
6153
a985b6c3
GR		 6154static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6155{
6156 u32 ssvpc;
6157
6158 /* Do not perform spoof check for 82598 */
6159 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6160 return;
6161
6162 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6163
6164 /*
6165 * ssvpc register is cleared on read, if zero then no
6166 * spoofed packets in the last interval.
6167 */
6168 if (!ssvpc)
6169 return;
6170
6171 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6172}
6173
93c52dd0
AD		 6174/**
6175 * ixgbe_watchdog_subtask - check and bring link up
6176 * @adapter - pointer to the device adapter structure
6177 **/
6178static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6179{
6180 /* if interface is down do nothing */
6181 if (test_bit(__IXGBE_DOWN, &adapter->state))
6182 return;
6183
6184 ixgbe_watchdog_update_link(adapter);
6185
6186 if (adapter->link_up)
6187 ixgbe_watchdog_link_is_up(adapter);
6188 else
6189 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6190
a985b6c3 6191 ixgbe_spoof_check(adapter);
9a799d71 6192 ixgbe_update_stats(adapter);
93c52dd0
AD		 6193
6194 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6195}
10eec955 6196
cf8280ee 6197/**
7086400d
AD		 6198 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6199 * @adapter - the ixgbe adapter structure
cf8280ee 6200 **/
7086400d 6201static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6202{
cf8280ee 6203 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6204 s32 err;
cf8280ee 6205
7086400d
AD		 6206 /* not searching for SFP so there is nothing to do here */
6207 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6208 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6209 return;
10eec955 6210
7086400d
AD		 6211 /* someone else is in init, wait until next service event */
6212 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6213 return;
cf8280ee 6214
7086400d
AD		 6215 err = hw->phy.ops.identify_sfp(hw);
6216 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6217 goto sfp_out;
264857b8 6218
7086400d
AD		 6219 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6220 /* If no cable is present, then we need to reset
6221 * the next time we find a good cable. */
6222 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6223 }
9a799d71 6224
7086400d
AD		 6225 /* exit on error */
6226 if (err)
6227 goto sfp_out;
e8e26350 6228
7086400d
AD		 6229 /* exit if reset not needed */
6230 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6231 goto sfp_out;
9a799d71 6232
7086400d 6233 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6234
7086400d
AD		 6235 /*
6236 * A module may be identified correctly, but the EEPROM may not have
6237 * support for that module. setup_sfp() will fail in that case, so
6238 * we should not allow that module to load.
6239 */
6240 if (hw->mac.type == ixgbe_mac_82598EB)
6241 err = hw->phy.ops.reset(hw);
6242 else
6243 err = hw->mac.ops.setup_sfp(hw);
6244
6245 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6246 goto sfp_out;
6247
6248 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6249 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6250
6251sfp_out:
6252 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6253
6254 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6255 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6256 e_dev_err("failed to initialize because an unsupported "
6257 "SFP+ module type was detected.\n");
6258 e_dev_err("Reload the driver after installing a "
6259 "supported module.\n");
6260 unregister_netdev(adapter->netdev);
bc59fcda 6261 }
7086400d 6262}
bc59fcda 6263
7086400d
AD		 6264/**
6265 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6266 * @adapter - the ixgbe adapter structure
6267 **/
6268static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6269{
6270 struct ixgbe_hw *hw = &adapter->hw;
6271 u32 autoneg;
6272 bool negotiation;
6273
6274 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6275 return;
6276
6277 /* someone else is in init, wait until next service event */
6278 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6279 return;
6280
6281 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6282
6283 autoneg = hw->phy.autoneg_advertised;
6284 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6285 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6286 hw->mac.autotry_restart = false;
6287 if (hw->mac.ops.setup_link)
6288 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6289
6290 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6291 adapter->link_check_timeout = jiffies;
6292 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6293}
6294
6295/**
6296 * ixgbe_service_timer - Timer Call-back
6297 * @data: pointer to adapter cast into an unsigned long
6298 **/
6299static void ixgbe_service_timer(unsigned long data)
6300{
6301 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6302 unsigned long next_event_offset;
6303
6304 /* poll faster when waiting for link */
6305 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6306 next_event_offset = HZ / 10;
6307 else
6308 next_event_offset = HZ * 2;
6309
6310 /* Reset the timer */
6311 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6312
6313 ixgbe_service_event_schedule(adapter);
6314}
6315
c83c6cbd
AD		 6316static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6317{
6318 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6319 return;
6320
6321 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6322
6323 /* If we're already down or resetting, just bail */
6324 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6325 test_bit(__IXGBE_RESETTING, &adapter->state))
6326 return;
6327
6328 ixgbe_dump(adapter);
6329 netdev_err(adapter->netdev, "Reset adapter\n");
6330 adapter->tx_timeout_count++;
6331
6332 ixgbe_reinit_locked(adapter);
6333}
6334
7086400d
AD		 6335/**
6336 * ixgbe_service_task - manages and runs subtasks
6337 * @work: pointer to work_struct containing our data
6338 **/
6339static void ixgbe_service_task(struct work_struct *work)
6340{
6341 struct ixgbe_adapter *adapter = container_of(work,
6342 struct ixgbe_adapter,
6343 service_task);
6344
c83c6cbd 6345 ixgbe_reset_subtask(adapter);
7086400d
AD		 6346 ixgbe_sfp_detection_subtask(adapter);
6347 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6348 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6349 ixgbe_watchdog_subtask(adapter);
d034acf1 6350 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6351 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6352
6353 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6354}
6355
9a799d71 6356static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696 6357 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5e09a105 6358 u32 tx_flags, u8 *hdr_len, __be16 protocol)
9a799d71
AK		 6359{
6360 struct ixgbe_adv_tx_context_desc *context_desc;
6361 unsigned int i;
6362 int err;
6363 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 6364 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6365 u32 mss_l4len_idx, l4len;
9a799d71
AK		 6366
6367 if (skb_is_gso(skb)) {
6368 if (skb_header_cloned(skb)) {
6369 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6370 if (err)
6371 return err;
6372 }
6373 l4len = tcp_hdrlen(skb);
6374 *hdr_len += l4len;
6375
5e09a105 6376 if (protocol == htons(ETH_P_IP)) {
9a799d71
AK		 6377 struct iphdr *iph = ip_hdr(skb);
6378 iph->tot_len = 0;
6379 iph->check = 0;
6380 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 6381 iph->daddr, 0,
6382 IPPROTO_TCP,
6383 0);
8e1e8a47 6384 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 6385 ipv6_hdr(skb)->payload_len = 0;
6386 tcp_hdr(skb)->check =
6387 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 6388 &ipv6_hdr(skb)->daddr,
6389 0, IPPROTO_TCP, 0);
9a799d71
AK		 6390 }
6391
6392 i = tx_ring->next_to_use;
6393
6394 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6395 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6396
6397 /* VLAN MACLEN IPLEN */
6398 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6399 vlan_macip_lens |=
6400 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6401 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 6402 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6403 *hdr_len += skb_network_offset(skb);
6404 vlan_macip_lens |=
6405 (skb_transport_header(skb) - skb_network_header(skb));
6406 *hdr_len +=
6407 (skb_transport_header(skb) - skb_network_header(skb));
6408 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6409 context_desc->seqnum_seed = 0;
6410
6411 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 6412 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 6413 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6414
5e09a105 6415 if (protocol == htons(ETH_P_IP))
9a799d71
AK		 6416 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6417 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6418 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6419
6420 /* MSS L4LEN IDX */
9f8cdf4f 6421 mss_l4len_idx =
9a799d71
AK		 6422 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6423 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 6424 /* use index 1 for TSO */
6425 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6426 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6427
6428 tx_buffer_info->time_stamp = jiffies;
6429 tx_buffer_info->next_to_watch = i;
6430
6431 i++;
6432 if (i == tx_ring->count)
6433 i = 0;
6434 tx_ring->next_to_use = i;
6435
6436 return true;
6437 }
6438 return false;
6439}
6440
5e09a105
HZ		 6441static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6442 __be16 protocol)
7ca647bd
JP		 6443{
6444 u32 rtn = 0;
7ca647bd
JP		 6445
6446 switch (protocol) {
6447 case cpu_to_be16(ETH_P_IP):
6448 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6449 switch (ip_hdr(skb)->protocol) {
6450 case IPPROTO_TCP:
6451 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6452 break;
6453 case IPPROTO_SCTP:
6454 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6455 break;
6456 }
6457 break;
6458 case cpu_to_be16(ETH_P_IPV6):
6459 /* XXX what about other V6 headers?? */
6460 switch (ipv6_hdr(skb)->nexthdr) {
6461 case IPPROTO_TCP:
6462 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6463 break;
6464 case IPPROTO_SCTP:
6465 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6466 break;
6467 }
6468 break;
6469 default:
6470 if (unlikely(net_ratelimit()))
6471 e_warn(probe, "partial checksum but proto=%x!\n",
5e09a105 6472 protocol);
7ca647bd
JP		 6473 break;
6474 }
6475
6476 return rtn;
6477}
6478
9a799d71 6479static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696 6480 struct ixgbe_ring *tx_ring,
5e09a105
HZ		 6481 struct sk_buff *skb, u32 tx_flags,
6482 __be16 protocol)
9a799d71
AK		 6483{
6484 struct ixgbe_adv_tx_context_desc *context_desc;
6485 unsigned int i;
6486 struct ixgbe_tx_buffer *tx_buffer_info;
6487 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6488
6489 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6490 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6491 i = tx_ring->next_to_use;
6492 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6493 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6494
6495 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6496 vlan_macip_lens |=
6497 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6498 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 6499 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6500 if (skb->ip_summed == CHECKSUM_PARTIAL)
6501 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 6502 skb_network_header(skb));
9a799d71
AK		 6503
6504 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6505 context_desc->seqnum_seed = 0;
6506
6507 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 6508 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6509
7ca647bd 6510 if (skb->ip_summed == CHECKSUM_PARTIAL)
5e09a105 6511 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
9a799d71
AK		 6512
6513 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 6514 /* use index zero for tx checksum offload */
9a799d71
AK		 6515 context_desc->mss_l4len_idx = 0;
6516
6517 tx_buffer_info->time_stamp = jiffies;
6518 tx_buffer_info->next_to_watch = i;
9f8cdf4f 6519
9a799d71
AK		 6520 i++;
6521 if (i == tx_ring->count)
6522 i = 0;
6523 tx_ring->next_to_use = i;
6524
6525 return true;
6526 }
9f8cdf4f 6527
9a799d71
AK		 6528 return false;
6529}
6530
6531static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6532 struct ixgbe_ring *tx_ring,
6533 struct sk_buff *skb, u32 tx_flags,
8ad494b0 6534 unsigned int first, const u8 hdr_len)
9a799d71 6535{
b6ec895e 6536 struct device *dev = tx_ring->dev;
9a799d71 6537 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6538 unsigned int len;
6539 unsigned int total = skb->len;
63544e9c 6540 unsigned int offset = 0, size, count = 0;
9a799d71
AK		 6541 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6542 unsigned int f;
8ad494b0
AD		 6543 unsigned int bytecount = skb->len;
6544 u16 gso_segs = 1;
63544e9c 6545 u16 i;
9a799d71
AK		 6546
6547 i = tx_ring->next_to_use;
6548
eacd73f7
YZ		 6549 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6550 /* excluding fcoe_crc_eof for FCoE */
6551 total -= sizeof(struct fcoe_crc_eof);
6552
6553 len = min(skb_headlen(skb), total);
9a799d71
AK		 6554 while (len) {
6555 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6556 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6557
6558 tx_buffer_info->length = size;
e5a43549 6559 tx_buffer_info->mapped_as_page = false;
b6ec895e 6560 tx_buffer_info->dma = dma_map_single(dev,
e5a43549 6561 skb->data + offset,
1b507730 6562 size, DMA_TO_DEVICE);
b6ec895e 6563 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6564 goto dma_error;
9a799d71
AK		 6565 tx_buffer_info->time_stamp = jiffies;
6566 tx_buffer_info->next_to_watch = i;
6567
6568 len -= size;
eacd73f7 6569 total -= size;
9a799d71
AK		 6570 offset += size;
6571 count++;
44df32c5
AD		 6572
6573 if (len) {
6574 i++;
6575 if (i == tx_ring->count)
6576 i = 0;
6577 }
9a799d71
AK		 6578 }
6579
6580 for (f = 0; f < nr_frags; f++) {
6581 struct skb_frag_struct *frag;
6582
6583 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6584 len = min((unsigned int)frag->size, total);
e5a43549 6585 offset = frag->page_offset;
9a799d71
AK		 6586
6587 while (len) {
44df32c5
AD		 6588 i++;
6589 if (i == tx_ring->count)
6590 i = 0;
6591
9a799d71
AK		 6592 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6593 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6594
6595 tx_buffer_info->length = size;
b6ec895e 6596 tx_buffer_info->dma = dma_map_page(dev,
e5a43549
AD		 6597 frag->page,
6598 offset, size,
1b507730 6599 DMA_TO_DEVICE);
e5a43549 6600 tx_buffer_info->mapped_as_page = true;
b6ec895e 6601 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6602 goto dma_error;
9a799d71
AK		 6603 tx_buffer_info->time_stamp = jiffies;
6604 tx_buffer_info->next_to_watch = i;
6605
6606 len -= size;
eacd73f7 6607 total -= size;
9a799d71
AK		 6608 offset += size;
6609 count++;
9a799d71 6610 }
eacd73f7
YZ		 6611 if (total == 0)
6612 break;
9a799d71 6613 }
44df32c5 6614
8ad494b0
AD		 6615 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6616 gso_segs = skb_shinfo(skb)->gso_segs;
6617#ifdef IXGBE_FCOE
6618 /* adjust for FCoE Sequence Offload */
6619 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6620 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6621 skb_shinfo(skb)->gso_size);
6622#endif /* IXGBE_FCOE */
6623 bytecount += (gso_segs - 1) * hdr_len;
6624
6625 /* multiply data chunks by size of headers */
6626 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6627 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
9a799d71
AK		 6628 tx_ring->tx_buffer_info[i].skb = skb;
6629 tx_ring->tx_buffer_info[first].next_to_watch = i;
6630
e5a43549
AD		 6631 return count;
6632
6633dma_error:
849c4542 6634 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6635
6636 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6637 tx_buffer_info->dma = 0;
6638 tx_buffer_info->time_stamp = 0;
6639 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6640 if (count)
6641 count--;
e5a43549
AD		 6642
6643 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6644 while (count--) {
e8e9f696 6645 if (i == 0)
e5a43549 6646 i += tx_ring->count;
c1fa347f 6647 i--;
e5a43549 6648 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 6649 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
e5a43549
AD		 6650 }
6651
e44d38e1 6652 return 0;
9a799d71
AK		 6653}
6654
84ea2591 6655static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
e8e9f696 6656 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6657{
6658 union ixgbe_adv_tx_desc *tx_desc = NULL;
6659 struct ixgbe_tx_buffer *tx_buffer_info;
6660 u32 olinfo_status = 0, cmd_type_len = 0;
6661 unsigned int i;
6662 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6663
6664 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6665
6666 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6667
6668 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6669 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6670
6671 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6672 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6673
6674 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6675 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6676
4eeae6fd
PW		 6677 /* use index 1 context for tso */
6678 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6679 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6680 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6681 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6682
6683 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6684 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6685 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6686
eacd73f7
YZ		 6687 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6688 olinfo_status |= IXGBE_ADVTXD_CC;
6689 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6690 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6691 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6692 }
6693
9a799d71
AK		 6694 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6695
6696 i = tx_ring->next_to_use;
6697 while (count--) {
6698 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6699 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6700 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6701 tx_desc->read.cmd_type_len =
e8e9f696 6702 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6703 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6704 i++;
6705 if (i == tx_ring->count)
6706 i = 0;
6707 }
6708
6709 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6710
6711 /*
6712 * Force memory writes to complete before letting h/w
6713 * know there are new descriptors to fetch. (Only
6714 * applicable for weak-ordered memory model archs,
6715 * such as IA-64).
6716 */
6717 wmb();
6718
6719 tx_ring->next_to_use = i;
84ea2591 6720 writel(i, tx_ring->tail);
9a799d71
AK		 6721}
6722
69830529
AD		 6723static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6724 u32 tx_flags, __be16 protocol)
6725{
6726 struct ixgbe_q_vector *q_vector = ring->q_vector;
6727 union ixgbe_atr_hash_dword input = { .dword = 0 };
6728 union ixgbe_atr_hash_dword common = { .dword = 0 };
6729 union {
6730 unsigned char *network;
6731 struct iphdr *ipv4;
6732 struct ipv6hdr *ipv6;
6733 } hdr;
ee9e0f0b 6734 struct tcphdr *th;
905e4a41 6735 __be16 vlan_id;
c4cf55e5 6736
69830529
AD		 6737 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6738 if (!q_vector)
6739 return;
6740
6741 /* do nothing if sampling is disabled */
6742 if (!ring->atr_sample_rate)
d3ead241 6743 return;
c4cf55e5 6744
69830529 6745 ring->atr_count++;
c4cf55e5 6746
69830529
AD		 6747 /* snag network header to get L4 type and address */
6748 hdr.network = skb_network_header(skb);
6749
6750 /* Currently only IPv4/IPv6 with TCP is supported */
6751 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6752 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6753 (protocol != __constant_htons(ETH_P_IP) ||
6754 hdr.ipv4->protocol != IPPROTO_TCP))
6755 return;
ee9e0f0b
AD		 6756
6757 th = tcp_hdr(skb);
c4cf55e5 6758
69830529
AD		 6759 /* skip this packet since the socket is closing */
6760 if (th->fin)
6761 return;
6762
6763 /* sample on all syn packets or once every atr sample count */
6764 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6765 return;
6766
6767 /* reset sample count */
6768 ring->atr_count = 0;
6769
6770 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6771
6772 /*
6773 * src and dst are inverted, think how the receiver sees them
6774 *
6775 * The input is broken into two sections, a non-compressed section
6776 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6777 * is XORed together and stored in the compressed dword.
6778 */
6779 input.formatted.vlan_id = vlan_id;
6780
6781 /*
6782 * since src port and flex bytes occupy the same word XOR them together
6783 * and write the value to source port portion of compressed dword
6784 */
6785 if (vlan_id)
6786 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6787 else
6788 common.port.src ^= th->dest ^ protocol;
6789 common.port.dst ^= th->source;
6790
6791 if (protocol == __constant_htons(ETH_P_IP)) {
6792 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6793 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6794 } else {
6795 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6796 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6797 hdr.ipv6->saddr.s6_addr32[1] ^
6798 hdr.ipv6->saddr.s6_addr32[2] ^
6799 hdr.ipv6->saddr.s6_addr32[3] ^
6800 hdr.ipv6->daddr.s6_addr32[0] ^
6801 hdr.ipv6->daddr.s6_addr32[1] ^
6802 hdr.ipv6->daddr.s6_addr32[2] ^
6803 hdr.ipv6->daddr.s6_addr32[3];
6804 }
c4cf55e5
PWJ		 6805
6806 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6807 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6808 input, common, ring->queue_index);
c4cf55e5
PWJ		 6809}
6810
63544e9c 6811static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6812{
fc77dc3c 6813 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6814 /* Herbert's original patch had:
6815 * smp_mb__after_netif_stop_queue();
6816 * but since that doesn't exist yet, just open code it. */
6817 smp_mb();
6818
6819 /* We need to check again in a case another CPU has just
6820 * made room available. */
7d4987de 6821 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6822 return -EBUSY;
6823
6824 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6825 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6826 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6827 return 0;
6828}
6829
63544e9c 6830static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6831{
7d4987de 6832 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6833 return 0;
fc77dc3c 6834 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6835}
6836
09a3b1f8
SH		 6837static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6838{
6839 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6840 int txq = smp_processor_id();
56075a98 6841#ifdef IXGBE_FCOE
5e09a105
HZ		 6842 __be16 protocol;
6843
6844 protocol = vlan_get_protocol(skb);
6845
e5b64635
JF		 6846 if (((protocol == htons(ETH_P_FCOE)) ||
6847 (protocol == htons(ETH_P_FIP))) &&
6848 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6849 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6850 txq += adapter->ring_feature[RING_F_FCOE].mask;
6851 return txq;
56075a98
JF		 6852 }
6853#endif
6854
fdd3d631
KK		 6855 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6856 while (unlikely(txq >= dev->real_num_tx_queues))
6857 txq -= dev->real_num_tx_queues;
5f715823 6858 return txq;
fdd3d631 6859 }
c4cf55e5 6860
09a3b1f8
SH		 6861 return skb_tx_hash(dev, skb);
6862}
6863
fc77dc3c 6864netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6865 struct ixgbe_adapter *adapter,
6866 struct ixgbe_ring *tx_ring)
9a799d71 6867{
9a799d71 6868 unsigned int tx_flags = 0;
5f715823 6869 int tso;
63544e9c
AD		 6870 u16 count = 0;
6871 u16 first;
9a799d71 6872 unsigned int f;
5e09a105 6873 __be16 protocol;
63544e9c 6874 u8 hdr_len = 0;
5e09a105
HZ		 6875
6876 protocol = vlan_get_protocol(skb);
9f8cdf4f 6877
eab6d18d 6878 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6879 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6880 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6881 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
e5b64635 6882 tx_flags |= tx_ring->dcb_tc << 13;
2f90b865
AD		 6883 }
6884 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6885 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6886 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6887 skb->priority != TC_PRIO_CONTROL) {
e5b64635 6888 tx_flags |= tx_ring->dcb_tc << 13;
2ea186ae
JF		 6889 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6890 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6891 }
eacd73f7 6892
09ad1cc0 6893#ifdef IXGBE_FCOE
56075a98
JF		 6894 /* for FCoE with DCB, we force the priority to what
6895 * was specified by the switch */
6896 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
e5b64635
JF		 6897 (protocol == htons(ETH_P_FCOE)))
6898 tx_flags |= IXGBE_TX_FLAGS_FCOE;
ca77cd59
RL		 6899#endif
6900
eacd73f7 6901 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6902 if (skb_is_gso(skb) ||
6903 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6904 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6905 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6906 count++;
6907
9f8cdf4f
JB		 6908 count += TXD_USE_COUNT(skb_headlen(skb));
6909 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6910 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6911
fc77dc3c 6912 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
5b7da515 6913 tx_ring->tx_stats.tx_busy++;
9a799d71
AK		 6914 return NETDEV_TX_BUSY;
6915 }
9a799d71 6916
9a799d71 6917 first = tx_ring->next_to_use;
eacd73f7
YZ		 6918 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6919#ifdef IXGBE_FCOE
6920 /* setup tx offload for FCoE */
6921 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6922 if (tso < 0) {
6923 dev_kfree_skb_any(skb);
6924 return NETDEV_TX_OK;
6925 }
6926 if (tso)
6927 tx_flags |= IXGBE_TX_FLAGS_FSO;
6928#endif /* IXGBE_FCOE */
6929 } else {
5e09a105 6930 if (protocol == htons(ETH_P_IP))
eacd73f7 6931 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5e09a105
HZ		 6932 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6933 protocol);
eacd73f7
YZ		 6934 if (tso < 0) {
6935 dev_kfree_skb_any(skb);
6936 return NETDEV_TX_OK;
6937 }
9a799d71 6938
eacd73f7
YZ		 6939 if (tso)
6940 tx_flags |= IXGBE_TX_FLAGS_TSO;
5e09a105
HZ		 6941 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6942 protocol) &&
eacd73f7
YZ		 6943 (skb->ip_summed == CHECKSUM_PARTIAL))
6944 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6945 }
9a799d71 6946
8ad494b0 6947 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
44df32c5 6948 if (count) {
c4cf55e5 6949 /* add the ATR filter if ATR is on */
69830529
AD		 6950 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6951 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
84ea2591 6952 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
fc77dc3c 6953 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71 6954
44df32c5
AD		 6955 } else {
6956 dev_kfree_skb_any(skb);
6957 tx_ring->tx_buffer_info[first].time_stamp = 0;
6958 tx_ring->next_to_use = first;
6959 }
9a799d71
AK		 6960
6961 return NETDEV_TX_OK;
6962}
6963
84418e3b
AD		 6964static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6965{
6966 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6967 struct ixgbe_ring *tx_ring;
6968
6969 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6970 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6971}
6972
9a799d71
AK		 6973/**
6974 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6975 * @netdev: network interface device structure
6976 * @p: pointer to an address structure
6977 *
6978 * Returns 0 on success, negative on failure
6979 **/
6980static int ixgbe_set_mac(struct net_device *netdev, void *p)
6981{
6982 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6983 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6984 struct sockaddr *addr = p;
6985
6986 if (!is_valid_ether_addr(addr->sa_data))
6987 return -EADDRNOTAVAIL;
6988
6989 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6990 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6991
1cdd1ec8
GR		 6992 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6993 IXGBE_RAH_AV);
9a799d71
AK		 6994
6995 return 0;
6996}
6997
6b73e10d
BH		 6998static int
6999ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7000{
7001 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7002 struct ixgbe_hw *hw = &adapter->hw;
7003 u16 value;
7004 int rc;
7005
7006 if (prtad != hw->phy.mdio.prtad)
7007 return -EINVAL;
7008 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7009 if (!rc)
7010 rc = value;
7011 return rc;
7012}
7013
7014static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7015 u16 addr, u16 value)
7016{
7017 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7018 struct ixgbe_hw *hw = &adapter->hw;
7019
7020 if (prtad != hw->phy.mdio.prtad)
7021 return -EINVAL;
7022 return hw->phy.ops.write_reg(hw, addr, devad, value);
7023}
7024
7025static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7026{
7027 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7028
7029 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7030}
7031
0365e6e4
PW		 7032/**
7033 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7034 * netdev->dev_addrs
0365e6e4
PW		 7035 * @netdev: network interface device structure
7036 *
7037 * Returns non-zero on failure
7038 **/
7039static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7040{
7041 int err = 0;
7042 struct ixgbe_adapter *adapter = netdev_priv(dev);
7043 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7044
7045 if (is_valid_ether_addr(mac->san_addr)) {
7046 rtnl_lock();
7047 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7048 rtnl_unlock();
7049 }
7050 return err;
7051}
7052
7053/**
7054 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7055 * netdev->dev_addrs
0365e6e4
PW		 7056 * @netdev: network interface device structure
7057 *
7058 * Returns non-zero on failure
7059 **/
7060static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7061{
7062 int err = 0;
7063 struct ixgbe_adapter *adapter = netdev_priv(dev);
7064 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7065
7066 if (is_valid_ether_addr(mac->san_addr)) {
7067 rtnl_lock();
7068 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7069 rtnl_unlock();
7070 }
7071 return err;
7072}
7073
9a799d71
AK		 7074#ifdef CONFIG_NET_POLL_CONTROLLER
7075/*
7076 * Polling 'interrupt' - used by things like netconsole to send skbs
7077 * without having to re-enable interrupts. It's not called while
7078 * the interrupt routine is executing.
7079 */
7080static void ixgbe_netpoll(struct net_device *netdev)
7081{
7082 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7083 int i;
9a799d71 7084
1a647bd2
AD		 7085 /* if interface is down do nothing */
7086 if (test_bit(__IXGBE_DOWN, &adapter->state))
7087 return;
7088
9a799d71 7089 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7090 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7091 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7092 for (i = 0; i < num_q_vectors; i++) {
7093 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7094 ixgbe_msix_clean_many(0, q_vector);
7095 }
7096 } else {
7097 ixgbe_intr(adapter->pdev->irq, netdev);
7098 }
9a799d71 7099 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7100}
7101#endif
7102
de1036b1
ED		 7103static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7104 struct rtnl_link_stats64 *stats)
7105{
7106 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7107 int i;
7108
1a51502b 7109 rcu_read_lock();
de1036b1 7110 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7111 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7112 u64 bytes, packets;
7113 unsigned int start;
7114
1a51502b
ED		 7115 if (ring) {
7116 do {
7117 start = u64_stats_fetch_begin_bh(&ring->syncp);
7118 packets = ring->stats.packets;
7119 bytes = ring->stats.bytes;
7120 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7121 stats->rx_packets += packets;
7122 stats->rx_bytes += bytes;
7123 }
de1036b1 7124 }
1ac9ad13
ED		 7125
7126 for (i = 0; i < adapter->num_tx_queues; i++) {
7127 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7128 u64 bytes, packets;
7129 unsigned int start;
7130
7131 if (ring) {
7132 do {
7133 start = u64_stats_fetch_begin_bh(&ring->syncp);
7134 packets = ring->stats.packets;
7135 bytes = ring->stats.bytes;
7136 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7137 stats->tx_packets += packets;
7138 stats->tx_bytes += bytes;
7139 }
7140 }
1a51502b 7141 rcu_read_unlock();
de1036b1
ED		 7142 /* following stats updated by ixgbe_watchdog_task() */
7143 stats->multicast = netdev->stats.multicast;
7144 stats->rx_errors = netdev->stats.rx_errors;
7145 stats->rx_length_errors = netdev->stats.rx_length_errors;
7146 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7147 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7148 return stats;
7149}
7150
8b1c0b24
JF		 7151/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7152 * #adapter: pointer to ixgbe_adapter
7153 * @tc: number of traffic classes currently enabled
7154 *
7155 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7156 * 802.1Q priority maps to a packet buffer that exists.
7157 */
7158static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7159{
7160 struct ixgbe_hw *hw = &adapter->hw;
7161 u32 reg, rsave;
7162 int i;
7163
7164 /* 82598 have a static priority to TC mapping that can not
7165 * be changed so no validation is needed.
7166 */
7167 if (hw->mac.type == ixgbe_mac_82598EB)
7168 return;
7169
7170 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7171 rsave = reg;
7172
7173 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7174 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7175
7176 /* If up2tc is out of bounds default to zero */
7177 if (up2tc > tc)
7178 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7179 }
7180
7181 if (reg != rsave)
7182 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7183
7184 return;
7185}
7186
7187
7188/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7189 * classes.
7190 *
7191 * @netdev: net device to configure
7192 * @tc: number of traffic classes to enable
7193 */
7194int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7195{
8b1c0b24
JF		 7196 struct ixgbe_adapter *adapter = netdev_priv(dev);
7197 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24
JF		 7198
7199 /* If DCB is anabled do not remove traffic classes, multiple
7200 * traffic classes are required to implement DCB
7201 */
7202 if (!tc && (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7203 return 0;
7204
7205 /* Hardware supports up to 8 traffic classes */
7206 if (tc > MAX_TRAFFIC_CLASS ||
7207 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7208 return -EINVAL;
7209
7210 /* Hardware has to reinitialize queues and interrupts to
7211 * match packet buffer alignment. Unfortunantly, the
7212 * hardware is not flexible enough to do this dynamically.
7213 */
7214 if (netif_running(dev))
7215 ixgbe_close(dev);
7216 ixgbe_clear_interrupt_scheme(adapter);
7217
7218 if (tc)
7219 netdev_set_num_tc(dev, tc);
7220 else
7221 netdev_reset_tc(dev);
7222
8b1c0b24
JF		 7223 ixgbe_init_interrupt_scheme(adapter);
7224 ixgbe_validate_rtr(adapter, tc);
7225 if (netif_running(dev))
7226 ixgbe_open(dev);
7227
7228 return 0;
7229}
de1036b1 7230
0edc3527 7231static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7232 .ndo_open = ixgbe_open,
0edc3527 7233 .ndo_stop = ixgbe_close,
00829823 7234 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7235 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7236 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7237 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7238 .ndo_validate_addr = eth_validate_addr,
7239 .ndo_set_mac_address = ixgbe_set_mac,
7240 .ndo_change_mtu = ixgbe_change_mtu,
7241 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7242 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7243 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7244 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7245 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7246 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7247 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7248 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7249 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7250 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7251#ifdef CONFIG_NET_POLL_CONTROLLER
7252 .ndo_poll_controller = ixgbe_netpoll,
7253#endif
332d4a7d
YZ		 7254#ifdef IXGBE_FCOE
7255 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7256 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7257 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7258 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7259 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7260 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7261#endif /* IXGBE_FCOE */
0edc3527
SH		 7262};
7263
1cdd1ec8
GR		 7264static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7265 const struct ixgbe_info *ii)
7266{
7267#ifdef CONFIG_PCI_IOV
7268 struct ixgbe_hw *hw = &adapter->hw;
7269 int err;
a1cbb15c
GR		 7270 int num_vf_macvlans, i;
7271 struct vf_macvlans *mv_list;
1cdd1ec8 7272
3377eba7 7273 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
1cdd1ec8
GR		 7274 return;
7275
7276 /* The 82599 supports up to 64 VFs per physical function
7277 * but this implementation limits allocation to 63 so that
7278 * basic networking resources are still available to the
7279 * physical function
7280 */
7281 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7282 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7283 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7284 if (err) {
396e799c 7285 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 7286 goto err_novfs;
7287 }
a1cbb15c
GR		 7288
7289 num_vf_macvlans = hw->mac.num_rar_entries -
7290 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7291
7292 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7293 sizeof(struct vf_macvlans),
7294 GFP_KERNEL);
7295 if (mv_list) {
7296 /* Initialize list of VF macvlans */
7297 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7298 for (i = 0; i < num_vf_macvlans; i++) {
7299 mv_list->vf = -1;
7300 mv_list->free = true;
7301 mv_list->rar_entry = hw->mac.num_rar_entries -
7302 (i + adapter->num_vfs + 1);
7303 list_add(&mv_list->l, &adapter->vf_mvs.l);
7304 mv_list++;
7305 }
7306 }
7307
1cdd1ec8
GR		 7308 /* If call to enable VFs succeeded then allocate memory
7309 * for per VF control structures.
7310 */
7311 adapter->vfinfo =
7312 kcalloc(adapter->num_vfs,
7313 sizeof(struct vf_data_storage), GFP_KERNEL);
7314 if (adapter->vfinfo) {
7315 /* Now that we're sure SR-IOV is enabled
7316 * and memory allocated set up the mailbox parameters
7317 */
7318 ixgbe_init_mbx_params_pf(hw);
7319 memcpy(&hw->mbx.ops, ii->mbx_ops,
7320 sizeof(hw->mbx.ops));
7321
7322 /* Disable RSC when in SR-IOV mode */
7323 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7324 IXGBE_FLAG2_RSC_ENABLED);
7325 return;
7326 }
7327
7328 /* Oh oh */
396e799c
ET		 7329 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7330 "SRIOV disabled\n");
1cdd1ec8
GR		 7331 pci_disable_sriov(adapter->pdev);
7332
7333err_novfs:
7334 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7335 adapter->num_vfs = 0;
7336#endif /* CONFIG_PCI_IOV */
7337}
7338
9a799d71
AK		 7339/**
7340 * ixgbe_probe - Device Initialization Routine
7341 * @pdev: PCI device information struct
7342 * @ent: entry in ixgbe_pci_tbl
7343 *
7344 * Returns 0 on success, negative on failure
7345 *
7346 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7347 * The OS initialization, configuring of the adapter private structure,
7348 * and a hardware reset occur.
7349 **/
7350static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7351 const struct pci_device_id *ent)
9a799d71
AK		 7352{
7353 struct net_device *netdev;
7354 struct ixgbe_adapter *adapter = NULL;
7355 struct ixgbe_hw *hw;
7356 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7357 static int cards_found;
7358 int i, err, pci_using_dac;
289700db 7359 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7360 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7361#ifdef IXGBE_FCOE
7362 u16 device_caps;
7363#endif
289700db 7364 u32 eec;
9a799d71 7365
bded64a7
AG		 7366 /* Catch broken hardware that put the wrong VF device ID in
7367 * the PCIe SR-IOV capability.
7368 */
7369 if (pdev->is_virtfn) {
7370 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7371 pci_name(pdev), pdev->vendor, pdev->device);
7372 return -EINVAL;
7373 }
7374
9ce77666 7375 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7376 if (err)
7377 return err;
7378
1b507730
NN		 7379 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7380 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7381 pci_using_dac = 1;
7382 } else {
1b507730 7383 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7384 if (err) {
1b507730
NN		 7385 err = dma_set_coherent_mask(&pdev->dev,
7386 DMA_BIT_MASK(32));
9a799d71 7387 if (err) {
b8bc0421
DC		 7388 dev_err(&pdev->dev,
7389 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7390 goto err_dma;
7391 }
7392 }
7393 pci_using_dac = 0;
7394 }
7395
9ce77666 7396 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7397 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7398 if (err) {
b8bc0421
DC		 7399 dev_err(&pdev->dev,
7400 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7401 goto err_pci_reg;
7402 }
7403
19d5afd4 7404 pci_enable_pcie_error_reporting(pdev);
6fabd715 7405
9a799d71 7406 pci_set_master(pdev);
fb3b27bc 7407 pci_save_state(pdev);
9a799d71 7408
e901acd6
JF		 7409#ifdef CONFIG_IXGBE_DCB
7410 indices *= MAX_TRAFFIC_CLASS;
7411#endif
7412
c85a2618
JF		 7413 if (ii->mac == ixgbe_mac_82598EB)
7414 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7415 else
7416 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7417
e901acd6 7418#ifdef IXGBE_FCOE
c85a2618
JF		 7419 indices += min_t(unsigned int, num_possible_cpus(),
7420 IXGBE_MAX_FCOE_INDICES);
7421#endif
c85a2618 7422 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7423 if (!netdev) {
7424 err = -ENOMEM;
7425 goto err_alloc_etherdev;
7426 }
7427
9a799d71
AK		 7428 SET_NETDEV_DEV(netdev, &pdev->dev);
7429
9a799d71 7430 adapter = netdev_priv(netdev);
c60fbb00 7431 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7432
7433 adapter->netdev = netdev;
7434 adapter->pdev = pdev;
7435 hw = &adapter->hw;
7436 hw->back = adapter;
7437 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7438
05857980 7439 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7440 pci_resource_len(pdev, 0));
9a799d71
AK		 7441 if (!hw->hw_addr) {
7442 err = -EIO;
7443 goto err_ioremap;
7444 }
7445
7446 for (i = 1; i <= 5; i++) {
7447 if (pci_resource_len(pdev, i) == 0)
7448 continue;
7449 }
7450
0edc3527 7451 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7452 ixgbe_set_ethtool_ops(netdev);
9a799d71 7453 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7454 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7455
9a799d71
AK		 7456 adapter->bd_number = cards_found;
7457
9a799d71
AK		 7458 /* Setup hw api */
7459 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7460 hw->mac.type = ii->mac;
9a799d71 7461
c44ade9e
JB		 7462 /* EEPROM */
7463 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7464 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7465 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7466 if (!(eec & (1 << 8)))
7467 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7468
7469 /* PHY */
7470 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7471 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7472 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7473 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7474 hw->phy.mdio.mmds = 0;
7475 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7476 hw->phy.mdio.dev = netdev;
7477 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7478 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7479
8ca783ab 7480 ii->get_invariants(hw);
9a799d71
AK		 7481
7482 /* setup the private structure */
7483 err = ixgbe_sw_init(adapter);
7484 if (err)
7485 goto err_sw_init;
7486
e86bff0e 7487 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7488 switch (adapter->hw.mac.type) {
7489 case ixgbe_mac_82599EB:
7490 case ixgbe_mac_X540:
e86bff0e 7491 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7492 break;
7493 default:
7494 break;
7495 }
e86bff0e 7496
bf069c97
DS		 7497 /*
7498 * If there is a fan on this device and it has failed log the
7499 * failure.
7500 */
7501 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7502 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7503 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7504 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7505 }
7506
c44ade9e 7507 /* reset_hw fills in the perm_addr as well */
119fc60a 7508 hw->phy.reset_if_overtemp = true;
c44ade9e 7509 err = hw->mac.ops.reset_hw(hw);
119fc60a 7510 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7511 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7512 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7513 err = 0;
7514 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7515 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7516 "module type was detected.\n");
7517 e_dev_err("Reload the driver after installing a supported "
7518 "module.\n");
04f165ef
PW		 7519 goto err_sw_init;
7520 } else if (err) {
849c4542 7521 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7522 goto err_sw_init;
7523 }
7524
1cdd1ec8
GR		 7525 ixgbe_probe_vf(adapter, ii);
7526
396e799c 7527 netdev->features = NETIF_F_SG |
e8e9f696
JP		 7528 NETIF_F_IP_CSUM |
7529 NETIF_F_HW_VLAN_TX |
7530 NETIF_F_HW_VLAN_RX |
7531 NETIF_F_HW_VLAN_FILTER;
9a799d71 7532
e9990a9c 7533 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 7534 netdev->features |= NETIF_F_TSO;
9a799d71 7535 netdev->features |= NETIF_F_TSO6;
78b6f4ce 7536 netdev->features |= NETIF_F_GRO;
67a74ee2 7537 netdev->features |= NETIF_F_RXHASH;
ad31c402 7538
58be7666
DS		 7539 switch (adapter->hw.mac.type) {
7540 case ixgbe_mac_82599EB:
7541 case ixgbe_mac_X540:
45a5ead0 7542 netdev->features |= NETIF_F_SCTP_CSUM;
58be7666
DS		 7543 break;
7544 default:
7545 break;
7546 }
45a5ead0 7547
ad31c402
JK		 7548 netdev->vlan_features |= NETIF_F_TSO;
7549 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7550 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7551 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7552 netdev->vlan_features |= NETIF_F_SG;
7553
1cdd1ec8
GR		 7554 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7555 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7556 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7557
7a6b6f51 7558#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7559 netdev->dcbnl_ops = &dcbnl_ops;
7560#endif
7561
eacd73f7 7562#ifdef IXGBE_FCOE
0d551589 7563 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7564 if (hw->mac.ops.get_device_caps) {
7565 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7566 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7567 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7568 }
7569 }
5e09d7f6
YZ		 7570 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7571 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7572 netdev->vlan_features |= NETIF_F_FSO;
7573 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7574 }
eacd73f7 7575#endif /* IXGBE_FCOE */
7b872a55 7576 if (pci_using_dac) {
9a799d71 7577 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7578 netdev->vlan_features |= NETIF_F_HIGHDMA;
7579 }
9a799d71 7580
0c19d6af 7581 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7582 netdev->features |= NETIF_F_LRO;
7583
9a799d71 7584 /* make sure the EEPROM is good */
c44ade9e 7585 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7586 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7587 err = -EIO;
7588 goto err_eeprom;
7589 }
7590
7591 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7592 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7593
c44ade9e 7594 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7595 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7596 err = -EIO;
7597 goto err_eeprom;
7598 }
7599
c6ecf39a
DS		 7600 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7601 if (hw->mac.ops.disable_tx_laser &&
7602 ((hw->phy.multispeed_fiber) ||
9f911707 7603 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 7604 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 7605 hw->mac.ops.disable_tx_laser(hw);
7606
7086400d
AD		 7607 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7608 (unsigned long) adapter);
9a799d71 7609
7086400d
AD		 7610 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7611 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7612
021230d4
AV		 7613 err = ixgbe_init_interrupt_scheme(adapter);
7614 if (err)
7615 goto err_sw_init;
9a799d71 7616
67a74ee2
ET		 7617 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7618 netdev->features &= ~NETIF_F_RXHASH;
7619
e8e26350 7620 switch (pdev->device) {
0b077fea
DS		 7621 case IXGBE_DEV_ID_82599_SFP:
7622 /* Only this subdevice supports WOL */
7623 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7624 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7625 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7626 break;
50d6c681
AD		 7627 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7628 /* All except this subdevice support WOL */
0b077fea
DS		 7629 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7630 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7631 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7632 break;
e8e26350 7633 case IXGBE_DEV_ID_82599_KX4:
495dce12 7634 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 7635 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 7636 break;
7637 default:
7638 adapter->wol = 0;
7639 break;
7640 }
e8e26350
PW		 7641 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7642
04f165ef
PW		 7643 /* pick up the PCI bus settings for reporting later */
7644 hw->mac.ops.get_bus_info(hw);
7645
9a799d71 7646 /* print bus type/speed/width info */
849c4542 7647 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7648 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7649 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7650 "Unknown"),
7651 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7652 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7653 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7654 "Unknown"),
7655 netdev->dev_addr);
289700db
DS		 7656
7657 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7658 if (err)
9fe93afd 7659 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7660 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7661 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7662 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7663 part_str);
e8e26350 7664 else
289700db
DS		 7665 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7666 hw->mac.type, hw->phy.type, part_str);
9a799d71 7667
e8e26350 7668 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7669 e_dev_warn("PCI-Express bandwidth available for this card is "
7670 "not sufficient for optimal performance.\n");
7671 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7672 "is required.\n");
0c254d86
AK		 7673 }
7674
34b0368c
PWJ		 7675 /* save off EEPROM version number */
7676 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7677
9a799d71 7678 /* reset the hardware with the new settings */
794caeb2 7679 err = hw->mac.ops.start_hw(hw);
c44ade9e 7680
794caeb2
PWJ		 7681 if (err == IXGBE_ERR_EEPROM_VERSION) {
7682 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7683 e_dev_warn("This device is a pre-production adapter/LOM. "
7684 "Please be aware there may be issues associated "
7685 "with your hardware. If you are experiencing "
7686 "problems please contact your Intel or hardware "
7687 "representative who provided you with this "
7688 "hardware.\n");
794caeb2 7689 }
9a799d71
AK		 7690 strcpy(netdev->name, "eth%d");
7691 err = register_netdev(netdev);
7692 if (err)
7693 goto err_register;
7694
54386467
JB		 7695 /* carrier off reporting is important to ethtool even BEFORE open */
7696 netif_carrier_off(netdev);
7697
5dd2d332 7698#ifdef CONFIG_IXGBE_DCA
652f093f 7699 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7700 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7701 ixgbe_setup_dca(adapter);
7702 }
7703#endif
1cdd1ec8 7704 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7705 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7706 for (i = 0; i < adapter->num_vfs; i++)
7707 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7708 }
7709
9612de92
ET		 7710 /* Inform firmware of driver version */
7711 if (hw->mac.ops.set_fw_drv_ver)
a38a104d
DS		 7712 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7713 FW_CEM_UNUSED_VER);
9612de92 7714
0365e6e4
PW		 7715 /* add san mac addr to netdev */
7716 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7717
849c4542 7718 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7719 cards_found++;
7720 return 0;
7721
7722err_register:
5eba3699 7723 ixgbe_release_hw_control(adapter);
7a921c93 7724 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7725err_sw_init:
7726err_eeprom:
1cdd1ec8
GR		 7727 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7728 ixgbe_disable_sriov(adapter);
7086400d 7729 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7730 iounmap(hw->hw_addr);
7731err_ioremap:
7732 free_netdev(netdev);
7733err_alloc_etherdev:
e8e9f696
JP		 7734 pci_release_selected_regions(pdev,
7735 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7736err_pci_reg:
7737err_dma:
7738 pci_disable_device(pdev);
7739 return err;
7740}
7741
7742/**
7743 * ixgbe_remove - Device Removal Routine
7744 * @pdev: PCI device information struct
7745 *
7746 * ixgbe_remove is called by the PCI subsystem to alert the driver
7747 * that it should release a PCI device. The could be caused by a
7748 * Hot-Plug event, or because the driver is going to be removed from
7749 * memory.
7750 **/
7751static void __devexit ixgbe_remove(struct pci_dev *pdev)
7752{
c60fbb00
AD		 7753 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7754 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7755
7756 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7757 cancel_work_sync(&adapter->service_task);
9a799d71 7758
5dd2d332 7759#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7760 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7761 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7762 dca_remove_requester(&pdev->dev);
7763 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7764 }
7765
7766#endif
332d4a7d
YZ		 7767#ifdef IXGBE_FCOE
7768 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7769 ixgbe_cleanup_fcoe(adapter);
7770
7771#endif /* IXGBE_FCOE */
0365e6e4
PW		 7772
7773 /* remove the added san mac */
7774 ixgbe_del_sanmac_netdev(netdev);
7775
c4900be0
DS		 7776 if (netdev->reg_state == NETREG_REGISTERED)
7777 unregister_netdev(netdev);
9a799d71 7778
1cdd1ec8
GR		 7779 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7780 ixgbe_disable_sriov(adapter);
7781
7a921c93 7782 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7783
021230d4 7784 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7785
7786 iounmap(adapter->hw.hw_addr);
9ce77666 7787 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7788 IORESOURCE_MEM));
9a799d71 7789
849c4542 7790 e_dev_info("complete\n");
021230d4 7791
9a799d71
AK		 7792 free_netdev(netdev);
7793
19d5afd4 7794 pci_disable_pcie_error_reporting(pdev);
6fabd715 7795
9a799d71
AK		 7796 pci_disable_device(pdev);
7797}
7798
7799/**
7800 * ixgbe_io_error_detected - called when PCI error is detected
7801 * @pdev: Pointer to PCI device
7802 * @state: The current pci connection state
7803 *
7804 * This function is called after a PCI bus error affecting
7805 * this device has been detected.
7806 */
7807static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7808 pci_channel_state_t state)
9a799d71 7809{
c60fbb00
AD		 7810 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7811 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7812
7813 netif_device_detach(netdev);
7814
3044b8d1
BL		 7815 if (state == pci_channel_io_perm_failure)
7816 return PCI_ERS_RESULT_DISCONNECT;
7817
9a799d71
AK		 7818 if (netif_running(netdev))
7819 ixgbe_down(adapter);
7820 pci_disable_device(pdev);
7821
b4617240 7822 /* Request a slot reset. */
9a799d71
AK		 7823 return PCI_ERS_RESULT_NEED_RESET;
7824}
7825
7826/**
7827 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7828 * @pdev: Pointer to PCI device
7829 *
7830 * Restart the card from scratch, as if from a cold-boot.
7831 */
7832static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7833{
c60fbb00 7834 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7835 pci_ers_result_t result;
7836 int err;
9a799d71 7837
9ce77666 7838 if (pci_enable_device_mem(pdev)) {
396e799c 7839 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7840 result = PCI_ERS_RESULT_DISCONNECT;
7841 } else {
7842 pci_set_master(pdev);
7843 pci_restore_state(pdev);
c0e1f68b 7844 pci_save_state(pdev);
9a799d71 7845
dd4d8ca6 7846 pci_wake_from_d3(pdev, false);
9a799d71 7847
6fabd715 7848 ixgbe_reset(adapter);
88512539 7849 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7850 result = PCI_ERS_RESULT_RECOVERED;
7851 }
7852
7853 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7854 if (err) {
849c4542
ET		 7855 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7856 "failed 0x%0x\n", err);
6fabd715
PWJ		 7857 /* non-fatal, continue */
7858 }
9a799d71 7859
6fabd715 7860 return result;
9a799d71
AK		 7861}
7862
7863/**
7864 * ixgbe_io_resume - called when traffic can start flowing again.
7865 * @pdev: Pointer to PCI device
7866 *
7867 * This callback is called when the error recovery driver tells us that
7868 * its OK to resume normal operation.
7869 */
7870static void ixgbe_io_resume(struct pci_dev *pdev)
7871{
c60fbb00
AD		 7872 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7873 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7874
7875 if (netif_running(netdev)) {
7876 if (ixgbe_up(adapter)) {
396e799c 7877 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7878 return;
7879 }
7880 }
7881
7882 netif_device_attach(netdev);
9a799d71
AK		 7883}
7884
7885static struct pci_error_handlers ixgbe_err_handler = {
7886 .error_detected = ixgbe_io_error_detected,
7887 .slot_reset = ixgbe_io_slot_reset,
7888 .resume = ixgbe_io_resume,
7889};
7890
7891static struct pci_driver ixgbe_driver = {
7892 .name = ixgbe_driver_name,
7893 .id_table = ixgbe_pci_tbl,
7894 .probe = ixgbe_probe,
7895 .remove = __devexit_p(ixgbe_remove),
7896#ifdef CONFIG_PM
7897 .suspend = ixgbe_suspend,
7898 .resume = ixgbe_resume,
7899#endif
7900 .shutdown = ixgbe_shutdown,
7901 .err_handler = &ixgbe_err_handler
7902};
7903
7904/**
7905 * ixgbe_init_module - Driver Registration Routine
7906 *
7907 * ixgbe_init_module is the first routine called when the driver is
7908 * loaded. All it does is register with the PCI subsystem.
7909 **/
7910static int __init ixgbe_init_module(void)
7911{
7912 int ret;
c7689578 7913 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7914 pr_info("%s\n", ixgbe_copyright);
9a799d71 7915
5dd2d332 7916#ifdef CONFIG_IXGBE_DCA
bd0362dd 7917 dca_register_notify(&dca_notifier);
bd0362dd 7918#endif
5dd2d332 7919
9a799d71
AK		 7920 ret = pci_register_driver(&ixgbe_driver);
7921 return ret;
7922}
b4617240 7923
9a799d71
AK		 7924module_init(ixgbe_init_module);
7925
7926/**
7927 * ixgbe_exit_module - Driver Exit Cleanup Routine
7928 *
7929 * ixgbe_exit_module is called just before the driver is removed
7930 * from memory.
7931 **/
7932static void __exit ixgbe_exit_module(void)
7933{
5dd2d332 7934#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7935 dca_unregister_notify(&dca_notifier);
7936#endif
9a799d71 7937 pci_unregister_driver(&ixgbe_driver);
1a51502b 7938 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7939}
bd0362dd 7940
5dd2d332 7941#ifdef CONFIG_IXGBE_DCA
bd0362dd 7942static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7943 void *p)
bd0362dd
JC		 7944{
7945 int ret_val;
7946
7947 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7948 __ixgbe_notify_dca);
bd0362dd
JC		 7949
7950 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7951}
b453368d 7952
5dd2d332 7953#endif /* CONFIG_IXGBE_DCA */
849c4542 7954
9a799d71
AK		 7955module_exit(ixgbe_exit_module);
7956
7957/* ixgbe_main.c */
Linux kernel - Deliverables
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