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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
a52055e0 | 4 | Copyright(c) 1999 - 2011 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
60127865 | 37 | #include <linux/pkt_sched.h> |
9a799d71 | 38 | #include <linux/ipv6.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
9a799d71 AK |
40 | #include <net/checksum.h> |
41 | #include <net/ip6_checksum.h> | |
42 | #include <linux/ethtool.h> | |
43 | #include <linux/if_vlan.h> | |
eacd73f7 | 44 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
45 | |
46 | #include "ixgbe.h" | |
47 | #include "ixgbe_common.h" | |
ee5f784a | 48 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 49 | #include "ixgbe_sriov.h" |
9a799d71 AK |
50 | |
51 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 52 | static const char ixgbe_driver_string[] = |
e8e9f696 | 53 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
75e3d3c6 | 54 | #define MAJ 3 |
c89c7112 DS |
55 | #define MIN 3 |
56 | #define BUILD 8 | |
75e3d3c6 JK |
57 | #define KFIX 2 |
58 | #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ | |
59 | __stringify(BUILD) "-k" __stringify(KFIX) | |
9c8eb720 | 60 | const char ixgbe_driver_version[] = DRV_VERSION; |
a52055e0 DS |
61 | static const char ixgbe_copyright[] = |
62 | "Copyright (c) 1999-2011 Intel Corporation."; | |
9a799d71 AK |
63 | |
64 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 65 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 66 | [board_82599] = &ixgbe_82599_info, |
fe15e8e1 | 67 | [board_X540] = &ixgbe_X540_info, |
9a799d71 AK |
68 | }; |
69 | ||
70 | /* ixgbe_pci_tbl - PCI Device ID Table | |
71 | * | |
72 | * Wildcard entries (PCI_ANY_ID) should come last | |
73 | * Last entry must be all 0s | |
74 | * | |
75 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
76 | * Class, Class Mask, private data (not used) } | |
77 | */ | |
a3aa1884 | 78 | static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { |
1e336d0f DS |
79 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), |
80 | board_82598 }, | |
9a799d71 | 81 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), |
3957d63d | 82 | board_82598 }, |
9a799d71 | 83 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 84 | board_82598 }, |
0befdb3e JB |
85 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
86 | board_82598 }, | |
3845bec0 PWJ |
87 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), |
88 | board_82598 }, | |
9a799d71 | 89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 90 | board_82598 }, |
8d792cd9 JB |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
92 | board_82598 }, | |
c4900be0 DS |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
94 | board_82598 }, | |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
96 | board_82598 }, | |
b95f5fcb JB |
97 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
98 | board_82598 }, | |
c4900be0 DS |
99 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
100 | board_82598 }, | |
2f21bdd3 DS |
101 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), |
102 | board_82598 }, | |
e8e26350 PW |
103 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), |
104 | board_82599 }, | |
1fcf03e6 PWJ |
105 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), |
106 | board_82599 }, | |
74757d49 DS |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), |
108 | board_82599 }, | |
e8e26350 PW |
109 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), |
110 | board_82599 }, | |
38ad1c8e DS |
111 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), |
112 | board_82599 }, | |
dbfec662 DS |
113 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), |
114 | board_82599 }, | |
8911184f PWJ |
115 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), |
116 | board_82599 }, | |
dbffcb21 DS |
117 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), |
118 | board_82599 }, | |
119 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), | |
120 | board_82599 }, | |
119fc60a MC |
121 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), |
122 | board_82599 }, | |
312eb931 DS |
123 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), |
124 | board_82599 }, | |
b93a2226 | 125 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), |
d994653d | 126 | board_X540 }, |
4c40ef02 ET |
127 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), |
128 | board_82599 }, | |
9a799d71 AK |
129 | |
130 | /* required last entry */ | |
131 | {0, } | |
132 | }; | |
133 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
134 | ||
5dd2d332 | 135 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 136 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
e8e9f696 | 137 | void *p); |
bd0362dd JC |
138 | static struct notifier_block dca_notifier = { |
139 | .notifier_call = ixgbe_notify_dca, | |
140 | .next = NULL, | |
141 | .priority = 0 | |
142 | }; | |
143 | #endif | |
144 | ||
1cdd1ec8 GR |
145 | #ifdef CONFIG_PCI_IOV |
146 | static unsigned int max_vfs; | |
147 | module_param(max_vfs, uint, 0); | |
e8e9f696 JP |
148 | MODULE_PARM_DESC(max_vfs, |
149 | "Maximum number of virtual functions to allocate per physical function"); | |
1cdd1ec8 GR |
150 | #endif /* CONFIG_PCI_IOV */ |
151 | ||
9a799d71 AK |
152 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
153 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
154 | MODULE_LICENSE("GPL"); | |
155 | MODULE_VERSION(DRV_VERSION); | |
156 | ||
157 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
158 | ||
1cdd1ec8 GR |
159 | static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter) |
160 | { | |
161 | struct ixgbe_hw *hw = &adapter->hw; | |
162 | u32 gcr; | |
163 | u32 gpie; | |
164 | u32 vmdctl; | |
165 | ||
166 | #ifdef CONFIG_PCI_IOV | |
167 | /* disable iov and allow time for transactions to clear */ | |
168 | pci_disable_sriov(adapter->pdev); | |
169 | #endif | |
170 | ||
171 | /* turn off device IOV mode */ | |
172 | gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
173 | gcr &= ~(IXGBE_GCR_EXT_SRIOV); | |
174 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr); | |
175 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
176 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
177 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
178 | ||
179 | /* set default pool back to 0 */ | |
180 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
181 | vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; | |
182 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); | |
183 | ||
184 | /* take a breather then clean up driver data */ | |
185 | msleep(100); | |
e8e9f696 JP |
186 | |
187 | kfree(adapter->vfinfo); | |
1cdd1ec8 GR |
188 | adapter->vfinfo = NULL; |
189 | ||
190 | adapter->num_vfs = 0; | |
191 | adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; | |
192 | } | |
193 | ||
dcd79aeb TI |
194 | struct ixgbe_reg_info { |
195 | u32 ofs; | |
196 | char *name; | |
197 | }; | |
198 | ||
199 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
200 | ||
201 | /* General Registers */ | |
202 | {IXGBE_CTRL, "CTRL"}, | |
203 | {IXGBE_STATUS, "STATUS"}, | |
204 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
205 | ||
206 | /* Interrupt Registers */ | |
207 | {IXGBE_EICR, "EICR"}, | |
208 | ||
209 | /* RX Registers */ | |
210 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
211 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
212 | {IXGBE_RDLEN(0), "RDLEN"}, | |
213 | {IXGBE_RDH(0), "RDH"}, | |
214 | {IXGBE_RDT(0), "RDT"}, | |
215 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
216 | {IXGBE_RDBAL(0), "RDBAL"}, | |
217 | {IXGBE_RDBAH(0), "RDBAH"}, | |
218 | ||
219 | /* TX Registers */ | |
220 | {IXGBE_TDBAL(0), "TDBAL"}, | |
221 | {IXGBE_TDBAH(0), "TDBAH"}, | |
222 | {IXGBE_TDLEN(0), "TDLEN"}, | |
223 | {IXGBE_TDH(0), "TDH"}, | |
224 | {IXGBE_TDT(0), "TDT"}, | |
225 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
226 | ||
227 | /* List Terminator */ | |
228 | {} | |
229 | }; | |
230 | ||
231 | ||
232 | /* | |
233 | * ixgbe_regdump - register printout routine | |
234 | */ | |
235 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
236 | { | |
237 | int i = 0, j = 0; | |
238 | char rname[16]; | |
239 | u32 regs[64]; | |
240 | ||
241 | switch (reginfo->ofs) { | |
242 | case IXGBE_SRRCTL(0): | |
243 | for (i = 0; i < 64; i++) | |
244 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
245 | break; | |
246 | case IXGBE_DCA_RXCTRL(0): | |
247 | for (i = 0; i < 64; i++) | |
248 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
249 | break; | |
250 | case IXGBE_RDLEN(0): | |
251 | for (i = 0; i < 64; i++) | |
252 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
253 | break; | |
254 | case IXGBE_RDH(0): | |
255 | for (i = 0; i < 64; i++) | |
256 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
257 | break; | |
258 | case IXGBE_RDT(0): | |
259 | for (i = 0; i < 64; i++) | |
260 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
261 | break; | |
262 | case IXGBE_RXDCTL(0): | |
263 | for (i = 0; i < 64; i++) | |
264 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
265 | break; | |
266 | case IXGBE_RDBAL(0): | |
267 | for (i = 0; i < 64; i++) | |
268 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
269 | break; | |
270 | case IXGBE_RDBAH(0): | |
271 | for (i = 0; i < 64; i++) | |
272 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
273 | break; | |
274 | case IXGBE_TDBAL(0): | |
275 | for (i = 0; i < 64; i++) | |
276 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
277 | break; | |
278 | case IXGBE_TDBAH(0): | |
279 | for (i = 0; i < 64; i++) | |
280 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
281 | break; | |
282 | case IXGBE_TDLEN(0): | |
283 | for (i = 0; i < 64; i++) | |
284 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
285 | break; | |
286 | case IXGBE_TDH(0): | |
287 | for (i = 0; i < 64; i++) | |
288 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
289 | break; | |
290 | case IXGBE_TDT(0): | |
291 | for (i = 0; i < 64; i++) | |
292 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
293 | break; | |
294 | case IXGBE_TXDCTL(0): | |
295 | for (i = 0; i < 64; i++) | |
296 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
297 | break; | |
298 | default: | |
c7689578 | 299 | pr_info("%-15s %08x\n", reginfo->name, |
dcd79aeb TI |
300 | IXGBE_READ_REG(hw, reginfo->ofs)); |
301 | return; | |
302 | } | |
303 | ||
304 | for (i = 0; i < 8; i++) { | |
305 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); | |
c7689578 | 306 | pr_err("%-15s", rname); |
dcd79aeb | 307 | for (j = 0; j < 8; j++) |
c7689578 JP |
308 | pr_cont(" %08x", regs[i*8+j]); |
309 | pr_cont("\n"); | |
dcd79aeb TI |
310 | } |
311 | ||
312 | } | |
313 | ||
314 | /* | |
315 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
316 | */ | |
317 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
318 | { | |
319 | struct net_device *netdev = adapter->netdev; | |
320 | struct ixgbe_hw *hw = &adapter->hw; | |
321 | struct ixgbe_reg_info *reginfo; | |
322 | int n = 0; | |
323 | struct ixgbe_ring *tx_ring; | |
324 | struct ixgbe_tx_buffer *tx_buffer_info; | |
325 | union ixgbe_adv_tx_desc *tx_desc; | |
326 | struct my_u0 { u64 a; u64 b; } *u0; | |
327 | struct ixgbe_ring *rx_ring; | |
328 | union ixgbe_adv_rx_desc *rx_desc; | |
329 | struct ixgbe_rx_buffer *rx_buffer_info; | |
330 | u32 staterr; | |
331 | int i = 0; | |
332 | ||
333 | if (!netif_msg_hw(adapter)) | |
334 | return; | |
335 | ||
336 | /* Print netdevice Info */ | |
337 | if (netdev) { | |
338 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
c7689578 | 339 | pr_info("Device Name state " |
dcd79aeb | 340 | "trans_start last_rx\n"); |
c7689578 JP |
341 | pr_info("%-15s %016lX %016lX %016lX\n", |
342 | netdev->name, | |
343 | netdev->state, | |
344 | netdev->trans_start, | |
345 | netdev->last_rx); | |
dcd79aeb TI |
346 | } |
347 | ||
348 | /* Print Registers */ | |
349 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
c7689578 | 350 | pr_info(" Register Name Value\n"); |
dcd79aeb TI |
351 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; |
352 | reginfo->name; reginfo++) { | |
353 | ixgbe_regdump(hw, reginfo); | |
354 | } | |
355 | ||
356 | /* Print TX Ring Summary */ | |
357 | if (!netdev || !netif_running(netdev)) | |
358 | goto exit; | |
359 | ||
360 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
c7689578 | 361 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
dcd79aeb TI |
362 | for (n = 0; n < adapter->num_tx_queues; n++) { |
363 | tx_ring = adapter->tx_ring[n]; | |
364 | tx_buffer_info = | |
365 | &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; | |
c7689578 | 366 | pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", |
dcd79aeb TI |
367 | n, tx_ring->next_to_use, tx_ring->next_to_clean, |
368 | (u64)tx_buffer_info->dma, | |
369 | tx_buffer_info->length, | |
370 | tx_buffer_info->next_to_watch, | |
371 | (u64)tx_buffer_info->time_stamp); | |
372 | } | |
373 | ||
374 | /* Print TX Rings */ | |
375 | if (!netif_msg_tx_done(adapter)) | |
376 | goto rx_ring_summary; | |
377 | ||
378 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
379 | ||
380 | /* Transmit Descriptor Formats | |
381 | * | |
382 | * Advanced Transmit Descriptor | |
383 | * +--------------------------------------------------------------+ | |
384 | * 0 | Buffer Address [63:0] | | |
385 | * +--------------------------------------------------------------+ | |
386 | * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | | |
387 | * +--------------------------------------------------------------+ | |
388 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
389 | */ | |
390 | ||
391 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
392 | tx_ring = adapter->tx_ring[n]; | |
c7689578 JP |
393 | pr_info("------------------------------------\n"); |
394 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
395 | pr_info("------------------------------------\n"); | |
396 | pr_info("T [desc] [address 63:0 ] " | |
dcd79aeb TI |
397 | "[PlPOIdStDDt Ln] [bi->dma ] " |
398 | "leng ntw timestamp bi->skb\n"); | |
399 | ||
400 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
31f05a2d | 401 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i); |
dcd79aeb TI |
402 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
403 | u0 = (struct my_u0 *)tx_desc; | |
c7689578 | 404 | pr_info("T [0x%03X] %016llX %016llX %016llX" |
dcd79aeb TI |
405 | " %04X %3X %016llX %p", i, |
406 | le64_to_cpu(u0->a), | |
407 | le64_to_cpu(u0->b), | |
408 | (u64)tx_buffer_info->dma, | |
409 | tx_buffer_info->length, | |
410 | tx_buffer_info->next_to_watch, | |
411 | (u64)tx_buffer_info->time_stamp, | |
412 | tx_buffer_info->skb); | |
413 | if (i == tx_ring->next_to_use && | |
414 | i == tx_ring->next_to_clean) | |
c7689578 | 415 | pr_cont(" NTC/U\n"); |
dcd79aeb | 416 | else if (i == tx_ring->next_to_use) |
c7689578 | 417 | pr_cont(" NTU\n"); |
dcd79aeb | 418 | else if (i == tx_ring->next_to_clean) |
c7689578 | 419 | pr_cont(" NTC\n"); |
dcd79aeb | 420 | else |
c7689578 | 421 | pr_cont("\n"); |
dcd79aeb TI |
422 | |
423 | if (netif_msg_pktdata(adapter) && | |
424 | tx_buffer_info->dma != 0) | |
425 | print_hex_dump(KERN_INFO, "", | |
426 | DUMP_PREFIX_ADDRESS, 16, 1, | |
427 | phys_to_virt(tx_buffer_info->dma), | |
428 | tx_buffer_info->length, true); | |
429 | } | |
430 | } | |
431 | ||
432 | /* Print RX Rings Summary */ | |
433 | rx_ring_summary: | |
434 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
c7689578 | 435 | pr_info("Queue [NTU] [NTC]\n"); |
dcd79aeb TI |
436 | for (n = 0; n < adapter->num_rx_queues; n++) { |
437 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
438 | pr_info("%5d %5X %5X\n", |
439 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
dcd79aeb TI |
440 | } |
441 | ||
442 | /* Print RX Rings */ | |
443 | if (!netif_msg_rx_status(adapter)) | |
444 | goto exit; | |
445 | ||
446 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
447 | ||
448 | /* Advanced Receive Descriptor (Read) Format | |
449 | * 63 1 0 | |
450 | * +-----------------------------------------------------+ | |
451 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
452 | * +----------------------------------------------+------+ | |
453 | * 8 | Header Buffer Address [63:1] | DD | | |
454 | * +-----------------------------------------------------+ | |
455 | * | |
456 | * | |
457 | * Advanced Receive Descriptor (Write-Back) Format | |
458 | * | |
459 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
460 | * +------------------------------------------------------+ | |
461 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
462 | * | Checksum Ident | | | | Type | Type | | |
463 | * +------------------------------------------------------+ | |
464 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
465 | * +------------------------------------------------------+ | |
466 | * 63 48 47 32 31 20 19 0 | |
467 | */ | |
468 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
469 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
470 | pr_info("------------------------------------\n"); |
471 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
472 | pr_info("------------------------------------\n"); | |
473 | pr_info("R [desc] [ PktBuf A0] " | |
dcd79aeb TI |
474 | "[ HeadBuf DD] [bi->dma ] [bi->skb] " |
475 | "<-- Adv Rx Read format\n"); | |
c7689578 | 476 | pr_info("RWB[desc] [PcsmIpSHl PtRs] " |
dcd79aeb TI |
477 | "[vl er S cks ln] ---------------- [bi->skb] " |
478 | "<-- Adv Rx Write-Back format\n"); | |
479 | ||
480 | for (i = 0; i < rx_ring->count; i++) { | |
481 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
31f05a2d | 482 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i); |
dcd79aeb TI |
483 | u0 = (struct my_u0 *)rx_desc; |
484 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
485 | if (staterr & IXGBE_RXD_STAT_DD) { | |
486 | /* Descriptor Done */ | |
c7689578 | 487 | pr_info("RWB[0x%03X] %016llX " |
dcd79aeb TI |
488 | "%016llX ---------------- %p", i, |
489 | le64_to_cpu(u0->a), | |
490 | le64_to_cpu(u0->b), | |
491 | rx_buffer_info->skb); | |
492 | } else { | |
c7689578 | 493 | pr_info("R [0x%03X] %016llX " |
dcd79aeb TI |
494 | "%016llX %016llX %p", i, |
495 | le64_to_cpu(u0->a), | |
496 | le64_to_cpu(u0->b), | |
497 | (u64)rx_buffer_info->dma, | |
498 | rx_buffer_info->skb); | |
499 | ||
500 | if (netif_msg_pktdata(adapter)) { | |
501 | print_hex_dump(KERN_INFO, "", | |
502 | DUMP_PREFIX_ADDRESS, 16, 1, | |
503 | phys_to_virt(rx_buffer_info->dma), | |
504 | rx_ring->rx_buf_len, true); | |
505 | ||
506 | if (rx_ring->rx_buf_len | |
507 | < IXGBE_RXBUFFER_2048) | |
508 | print_hex_dump(KERN_INFO, "", | |
509 | DUMP_PREFIX_ADDRESS, 16, 1, | |
510 | phys_to_virt( | |
511 | rx_buffer_info->page_dma + | |
512 | rx_buffer_info->page_offset | |
513 | ), | |
514 | PAGE_SIZE/2, true); | |
515 | } | |
516 | } | |
517 | ||
518 | if (i == rx_ring->next_to_use) | |
c7689578 | 519 | pr_cont(" NTU\n"); |
dcd79aeb | 520 | else if (i == rx_ring->next_to_clean) |
c7689578 | 521 | pr_cont(" NTC\n"); |
dcd79aeb | 522 | else |
c7689578 | 523 | pr_cont("\n"); |
dcd79aeb TI |
524 | |
525 | } | |
526 | } | |
527 | ||
528 | exit: | |
529 | return; | |
530 | } | |
531 | ||
5eba3699 AV |
532 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
533 | { | |
534 | u32 ctrl_ext; | |
535 | ||
536 | /* Let firmware take over control of h/w */ | |
537 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
538 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 539 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
540 | } |
541 | ||
542 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
543 | { | |
544 | u32 ctrl_ext; | |
545 | ||
546 | /* Let firmware know the driver has taken over */ | |
547 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
548 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 549 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 550 | } |
9a799d71 | 551 | |
e8e26350 PW |
552 | /* |
553 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
554 | * @adapter: pointer to adapter struct | |
555 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
556 | * @queue: queue to map the corresponding interrupt to | |
557 | * @msix_vector: the vector to map to the corresponding queue | |
558 | * | |
559 | */ | |
560 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
e8e9f696 | 561 | u8 queue, u8 msix_vector) |
9a799d71 AK |
562 | { |
563 | u32 ivar, index; | |
e8e26350 PW |
564 | struct ixgbe_hw *hw = &adapter->hw; |
565 | switch (hw->mac.type) { | |
566 | case ixgbe_mac_82598EB: | |
567 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
568 | if (direction == -1) | |
569 | direction = 0; | |
570 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
571 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
572 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
573 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
574 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
575 | break; | |
576 | case ixgbe_mac_82599EB: | |
b93a2226 | 577 | case ixgbe_mac_X540: |
e8e26350 PW |
578 | if (direction == -1) { |
579 | /* other causes */ | |
580 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
581 | index = ((queue & 1) * 8); | |
582 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
583 | ivar &= ~(0xFF << index); | |
584 | ivar |= (msix_vector << index); | |
585 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
586 | break; | |
587 | } else { | |
588 | /* tx or rx causes */ | |
589 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
590 | index = ((16 * (queue & 1)) + (8 * direction)); | |
591 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
592 | ivar &= ~(0xFF << index); | |
593 | ivar |= (msix_vector << index); | |
594 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
595 | break; | |
596 | } | |
597 | default: | |
598 | break; | |
599 | } | |
9a799d71 AK |
600 | } |
601 | ||
fe49f04a | 602 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
e8e9f696 | 603 | u64 qmask) |
fe49f04a AD |
604 | { |
605 | u32 mask; | |
606 | ||
bd508178 AD |
607 | switch (adapter->hw.mac.type) { |
608 | case ixgbe_mac_82598EB: | |
fe49f04a AD |
609 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
610 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
bd508178 AD |
611 | break; |
612 | case ixgbe_mac_82599EB: | |
b93a2226 | 613 | case ixgbe_mac_X540: |
fe49f04a AD |
614 | mask = (qmask & 0xFFFFFFFF); |
615 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
616 | mask = (qmask >> 32); | |
617 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
bd508178 AD |
618 | break; |
619 | default: | |
620 | break; | |
fe49f04a AD |
621 | } |
622 | } | |
623 | ||
b6ec895e AD |
624 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring, |
625 | struct ixgbe_tx_buffer *tx_buffer_info) | |
9a799d71 | 626 | { |
e5a43549 AD |
627 | if (tx_buffer_info->dma) { |
628 | if (tx_buffer_info->mapped_as_page) | |
b6ec895e | 629 | dma_unmap_page(tx_ring->dev, |
e5a43549 AD |
630 | tx_buffer_info->dma, |
631 | tx_buffer_info->length, | |
1b507730 | 632 | DMA_TO_DEVICE); |
e5a43549 | 633 | else |
b6ec895e | 634 | dma_unmap_single(tx_ring->dev, |
e5a43549 AD |
635 | tx_buffer_info->dma, |
636 | tx_buffer_info->length, | |
1b507730 | 637 | DMA_TO_DEVICE); |
e5a43549 AD |
638 | tx_buffer_info->dma = 0; |
639 | } | |
9a799d71 AK |
640 | if (tx_buffer_info->skb) { |
641 | dev_kfree_skb_any(tx_buffer_info->skb); | |
642 | tx_buffer_info->skb = NULL; | |
643 | } | |
44df32c5 | 644 | tx_buffer_info->time_stamp = 0; |
9a799d71 AK |
645 | /* tx_buffer_info must be completely set up in the transmit path */ |
646 | } | |
647 | ||
26f23d82 | 648 | /** |
c84d324c JF |
649 | * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class |
650 | * @adapter: driver private struct | |
651 | * @index: reg idx of queue to query (0-127) | |
26f23d82 | 652 | * |
25985edc | 653 | * Helper function to determine the traffic index for a particular |
c84d324c | 654 | * register index. |
26f23d82 | 655 | * |
c84d324c | 656 | * Returns : a tc index for use in range 0-7, or 0-3 |
26f23d82 | 657 | */ |
3b2ee943 | 658 | static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx) |
26f23d82 | 659 | { |
c84d324c | 660 | int tc = -1; |
e5b64635 | 661 | int dcb_i = netdev_get_num_tc(adapter->netdev); |
26f23d82 | 662 | |
c84d324c JF |
663 | /* if DCB is not enabled the queues have no TC */ |
664 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) | |
665 | return tc; | |
26f23d82 | 666 | |
c84d324c JF |
667 | /* check valid range */ |
668 | if (reg_idx >= adapter->hw.mac.max_tx_queues) | |
669 | return tc; | |
670 | ||
671 | switch (adapter->hw.mac.type) { | |
672 | case ixgbe_mac_82598EB: | |
673 | tc = reg_idx >> 2; | |
674 | break; | |
675 | default: | |
676 | if (dcb_i != 4 && dcb_i != 8) | |
6837e895 | 677 | break; |
c84d324c JF |
678 | |
679 | /* if VMDq is enabled the lowest order bits determine TC */ | |
680 | if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED | | |
681 | IXGBE_FLAG_VMDQ_ENABLED)) { | |
682 | tc = reg_idx & (dcb_i - 1); | |
683 | break; | |
684 | } | |
685 | ||
686 | /* | |
687 | * Convert the reg_idx into the correct TC. This bitmask | |
688 | * targets the last full 32 ring traffic class and assigns | |
689 | * it a value of 1. From there the rest of the rings are | |
690 | * based on shifting the mask further up to include the | |
691 | * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i | |
692 | * will only ever be 8 or 4 and that reg_idx will never | |
693 | * be greater then 128. The code without the power of 2 | |
694 | * optimizations would be: | |
695 | * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32) | |
696 | */ | |
697 | tc = ((reg_idx & 0X1F) + 0x20) * dcb_i; | |
698 | tc >>= 9 - (reg_idx >> 5); | |
699 | } | |
700 | ||
701 | return tc; | |
702 | } | |
703 | ||
704 | static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) | |
705 | { | |
706 | struct ixgbe_hw *hw = &adapter->hw; | |
707 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
708 | u32 data = 0; | |
709 | u32 xoff[8] = {0}; | |
710 | int i; | |
711 | ||
712 | if ((hw->fc.current_mode == ixgbe_fc_full) || | |
713 | (hw->fc.current_mode == ixgbe_fc_rx_pause)) { | |
714 | switch (hw->mac.type) { | |
715 | case ixgbe_mac_82598EB: | |
716 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
6837e895 PW |
717 | break; |
718 | default: | |
c84d324c JF |
719 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); |
720 | } | |
721 | hwstats->lxoffrxc += data; | |
722 | ||
723 | /* refill credits (no tx hang) if we received xoff */ | |
724 | if (!data) | |
725 | return; | |
726 | ||
727 | for (i = 0; i < adapter->num_tx_queues; i++) | |
728 | clear_bit(__IXGBE_HANG_CHECK_ARMED, | |
729 | &adapter->tx_ring[i]->state); | |
730 | return; | |
731 | } else if (!(adapter->dcb_cfg.pfc_mode_enable)) | |
732 | return; | |
733 | ||
734 | /* update stats for each tc, only valid with PFC enabled */ | |
735 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
736 | switch (hw->mac.type) { | |
737 | case ixgbe_mac_82598EB: | |
738 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); | |
bd508178 | 739 | break; |
c84d324c JF |
740 | default: |
741 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); | |
26f23d82 | 742 | } |
c84d324c JF |
743 | hwstats->pxoffrxc[i] += xoff[i]; |
744 | } | |
745 | ||
746 | /* disarm tx queues that have received xoff frames */ | |
747 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
748 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
749 | u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx); | |
750 | ||
751 | if (xoff[tc]) | |
752 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
26f23d82 | 753 | } |
26f23d82 YZ |
754 | } |
755 | ||
c84d324c | 756 | static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) |
9a799d71 | 757 | { |
c84d324c JF |
758 | return ring->tx_stats.completed; |
759 | } | |
760 | ||
761 | static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) | |
762 | { | |
763 | struct ixgbe_adapter *adapter = netdev_priv(ring->netdev); | |
e01c31a5 | 764 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 765 | |
c84d324c JF |
766 | u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); |
767 | u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); | |
768 | ||
769 | if (head != tail) | |
770 | return (head < tail) ? | |
771 | tail - head : (tail + ring->count - head); | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
776 | static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) | |
777 | { | |
778 | u32 tx_done = ixgbe_get_tx_completed(tx_ring); | |
779 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
780 | u32 tx_pending = ixgbe_get_tx_pending(tx_ring); | |
781 | bool ret = false; | |
782 | ||
7d637bcc | 783 | clear_check_for_tx_hang(tx_ring); |
c84d324c JF |
784 | |
785 | /* | |
786 | * Check for a hung queue, but be thorough. This verifies | |
787 | * that a transmit has been completed since the previous | |
788 | * check AND there is at least one packet pending. The | |
789 | * ARMED bit is set to indicate a potential hang. The | |
790 | * bit is cleared if a pause frame is received to remove | |
791 | * false hang detection due to PFC or 802.3x frames. By | |
792 | * requiring this to fail twice we avoid races with | |
793 | * pfc clearing the ARMED bit and conditions where we | |
794 | * run the check_tx_hang logic with a transmit completion | |
795 | * pending but without time to complete it yet. | |
796 | */ | |
797 | if ((tx_done_old == tx_done) && tx_pending) { | |
798 | /* make sure it is true for two checks in a row */ | |
799 | ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, | |
800 | &tx_ring->state); | |
801 | } else { | |
802 | /* update completed stats and continue */ | |
803 | tx_ring->tx_stats.tx_done_old = tx_done; | |
804 | /* reset the countdown */ | |
805 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
9a799d71 AK |
806 | } |
807 | ||
c84d324c | 808 | return ret; |
9a799d71 AK |
809 | } |
810 | ||
b4617240 PW |
811 | #define IXGBE_MAX_TXD_PWR 14 |
812 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
813 | |
814 | /* Tx Descriptors needed, worst case */ | |
815 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
816 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
817 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 818 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 819 | |
e01c31a5 JB |
820 | static void ixgbe_tx_timeout(struct net_device *netdev); |
821 | ||
9a799d71 AK |
822 | /** |
823 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 824 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 825 | * @tx_ring: tx ring to clean |
9a799d71 | 826 | **/ |
fe49f04a | 827 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 828 | struct ixgbe_ring *tx_ring) |
9a799d71 | 829 | { |
fe49f04a | 830 | struct ixgbe_adapter *adapter = q_vector->adapter; |
12207e49 PWJ |
831 | union ixgbe_adv_tx_desc *tx_desc, *eop_desc; |
832 | struct ixgbe_tx_buffer *tx_buffer_info; | |
e01c31a5 | 833 | unsigned int total_bytes = 0, total_packets = 0; |
b953799e | 834 | u16 i, eop, count = 0; |
9a799d71 AK |
835 | |
836 | i = tx_ring->next_to_clean; | |
12207e49 | 837 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
31f05a2d | 838 | eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop); |
12207e49 PWJ |
839 | |
840 | while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && | |
9a1a69ad | 841 | (count < tx_ring->work_limit)) { |
12207e49 | 842 | bool cleaned = false; |
2d0bb1c1 | 843 | rmb(); /* read buffer_info after eop_desc */ |
12207e49 | 844 | for ( ; !cleaned; count++) { |
31f05a2d | 845 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i); |
9a799d71 | 846 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
8ad494b0 AD |
847 | |
848 | tx_desc->wb.status = 0; | |
12207e49 | 849 | cleaned = (i == eop); |
9a799d71 | 850 | |
8ad494b0 AD |
851 | i++; |
852 | if (i == tx_ring->count) | |
853 | i = 0; | |
e01c31a5 | 854 | |
8ad494b0 AD |
855 | if (cleaned && tx_buffer_info->skb) { |
856 | total_bytes += tx_buffer_info->bytecount; | |
857 | total_packets += tx_buffer_info->gso_segs; | |
e092be60 | 858 | } |
e01c31a5 | 859 | |
b6ec895e | 860 | ixgbe_unmap_and_free_tx_resource(tx_ring, |
e8e9f696 | 861 | tx_buffer_info); |
e01c31a5 | 862 | } |
12207e49 | 863 | |
c84d324c | 864 | tx_ring->tx_stats.completed++; |
12207e49 | 865 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
31f05a2d | 866 | eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop); |
12207e49 PWJ |
867 | } |
868 | ||
9a799d71 | 869 | tx_ring->next_to_clean = i; |
b953799e AD |
870 | tx_ring->total_bytes += total_bytes; |
871 | tx_ring->total_packets += total_packets; | |
872 | u64_stats_update_begin(&tx_ring->syncp); | |
873 | tx_ring->stats.packets += total_packets; | |
874 | tx_ring->stats.bytes += total_bytes; | |
875 | u64_stats_update_end(&tx_ring->syncp); | |
876 | ||
c84d324c JF |
877 | if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { |
878 | /* schedule immediate reset if we believe we hung */ | |
879 | struct ixgbe_hw *hw = &adapter->hw; | |
880 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop); | |
881 | e_err(drv, "Detected Tx Unit Hang\n" | |
882 | " Tx Queue <%d>\n" | |
883 | " TDH, TDT <%x>, <%x>\n" | |
884 | " next_to_use <%x>\n" | |
885 | " next_to_clean <%x>\n" | |
886 | "tx_buffer_info[next_to_clean]\n" | |
887 | " time_stamp <%lx>\n" | |
888 | " jiffies <%lx>\n", | |
889 | tx_ring->queue_index, | |
890 | IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), | |
891 | IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), | |
892 | tx_ring->next_to_use, eop, | |
893 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
894 | ||
895 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
896 | ||
897 | e_info(probe, | |
898 | "tx hang %d detected on queue %d, resetting adapter\n", | |
899 | adapter->tx_timeout_count + 1, tx_ring->queue_index); | |
900 | ||
b953799e | 901 | /* schedule immediate reset if we believe we hung */ |
b953799e AD |
902 | ixgbe_tx_timeout(adapter->netdev); |
903 | ||
904 | /* the adapter is about to reset, no point in enabling stuff */ | |
905 | return true; | |
906 | } | |
9a799d71 | 907 | |
e092be60 | 908 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
fc77dc3c | 909 | if (unlikely(count && netif_carrier_ok(tx_ring->netdev) && |
e8e9f696 | 910 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { |
e092be60 AV |
911 | /* Make sure that anybody stopping the queue after this |
912 | * sees the new next_to_clean. | |
913 | */ | |
914 | smp_mb(); | |
fc77dc3c | 915 | if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) && |
30eba97a | 916 | !test_bit(__IXGBE_DOWN, &adapter->state)) { |
fc77dc3c | 917 | netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 918 | ++tx_ring->tx_stats.restart_queue; |
30eba97a | 919 | } |
e092be60 | 920 | } |
9a799d71 | 921 | |
807540ba | 922 | return count < tx_ring->work_limit; |
9a799d71 AK |
923 | } |
924 | ||
5dd2d332 | 925 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 926 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
33cf09c9 AD |
927 | struct ixgbe_ring *rx_ring, |
928 | int cpu) | |
bd0362dd | 929 | { |
33cf09c9 | 930 | struct ixgbe_hw *hw = &adapter->hw; |
bd0362dd | 931 | u32 rxctrl; |
33cf09c9 AD |
932 | u8 reg_idx = rx_ring->reg_idx; |
933 | ||
934 | rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx)); | |
935 | switch (hw->mac.type) { | |
936 | case ixgbe_mac_82598EB: | |
937 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
938 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
939 | break; | |
940 | case ixgbe_mac_82599EB: | |
b93a2226 | 941 | case ixgbe_mac_X540: |
33cf09c9 AD |
942 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; |
943 | rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
944 | IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); | |
945 | break; | |
946 | default: | |
947 | break; | |
bd0362dd | 948 | } |
33cf09c9 AD |
949 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
950 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
951 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); | |
33cf09c9 | 952 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); |
bd0362dd JC |
953 | } |
954 | ||
955 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
33cf09c9 AD |
956 | struct ixgbe_ring *tx_ring, |
957 | int cpu) | |
bd0362dd | 958 | { |
33cf09c9 | 959 | struct ixgbe_hw *hw = &adapter->hw; |
bd0362dd | 960 | u32 txctrl; |
33cf09c9 AD |
961 | u8 reg_idx = tx_ring->reg_idx; |
962 | ||
963 | switch (hw->mac.type) { | |
964 | case ixgbe_mac_82598EB: | |
965 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx)); | |
966 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; | |
967 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
968 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
33cf09c9 AD |
969 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl); |
970 | break; | |
971 | case ixgbe_mac_82599EB: | |
b93a2226 | 972 | case ixgbe_mac_X540: |
33cf09c9 AD |
973 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx)); |
974 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; | |
975 | txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
976 | IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); | |
977 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
33cf09c9 AD |
978 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl); |
979 | break; | |
980 | default: | |
981 | break; | |
982 | } | |
983 | } | |
984 | ||
985 | static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) | |
986 | { | |
987 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
bd0362dd | 988 | int cpu = get_cpu(); |
33cf09c9 AD |
989 | long r_idx; |
990 | int i; | |
bd0362dd | 991 | |
33cf09c9 AD |
992 | if (q_vector->cpu == cpu) |
993 | goto out_no_update; | |
994 | ||
995 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
996 | for (i = 0; i < q_vector->txr_count; i++) { | |
997 | ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu); | |
998 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
999 | r_idx + 1); | |
bd0362dd | 1000 | } |
33cf09c9 AD |
1001 | |
1002 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1003 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1004 | ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu); | |
1005 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1006 | r_idx + 1); | |
1007 | } | |
1008 | ||
1009 | q_vector->cpu = cpu; | |
1010 | out_no_update: | |
bd0362dd JC |
1011 | put_cpu(); |
1012 | } | |
1013 | ||
1014 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
1015 | { | |
33cf09c9 | 1016 | int num_q_vectors; |
bd0362dd JC |
1017 | int i; |
1018 | ||
1019 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
1020 | return; | |
1021 | ||
e35ec126 AD |
1022 | /* always use CB2 mode, difference is masked in the CB driver */ |
1023 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
1024 | ||
33cf09c9 AD |
1025 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
1026 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1027 | else | |
1028 | num_q_vectors = 1; | |
1029 | ||
1030 | for (i = 0; i < num_q_vectors; i++) { | |
1031 | adapter->q_vector[i]->cpu = -1; | |
1032 | ixgbe_update_dca(adapter->q_vector[i]); | |
bd0362dd JC |
1033 | } |
1034 | } | |
1035 | ||
1036 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
1037 | { | |
c60fbb00 | 1038 | struct ixgbe_adapter *adapter = dev_get_drvdata(dev); |
bd0362dd JC |
1039 | unsigned long event = *(unsigned long *)data; |
1040 | ||
33cf09c9 AD |
1041 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) |
1042 | return 0; | |
1043 | ||
bd0362dd JC |
1044 | switch (event) { |
1045 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
1046 | /* if we're already enabled, don't do it again */ |
1047 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1048 | break; | |
652f093f | 1049 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 1050 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
1051 | ixgbe_setup_dca(adapter); |
1052 | break; | |
1053 | } | |
1054 | /* Fall Through since DCA is disabled. */ | |
1055 | case DCA_PROVIDER_REMOVE: | |
1056 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
1057 | dca_remove_requester(dev); | |
1058 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
1059 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
1060 | } | |
1061 | break; | |
1062 | } | |
1063 | ||
652f093f | 1064 | return 0; |
bd0362dd JC |
1065 | } |
1066 | ||
5dd2d332 | 1067 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
1068 | /** |
1069 | * ixgbe_receive_skb - Send a completed packet up the stack | |
1070 | * @adapter: board private structure | |
1071 | * @skb: packet to send up | |
177db6ff MC |
1072 | * @status: hardware indication of status of receive |
1073 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
1074 | * @rx_desc: rx descriptor | |
9a799d71 | 1075 | **/ |
78b6f4ce | 1076 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
e8e9f696 JP |
1077 | struct sk_buff *skb, u8 status, |
1078 | struct ixgbe_ring *ring, | |
1079 | union ixgbe_adv_rx_desc *rx_desc) | |
9a799d71 | 1080 | { |
78b6f4ce HX |
1081 | struct ixgbe_adapter *adapter = q_vector->adapter; |
1082 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
1083 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
1084 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 1085 | |
f62bbb5e JG |
1086 | if (is_vlan && (tag & VLAN_VID_MASK)) |
1087 | __vlan_hwaccel_put_tag(skb, tag); | |
1088 | ||
1089 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) | |
1090 | napi_gro_receive(napi, skb); | |
1091 | else | |
1092 | netif_rx(skb); | |
9a799d71 AK |
1093 | } |
1094 | ||
e59bd25d AV |
1095 | /** |
1096 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
1097 | * @adapter: address of board private structure | |
1098 | * @status_err: hardware indication of status of receive | |
1099 | * @skb: skb currently being received and modified | |
1100 | **/ | |
9a799d71 | 1101 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
8bae1b2b DS |
1102 | union ixgbe_adv_rx_desc *rx_desc, |
1103 | struct sk_buff *skb) | |
9a799d71 | 1104 | { |
8bae1b2b DS |
1105 | u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error); |
1106 | ||
bc8acf2c | 1107 | skb_checksum_none_assert(skb); |
9a799d71 | 1108 | |
712744be JB |
1109 | /* Rx csum disabled */ |
1110 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 1111 | return; |
e59bd25d AV |
1112 | |
1113 | /* if IP and error */ | |
1114 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
1115 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
1116 | adapter->hw_csum_rx_error++; |
1117 | return; | |
1118 | } | |
e59bd25d AV |
1119 | |
1120 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
1121 | return; | |
1122 | ||
1123 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
8bae1b2b DS |
1124 | u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
1125 | ||
1126 | /* | |
1127 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
1128 | * checksum errors. | |
1129 | */ | |
1130 | if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) && | |
1131 | (adapter->hw.mac.type == ixgbe_mac_82599EB)) | |
1132 | return; | |
1133 | ||
e59bd25d AV |
1134 | adapter->hw_csum_rx_error++; |
1135 | return; | |
1136 | } | |
1137 | ||
9a799d71 | 1138 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 1139 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
1140 | } |
1141 | ||
84ea2591 | 1142 | static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val) |
e8e26350 PW |
1143 | { |
1144 | /* | |
1145 | * Force memory writes to complete before letting h/w | |
1146 | * know there are new descriptors to fetch. (Only | |
1147 | * applicable for weak-ordered memory model archs, | |
1148 | * such as IA-64). | |
1149 | */ | |
1150 | wmb(); | |
84ea2591 | 1151 | writel(val, rx_ring->tail); |
e8e26350 PW |
1152 | } |
1153 | ||
9a799d71 AK |
1154 | /** |
1155 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
fc77dc3c AD |
1156 | * @rx_ring: ring to place buffers on |
1157 | * @cleaned_count: number of buffers to replace | |
9a799d71 | 1158 | **/ |
fc77dc3c | 1159 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) |
9a799d71 | 1160 | { |
9a799d71 | 1161 | union ixgbe_adv_rx_desc *rx_desc; |
3a581073 | 1162 | struct ixgbe_rx_buffer *bi; |
d5f398ed AD |
1163 | struct sk_buff *skb; |
1164 | u16 i = rx_ring->next_to_use; | |
9a799d71 | 1165 | |
fc77dc3c AD |
1166 | /* do nothing if no valid netdev defined */ |
1167 | if (!rx_ring->netdev) | |
1168 | return; | |
1169 | ||
9a799d71 | 1170 | while (cleaned_count--) { |
31f05a2d | 1171 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i); |
d5f398ed AD |
1172 | bi = &rx_ring->rx_buffer_info[i]; |
1173 | skb = bi->skb; | |
9a799d71 | 1174 | |
d5f398ed | 1175 | if (!skb) { |
fc77dc3c | 1176 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, |
d5f398ed | 1177 | rx_ring->rx_buf_len); |
9a799d71 | 1178 | if (!skb) { |
5b7da515 | 1179 | rx_ring->rx_stats.alloc_rx_buff_failed++; |
9a799d71 AK |
1180 | goto no_buffers; |
1181 | } | |
d716a7d8 AD |
1182 | /* initialize queue mapping */ |
1183 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
d5f398ed | 1184 | bi->skb = skb; |
d716a7d8 | 1185 | } |
9a799d71 | 1186 | |
d716a7d8 | 1187 | if (!bi->dma) { |
b6ec895e | 1188 | bi->dma = dma_map_single(rx_ring->dev, |
d5f398ed | 1189 | skb->data, |
e8e9f696 | 1190 | rx_ring->rx_buf_len, |
1b507730 | 1191 | DMA_FROM_DEVICE); |
b6ec895e | 1192 | if (dma_mapping_error(rx_ring->dev, bi->dma)) { |
5b7da515 | 1193 | rx_ring->rx_stats.alloc_rx_buff_failed++; |
d5f398ed AD |
1194 | bi->dma = 0; |
1195 | goto no_buffers; | |
1196 | } | |
9a799d71 | 1197 | } |
d5f398ed | 1198 | |
7d637bcc | 1199 | if (ring_is_ps_enabled(rx_ring)) { |
d5f398ed | 1200 | if (!bi->page) { |
fc77dc3c | 1201 | bi->page = netdev_alloc_page(rx_ring->netdev); |
d5f398ed | 1202 | if (!bi->page) { |
5b7da515 | 1203 | rx_ring->rx_stats.alloc_rx_page_failed++; |
d5f398ed AD |
1204 | goto no_buffers; |
1205 | } | |
1206 | } | |
1207 | ||
1208 | if (!bi->page_dma) { | |
1209 | /* use a half page if we're re-using */ | |
1210 | bi->page_offset ^= PAGE_SIZE / 2; | |
b6ec895e | 1211 | bi->page_dma = dma_map_page(rx_ring->dev, |
d5f398ed AD |
1212 | bi->page, |
1213 | bi->page_offset, | |
1214 | PAGE_SIZE / 2, | |
1215 | DMA_FROM_DEVICE); | |
b6ec895e | 1216 | if (dma_mapping_error(rx_ring->dev, |
d5f398ed | 1217 | bi->page_dma)) { |
5b7da515 | 1218 | rx_ring->rx_stats.alloc_rx_page_failed++; |
d5f398ed AD |
1219 | bi->page_dma = 0; |
1220 | goto no_buffers; | |
1221 | } | |
1222 | } | |
1223 | ||
1224 | /* Refresh the desc even if buffer_addrs didn't change | |
1225 | * because each write-back erases this info. */ | |
3a581073 JB |
1226 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
1227 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 1228 | } else { |
3a581073 | 1229 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
84418e3b | 1230 | rx_desc->read.hdr_addr = 0; |
9a799d71 AK |
1231 | } |
1232 | ||
1233 | i++; | |
1234 | if (i == rx_ring->count) | |
1235 | i = 0; | |
9a799d71 | 1236 | } |
7c6e0a43 | 1237 | |
9a799d71 AK |
1238 | no_buffers: |
1239 | if (rx_ring->next_to_use != i) { | |
1240 | rx_ring->next_to_use = i; | |
84ea2591 | 1241 | ixgbe_release_rx_desc(rx_ring, i); |
9a799d71 AK |
1242 | } |
1243 | } | |
1244 | ||
c267fc16 | 1245 | static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc) |
7c6e0a43 | 1246 | { |
c267fc16 AD |
1247 | /* HW will not DMA in data larger than the given buffer, even if it |
1248 | * parses the (NFS, of course) header to be larger. In that case, it | |
1249 | * fills the header buffer and spills the rest into the page. | |
1250 | */ | |
1251 | u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info); | |
1252 | u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
1253 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; | |
1254 | if (hlen > IXGBE_RX_HDR_SIZE) | |
1255 | hlen = IXGBE_RX_HDR_SIZE; | |
1256 | return hlen; | |
7c6e0a43 JB |
1257 | } |
1258 | ||
f8212f97 AD |
1259 | /** |
1260 | * ixgbe_transform_rsc_queue - change rsc queue into a full packet | |
1261 | * @skb: pointer to the last skb in the rsc queue | |
1262 | * | |
1263 | * This function changes a queue full of hw rsc buffers into a completed | |
1264 | * packet. It uses the ->prev pointers to find the first packet and then | |
1265 | * turns it into the frag list owner. | |
1266 | **/ | |
aa80175a | 1267 | static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb) |
f8212f97 AD |
1268 | { |
1269 | unsigned int frag_list_size = 0; | |
aa80175a | 1270 | unsigned int skb_cnt = 1; |
f8212f97 AD |
1271 | |
1272 | while (skb->prev) { | |
1273 | struct sk_buff *prev = skb->prev; | |
1274 | frag_list_size += skb->len; | |
1275 | skb->prev = NULL; | |
1276 | skb = prev; | |
aa80175a | 1277 | skb_cnt++; |
f8212f97 AD |
1278 | } |
1279 | ||
1280 | skb_shinfo(skb)->frag_list = skb->next; | |
1281 | skb->next = NULL; | |
1282 | skb->len += frag_list_size; | |
1283 | skb->data_len += frag_list_size; | |
1284 | skb->truesize += frag_list_size; | |
aa80175a AD |
1285 | IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt; |
1286 | ||
f8212f97 AD |
1287 | return skb; |
1288 | } | |
1289 | ||
aa80175a AD |
1290 | static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc) |
1291 | { | |
1292 | return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) & | |
1293 | IXGBE_RXDADV_RSCCNT_MASK); | |
1294 | } | |
43634e82 | 1295 | |
c267fc16 | 1296 | static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 JP |
1297 | struct ixgbe_ring *rx_ring, |
1298 | int *work_done, int work_to_do) | |
9a799d71 | 1299 | { |
78b6f4ce | 1300 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a799d71 AK |
1301 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; |
1302 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
1303 | struct sk_buff *skb; | |
d2f4fbe2 | 1304 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
c267fc16 | 1305 | const int current_node = numa_node_id(); |
3d8fd385 YZ |
1306 | #ifdef IXGBE_FCOE |
1307 | int ddp_bytes = 0; | |
1308 | #endif /* IXGBE_FCOE */ | |
c267fc16 AD |
1309 | u32 staterr; |
1310 | u16 i; | |
1311 | u16 cleaned_count = 0; | |
aa80175a | 1312 | bool pkt_is_rsc = false; |
9a799d71 AK |
1313 | |
1314 | i = rx_ring->next_to_clean; | |
31f05a2d | 1315 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i); |
9a799d71 | 1316 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
9a799d71 AK |
1317 | |
1318 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 1319 | u32 upper_len = 0; |
9a799d71 | 1320 | |
3c945e5b | 1321 | rmb(); /* read descriptor and rx_buffer_info after status DD */ |
9a799d71 | 1322 | |
c267fc16 AD |
1323 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; |
1324 | ||
9a799d71 | 1325 | skb = rx_buffer_info->skb; |
9a799d71 | 1326 | rx_buffer_info->skb = NULL; |
c267fc16 | 1327 | prefetch(skb->data); |
9a799d71 | 1328 | |
c267fc16 | 1329 | if (ring_is_rsc_enabled(rx_ring)) |
aa80175a | 1330 | pkt_is_rsc = ixgbe_get_rsc_state(rx_desc); |
c267fc16 AD |
1331 | |
1332 | /* if this is a skb from previous receive DMA will be 0 */ | |
21fa4e66 | 1333 | if (rx_buffer_info->dma) { |
c267fc16 | 1334 | u16 hlen; |
aa80175a | 1335 | if (pkt_is_rsc && |
c267fc16 AD |
1336 | !(staterr & IXGBE_RXD_STAT_EOP) && |
1337 | !skb->prev) { | |
43634e82 MC |
1338 | /* |
1339 | * When HWRSC is enabled, delay unmapping | |
1340 | * of the first packet. It carries the | |
1341 | * header information, HW may still | |
1342 | * access the header after the writeback. | |
1343 | * Only unmap it when EOP is reached | |
1344 | */ | |
e8171aaa | 1345 | IXGBE_RSC_CB(skb)->delay_unmap = true; |
43634e82 | 1346 | IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma; |
e8171aaa | 1347 | } else { |
b6ec895e | 1348 | dma_unmap_single(rx_ring->dev, |
e8e9f696 JP |
1349 | rx_buffer_info->dma, |
1350 | rx_ring->rx_buf_len, | |
1351 | DMA_FROM_DEVICE); | |
e8171aaa | 1352 | } |
4f57ca6e | 1353 | rx_buffer_info->dma = 0; |
c267fc16 AD |
1354 | |
1355 | if (ring_is_ps_enabled(rx_ring)) { | |
1356 | hlen = ixgbe_get_hlen(rx_desc); | |
1357 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
1358 | } else { | |
1359 | hlen = le16_to_cpu(rx_desc->wb.upper.length); | |
1360 | } | |
1361 | ||
1362 | skb_put(skb, hlen); | |
1363 | } else { | |
1364 | /* assume packet split since header is unmapped */ | |
1365 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
9a799d71 AK |
1366 | } |
1367 | ||
1368 | if (upper_len) { | |
b6ec895e AD |
1369 | dma_unmap_page(rx_ring->dev, |
1370 | rx_buffer_info->page_dma, | |
1371 | PAGE_SIZE / 2, | |
1372 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1373 | rx_buffer_info->page_dma = 0; |
1374 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
e8e9f696 JP |
1375 | rx_buffer_info->page, |
1376 | rx_buffer_info->page_offset, | |
1377 | upper_len); | |
762f4c57 | 1378 | |
c267fc16 AD |
1379 | if ((page_count(rx_buffer_info->page) == 1) && |
1380 | (page_to_nid(rx_buffer_info->page) == current_node)) | |
762f4c57 | 1381 | get_page(rx_buffer_info->page); |
c267fc16 AD |
1382 | else |
1383 | rx_buffer_info->page = NULL; | |
9a799d71 AK |
1384 | |
1385 | skb->len += upper_len; | |
1386 | skb->data_len += upper_len; | |
1387 | skb->truesize += upper_len; | |
1388 | } | |
1389 | ||
1390 | i++; | |
1391 | if (i == rx_ring->count) | |
1392 | i = 0; | |
9a799d71 | 1393 | |
31f05a2d | 1394 | next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i); |
9a799d71 | 1395 | prefetch(next_rxd); |
9a799d71 | 1396 | cleaned_count++; |
f8212f97 | 1397 | |
aa80175a | 1398 | if (pkt_is_rsc) { |
f8212f97 AD |
1399 | u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >> |
1400 | IXGBE_RXDADV_NEXTP_SHIFT; | |
1401 | next_buffer = &rx_ring->rx_buffer_info[nextp]; | |
f8212f97 AD |
1402 | } else { |
1403 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
1404 | } | |
1405 | ||
c267fc16 | 1406 | if (!(staterr & IXGBE_RXD_STAT_EOP)) { |
7d637bcc | 1407 | if (ring_is_ps_enabled(rx_ring)) { |
f8212f97 AD |
1408 | rx_buffer_info->skb = next_buffer->skb; |
1409 | rx_buffer_info->dma = next_buffer->dma; | |
1410 | next_buffer->skb = skb; | |
1411 | next_buffer->dma = 0; | |
1412 | } else { | |
1413 | skb->next = next_buffer->skb; | |
1414 | skb->next->prev = skb; | |
1415 | } | |
5b7da515 | 1416 | rx_ring->rx_stats.non_eop_descs++; |
9a799d71 AK |
1417 | goto next_desc; |
1418 | } | |
1419 | ||
aa80175a AD |
1420 | if (skb->prev) { |
1421 | skb = ixgbe_transform_rsc_queue(skb); | |
1422 | /* if we got here without RSC the packet is invalid */ | |
1423 | if (!pkt_is_rsc) { | |
1424 | __pskb_trim(skb, 0); | |
1425 | rx_buffer_info->skb = skb; | |
1426 | goto next_desc; | |
1427 | } | |
1428 | } | |
c267fc16 AD |
1429 | |
1430 | if (ring_is_rsc_enabled(rx_ring)) { | |
1431 | if (IXGBE_RSC_CB(skb)->delay_unmap) { | |
1432 | dma_unmap_single(rx_ring->dev, | |
1433 | IXGBE_RSC_CB(skb)->dma, | |
1434 | rx_ring->rx_buf_len, | |
1435 | DMA_FROM_DEVICE); | |
1436 | IXGBE_RSC_CB(skb)->dma = 0; | |
1437 | IXGBE_RSC_CB(skb)->delay_unmap = false; | |
1438 | } | |
aa80175a AD |
1439 | } |
1440 | if (pkt_is_rsc) { | |
c267fc16 AD |
1441 | if (ring_is_ps_enabled(rx_ring)) |
1442 | rx_ring->rx_stats.rsc_count += | |
aa80175a | 1443 | skb_shinfo(skb)->nr_frags; |
c267fc16 | 1444 | else |
aa80175a AD |
1445 | rx_ring->rx_stats.rsc_count += |
1446 | IXGBE_RSC_CB(skb)->skb_cnt; | |
c267fc16 AD |
1447 | rx_ring->rx_stats.rsc_flush++; |
1448 | } | |
1449 | ||
1450 | /* ERR_MASK will only have valid bits if EOP set */ | |
9a799d71 | 1451 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { |
c267fc16 AD |
1452 | /* trim packet back to size 0 and recycle it */ |
1453 | __pskb_trim(skb, 0); | |
1454 | rx_buffer_info->skb = skb; | |
9a799d71 AK |
1455 | goto next_desc; |
1456 | } | |
1457 | ||
8bae1b2b | 1458 | ixgbe_rx_checksum(adapter, rx_desc, skb); |
d2f4fbe2 AV |
1459 | |
1460 | /* probably a little skewed due to removing CRC */ | |
1461 | total_rx_bytes += skb->len; | |
1462 | total_rx_packets++; | |
1463 | ||
fc77dc3c | 1464 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); |
332d4a7d YZ |
1465 | #ifdef IXGBE_FCOE |
1466 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
3d8fd385 YZ |
1467 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { |
1468 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); | |
1469 | if (!ddp_bytes) | |
332d4a7d | 1470 | goto next_desc; |
3d8fd385 | 1471 | } |
332d4a7d | 1472 | #endif /* IXGBE_FCOE */ |
fdaff1ce | 1473 | ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc); |
9a799d71 AK |
1474 | |
1475 | next_desc: | |
1476 | rx_desc->wb.upper.status_error = 0; | |
1477 | ||
c267fc16 AD |
1478 | (*work_done)++; |
1479 | if (*work_done >= work_to_do) | |
1480 | break; | |
1481 | ||
9a799d71 AK |
1482 | /* return some buffers to hardware, one at a time is too slow */ |
1483 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
fc77dc3c | 1484 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); |
9a799d71 AK |
1485 | cleaned_count = 0; |
1486 | } | |
1487 | ||
1488 | /* use prefetched values */ | |
1489 | rx_desc = next_rxd; | |
9a799d71 | 1490 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
177db6ff MC |
1491 | } |
1492 | ||
9a799d71 AK |
1493 | rx_ring->next_to_clean = i; |
1494 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
1495 | ||
1496 | if (cleaned_count) | |
fc77dc3c | 1497 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); |
9a799d71 | 1498 | |
3d8fd385 YZ |
1499 | #ifdef IXGBE_FCOE |
1500 | /* include DDPed FCoE data */ | |
1501 | if (ddp_bytes > 0) { | |
1502 | unsigned int mss; | |
1503 | ||
fc77dc3c | 1504 | mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) - |
3d8fd385 YZ |
1505 | sizeof(struct fc_frame_header) - |
1506 | sizeof(struct fcoe_crc_eof); | |
1507 | if (mss > 512) | |
1508 | mss &= ~511; | |
1509 | total_rx_bytes += ddp_bytes; | |
1510 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
1511 | } | |
1512 | #endif /* IXGBE_FCOE */ | |
1513 | ||
f494e8fa AV |
1514 | rx_ring->total_packets += total_rx_packets; |
1515 | rx_ring->total_bytes += total_rx_bytes; | |
c267fc16 AD |
1516 | u64_stats_update_begin(&rx_ring->syncp); |
1517 | rx_ring->stats.packets += total_rx_packets; | |
1518 | rx_ring->stats.bytes += total_rx_bytes; | |
1519 | u64_stats_update_end(&rx_ring->syncp); | |
9a799d71 AK |
1520 | } |
1521 | ||
021230d4 | 1522 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
1523 | /** |
1524 | * ixgbe_configure_msix - Configure MSI-X hardware | |
1525 | * @adapter: board private structure | |
1526 | * | |
1527 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
1528 | * interrupts. | |
1529 | **/ | |
1530 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
1531 | { | |
021230d4 | 1532 | struct ixgbe_q_vector *q_vector; |
bf29ee6c | 1533 | int i, q_vectors, v_idx, r_idx; |
021230d4 | 1534 | u32 mask; |
9a799d71 | 1535 | |
021230d4 | 1536 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 1537 | |
4df10466 JB |
1538 | /* |
1539 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
1540 | * corresponding register. |
1541 | */ | |
1542 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
7a921c93 | 1543 | q_vector = adapter->q_vector[v_idx]; |
984b3f57 | 1544 | /* XXX for_each_set_bit(...) */ |
021230d4 | 1545 | r_idx = find_first_bit(q_vector->rxr_idx, |
e8e9f696 | 1546 | adapter->num_rx_queues); |
021230d4 AV |
1547 | |
1548 | for (i = 0; i < q_vector->rxr_count; i++) { | |
bf29ee6c AD |
1549 | u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx; |
1550 | ixgbe_set_ivar(adapter, 0, reg_idx, v_idx); | |
021230d4 | 1551 | r_idx = find_next_bit(q_vector->rxr_idx, |
e8e9f696 JP |
1552 | adapter->num_rx_queues, |
1553 | r_idx + 1); | |
021230d4 AV |
1554 | } |
1555 | r_idx = find_first_bit(q_vector->txr_idx, | |
e8e9f696 | 1556 | adapter->num_tx_queues); |
021230d4 AV |
1557 | |
1558 | for (i = 0; i < q_vector->txr_count; i++) { | |
bf29ee6c AD |
1559 | u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx; |
1560 | ixgbe_set_ivar(adapter, 1, reg_idx, v_idx); | |
021230d4 | 1561 | r_idx = find_next_bit(q_vector->txr_idx, |
e8e9f696 JP |
1562 | adapter->num_tx_queues, |
1563 | r_idx + 1); | |
021230d4 AV |
1564 | } |
1565 | ||
021230d4 | 1566 | if (q_vector->txr_count && !q_vector->rxr_count) |
f7554a2b NS |
1567 | /* tx only */ |
1568 | q_vector->eitr = adapter->tx_eitr_param; | |
509ee935 | 1569 | else if (q_vector->rxr_count) |
f7554a2b NS |
1570 | /* rx or mixed */ |
1571 | q_vector->eitr = adapter->rx_eitr_param; | |
021230d4 | 1572 | |
fe49f04a | 1573 | ixgbe_write_eitr(q_vector); |
b25ebfd2 PW |
1574 | /* If Flow Director is enabled, set interrupt affinity */ |
1575 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
1576 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) { | |
1577 | /* | |
1578 | * Allocate the affinity_hint cpumask, assign the mask | |
1579 | * for this vector, and set our affinity_hint for | |
1580 | * this irq. | |
1581 | */ | |
1582 | if (!alloc_cpumask_var(&q_vector->affinity_mask, | |
1583 | GFP_KERNEL)) | |
1584 | return; | |
1585 | cpumask_set_cpu(v_idx, q_vector->affinity_mask); | |
1586 | irq_set_affinity_hint(adapter->msix_entries[v_idx].vector, | |
1587 | q_vector->affinity_mask); | |
1588 | } | |
9a799d71 AK |
1589 | } |
1590 | ||
bd508178 AD |
1591 | switch (adapter->hw.mac.type) { |
1592 | case ixgbe_mac_82598EB: | |
e8e26350 | 1593 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, |
e8e9f696 | 1594 | v_idx); |
bd508178 AD |
1595 | break; |
1596 | case ixgbe_mac_82599EB: | |
b93a2226 | 1597 | case ixgbe_mac_X540: |
e8e26350 | 1598 | ixgbe_set_ivar(adapter, -1, 1, v_idx); |
bd508178 AD |
1599 | break; |
1600 | ||
1601 | default: | |
1602 | break; | |
1603 | } | |
021230d4 AV |
1604 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1605 | ||
41fb9248 | 1606 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 1607 | mask = IXGBE_EIMS_ENABLE_MASK; |
1cdd1ec8 GR |
1608 | if (adapter->num_vfs) |
1609 | mask &= ~(IXGBE_EIMS_OTHER | | |
1610 | IXGBE_EIMS_MAILBOX | | |
1611 | IXGBE_EIMS_LSC); | |
1612 | else | |
1613 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); | |
021230d4 | 1614 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
1615 | } |
1616 | ||
f494e8fa AV |
1617 | enum latency_range { |
1618 | lowest_latency = 0, | |
1619 | low_latency = 1, | |
1620 | bulk_latency = 2, | |
1621 | latency_invalid = 255 | |
1622 | }; | |
1623 | ||
1624 | /** | |
1625 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
1626 | * @adapter: pointer to adapter | |
1627 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
1628 | * @itr_setting: current throttle rate in ints/second | |
1629 | * @packets: the number of packets during this measurement interval | |
1630 | * @bytes: the number of bytes during this measurement interval | |
1631 | * | |
1632 | * Stores a new ITR value based on packets and byte | |
1633 | * counts during the last interrupt. The advantage of per interrupt | |
1634 | * computation is faster updates and more accurate ITR for the current | |
1635 | * traffic pattern. Constants in this function were computed | |
1636 | * based on theoretical maximum wire speed and thresholds were set based | |
1637 | * on testing data as well as attempting to minimize response time | |
1638 | * while increasing bulk throughput. | |
1639 | * this functionality is controlled by the InterruptThrottleRate module | |
1640 | * parameter (see ixgbe_param.c) | |
1641 | **/ | |
1642 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
e8e9f696 JP |
1643 | u32 eitr, u8 itr_setting, |
1644 | int packets, int bytes) | |
f494e8fa AV |
1645 | { |
1646 | unsigned int retval = itr_setting; | |
1647 | u32 timepassed_us; | |
1648 | u64 bytes_perint; | |
1649 | ||
1650 | if (packets == 0) | |
1651 | goto update_itr_done; | |
1652 | ||
1653 | ||
1654 | /* simple throttlerate management | |
1655 | * 0-20MB/s lowest (100000 ints/s) | |
1656 | * 20-100MB/s low (20000 ints/s) | |
1657 | * 100-1249MB/s bulk (8000 ints/s) | |
1658 | */ | |
1659 | /* what was last interrupt timeslice? */ | |
1660 | timepassed_us = 1000000/eitr; | |
1661 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
1662 | ||
1663 | switch (itr_setting) { | |
1664 | case lowest_latency: | |
1665 | if (bytes_perint > adapter->eitr_low) | |
1666 | retval = low_latency; | |
1667 | break; | |
1668 | case low_latency: | |
1669 | if (bytes_perint > adapter->eitr_high) | |
1670 | retval = bulk_latency; | |
1671 | else if (bytes_perint <= adapter->eitr_low) | |
1672 | retval = lowest_latency; | |
1673 | break; | |
1674 | case bulk_latency: | |
1675 | if (bytes_perint <= adapter->eitr_high) | |
1676 | retval = low_latency; | |
1677 | break; | |
1678 | } | |
1679 | ||
1680 | update_itr_done: | |
1681 | return retval; | |
1682 | } | |
1683 | ||
509ee935 JB |
1684 | /** |
1685 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1686 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1687 | * |
1688 | * This function is made to be called by ethtool and by the driver | |
1689 | * when it needs to update EITR registers at runtime. Hardware | |
1690 | * specific quirks/differences are taken care of here. | |
1691 | */ | |
fe49f04a | 1692 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1693 | { |
fe49f04a | 1694 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1695 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
1696 | int v_idx = q_vector->v_idx; |
1697 | u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr); | |
1698 | ||
bd508178 AD |
1699 | switch (adapter->hw.mac.type) { |
1700 | case ixgbe_mac_82598EB: | |
509ee935 JB |
1701 | /* must write high and low 16 bits to reset counter */ |
1702 | itr_reg |= (itr_reg << 16); | |
bd508178 AD |
1703 | break; |
1704 | case ixgbe_mac_82599EB: | |
b93a2226 | 1705 | case ixgbe_mac_X540: |
f8d1dcaf | 1706 | /* |
b93a2226 | 1707 | * 82599 and X540 can support a value of zero, so allow it for |
f8d1dcaf JB |
1708 | * max interrupt rate, but there is an errata where it can |
1709 | * not be zero with RSC | |
1710 | */ | |
1711 | if (itr_reg == 8 && | |
1712 | !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) | |
1713 | itr_reg = 0; | |
1714 | ||
509ee935 JB |
1715 | /* |
1716 | * set the WDIS bit to not clear the timer bits and cause an | |
1717 | * immediate assertion of the interrupt | |
1718 | */ | |
1719 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
bd508178 AD |
1720 | break; |
1721 | default: | |
1722 | break; | |
509ee935 JB |
1723 | } |
1724 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1725 | } | |
1726 | ||
f494e8fa AV |
1727 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) |
1728 | { | |
1729 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
125601bf | 1730 | int i, r_idx; |
f494e8fa AV |
1731 | u32 new_itr; |
1732 | u8 current_itr, ret_itr; | |
f494e8fa AV |
1733 | |
1734 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1735 | for (i = 0; i < q_vector->txr_count; i++) { | |
125601bf | 1736 | struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx]; |
f494e8fa | 1737 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, |
e8e9f696 JP |
1738 | q_vector->tx_itr, |
1739 | tx_ring->total_packets, | |
1740 | tx_ring->total_bytes); | |
f494e8fa AV |
1741 | /* if the result for this queue would decrease interrupt |
1742 | * rate for this vector then use that result */ | |
30efa5a3 | 1743 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
e8e9f696 | 1744 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 1745 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
e8e9f696 | 1746 | r_idx + 1); |
f494e8fa AV |
1747 | } |
1748 | ||
1749 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1750 | for (i = 0; i < q_vector->rxr_count; i++) { | |
125601bf | 1751 | struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx]; |
f494e8fa | 1752 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, |
e8e9f696 JP |
1753 | q_vector->rx_itr, |
1754 | rx_ring->total_packets, | |
1755 | rx_ring->total_bytes); | |
f494e8fa AV |
1756 | /* if the result for this queue would decrease interrupt |
1757 | * rate for this vector then use that result */ | |
30efa5a3 | 1758 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
e8e9f696 | 1759 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 1760 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
e8e9f696 | 1761 | r_idx + 1); |
f494e8fa AV |
1762 | } |
1763 | ||
30efa5a3 | 1764 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1765 | |
1766 | switch (current_itr) { | |
1767 | /* counts and packets in update_itr are dependent on these numbers */ | |
1768 | case lowest_latency: | |
1769 | new_itr = 100000; | |
1770 | break; | |
1771 | case low_latency: | |
1772 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1773 | break; | |
1774 | case bulk_latency: | |
1775 | default: | |
1776 | new_itr = 8000; | |
1777 | break; | |
1778 | } | |
1779 | ||
1780 | if (new_itr != q_vector->eitr) { | |
fe49f04a | 1781 | /* do an exponential smoothing */ |
125601bf | 1782 | new_itr = ((q_vector->eitr * 9) + new_itr)/10; |
509ee935 JB |
1783 | |
1784 | /* save the algorithm value here, not the smoothed one */ | |
1785 | q_vector->eitr = new_itr; | |
fe49f04a AD |
1786 | |
1787 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 1788 | } |
f494e8fa AV |
1789 | } |
1790 | ||
119fc60a MC |
1791 | /** |
1792 | * ixgbe_check_overtemp_task - worker thread to check over tempurature | |
1793 | * @work: pointer to work_struct containing our data | |
1794 | **/ | |
1795 | static void ixgbe_check_overtemp_task(struct work_struct *work) | |
1796 | { | |
1797 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
1798 | struct ixgbe_adapter, |
1799 | check_overtemp_task); | |
119fc60a MC |
1800 | struct ixgbe_hw *hw = &adapter->hw; |
1801 | u32 eicr = adapter->interrupt_event; | |
1802 | ||
7ca647bd JP |
1803 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) |
1804 | return; | |
1805 | ||
1806 | switch (hw->device_id) { | |
1807 | case IXGBE_DEV_ID_82599_T3_LOM: { | |
1808 | u32 autoneg; | |
1809 | bool link_up = false; | |
1810 | ||
1811 | if (hw->mac.ops.check_link) | |
1812 | hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
1813 | ||
1814 | if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) || | |
1815 | (eicr & IXGBE_EICR_LSC)) | |
1816 | /* Check if this is due to overtemp */ | |
1817 | if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP) | |
1818 | break; | |
1819 | return; | |
1820 | } | |
1821 | default: | |
1822 | if (!(eicr & IXGBE_EICR_GPI_SDP0)) | |
119fc60a | 1823 | return; |
7ca647bd | 1824 | break; |
119fc60a | 1825 | } |
7ca647bd JP |
1826 | e_crit(drv, |
1827 | "Network adapter has been stopped because it has over heated. " | |
1828 | "Restart the computer. If the problem persists, " | |
1829 | "power off the system and replace the adapter\n"); | |
1830 | /* write to clear the interrupt */ | |
1831 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0); | |
119fc60a MC |
1832 | } |
1833 | ||
0befdb3e JB |
1834 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
1835 | { | |
1836 | struct ixgbe_hw *hw = &adapter->hw; | |
1837 | ||
1838 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
1839 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
396e799c | 1840 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
0befdb3e JB |
1841 | /* write to clear the interrupt */ |
1842 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1843 | } | |
1844 | } | |
cf8280ee | 1845 | |
e8e26350 PW |
1846 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
1847 | { | |
1848 | struct ixgbe_hw *hw = &adapter->hw; | |
1849 | ||
73c4b7cd AD |
1850 | if (eicr & IXGBE_EICR_GPI_SDP2) { |
1851 | /* Clear the interrupt */ | |
1852 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
1853 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1854 | schedule_work(&adapter->sfp_config_module_task); | |
1855 | } | |
1856 | ||
e8e26350 PW |
1857 | if (eicr & IXGBE_EICR_GPI_SDP1) { |
1858 | /* Clear the interrupt */ | |
1859 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
73c4b7cd AD |
1860 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1861 | schedule_work(&adapter->multispeed_fiber_task); | |
e8e26350 PW |
1862 | } |
1863 | } | |
1864 | ||
cf8280ee JB |
1865 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
1866 | { | |
1867 | struct ixgbe_hw *hw = &adapter->hw; | |
1868 | ||
1869 | adapter->lsc_int++; | |
1870 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
1871 | adapter->link_check_timeout = jiffies; | |
1872 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1873 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 1874 | IXGBE_WRITE_FLUSH(hw); |
cf8280ee JB |
1875 | schedule_work(&adapter->watchdog_task); |
1876 | } | |
1877 | } | |
1878 | ||
9a799d71 AK |
1879 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
1880 | { | |
1881 | struct net_device *netdev = data; | |
1882 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1883 | struct ixgbe_hw *hw = &adapter->hw; | |
54037505 DS |
1884 | u32 eicr; |
1885 | ||
1886 | /* | |
1887 | * Workaround for Silicon errata. Use clear-by-write instead | |
1888 | * of clear-by-read. Reading with EICS will return the | |
1889 | * interrupt causes without clearing, which later be done | |
1890 | * with the write to EICR. | |
1891 | */ | |
1892 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
1893 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
9a799d71 | 1894 | |
cf8280ee JB |
1895 | if (eicr & IXGBE_EICR_LSC) |
1896 | ixgbe_check_lsc(adapter); | |
d4f80882 | 1897 | |
1cdd1ec8 GR |
1898 | if (eicr & IXGBE_EICR_MAILBOX) |
1899 | ixgbe_msg_task(adapter); | |
1900 | ||
bd508178 AD |
1901 | switch (hw->mac.type) { |
1902 | case ixgbe_mac_82599EB: | |
d994653d DS |
1903 | ixgbe_check_sfp_event(adapter, eicr); |
1904 | if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && | |
1905 | ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) { | |
1906 | adapter->interrupt_event = eicr; | |
1907 | schedule_work(&adapter->check_overtemp_task); | |
1908 | } | |
1909 | /* now fallthrough to handle Flow Director */ | |
b93a2226 | 1910 | case ixgbe_mac_X540: |
c4cf55e5 PWJ |
1911 | /* Handle Flow Director Full threshold interrupt */ |
1912 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
1913 | int i; | |
1914 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR); | |
1915 | /* Disable transmits before FDIR Re-initialization */ | |
1916 | netif_tx_stop_all_queues(netdev); | |
1917 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1918 | struct ixgbe_ring *tx_ring = | |
e8e9f696 | 1919 | adapter->tx_ring[i]; |
7d637bcc AD |
1920 | if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, |
1921 | &tx_ring->state)) | |
c4cf55e5 PWJ |
1922 | schedule_work(&adapter->fdir_reinit_task); |
1923 | } | |
1924 | } | |
bd508178 AD |
1925 | break; |
1926 | default: | |
1927 | break; | |
c4cf55e5 | 1928 | } |
bd508178 AD |
1929 | |
1930 | ixgbe_check_fan_failure(adapter, eicr); | |
1931 | ||
d4f80882 AV |
1932 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1933 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
1934 | |
1935 | return IRQ_HANDLED; | |
1936 | } | |
1937 | ||
fe49f04a AD |
1938 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
1939 | u64 qmask) | |
1940 | { | |
1941 | u32 mask; | |
bd508178 | 1942 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 1943 | |
bd508178 AD |
1944 | switch (hw->mac.type) { |
1945 | case ixgbe_mac_82598EB: | |
fe49f04a | 1946 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
1947 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); |
1948 | break; | |
1949 | case ixgbe_mac_82599EB: | |
b93a2226 | 1950 | case ixgbe_mac_X540: |
fe49f04a | 1951 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
1952 | if (mask) |
1953 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | |
fe49f04a | 1954 | mask = (qmask >> 32); |
bd508178 AD |
1955 | if (mask) |
1956 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | |
1957 | break; | |
1958 | default: | |
1959 | break; | |
fe49f04a AD |
1960 | } |
1961 | /* skip the flush */ | |
1962 | } | |
1963 | ||
1964 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
e8e9f696 | 1965 | u64 qmask) |
fe49f04a AD |
1966 | { |
1967 | u32 mask; | |
bd508178 | 1968 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 1969 | |
bd508178 AD |
1970 | switch (hw->mac.type) { |
1971 | case ixgbe_mac_82598EB: | |
fe49f04a | 1972 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
1973 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); |
1974 | break; | |
1975 | case ixgbe_mac_82599EB: | |
b93a2226 | 1976 | case ixgbe_mac_X540: |
fe49f04a | 1977 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
1978 | if (mask) |
1979 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); | |
fe49f04a | 1980 | mask = (qmask >> 32); |
bd508178 AD |
1981 | if (mask) |
1982 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); | |
1983 | break; | |
1984 | default: | |
1985 | break; | |
fe49f04a AD |
1986 | } |
1987 | /* skip the flush */ | |
1988 | } | |
1989 | ||
9a799d71 AK |
1990 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) |
1991 | { | |
021230d4 AV |
1992 | struct ixgbe_q_vector *q_vector = data; |
1993 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1994 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
1995 | int i, r_idx; |
1996 | ||
1997 | if (!q_vector->txr_count) | |
1998 | return IRQ_HANDLED; | |
1999 | ||
2000 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
2001 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 2002 | tx_ring = adapter->tx_ring[r_idx]; |
3a581073 JB |
2003 | tx_ring->total_bytes = 0; |
2004 | tx_ring->total_packets = 0; | |
021230d4 | 2005 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
e8e9f696 | 2006 | r_idx + 1); |
021230d4 | 2007 | } |
9a799d71 | 2008 | |
9b471446 | 2009 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 AD |
2010 | napi_schedule(&q_vector->napi); |
2011 | ||
9a799d71 AK |
2012 | return IRQ_HANDLED; |
2013 | } | |
2014 | ||
021230d4 AV |
2015 | /** |
2016 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
2017 | * @irq: unused | |
2018 | * @data: pointer to our q_vector struct for this interrupt vector | |
2019 | **/ | |
9a799d71 AK |
2020 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
2021 | { | |
021230d4 AV |
2022 | struct ixgbe_q_vector *q_vector = data; |
2023 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 2024 | struct ixgbe_ring *rx_ring; |
021230d4 | 2025 | int r_idx; |
30efa5a3 | 2026 | int i; |
021230d4 | 2027 | |
33cf09c9 AD |
2028 | #ifdef CONFIG_IXGBE_DCA |
2029 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2030 | ixgbe_update_dca(q_vector); | |
2031 | #endif | |
2032 | ||
021230d4 | 2033 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
33cf09c9 | 2034 | for (i = 0; i < q_vector->rxr_count; i++) { |
4a0b9ca0 | 2035 | rx_ring = adapter->rx_ring[r_idx]; |
30efa5a3 JB |
2036 | rx_ring->total_bytes = 0; |
2037 | rx_ring->total_packets = 0; | |
2038 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
e8e9f696 | 2039 | r_idx + 1); |
30efa5a3 JB |
2040 | } |
2041 | ||
021230d4 AV |
2042 | if (!q_vector->rxr_count) |
2043 | return IRQ_HANDLED; | |
2044 | ||
9b471446 | 2045 | /* EIAM disabled interrupts (on this vector) for us */ |
288379f0 | 2046 | napi_schedule(&q_vector->napi); |
021230d4 AV |
2047 | |
2048 | return IRQ_HANDLED; | |
2049 | } | |
2050 | ||
2051 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
2052 | { | |
91281fd3 AD |
2053 | struct ixgbe_q_vector *q_vector = data; |
2054 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
2055 | struct ixgbe_ring *ring; | |
2056 | int r_idx; | |
2057 | int i; | |
2058 | ||
2059 | if (!q_vector->txr_count && !q_vector->rxr_count) | |
2060 | return IRQ_HANDLED; | |
2061 | ||
2062 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
2063 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 2064 | ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
2065 | ring->total_bytes = 0; |
2066 | ring->total_packets = 0; | |
2067 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
e8e9f696 | 2068 | r_idx + 1); |
91281fd3 AD |
2069 | } |
2070 | ||
2071 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
2072 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 2073 | ring = adapter->rx_ring[r_idx]; |
91281fd3 AD |
2074 | ring->total_bytes = 0; |
2075 | ring->total_packets = 0; | |
2076 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
e8e9f696 | 2077 | r_idx + 1); |
91281fd3 AD |
2078 | } |
2079 | ||
9b471446 | 2080 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 2081 | napi_schedule(&q_vector->napi); |
9a799d71 | 2082 | |
9a799d71 AK |
2083 | return IRQ_HANDLED; |
2084 | } | |
2085 | ||
021230d4 AV |
2086 | /** |
2087 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
2088 | * @napi: napi struct with our devices info in it | |
2089 | * @budget: amount of work driver is allowed to do this pass, in packets | |
2090 | * | |
f0848276 JB |
2091 | * This function is optimized for cleaning one queue only on a single |
2092 | * q_vector!!! | |
021230d4 | 2093 | **/ |
9a799d71 AK |
2094 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
2095 | { | |
021230d4 | 2096 | struct ixgbe_q_vector *q_vector = |
e8e9f696 | 2097 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 2098 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 2099 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 2100 | int work_done = 0; |
021230d4 | 2101 | long r_idx; |
9a799d71 | 2102 | |
5dd2d332 | 2103 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 2104 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
33cf09c9 | 2105 | ixgbe_update_dca(q_vector); |
bd0362dd | 2106 | #endif |
9a799d71 | 2107 | |
33cf09c9 AD |
2108 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
2109 | rx_ring = adapter->rx_ring[r_idx]; | |
2110 | ||
78b6f4ce | 2111 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
9a799d71 | 2112 | |
021230d4 AV |
2113 | /* If all Rx work done, exit the polling mode */ |
2114 | if (work_done < budget) { | |
288379f0 | 2115 | napi_complete(napi); |
f7554a2b | 2116 | if (adapter->rx_itr_setting & 1) |
f494e8fa | 2117 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 2118 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
fe49f04a | 2119 | ixgbe_irq_enable_queues(adapter, |
e8e9f696 | 2120 | ((u64)1 << q_vector->v_idx)); |
9a799d71 AK |
2121 | } |
2122 | ||
2123 | return work_done; | |
2124 | } | |
2125 | ||
f0848276 | 2126 | /** |
91281fd3 | 2127 | * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine |
f0848276 JB |
2128 | * @napi: napi struct with our devices info in it |
2129 | * @budget: amount of work driver is allowed to do this pass, in packets | |
2130 | * | |
2131 | * This function will clean more than one rx queue associated with a | |
2132 | * q_vector. | |
2133 | **/ | |
91281fd3 | 2134 | static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget) |
f0848276 JB |
2135 | { |
2136 | struct ixgbe_q_vector *q_vector = | |
e8e9f696 | 2137 | container_of(napi, struct ixgbe_q_vector, napi); |
f0848276 | 2138 | struct ixgbe_adapter *adapter = q_vector->adapter; |
91281fd3 | 2139 | struct ixgbe_ring *ring = NULL; |
f0848276 JB |
2140 | int work_done = 0, i; |
2141 | long r_idx; | |
91281fd3 AD |
2142 | bool tx_clean_complete = true; |
2143 | ||
33cf09c9 AD |
2144 | #ifdef CONFIG_IXGBE_DCA |
2145 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2146 | ixgbe_update_dca(q_vector); | |
2147 | #endif | |
2148 | ||
91281fd3 AD |
2149 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); |
2150 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 2151 | ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
2152 | tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring); |
2153 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
e8e9f696 | 2154 | r_idx + 1); |
91281fd3 | 2155 | } |
f0848276 JB |
2156 | |
2157 | /* attempt to distribute budget to each queue fairly, but don't allow | |
2158 | * the budget to go below 1 because we'll exit polling */ | |
2159 | budget /= (q_vector->rxr_count ?: 1); | |
2160 | budget = max(budget, 1); | |
2161 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
2162 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 2163 | ring = adapter->rx_ring[r_idx]; |
91281fd3 | 2164 | ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget); |
f0848276 | 2165 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
e8e9f696 | 2166 | r_idx + 1); |
f0848276 JB |
2167 | } |
2168 | ||
2169 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
4a0b9ca0 | 2170 | ring = adapter->rx_ring[r_idx]; |
f0848276 | 2171 | /* If all Rx work done, exit the polling mode */ |
7f821875 | 2172 | if (work_done < budget) { |
288379f0 | 2173 | napi_complete(napi); |
f7554a2b | 2174 | if (adapter->rx_itr_setting & 1) |
f0848276 JB |
2175 | ixgbe_set_itr_msix(q_vector); |
2176 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
fe49f04a | 2177 | ixgbe_irq_enable_queues(adapter, |
e8e9f696 | 2178 | ((u64)1 << q_vector->v_idx)); |
f0848276 JB |
2179 | return 0; |
2180 | } | |
2181 | ||
2182 | return work_done; | |
2183 | } | |
91281fd3 AD |
2184 | |
2185 | /** | |
2186 | * ixgbe_clean_txonly - msix (aka one shot) tx clean routine | |
2187 | * @napi: napi struct with our devices info in it | |
2188 | * @budget: amount of work driver is allowed to do this pass, in packets | |
2189 | * | |
2190 | * This function is optimized for cleaning one queue only on a single | |
2191 | * q_vector!!! | |
2192 | **/ | |
2193 | static int ixgbe_clean_txonly(struct napi_struct *napi, int budget) | |
2194 | { | |
2195 | struct ixgbe_q_vector *q_vector = | |
e8e9f696 | 2196 | container_of(napi, struct ixgbe_q_vector, napi); |
91281fd3 AD |
2197 | struct ixgbe_adapter *adapter = q_vector->adapter; |
2198 | struct ixgbe_ring *tx_ring = NULL; | |
2199 | int work_done = 0; | |
2200 | long r_idx; | |
2201 | ||
91281fd3 AD |
2202 | #ifdef CONFIG_IXGBE_DCA |
2203 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
33cf09c9 | 2204 | ixgbe_update_dca(q_vector); |
91281fd3 AD |
2205 | #endif |
2206 | ||
33cf09c9 AD |
2207 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); |
2208 | tx_ring = adapter->tx_ring[r_idx]; | |
2209 | ||
91281fd3 AD |
2210 | if (!ixgbe_clean_tx_irq(q_vector, tx_ring)) |
2211 | work_done = budget; | |
2212 | ||
f7554a2b | 2213 | /* If all Tx work done, exit the polling mode */ |
91281fd3 AD |
2214 | if (work_done < budget) { |
2215 | napi_complete(napi); | |
f7554a2b | 2216 | if (adapter->tx_itr_setting & 1) |
91281fd3 AD |
2217 | ixgbe_set_itr_msix(q_vector); |
2218 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
e8e9f696 JP |
2219 | ixgbe_irq_enable_queues(adapter, |
2220 | ((u64)1 << q_vector->v_idx)); | |
91281fd3 AD |
2221 | } |
2222 | ||
2223 | return work_done; | |
2224 | } | |
2225 | ||
021230d4 | 2226 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
e8e9f696 | 2227 | int r_idx) |
021230d4 | 2228 | { |
7a921c93 | 2229 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
2274543f | 2230 | struct ixgbe_ring *rx_ring = a->rx_ring[r_idx]; |
7a921c93 AD |
2231 | |
2232 | set_bit(r_idx, q_vector->rxr_idx); | |
2233 | q_vector->rxr_count++; | |
2274543f | 2234 | rx_ring->q_vector = q_vector; |
021230d4 AV |
2235 | } |
2236 | ||
2237 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
e8e9f696 | 2238 | int t_idx) |
021230d4 | 2239 | { |
7a921c93 | 2240 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
2274543f | 2241 | struct ixgbe_ring *tx_ring = a->tx_ring[t_idx]; |
7a921c93 AD |
2242 | |
2243 | set_bit(t_idx, q_vector->txr_idx); | |
2244 | q_vector->txr_count++; | |
2274543f | 2245 | tx_ring->q_vector = q_vector; |
021230d4 AV |
2246 | } |
2247 | ||
9a799d71 | 2248 | /** |
021230d4 AV |
2249 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
2250 | * @adapter: board private structure to initialize | |
9a799d71 | 2251 | * |
021230d4 AV |
2252 | * This function maps descriptor rings to the queue-specific vectors |
2253 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
2254 | * one vector per ring/queue, but on a constrained vector budget, we | |
2255 | * group the rings as "efficiently" as possible. You would add new | |
2256 | * mapping configurations in here. | |
9a799d71 | 2257 | **/ |
d0759ebb | 2258 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter) |
021230d4 | 2259 | { |
d0759ebb | 2260 | int q_vectors; |
021230d4 AV |
2261 | int v_start = 0; |
2262 | int rxr_idx = 0, txr_idx = 0; | |
2263 | int rxr_remaining = adapter->num_rx_queues; | |
2264 | int txr_remaining = adapter->num_tx_queues; | |
2265 | int i, j; | |
2266 | int rqpv, tqpv; | |
2267 | int err = 0; | |
2268 | ||
2269 | /* No mapping required if MSI-X is disabled. */ | |
2270 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2271 | goto out; | |
9a799d71 | 2272 | |
d0759ebb AD |
2273 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
2274 | ||
021230d4 AV |
2275 | /* |
2276 | * The ideal configuration... | |
2277 | * We have enough vectors to map one per queue. | |
2278 | */ | |
d0759ebb | 2279 | if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) { |
021230d4 AV |
2280 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) |
2281 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 2282 | |
021230d4 AV |
2283 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
2284 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 2285 | |
9a799d71 | 2286 | goto out; |
021230d4 | 2287 | } |
9a799d71 | 2288 | |
021230d4 AV |
2289 | /* |
2290 | * If we don't have enough vectors for a 1-to-1 | |
2291 | * mapping, we'll have to group them so there are | |
2292 | * multiple queues per vector. | |
2293 | */ | |
2294 | /* Re-adjusting *qpv takes care of the remainder. */ | |
d0759ebb AD |
2295 | for (i = v_start; i < q_vectors; i++) { |
2296 | rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i); | |
021230d4 AV |
2297 | for (j = 0; j < rqpv; j++) { |
2298 | map_vector_to_rxq(adapter, i, rxr_idx); | |
2299 | rxr_idx++; | |
2300 | rxr_remaining--; | |
2301 | } | |
d0759ebb | 2302 | tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i); |
021230d4 AV |
2303 | for (j = 0; j < tqpv; j++) { |
2304 | map_vector_to_txq(adapter, i, txr_idx); | |
2305 | txr_idx++; | |
2306 | txr_remaining--; | |
9a799d71 | 2307 | } |
9a799d71 | 2308 | } |
021230d4 AV |
2309 | out: |
2310 | return err; | |
2311 | } | |
2312 | ||
2313 | /** | |
2314 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
2315 | * @adapter: board private structure | |
2316 | * | |
2317 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
2318 | * interrupts from the kernel. | |
2319 | **/ | |
2320 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
2321 | { | |
2322 | struct net_device *netdev = adapter->netdev; | |
2323 | irqreturn_t (*handler)(int, void *); | |
2324 | int i, vector, q_vectors, err; | |
e8e9f696 | 2325 | int ri = 0, ti = 0; |
021230d4 AV |
2326 | |
2327 | /* Decrement for Other and TCP Timer vectors */ | |
2328 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2329 | ||
d0759ebb | 2330 | err = ixgbe_map_rings_to_vectors(adapter); |
021230d4 | 2331 | if (err) |
d0759ebb | 2332 | return err; |
021230d4 | 2333 | |
d0759ebb AD |
2334 | #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \ |
2335 | ? &ixgbe_msix_clean_many : \ | |
2336 | (_v)->rxr_count ? &ixgbe_msix_clean_rx : \ | |
2337 | (_v)->txr_count ? &ixgbe_msix_clean_tx : \ | |
2338 | NULL) | |
021230d4 | 2339 | for (vector = 0; vector < q_vectors; vector++) { |
d0759ebb AD |
2340 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; |
2341 | handler = SET_HANDLER(q_vector); | |
cb13fc20 | 2342 | |
e8e9f696 | 2343 | if (handler == &ixgbe_msix_clean_rx) { |
9fe93afd DS |
2344 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
2345 | "%s-%s-%d", netdev->name, "rx", ri++); | |
e8e9f696 | 2346 | } else if (handler == &ixgbe_msix_clean_tx) { |
9fe93afd DS |
2347 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
2348 | "%s-%s-%d", netdev->name, "tx", ti++); | |
d0759ebb | 2349 | } else if (handler == &ixgbe_msix_clean_many) { |
9fe93afd DS |
2350 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
2351 | "%s-%s-%d", netdev->name, "TxRx", ri++); | |
32aa77a4 | 2352 | ti++; |
d0759ebb AD |
2353 | } else { |
2354 | /* skip this unused q_vector */ | |
2355 | continue; | |
32aa77a4 | 2356 | } |
021230d4 | 2357 | err = request_irq(adapter->msix_entries[vector].vector, |
d0759ebb AD |
2358 | handler, 0, q_vector->name, |
2359 | q_vector); | |
9a799d71 | 2360 | if (err) { |
396e799c | 2361 | e_err(probe, "request_irq failed for MSIX interrupt " |
849c4542 | 2362 | "Error: %d\n", err); |
021230d4 | 2363 | goto free_queue_irqs; |
9a799d71 | 2364 | } |
9a799d71 AK |
2365 | } |
2366 | ||
d0759ebb | 2367 | sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name); |
021230d4 | 2368 | err = request_irq(adapter->msix_entries[vector].vector, |
d0759ebb | 2369 | ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev); |
9a799d71 | 2370 | if (err) { |
396e799c | 2371 | e_err(probe, "request_irq for msix_lsc failed: %d\n", err); |
021230d4 | 2372 | goto free_queue_irqs; |
9a799d71 AK |
2373 | } |
2374 | ||
9a799d71 AK |
2375 | return 0; |
2376 | ||
021230d4 AV |
2377 | free_queue_irqs: |
2378 | for (i = vector - 1; i >= 0; i--) | |
2379 | free_irq(adapter->msix_entries[--vector].vector, | |
e8e9f696 | 2380 | adapter->q_vector[i]); |
021230d4 AV |
2381 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
2382 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
2383 | kfree(adapter->msix_entries); |
2384 | adapter->msix_entries = NULL; | |
9a799d71 AK |
2385 | return err; |
2386 | } | |
2387 | ||
f494e8fa AV |
2388 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
2389 | { | |
7a921c93 | 2390 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
4a0b9ca0 PW |
2391 | struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; |
2392 | struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; | |
125601bf AD |
2393 | u32 new_itr = q_vector->eitr; |
2394 | u8 current_itr; | |
f494e8fa | 2395 | |
30efa5a3 | 2396 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
e8e9f696 JP |
2397 | q_vector->tx_itr, |
2398 | tx_ring->total_packets, | |
2399 | tx_ring->total_bytes); | |
30efa5a3 | 2400 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
e8e9f696 JP |
2401 | q_vector->rx_itr, |
2402 | rx_ring->total_packets, | |
2403 | rx_ring->total_bytes); | |
f494e8fa | 2404 | |
30efa5a3 | 2405 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
2406 | |
2407 | switch (current_itr) { | |
2408 | /* counts and packets in update_itr are dependent on these numbers */ | |
2409 | case lowest_latency: | |
2410 | new_itr = 100000; | |
2411 | break; | |
2412 | case low_latency: | |
2413 | new_itr = 20000; /* aka hwitr = ~200 */ | |
2414 | break; | |
2415 | case bulk_latency: | |
2416 | new_itr = 8000; | |
2417 | break; | |
2418 | default: | |
2419 | break; | |
2420 | } | |
2421 | ||
2422 | if (new_itr != q_vector->eitr) { | |
fe49f04a | 2423 | /* do an exponential smoothing */ |
125601bf | 2424 | new_itr = ((q_vector->eitr * 9) + new_itr)/10; |
509ee935 | 2425 | |
125601bf | 2426 | /* save the algorithm value here */ |
509ee935 | 2427 | q_vector->eitr = new_itr; |
fe49f04a AD |
2428 | |
2429 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 2430 | } |
f494e8fa AV |
2431 | } |
2432 | ||
79aefa45 AD |
2433 | /** |
2434 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
2435 | * @adapter: board private structure | |
2436 | **/ | |
6af3b9eb ET |
2437 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, |
2438 | bool flush) | |
79aefa45 AD |
2439 | { |
2440 | u32 mask; | |
835462fc NS |
2441 | |
2442 | mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); | |
119fc60a MC |
2443 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
2444 | mask |= IXGBE_EIMS_GPI_SDP0; | |
6ab33d51 DM |
2445 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
2446 | mask |= IXGBE_EIMS_GPI_SDP1; | |
bd508178 AD |
2447 | switch (adapter->hw.mac.type) { |
2448 | case ixgbe_mac_82599EB: | |
b93a2226 | 2449 | case ixgbe_mac_X540: |
2a41ff81 | 2450 | mask |= IXGBE_EIMS_ECC; |
e8e26350 PW |
2451 | mask |= IXGBE_EIMS_GPI_SDP1; |
2452 | mask |= IXGBE_EIMS_GPI_SDP2; | |
1cdd1ec8 GR |
2453 | if (adapter->num_vfs) |
2454 | mask |= IXGBE_EIMS_MAILBOX; | |
bd508178 AD |
2455 | break; |
2456 | default: | |
2457 | break; | |
e8e26350 | 2458 | } |
c4cf55e5 PWJ |
2459 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
2460 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
2461 | mask |= IXGBE_EIMS_FLOW_DIR; | |
e8e26350 | 2462 | |
79aefa45 | 2463 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
6af3b9eb ET |
2464 | if (queues) |
2465 | ixgbe_irq_enable_queues(adapter, ~0); | |
2466 | if (flush) | |
2467 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1cdd1ec8 GR |
2468 | |
2469 | if (adapter->num_vfs > 32) { | |
2470 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
2471 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
2472 | } | |
79aefa45 | 2473 | } |
021230d4 | 2474 | |
9a799d71 | 2475 | /** |
021230d4 | 2476 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
2477 | * @irq: interrupt number |
2478 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
2479 | **/ |
2480 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
2481 | { | |
2482 | struct net_device *netdev = data; | |
2483 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2484 | struct ixgbe_hw *hw = &adapter->hw; | |
7a921c93 | 2485 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
2486 | u32 eicr; |
2487 | ||
54037505 | 2488 | /* |
6af3b9eb | 2489 | * Workaround for silicon errata on 82598. Mask the interrupts |
54037505 DS |
2490 | * before the read of EICR. |
2491 | */ | |
2492 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
2493 | ||
021230d4 AV |
2494 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
2495 | * therefore no explict interrupt disable is necessary */ | |
2496 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e | 2497 | if (!eicr) { |
6af3b9eb ET |
2498 | /* |
2499 | * shared interrupt alert! | |
f47cf66e | 2500 | * make sure interrupts are enabled because the read will |
6af3b9eb ET |
2501 | * have disabled interrupts due to EIAM |
2502 | * finish the workaround of silicon errata on 82598. Unmask | |
2503 | * the interrupt that we masked before the EICR read. | |
2504 | */ | |
2505 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2506 | ixgbe_irq_enable(adapter, true, true); | |
9a799d71 | 2507 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 2508 | } |
9a799d71 | 2509 | |
cf8280ee JB |
2510 | if (eicr & IXGBE_EICR_LSC) |
2511 | ixgbe_check_lsc(adapter); | |
021230d4 | 2512 | |
bd508178 AD |
2513 | switch (hw->mac.type) { |
2514 | case ixgbe_mac_82599EB: | |
e8e26350 | 2515 | ixgbe_check_sfp_event(adapter, eicr); |
bd508178 AD |
2516 | if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
2517 | ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) { | |
2518 | adapter->interrupt_event = eicr; | |
2519 | schedule_work(&adapter->check_overtemp_task); | |
2520 | } | |
2521 | break; | |
2522 | default: | |
2523 | break; | |
2524 | } | |
e8e26350 | 2525 | |
0befdb3e JB |
2526 | ixgbe_check_fan_failure(adapter, eicr); |
2527 | ||
7a921c93 | 2528 | if (napi_schedule_prep(&(q_vector->napi))) { |
4a0b9ca0 PW |
2529 | adapter->tx_ring[0]->total_packets = 0; |
2530 | adapter->tx_ring[0]->total_bytes = 0; | |
2531 | adapter->rx_ring[0]->total_packets = 0; | |
2532 | adapter->rx_ring[0]->total_bytes = 0; | |
021230d4 | 2533 | /* would disable interrupts here but EIAM disabled it */ |
7a921c93 | 2534 | __napi_schedule(&(q_vector->napi)); |
9a799d71 AK |
2535 | } |
2536 | ||
6af3b9eb ET |
2537 | /* |
2538 | * re-enable link(maybe) and non-queue interrupts, no flush. | |
2539 | * ixgbe_poll will re-enable the queue interrupts | |
2540 | */ | |
2541 | ||
2542 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2543 | ixgbe_irq_enable(adapter, false, false); | |
2544 | ||
9a799d71 AK |
2545 | return IRQ_HANDLED; |
2546 | } | |
2547 | ||
021230d4 AV |
2548 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
2549 | { | |
2550 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2551 | ||
2552 | for (i = 0; i < q_vectors; i++) { | |
7a921c93 | 2553 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; |
021230d4 AV |
2554 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); |
2555 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
2556 | q_vector->rxr_count = 0; | |
2557 | q_vector->txr_count = 0; | |
2558 | } | |
2559 | } | |
2560 | ||
9a799d71 AK |
2561 | /** |
2562 | * ixgbe_request_irq - initialize interrupts | |
2563 | * @adapter: board private structure | |
2564 | * | |
2565 | * Attempts to configure interrupts using the best available | |
2566 | * capabilities of the hardware and kernel. | |
2567 | **/ | |
021230d4 | 2568 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2569 | { |
2570 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 2571 | int err; |
9a799d71 | 2572 | |
021230d4 AV |
2573 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2574 | err = ixgbe_request_msix_irqs(adapter); | |
2575 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
a0607fd3 | 2576 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
e8e9f696 | 2577 | netdev->name, netdev); |
021230d4 | 2578 | } else { |
a0607fd3 | 2579 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
e8e9f696 | 2580 | netdev->name, netdev); |
9a799d71 AK |
2581 | } |
2582 | ||
9a799d71 | 2583 | if (err) |
396e799c | 2584 | e_err(probe, "request_irq failed, Error %d\n", err); |
9a799d71 | 2585 | |
9a799d71 AK |
2586 | return err; |
2587 | } | |
2588 | ||
2589 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
2590 | { | |
2591 | struct net_device *netdev = adapter->netdev; | |
2592 | ||
2593 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 2594 | int i, q_vectors; |
9a799d71 | 2595 | |
021230d4 AV |
2596 | q_vectors = adapter->num_msix_vectors; |
2597 | ||
2598 | i = q_vectors - 1; | |
9a799d71 | 2599 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 2600 | |
021230d4 AV |
2601 | i--; |
2602 | for (; i >= 0; i--) { | |
894ff7cf AD |
2603 | /* free only the irqs that were actually requested */ |
2604 | if (!adapter->q_vector[i]->rxr_count && | |
2605 | !adapter->q_vector[i]->txr_count) | |
2606 | continue; | |
2607 | ||
021230d4 | 2608 | free_irq(adapter->msix_entries[i].vector, |
e8e9f696 | 2609 | adapter->q_vector[i]); |
021230d4 AV |
2610 | } |
2611 | ||
2612 | ixgbe_reset_q_vectors(adapter); | |
2613 | } else { | |
2614 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
2615 | } |
2616 | } | |
2617 | ||
22d5a71b JB |
2618 | /** |
2619 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
2620 | * @adapter: board private structure | |
2621 | **/ | |
2622 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
2623 | { | |
bd508178 AD |
2624 | switch (adapter->hw.mac.type) { |
2625 | case ixgbe_mac_82598EB: | |
835462fc | 2626 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); |
bd508178 AD |
2627 | break; |
2628 | case ixgbe_mac_82599EB: | |
b93a2226 | 2629 | case ixgbe_mac_X540: |
835462fc NS |
2630 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); |
2631 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 2632 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
1cdd1ec8 GR |
2633 | if (adapter->num_vfs > 32) |
2634 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
bd508178 AD |
2635 | break; |
2636 | default: | |
2637 | break; | |
22d5a71b JB |
2638 | } |
2639 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
2640 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
2641 | int i; | |
2642 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
2643 | synchronize_irq(adapter->msix_entries[i].vector); | |
2644 | } else { | |
2645 | synchronize_irq(adapter->pdev->irq); | |
2646 | } | |
2647 | } | |
2648 | ||
9a799d71 AK |
2649 | /** |
2650 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
2651 | * | |
2652 | **/ | |
2653 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
2654 | { | |
9a799d71 AK |
2655 | struct ixgbe_hw *hw = &adapter->hw; |
2656 | ||
021230d4 | 2657 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
e8e9f696 | 2658 | EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param)); |
9a799d71 | 2659 | |
e8e26350 PW |
2660 | ixgbe_set_ivar(adapter, 0, 0, 0); |
2661 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 AV |
2662 | |
2663 | map_vector_to_rxq(adapter, 0, 0); | |
2664 | map_vector_to_txq(adapter, 0, 0); | |
2665 | ||
396e799c | 2666 | e_info(hw, "Legacy interrupt IVAR setup done\n"); |
9a799d71 AK |
2667 | } |
2668 | ||
43e69bf0 AD |
2669 | /** |
2670 | * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset | |
2671 | * @adapter: board private structure | |
2672 | * @ring: structure containing ring specific data | |
2673 | * | |
2674 | * Configure the Tx descriptor ring after a reset. | |
2675 | **/ | |
84418e3b AD |
2676 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, |
2677 | struct ixgbe_ring *ring) | |
43e69bf0 AD |
2678 | { |
2679 | struct ixgbe_hw *hw = &adapter->hw; | |
2680 | u64 tdba = ring->dma; | |
2f1860b8 AD |
2681 | int wait_loop = 10; |
2682 | u32 txdctl; | |
bf29ee6c | 2683 | u8 reg_idx = ring->reg_idx; |
43e69bf0 | 2684 | |
2f1860b8 AD |
2685 | /* disable queue to avoid issues while updating state */ |
2686 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); | |
2687 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), | |
2688 | txdctl & ~IXGBE_TXDCTL_ENABLE); | |
2689 | IXGBE_WRITE_FLUSH(hw); | |
2690 | ||
43e69bf0 | 2691 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), |
e8e9f696 | 2692 | (tdba & DMA_BIT_MASK(32))); |
43e69bf0 AD |
2693 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); |
2694 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), | |
2695 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
2696 | IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); | |
2697 | IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); | |
84ea2591 | 2698 | ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx); |
43e69bf0 | 2699 | |
2f1860b8 AD |
2700 | /* configure fetching thresholds */ |
2701 | if (adapter->rx_itr_setting == 0) { | |
2702 | /* cannot set wthresh when itr==0 */ | |
2703 | txdctl &= ~0x007F0000; | |
2704 | } else { | |
2705 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ | |
2706 | txdctl |= (8 << 16); | |
2707 | } | |
2708 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
2709 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
2710 | txdctl |= 32; | |
2711 | } | |
2712 | ||
2713 | /* reinitialize flowdirector state */ | |
ee9e0f0b AD |
2714 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2715 | adapter->atr_sample_rate) { | |
2716 | ring->atr_sample_rate = adapter->atr_sample_rate; | |
2717 | ring->atr_count = 0; | |
2718 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); | |
2719 | } else { | |
2720 | ring->atr_sample_rate = 0; | |
2721 | } | |
2f1860b8 | 2722 | |
c84d324c JF |
2723 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); |
2724 | ||
2f1860b8 AD |
2725 | /* enable queue */ |
2726 | txdctl |= IXGBE_TXDCTL_ENABLE; | |
2727 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); | |
2728 | ||
2729 | /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2730 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2731 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2732 | return; | |
2733 | ||
2734 | /* poll to verify queue is enabled */ | |
2735 | do { | |
032b4325 | 2736 | usleep_range(1000, 2000); |
2f1860b8 AD |
2737 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); |
2738 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
2739 | if (!wait_loop) | |
2740 | e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); | |
43e69bf0 AD |
2741 | } |
2742 | ||
120ff942 AD |
2743 | static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) |
2744 | { | |
2745 | struct ixgbe_hw *hw = &adapter->hw; | |
2746 | u32 rttdcs; | |
2747 | u32 mask; | |
2748 | ||
2749 | if (hw->mac.type == ixgbe_mac_82598EB) | |
2750 | return; | |
2751 | ||
2752 | /* disable the arbiter while setting MTQC */ | |
2753 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
2754 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
2755 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2756 | ||
2757 | /* set transmit pool layout */ | |
2758 | mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED); | |
2759 | switch (adapter->flags & mask) { | |
2760 | ||
2761 | case (IXGBE_FLAG_SRIOV_ENABLED): | |
2762 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2763 | (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF)); | |
2764 | break; | |
2765 | ||
2766 | case (IXGBE_FLAG_DCB_ENABLED): | |
2767 | /* We enable 8 traffic classes, DCB only */ | |
2768 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2769 | (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ)); | |
2770 | break; | |
2771 | ||
2772 | default: | |
2773 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB); | |
2774 | break; | |
2775 | } | |
2776 | ||
2777 | /* re-enable the arbiter */ | |
2778 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2779 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2780 | } | |
2781 | ||
9a799d71 | 2782 | /** |
3a581073 | 2783 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
2784 | * @adapter: board private structure |
2785 | * | |
2786 | * Configure the Tx unit of the MAC after a reset. | |
2787 | **/ | |
2788 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
2789 | { | |
2f1860b8 AD |
2790 | struct ixgbe_hw *hw = &adapter->hw; |
2791 | u32 dmatxctl; | |
43e69bf0 | 2792 | u32 i; |
9a799d71 | 2793 | |
2f1860b8 AD |
2794 | ixgbe_setup_mtqc(adapter); |
2795 | ||
2796 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
2797 | /* DMATXCTL.EN must be before Tx queues are enabled */ | |
2798 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2799 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2800 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2801 | } | |
2802 | ||
9a799d71 | 2803 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
43e69bf0 AD |
2804 | for (i = 0; i < adapter->num_tx_queues; i++) |
2805 | ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
2806 | } |
2807 | ||
e8e26350 | 2808 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2809 | |
a6616b42 | 2810 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
e8e9f696 | 2811 | struct ixgbe_ring *rx_ring) |
cc41ac7c | 2812 | { |
cc41ac7c | 2813 | u32 srrctl; |
bf29ee6c | 2814 | u8 reg_idx = rx_ring->reg_idx; |
3be1adfb | 2815 | |
bd508178 AD |
2816 | switch (adapter->hw.mac.type) { |
2817 | case ixgbe_mac_82598EB: { | |
2818 | struct ixgbe_ring_feature *feature = adapter->ring_feature; | |
2819 | const int mask = feature[RING_F_RSS].mask; | |
bf29ee6c | 2820 | reg_idx = reg_idx & mask; |
cc41ac7c | 2821 | } |
bd508178 AD |
2822 | break; |
2823 | case ixgbe_mac_82599EB: | |
b93a2226 | 2824 | case ixgbe_mac_X540: |
bd508178 AD |
2825 | default: |
2826 | break; | |
2827 | } | |
2828 | ||
bf29ee6c | 2829 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx)); |
cc41ac7c JB |
2830 | |
2831 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2832 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
9e10e045 AD |
2833 | if (adapter->num_vfs) |
2834 | srrctl |= IXGBE_SRRCTL_DROP_EN; | |
cc41ac7c | 2835 | |
afafd5b0 AD |
2836 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
2837 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2838 | ||
7d637bcc | 2839 | if (ring_is_ps_enabled(rx_ring)) { |
afafd5b0 AD |
2840 | #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER |
2841 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2842 | #else | |
2843 | srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2844 | #endif | |
cc41ac7c | 2845 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
cc41ac7c | 2846 | } else { |
afafd5b0 AD |
2847 | srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >> |
2848 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
cc41ac7c | 2849 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
cc41ac7c | 2850 | } |
e8e26350 | 2851 | |
bf29ee6c | 2852 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl); |
cc41ac7c | 2853 | } |
9a799d71 | 2854 | |
05abb126 | 2855 | static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
0cefafad | 2856 | { |
05abb126 AD |
2857 | struct ixgbe_hw *hw = &adapter->hw; |
2858 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, | |
e8e9f696 JP |
2859 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, |
2860 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
05abb126 AD |
2861 | u32 mrqc = 0, reta = 0; |
2862 | u32 rxcsum; | |
2863 | int i, j; | |
0cefafad JB |
2864 | int mask; |
2865 | ||
05abb126 AD |
2866 | /* Fill out hash function seeds */ |
2867 | for (i = 0; i < 10; i++) | |
2868 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); | |
2869 | ||
2870 | /* Fill out redirection table */ | |
2871 | for (i = 0, j = 0; i < 128; i++, j++) { | |
2872 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
2873 | j = 0; | |
2874 | /* reta = 4-byte sliding window of | |
2875 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2876 | reta = (reta << 8) | (j * 0x11); | |
2877 | if ((i & 3) == 3) | |
2878 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
2879 | } | |
0cefafad | 2880 | |
05abb126 AD |
2881 | /* Disable indicating checksum in descriptor, enables RSS hash */ |
2882 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
2883 | rxcsum |= IXGBE_RXCSUM_PCSD; | |
2884 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
2885 | ||
2886 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
2887 | mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED; | |
2888 | else | |
2889 | mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
0cefafad | 2890 | #ifdef CONFIG_IXGBE_DCB |
05abb126 | 2891 | | IXGBE_FLAG_DCB_ENABLED |
0cefafad | 2892 | #endif |
05abb126 AD |
2893 | | IXGBE_FLAG_SRIOV_ENABLED |
2894 | ); | |
0cefafad JB |
2895 | |
2896 | switch (mask) { | |
8187cd48 JF |
2897 | #ifdef CONFIG_IXGBE_DCB |
2898 | case (IXGBE_FLAG_DCB_ENABLED | IXGBE_FLAG_RSS_ENABLED): | |
2899 | mrqc = IXGBE_MRQC_RTRSS8TCEN; | |
2900 | break; | |
2901 | case (IXGBE_FLAG_DCB_ENABLED): | |
2902 | mrqc = IXGBE_MRQC_RT8TCEN; | |
2903 | break; | |
2904 | #endif /* CONFIG_IXGBE_DCB */ | |
0cefafad JB |
2905 | case (IXGBE_FLAG_RSS_ENABLED): |
2906 | mrqc = IXGBE_MRQC_RSSEN; | |
2907 | break; | |
1cdd1ec8 GR |
2908 | case (IXGBE_FLAG_SRIOV_ENABLED): |
2909 | mrqc = IXGBE_MRQC_VMDQEN; | |
2910 | break; | |
0cefafad JB |
2911 | default: |
2912 | break; | |
2913 | } | |
2914 | ||
05abb126 AD |
2915 | /* Perform hash on these packet types */ |
2916 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 | |
2917 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
2918 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
2919 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; | |
2920 | ||
2921 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); | |
0cefafad JB |
2922 | } |
2923 | ||
b93a2226 DS |
2924 | /** |
2925 | * ixgbe_clear_rscctl - disable RSC for the indicated ring | |
2926 | * @adapter: address of board private structure | |
2927 | * @ring: structure containing ring specific data | |
2928 | **/ | |
2929 | void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter, | |
2930 | struct ixgbe_ring *ring) | |
2931 | { | |
2932 | struct ixgbe_hw *hw = &adapter->hw; | |
2933 | u32 rscctrl; | |
2934 | u8 reg_idx = ring->reg_idx; | |
2935 | ||
2936 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); | |
2937 | rscctrl &= ~IXGBE_RSCCTL_RSCEN; | |
2938 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); | |
2939 | } | |
2940 | ||
bb5a9ad2 NS |
2941 | /** |
2942 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
2943 | * @adapter: address of board private structure | |
2944 | * @index: index of ring to set | |
bb5a9ad2 | 2945 | **/ |
b93a2226 | 2946 | void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
7367096a | 2947 | struct ixgbe_ring *ring) |
bb5a9ad2 | 2948 | { |
bb5a9ad2 | 2949 | struct ixgbe_hw *hw = &adapter->hw; |
bb5a9ad2 | 2950 | u32 rscctrl; |
edd2ea55 | 2951 | int rx_buf_len; |
bf29ee6c | 2952 | u8 reg_idx = ring->reg_idx; |
7367096a | 2953 | |
7d637bcc | 2954 | if (!ring_is_rsc_enabled(ring)) |
7367096a | 2955 | return; |
bb5a9ad2 | 2956 | |
7367096a AD |
2957 | rx_buf_len = ring->rx_buf_len; |
2958 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); | |
bb5a9ad2 NS |
2959 | rscctrl |= IXGBE_RSCCTL_RSCEN; |
2960 | /* | |
2961 | * we must limit the number of descriptors so that the | |
2962 | * total size of max desc * buf_len is not greater | |
2963 | * than 65535 | |
2964 | */ | |
7d637bcc | 2965 | if (ring_is_ps_enabled(ring)) { |
bb5a9ad2 NS |
2966 | #if (MAX_SKB_FRAGS > 16) |
2967 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2968 | #elif (MAX_SKB_FRAGS > 8) | |
2969 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2970 | #elif (MAX_SKB_FRAGS > 4) | |
2971 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2972 | #else | |
2973 | rscctrl |= IXGBE_RSCCTL_MAXDESC_1; | |
2974 | #endif | |
2975 | } else { | |
2976 | if (rx_buf_len < IXGBE_RXBUFFER_4096) | |
2977 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2978 | else if (rx_buf_len < IXGBE_RXBUFFER_8192) | |
2979 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2980 | else | |
2981 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2982 | } | |
7367096a | 2983 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); |
bb5a9ad2 NS |
2984 | } |
2985 | ||
9e10e045 AD |
2986 | /** |
2987 | * ixgbe_set_uta - Set unicast filter table address | |
2988 | * @adapter: board private structure | |
2989 | * | |
2990 | * The unicast table address is a register array of 32-bit registers. | |
2991 | * The table is meant to be used in a way similar to how the MTA is used | |
2992 | * however due to certain limitations in the hardware it is necessary to | |
2993 | * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous | |
2994 | * enable bit to allow vlan tag stripping when promiscuous mode is enabled | |
2995 | **/ | |
2996 | static void ixgbe_set_uta(struct ixgbe_adapter *adapter) | |
2997 | { | |
2998 | struct ixgbe_hw *hw = &adapter->hw; | |
2999 | int i; | |
3000 | ||
3001 | /* The UTA table only exists on 82599 hardware and newer */ | |
3002 | if (hw->mac.type < ixgbe_mac_82599EB) | |
3003 | return; | |
3004 | ||
3005 | /* we only need to do this if VMDq is enabled */ | |
3006 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
3007 | return; | |
3008 | ||
3009 | for (i = 0; i < 128; i++) | |
3010 | IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); | |
3011 | } | |
3012 | ||
3013 | #define IXGBE_MAX_RX_DESC_POLL 10 | |
3014 | static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
3015 | struct ixgbe_ring *ring) | |
3016 | { | |
3017 | struct ixgbe_hw *hw = &adapter->hw; | |
9e10e045 AD |
3018 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; |
3019 | u32 rxdctl; | |
bf29ee6c | 3020 | u8 reg_idx = ring->reg_idx; |
9e10e045 AD |
3021 | |
3022 | /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
3023 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3024 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3025 | return; | |
3026 | ||
3027 | do { | |
032b4325 | 3028 | usleep_range(1000, 2000); |
9e10e045 AD |
3029 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
3030 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3031 | ||
3032 | if (!wait_loop) { | |
3033 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " | |
3034 | "the polling period\n", reg_idx); | |
3035 | } | |
3036 | } | |
3037 | ||
2d39d576 YZ |
3038 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
3039 | struct ixgbe_ring *ring) | |
3040 | { | |
3041 | struct ixgbe_hw *hw = &adapter->hw; | |
3042 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; | |
3043 | u32 rxdctl; | |
3044 | u8 reg_idx = ring->reg_idx; | |
3045 | ||
3046 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3047 | rxdctl &= ~IXGBE_RXDCTL_ENABLE; | |
3048 | ||
3049 | /* write value back with RXDCTL.ENABLE bit cleared */ | |
3050 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3051 | ||
3052 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3053 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3054 | return; | |
3055 | ||
3056 | /* the hardware may take up to 100us to really disable the rx queue */ | |
3057 | do { | |
3058 | udelay(10); | |
3059 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3060 | } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3061 | ||
3062 | if (!wait_loop) { | |
3063 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " | |
3064 | "the polling period\n", reg_idx); | |
3065 | } | |
3066 | } | |
3067 | ||
84418e3b AD |
3068 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, |
3069 | struct ixgbe_ring *ring) | |
acd37177 AD |
3070 | { |
3071 | struct ixgbe_hw *hw = &adapter->hw; | |
3072 | u64 rdba = ring->dma; | |
9e10e045 | 3073 | u32 rxdctl; |
bf29ee6c | 3074 | u8 reg_idx = ring->reg_idx; |
acd37177 | 3075 | |
9e10e045 AD |
3076 | /* disable queue to avoid issues while updating state */ |
3077 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2d39d576 | 3078 | ixgbe_disable_rx_queue(adapter, ring); |
9e10e045 | 3079 | |
acd37177 AD |
3080 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); |
3081 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); | |
3082 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), | |
3083 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
3084 | IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); | |
3085 | IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); | |
84ea2591 | 3086 | ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx); |
9e10e045 AD |
3087 | |
3088 | ixgbe_configure_srrctl(adapter, ring); | |
3089 | ixgbe_configure_rscctl(adapter, ring); | |
3090 | ||
e9f98072 GR |
3091 | /* If operating in IOV mode set RLPML for X540 */ |
3092 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
3093 | hw->mac.type == ixgbe_mac_X540) { | |
3094 | rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK; | |
3095 | rxdctl |= ((ring->netdev->mtu + ETH_HLEN + | |
3096 | ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN); | |
3097 | } | |
3098 | ||
9e10e045 AD |
3099 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3100 | /* | |
3101 | * enable cache line friendly hardware writes: | |
3102 | * PTHRESH=32 descriptors (half the internal cache), | |
3103 | * this also removes ugly rx_no_buffer_count increment | |
3104 | * HTHRESH=4 descriptors (to minimize latency on fetch) | |
3105 | * WTHRESH=8 burst writeback up to two cache lines | |
3106 | */ | |
3107 | rxdctl &= ~0x3FFFFF; | |
3108 | rxdctl |= 0x080420; | |
3109 | } | |
3110 | ||
3111 | /* enable receive descriptor ring */ | |
3112 | rxdctl |= IXGBE_RXDCTL_ENABLE; | |
3113 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3114 | ||
3115 | ixgbe_rx_desc_queue_enable(adapter, ring); | |
fc77dc3c | 3116 | ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring)); |
acd37177 AD |
3117 | } |
3118 | ||
48654521 AD |
3119 | static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) |
3120 | { | |
3121 | struct ixgbe_hw *hw = &adapter->hw; | |
3122 | int p; | |
3123 | ||
3124 | /* PSRTYPE must be initialized in non 82598 adapters */ | |
3125 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
e8e9f696 JP |
3126 | IXGBE_PSRTYPE_UDPHDR | |
3127 | IXGBE_PSRTYPE_IPV4HDR | | |
48654521 | 3128 | IXGBE_PSRTYPE_L2HDR | |
e8e9f696 | 3129 | IXGBE_PSRTYPE_IPV6HDR; |
48654521 AD |
3130 | |
3131 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3132 | return; | |
3133 | ||
3134 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) | |
3135 | psrtype |= (adapter->num_rx_queues_per_pool << 29); | |
3136 | ||
3137 | for (p = 0; p < adapter->num_rx_pools; p++) | |
3138 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p), | |
3139 | psrtype); | |
3140 | } | |
3141 | ||
f5b4a52e AD |
3142 | static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) |
3143 | { | |
3144 | struct ixgbe_hw *hw = &adapter->hw; | |
3145 | u32 gcr_ext; | |
3146 | u32 vt_reg_bits; | |
3147 | u32 reg_offset, vf_shift; | |
3148 | u32 vmdctl; | |
3149 | ||
3150 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
3151 | return; | |
3152 | ||
3153 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
3154 | vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN; | |
3155 | vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT); | |
3156 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits); | |
3157 | ||
3158 | vf_shift = adapter->num_vfs % 32; | |
3159 | reg_offset = (adapter->num_vfs > 32) ? 1 : 0; | |
3160 | ||
3161 | /* Enable only the PF's pool for Tx/Rx */ | |
3162 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift)); | |
3163 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0); | |
3164 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift)); | |
3165 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0); | |
3166 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
3167 | ||
3168 | /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ | |
3169 | hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs); | |
3170 | ||
3171 | /* | |
3172 | * Set up VF register offsets for selected VT Mode, | |
3173 | * i.e. 32 or 64 VFs for SR-IOV | |
3174 | */ | |
3175 | gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
3176 | gcr_ext |= IXGBE_GCR_EXT_MSIX_EN; | |
3177 | gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64; | |
3178 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); | |
3179 | ||
3180 | /* enable Tx loopback for VF/PF communication */ | |
3181 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
a985b6c3 GR |
3182 | /* Enable MAC Anti-Spoofing */ |
3183 | hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0), | |
3184 | adapter->num_vfs); | |
f5b4a52e AD |
3185 | } |
3186 | ||
477de6ed | 3187 | static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) |
9a799d71 | 3188 | { |
9a799d71 AK |
3189 | struct ixgbe_hw *hw = &adapter->hw; |
3190 | struct net_device *netdev = adapter->netdev; | |
3191 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
7c6e0a43 | 3192 | int rx_buf_len; |
477de6ed AD |
3193 | struct ixgbe_ring *rx_ring; |
3194 | int i; | |
3195 | u32 mhadd, hlreg0; | |
48654521 | 3196 | |
9a799d71 | 3197 | /* Decide whether to use packet split mode or not */ |
a124339a DS |
3198 | /* On by default */ |
3199 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; | |
3200 | ||
1cdd1ec8 | 3201 | /* Do not use packet split if we're in SR-IOV Mode */ |
a124339a DS |
3202 | if (adapter->num_vfs) |
3203 | adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED; | |
3204 | ||
3205 | /* Disable packet split due to 82599 erratum #45 */ | |
3206 | if (hw->mac.type == ixgbe_mac_82599EB) | |
3207 | adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED; | |
9a799d71 AK |
3208 | |
3209 | /* Set the RX buffer length according to the mode */ | |
3210 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 3211 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
9a799d71 | 3212 | } else { |
0c19d6af | 3213 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && |
f8212f97 | 3214 | (netdev->mtu <= ETH_DATA_LEN)) |
7c6e0a43 | 3215 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 3216 | else |
477de6ed | 3217 | rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024); |
9a799d71 AK |
3218 | } |
3219 | ||
63f39bd1 | 3220 | #ifdef IXGBE_FCOE |
477de6ed AD |
3221 | /* adjust max frame to be able to do baby jumbo for FCoE */ |
3222 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
3223 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
3224 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9a799d71 | 3225 | |
477de6ed AD |
3226 | #endif /* IXGBE_FCOE */ |
3227 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); | |
3228 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { | |
3229 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
3230 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
3231 | ||
3232 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
3233 | } | |
3234 | ||
3235 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
3236 | /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ | |
3237 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
3238 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
9a799d71 | 3239 | |
0cefafad JB |
3240 | /* |
3241 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3242 | * the Base and Length of the Rx Descriptor Ring | |
3243 | */ | |
9a799d71 | 3244 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 3245 | rx_ring = adapter->rx_ring[i]; |
a6616b42 | 3246 | rx_ring->rx_buf_len = rx_buf_len; |
cc41ac7c | 3247 | |
6e455b89 | 3248 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) |
7d637bcc AD |
3249 | set_ring_ps_enabled(rx_ring); |
3250 | else | |
3251 | clear_ring_ps_enabled(rx_ring); | |
3252 | ||
3253 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) | |
3254 | set_ring_rsc_enabled(rx_ring); | |
1b3ff02e | 3255 | else |
7d637bcc | 3256 | clear_ring_rsc_enabled(rx_ring); |
cc41ac7c | 3257 | |
63f39bd1 | 3258 | #ifdef IXGBE_FCOE |
e8e9f696 | 3259 | if (netdev->features & NETIF_F_FCOE_MTU) { |
63f39bd1 YZ |
3260 | struct ixgbe_ring_feature *f; |
3261 | f = &adapter->ring_feature[RING_F_FCOE]; | |
6e455b89 | 3262 | if ((i >= f->mask) && (i < f->mask + f->indices)) { |
7d637bcc | 3263 | clear_ring_ps_enabled(rx_ring); |
6e455b89 YZ |
3264 | if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) |
3265 | rx_ring->rx_buf_len = | |
e8e9f696 | 3266 | IXGBE_FCOE_JUMBO_FRAME_SIZE; |
7d637bcc AD |
3267 | } else if (!ring_is_rsc_enabled(rx_ring) && |
3268 | !ring_is_ps_enabled(rx_ring)) { | |
3269 | rx_ring->rx_buf_len = | |
3270 | IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
6e455b89 | 3271 | } |
63f39bd1 | 3272 | } |
63f39bd1 | 3273 | #endif /* IXGBE_FCOE */ |
477de6ed | 3274 | } |
477de6ed AD |
3275 | } |
3276 | ||
7367096a AD |
3277 | static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) |
3278 | { | |
3279 | struct ixgbe_hw *hw = &adapter->hw; | |
3280 | u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
3281 | ||
3282 | switch (hw->mac.type) { | |
3283 | case ixgbe_mac_82598EB: | |
3284 | /* | |
3285 | * For VMDq support of different descriptor types or | |
3286 | * buffer sizes through the use of multiple SRRCTL | |
3287 | * registers, RDRXCTL.MVMEN must be set to 1 | |
3288 | * | |
3289 | * also, the manual doesn't mention it clearly but DCA hints | |
3290 | * will only use queue 0's tags unless this bit is set. Side | |
3291 | * effects of setting this bit are only that SRRCTL must be | |
3292 | * fully programmed [0..15] | |
3293 | */ | |
3294 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
3295 | break; | |
3296 | case ixgbe_mac_82599EB: | |
b93a2226 | 3297 | case ixgbe_mac_X540: |
7367096a AD |
3298 | /* Disable RSC for ACK packets */ |
3299 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
3300 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
3301 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; | |
3302 | /* hardware requires some bits to be set by default */ | |
3303 | rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); | |
3304 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
3305 | break; | |
3306 | default: | |
3307 | /* We should do nothing since we don't know this hardware */ | |
3308 | return; | |
3309 | } | |
3310 | ||
3311 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
3312 | } | |
3313 | ||
477de6ed AD |
3314 | /** |
3315 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset | |
3316 | * @adapter: board private structure | |
3317 | * | |
3318 | * Configure the Rx unit of the MAC after a reset. | |
3319 | **/ | |
3320 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
3321 | { | |
3322 | struct ixgbe_hw *hw = &adapter->hw; | |
477de6ed AD |
3323 | int i; |
3324 | u32 rxctrl; | |
477de6ed AD |
3325 | |
3326 | /* disable receives while setting up the descriptors */ | |
3327 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
3328 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
3329 | ||
3330 | ixgbe_setup_psrtype(adapter); | |
7367096a | 3331 | ixgbe_setup_rdrxctl(adapter); |
477de6ed | 3332 | |
9e10e045 | 3333 | /* Program registers for the distribution of queues */ |
f5b4a52e | 3334 | ixgbe_setup_mrqc(adapter); |
f5b4a52e | 3335 | |
9e10e045 AD |
3336 | ixgbe_set_uta(adapter); |
3337 | ||
477de6ed AD |
3338 | /* set_rx_buffer_len must be called before ring initialization */ |
3339 | ixgbe_set_rx_buffer_len(adapter); | |
3340 | ||
3341 | /* | |
3342 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3343 | * the Base and Length of the Rx Descriptor Ring | |
3344 | */ | |
9e10e045 AD |
3345 | for (i = 0; i < adapter->num_rx_queues; i++) |
3346 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
177db6ff | 3347 | |
9e10e045 AD |
3348 | /* disable drop enable for 82598 parts */ |
3349 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3350 | rxctrl |= IXGBE_RXCTRL_DMBYPS; | |
3351 | ||
3352 | /* enable all receives */ | |
3353 | rxctrl |= IXGBE_RXCTRL_RXEN; | |
3354 | hw->mac.ops.enable_rx_dma(hw, rxctrl); | |
9a799d71 AK |
3355 | } |
3356 | ||
068c89b0 DS |
3357 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
3358 | { | |
3359 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3360 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3361 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
3362 | |
3363 | /* add VID to filter table */ | |
1ada1b1b | 3364 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true); |
f62bbb5e | 3365 | set_bit(vid, adapter->active_vlans); |
068c89b0 DS |
3366 | } |
3367 | ||
3368 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
3369 | { | |
3370 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3371 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3372 | int pool_ndx = adapter->num_vfs; |
068c89b0 | 3373 | |
068c89b0 | 3374 | /* remove VID from filter table */ |
1ada1b1b | 3375 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false); |
f62bbb5e | 3376 | clear_bit(vid, adapter->active_vlans); |
068c89b0 DS |
3377 | } |
3378 | ||
5f6c0181 JB |
3379 | /** |
3380 | * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering | |
3381 | * @adapter: driver data | |
3382 | */ | |
3383 | static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter) | |
3384 | { | |
3385 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e JG |
3386 | u32 vlnctrl; |
3387 | ||
3388 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3389 | vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); | |
3390 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3391 | } | |
3392 | ||
3393 | /** | |
3394 | * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering | |
3395 | * @adapter: driver data | |
3396 | */ | |
3397 | static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter) | |
3398 | { | |
3399 | struct ixgbe_hw *hw = &adapter->hw; | |
3400 | u32 vlnctrl; | |
3401 | ||
3402 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3403 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
3404 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
3405 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3406 | } | |
3407 | ||
3408 | /** | |
3409 | * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping | |
3410 | * @adapter: driver data | |
3411 | */ | |
3412 | static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) | |
3413 | { | |
3414 | struct ixgbe_hw *hw = &adapter->hw; | |
3415 | u32 vlnctrl; | |
5f6c0181 JB |
3416 | int i, j; |
3417 | ||
3418 | switch (hw->mac.type) { | |
3419 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3420 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3421 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3422 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3423 | break; | |
3424 | case ixgbe_mac_82599EB: | |
b93a2226 | 3425 | case ixgbe_mac_X540: |
5f6c0181 JB |
3426 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3427 | j = adapter->rx_ring[i]->reg_idx; | |
3428 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3429 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
3430 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3431 | } | |
3432 | break; | |
3433 | default: | |
3434 | break; | |
3435 | } | |
3436 | } | |
3437 | ||
3438 | /** | |
f62bbb5e | 3439 | * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping |
5f6c0181 JB |
3440 | * @adapter: driver data |
3441 | */ | |
f62bbb5e | 3442 | static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) |
5f6c0181 JB |
3443 | { |
3444 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e | 3445 | u32 vlnctrl; |
5f6c0181 JB |
3446 | int i, j; |
3447 | ||
3448 | switch (hw->mac.type) { | |
3449 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3450 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3451 | vlnctrl |= IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3452 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3453 | break; | |
3454 | case ixgbe_mac_82599EB: | |
b93a2226 | 3455 | case ixgbe_mac_X540: |
5f6c0181 JB |
3456 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3457 | j = adapter->rx_ring[i]->reg_idx; | |
3458 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3459 | vlnctrl |= IXGBE_RXDCTL_VME; | |
3460 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3461 | } | |
3462 | break; | |
3463 | default: | |
3464 | break; | |
3465 | } | |
3466 | } | |
3467 | ||
9a799d71 AK |
3468 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
3469 | { | |
f62bbb5e | 3470 | u16 vid; |
9a799d71 | 3471 | |
f62bbb5e JG |
3472 | ixgbe_vlan_rx_add_vid(adapter->netdev, 0); |
3473 | ||
3474 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) | |
3475 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
9a799d71 AK |
3476 | } |
3477 | ||
2850062a AD |
3478 | /** |
3479 | * ixgbe_write_uc_addr_list - write unicast addresses to RAR table | |
3480 | * @netdev: network interface device structure | |
3481 | * | |
3482 | * Writes unicast address list to the RAR table. | |
3483 | * Returns: -ENOMEM on failure/insufficient address space | |
3484 | * 0 on no addresses written | |
3485 | * X on writing X addresses to the RAR table | |
3486 | **/ | |
3487 | static int ixgbe_write_uc_addr_list(struct net_device *netdev) | |
3488 | { | |
3489 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3490 | struct ixgbe_hw *hw = &adapter->hw; | |
3491 | unsigned int vfn = adapter->num_vfs; | |
3492 | unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1); | |
3493 | int count = 0; | |
3494 | ||
3495 | /* return ENOMEM indicating insufficient memory for addresses */ | |
3496 | if (netdev_uc_count(netdev) > rar_entries) | |
3497 | return -ENOMEM; | |
3498 | ||
3499 | if (!netdev_uc_empty(netdev) && rar_entries) { | |
3500 | struct netdev_hw_addr *ha; | |
3501 | /* return error if we do not support writing to RAR table */ | |
3502 | if (!hw->mac.ops.set_rar) | |
3503 | return -ENOMEM; | |
3504 | ||
3505 | netdev_for_each_uc_addr(ha, netdev) { | |
3506 | if (!rar_entries) | |
3507 | break; | |
3508 | hw->mac.ops.set_rar(hw, rar_entries--, ha->addr, | |
3509 | vfn, IXGBE_RAH_AV); | |
3510 | count++; | |
3511 | } | |
3512 | } | |
3513 | /* write the addresses in reverse order to avoid write combining */ | |
3514 | for (; rar_entries > 0 ; rar_entries--) | |
3515 | hw->mac.ops.clear_rar(hw, rar_entries); | |
3516 | ||
3517 | return count; | |
3518 | } | |
3519 | ||
9a799d71 | 3520 | /** |
2c5645cf | 3521 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
3522 | * @netdev: network interface device structure |
3523 | * | |
2c5645cf CL |
3524 | * The set_rx_method entry point is called whenever the unicast/multicast |
3525 | * address list or the network interface flags are updated. This routine is | |
3526 | * responsible for configuring the hardware for proper unicast, multicast and | |
3527 | * promiscuous mode. | |
9a799d71 | 3528 | **/ |
7f870475 | 3529 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
3530 | { |
3531 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3532 | struct ixgbe_hw *hw = &adapter->hw; | |
2850062a AD |
3533 | u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; |
3534 | int count; | |
9a799d71 AK |
3535 | |
3536 | /* Check for Promiscuous and All Multicast modes */ | |
3537 | ||
3538 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3539 | ||
f5dc442b AD |
3540 | /* set all bits that we expect to always be set */ |
3541 | fctrl |= IXGBE_FCTRL_BAM; | |
3542 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ | |
3543 | fctrl |= IXGBE_FCTRL_PMCF; | |
3544 | ||
2850062a AD |
3545 | /* clear the bits we are changing the status of */ |
3546 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
3547 | ||
9a799d71 | 3548 | if (netdev->flags & IFF_PROMISC) { |
e433ea1f | 3549 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 3550 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
2850062a | 3551 | vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE); |
5f6c0181 JB |
3552 | /* don't hardware filter vlans in promisc mode */ |
3553 | ixgbe_vlan_filter_disable(adapter); | |
9a799d71 | 3554 | } else { |
746b9f02 PM |
3555 | if (netdev->flags & IFF_ALLMULTI) { |
3556 | fctrl |= IXGBE_FCTRL_MPE; | |
2850062a AD |
3557 | vmolr |= IXGBE_VMOLR_MPE; |
3558 | } else { | |
3559 | /* | |
3560 | * Write addresses to the MTA, if the attempt fails | |
25985edc | 3561 | * then we should just turn on promiscuous mode so |
2850062a AD |
3562 | * that we can at least receive multicast traffic |
3563 | */ | |
3564 | hw->mac.ops.update_mc_addr_list(hw, netdev); | |
3565 | vmolr |= IXGBE_VMOLR_ROMPE; | |
746b9f02 | 3566 | } |
5f6c0181 | 3567 | ixgbe_vlan_filter_enable(adapter); |
e433ea1f | 3568 | hw->addr_ctrl.user_set_promisc = false; |
2850062a AD |
3569 | /* |
3570 | * Write addresses to available RAR registers, if there is not | |
3571 | * sufficient space to store all the addresses then enable | |
25985edc | 3572 | * unicast promiscuous mode |
2850062a AD |
3573 | */ |
3574 | count = ixgbe_write_uc_addr_list(netdev); | |
3575 | if (count < 0) { | |
3576 | fctrl |= IXGBE_FCTRL_UPE; | |
3577 | vmolr |= IXGBE_VMOLR_ROPE; | |
3578 | } | |
9a799d71 AK |
3579 | } |
3580 | ||
2850062a | 3581 | if (adapter->num_vfs) { |
1cdd1ec8 | 3582 | ixgbe_restore_vf_multicasts(adapter); |
2850062a AD |
3583 | vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) & |
3584 | ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | | |
3585 | IXGBE_VMOLR_ROPE); | |
3586 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr); | |
3587 | } | |
3588 | ||
3589 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
f62bbb5e JG |
3590 | |
3591 | if (netdev->features & NETIF_F_HW_VLAN_RX) | |
3592 | ixgbe_vlan_strip_enable(adapter); | |
3593 | else | |
3594 | ixgbe_vlan_strip_disable(adapter); | |
9a799d71 AK |
3595 | } |
3596 | ||
021230d4 AV |
3597 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
3598 | { | |
3599 | int q_idx; | |
3600 | struct ixgbe_q_vector *q_vector; | |
3601 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3602 | ||
3603 | /* legacy and MSI only use one vector */ | |
3604 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3605 | q_vectors = 1; | |
3606 | ||
3607 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 3608 | struct napi_struct *napi; |
7a921c93 | 3609 | q_vector = adapter->q_vector[q_idx]; |
f0848276 | 3610 | napi = &q_vector->napi; |
91281fd3 AD |
3611 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
3612 | if (!q_vector->rxr_count || !q_vector->txr_count) { | |
3613 | if (q_vector->txr_count == 1) | |
3614 | napi->poll = &ixgbe_clean_txonly; | |
3615 | else if (q_vector->rxr_count == 1) | |
3616 | napi->poll = &ixgbe_clean_rxonly; | |
3617 | } | |
3618 | } | |
f0848276 JB |
3619 | |
3620 | napi_enable(napi); | |
021230d4 AV |
3621 | } |
3622 | } | |
3623 | ||
3624 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
3625 | { | |
3626 | int q_idx; | |
3627 | struct ixgbe_q_vector *q_vector; | |
3628 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3629 | ||
3630 | /* legacy and MSI only use one vector */ | |
3631 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3632 | q_vectors = 1; | |
3633 | ||
3634 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 3635 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
3636 | napi_disable(&q_vector->napi); |
3637 | } | |
3638 | } | |
3639 | ||
7a6b6f51 | 3640 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3641 | /* |
3642 | * ixgbe_configure_dcb - Configure DCB hardware | |
3643 | * @adapter: ixgbe adapter struct | |
3644 | * | |
3645 | * This is called by the driver on open to configure the DCB hardware. | |
3646 | * This is also called by the gennetlink interface when reconfiguring | |
3647 | * the DCB state. | |
3648 | */ | |
3649 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
3650 | { | |
3651 | struct ixgbe_hw *hw = &adapter->hw; | |
9806307a | 3652 | int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
2f90b865 | 3653 | |
67ebd791 AD |
3654 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { |
3655 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3656 | netif_set_gso_max_size(adapter->netdev, 65536); | |
3657 | return; | |
3658 | } | |
3659 | ||
3660 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3661 | netif_set_gso_max_size(adapter->netdev, 32768); | |
3662 | ||
2f90b865 | 3663 | |
2f90b865 | 3664 | /* Enable VLAN tag insert/strip */ |
f62bbb5e | 3665 | adapter->netdev->features |= NETIF_F_HW_VLAN_RX; |
5f6c0181 | 3666 | |
2f90b865 | 3667 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
01fa7d90 AD |
3668 | |
3669 | /* reconfigure the hardware */ | |
c27931da JF |
3670 | if (adapter->dcbx_cap & (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE)) { |
3671 | #ifdef CONFIG_FCOE | |
3672 | if (adapter->netdev->features & NETIF_F_FCOE_MTU) | |
3673 | max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); | |
3674 | #endif | |
3675 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
3676 | DCB_TX_CONFIG); | |
3677 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
3678 | DCB_RX_CONFIG); | |
3679 | ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); | |
3680 | } else { | |
3681 | struct net_device *dev = adapter->netdev; | |
3682 | ||
3683 | if (adapter->ixgbe_ieee_ets) | |
3684 | dev->dcbnl_ops->ieee_setets(dev, | |
3685 | adapter->ixgbe_ieee_ets); | |
3686 | if (adapter->ixgbe_ieee_pfc) | |
3687 | dev->dcbnl_ops->ieee_setpfc(dev, | |
3688 | adapter->ixgbe_ieee_pfc); | |
3689 | } | |
8187cd48 JF |
3690 | |
3691 | /* Enable RSS Hash per TC */ | |
3692 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
3693 | int i; | |
3694 | u32 reg = 0; | |
3695 | ||
3696 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
3697 | u8 msb = 0; | |
3698 | u8 cnt = adapter->netdev->tc_to_txq[i].count; | |
3699 | ||
3700 | while (cnt >>= 1) | |
3701 | msb++; | |
3702 | ||
3703 | reg |= msb << IXGBE_RQTC_SHIFT_TC(i); | |
3704 | } | |
3705 | IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg); | |
3706 | } | |
2f90b865 AD |
3707 | } |
3708 | ||
3709 | #endif | |
9a799d71 AK |
3710 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
3711 | { | |
3712 | struct net_device *netdev = adapter->netdev; | |
c4cf55e5 | 3713 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
3714 | int i; |
3715 | ||
7a6b6f51 | 3716 | #ifdef CONFIG_IXGBE_DCB |
67ebd791 | 3717 | ixgbe_configure_dcb(adapter); |
2f90b865 | 3718 | #endif |
9a799d71 | 3719 | |
f62bbb5e JG |
3720 | ixgbe_set_rx_mode(netdev); |
3721 | ixgbe_restore_vlan(adapter); | |
3722 | ||
eacd73f7 YZ |
3723 | #ifdef IXGBE_FCOE |
3724 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
3725 | ixgbe_configure_fcoe(adapter); | |
3726 | ||
3727 | #endif /* IXGBE_FCOE */ | |
c4cf55e5 PWJ |
3728 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
3729 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 3730 | adapter->tx_ring[i]->atr_sample_rate = |
e8e9f696 | 3731 | adapter->atr_sample_rate; |
c4cf55e5 PWJ |
3732 | ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc); |
3733 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { | |
3734 | ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc); | |
3735 | } | |
933d41f1 | 3736 | ixgbe_configure_virtualization(adapter); |
c4cf55e5 | 3737 | |
9a799d71 AK |
3738 | ixgbe_configure_tx(adapter); |
3739 | ixgbe_configure_rx(adapter); | |
9a799d71 AK |
3740 | } |
3741 | ||
e8e26350 PW |
3742 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
3743 | { | |
3744 | switch (hw->phy.type) { | |
3745 | case ixgbe_phy_sfp_avago: | |
3746 | case ixgbe_phy_sfp_ftl: | |
3747 | case ixgbe_phy_sfp_intel: | |
3748 | case ixgbe_phy_sfp_unknown: | |
ea0a04df DS |
3749 | case ixgbe_phy_sfp_passive_tyco: |
3750 | case ixgbe_phy_sfp_passive_unknown: | |
3751 | case ixgbe_phy_sfp_active_unknown: | |
3752 | case ixgbe_phy_sfp_ftl_active: | |
e8e26350 PW |
3753 | return true; |
3754 | default: | |
3755 | return false; | |
3756 | } | |
3757 | } | |
3758 | ||
0ecc061d | 3759 | /** |
e8e26350 PW |
3760 | * ixgbe_sfp_link_config - set up SFP+ link |
3761 | * @adapter: pointer to private adapter struct | |
3762 | **/ | |
3763 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
3764 | { | |
3765 | struct ixgbe_hw *hw = &adapter->hw; | |
3766 | ||
3767 | if (hw->phy.multispeed_fiber) { | |
3768 | /* | |
3769 | * In multispeed fiber setups, the device may not have | |
3770 | * had a physical connection when the driver loaded. | |
3771 | * If that's the case, the initial link configuration | |
3772 | * couldn't get the MAC into 10G or 1G mode, so we'll | |
3773 | * never have a link status change interrupt fire. | |
3774 | * We need to try and force an autonegotiation | |
3775 | * session, then bring up link. | |
3776 | */ | |
4c7e604b AG |
3777 | if (hw->mac.ops.setup_sfp) |
3778 | hw->mac.ops.setup_sfp(hw); | |
e8e26350 PW |
3779 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) |
3780 | schedule_work(&adapter->multispeed_fiber_task); | |
3781 | } else { | |
3782 | /* | |
3783 | * Direct Attach Cu and non-multispeed fiber modules | |
3784 | * still need to be configured properly prior to | |
3785 | * attempting link. | |
3786 | */ | |
3787 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK)) | |
3788 | schedule_work(&adapter->sfp_config_module_task); | |
3789 | } | |
3790 | } | |
3791 | ||
3792 | /** | |
3793 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
3794 | * @hw: pointer to private hardware struct |
3795 | * | |
3796 | * Returns 0 on success, negative on failure | |
3797 | **/ | |
e8e26350 | 3798 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
3799 | { |
3800 | u32 autoneg; | |
8620a103 | 3801 | bool negotiation, link_up = false; |
0ecc061d PWJ |
3802 | u32 ret = IXGBE_ERR_LINK_SETUP; |
3803 | ||
3804 | if (hw->mac.ops.check_link) | |
3805 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
3806 | ||
3807 | if (ret) | |
3808 | goto link_cfg_out; | |
3809 | ||
0b0c2b31 ET |
3810 | autoneg = hw->phy.autoneg_advertised; |
3811 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
e8e9f696 JP |
3812 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, |
3813 | &negotiation); | |
0ecc061d PWJ |
3814 | if (ret) |
3815 | goto link_cfg_out; | |
3816 | ||
8620a103 MC |
3817 | if (hw->mac.ops.setup_link) |
3818 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
3819 | link_cfg_out: |
3820 | return ret; | |
3821 | } | |
3822 | ||
a34bcfff | 3823 | static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) |
9a799d71 | 3824 | { |
9a799d71 | 3825 | struct ixgbe_hw *hw = &adapter->hw; |
a34bcfff | 3826 | u32 gpie = 0; |
9a799d71 | 3827 | |
9b471446 | 3828 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
a34bcfff AD |
3829 | gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
3830 | IXGBE_GPIE_OCD; | |
3831 | gpie |= IXGBE_GPIE_EIAME; | |
9b471446 JB |
3832 | /* |
3833 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
3834 | * this saves a register write for every interrupt | |
3835 | */ | |
3836 | switch (hw->mac.type) { | |
3837 | case ixgbe_mac_82598EB: | |
3838 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3839 | break; | |
9b471446 | 3840 | case ixgbe_mac_82599EB: |
b93a2226 DS |
3841 | case ixgbe_mac_X540: |
3842 | default: | |
9b471446 JB |
3843 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); |
3844 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
3845 | break; | |
3846 | } | |
3847 | } else { | |
021230d4 AV |
3848 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
3849 | * specifically only auto mask tx and rx interrupts */ | |
3850 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3851 | } | |
9a799d71 | 3852 | |
a34bcfff AD |
3853 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
3854 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
3855 | ||
3856 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
3857 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
3858 | gpie |= IXGBE_GPIE_VTMODE_64; | |
119fc60a MC |
3859 | } |
3860 | ||
a34bcfff AD |
3861 | /* Enable fan failure interrupt */ |
3862 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
0befdb3e | 3863 | gpie |= IXGBE_SDP1_GPIEN; |
0befdb3e | 3864 | |
2698b208 | 3865 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 PW |
3866 | gpie |= IXGBE_SDP1_GPIEN; |
3867 | gpie |= IXGBE_SDP2_GPIEN; | |
2698b208 | 3868 | } |
a34bcfff AD |
3869 | |
3870 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
3871 | } | |
3872 | ||
3873 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) | |
3874 | { | |
3875 | struct ixgbe_hw *hw = &adapter->hw; | |
a34bcfff | 3876 | int err; |
a34bcfff AD |
3877 | u32 ctrl_ext; |
3878 | ||
3879 | ixgbe_get_hw_control(adapter); | |
3880 | ixgbe_setup_gpie(adapter); | |
e8e26350 | 3881 | |
9a799d71 AK |
3882 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3883 | ixgbe_configure_msix(adapter); | |
3884 | else | |
3885 | ixgbe_configure_msi_and_legacy(adapter); | |
3886 | ||
c6ecf39a DS |
3887 | /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */ |
3888 | if (hw->mac.ops.enable_tx_laser && | |
3889 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 3890 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a | 3891 | (hw->mac.type == ixgbe_mac_82599EB)))) |
61fac744 PW |
3892 | hw->mac.ops.enable_tx_laser(hw); |
3893 | ||
9a799d71 | 3894 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
3895 | ixgbe_napi_enable_all(adapter); |
3896 | ||
73c4b7cd AD |
3897 | if (ixgbe_is_sfp(hw)) { |
3898 | ixgbe_sfp_link_config(adapter); | |
3899 | } else { | |
3900 | err = ixgbe_non_sfp_link_config(hw); | |
3901 | if (err) | |
3902 | e_err(probe, "link_config FAILED %d\n", err); | |
3903 | } | |
3904 | ||
021230d4 AV |
3905 | /* clear any pending interrupts, may auto mask */ |
3906 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
6af3b9eb | 3907 | ixgbe_irq_enable(adapter, true, true); |
9a799d71 | 3908 | |
bf069c97 DS |
3909 | /* |
3910 | * If this adapter has a fan, check to see if we had a failure | |
3911 | * before we enabled the interrupt. | |
3912 | */ | |
3913 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
3914 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
3915 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 3916 | e_crit(drv, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
3917 | } |
3918 | ||
e8e26350 PW |
3919 | /* |
3920 | * For hot-pluggable SFP+ devices, a new SFP+ module may have | |
19343de2 DS |
3921 | * arrived before interrupts were enabled but after probe. Such |
3922 | * devices wouldn't have their type identified yet. We need to | |
3923 | * kick off the SFP+ module setup first, then try to bring up link. | |
e8e26350 PW |
3924 | * If we're not hot-pluggable SFP+, we just need to configure link |
3925 | * and bring it up. | |
3926 | */ | |
21cc5b4f | 3927 | if (hw->phy.type == ixgbe_phy_none) |
73c4b7cd | 3928 | schedule_work(&adapter->sfp_config_module_task); |
0ecc061d | 3929 | |
1da100bb | 3930 | /* enable transmits */ |
477de6ed | 3931 | netif_tx_start_all_queues(adapter->netdev); |
1da100bb | 3932 | |
9a799d71 AK |
3933 | /* bring the link up in the watchdog, this could race with our first |
3934 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
3935 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
3936 | adapter->link_check_timeout = jiffies; | |
9a799d71 | 3937 | mod_timer(&adapter->watchdog_timer, jiffies); |
c9205697 GR |
3938 | |
3939 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
3940 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
3941 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
3942 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
3943 | ||
9a799d71 AK |
3944 | return 0; |
3945 | } | |
3946 | ||
d4f80882 AV |
3947 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
3948 | { | |
3949 | WARN_ON(in_interrupt()); | |
3950 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
032b4325 | 3951 | usleep_range(1000, 2000); |
d4f80882 | 3952 | ixgbe_down(adapter); |
5809a1ae GR |
3953 | /* |
3954 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
3955 | * back up to give the VFs time to respond to the reset. The | |
3956 | * two second wait is based upon the watchdog timer cycle in | |
3957 | * the VF driver. | |
3958 | */ | |
3959 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3960 | msleep(2000); | |
d4f80882 AV |
3961 | ixgbe_up(adapter); |
3962 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
3963 | } | |
3964 | ||
9a799d71 AK |
3965 | int ixgbe_up(struct ixgbe_adapter *adapter) |
3966 | { | |
3967 | /* hardware has been reset, we need to reload some things */ | |
3968 | ixgbe_configure(adapter); | |
3969 | ||
3970 | return ixgbe_up_complete(adapter); | |
3971 | } | |
3972 | ||
3973 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
3974 | { | |
c44ade9e | 3975 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
3976 | int err; |
3977 | ||
3978 | err = hw->mac.ops.init_hw(hw); | |
da4dd0f7 PWJ |
3979 | switch (err) { |
3980 | case 0: | |
3981 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
3982 | break; | |
3983 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
849c4542 | 3984 | e_dev_err("master disable timed out\n"); |
da4dd0f7 | 3985 | break; |
794caeb2 PWJ |
3986 | case IXGBE_ERR_EEPROM_VERSION: |
3987 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
3988 | e_dev_warn("This device is a pre-production adapter/LOM. " |
3989 | "Please be aware there may be issuesassociated with " | |
3990 | "your hardware. If you are experiencing problems " | |
3991 | "please contact your Intel or hardware " | |
3992 | "representative who provided you with this " | |
3993 | "hardware.\n"); | |
794caeb2 | 3994 | break; |
da4dd0f7 | 3995 | default: |
849c4542 | 3996 | e_dev_err("Hardware Error: %d\n", err); |
da4dd0f7 | 3997 | } |
9a799d71 AK |
3998 | |
3999 | /* reprogram the RAR[0] in case user changed it. */ | |
1cdd1ec8 GR |
4000 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
4001 | IXGBE_RAH_AV); | |
9a799d71 AK |
4002 | } |
4003 | ||
9a799d71 AK |
4004 | /** |
4005 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
9a799d71 AK |
4006 | * @rx_ring: ring to free buffers from |
4007 | **/ | |
b6ec895e | 4008 | static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) |
9a799d71 | 4009 | { |
b6ec895e | 4010 | struct device *dev = rx_ring->dev; |
9a799d71 | 4011 | unsigned long size; |
b6ec895e | 4012 | u16 i; |
9a799d71 | 4013 | |
84418e3b AD |
4014 | /* ring already cleared, nothing to do */ |
4015 | if (!rx_ring->rx_buffer_info) | |
4016 | return; | |
9a799d71 | 4017 | |
84418e3b | 4018 | /* Free all the Rx ring sk_buffs */ |
9a799d71 AK |
4019 | for (i = 0; i < rx_ring->count; i++) { |
4020 | struct ixgbe_rx_buffer *rx_buffer_info; | |
4021 | ||
4022 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
4023 | if (rx_buffer_info->dma) { | |
b6ec895e | 4024 | dma_unmap_single(rx_ring->dev, rx_buffer_info->dma, |
e8e9f696 | 4025 | rx_ring->rx_buf_len, |
1b507730 | 4026 | DMA_FROM_DEVICE); |
9a799d71 AK |
4027 | rx_buffer_info->dma = 0; |
4028 | } | |
4029 | if (rx_buffer_info->skb) { | |
f8212f97 | 4030 | struct sk_buff *skb = rx_buffer_info->skb; |
9a799d71 | 4031 | rx_buffer_info->skb = NULL; |
f8212f97 AD |
4032 | do { |
4033 | struct sk_buff *this = skb; | |
e8171aaa | 4034 | if (IXGBE_RSC_CB(this)->delay_unmap) { |
b6ec895e | 4035 | dma_unmap_single(dev, |
1b507730 | 4036 | IXGBE_RSC_CB(this)->dma, |
e8e9f696 | 4037 | rx_ring->rx_buf_len, |
1b507730 | 4038 | DMA_FROM_DEVICE); |
fd3686a8 | 4039 | IXGBE_RSC_CB(this)->dma = 0; |
e8171aaa | 4040 | IXGBE_RSC_CB(skb)->delay_unmap = false; |
fd3686a8 | 4041 | } |
f8212f97 AD |
4042 | skb = skb->prev; |
4043 | dev_kfree_skb(this); | |
4044 | } while (skb); | |
9a799d71 AK |
4045 | } |
4046 | if (!rx_buffer_info->page) | |
4047 | continue; | |
4f57ca6e | 4048 | if (rx_buffer_info->page_dma) { |
b6ec895e | 4049 | dma_unmap_page(dev, rx_buffer_info->page_dma, |
1b507730 | 4050 | PAGE_SIZE / 2, DMA_FROM_DEVICE); |
4f57ca6e JB |
4051 | rx_buffer_info->page_dma = 0; |
4052 | } | |
9a799d71 AK |
4053 | put_page(rx_buffer_info->page); |
4054 | rx_buffer_info->page = NULL; | |
762f4c57 | 4055 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
4056 | } |
4057 | ||
4058 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
4059 | memset(rx_ring->rx_buffer_info, 0, size); | |
4060 | ||
4061 | /* Zero out the descriptor ring */ | |
4062 | memset(rx_ring->desc, 0, rx_ring->size); | |
4063 | ||
4064 | rx_ring->next_to_clean = 0; | |
4065 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
4066 | } |
4067 | ||
4068 | /** | |
4069 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
9a799d71 AK |
4070 | * @tx_ring: ring to be cleaned |
4071 | **/ | |
b6ec895e | 4072 | static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) |
9a799d71 AK |
4073 | { |
4074 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4075 | unsigned long size; | |
b6ec895e | 4076 | u16 i; |
9a799d71 | 4077 | |
84418e3b AD |
4078 | /* ring already cleared, nothing to do */ |
4079 | if (!tx_ring->tx_buffer_info) | |
4080 | return; | |
9a799d71 | 4081 | |
84418e3b | 4082 | /* Free all the Tx ring sk_buffs */ |
9a799d71 AK |
4083 | for (i = 0; i < tx_ring->count; i++) { |
4084 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
b6ec895e | 4085 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
9a799d71 AK |
4086 | } |
4087 | ||
4088 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
4089 | memset(tx_ring->tx_buffer_info, 0, size); | |
4090 | ||
4091 | /* Zero out the descriptor ring */ | |
4092 | memset(tx_ring->desc, 0, tx_ring->size); | |
4093 | ||
4094 | tx_ring->next_to_use = 0; | |
4095 | tx_ring->next_to_clean = 0; | |
9a799d71 AK |
4096 | } |
4097 | ||
4098 | /** | |
021230d4 | 4099 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
4100 | * @adapter: board private structure |
4101 | **/ | |
021230d4 | 4102 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4103 | { |
4104 | int i; | |
4105 | ||
021230d4 | 4106 | for (i = 0; i < adapter->num_rx_queues; i++) |
b6ec895e | 4107 | ixgbe_clean_rx_ring(adapter->rx_ring[i]); |
9a799d71 AK |
4108 | } |
4109 | ||
4110 | /** | |
021230d4 | 4111 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
4112 | * @adapter: board private structure |
4113 | **/ | |
021230d4 | 4114 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4115 | { |
4116 | int i; | |
4117 | ||
021230d4 | 4118 | for (i = 0; i < adapter->num_tx_queues; i++) |
b6ec895e | 4119 | ixgbe_clean_tx_ring(adapter->tx_ring[i]); |
9a799d71 AK |
4120 | } |
4121 | ||
4122 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
4123 | { | |
4124 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 4125 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 4126 | u32 rxctrl; |
7f821875 | 4127 | u32 txdctl; |
bf29ee6c | 4128 | int i; |
b25ebfd2 | 4129 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 AK |
4130 | |
4131 | /* signal that we are down to the interrupt handler */ | |
4132 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4133 | ||
767081ad GR |
4134 | /* disable receive for all VFs and wait one second */ |
4135 | if (adapter->num_vfs) { | |
767081ad GR |
4136 | /* ping all the active vfs to let them know we are going down */ |
4137 | ixgbe_ping_all_vfs(adapter); | |
581d1aa7 | 4138 | |
767081ad GR |
4139 | /* Disable all VFTE/VFRE TX/RX */ |
4140 | ixgbe_disable_tx_rx(adapter); | |
581d1aa7 GR |
4141 | |
4142 | /* Mark all the VFs as inactive */ | |
4143 | for (i = 0 ; i < adapter->num_vfs; i++) | |
4144 | adapter->vfinfo[i].clear_to_send = 0; | |
767081ad GR |
4145 | } |
4146 | ||
9a799d71 | 4147 | /* disable receives */ |
7f821875 JB |
4148 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
4149 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 | 4150 | |
2d39d576 YZ |
4151 | /* disable all enabled rx queues */ |
4152 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4153 | /* this call also flushes the previous write */ | |
4154 | ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); | |
4155 | ||
032b4325 | 4156 | usleep_range(10000, 20000); |
9a799d71 | 4157 | |
7f821875 JB |
4158 | netif_tx_stop_all_queues(netdev); |
4159 | ||
0a1f87cb DS |
4160 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
4161 | del_timer_sync(&adapter->sfp_timer); | |
9a799d71 | 4162 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 4163 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 4164 | |
c0dfb90e JF |
4165 | netif_carrier_off(netdev); |
4166 | netif_tx_disable(netdev); | |
4167 | ||
4168 | ixgbe_irq_disable(adapter); | |
4169 | ||
4170 | ixgbe_napi_disable_all(adapter); | |
4171 | ||
b25ebfd2 PW |
4172 | /* Cleanup the affinity_hint CPU mask memory and callback */ |
4173 | for (i = 0; i < num_q_vectors; i++) { | |
4174 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
4175 | /* clear the affinity_mask in the IRQ descriptor */ | |
4176 | irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL); | |
4177 | /* release the CPU mask memory */ | |
4178 | free_cpumask_var(q_vector->affinity_mask); | |
4179 | } | |
4180 | ||
c4cf55e5 PWJ |
4181 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
4182 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
4183 | cancel_work_sync(&adapter->fdir_reinit_task); | |
4184 | ||
119fc60a MC |
4185 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
4186 | cancel_work_sync(&adapter->check_overtemp_task); | |
4187 | ||
7f821875 JB |
4188 | /* disable transmits in the hardware now that interrupts are off */ |
4189 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
bf29ee6c AD |
4190 | u8 reg_idx = adapter->tx_ring[i]->reg_idx; |
4191 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); | |
4192 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), | |
e8e9f696 | 4193 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); |
7f821875 | 4194 | } |
88512539 | 4195 | /* Disable the Tx DMA engine on 82599 */ |
bd508178 AD |
4196 | switch (hw->mac.type) { |
4197 | case ixgbe_mac_82599EB: | |
b93a2226 | 4198 | case ixgbe_mac_X540: |
88512539 | 4199 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, |
e8e9f696 JP |
4200 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & |
4201 | ~IXGBE_DMATXCTL_TE)); | |
bd508178 AD |
4202 | break; |
4203 | default: | |
4204 | break; | |
4205 | } | |
7f821875 | 4206 | |
6f4a0e45 PL |
4207 | if (!pci_channel_offline(adapter->pdev)) |
4208 | ixgbe_reset(adapter); | |
c6ecf39a DS |
4209 | |
4210 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ | |
4211 | if (hw->mac.ops.disable_tx_laser && | |
4212 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 4213 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a DS |
4214 | (hw->mac.type == ixgbe_mac_82599EB)))) |
4215 | hw->mac.ops.disable_tx_laser(hw); | |
4216 | ||
9a799d71 AK |
4217 | ixgbe_clean_all_tx_rings(adapter); |
4218 | ixgbe_clean_all_rx_rings(adapter); | |
4219 | ||
5dd2d332 | 4220 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 4221 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 4222 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 4223 | #endif |
9a799d71 AK |
4224 | } |
4225 | ||
9a799d71 | 4226 | /** |
021230d4 AV |
4227 | * ixgbe_poll - NAPI Rx polling callback |
4228 | * @napi: structure for representing this polling device | |
4229 | * @budget: how many packets driver is allowed to clean | |
4230 | * | |
4231 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 4232 | **/ |
021230d4 | 4233 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 4234 | { |
9a1a69ad | 4235 | struct ixgbe_q_vector *q_vector = |
e8e9f696 | 4236 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 4237 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a1a69ad | 4238 | int tx_clean_complete, work_done = 0; |
9a799d71 | 4239 | |
5dd2d332 | 4240 | #ifdef CONFIG_IXGBE_DCA |
33cf09c9 AD |
4241 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
4242 | ixgbe_update_dca(q_vector); | |
bd0362dd JC |
4243 | #endif |
4244 | ||
4a0b9ca0 PW |
4245 | tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]); |
4246 | ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget); | |
9a799d71 | 4247 | |
9a1a69ad | 4248 | if (!tx_clean_complete) |
d2c7ddd6 DM |
4249 | work_done = budget; |
4250 | ||
53e52c72 DM |
4251 | /* If budget not fully consumed, exit the polling mode */ |
4252 | if (work_done < budget) { | |
288379f0 | 4253 | napi_complete(napi); |
f7554a2b | 4254 | if (adapter->rx_itr_setting & 1) |
f494e8fa | 4255 | ixgbe_set_itr(adapter); |
d4f80882 | 4256 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 4257 | ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 4258 | } |
9a799d71 AK |
4259 | return work_done; |
4260 | } | |
4261 | ||
4262 | /** | |
4263 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
4264 | * @netdev: network interface device structure | |
4265 | **/ | |
4266 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
4267 | { | |
4268 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4269 | ||
c84d324c JF |
4270 | adapter->tx_timeout_count++; |
4271 | ||
9a799d71 AK |
4272 | /* Do the reset outside of interrupt context */ |
4273 | schedule_work(&adapter->reset_task); | |
4274 | } | |
4275 | ||
4276 | static void ixgbe_reset_task(struct work_struct *work) | |
4277 | { | |
4278 | struct ixgbe_adapter *adapter; | |
4279 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
4280 | ||
2f90b865 AD |
4281 | /* If we're already down or resetting, just bail */ |
4282 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
4283 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
4284 | return; | |
4285 | ||
dcd79aeb TI |
4286 | ixgbe_dump(adapter); |
4287 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
d4f80882 | 4288 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
4289 | } |
4290 | ||
4df10466 JB |
4291 | /** |
4292 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
4293 | * @adapter: board private structure to initialize | |
4294 | * | |
4295 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
4296 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
4297 | * | |
4298 | **/ | |
bc97114d PWJ |
4299 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
4300 | { | |
4301 | bool ret = false; | |
0cefafad | 4302 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS]; |
bc97114d PWJ |
4303 | |
4304 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
0cefafad JB |
4305 | f->mask = 0xF; |
4306 | adapter->num_rx_queues = f->indices; | |
4307 | adapter->num_tx_queues = f->indices; | |
bc97114d PWJ |
4308 | ret = true; |
4309 | } else { | |
bc97114d | 4310 | ret = false; |
b9804972 JB |
4311 | } |
4312 | ||
bc97114d PWJ |
4313 | return ret; |
4314 | } | |
4315 | ||
c4cf55e5 PWJ |
4316 | /** |
4317 | * ixgbe_set_fdir_queues: Allocate queues for Flow Director | |
4318 | * @adapter: board private structure to initialize | |
4319 | * | |
4320 | * Flow Director is an advanced Rx filter, attempting to get Rx flows back | |
4321 | * to the original CPU that initiated the Tx session. This runs in addition | |
4322 | * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the | |
4323 | * Rx load across CPUs using RSS. | |
4324 | * | |
4325 | **/ | |
e8e9f696 | 4326 | static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter) |
c4cf55e5 PWJ |
4327 | { |
4328 | bool ret = false; | |
4329 | struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR]; | |
4330 | ||
4331 | f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices); | |
4332 | f_fdir->mask = 0; | |
4333 | ||
4334 | /* Flow Director must have RSS enabled */ | |
4335 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
4336 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
4337 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) { | |
4338 | adapter->num_tx_queues = f_fdir->indices; | |
4339 | adapter->num_rx_queues = f_fdir->indices; | |
4340 | ret = true; | |
4341 | } else { | |
4342 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
4343 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
4344 | } | |
4345 | return ret; | |
4346 | } | |
4347 | ||
0331a832 YZ |
4348 | #ifdef IXGBE_FCOE |
4349 | /** | |
4350 | * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE) | |
4351 | * @adapter: board private structure to initialize | |
4352 | * | |
4353 | * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges. | |
4354 | * The ring feature mask is not used as a mask for FCoE, as it can take any 8 | |
4355 | * rx queues out of the max number of rx queues, instead, it is used as the | |
4356 | * index of the first rx queue used by FCoE. | |
4357 | * | |
4358 | **/ | |
4359 | static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter) | |
4360 | { | |
0331a832 YZ |
4361 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; |
4362 | ||
e5b64635 JF |
4363 | if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) |
4364 | return false; | |
4365 | ||
4366 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
0331a832 | 4367 | #ifdef CONFIG_IXGBE_DCB |
e5b64635 JF |
4368 | int tc; |
4369 | struct net_device *dev = adapter->netdev; | |
4370 | ||
4371 | tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up); | |
4372 | f->indices = dev->tc_to_txq[tc].count; | |
4373 | f->mask = dev->tc_to_txq[tc].offset; | |
0331a832 | 4374 | #endif |
e5b64635 JF |
4375 | } else { |
4376 | f->indices = min((int)num_online_cpus(), f->indices); | |
4377 | ||
4378 | adapter->num_rx_queues = 1; | |
4379 | adapter->num_tx_queues = 1; | |
4380 | ||
0331a832 | 4381 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
396e799c | 4382 | e_info(probe, "FCoE enabled with RSS\n"); |
8faa2a78 YZ |
4383 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || |
4384 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) | |
4385 | ixgbe_set_fdir_queues(adapter); | |
4386 | else | |
4387 | ixgbe_set_rss_queues(adapter); | |
0331a832 YZ |
4388 | } |
4389 | /* adding FCoE rx rings to the end */ | |
4390 | f->mask = adapter->num_rx_queues; | |
4391 | adapter->num_rx_queues += f->indices; | |
8de8b2e6 | 4392 | adapter->num_tx_queues += f->indices; |
e5b64635 | 4393 | } |
0331a832 | 4394 | |
e5b64635 JF |
4395 | return true; |
4396 | } | |
4397 | #endif /* IXGBE_FCOE */ | |
4398 | ||
4399 | #ifdef CONFIG_IXGBE_DCB | |
4400 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
4401 | { | |
4402 | bool ret = false; | |
4403 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB]; | |
4404 | int i, q; | |
4405 | ||
4406 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) | |
4407 | return ret; | |
4408 | ||
4409 | f->indices = 0; | |
4410 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
4411 | q = min((int)num_online_cpus(), MAX_TRAFFIC_CLASS); | |
4412 | f->indices += q; | |
0331a832 YZ |
4413 | } |
4414 | ||
e5b64635 JF |
4415 | f->mask = 0x7 << 3; |
4416 | adapter->num_rx_queues = f->indices; | |
4417 | adapter->num_tx_queues = f->indices; | |
4418 | ret = true; | |
4419 | ||
4420 | #ifdef IXGBE_FCOE | |
4421 | /* FCoE enabled queues require special configuration done through | |
4422 | * configure_fcoe() and others. Here we map FCoE indices onto the | |
4423 | * DCB queue pairs allowing FCoE to own configuration later. | |
4424 | */ | |
4425 | ixgbe_set_fcoe_queues(adapter); | |
4426 | #endif | |
4427 | ||
0331a832 YZ |
4428 | return ret; |
4429 | } | |
e5b64635 | 4430 | #endif |
0331a832 | 4431 | |
1cdd1ec8 GR |
4432 | /** |
4433 | * ixgbe_set_sriov_queues: Allocate queues for IOV use | |
4434 | * @adapter: board private structure to initialize | |
4435 | * | |
4436 | * IOV doesn't actually use anything, so just NAK the | |
4437 | * request for now and let the other queue routines | |
4438 | * figure out what to do. | |
4439 | */ | |
4440 | static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter) | |
4441 | { | |
4442 | return false; | |
4443 | } | |
4444 | ||
4df10466 | 4445 | /* |
25985edc | 4446 | * ixgbe_set_num_queues: Allocate queues for device, feature dependent |
4df10466 JB |
4447 | * @adapter: board private structure to initialize |
4448 | * | |
4449 | * This is the top level queue allocation routine. The order here is very | |
4450 | * important, starting with the "most" number of features turned on at once, | |
4451 | * and ending with the smallest set of features. This way large combinations | |
4452 | * can be allocated if they're turned on, and smaller combinations are the | |
4453 | * fallthrough conditions. | |
4454 | * | |
4455 | **/ | |
847f53ff | 4456 | static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
bc97114d | 4457 | { |
1cdd1ec8 GR |
4458 | /* Start with base case */ |
4459 | adapter->num_rx_queues = 1; | |
4460 | adapter->num_tx_queues = 1; | |
4461 | adapter->num_rx_pools = adapter->num_rx_queues; | |
4462 | adapter->num_rx_queues_per_pool = 1; | |
4463 | ||
4464 | if (ixgbe_set_sriov_queues(adapter)) | |
847f53ff | 4465 | goto done; |
1cdd1ec8 | 4466 | |
bc97114d PWJ |
4467 | #ifdef CONFIG_IXGBE_DCB |
4468 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 4469 | goto done; |
bc97114d PWJ |
4470 | |
4471 | #endif | |
e5b64635 JF |
4472 | #ifdef IXGBE_FCOE |
4473 | if (ixgbe_set_fcoe_queues(adapter)) | |
4474 | goto done; | |
4475 | ||
4476 | #endif /* IXGBE_FCOE */ | |
c4cf55e5 PWJ |
4477 | if (ixgbe_set_fdir_queues(adapter)) |
4478 | goto done; | |
4479 | ||
bc97114d | 4480 | if (ixgbe_set_rss_queues(adapter)) |
af22ab1b WF |
4481 | goto done; |
4482 | ||
4483 | /* fallback to base case */ | |
4484 | adapter->num_rx_queues = 1; | |
4485 | adapter->num_tx_queues = 1; | |
4486 | ||
4487 | done: | |
847f53ff | 4488 | /* Notify the stack of the (possibly) reduced queue counts. */ |
f0796d5c | 4489 | netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); |
847f53ff BH |
4490 | return netif_set_real_num_rx_queues(adapter->netdev, |
4491 | adapter->num_rx_queues); | |
b9804972 JB |
4492 | } |
4493 | ||
021230d4 | 4494 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
e8e9f696 | 4495 | int vectors) |
021230d4 AV |
4496 | { |
4497 | int err, vector_threshold; | |
4498 | ||
4499 | /* We'll want at least 3 (vector_threshold): | |
4500 | * 1) TxQ[0] Cleanup | |
4501 | * 2) RxQ[0] Cleanup | |
4502 | * 3) Other (Link Status Change, etc.) | |
4503 | * 4) TCP Timer (optional) | |
4504 | */ | |
4505 | vector_threshold = MIN_MSIX_COUNT; | |
4506 | ||
4507 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
4508 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
4509 | * Right now, we simply care about how many we'll get; we'll | |
4510 | * set them up later while requesting irq's. | |
4511 | */ | |
4512 | while (vectors >= vector_threshold) { | |
4513 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
e8e9f696 | 4514 | vectors); |
021230d4 AV |
4515 | if (!err) /* Success in acquiring all requested vectors. */ |
4516 | break; | |
4517 | else if (err < 0) | |
4518 | vectors = 0; /* Nasty failure, quit now */ | |
4519 | else /* err == number of vectors we should try again with */ | |
4520 | vectors = err; | |
4521 | } | |
4522 | ||
4523 | if (vectors < vector_threshold) { | |
4524 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
4525 | * This just means we'll go with either a single MSI | |
4526 | * vector or fall back to legacy interrupts. | |
4527 | */ | |
849c4542 ET |
4528 | netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, |
4529 | "Unable to allocate MSI-X interrupts\n"); | |
021230d4 AV |
4530 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
4531 | kfree(adapter->msix_entries); | |
4532 | adapter->msix_entries = NULL; | |
021230d4 AV |
4533 | } else { |
4534 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
4535 | /* |
4536 | * Adjust for only the vectors we'll use, which is minimum | |
4537 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
4538 | * vectors we were allocated. | |
4539 | */ | |
4540 | adapter->num_msix_vectors = min(vectors, | |
e8e9f696 | 4541 | adapter->max_msix_q_vectors + NON_Q_VECTORS); |
021230d4 AV |
4542 | } |
4543 | } | |
4544 | ||
021230d4 | 4545 | /** |
bc97114d | 4546 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
4547 | * @adapter: board private structure to initialize |
4548 | * | |
bc97114d PWJ |
4549 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
4550 | * | |
021230d4 | 4551 | **/ |
bc97114d | 4552 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 4553 | { |
bc97114d | 4554 | int i; |
bc97114d | 4555 | |
9d6b758f AD |
4556 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) |
4557 | return false; | |
bc97114d | 4558 | |
9d6b758f AD |
4559 | for (i = 0; i < adapter->num_rx_queues; i++) |
4560 | adapter->rx_ring[i]->reg_idx = i; | |
4561 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4562 | adapter->tx_ring[i]->reg_idx = i; | |
4563 | ||
4564 | return true; | |
bc97114d PWJ |
4565 | } |
4566 | ||
4567 | #ifdef CONFIG_IXGBE_DCB | |
e5b64635 JF |
4568 | |
4569 | /* ixgbe_get_first_reg_idx - Return first register index associated with ring */ | |
b32c8dcc JF |
4570 | static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc, |
4571 | unsigned int *tx, unsigned int *rx) | |
e5b64635 JF |
4572 | { |
4573 | struct net_device *dev = adapter->netdev; | |
4574 | struct ixgbe_hw *hw = &adapter->hw; | |
4575 | u8 num_tcs = netdev_get_num_tc(dev); | |
4576 | ||
4577 | *tx = 0; | |
4578 | *rx = 0; | |
4579 | ||
4580 | switch (hw->mac.type) { | |
4581 | case ixgbe_mac_82598EB: | |
4582 | *tx = tc << 3; | |
4583 | *rx = tc << 2; | |
4584 | break; | |
4585 | case ixgbe_mac_82599EB: | |
4586 | case ixgbe_mac_X540: | |
4587 | if (num_tcs == 8) { | |
4588 | if (tc < 3) { | |
4589 | *tx = tc << 5; | |
4590 | *rx = tc << 4; | |
4591 | } else if (tc < 5) { | |
4592 | *tx = ((tc + 2) << 4); | |
4593 | *rx = tc << 4; | |
4594 | } else if (tc < num_tcs) { | |
4595 | *tx = ((tc + 8) << 3); | |
4596 | *rx = tc << 4; | |
4597 | } | |
4598 | } else if (num_tcs == 4) { | |
4599 | *rx = tc << 5; | |
4600 | switch (tc) { | |
4601 | case 0: | |
4602 | *tx = 0; | |
4603 | break; | |
4604 | case 1: | |
4605 | *tx = 64; | |
4606 | break; | |
4607 | case 2: | |
4608 | *tx = 96; | |
4609 | break; | |
4610 | case 3: | |
4611 | *tx = 112; | |
4612 | break; | |
4613 | default: | |
4614 | break; | |
4615 | } | |
4616 | } | |
4617 | break; | |
4618 | default: | |
4619 | break; | |
4620 | } | |
4621 | } | |
4622 | ||
4623 | #define IXGBE_MAX_Q_PER_TC (IXGBE_MAX_DCB_INDICES / MAX_TRAFFIC_CLASS) | |
4624 | ||
4625 | /* ixgbe_setup_tc - routine to configure net_device for multiple traffic | |
4626 | * classes. | |
4627 | * | |
4628 | * @netdev: net device to configure | |
4629 | * @tc: number of traffic classes to enable | |
4630 | */ | |
4631 | int ixgbe_setup_tc(struct net_device *dev, u8 tc) | |
4632 | { | |
4633 | int i; | |
4634 | unsigned int q, offset = 0; | |
4635 | ||
4636 | if (!tc) { | |
4637 | netdev_reset_tc(dev); | |
4638 | } else { | |
24095aa3 JF |
4639 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
4640 | ||
4641 | /* Hardware supports up to 8 traffic classes */ | |
4642 | if (tc > MAX_TRAFFIC_CLASS || netdev_set_num_tc(dev, tc)) | |
e5b64635 JF |
4643 | return -EINVAL; |
4644 | ||
4645 | /* Partition Tx queues evenly amongst traffic classes */ | |
4646 | for (i = 0; i < tc; i++) { | |
4647 | q = min((int)num_online_cpus(), IXGBE_MAX_Q_PER_TC); | |
4648 | netdev_set_prio_tc_map(dev, i, i); | |
4649 | netdev_set_tc_queue(dev, i, q, offset); | |
4650 | offset += q; | |
4651 | } | |
24095aa3 JF |
4652 | |
4653 | /* This enables multiple traffic class support in the hardware | |
4654 | * which defaults to strict priority transmission by default. | |
4655 | * If traffic classes are already enabled perhaps through DCB | |
4656 | * code path then existing configuration will be used. | |
4657 | */ | |
4658 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) && | |
4659 | dev->dcbnl_ops && dev->dcbnl_ops->setdcbx) { | |
4660 | struct ieee_ets ets = { | |
4661 | .prio_tc = {0, 1, 2, 3, 4, 5, 6, 7}, | |
4662 | }; | |
4663 | u8 mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE; | |
4664 | ||
4665 | dev->dcbnl_ops->setdcbx(dev, mode); | |
4666 | dev->dcbnl_ops->ieee_setets(dev, &ets); | |
4667 | } | |
e5b64635 JF |
4668 | } |
4669 | return 0; | |
4670 | } | |
4671 | ||
bc97114d PWJ |
4672 | /** |
4673 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
4674 | * @adapter: board private structure to initialize | |
4675 | * | |
4676 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
4677 | * | |
4678 | **/ | |
4679 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
4680 | { | |
e5b64635 JF |
4681 | struct net_device *dev = adapter->netdev; |
4682 | int i, j, k; | |
4683 | u8 num_tcs = netdev_get_num_tc(dev); | |
bc97114d | 4684 | |
bd508178 AD |
4685 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) |
4686 | return false; | |
f92ef202 | 4687 | |
e5b64635 JF |
4688 | for (i = 0, k = 0; i < num_tcs; i++) { |
4689 | unsigned int tx_s, rx_s; | |
4690 | u16 count = dev->tc_to_txq[i].count; | |
4691 | ||
4692 | ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s); | |
4693 | for (j = 0; j < count; j++, k++) { | |
4694 | adapter->tx_ring[k]->reg_idx = tx_s + j; | |
4695 | adapter->rx_ring[k]->reg_idx = rx_s + j; | |
4696 | adapter->tx_ring[k]->dcb_tc = i; | |
4697 | adapter->rx_ring[k]->dcb_tc = i; | |
021230d4 | 4698 | } |
021230d4 | 4699 | } |
e5b64635 JF |
4700 | |
4701 | return true; | |
bc97114d PWJ |
4702 | } |
4703 | #endif | |
4704 | ||
c4cf55e5 PWJ |
4705 | /** |
4706 | * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director | |
4707 | * @adapter: board private structure to initialize | |
4708 | * | |
4709 | * Cache the descriptor ring offsets for Flow Director to the assigned rings. | |
4710 | * | |
4711 | **/ | |
e8e9f696 | 4712 | static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter) |
c4cf55e5 PWJ |
4713 | { |
4714 | int i; | |
4715 | bool ret = false; | |
4716 | ||
4717 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
4718 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
4719 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) { | |
4720 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 4721 | adapter->rx_ring[i]->reg_idx = i; |
c4cf55e5 | 4722 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 4723 | adapter->tx_ring[i]->reg_idx = i; |
c4cf55e5 PWJ |
4724 | ret = true; |
4725 | } | |
4726 | ||
4727 | return ret; | |
4728 | } | |
4729 | ||
0331a832 YZ |
4730 | #ifdef IXGBE_FCOE |
4731 | /** | |
4732 | * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE | |
4733 | * @adapter: board private structure to initialize | |
4734 | * | |
4735 | * Cache the descriptor ring offsets for FCoE mode to the assigned rings. | |
4736 | * | |
4737 | */ | |
4738 | static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter) | |
4739 | { | |
0331a832 | 4740 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; |
bf29ee6c AD |
4741 | int i; |
4742 | u8 fcoe_rx_i = 0, fcoe_tx_i = 0; | |
4743 | ||
4744 | if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) | |
4745 | return false; | |
0331a832 | 4746 | |
bf29ee6c AD |
4747 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
4748 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
4749 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) | |
4750 | ixgbe_cache_ring_fdir(adapter); | |
4751 | else | |
4752 | ixgbe_cache_ring_rss(adapter); | |
8faa2a78 | 4753 | |
bf29ee6c AD |
4754 | fcoe_rx_i = f->mask; |
4755 | fcoe_tx_i = f->mask; | |
0331a832 | 4756 | } |
bf29ee6c AD |
4757 | for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) { |
4758 | adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i; | |
4759 | adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i; | |
4760 | } | |
4761 | return true; | |
0331a832 YZ |
4762 | } |
4763 | ||
4764 | #endif /* IXGBE_FCOE */ | |
1cdd1ec8 GR |
4765 | /** |
4766 | * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov | |
4767 | * @adapter: board private structure to initialize | |
4768 | * | |
4769 | * SR-IOV doesn't use any descriptor rings but changes the default if | |
4770 | * no other mapping is used. | |
4771 | * | |
4772 | */ | |
4773 | static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter) | |
4774 | { | |
4a0b9ca0 PW |
4775 | adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2; |
4776 | adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2; | |
1cdd1ec8 GR |
4777 | if (adapter->num_vfs) |
4778 | return true; | |
4779 | else | |
4780 | return false; | |
4781 | } | |
4782 | ||
bc97114d PWJ |
4783 | /** |
4784 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
4785 | * @adapter: board private structure to initialize | |
4786 | * | |
4787 | * Once we know the feature-set enabled for the device, we'll cache | |
4788 | * the register offset the descriptor ring is assigned to. | |
4789 | * | |
4790 | * Note, the order the various feature calls is important. It must start with | |
4791 | * the "most" features enabled at the same time, then trickle down to the | |
4792 | * least amount of features turned on at once. | |
4793 | **/ | |
4794 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
4795 | { | |
4796 | /* start with default case */ | |
4a0b9ca0 PW |
4797 | adapter->rx_ring[0]->reg_idx = 0; |
4798 | adapter->tx_ring[0]->reg_idx = 0; | |
bc97114d | 4799 | |
1cdd1ec8 GR |
4800 | if (ixgbe_cache_ring_sriov(adapter)) |
4801 | return; | |
4802 | ||
e5b64635 JF |
4803 | #ifdef CONFIG_IXGBE_DCB |
4804 | if (ixgbe_cache_ring_dcb(adapter)) | |
4805 | return; | |
4806 | #endif | |
4807 | ||
0331a832 YZ |
4808 | #ifdef IXGBE_FCOE |
4809 | if (ixgbe_cache_ring_fcoe(adapter)) | |
4810 | return; | |
0331a832 | 4811 | #endif /* IXGBE_FCOE */ |
bc97114d | 4812 | |
c4cf55e5 PWJ |
4813 | if (ixgbe_cache_ring_fdir(adapter)) |
4814 | return; | |
4815 | ||
bc97114d PWJ |
4816 | if (ixgbe_cache_ring_rss(adapter)) |
4817 | return; | |
021230d4 AV |
4818 | } |
4819 | ||
9a799d71 AK |
4820 | /** |
4821 | * ixgbe_alloc_queues - Allocate memory for all rings | |
4822 | * @adapter: board private structure to initialize | |
4823 | * | |
4824 | * We allocate one ring per queue at run-time since we don't know the | |
4df10466 JB |
4825 | * number of queues at compile-time. The polling_netdev array is |
4826 | * intended for Multiqueue, but should work fine with a single queue. | |
9a799d71 | 4827 | **/ |
2f90b865 | 4828 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 | 4829 | { |
e2ddeba9 | 4830 | int rx = 0, tx = 0, nid = adapter->node; |
9a799d71 | 4831 | |
e2ddeba9 ED |
4832 | if (nid < 0 || !node_online(nid)) |
4833 | nid = first_online_node; | |
4834 | ||
4835 | for (; tx < adapter->num_tx_queues; tx++) { | |
4836 | struct ixgbe_ring *ring; | |
4837 | ||
4838 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid); | |
4a0b9ca0 | 4839 | if (!ring) |
e2ddeba9 | 4840 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
4a0b9ca0 | 4841 | if (!ring) |
e2ddeba9 | 4842 | goto err_allocation; |
4a0b9ca0 | 4843 | ring->count = adapter->tx_ring_count; |
e2ddeba9 ED |
4844 | ring->queue_index = tx; |
4845 | ring->numa_node = nid; | |
b6ec895e | 4846 | ring->dev = &adapter->pdev->dev; |
fc77dc3c | 4847 | ring->netdev = adapter->netdev; |
4a0b9ca0 | 4848 | |
e2ddeba9 | 4849 | adapter->tx_ring[tx] = ring; |
021230d4 | 4850 | } |
b9804972 | 4851 | |
e2ddeba9 ED |
4852 | for (; rx < adapter->num_rx_queues; rx++) { |
4853 | struct ixgbe_ring *ring; | |
4a0b9ca0 | 4854 | |
e2ddeba9 | 4855 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid); |
4a0b9ca0 | 4856 | if (!ring) |
e2ddeba9 | 4857 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
4a0b9ca0 | 4858 | if (!ring) |
e2ddeba9 ED |
4859 | goto err_allocation; |
4860 | ring->count = adapter->rx_ring_count; | |
4861 | ring->queue_index = rx; | |
4862 | ring->numa_node = nid; | |
b6ec895e | 4863 | ring->dev = &adapter->pdev->dev; |
fc77dc3c | 4864 | ring->netdev = adapter->netdev; |
4a0b9ca0 | 4865 | |
e2ddeba9 | 4866 | adapter->rx_ring[rx] = ring; |
021230d4 AV |
4867 | } |
4868 | ||
4869 | ixgbe_cache_ring_register(adapter); | |
4870 | ||
4871 | return 0; | |
4872 | ||
e2ddeba9 ED |
4873 | err_allocation: |
4874 | while (tx) | |
4875 | kfree(adapter->tx_ring[--tx]); | |
4876 | ||
4877 | while (rx) | |
4878 | kfree(adapter->rx_ring[--rx]); | |
021230d4 AV |
4879 | return -ENOMEM; |
4880 | } | |
4881 | ||
4882 | /** | |
4883 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
4884 | * @adapter: board private structure to initialize | |
4885 | * | |
4886 | * Attempt to configure the interrupts using the best available | |
4887 | * capabilities of the hardware and the kernel. | |
4888 | **/ | |
feea6a57 | 4889 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 4890 | { |
8be0e467 | 4891 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
4892 | int err = 0; |
4893 | int vector, v_budget; | |
4894 | ||
4895 | /* | |
4896 | * It's easy to be greedy for MSI-X vectors, but it really | |
4897 | * doesn't do us much good if we have a lot more vectors | |
4898 | * than CPU's. So let's be conservative and only ask for | |
342bde1b | 4899 | * (roughly) the same number of vectors as there are CPU's. |
021230d4 AV |
4900 | */ |
4901 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
e8e9f696 | 4902 | (int)num_online_cpus()) + NON_Q_VECTORS; |
021230d4 AV |
4903 | |
4904 | /* | |
4905 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
4906 | * hw.mac->max_msix_vectors vectors. With features |
4907 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
4908 | * descriptor queues supported by our device. Thus, we cap it off in | |
4909 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 4910 | */ |
8be0e467 | 4911 | v_budget = min(v_budget, (int)hw->mac.max_msix_vectors); |
021230d4 AV |
4912 | |
4913 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
4914 | * mean we disable MSI-X capabilities of the adapter. */ | |
4915 | adapter->msix_entries = kcalloc(v_budget, | |
e8e9f696 | 4916 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
4917 | if (adapter->msix_entries) { |
4918 | for (vector = 0; vector < v_budget; vector++) | |
4919 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 4920 | |
7a921c93 | 4921 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 4922 | |
7a921c93 AD |
4923 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
4924 | goto out; | |
4925 | } | |
26d27844 | 4926 | |
7a921c93 AD |
4927 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
4928 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
45b9f509 AD |
4929 | if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE | |
4930 | IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) { | |
4931 | e_err(probe, | |
4932 | "Flow Director is not supported while multiple " | |
4933 | "queues are disabled. Disabling Flow Director\n"); | |
4934 | } | |
c4cf55e5 PWJ |
4935 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
4936 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
4937 | adapter->atr_sample_rate = 0; | |
1cdd1ec8 GR |
4938 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
4939 | ixgbe_disable_sriov(adapter); | |
4940 | ||
847f53ff BH |
4941 | err = ixgbe_set_num_queues(adapter); |
4942 | if (err) | |
4943 | return err; | |
021230d4 | 4944 | |
021230d4 AV |
4945 | err = pci_enable_msi(adapter->pdev); |
4946 | if (!err) { | |
4947 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
4948 | } else { | |
849c4542 ET |
4949 | netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, |
4950 | "Unable to allocate MSI interrupt, " | |
4951 | "falling back to legacy. Error: %d\n", err); | |
021230d4 AV |
4952 | /* reset err */ |
4953 | err = 0; | |
4954 | } | |
4955 | ||
4956 | out: | |
021230d4 AV |
4957 | return err; |
4958 | } | |
4959 | ||
7a921c93 AD |
4960 | /** |
4961 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
4962 | * @adapter: board private structure to initialize | |
4963 | * | |
4964 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
4965 | * return -ENOMEM. | |
4966 | **/ | |
4967 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
4968 | { | |
4969 | int q_idx, num_q_vectors; | |
4970 | struct ixgbe_q_vector *q_vector; | |
7a921c93 AD |
4971 | int (*poll)(struct napi_struct *, int); |
4972 | ||
4973 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
4974 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
91281fd3 | 4975 | poll = &ixgbe_clean_rxtx_many; |
7a921c93 AD |
4976 | } else { |
4977 | num_q_vectors = 1; | |
7a921c93 AD |
4978 | poll = &ixgbe_poll; |
4979 | } | |
4980 | ||
4981 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
1a6c14a2 | 4982 | q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector), |
e8e9f696 | 4983 | GFP_KERNEL, adapter->node); |
1a6c14a2 JB |
4984 | if (!q_vector) |
4985 | q_vector = kzalloc(sizeof(struct ixgbe_q_vector), | |
e8e9f696 | 4986 | GFP_KERNEL); |
7a921c93 AD |
4987 | if (!q_vector) |
4988 | goto err_out; | |
4989 | q_vector->adapter = adapter; | |
f7554a2b NS |
4990 | if (q_vector->txr_count && !q_vector->rxr_count) |
4991 | q_vector->eitr = adapter->tx_eitr_param; | |
4992 | else | |
4993 | q_vector->eitr = adapter->rx_eitr_param; | |
fe49f04a | 4994 | q_vector->v_idx = q_idx; |
91281fd3 | 4995 | netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64); |
7a921c93 AD |
4996 | adapter->q_vector[q_idx] = q_vector; |
4997 | } | |
4998 | ||
4999 | return 0; | |
5000 | ||
5001 | err_out: | |
5002 | while (q_idx) { | |
5003 | q_idx--; | |
5004 | q_vector = adapter->q_vector[q_idx]; | |
5005 | netif_napi_del(&q_vector->napi); | |
5006 | kfree(q_vector); | |
5007 | adapter->q_vector[q_idx] = NULL; | |
5008 | } | |
5009 | return -ENOMEM; | |
5010 | } | |
5011 | ||
5012 | /** | |
5013 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
5014 | * @adapter: board private structure to initialize | |
5015 | * | |
5016 | * This function frees the memory allocated to the q_vectors. In addition if | |
5017 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
5018 | * to freeing the q_vector. | |
5019 | **/ | |
5020 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
5021 | { | |
5022 | int q_idx, num_q_vectors; | |
7a921c93 | 5023 | |
91281fd3 | 5024 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
7a921c93 | 5025 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
91281fd3 | 5026 | else |
7a921c93 | 5027 | num_q_vectors = 1; |
7a921c93 AD |
5028 | |
5029 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
5030 | struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx]; | |
7a921c93 | 5031 | adapter->q_vector[q_idx] = NULL; |
91281fd3 | 5032 | netif_napi_del(&q_vector->napi); |
7a921c93 AD |
5033 | kfree(q_vector); |
5034 | } | |
5035 | } | |
5036 | ||
7b25cdba | 5037 | static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
5038 | { |
5039 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
5040 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
5041 | pci_disable_msix(adapter->pdev); | |
5042 | kfree(adapter->msix_entries); | |
5043 | adapter->msix_entries = NULL; | |
5044 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
5045 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
5046 | pci_disable_msi(adapter->pdev); | |
5047 | } | |
021230d4 AV |
5048 | } |
5049 | ||
5050 | /** | |
5051 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
5052 | * @adapter: board private structure to initialize | |
5053 | * | |
5054 | * We determine which interrupt scheme to use based on... | |
5055 | * - Kernel support (MSI, MSI-X) | |
5056 | * - which can be user-defined (via MODULE_PARAM) | |
5057 | * - Hardware queue count (num_*_queues) | |
5058 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
5059 | **/ | |
2f90b865 | 5060 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
5061 | { |
5062 | int err; | |
5063 | ||
5064 | /* Number of supported queues */ | |
847f53ff BH |
5065 | err = ixgbe_set_num_queues(adapter); |
5066 | if (err) | |
5067 | return err; | |
021230d4 | 5068 | |
021230d4 AV |
5069 | err = ixgbe_set_interrupt_capability(adapter); |
5070 | if (err) { | |
849c4542 | 5071 | e_dev_err("Unable to setup interrupt capabilities\n"); |
021230d4 | 5072 | goto err_set_interrupt; |
9a799d71 AK |
5073 | } |
5074 | ||
7a921c93 AD |
5075 | err = ixgbe_alloc_q_vectors(adapter); |
5076 | if (err) { | |
849c4542 | 5077 | e_dev_err("Unable to allocate memory for queue vectors\n"); |
7a921c93 AD |
5078 | goto err_alloc_q_vectors; |
5079 | } | |
5080 | ||
5081 | err = ixgbe_alloc_queues(adapter); | |
5082 | if (err) { | |
849c4542 | 5083 | e_dev_err("Unable to allocate memory for queues\n"); |
7a921c93 AD |
5084 | goto err_alloc_queues; |
5085 | } | |
5086 | ||
849c4542 | 5087 | e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n", |
396e799c ET |
5088 | (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled", |
5089 | adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
5090 | |
5091 | set_bit(__IXGBE_DOWN, &adapter->state); | |
5092 | ||
9a799d71 | 5093 | return 0; |
021230d4 | 5094 | |
7a921c93 AD |
5095 | err_alloc_queues: |
5096 | ixgbe_free_q_vectors(adapter); | |
5097 | err_alloc_q_vectors: | |
5098 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 5099 | err_set_interrupt: |
7a921c93 AD |
5100 | return err; |
5101 | } | |
5102 | ||
1a51502b ED |
5103 | static void ring_free_rcu(struct rcu_head *head) |
5104 | { | |
5105 | kfree(container_of(head, struct ixgbe_ring, rcu)); | |
5106 | } | |
5107 | ||
7a921c93 AD |
5108 | /** |
5109 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
5110 | * @adapter: board private structure to clear interrupt scheme on | |
5111 | * | |
5112 | * We go through and clear interrupt specific resources and reset the structure | |
5113 | * to pre-load conditions | |
5114 | **/ | |
5115 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
5116 | { | |
4a0b9ca0 PW |
5117 | int i; |
5118 | ||
5119 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
5120 | kfree(adapter->tx_ring[i]); | |
5121 | adapter->tx_ring[i] = NULL; | |
5122 | } | |
5123 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1a51502b ED |
5124 | struct ixgbe_ring *ring = adapter->rx_ring[i]; |
5125 | ||
5126 | /* ixgbe_get_stats64() might access this ring, we must wait | |
5127 | * a grace period before freeing it. | |
5128 | */ | |
5129 | call_rcu(&ring->rcu, ring_free_rcu); | |
4a0b9ca0 PW |
5130 | adapter->rx_ring[i] = NULL; |
5131 | } | |
7a921c93 | 5132 | |
b8eb3a10 DS |
5133 | adapter->num_tx_queues = 0; |
5134 | adapter->num_rx_queues = 0; | |
5135 | ||
7a921c93 AD |
5136 | ixgbe_free_q_vectors(adapter); |
5137 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
5138 | } |
5139 | ||
c4900be0 DS |
5140 | /** |
5141 | * ixgbe_sfp_timer - worker thread to find a missing module | |
5142 | * @data: pointer to our adapter struct | |
5143 | **/ | |
5144 | static void ixgbe_sfp_timer(unsigned long data) | |
5145 | { | |
5146 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
5147 | ||
4df10466 JB |
5148 | /* |
5149 | * Do the sfp_timer outside of interrupt context due to the | |
c4900be0 DS |
5150 | * delays that sfp+ detection requires |
5151 | */ | |
5152 | schedule_work(&adapter->sfp_task); | |
5153 | } | |
5154 | ||
5155 | /** | |
5156 | * ixgbe_sfp_task - worker thread to find a missing module | |
5157 | * @work: pointer to work_struct containing our data | |
5158 | **/ | |
5159 | static void ixgbe_sfp_task(struct work_struct *work) | |
5160 | { | |
5161 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
5162 | struct ixgbe_adapter, |
5163 | sfp_task); | |
c4900be0 DS |
5164 | struct ixgbe_hw *hw = &adapter->hw; |
5165 | ||
5166 | if ((hw->phy.type == ixgbe_phy_nl) && | |
5167 | (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { | |
5168 | s32 ret = hw->phy.ops.identify_sfp(hw); | |
63d6e1d8 | 5169 | if (ret == IXGBE_ERR_SFP_NOT_PRESENT) |
c4900be0 DS |
5170 | goto reschedule; |
5171 | ret = hw->phy.ops.reset(hw); | |
5172 | if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
849c4542 ET |
5173 | e_dev_err("failed to initialize because an unsupported " |
5174 | "SFP+ module type was detected.\n"); | |
5175 | e_dev_err("Reload the driver after installing a " | |
5176 | "supported module.\n"); | |
c4900be0 DS |
5177 | unregister_netdev(adapter->netdev); |
5178 | } else { | |
396e799c | 5179 | e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); |
c4900be0 DS |
5180 | } |
5181 | /* don't need this routine any more */ | |
5182 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
5183 | } | |
5184 | return; | |
5185 | reschedule: | |
5186 | if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) | |
5187 | mod_timer(&adapter->sfp_timer, | |
e8e9f696 | 5188 | round_jiffies(jiffies + (2 * HZ))); |
c4900be0 DS |
5189 | } |
5190 | ||
9a799d71 AK |
5191 | /** |
5192 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
5193 | * @adapter: board private structure to initialize | |
5194 | * | |
5195 | * ixgbe_sw_init initializes the Adapter private data structure. | |
5196 | * Fields are initialized based on PCI device information and | |
5197 | * OS network device settings (MTU size). | |
5198 | **/ | |
5199 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
5200 | { | |
5201 | struct ixgbe_hw *hw = &adapter->hw; | |
5202 | struct pci_dev *pdev = adapter->pdev; | |
9a713e7c | 5203 | struct net_device *dev = adapter->netdev; |
021230d4 | 5204 | unsigned int rss; |
7a6b6f51 | 5205 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
5206 | int j; |
5207 | struct tc_configuration *tc; | |
5208 | #endif | |
16b61beb | 5209 | int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 | 5210 | |
c44ade9e JB |
5211 | /* PCI config space info */ |
5212 | ||
5213 | hw->vendor_id = pdev->vendor; | |
5214 | hw->device_id = pdev->device; | |
5215 | hw->revision_id = pdev->revision; | |
5216 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
5217 | hw->subsystem_device_id = pdev->subsystem_device; | |
5218 | ||
021230d4 AV |
5219 | /* Set capability flags */ |
5220 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
5221 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
5222 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 5223 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
bd508178 AD |
5224 | switch (hw->mac.type) { |
5225 | case ixgbe_mac_82598EB: | |
bf069c97 DS |
5226 | if (hw->device_id == IXGBE_DEV_ID_82598AT) |
5227 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 5228 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bd508178 AD |
5229 | break; |
5230 | case ixgbe_mac_82599EB: | |
b93a2226 | 5231 | case ixgbe_mac_X540: |
e8e26350 | 5232 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
0c19d6af PWJ |
5233 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
5234 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
119fc60a MC |
5235 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) |
5236 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
45b9f509 AD |
5237 | /* n-tuple support exists, always init our spinlock */ |
5238 | spin_lock_init(&adapter->fdir_perfect_lock); | |
5239 | /* Flow Director hash filters enabled */ | |
5240 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
5241 | adapter->atr_sample_rate = 20; | |
c4cf55e5 | 5242 | adapter->ring_feature[RING_F_FDIR].indices = |
e8e9f696 | 5243 | IXGBE_MAX_FDIR_INDICES; |
c4cf55e5 | 5244 | adapter->fdir_pballoc = 0; |
eacd73f7 | 5245 | #ifdef IXGBE_FCOE |
0d551589 YZ |
5246 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
5247 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
5248 | adapter->ring_feature[RING_F_FCOE].indices = 0; | |
61a0f421 | 5249 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 YZ |
5250 | /* Default traffic class to use for FCoE */ |
5251 | adapter->fcoe.tc = IXGBE_FCOE_DEFTC; | |
56075a98 | 5252 | adapter->fcoe.up = IXGBE_FCOE_DEFTC; |
61a0f421 | 5253 | #endif |
eacd73f7 | 5254 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5255 | break; |
5256 | default: | |
5257 | break; | |
f8212f97 | 5258 | } |
2f90b865 | 5259 | |
7a6b6f51 | 5260 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
5261 | /* Configure DCB traffic classes */ |
5262 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
5263 | tc = &adapter->dcb_cfg.tc_config[j]; | |
5264 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
5265 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
5266 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
5267 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
5268 | tc->dcb_pfc = pfc_disabled; | |
5269 | } | |
5270 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
5271 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
5272 | adapter->dcb_cfg.rx_pba_cfg = pba_equal; | |
264857b8 | 5273 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 | 5274 | adapter->dcb_set_bitmap = 0x00; |
3032309b | 5275 | adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; |
2f90b865 | 5276 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, |
e5b64635 | 5277 | MAX_TRAFFIC_CLASS); |
2f90b865 AD |
5278 | |
5279 | #endif | |
9a799d71 AK |
5280 | |
5281 | /* default flow control settings */ | |
cd7664f6 | 5282 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 5283 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
264857b8 PWJ |
5284 | #ifdef CONFIG_DCB |
5285 | adapter->last_lfc_mode = hw->fc.current_mode; | |
5286 | #endif | |
16b61beb JF |
5287 | hw->fc.high_water = FC_HIGH_WATER(max_frame); |
5288 | hw->fc.low_water = FC_LOW_WATER(max_frame); | |
2b9ade93 JB |
5289 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; |
5290 | hw->fc.send_xon = true; | |
71fd570b | 5291 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 5292 | |
30efa5a3 | 5293 | /* enable itr by default in dynamic mode */ |
f7554a2b NS |
5294 | adapter->rx_itr_setting = 1; |
5295 | adapter->rx_eitr_param = 20000; | |
5296 | adapter->tx_itr_setting = 1; | |
5297 | adapter->tx_eitr_param = 10000; | |
30efa5a3 JB |
5298 | |
5299 | /* set defaults for eitr in MegaBytes */ | |
5300 | adapter->eitr_low = 10; | |
5301 | adapter->eitr_high = 20; | |
5302 | ||
5303 | /* set default ring sizes */ | |
5304 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
5305 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
5306 | ||
9a799d71 | 5307 | /* initialize eeprom parameters */ |
c44ade9e | 5308 | if (ixgbe_init_eeprom_params_generic(hw)) { |
849c4542 | 5309 | e_dev_err("EEPROM initialization failed\n"); |
9a799d71 AK |
5310 | return -EIO; |
5311 | } | |
5312 | ||
021230d4 | 5313 | /* enable rx csum by default */ |
9a799d71 AK |
5314 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
5315 | ||
1a6c14a2 JB |
5316 | /* get assigned NUMA node */ |
5317 | adapter->node = dev_to_node(&pdev->dev); | |
5318 | ||
9a799d71 AK |
5319 | set_bit(__IXGBE_DOWN, &adapter->state); |
5320 | ||
5321 | return 0; | |
5322 | } | |
5323 | ||
5324 | /** | |
5325 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3a581073 | 5326 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
5327 | * |
5328 | * Return 0 on success, negative on failure | |
5329 | **/ | |
b6ec895e | 5330 | int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 5331 | { |
b6ec895e | 5332 | struct device *dev = tx_ring->dev; |
9a799d71 AK |
5333 | int size; |
5334 | ||
3a581073 | 5335 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
89bf67f1 | 5336 | tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node); |
1a6c14a2 | 5337 | if (!tx_ring->tx_buffer_info) |
89bf67f1 | 5338 | tx_ring->tx_buffer_info = vzalloc(size); |
e01c31a5 JB |
5339 | if (!tx_ring->tx_buffer_info) |
5340 | goto err; | |
9a799d71 AK |
5341 | |
5342 | /* round up to nearest 4K */ | |
12207e49 | 5343 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 5344 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 5345 | |
b6ec895e | 5346 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, |
1b507730 | 5347 | &tx_ring->dma, GFP_KERNEL); |
e01c31a5 JB |
5348 | if (!tx_ring->desc) |
5349 | goto err; | |
9a799d71 | 5350 | |
3a581073 JB |
5351 | tx_ring->next_to_use = 0; |
5352 | tx_ring->next_to_clean = 0; | |
5353 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 5354 | return 0; |
e01c31a5 JB |
5355 | |
5356 | err: | |
5357 | vfree(tx_ring->tx_buffer_info); | |
5358 | tx_ring->tx_buffer_info = NULL; | |
b6ec895e | 5359 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); |
e01c31a5 | 5360 | return -ENOMEM; |
9a799d71 AK |
5361 | } |
5362 | ||
69888674 AD |
5363 | /** |
5364 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
5365 | * @adapter: board private structure | |
5366 | * | |
5367 | * If this function returns with an error, then it's possible one or | |
5368 | * more of the rings is populated (while the rest are not). It is the | |
5369 | * callers duty to clean those orphaned rings. | |
5370 | * | |
5371 | * Return 0 on success, negative on failure | |
5372 | **/ | |
5373 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
5374 | { | |
5375 | int i, err = 0; | |
5376 | ||
5377 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
b6ec895e | 5378 | err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); |
69888674 AD |
5379 | if (!err) |
5380 | continue; | |
396e799c | 5381 | e_err(probe, "Allocation for Tx Queue %u failed\n", i); |
69888674 AD |
5382 | break; |
5383 | } | |
5384 | ||
5385 | return err; | |
5386 | } | |
5387 | ||
9a799d71 AK |
5388 | /** |
5389 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3a581073 | 5390 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
5391 | * |
5392 | * Returns 0 on success, negative on failure | |
5393 | **/ | |
b6ec895e | 5394 | int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 5395 | { |
b6ec895e | 5396 | struct device *dev = rx_ring->dev; |
021230d4 | 5397 | int size; |
9a799d71 | 5398 | |
3a581073 | 5399 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
89bf67f1 | 5400 | rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node); |
1a6c14a2 | 5401 | if (!rx_ring->rx_buffer_info) |
89bf67f1 | 5402 | rx_ring->rx_buffer_info = vzalloc(size); |
b6ec895e AD |
5403 | if (!rx_ring->rx_buffer_info) |
5404 | goto err; | |
9a799d71 | 5405 | |
9a799d71 | 5406 | /* Round up to nearest 4K */ |
3a581073 JB |
5407 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
5408 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 5409 | |
b6ec895e | 5410 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, |
1b507730 | 5411 | &rx_ring->dma, GFP_KERNEL); |
9a799d71 | 5412 | |
b6ec895e AD |
5413 | if (!rx_ring->desc) |
5414 | goto err; | |
9a799d71 | 5415 | |
3a581073 JB |
5416 | rx_ring->next_to_clean = 0; |
5417 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
5418 | |
5419 | return 0; | |
b6ec895e AD |
5420 | err: |
5421 | vfree(rx_ring->rx_buffer_info); | |
5422 | rx_ring->rx_buffer_info = NULL; | |
5423 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); | |
177db6ff | 5424 | return -ENOMEM; |
9a799d71 AK |
5425 | } |
5426 | ||
69888674 AD |
5427 | /** |
5428 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
5429 | * @adapter: board private structure | |
5430 | * | |
5431 | * If this function returns with an error, then it's possible one or | |
5432 | * more of the rings is populated (while the rest are not). It is the | |
5433 | * callers duty to clean those orphaned rings. | |
5434 | * | |
5435 | * Return 0 on success, negative on failure | |
5436 | **/ | |
69888674 AD |
5437 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) |
5438 | { | |
5439 | int i, err = 0; | |
5440 | ||
5441 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
b6ec895e | 5442 | err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); |
69888674 AD |
5443 | if (!err) |
5444 | continue; | |
396e799c | 5445 | e_err(probe, "Allocation for Rx Queue %u failed\n", i); |
69888674 AD |
5446 | break; |
5447 | } | |
5448 | ||
5449 | return err; | |
5450 | } | |
5451 | ||
9a799d71 AK |
5452 | /** |
5453 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
9a799d71 AK |
5454 | * @tx_ring: Tx descriptor ring for a specific queue |
5455 | * | |
5456 | * Free all transmit software resources | |
5457 | **/ | |
b6ec895e | 5458 | void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 5459 | { |
b6ec895e | 5460 | ixgbe_clean_tx_ring(tx_ring); |
9a799d71 AK |
5461 | |
5462 | vfree(tx_ring->tx_buffer_info); | |
5463 | tx_ring->tx_buffer_info = NULL; | |
5464 | ||
b6ec895e AD |
5465 | /* if not set, then don't free */ |
5466 | if (!tx_ring->desc) | |
5467 | return; | |
5468 | ||
5469 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
5470 | tx_ring->desc, tx_ring->dma); | |
9a799d71 AK |
5471 | |
5472 | tx_ring->desc = NULL; | |
5473 | } | |
5474 | ||
5475 | /** | |
5476 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
5477 | * @adapter: board private structure | |
5478 | * | |
5479 | * Free all transmit software resources | |
5480 | **/ | |
5481 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
5482 | { | |
5483 | int i; | |
5484 | ||
5485 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 5486 | if (adapter->tx_ring[i]->desc) |
b6ec895e | 5487 | ixgbe_free_tx_resources(adapter->tx_ring[i]); |
9a799d71 AK |
5488 | } |
5489 | ||
5490 | /** | |
b4617240 | 5491 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
5492 | * @rx_ring: ring to clean the resources from |
5493 | * | |
5494 | * Free all receive software resources | |
5495 | **/ | |
b6ec895e | 5496 | void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 5497 | { |
b6ec895e | 5498 | ixgbe_clean_rx_ring(rx_ring); |
9a799d71 AK |
5499 | |
5500 | vfree(rx_ring->rx_buffer_info); | |
5501 | rx_ring->rx_buffer_info = NULL; | |
5502 | ||
b6ec895e AD |
5503 | /* if not set, then don't free */ |
5504 | if (!rx_ring->desc) | |
5505 | return; | |
5506 | ||
5507 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
5508 | rx_ring->desc, rx_ring->dma); | |
9a799d71 AK |
5509 | |
5510 | rx_ring->desc = NULL; | |
5511 | } | |
5512 | ||
5513 | /** | |
5514 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
5515 | * @adapter: board private structure | |
5516 | * | |
5517 | * Free all receive software resources | |
5518 | **/ | |
5519 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
5520 | { | |
5521 | int i; | |
5522 | ||
5523 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 5524 | if (adapter->rx_ring[i]->desc) |
b6ec895e | 5525 | ixgbe_free_rx_resources(adapter->rx_ring[i]); |
9a799d71 AK |
5526 | } |
5527 | ||
9a799d71 AK |
5528 | /** |
5529 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
5530 | * @netdev: network interface device structure | |
5531 | * @new_mtu: new value for maximum frame size | |
5532 | * | |
5533 | * Returns 0 on success, negative on failure | |
5534 | **/ | |
5535 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
5536 | { | |
5537 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
16b61beb | 5538 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
5539 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; |
5540 | ||
42c783c5 | 5541 | /* MTU < 68 is an error and causes problems on some kernels */ |
e9f98072 GR |
5542 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED && |
5543 | hw->mac.type != ixgbe_mac_X540) { | |
5544 | if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE)) | |
5545 | return -EINVAL; | |
5546 | } else { | |
5547 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
5548 | return -EINVAL; | |
5549 | } | |
9a799d71 | 5550 | |
396e799c | 5551 | e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
021230d4 | 5552 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
5553 | netdev->mtu = new_mtu; |
5554 | ||
16b61beb JF |
5555 | hw->fc.high_water = FC_HIGH_WATER(max_frame); |
5556 | hw->fc.low_water = FC_LOW_WATER(max_frame); | |
5557 | ||
d4f80882 AV |
5558 | if (netif_running(netdev)) |
5559 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
5560 | |
5561 | return 0; | |
5562 | } | |
5563 | ||
5564 | /** | |
5565 | * ixgbe_open - Called when a network interface is made active | |
5566 | * @netdev: network interface device structure | |
5567 | * | |
5568 | * Returns 0 on success, negative value on failure | |
5569 | * | |
5570 | * The open entry point is called when a network interface is made | |
5571 | * active by the system (IFF_UP). At this point all resources needed | |
5572 | * for transmit and receive operations are allocated, the interrupt | |
5573 | * handler is registered with the OS, the watchdog timer is started, | |
5574 | * and the stack is notified that the interface is ready. | |
5575 | **/ | |
5576 | static int ixgbe_open(struct net_device *netdev) | |
5577 | { | |
5578 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5579 | int err; | |
4bebfaa5 AK |
5580 | |
5581 | /* disallow open during test */ | |
5582 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
5583 | return -EBUSY; | |
9a799d71 | 5584 | |
54386467 JB |
5585 | netif_carrier_off(netdev); |
5586 | ||
9a799d71 AK |
5587 | /* allocate transmit descriptors */ |
5588 | err = ixgbe_setup_all_tx_resources(adapter); | |
5589 | if (err) | |
5590 | goto err_setup_tx; | |
5591 | ||
9a799d71 AK |
5592 | /* allocate receive descriptors */ |
5593 | err = ixgbe_setup_all_rx_resources(adapter); | |
5594 | if (err) | |
5595 | goto err_setup_rx; | |
5596 | ||
5597 | ixgbe_configure(adapter); | |
5598 | ||
021230d4 | 5599 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
5600 | if (err) |
5601 | goto err_req_irq; | |
5602 | ||
9a799d71 AK |
5603 | err = ixgbe_up_complete(adapter); |
5604 | if (err) | |
5605 | goto err_up; | |
5606 | ||
d55b53ff JK |
5607 | netif_tx_start_all_queues(netdev); |
5608 | ||
9a799d71 AK |
5609 | return 0; |
5610 | ||
5611 | err_up: | |
5eba3699 | 5612 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5613 | ixgbe_free_irq(adapter); |
5614 | err_req_irq: | |
9a799d71 | 5615 | err_setup_rx: |
a20a1199 | 5616 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 5617 | err_setup_tx: |
a20a1199 | 5618 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
5619 | ixgbe_reset(adapter); |
5620 | ||
5621 | return err; | |
5622 | } | |
5623 | ||
5624 | /** | |
5625 | * ixgbe_close - Disables a network interface | |
5626 | * @netdev: network interface device structure | |
5627 | * | |
5628 | * Returns 0, this is not allowed to fail | |
5629 | * | |
5630 | * The close entry point is called when an interface is de-activated | |
5631 | * by the OS. The hardware is still under the drivers control, but | |
5632 | * needs to be disabled. A global MAC reset is issued to stop the | |
5633 | * hardware, and all transmit and receive resources are freed. | |
5634 | **/ | |
5635 | static int ixgbe_close(struct net_device *netdev) | |
5636 | { | |
5637 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
5638 | |
5639 | ixgbe_down(adapter); | |
5640 | ixgbe_free_irq(adapter); | |
5641 | ||
5642 | ixgbe_free_all_tx_resources(adapter); | |
5643 | ixgbe_free_all_rx_resources(adapter); | |
5644 | ||
5eba3699 | 5645 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5646 | |
5647 | return 0; | |
5648 | } | |
5649 | ||
b3c8b4ba AD |
5650 | #ifdef CONFIG_PM |
5651 | static int ixgbe_resume(struct pci_dev *pdev) | |
5652 | { | |
c60fbb00 AD |
5653 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
5654 | struct net_device *netdev = adapter->netdev; | |
b3c8b4ba AD |
5655 | u32 err; |
5656 | ||
5657 | pci_set_power_state(pdev, PCI_D0); | |
5658 | pci_restore_state(pdev); | |
656ab817 DS |
5659 | /* |
5660 | * pci_restore_state clears dev->state_saved so call | |
5661 | * pci_save_state to restore it. | |
5662 | */ | |
5663 | pci_save_state(pdev); | |
9ce77666 | 5664 | |
5665 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 5666 | if (err) { |
849c4542 | 5667 | e_dev_err("Cannot enable PCI device from suspend\n"); |
b3c8b4ba AD |
5668 | return err; |
5669 | } | |
5670 | pci_set_master(pdev); | |
5671 | ||
dd4d8ca6 | 5672 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
5673 | |
5674 | err = ixgbe_init_interrupt_scheme(adapter); | |
5675 | if (err) { | |
849c4542 | 5676 | e_dev_err("Cannot initialize interrupts for device\n"); |
b3c8b4ba AD |
5677 | return err; |
5678 | } | |
5679 | ||
b3c8b4ba AD |
5680 | ixgbe_reset(adapter); |
5681 | ||
495dce12 WJP |
5682 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
5683 | ||
b3c8b4ba | 5684 | if (netif_running(netdev)) { |
c60fbb00 | 5685 | err = ixgbe_open(netdev); |
b3c8b4ba AD |
5686 | if (err) |
5687 | return err; | |
5688 | } | |
5689 | ||
5690 | netif_device_attach(netdev); | |
5691 | ||
5692 | return 0; | |
5693 | } | |
b3c8b4ba | 5694 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
5695 | |
5696 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba | 5697 | { |
c60fbb00 AD |
5698 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
5699 | struct net_device *netdev = adapter->netdev; | |
e8e26350 PW |
5700 | struct ixgbe_hw *hw = &adapter->hw; |
5701 | u32 ctrl, fctrl; | |
5702 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
5703 | #ifdef CONFIG_PM |
5704 | int retval = 0; | |
5705 | #endif | |
5706 | ||
5707 | netif_device_detach(netdev); | |
5708 | ||
5709 | if (netif_running(netdev)) { | |
5710 | ixgbe_down(adapter); | |
5711 | ixgbe_free_irq(adapter); | |
5712 | ixgbe_free_all_tx_resources(adapter); | |
5713 | ixgbe_free_all_rx_resources(adapter); | |
5714 | } | |
b3c8b4ba | 5715 | |
5f5ae6fc | 5716 | ixgbe_clear_interrupt_scheme(adapter); |
d033d526 JF |
5717 | #ifdef CONFIG_DCB |
5718 | kfree(adapter->ixgbe_ieee_pfc); | |
5719 | kfree(adapter->ixgbe_ieee_ets); | |
5720 | #endif | |
5f5ae6fc | 5721 | |
b3c8b4ba AD |
5722 | #ifdef CONFIG_PM |
5723 | retval = pci_save_state(pdev); | |
5724 | if (retval) | |
5725 | return retval; | |
4df10466 | 5726 | |
b3c8b4ba | 5727 | #endif |
e8e26350 PW |
5728 | if (wufc) { |
5729 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 5730 | |
e8e26350 PW |
5731 | /* turn on all-multi mode if wake on multicast is enabled */ |
5732 | if (wufc & IXGBE_WUFC_MC) { | |
5733 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5734 | fctrl |= IXGBE_FCTRL_MPE; | |
5735 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
5736 | } | |
5737 | ||
5738 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
5739 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
5740 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
5741 | ||
5742 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
5743 | } else { | |
5744 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
5745 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
5746 | } | |
5747 | ||
bd508178 AD |
5748 | switch (hw->mac.type) { |
5749 | case ixgbe_mac_82598EB: | |
dd4d8ca6 | 5750 | pci_wake_from_d3(pdev, false); |
bd508178 AD |
5751 | break; |
5752 | case ixgbe_mac_82599EB: | |
b93a2226 | 5753 | case ixgbe_mac_X540: |
bd508178 AD |
5754 | pci_wake_from_d3(pdev, !!wufc); |
5755 | break; | |
5756 | default: | |
5757 | break; | |
5758 | } | |
b3c8b4ba | 5759 | |
9d8d05ae RW |
5760 | *enable_wake = !!wufc; |
5761 | ||
b3c8b4ba AD |
5762 | ixgbe_release_hw_control(adapter); |
5763 | ||
5764 | pci_disable_device(pdev); | |
5765 | ||
9d8d05ae RW |
5766 | return 0; |
5767 | } | |
5768 | ||
5769 | #ifdef CONFIG_PM | |
5770 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
5771 | { | |
5772 | int retval; | |
5773 | bool wake; | |
5774 | ||
5775 | retval = __ixgbe_shutdown(pdev, &wake); | |
5776 | if (retval) | |
5777 | return retval; | |
5778 | ||
5779 | if (wake) { | |
5780 | pci_prepare_to_sleep(pdev); | |
5781 | } else { | |
5782 | pci_wake_from_d3(pdev, false); | |
5783 | pci_set_power_state(pdev, PCI_D3hot); | |
5784 | } | |
b3c8b4ba AD |
5785 | |
5786 | return 0; | |
5787 | } | |
9d8d05ae | 5788 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
5789 | |
5790 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
5791 | { | |
9d8d05ae RW |
5792 | bool wake; |
5793 | ||
5794 | __ixgbe_shutdown(pdev, &wake); | |
5795 | ||
5796 | if (system_state == SYSTEM_POWER_OFF) { | |
5797 | pci_wake_from_d3(pdev, wake); | |
5798 | pci_set_power_state(pdev, PCI_D3hot); | |
5799 | } | |
b3c8b4ba AD |
5800 | } |
5801 | ||
9a799d71 AK |
5802 | /** |
5803 | * ixgbe_update_stats - Update the board statistics counters. | |
5804 | * @adapter: board private structure | |
5805 | **/ | |
5806 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
5807 | { | |
2d86f139 | 5808 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 5809 | struct ixgbe_hw *hw = &adapter->hw; |
5b7da515 | 5810 | struct ixgbe_hw_stats *hwstats = &adapter->stats; |
6f11eef7 AV |
5811 | u64 total_mpc = 0; |
5812 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
5b7da515 AD |
5813 | u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; |
5814 | u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; | |
5815 | u64 bytes = 0, packets = 0; | |
9a799d71 | 5816 | |
d08935c2 DS |
5817 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5818 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5819 | return; | |
5820 | ||
94b982b2 | 5821 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 5822 | u64 rsc_count = 0; |
94b982b2 | 5823 | u64 rsc_flush = 0; |
d51019a4 PW |
5824 | for (i = 0; i < 16; i++) |
5825 | adapter->hw_rx_no_dma_resources += | |
7ca647bd | 5826 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); |
94b982b2 | 5827 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5b7da515 AD |
5828 | rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; |
5829 | rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; | |
94b982b2 MC |
5830 | } |
5831 | adapter->rsc_total_count = rsc_count; | |
5832 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
5833 | } |
5834 | ||
5b7da515 AD |
5835 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5836 | struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; | |
5837 | non_eop_descs += rx_ring->rx_stats.non_eop_descs; | |
5838 | alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; | |
5839 | alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; | |
5840 | bytes += rx_ring->stats.bytes; | |
5841 | packets += rx_ring->stats.packets; | |
5842 | } | |
5843 | adapter->non_eop_descs = non_eop_descs; | |
5844 | adapter->alloc_rx_page_failed = alloc_rx_page_failed; | |
5845 | adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; | |
5846 | netdev->stats.rx_bytes = bytes; | |
5847 | netdev->stats.rx_packets = packets; | |
5848 | ||
5849 | bytes = 0; | |
5850 | packets = 0; | |
7ca3bc58 | 5851 | /* gather some stats to the adapter struct that are per queue */ |
5b7da515 AD |
5852 | for (i = 0; i < adapter->num_tx_queues; i++) { |
5853 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
5854 | restart_queue += tx_ring->tx_stats.restart_queue; | |
5855 | tx_busy += tx_ring->tx_stats.tx_busy; | |
5856 | bytes += tx_ring->stats.bytes; | |
5857 | packets += tx_ring->stats.packets; | |
5858 | } | |
eb985f09 | 5859 | adapter->restart_queue = restart_queue; |
5b7da515 AD |
5860 | adapter->tx_busy = tx_busy; |
5861 | netdev->stats.tx_bytes = bytes; | |
5862 | netdev->stats.tx_packets = packets; | |
7ca3bc58 | 5863 | |
7ca647bd | 5864 | hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
6f11eef7 AV |
5865 | for (i = 0; i < 8; i++) { |
5866 | /* for packet buffers not used, the register should read 0 */ | |
5867 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
5868 | missed_rx += mpc; | |
7ca647bd JP |
5869 | hwstats->mpc[i] += mpc; |
5870 | total_mpc += hwstats->mpc[i]; | |
e8e26350 | 5871 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
5872 | hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
5873 | hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
5874 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
5875 | hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
5876 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
bd508178 AD |
5877 | switch (hw->mac.type) { |
5878 | case ixgbe_mac_82598EB: | |
7ca647bd JP |
5879 | hwstats->pxonrxc[i] += |
5880 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
bd508178 AD |
5881 | break; |
5882 | case ixgbe_mac_82599EB: | |
b93a2226 | 5883 | case ixgbe_mac_X540: |
bd508178 AD |
5884 | hwstats->pxonrxc[i] += |
5885 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
bd508178 AD |
5886 | break; |
5887 | default: | |
5888 | break; | |
e8e26350 | 5889 | } |
7ca647bd JP |
5890 | hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
5891 | hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
6f11eef7 | 5892 | } |
7ca647bd | 5893 | hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); |
6f11eef7 | 5894 | /* work around hardware counting issue */ |
7ca647bd | 5895 | hwstats->gprc -= missed_rx; |
6f11eef7 | 5896 | |
c84d324c JF |
5897 | ixgbe_update_xoff_received(adapter); |
5898 | ||
6f11eef7 | 5899 | /* 82598 hardware only has a 32 bit counter in the high register */ |
bd508178 AD |
5900 | switch (hw->mac.type) { |
5901 | case ixgbe_mac_82598EB: | |
5902 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
bd508178 AD |
5903 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
5904 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
5905 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
5906 | break; | |
5907 | case ixgbe_mac_82599EB: | |
b93a2226 | 5908 | case ixgbe_mac_X540: |
7ca647bd | 5909 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
bd508178 | 5910 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ |
7ca647bd | 5911 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
bd508178 | 5912 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ |
7ca647bd | 5913 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
bd508178 | 5914 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
7ca647bd | 5915 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
7ca647bd JP |
5916 | hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
5917 | hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c | 5918 | #ifdef IXGBE_FCOE |
7ca647bd JP |
5919 | hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); |
5920 | hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
5921 | hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
5922 | hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
5923 | hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
5924 | hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
6d45522c | 5925 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5926 | break; |
5927 | default: | |
5928 | break; | |
e8e26350 | 5929 | } |
9a799d71 | 5930 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
7ca647bd JP |
5931 | hwstats->bprc += bprc; |
5932 | hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 | 5933 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
5934 | hwstats->mprc -= bprc; |
5935 | hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
5936 | hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
5937 | hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
5938 | hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
5939 | hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
5940 | hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
5941 | hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
5942 | hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); | |
6f11eef7 | 5943 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
7ca647bd | 5944 | hwstats->lxontxc += lxon; |
6f11eef7 | 5945 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
7ca647bd JP |
5946 | hwstats->lxofftxc += lxoff; |
5947 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
5948 | hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
5949 | hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); | |
6f11eef7 AV |
5950 | /* |
5951 | * 82598 errata - tx of flow control packets is included in tx counters | |
5952 | */ | |
5953 | xon_off_tot = lxon + lxoff; | |
7ca647bd JP |
5954 | hwstats->gptc -= xon_off_tot; |
5955 | hwstats->mptc -= xon_off_tot; | |
5956 | hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
5957 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
5958 | hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
5959 | hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
5960 | hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); | |
5961 | hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
5962 | hwstats->ptc64 -= xon_off_tot; | |
5963 | hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); | |
5964 | hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
5965 | hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
5966 | hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
5967 | hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
5968 | hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); | |
9a799d71 AK |
5969 | |
5970 | /* Fill out the OS statistics structure */ | |
7ca647bd | 5971 | netdev->stats.multicast = hwstats->mprc; |
9a799d71 AK |
5972 | |
5973 | /* Rx Errors */ | |
7ca647bd | 5974 | netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; |
2d86f139 | 5975 | netdev->stats.rx_dropped = 0; |
7ca647bd JP |
5976 | netdev->stats.rx_length_errors = hwstats->rlec; |
5977 | netdev->stats.rx_crc_errors = hwstats->crcerrs; | |
2d86f139 | 5978 | netdev->stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
5979 | } |
5980 | ||
5981 | /** | |
5982 | * ixgbe_watchdog - Timer Call-back | |
5983 | * @data: pointer to adapter cast into an unsigned long | |
5984 | **/ | |
5985 | static void ixgbe_watchdog(unsigned long data) | |
5986 | { | |
5987 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee | 5988 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
5989 | u64 eics = 0; |
5990 | int i; | |
cf8280ee | 5991 | |
fe49f04a AD |
5992 | /* |
5993 | * Do the watchdog outside of interrupt context due to the lovely | |
5994 | * delays that some of the newer hardware requires | |
5995 | */ | |
22d5a71b | 5996 | |
fe49f04a AD |
5997 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
5998 | goto watchdog_short_circuit; | |
22d5a71b | 5999 | |
fe49f04a AD |
6000 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
6001 | /* | |
6002 | * for legacy and MSI interrupts don't set any bits | |
6003 | * that are enabled for EIAM, because this operation | |
6004 | * would set *both* EIMS and EICS for any bit in EIAM | |
6005 | */ | |
6006 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
6007 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
6008 | goto watchdog_reschedule; | |
6009 | } | |
6010 | ||
6011 | /* get one bit for every active tx/rx interrupt vector */ | |
6012 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { | |
6013 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; | |
6014 | if (qv->rxr_count || qv->txr_count) | |
6015 | eics |= ((u64)1 << i); | |
cf8280ee | 6016 | } |
9a799d71 | 6017 | |
fe49f04a AD |
6018 | /* Cause software interrupt to ensure rx rings are cleaned */ |
6019 | ixgbe_irq_rearm_queues(adapter, eics); | |
6020 | ||
6021 | watchdog_reschedule: | |
6022 | /* Reset the timer */ | |
6023 | mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ)); | |
6024 | ||
6025 | watchdog_short_circuit: | |
cf8280ee JB |
6026 | schedule_work(&adapter->watchdog_task); |
6027 | } | |
6028 | ||
e8e26350 PW |
6029 | /** |
6030 | * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber | |
6031 | * @work: pointer to work_struct containing our data | |
6032 | **/ | |
6033 | static void ixgbe_multispeed_fiber_task(struct work_struct *work) | |
6034 | { | |
6035 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
6036 | struct ixgbe_adapter, |
6037 | multispeed_fiber_task); | |
e8e26350 PW |
6038 | struct ixgbe_hw *hw = &adapter->hw; |
6039 | u32 autoneg; | |
8620a103 | 6040 | bool negotiation; |
e8e26350 PW |
6041 | |
6042 | adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK; | |
a1f25324 MC |
6043 | autoneg = hw->phy.autoneg_advertised; |
6044 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
8620a103 | 6045 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); |
1097cd17 | 6046 | hw->mac.autotry_restart = false; |
8620a103 MC |
6047 | if (hw->mac.ops.setup_link) |
6048 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
e8e26350 PW |
6049 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
6050 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK; | |
6051 | } | |
6052 | ||
6053 | /** | |
6054 | * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module | |
6055 | * @work: pointer to work_struct containing our data | |
6056 | **/ | |
6057 | static void ixgbe_sfp_config_module_task(struct work_struct *work) | |
6058 | { | |
6059 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
6060 | struct ixgbe_adapter, |
6061 | sfp_config_module_task); | |
e8e26350 PW |
6062 | struct ixgbe_hw *hw = &adapter->hw; |
6063 | u32 err; | |
6064 | ||
6065 | adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK; | |
63d6e1d8 DS |
6066 | |
6067 | /* Time for electrical oscillations to settle down */ | |
6068 | msleep(100); | |
e8e26350 | 6069 | err = hw->phy.ops.identify_sfp(hw); |
63d6e1d8 | 6070 | |
e8e26350 | 6071 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { |
849c4542 ET |
6072 | e_dev_err("failed to initialize because an unsupported SFP+ " |
6073 | "module type was detected.\n"); | |
6074 | e_dev_err("Reload the driver after installing a supported " | |
6075 | "module.\n"); | |
63d6e1d8 | 6076 | unregister_netdev(adapter->netdev); |
e8e26350 PW |
6077 | return; |
6078 | } | |
4c7e604b AG |
6079 | if (hw->mac.ops.setup_sfp) |
6080 | hw->mac.ops.setup_sfp(hw); | |
e8e26350 | 6081 | |
8d1c3c07 | 6082 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) |
e8e26350 PW |
6083 | /* This will also work for DA Twinax connections */ |
6084 | schedule_work(&adapter->multispeed_fiber_task); | |
6085 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK; | |
6086 | } | |
6087 | ||
c4cf55e5 PWJ |
6088 | /** |
6089 | * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table | |
6090 | * @work: pointer to work_struct containing our data | |
6091 | **/ | |
6092 | static void ixgbe_fdir_reinit_task(struct work_struct *work) | |
6093 | { | |
6094 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
6095 | struct ixgbe_adapter, |
6096 | fdir_reinit_task); | |
c4cf55e5 PWJ |
6097 | struct ixgbe_hw *hw = &adapter->hw; |
6098 | int i; | |
6099 | ||
6100 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { | |
6101 | for (i = 0; i < adapter->num_tx_queues; i++) | |
7d637bcc AD |
6102 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, |
6103 | &(adapter->tx_ring[i]->state)); | |
c4cf55e5 | 6104 | } else { |
396e799c | 6105 | e_err(probe, "failed to finish FDIR re-initialization, " |
849c4542 | 6106 | "ignored adding FDIR ATR filters\n"); |
c4cf55e5 PWJ |
6107 | } |
6108 | /* Done FDIR Re-initialization, enable transmits */ | |
6109 | netif_tx_start_all_queues(adapter->netdev); | |
6110 | } | |
6111 | ||
a985b6c3 GR |
6112 | static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) |
6113 | { | |
6114 | u32 ssvpc; | |
6115 | ||
6116 | /* Do not perform spoof check for 82598 */ | |
6117 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
6118 | return; | |
6119 | ||
6120 | ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); | |
6121 | ||
6122 | /* | |
6123 | * ssvpc register is cleared on read, if zero then no | |
6124 | * spoofed packets in the last interval. | |
6125 | */ | |
6126 | if (!ssvpc) | |
6127 | return; | |
6128 | ||
6129 | e_warn(drv, "%d Spoofed packets detected\n", ssvpc); | |
6130 | } | |
6131 | ||
10eec955 JF |
6132 | static DEFINE_MUTEX(ixgbe_watchdog_lock); |
6133 | ||
cf8280ee | 6134 | /** |
69888674 AD |
6135 | * ixgbe_watchdog_task - worker thread to bring link up |
6136 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
6137 | **/ |
6138 | static void ixgbe_watchdog_task(struct work_struct *work) | |
6139 | { | |
6140 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
6141 | struct ixgbe_adapter, |
6142 | watchdog_task); | |
cf8280ee JB |
6143 | struct net_device *netdev = adapter->netdev; |
6144 | struct ixgbe_hw *hw = &adapter->hw; | |
10eec955 JF |
6145 | u32 link_speed; |
6146 | bool link_up; | |
bc59fcda NS |
6147 | int i; |
6148 | struct ixgbe_ring *tx_ring; | |
6149 | int some_tx_pending = 0; | |
cf8280ee | 6150 | |
10eec955 JF |
6151 | mutex_lock(&ixgbe_watchdog_lock); |
6152 | ||
6153 | link_up = adapter->link_up; | |
6154 | link_speed = adapter->link_speed; | |
cf8280ee JB |
6155 | |
6156 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
6157 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
264857b8 PWJ |
6158 | if (link_up) { |
6159 | #ifdef CONFIG_DCB | |
6160 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
6161 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) | |
620fa036 | 6162 | hw->mac.ops.fc_enable(hw, i); |
264857b8 | 6163 | } else { |
620fa036 | 6164 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
6165 | } |
6166 | #else | |
620fa036 | 6167 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
6168 | #endif |
6169 | } | |
6170 | ||
cf8280ee JB |
6171 | if (link_up || |
6172 | time_after(jiffies, (adapter->link_check_timeout + | |
e8e9f696 | 6173 | IXGBE_TRY_LINK_TIMEOUT))) { |
cf8280ee | 6174 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
264857b8 | 6175 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); |
cf8280ee JB |
6176 | } |
6177 | adapter->link_up = link_up; | |
6178 | adapter->link_speed = link_speed; | |
6179 | } | |
9a799d71 AK |
6180 | |
6181 | if (link_up) { | |
6182 | if (!netif_carrier_ok(netdev)) { | |
e8e26350 PW |
6183 | bool flow_rx, flow_tx; |
6184 | ||
bd508178 AD |
6185 | switch (hw->mac.type) { |
6186 | case ixgbe_mac_82598EB: { | |
e8e26350 PW |
6187 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
6188 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
078788b6 PWJ |
6189 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); |
6190 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
e8e26350 | 6191 | } |
bd508178 | 6192 | break; |
b93a2226 DS |
6193 | case ixgbe_mac_82599EB: |
6194 | case ixgbe_mac_X540: { | |
bd508178 AD |
6195 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); |
6196 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
6197 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); | |
6198 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
6199 | } | |
6200 | break; | |
6201 | default: | |
6202 | flow_tx = false; | |
6203 | flow_rx = false; | |
6204 | break; | |
6205 | } | |
e8e26350 | 6206 | |
396e799c | 6207 | e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", |
a46e534b | 6208 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? |
849c4542 ET |
6209 | "10 Gbps" : |
6210 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
1b1c0a48 AS |
6211 | "1 Gbps" : |
6212 | (link_speed == IXGBE_LINK_SPEED_100_FULL ? | |
6213 | "100 Mbps" : | |
6214 | "unknown speed"))), | |
e8e26350 | 6215 | ((flow_rx && flow_tx) ? "RX/TX" : |
849c4542 ET |
6216 | (flow_rx ? "RX" : |
6217 | (flow_tx ? "TX" : "None")))); | |
9a799d71 AK |
6218 | |
6219 | netif_carrier_on(netdev); | |
ff4ab206 | 6220 | ixgbe_check_vf_rate_limit(adapter); |
9a799d71 AK |
6221 | } else { |
6222 | /* Force detection of hung controller */ | |
7d637bcc AD |
6223 | for (i = 0; i < adapter->num_tx_queues; i++) { |
6224 | tx_ring = adapter->tx_ring[i]; | |
6225 | set_check_for_tx_hang(tx_ring); | |
6226 | } | |
9a799d71 AK |
6227 | } |
6228 | } else { | |
cf8280ee JB |
6229 | adapter->link_up = false; |
6230 | adapter->link_speed = 0; | |
9a799d71 | 6231 | if (netif_carrier_ok(netdev)) { |
396e799c | 6232 | e_info(drv, "NIC Link is Down\n"); |
9a799d71 | 6233 | netif_carrier_off(netdev); |
9a799d71 AK |
6234 | } |
6235 | } | |
6236 | ||
bc59fcda NS |
6237 | if (!netif_carrier_ok(netdev)) { |
6238 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 6239 | tx_ring = adapter->tx_ring[i]; |
bc59fcda NS |
6240 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { |
6241 | some_tx_pending = 1; | |
6242 | break; | |
6243 | } | |
6244 | } | |
6245 | ||
6246 | if (some_tx_pending) { | |
6247 | /* We've lost link, so the controller stops DMA, | |
6248 | * but we've got queued Tx work that's never going | |
6249 | * to get done, so reset controller to flush Tx. | |
6250 | * (Do the reset outside of interrupt context). | |
6251 | */ | |
6252 | schedule_work(&adapter->reset_task); | |
6253 | } | |
6254 | } | |
6255 | ||
a985b6c3 | 6256 | ixgbe_spoof_check(adapter); |
9a799d71 | 6257 | ixgbe_update_stats(adapter); |
10eec955 | 6258 | mutex_unlock(&ixgbe_watchdog_lock); |
9a799d71 AK |
6259 | } |
6260 | ||
9a799d71 | 6261 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
e8e9f696 | 6262 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
5e09a105 | 6263 | u32 tx_flags, u8 *hdr_len, __be16 protocol) |
9a799d71 AK |
6264 | { |
6265 | struct ixgbe_adv_tx_context_desc *context_desc; | |
6266 | unsigned int i; | |
6267 | int err; | |
6268 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
6269 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
6270 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
6271 | |
6272 | if (skb_is_gso(skb)) { | |
6273 | if (skb_header_cloned(skb)) { | |
6274 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
6275 | if (err) | |
6276 | return err; | |
6277 | } | |
6278 | l4len = tcp_hdrlen(skb); | |
6279 | *hdr_len += l4len; | |
6280 | ||
5e09a105 | 6281 | if (protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
6282 | struct iphdr *iph = ip_hdr(skb); |
6283 | iph->tot_len = 0; | |
6284 | iph->check = 0; | |
6285 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
e8e9f696 JP |
6286 | iph->daddr, 0, |
6287 | IPPROTO_TCP, | |
6288 | 0); | |
8e1e8a47 | 6289 | } else if (skb_is_gso_v6(skb)) { |
9a799d71 AK |
6290 | ipv6_hdr(skb)->payload_len = 0; |
6291 | tcp_hdr(skb)->check = | |
6292 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
e8e9f696 JP |
6293 | &ipv6_hdr(skb)->daddr, |
6294 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
6295 | } |
6296 | ||
6297 | i = tx_ring->next_to_use; | |
6298 | ||
6299 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
31f05a2d | 6300 | context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i); |
9a799d71 AK |
6301 | |
6302 | /* VLAN MACLEN IPLEN */ | |
6303 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
6304 | vlan_macip_lens |= | |
6305 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
6306 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
e8e9f696 | 6307 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
6308 | *hdr_len += skb_network_offset(skb); |
6309 | vlan_macip_lens |= | |
6310 | (skb_transport_header(skb) - skb_network_header(skb)); | |
6311 | *hdr_len += | |
6312 | (skb_transport_header(skb) - skb_network_header(skb)); | |
6313 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
6314 | context_desc->seqnum_seed = 0; | |
6315 | ||
6316 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 6317 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
e8e9f696 | 6318 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 6319 | |
5e09a105 | 6320 | if (protocol == htons(ETH_P_IP)) |
9a799d71 AK |
6321 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
6322 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
6323 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
6324 | ||
6325 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 6326 | mss_l4len_idx = |
9a799d71 AK |
6327 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
6328 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
6329 | /* use index 1 for TSO */ |
6330 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
6331 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
6332 | ||
6333 | tx_buffer_info->time_stamp = jiffies; | |
6334 | tx_buffer_info->next_to_watch = i; | |
6335 | ||
6336 | i++; | |
6337 | if (i == tx_ring->count) | |
6338 | i = 0; | |
6339 | tx_ring->next_to_use = i; | |
6340 | ||
6341 | return true; | |
6342 | } | |
6343 | return false; | |
6344 | } | |
6345 | ||
5e09a105 HZ |
6346 | static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb, |
6347 | __be16 protocol) | |
7ca647bd JP |
6348 | { |
6349 | u32 rtn = 0; | |
7ca647bd JP |
6350 | |
6351 | switch (protocol) { | |
6352 | case cpu_to_be16(ETH_P_IP): | |
6353 | rtn |= IXGBE_ADVTXD_TUCMD_IPV4; | |
6354 | switch (ip_hdr(skb)->protocol) { | |
6355 | case IPPROTO_TCP: | |
6356 | rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
6357 | break; | |
6358 | case IPPROTO_SCTP: | |
6359 | rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
6360 | break; | |
6361 | } | |
6362 | break; | |
6363 | case cpu_to_be16(ETH_P_IPV6): | |
6364 | /* XXX what about other V6 headers?? */ | |
6365 | switch (ipv6_hdr(skb)->nexthdr) { | |
6366 | case IPPROTO_TCP: | |
6367 | rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
6368 | break; | |
6369 | case IPPROTO_SCTP: | |
6370 | rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
6371 | break; | |
6372 | } | |
6373 | break; | |
6374 | default: | |
6375 | if (unlikely(net_ratelimit())) | |
6376 | e_warn(probe, "partial checksum but proto=%x!\n", | |
5e09a105 | 6377 | protocol); |
7ca647bd JP |
6378 | break; |
6379 | } | |
6380 | ||
6381 | return rtn; | |
6382 | } | |
6383 | ||
9a799d71 | 6384 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, |
e8e9f696 | 6385 | struct ixgbe_ring *tx_ring, |
5e09a105 HZ |
6386 | struct sk_buff *skb, u32 tx_flags, |
6387 | __be16 protocol) | |
9a799d71 AK |
6388 | { |
6389 | struct ixgbe_adv_tx_context_desc *context_desc; | |
6390 | unsigned int i; | |
6391 | struct ixgbe_tx_buffer *tx_buffer_info; | |
6392 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
6393 | ||
6394 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
6395 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
6396 | i = tx_ring->next_to_use; | |
6397 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
31f05a2d | 6398 | context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i); |
9a799d71 AK |
6399 | |
6400 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
6401 | vlan_macip_lens |= | |
6402 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
6403 | vlan_macip_lens |= (skb_network_offset(skb) << | |
e8e9f696 | 6404 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
6405 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
6406 | vlan_macip_lens |= (skb_transport_header(skb) - | |
e8e9f696 | 6407 | skb_network_header(skb)); |
9a799d71 AK |
6408 | |
6409 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
6410 | context_desc->seqnum_seed = 0; | |
6411 | ||
6412 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
e8e9f696 | 6413 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 6414 | |
7ca647bd | 6415 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
5e09a105 | 6416 | type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol); |
9a799d71 AK |
6417 | |
6418 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 6419 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
6420 | context_desc->mss_l4len_idx = 0; |
6421 | ||
6422 | tx_buffer_info->time_stamp = jiffies; | |
6423 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 6424 | |
9a799d71 AK |
6425 | i++; |
6426 | if (i == tx_ring->count) | |
6427 | i = 0; | |
6428 | tx_ring->next_to_use = i; | |
6429 | ||
6430 | return true; | |
6431 | } | |
9f8cdf4f | 6432 | |
9a799d71 AK |
6433 | return false; |
6434 | } | |
6435 | ||
6436 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
e8e9f696 JP |
6437 | struct ixgbe_ring *tx_ring, |
6438 | struct sk_buff *skb, u32 tx_flags, | |
8ad494b0 | 6439 | unsigned int first, const u8 hdr_len) |
9a799d71 | 6440 | { |
b6ec895e | 6441 | struct device *dev = tx_ring->dev; |
9a799d71 | 6442 | struct ixgbe_tx_buffer *tx_buffer_info; |
eacd73f7 YZ |
6443 | unsigned int len; |
6444 | unsigned int total = skb->len; | |
9a799d71 AK |
6445 | unsigned int offset = 0, size, count = 0, i; |
6446 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
6447 | unsigned int f; | |
8ad494b0 AD |
6448 | unsigned int bytecount = skb->len; |
6449 | u16 gso_segs = 1; | |
9a799d71 AK |
6450 | |
6451 | i = tx_ring->next_to_use; | |
6452 | ||
eacd73f7 YZ |
6453 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) |
6454 | /* excluding fcoe_crc_eof for FCoE */ | |
6455 | total -= sizeof(struct fcoe_crc_eof); | |
6456 | ||
6457 | len = min(skb_headlen(skb), total); | |
9a799d71 AK |
6458 | while (len) { |
6459 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
6460 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
6461 | ||
6462 | tx_buffer_info->length = size; | |
e5a43549 | 6463 | tx_buffer_info->mapped_as_page = false; |
b6ec895e | 6464 | tx_buffer_info->dma = dma_map_single(dev, |
e5a43549 | 6465 | skb->data + offset, |
1b507730 | 6466 | size, DMA_TO_DEVICE); |
b6ec895e | 6467 | if (dma_mapping_error(dev, tx_buffer_info->dma)) |
e5a43549 | 6468 | goto dma_error; |
9a799d71 AK |
6469 | tx_buffer_info->time_stamp = jiffies; |
6470 | tx_buffer_info->next_to_watch = i; | |
6471 | ||
6472 | len -= size; | |
eacd73f7 | 6473 | total -= size; |
9a799d71 AK |
6474 | offset += size; |
6475 | count++; | |
44df32c5 AD |
6476 | |
6477 | if (len) { | |
6478 | i++; | |
6479 | if (i == tx_ring->count) | |
6480 | i = 0; | |
6481 | } | |
9a799d71 AK |
6482 | } |
6483 | ||
6484 | for (f = 0; f < nr_frags; f++) { | |
6485 | struct skb_frag_struct *frag; | |
6486 | ||
6487 | frag = &skb_shinfo(skb)->frags[f]; | |
eacd73f7 | 6488 | len = min((unsigned int)frag->size, total); |
e5a43549 | 6489 | offset = frag->page_offset; |
9a799d71 AK |
6490 | |
6491 | while (len) { | |
44df32c5 AD |
6492 | i++; |
6493 | if (i == tx_ring->count) | |
6494 | i = 0; | |
6495 | ||
9a799d71 AK |
6496 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
6497 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
6498 | ||
6499 | tx_buffer_info->length = size; | |
b6ec895e | 6500 | tx_buffer_info->dma = dma_map_page(dev, |
e5a43549 AD |
6501 | frag->page, |
6502 | offset, size, | |
1b507730 | 6503 | DMA_TO_DEVICE); |
e5a43549 | 6504 | tx_buffer_info->mapped_as_page = true; |
b6ec895e | 6505 | if (dma_mapping_error(dev, tx_buffer_info->dma)) |
e5a43549 | 6506 | goto dma_error; |
9a799d71 AK |
6507 | tx_buffer_info->time_stamp = jiffies; |
6508 | tx_buffer_info->next_to_watch = i; | |
6509 | ||
6510 | len -= size; | |
eacd73f7 | 6511 | total -= size; |
9a799d71 AK |
6512 | offset += size; |
6513 | count++; | |
9a799d71 | 6514 | } |
eacd73f7 YZ |
6515 | if (total == 0) |
6516 | break; | |
9a799d71 | 6517 | } |
44df32c5 | 6518 | |
8ad494b0 AD |
6519 | if (tx_flags & IXGBE_TX_FLAGS_TSO) |
6520 | gso_segs = skb_shinfo(skb)->gso_segs; | |
6521 | #ifdef IXGBE_FCOE | |
6522 | /* adjust for FCoE Sequence Offload */ | |
6523 | else if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
6524 | gso_segs = DIV_ROUND_UP(skb->len - hdr_len, | |
6525 | skb_shinfo(skb)->gso_size); | |
6526 | #endif /* IXGBE_FCOE */ | |
6527 | bytecount += (gso_segs - 1) * hdr_len; | |
6528 | ||
6529 | /* multiply data chunks by size of headers */ | |
6530 | tx_ring->tx_buffer_info[i].bytecount = bytecount; | |
6531 | tx_ring->tx_buffer_info[i].gso_segs = gso_segs; | |
9a799d71 AK |
6532 | tx_ring->tx_buffer_info[i].skb = skb; |
6533 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
6534 | ||
e5a43549 AD |
6535 | return count; |
6536 | ||
6537 | dma_error: | |
849c4542 | 6538 | e_dev_err("TX DMA map failed\n"); |
e5a43549 AD |
6539 | |
6540 | /* clear timestamp and dma mappings for failed tx_buffer_info map */ | |
6541 | tx_buffer_info->dma = 0; | |
6542 | tx_buffer_info->time_stamp = 0; | |
6543 | tx_buffer_info->next_to_watch = 0; | |
c1fa347f RK |
6544 | if (count) |
6545 | count--; | |
e5a43549 AD |
6546 | |
6547 | /* clear timestamp and dma mappings for remaining portion of packet */ | |
c1fa347f | 6548 | while (count--) { |
e8e9f696 | 6549 | if (i == 0) |
e5a43549 | 6550 | i += tx_ring->count; |
c1fa347f | 6551 | i--; |
e5a43549 | 6552 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
b6ec895e | 6553 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
e5a43549 AD |
6554 | } |
6555 | ||
e44d38e1 | 6556 | return 0; |
9a799d71 AK |
6557 | } |
6558 | ||
84ea2591 | 6559 | static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring, |
e8e9f696 | 6560 | int tx_flags, int count, u32 paylen, u8 hdr_len) |
9a799d71 AK |
6561 | { |
6562 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
6563 | struct ixgbe_tx_buffer *tx_buffer_info; | |
6564 | u32 olinfo_status = 0, cmd_type_len = 0; | |
6565 | unsigned int i; | |
6566 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
6567 | ||
6568 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
6569 | ||
6570 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
6571 | ||
6572 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
6573 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
6574 | ||
6575 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
6576 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
6577 | ||
6578 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
e8e9f696 | 6579 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 6580 | |
4eeae6fd PW |
6581 | /* use index 1 context for tso */ |
6582 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
6583 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
6584 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
e8e9f696 | 6585 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
6586 | |
6587 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
6588 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
e8e9f696 | 6589 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 6590 | |
eacd73f7 YZ |
6591 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
6592 | olinfo_status |= IXGBE_ADVTXD_CC; | |
6593 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
6594 | if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
6595 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
6596 | } | |
6597 | ||
9a799d71 AK |
6598 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); |
6599 | ||
6600 | i = tx_ring->next_to_use; | |
6601 | while (count--) { | |
6602 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
31f05a2d | 6603 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i); |
9a799d71 AK |
6604 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); |
6605 | tx_desc->read.cmd_type_len = | |
e8e9f696 | 6606 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 6607 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
6608 | i++; |
6609 | if (i == tx_ring->count) | |
6610 | i = 0; | |
6611 | } | |
6612 | ||
6613 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
6614 | ||
6615 | /* | |
6616 | * Force memory writes to complete before letting h/w | |
6617 | * know there are new descriptors to fetch. (Only | |
6618 | * applicable for weak-ordered memory model archs, | |
6619 | * such as IA-64). | |
6620 | */ | |
6621 | wmb(); | |
6622 | ||
6623 | tx_ring->next_to_use = i; | |
84ea2591 | 6624 | writel(i, tx_ring->tail); |
9a799d71 AK |
6625 | } |
6626 | ||
69830529 AD |
6627 | static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb, |
6628 | u32 tx_flags, __be16 protocol) | |
6629 | { | |
6630 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
6631 | union ixgbe_atr_hash_dword input = { .dword = 0 }; | |
6632 | union ixgbe_atr_hash_dword common = { .dword = 0 }; | |
6633 | union { | |
6634 | unsigned char *network; | |
6635 | struct iphdr *ipv4; | |
6636 | struct ipv6hdr *ipv6; | |
6637 | } hdr; | |
ee9e0f0b | 6638 | struct tcphdr *th; |
905e4a41 | 6639 | __be16 vlan_id; |
c4cf55e5 | 6640 | |
69830529 AD |
6641 | /* if ring doesn't have a interrupt vector, cannot perform ATR */ |
6642 | if (!q_vector) | |
6643 | return; | |
6644 | ||
6645 | /* do nothing if sampling is disabled */ | |
6646 | if (!ring->atr_sample_rate) | |
d3ead241 | 6647 | return; |
c4cf55e5 | 6648 | |
69830529 | 6649 | ring->atr_count++; |
c4cf55e5 | 6650 | |
69830529 AD |
6651 | /* snag network header to get L4 type and address */ |
6652 | hdr.network = skb_network_header(skb); | |
6653 | ||
6654 | /* Currently only IPv4/IPv6 with TCP is supported */ | |
6655 | if ((protocol != __constant_htons(ETH_P_IPV6) || | |
6656 | hdr.ipv6->nexthdr != IPPROTO_TCP) && | |
6657 | (protocol != __constant_htons(ETH_P_IP) || | |
6658 | hdr.ipv4->protocol != IPPROTO_TCP)) | |
6659 | return; | |
ee9e0f0b AD |
6660 | |
6661 | th = tcp_hdr(skb); | |
c4cf55e5 | 6662 | |
69830529 AD |
6663 | /* skip this packet since the socket is closing */ |
6664 | if (th->fin) | |
6665 | return; | |
6666 | ||
6667 | /* sample on all syn packets or once every atr sample count */ | |
6668 | if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) | |
6669 | return; | |
6670 | ||
6671 | /* reset sample count */ | |
6672 | ring->atr_count = 0; | |
6673 | ||
6674 | vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6675 | ||
6676 | /* | |
6677 | * src and dst are inverted, think how the receiver sees them | |
6678 | * | |
6679 | * The input is broken into two sections, a non-compressed section | |
6680 | * containing vm_pool, vlan_id, and flow_type. The rest of the data | |
6681 | * is XORed together and stored in the compressed dword. | |
6682 | */ | |
6683 | input.formatted.vlan_id = vlan_id; | |
6684 | ||
6685 | /* | |
6686 | * since src port and flex bytes occupy the same word XOR them together | |
6687 | * and write the value to source port portion of compressed dword | |
6688 | */ | |
6689 | if (vlan_id) | |
6690 | common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q); | |
6691 | else | |
6692 | common.port.src ^= th->dest ^ protocol; | |
6693 | common.port.dst ^= th->source; | |
6694 | ||
6695 | if (protocol == __constant_htons(ETH_P_IP)) { | |
6696 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; | |
6697 | common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; | |
6698 | } else { | |
6699 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; | |
6700 | common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ | |
6701 | hdr.ipv6->saddr.s6_addr32[1] ^ | |
6702 | hdr.ipv6->saddr.s6_addr32[2] ^ | |
6703 | hdr.ipv6->saddr.s6_addr32[3] ^ | |
6704 | hdr.ipv6->daddr.s6_addr32[0] ^ | |
6705 | hdr.ipv6->daddr.s6_addr32[1] ^ | |
6706 | hdr.ipv6->daddr.s6_addr32[2] ^ | |
6707 | hdr.ipv6->daddr.s6_addr32[3]; | |
6708 | } | |
c4cf55e5 PWJ |
6709 | |
6710 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
69830529 AD |
6711 | ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, |
6712 | input, common, ring->queue_index); | |
c4cf55e5 PWJ |
6713 | } |
6714 | ||
fc77dc3c | 6715 | static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size) |
e092be60 | 6716 | { |
fc77dc3c | 6717 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); |
e092be60 AV |
6718 | /* Herbert's original patch had: |
6719 | * smp_mb__after_netif_stop_queue(); | |
6720 | * but since that doesn't exist yet, just open code it. */ | |
6721 | smp_mb(); | |
6722 | ||
6723 | /* We need to check again in a case another CPU has just | |
6724 | * made room available. */ | |
6725 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
6726 | return -EBUSY; | |
6727 | ||
6728 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
fc77dc3c | 6729 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 6730 | ++tx_ring->tx_stats.restart_queue; |
e092be60 AV |
6731 | return 0; |
6732 | } | |
6733 | ||
fc77dc3c | 6734 | static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
6735 | { |
6736 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
6737 | return 0; | |
fc77dc3c | 6738 | return __ixgbe_maybe_stop_tx(tx_ring, size); |
e092be60 AV |
6739 | } |
6740 | ||
09a3b1f8 SH |
6741 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
6742 | { | |
6743 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5f715823 | 6744 | int txq = smp_processor_id(); |
56075a98 | 6745 | #ifdef IXGBE_FCOE |
5e09a105 HZ |
6746 | __be16 protocol; |
6747 | ||
6748 | protocol = vlan_get_protocol(skb); | |
6749 | ||
e5b64635 JF |
6750 | if (((protocol == htons(ETH_P_FCOE)) || |
6751 | (protocol == htons(ETH_P_FIP))) && | |
6752 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
6753 | txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1); | |
6754 | txq += adapter->ring_feature[RING_F_FCOE].mask; | |
6755 | return txq; | |
56075a98 JF |
6756 | } |
6757 | #endif | |
6758 | ||
fdd3d631 KK |
6759 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
6760 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
6761 | txq -= dev->real_num_tx_queues; | |
5f715823 | 6762 | return txq; |
fdd3d631 | 6763 | } |
c4cf55e5 | 6764 | |
09a3b1f8 SH |
6765 | return skb_tx_hash(dev, skb); |
6766 | } | |
6767 | ||
fc77dc3c | 6768 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
84418e3b AD |
6769 | struct ixgbe_adapter *adapter, |
6770 | struct ixgbe_ring *tx_ring) | |
9a799d71 | 6771 | { |
9a799d71 AK |
6772 | unsigned int first; |
6773 | unsigned int tx_flags = 0; | |
30eba97a | 6774 | u8 hdr_len = 0; |
5f715823 | 6775 | int tso; |
9a799d71 AK |
6776 | int count = 0; |
6777 | unsigned int f; | |
5e09a105 HZ |
6778 | __be16 protocol; |
6779 | ||
6780 | protocol = vlan_get_protocol(skb); | |
9f8cdf4f | 6781 | |
eab6d18d | 6782 | if (vlan_tx_tag_present(skb)) { |
9f8cdf4f | 6783 | tx_flags |= vlan_tx_tag_get(skb); |
2f90b865 AD |
6784 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
6785 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
e5b64635 | 6786 | tx_flags |= tx_ring->dcb_tc << 13; |
2f90b865 AD |
6787 | } |
6788 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
6789 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
33c66bd1 JF |
6790 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED && |
6791 | skb->priority != TC_PRIO_CONTROL) { | |
e5b64635 | 6792 | tx_flags |= tx_ring->dcb_tc << 13; |
2ea186ae JF |
6793 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; |
6794 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 6795 | } |
eacd73f7 | 6796 | |
09ad1cc0 | 6797 | #ifdef IXGBE_FCOE |
56075a98 JF |
6798 | /* for FCoE with DCB, we force the priority to what |
6799 | * was specified by the switch */ | |
6800 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED && | |
e5b64635 JF |
6801 | (protocol == htons(ETH_P_FCOE))) |
6802 | tx_flags |= IXGBE_TX_FLAGS_FCOE; | |
ca77cd59 RL |
6803 | #endif |
6804 | ||
eacd73f7 | 6805 | /* four things can cause us to need a context descriptor */ |
9f8cdf4f JB |
6806 | if (skb_is_gso(skb) || |
6807 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
eacd73f7 YZ |
6808 | (tx_flags & IXGBE_TX_FLAGS_VLAN) || |
6809 | (tx_flags & IXGBE_TX_FLAGS_FCOE)) | |
9a799d71 AK |
6810 | count++; |
6811 | ||
9f8cdf4f JB |
6812 | count += TXD_USE_COUNT(skb_headlen(skb)); |
6813 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
6814 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
6815 | ||
fc77dc3c | 6816 | if (ixgbe_maybe_stop_tx(tx_ring, count)) { |
5b7da515 | 6817 | tx_ring->tx_stats.tx_busy++; |
9a799d71 AK |
6818 | return NETDEV_TX_BUSY; |
6819 | } | |
9a799d71 | 6820 | |
9a799d71 | 6821 | first = tx_ring->next_to_use; |
eacd73f7 YZ |
6822 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
6823 | #ifdef IXGBE_FCOE | |
6824 | /* setup tx offload for FCoE */ | |
6825 | tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
6826 | if (tso < 0) { | |
6827 | dev_kfree_skb_any(skb); | |
6828 | return NETDEV_TX_OK; | |
6829 | } | |
6830 | if (tso) | |
6831 | tx_flags |= IXGBE_TX_FLAGS_FSO; | |
6832 | #endif /* IXGBE_FCOE */ | |
6833 | } else { | |
5e09a105 | 6834 | if (protocol == htons(ETH_P_IP)) |
eacd73f7 | 6835 | tx_flags |= IXGBE_TX_FLAGS_IPV4; |
5e09a105 HZ |
6836 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len, |
6837 | protocol); | |
eacd73f7 YZ |
6838 | if (tso < 0) { |
6839 | dev_kfree_skb_any(skb); | |
6840 | return NETDEV_TX_OK; | |
6841 | } | |
9a799d71 | 6842 | |
eacd73f7 YZ |
6843 | if (tso) |
6844 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
5e09a105 HZ |
6845 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags, |
6846 | protocol) && | |
eacd73f7 YZ |
6847 | (skb->ip_summed == CHECKSUM_PARTIAL)) |
6848 | tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
6849 | } | |
9a799d71 | 6850 | |
8ad494b0 | 6851 | count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len); |
44df32c5 | 6852 | if (count) { |
c4cf55e5 | 6853 | /* add the ATR filter if ATR is on */ |
69830529 AD |
6854 | if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) |
6855 | ixgbe_atr(tx_ring, skb, tx_flags, protocol); | |
84ea2591 | 6856 | ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len); |
fc77dc3c | 6857 | ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); |
9a799d71 | 6858 | |
44df32c5 AD |
6859 | } else { |
6860 | dev_kfree_skb_any(skb); | |
6861 | tx_ring->tx_buffer_info[first].time_stamp = 0; | |
6862 | tx_ring->next_to_use = first; | |
6863 | } | |
9a799d71 AK |
6864 | |
6865 | return NETDEV_TX_OK; | |
6866 | } | |
6867 | ||
84418e3b AD |
6868 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
6869 | { | |
6870 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6871 | struct ixgbe_ring *tx_ring; | |
6872 | ||
6873 | tx_ring = adapter->tx_ring[skb->queue_mapping]; | |
fc77dc3c | 6874 | return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); |
84418e3b AD |
6875 | } |
6876 | ||
9a799d71 AK |
6877 | /** |
6878 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
6879 | * @netdev: network interface device structure | |
6880 | * @p: pointer to an address structure | |
6881 | * | |
6882 | * Returns 0 on success, negative on failure | |
6883 | **/ | |
6884 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
6885 | { | |
6886 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 6887 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
6888 | struct sockaddr *addr = p; |
6889 | ||
6890 | if (!is_valid_ether_addr(addr->sa_data)) | |
6891 | return -EADDRNOTAVAIL; | |
6892 | ||
6893 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 6894 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 6895 | |
1cdd1ec8 GR |
6896 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
6897 | IXGBE_RAH_AV); | |
9a799d71 AK |
6898 | |
6899 | return 0; | |
6900 | } | |
6901 | ||
6b73e10d BH |
6902 | static int |
6903 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
6904 | { | |
6905 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6906 | struct ixgbe_hw *hw = &adapter->hw; | |
6907 | u16 value; | |
6908 | int rc; | |
6909 | ||
6910 | if (prtad != hw->phy.mdio.prtad) | |
6911 | return -EINVAL; | |
6912 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
6913 | if (!rc) | |
6914 | rc = value; | |
6915 | return rc; | |
6916 | } | |
6917 | ||
6918 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
6919 | u16 addr, u16 value) | |
6920 | { | |
6921 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6922 | struct ixgbe_hw *hw = &adapter->hw; | |
6923 | ||
6924 | if (prtad != hw->phy.mdio.prtad) | |
6925 | return -EINVAL; | |
6926 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
6927 | } | |
6928 | ||
6929 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
6930 | { | |
6931 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6932 | ||
6933 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
6934 | } | |
6935 | ||
0365e6e4 PW |
6936 | /** |
6937 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 6938 | * netdev->dev_addrs |
0365e6e4 PW |
6939 | * @netdev: network interface device structure |
6940 | * | |
6941 | * Returns non-zero on failure | |
6942 | **/ | |
6943 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
6944 | { | |
6945 | int err = 0; | |
6946 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6947 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6948 | ||
6949 | if (is_valid_ether_addr(mac->san_addr)) { | |
6950 | rtnl_lock(); | |
6951 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6952 | rtnl_unlock(); | |
6953 | } | |
6954 | return err; | |
6955 | } | |
6956 | ||
6957 | /** | |
6958 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 6959 | * netdev->dev_addrs |
0365e6e4 PW |
6960 | * @netdev: network interface device structure |
6961 | * | |
6962 | * Returns non-zero on failure | |
6963 | **/ | |
6964 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
6965 | { | |
6966 | int err = 0; | |
6967 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6968 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6969 | ||
6970 | if (is_valid_ether_addr(mac->san_addr)) { | |
6971 | rtnl_lock(); | |
6972 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6973 | rtnl_unlock(); | |
6974 | } | |
6975 | return err; | |
6976 | } | |
6977 | ||
9a799d71 AK |
6978 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6979 | /* | |
6980 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
6981 | * without having to re-enable interrupts. It's not called while | |
6982 | * the interrupt routine is executing. | |
6983 | */ | |
6984 | static void ixgbe_netpoll(struct net_device *netdev) | |
6985 | { | |
6986 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 6987 | int i; |
9a799d71 | 6988 | |
1a647bd2 AD |
6989 | /* if interface is down do nothing */ |
6990 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
6991 | return; | |
6992 | ||
9a799d71 | 6993 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 PWJ |
6994 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
6995 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
6996 | for (i = 0; i < num_q_vectors; i++) { | |
6997 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
6998 | ixgbe_msix_clean_many(0, q_vector); | |
6999 | } | |
7000 | } else { | |
7001 | ixgbe_intr(adapter->pdev->irq, netdev); | |
7002 | } | |
9a799d71 | 7003 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 AK |
7004 | } |
7005 | #endif | |
7006 | ||
de1036b1 ED |
7007 | static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, |
7008 | struct rtnl_link_stats64 *stats) | |
7009 | { | |
7010 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7011 | int i; | |
7012 | ||
1a51502b | 7013 | rcu_read_lock(); |
de1036b1 | 7014 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1a51502b | 7015 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); |
de1036b1 ED |
7016 | u64 bytes, packets; |
7017 | unsigned int start; | |
7018 | ||
1a51502b ED |
7019 | if (ring) { |
7020 | do { | |
7021 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
7022 | packets = ring->stats.packets; | |
7023 | bytes = ring->stats.bytes; | |
7024 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
7025 | stats->rx_packets += packets; | |
7026 | stats->rx_bytes += bytes; | |
7027 | } | |
de1036b1 | 7028 | } |
1ac9ad13 ED |
7029 | |
7030 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
7031 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); | |
7032 | u64 bytes, packets; | |
7033 | unsigned int start; | |
7034 | ||
7035 | if (ring) { | |
7036 | do { | |
7037 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
7038 | packets = ring->stats.packets; | |
7039 | bytes = ring->stats.bytes; | |
7040 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
7041 | stats->tx_packets += packets; | |
7042 | stats->tx_bytes += bytes; | |
7043 | } | |
7044 | } | |
1a51502b | 7045 | rcu_read_unlock(); |
de1036b1 ED |
7046 | /* following stats updated by ixgbe_watchdog_task() */ |
7047 | stats->multicast = netdev->stats.multicast; | |
7048 | stats->rx_errors = netdev->stats.rx_errors; | |
7049 | stats->rx_length_errors = netdev->stats.rx_length_errors; | |
7050 | stats->rx_crc_errors = netdev->stats.rx_crc_errors; | |
7051 | stats->rx_missed_errors = netdev->stats.rx_missed_errors; | |
7052 | return stats; | |
7053 | } | |
7054 | ||
7055 | ||
0edc3527 | 7056 | static const struct net_device_ops ixgbe_netdev_ops = { |
e8e9f696 | 7057 | .ndo_open = ixgbe_open, |
0edc3527 | 7058 | .ndo_stop = ixgbe_close, |
00829823 | 7059 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 7060 | .ndo_select_queue = ixgbe_select_queue, |
e90d400c | 7061 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
7062 | .ndo_set_multicast_list = ixgbe_set_rx_mode, |
7063 | .ndo_validate_addr = eth_validate_addr, | |
7064 | .ndo_set_mac_address = ixgbe_set_mac, | |
7065 | .ndo_change_mtu = ixgbe_change_mtu, | |
7066 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
0edc3527 SH |
7067 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, |
7068 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 7069 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
7070 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
7071 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
7072 | .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw, | |
7073 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, | |
de1036b1 | 7074 | .ndo_get_stats64 = ixgbe_get_stats64, |
24095aa3 JF |
7075 | #ifdef CONFIG_IXGBE_DCB |
7076 | .ndo_setup_tc = ixgbe_setup_tc, | |
7077 | #endif | |
0edc3527 SH |
7078 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7079 | .ndo_poll_controller = ixgbe_netpoll, | |
7080 | #endif | |
332d4a7d YZ |
7081 | #ifdef IXGBE_FCOE |
7082 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
68a683cf | 7083 | .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, |
332d4a7d | 7084 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, |
8450ff8c YZ |
7085 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
7086 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 7087 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
332d4a7d | 7088 | #endif /* IXGBE_FCOE */ |
0edc3527 SH |
7089 | }; |
7090 | ||
1cdd1ec8 GR |
7091 | static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter, |
7092 | const struct ixgbe_info *ii) | |
7093 | { | |
7094 | #ifdef CONFIG_PCI_IOV | |
7095 | struct ixgbe_hw *hw = &adapter->hw; | |
7096 | int err; | |
7097 | ||
3377eba7 | 7098 | if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs) |
1cdd1ec8 GR |
7099 | return; |
7100 | ||
7101 | /* The 82599 supports up to 64 VFs per physical function | |
7102 | * but this implementation limits allocation to 63 so that | |
7103 | * basic networking resources are still available to the | |
7104 | * physical function | |
7105 | */ | |
7106 | adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs; | |
7107 | adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED; | |
7108 | err = pci_enable_sriov(adapter->pdev, adapter->num_vfs); | |
7109 | if (err) { | |
396e799c | 7110 | e_err(probe, "Failed to enable PCI sriov: %d\n", err); |
1cdd1ec8 GR |
7111 | goto err_novfs; |
7112 | } | |
7113 | /* If call to enable VFs succeeded then allocate memory | |
7114 | * for per VF control structures. | |
7115 | */ | |
7116 | adapter->vfinfo = | |
7117 | kcalloc(adapter->num_vfs, | |
7118 | sizeof(struct vf_data_storage), GFP_KERNEL); | |
7119 | if (adapter->vfinfo) { | |
7120 | /* Now that we're sure SR-IOV is enabled | |
7121 | * and memory allocated set up the mailbox parameters | |
7122 | */ | |
7123 | ixgbe_init_mbx_params_pf(hw); | |
7124 | memcpy(&hw->mbx.ops, ii->mbx_ops, | |
7125 | sizeof(hw->mbx.ops)); | |
7126 | ||
7127 | /* Disable RSC when in SR-IOV mode */ | |
7128 | adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE | | |
7129 | IXGBE_FLAG2_RSC_ENABLED); | |
7130 | return; | |
7131 | } | |
7132 | ||
7133 | /* Oh oh */ | |
396e799c ET |
7134 | e_err(probe, "Unable to allocate memory for VF Data Storage - " |
7135 | "SRIOV disabled\n"); | |
1cdd1ec8 GR |
7136 | pci_disable_sriov(adapter->pdev); |
7137 | ||
7138 | err_novfs: | |
7139 | adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; | |
7140 | adapter->num_vfs = 0; | |
7141 | #endif /* CONFIG_PCI_IOV */ | |
7142 | } | |
7143 | ||
9a799d71 AK |
7144 | /** |
7145 | * ixgbe_probe - Device Initialization Routine | |
7146 | * @pdev: PCI device information struct | |
7147 | * @ent: entry in ixgbe_pci_tbl | |
7148 | * | |
7149 | * Returns 0 on success, negative on failure | |
7150 | * | |
7151 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
7152 | * The OS initialization, configuring of the adapter private structure, | |
7153 | * and a hardware reset occur. | |
7154 | **/ | |
7155 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
e8e9f696 | 7156 | const struct pci_device_id *ent) |
9a799d71 AK |
7157 | { |
7158 | struct net_device *netdev; | |
7159 | struct ixgbe_adapter *adapter = NULL; | |
7160 | struct ixgbe_hw *hw; | |
7161 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
7162 | static int cards_found; |
7163 | int i, err, pci_using_dac; | |
289700db | 7164 | u8 part_str[IXGBE_PBANUM_LENGTH]; |
c85a2618 | 7165 | unsigned int indices = num_possible_cpus(); |
eacd73f7 YZ |
7166 | #ifdef IXGBE_FCOE |
7167 | u16 device_caps; | |
7168 | #endif | |
289700db | 7169 | u32 eec; |
9a799d71 | 7170 | |
bded64a7 AG |
7171 | /* Catch broken hardware that put the wrong VF device ID in |
7172 | * the PCIe SR-IOV capability. | |
7173 | */ | |
7174 | if (pdev->is_virtfn) { | |
7175 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
7176 | pci_name(pdev), pdev->vendor, pdev->device); | |
7177 | return -EINVAL; | |
7178 | } | |
7179 | ||
9ce77666 | 7180 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
7181 | if (err) |
7182 | return err; | |
7183 | ||
1b507730 NN |
7184 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && |
7185 | !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
7186 | pci_using_dac = 1; |
7187 | } else { | |
1b507730 | 7188 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 7189 | if (err) { |
1b507730 NN |
7190 | err = dma_set_coherent_mask(&pdev->dev, |
7191 | DMA_BIT_MASK(32)); | |
9a799d71 | 7192 | if (err) { |
b8bc0421 DC |
7193 | dev_err(&pdev->dev, |
7194 | "No usable DMA configuration, aborting\n"); | |
9a799d71 AK |
7195 | goto err_dma; |
7196 | } | |
7197 | } | |
7198 | pci_using_dac = 0; | |
7199 | } | |
7200 | ||
9ce77666 | 7201 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7202 | IORESOURCE_MEM), ixgbe_driver_name); |
9a799d71 | 7203 | if (err) { |
b8bc0421 DC |
7204 | dev_err(&pdev->dev, |
7205 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
7206 | goto err_pci_reg; |
7207 | } | |
7208 | ||
19d5afd4 | 7209 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 7210 | |
9a799d71 | 7211 | pci_set_master(pdev); |
fb3b27bc | 7212 | pci_save_state(pdev); |
9a799d71 | 7213 | |
c85a2618 JF |
7214 | if (ii->mac == ixgbe_mac_82598EB) |
7215 | indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); | |
7216 | else | |
7217 | indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); | |
7218 | ||
e5b64635 | 7219 | #if defined(CONFIG_DCB) |
c85a2618 | 7220 | indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES); |
e5b64635 | 7221 | #elif defined(IXGBE_FCOE) |
c85a2618 JF |
7222 | indices += min_t(unsigned int, num_possible_cpus(), |
7223 | IXGBE_MAX_FCOE_INDICES); | |
7224 | #endif | |
c85a2618 | 7225 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
7226 | if (!netdev) { |
7227 | err = -ENOMEM; | |
7228 | goto err_alloc_etherdev; | |
7229 | } | |
7230 | ||
9a799d71 AK |
7231 | SET_NETDEV_DEV(netdev, &pdev->dev); |
7232 | ||
9a799d71 | 7233 | adapter = netdev_priv(netdev); |
c60fbb00 | 7234 | pci_set_drvdata(pdev, adapter); |
9a799d71 AK |
7235 | |
7236 | adapter->netdev = netdev; | |
7237 | adapter->pdev = pdev; | |
7238 | hw = &adapter->hw; | |
7239 | hw->back = adapter; | |
7240 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
7241 | ||
05857980 | 7242 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
e8e9f696 | 7243 | pci_resource_len(pdev, 0)); |
9a799d71 AK |
7244 | if (!hw->hw_addr) { |
7245 | err = -EIO; | |
7246 | goto err_ioremap; | |
7247 | } | |
7248 | ||
7249 | for (i = 1; i <= 5; i++) { | |
7250 | if (pci_resource_len(pdev, i) == 0) | |
7251 | continue; | |
7252 | } | |
7253 | ||
0edc3527 | 7254 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 7255 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 7256 | netdev->watchdog_timeo = 5 * HZ; |
9fe93afd | 7257 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); |
9a799d71 | 7258 | |
9a799d71 AK |
7259 | adapter->bd_number = cards_found; |
7260 | ||
9a799d71 AK |
7261 | /* Setup hw api */ |
7262 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 7263 | hw->mac.type = ii->mac; |
9a799d71 | 7264 | |
c44ade9e JB |
7265 | /* EEPROM */ |
7266 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
7267 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
7268 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
7269 | if (!(eec & (1 << 8))) | |
7270 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
7271 | ||
7272 | /* PHY */ | |
7273 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 7274 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
7275 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
7276 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
7277 | hw->phy.mdio.mmds = 0; | |
7278 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
7279 | hw->phy.mdio.dev = netdev; | |
7280 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
7281 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 DS |
7282 | |
7283 | /* set up this timer and work struct before calling get_invariants | |
7284 | * which might start the timer | |
7285 | */ | |
7286 | init_timer(&adapter->sfp_timer); | |
c061b18d | 7287 | adapter->sfp_timer.function = ixgbe_sfp_timer; |
c4900be0 DS |
7288 | adapter->sfp_timer.data = (unsigned long) adapter; |
7289 | ||
7290 | INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); | |
c44ade9e | 7291 | |
e8e26350 PW |
7292 | /* multispeed fiber has its own tasklet, called from GPI SDP1 context */ |
7293 | INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task); | |
7294 | ||
7295 | /* a new SFP+ module arrival, called from GPI SDP2 context */ | |
7296 | INIT_WORK(&adapter->sfp_config_module_task, | |
e8e9f696 | 7297 | ixgbe_sfp_config_module_task); |
e8e26350 | 7298 | |
8ca783ab | 7299 | ii->get_invariants(hw); |
9a799d71 AK |
7300 | |
7301 | /* setup the private structure */ | |
7302 | err = ixgbe_sw_init(adapter); | |
7303 | if (err) | |
7304 | goto err_sw_init; | |
7305 | ||
e86bff0e | 7306 | /* Make it possible the adapter to be woken up via WOL */ |
b93a2226 DS |
7307 | switch (adapter->hw.mac.type) { |
7308 | case ixgbe_mac_82599EB: | |
7309 | case ixgbe_mac_X540: | |
e86bff0e | 7310 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
b93a2226 DS |
7311 | break; |
7312 | default: | |
7313 | break; | |
7314 | } | |
e86bff0e | 7315 | |
bf069c97 DS |
7316 | /* |
7317 | * If there is a fan on this device and it has failed log the | |
7318 | * failure. | |
7319 | */ | |
7320 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
7321 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
7322 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 7323 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
7324 | } |
7325 | ||
c44ade9e | 7326 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 7327 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 7328 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 7329 | hw->phy.reset_if_overtemp = false; |
8ca783ab DS |
7330 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
7331 | hw->mac.type == ixgbe_mac_82598EB) { | |
7332 | /* | |
7333 | * Start a kernel thread to watch for a module to arrive. | |
7334 | * Only do this for 82598, since 82599 will generate | |
7335 | * interrupts on module arrival. | |
7336 | */ | |
7337 | set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
7338 | mod_timer(&adapter->sfp_timer, | |
7339 | round_jiffies(jiffies + (2 * HZ))); | |
7340 | err = 0; | |
7341 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
849c4542 ET |
7342 | e_dev_err("failed to initialize because an unsupported SFP+ " |
7343 | "module type was detected.\n"); | |
7344 | e_dev_err("Reload the driver after installing a supported " | |
7345 | "module.\n"); | |
04f165ef PW |
7346 | goto err_sw_init; |
7347 | } else if (err) { | |
849c4542 | 7348 | e_dev_err("HW Init failed: %d\n", err); |
c44ade9e JB |
7349 | goto err_sw_init; |
7350 | } | |
7351 | ||
1cdd1ec8 GR |
7352 | ixgbe_probe_vf(adapter, ii); |
7353 | ||
396e799c | 7354 | netdev->features = NETIF_F_SG | |
e8e9f696 JP |
7355 | NETIF_F_IP_CSUM | |
7356 | NETIF_F_HW_VLAN_TX | | |
7357 | NETIF_F_HW_VLAN_RX | | |
7358 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 7359 | |
e9990a9c | 7360 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 7361 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 7362 | netdev->features |= NETIF_F_TSO6; |
78b6f4ce | 7363 | netdev->features |= NETIF_F_GRO; |
ad31c402 | 7364 | |
58be7666 DS |
7365 | switch (adapter->hw.mac.type) { |
7366 | case ixgbe_mac_82599EB: | |
7367 | case ixgbe_mac_X540: | |
45a5ead0 | 7368 | netdev->features |= NETIF_F_SCTP_CSUM; |
58be7666 DS |
7369 | break; |
7370 | default: | |
7371 | break; | |
7372 | } | |
45a5ead0 | 7373 | |
ad31c402 JK |
7374 | netdev->vlan_features |= NETIF_F_TSO; |
7375 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 7376 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 7377 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
7378 | netdev->vlan_features |= NETIF_F_SG; |
7379 | ||
1cdd1ec8 GR |
7380 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7381 | adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED | | |
7382 | IXGBE_FLAG_DCB_ENABLED); | |
2f90b865 | 7383 | |
7a6b6f51 | 7384 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
7385 | netdev->dcbnl_ops = &dcbnl_ops; |
7386 | #endif | |
7387 | ||
eacd73f7 | 7388 | #ifdef IXGBE_FCOE |
0d551589 | 7389 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
7390 | if (hw->mac.ops.get_device_caps) { |
7391 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
7392 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
7393 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 YZ |
7394 | } |
7395 | } | |
5e09d7f6 YZ |
7396 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
7397 | netdev->vlan_features |= NETIF_F_FCOE_CRC; | |
7398 | netdev->vlan_features |= NETIF_F_FSO; | |
7399 | netdev->vlan_features |= NETIF_F_FCOE_MTU; | |
7400 | } | |
eacd73f7 | 7401 | #endif /* IXGBE_FCOE */ |
7b872a55 | 7402 | if (pci_using_dac) { |
9a799d71 | 7403 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
7404 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
7405 | } | |
9a799d71 | 7406 | |
0c19d6af | 7407 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
7408 | netdev->features |= NETIF_F_LRO; |
7409 | ||
9a799d71 | 7410 | /* make sure the EEPROM is good */ |
c44ade9e | 7411 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
849c4542 | 7412 | e_dev_err("The EEPROM Checksum Is Not Valid\n"); |
9a799d71 AK |
7413 | err = -EIO; |
7414 | goto err_eeprom; | |
7415 | } | |
7416 | ||
7417 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
7418 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
7419 | ||
c44ade9e | 7420 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
849c4542 | 7421 | e_dev_err("invalid MAC address\n"); |
9a799d71 AK |
7422 | err = -EIO; |
7423 | goto err_eeprom; | |
7424 | } | |
7425 | ||
c6ecf39a DS |
7426 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ |
7427 | if (hw->mac.ops.disable_tx_laser && | |
7428 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 7429 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a | 7430 | (hw->mac.type == ixgbe_mac_82599EB)))) |
61fac744 PW |
7431 | hw->mac.ops.disable_tx_laser(hw); |
7432 | ||
9a799d71 | 7433 | init_timer(&adapter->watchdog_timer); |
c061b18d | 7434 | adapter->watchdog_timer.function = ixgbe_watchdog; |
9a799d71 AK |
7435 | adapter->watchdog_timer.data = (unsigned long)adapter; |
7436 | ||
7437 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 7438 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 7439 | |
021230d4 AV |
7440 | err = ixgbe_init_interrupt_scheme(adapter); |
7441 | if (err) | |
7442 | goto err_sw_init; | |
9a799d71 | 7443 | |
e8e26350 | 7444 | switch (pdev->device) { |
0b077fea DS |
7445 | case IXGBE_DEV_ID_82599_SFP: |
7446 | /* Only this subdevice supports WOL */ | |
7447 | if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP) | |
7448 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | | |
7449 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); | |
7450 | break; | |
50d6c681 AD |
7451 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: |
7452 | /* All except this subdevice support WOL */ | |
0b077fea DS |
7453 | if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) |
7454 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | | |
7455 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); | |
7456 | break; | |
e8e26350 | 7457 | case IXGBE_DEV_ID_82599_KX4: |
495dce12 | 7458 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | |
e8e9f696 | 7459 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); |
e8e26350 PW |
7460 | break; |
7461 | default: | |
7462 | adapter->wol = 0; | |
7463 | break; | |
7464 | } | |
e8e26350 PW |
7465 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
7466 | ||
04f165ef PW |
7467 | /* pick up the PCI bus settings for reporting later */ |
7468 | hw->mac.ops.get_bus_info(hw); | |
7469 | ||
9a799d71 | 7470 | /* print bus type/speed/width info */ |
849c4542 | 7471 | e_dev_info("(PCI Express:%s:%s) %pM\n", |
e8e9f696 JP |
7472 | (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" : |
7473 | hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" : | |
7474 | "Unknown"), | |
7475 | (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" : | |
7476 | hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" : | |
7477 | hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" : | |
7478 | "Unknown"), | |
7479 | netdev->dev_addr); | |
289700db DS |
7480 | |
7481 | err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH); | |
7482 | if (err) | |
9fe93afd | 7483 | strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH); |
e8e26350 | 7484 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
289700db | 7485 | e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", |
849c4542 | 7486 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, |
289700db | 7487 | part_str); |
e8e26350 | 7488 | else |
289700db DS |
7489 | e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", |
7490 | hw->mac.type, hw->phy.type, part_str); | |
9a799d71 | 7491 | |
e8e26350 | 7492 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
849c4542 ET |
7493 | e_dev_warn("PCI-Express bandwidth available for this card is " |
7494 | "not sufficient for optimal performance.\n"); | |
7495 | e_dev_warn("For optimal performance a x8 PCI-Express slot " | |
7496 | "is required.\n"); | |
0c254d86 AK |
7497 | } |
7498 | ||
34b0368c PWJ |
7499 | /* save off EEPROM version number */ |
7500 | hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version); | |
7501 | ||
9a799d71 | 7502 | /* reset the hardware with the new settings */ |
794caeb2 | 7503 | err = hw->mac.ops.start_hw(hw); |
c44ade9e | 7504 | |
794caeb2 PWJ |
7505 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
7506 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
7507 | e_dev_warn("This device is a pre-production adapter/LOM. " |
7508 | "Please be aware there may be issues associated " | |
7509 | "with your hardware. If you are experiencing " | |
7510 | "problems please contact your Intel or hardware " | |
7511 | "representative who provided you with this " | |
7512 | "hardware.\n"); | |
794caeb2 | 7513 | } |
9a799d71 AK |
7514 | strcpy(netdev->name, "eth%d"); |
7515 | err = register_netdev(netdev); | |
7516 | if (err) | |
7517 | goto err_register; | |
7518 | ||
54386467 JB |
7519 | /* carrier off reporting is important to ethtool even BEFORE open */ |
7520 | netif_carrier_off(netdev); | |
7521 | ||
c4cf55e5 PWJ |
7522 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
7523 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
7524 | INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task); | |
7525 | ||
119fc60a | 7526 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
e8e9f696 JP |
7527 | INIT_WORK(&adapter->check_overtemp_task, |
7528 | ixgbe_check_overtemp_task); | |
5dd2d332 | 7529 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 7530 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 7531 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
7532 | ixgbe_setup_dca(adapter); |
7533 | } | |
7534 | #endif | |
1cdd1ec8 | 7535 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
396e799c | 7536 | e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); |
1cdd1ec8 GR |
7537 | for (i = 0; i < adapter->num_vfs; i++) |
7538 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
7539 | } | |
7540 | ||
0365e6e4 PW |
7541 | /* add san mac addr to netdev */ |
7542 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 | 7543 | |
849c4542 | 7544 | e_dev_info("Intel(R) 10 Gigabit Network Connection\n"); |
9a799d71 AK |
7545 | cards_found++; |
7546 | return 0; | |
7547 | ||
7548 | err_register: | |
5eba3699 | 7549 | ixgbe_release_hw_control(adapter); |
7a921c93 | 7550 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 AK |
7551 | err_sw_init: |
7552 | err_eeprom: | |
1cdd1ec8 GR |
7553 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7554 | ixgbe_disable_sriov(adapter); | |
c4900be0 DS |
7555 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
7556 | del_timer_sync(&adapter->sfp_timer); | |
7557 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
7558 | cancel_work_sync(&adapter->multispeed_fiber_task); |
7559 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
7560 | iounmap(hw->hw_addr); |
7561 | err_ioremap: | |
7562 | free_netdev(netdev); | |
7563 | err_alloc_etherdev: | |
e8e9f696 JP |
7564 | pci_release_selected_regions(pdev, |
7565 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9a799d71 AK |
7566 | err_pci_reg: |
7567 | err_dma: | |
7568 | pci_disable_device(pdev); | |
7569 | return err; | |
7570 | } | |
7571 | ||
7572 | /** | |
7573 | * ixgbe_remove - Device Removal Routine | |
7574 | * @pdev: PCI device information struct | |
7575 | * | |
7576 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
7577 | * that it should release a PCI device. The could be caused by a | |
7578 | * Hot-Plug event, or because the driver is going to be removed from | |
7579 | * memory. | |
7580 | **/ | |
7581 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
7582 | { | |
c60fbb00 AD |
7583 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7584 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
7585 | |
7586 | set_bit(__IXGBE_DOWN, &adapter->state); | |
760141a5 TH |
7587 | |
7588 | /* | |
7589 | * The timers may be rescheduled, so explicitly disable them | |
7590 | * from being rescheduled. | |
c4900be0 DS |
7591 | */ |
7592 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
9a799d71 | 7593 | del_timer_sync(&adapter->watchdog_timer); |
c4900be0 | 7594 | del_timer_sync(&adapter->sfp_timer); |
760141a5 | 7595 | |
c4900be0 DS |
7596 | cancel_work_sync(&adapter->watchdog_task); |
7597 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
7598 | cancel_work_sync(&adapter->multispeed_fiber_task); |
7599 | cancel_work_sync(&adapter->sfp_config_module_task); | |
c4cf55e5 PWJ |
7600 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
7601 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
7602 | cancel_work_sync(&adapter->fdir_reinit_task); | |
760141a5 TH |
7603 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
7604 | cancel_work_sync(&adapter->check_overtemp_task); | |
9a799d71 | 7605 | |
5dd2d332 | 7606 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7607 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
7608 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
7609 | dca_remove_requester(&pdev->dev); | |
7610 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
7611 | } | |
7612 | ||
7613 | #endif | |
332d4a7d YZ |
7614 | #ifdef IXGBE_FCOE |
7615 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
7616 | ixgbe_cleanup_fcoe(adapter); | |
7617 | ||
7618 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
7619 | |
7620 | /* remove the added san mac */ | |
7621 | ixgbe_del_sanmac_netdev(netdev); | |
7622 | ||
c4900be0 DS |
7623 | if (netdev->reg_state == NETREG_REGISTERED) |
7624 | unregister_netdev(netdev); | |
9a799d71 | 7625 | |
1cdd1ec8 GR |
7626 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7627 | ixgbe_disable_sriov(adapter); | |
7628 | ||
7a921c93 | 7629 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 7630 | |
021230d4 | 7631 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
7632 | |
7633 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 7634 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7635 | IORESOURCE_MEM)); |
9a799d71 | 7636 | |
849c4542 | 7637 | e_dev_info("complete\n"); |
021230d4 | 7638 | |
9a799d71 AK |
7639 | free_netdev(netdev); |
7640 | ||
19d5afd4 | 7641 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 7642 | |
9a799d71 AK |
7643 | pci_disable_device(pdev); |
7644 | } | |
7645 | ||
7646 | /** | |
7647 | * ixgbe_io_error_detected - called when PCI error is detected | |
7648 | * @pdev: Pointer to PCI device | |
7649 | * @state: The current pci connection state | |
7650 | * | |
7651 | * This function is called after a PCI bus error affecting | |
7652 | * this device has been detected. | |
7653 | */ | |
7654 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
e8e9f696 | 7655 | pci_channel_state_t state) |
9a799d71 | 7656 | { |
c60fbb00 AD |
7657 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7658 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
7659 | |
7660 | netif_device_detach(netdev); | |
7661 | ||
3044b8d1 BL |
7662 | if (state == pci_channel_io_perm_failure) |
7663 | return PCI_ERS_RESULT_DISCONNECT; | |
7664 | ||
9a799d71 AK |
7665 | if (netif_running(netdev)) |
7666 | ixgbe_down(adapter); | |
7667 | pci_disable_device(pdev); | |
7668 | ||
b4617240 | 7669 | /* Request a slot reset. */ |
9a799d71 AK |
7670 | return PCI_ERS_RESULT_NEED_RESET; |
7671 | } | |
7672 | ||
7673 | /** | |
7674 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
7675 | * @pdev: Pointer to PCI device | |
7676 | * | |
7677 | * Restart the card from scratch, as if from a cold-boot. | |
7678 | */ | |
7679 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
7680 | { | |
c60fbb00 | 7681 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6fabd715 PWJ |
7682 | pci_ers_result_t result; |
7683 | int err; | |
9a799d71 | 7684 | |
9ce77666 | 7685 | if (pci_enable_device_mem(pdev)) { |
396e799c | 7686 | e_err(probe, "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
7687 | result = PCI_ERS_RESULT_DISCONNECT; |
7688 | } else { | |
7689 | pci_set_master(pdev); | |
7690 | pci_restore_state(pdev); | |
c0e1f68b | 7691 | pci_save_state(pdev); |
9a799d71 | 7692 | |
dd4d8ca6 | 7693 | pci_wake_from_d3(pdev, false); |
9a799d71 | 7694 | |
6fabd715 | 7695 | ixgbe_reset(adapter); |
88512539 | 7696 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
7697 | result = PCI_ERS_RESULT_RECOVERED; |
7698 | } | |
7699 | ||
7700 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
7701 | if (err) { | |
849c4542 ET |
7702 | e_dev_err("pci_cleanup_aer_uncorrect_error_status " |
7703 | "failed 0x%0x\n", err); | |
6fabd715 PWJ |
7704 | /* non-fatal, continue */ |
7705 | } | |
9a799d71 | 7706 | |
6fabd715 | 7707 | return result; |
9a799d71 AK |
7708 | } |
7709 | ||
7710 | /** | |
7711 | * ixgbe_io_resume - called when traffic can start flowing again. | |
7712 | * @pdev: Pointer to PCI device | |
7713 | * | |
7714 | * This callback is called when the error recovery driver tells us that | |
7715 | * its OK to resume normal operation. | |
7716 | */ | |
7717 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
7718 | { | |
c60fbb00 AD |
7719 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7720 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
7721 | |
7722 | if (netif_running(netdev)) { | |
7723 | if (ixgbe_up(adapter)) { | |
396e799c | 7724 | e_info(probe, "ixgbe_up failed after reset\n"); |
9a799d71 AK |
7725 | return; |
7726 | } | |
7727 | } | |
7728 | ||
7729 | netif_device_attach(netdev); | |
9a799d71 AK |
7730 | } |
7731 | ||
7732 | static struct pci_error_handlers ixgbe_err_handler = { | |
7733 | .error_detected = ixgbe_io_error_detected, | |
7734 | .slot_reset = ixgbe_io_slot_reset, | |
7735 | .resume = ixgbe_io_resume, | |
7736 | }; | |
7737 | ||
7738 | static struct pci_driver ixgbe_driver = { | |
7739 | .name = ixgbe_driver_name, | |
7740 | .id_table = ixgbe_pci_tbl, | |
7741 | .probe = ixgbe_probe, | |
7742 | .remove = __devexit_p(ixgbe_remove), | |
7743 | #ifdef CONFIG_PM | |
7744 | .suspend = ixgbe_suspend, | |
7745 | .resume = ixgbe_resume, | |
7746 | #endif | |
7747 | .shutdown = ixgbe_shutdown, | |
7748 | .err_handler = &ixgbe_err_handler | |
7749 | }; | |
7750 | ||
7751 | /** | |
7752 | * ixgbe_init_module - Driver Registration Routine | |
7753 | * | |
7754 | * ixgbe_init_module is the first routine called when the driver is | |
7755 | * loaded. All it does is register with the PCI subsystem. | |
7756 | **/ | |
7757 | static int __init ixgbe_init_module(void) | |
7758 | { | |
7759 | int ret; | |
c7689578 | 7760 | pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); |
849c4542 | 7761 | pr_info("%s\n", ixgbe_copyright); |
9a799d71 | 7762 | |
5dd2d332 | 7763 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7764 | dca_register_notify(&dca_notifier); |
bd0362dd | 7765 | #endif |
5dd2d332 | 7766 | |
9a799d71 AK |
7767 | ret = pci_register_driver(&ixgbe_driver); |
7768 | return ret; | |
7769 | } | |
b4617240 | 7770 | |
9a799d71 AK |
7771 | module_init(ixgbe_init_module); |
7772 | ||
7773 | /** | |
7774 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
7775 | * | |
7776 | * ixgbe_exit_module is called just before the driver is removed | |
7777 | * from memory. | |
7778 | **/ | |
7779 | static void __exit ixgbe_exit_module(void) | |
7780 | { | |
5dd2d332 | 7781 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7782 | dca_unregister_notify(&dca_notifier); |
7783 | #endif | |
9a799d71 | 7784 | pci_unregister_driver(&ixgbe_driver); |
1a51502b | 7785 | rcu_barrier(); /* Wait for completion of call_rcu()'s */ |
9a799d71 | 7786 | } |
bd0362dd | 7787 | |
5dd2d332 | 7788 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7789 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
e8e9f696 | 7790 | void *p) |
bd0362dd JC |
7791 | { |
7792 | int ret_val; | |
7793 | ||
7794 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
e8e9f696 | 7795 | __ixgbe_notify_dca); |
bd0362dd JC |
7796 | |
7797 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
7798 | } | |
b453368d | 7799 | |
5dd2d332 | 7800 | #endif /* CONFIG_IXGBE_DCA */ |
849c4542 | 7801 | |
9a799d71 AK |
7802 | module_exit(ixgbe_exit_module); |
7803 | ||
7804 | /* ixgbe_main.c */ |