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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
3efac5a0 | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
37 | #include <linux/ipv6.h> | |
38 | #include <net/checksum.h> | |
39 | #include <net/ip6_checksum.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/if_vlan.h> | |
eacd73f7 | 42 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
43 | |
44 | #include "ixgbe.h" | |
45 | #include "ixgbe_common.h" | |
46 | ||
47 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 48 | static const char ixgbe_driver_string[] = |
b4617240 | 49 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
9a799d71 | 50 | |
04193058 | 51 | #define DRV_VERSION "2.0.16-k2" |
9c8eb720 | 52 | const char ixgbe_driver_version[] = DRV_VERSION; |
3efac5a0 | 53 | static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation."; |
9a799d71 AK |
54 | |
55 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 56 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 57 | [board_82599] = &ixgbe_82599_info, |
9a799d71 AK |
58 | }; |
59 | ||
60 | /* ixgbe_pci_tbl - PCI Device ID Table | |
61 | * | |
62 | * Wildcard entries (PCI_ANY_ID) should come last | |
63 | * Last entry must be all 0s | |
64 | * | |
65 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
66 | * Class, Class Mask, private data (not used) } | |
67 | */ | |
68 | static struct pci_device_id ixgbe_pci_tbl[] = { | |
1e336d0f DS |
69 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), |
70 | board_82598 }, | |
9a799d71 | 71 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), |
3957d63d | 72 | board_82598 }, |
9a799d71 | 73 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 74 | board_82598 }, |
0befdb3e JB |
75 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
76 | board_82598 }, | |
9a799d71 | 77 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 78 | board_82598 }, |
8d792cd9 JB |
79 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
80 | board_82598 }, | |
c4900be0 DS |
81 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
82 | board_82598 }, | |
83 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
84 | board_82598 }, | |
b95f5fcb JB |
85 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
86 | board_82598 }, | |
c4900be0 DS |
87 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
88 | board_82598 }, | |
2f21bdd3 DS |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), |
90 | board_82598 }, | |
e8e26350 PW |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), |
92 | board_82599 }, | |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), | |
94 | board_82599 }, | |
9a799d71 AK |
95 | |
96 | /* required last entry */ | |
97 | {0, } | |
98 | }; | |
99 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
100 | ||
5dd2d332 | 101 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 102 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
b4617240 | 103 | void *p); |
bd0362dd JC |
104 | static struct notifier_block dca_notifier = { |
105 | .notifier_call = ixgbe_notify_dca, | |
106 | .next = NULL, | |
107 | .priority = 0 | |
108 | }; | |
109 | #endif | |
110 | ||
9a799d71 AK |
111 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
112 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
113 | MODULE_LICENSE("GPL"); | |
114 | MODULE_VERSION(DRV_VERSION); | |
115 | ||
116 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
117 | ||
5eba3699 AV |
118 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
119 | { | |
120 | u32 ctrl_ext; | |
121 | ||
122 | /* Let firmware take over control of h/w */ | |
123 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
124 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 125 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
126 | } |
127 | ||
128 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
129 | { | |
130 | u32 ctrl_ext; | |
131 | ||
132 | /* Let firmware know the driver has taken over */ | |
133 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
134 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 135 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 136 | } |
9a799d71 | 137 | |
e8e26350 PW |
138 | /* |
139 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
140 | * @adapter: pointer to adapter struct | |
141 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
142 | * @queue: queue to map the corresponding interrupt to | |
143 | * @msix_vector: the vector to map to the corresponding queue | |
144 | * | |
145 | */ | |
146 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
147 | u8 queue, u8 msix_vector) | |
9a799d71 AK |
148 | { |
149 | u32 ivar, index; | |
e8e26350 PW |
150 | struct ixgbe_hw *hw = &adapter->hw; |
151 | switch (hw->mac.type) { | |
152 | case ixgbe_mac_82598EB: | |
153 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
154 | if (direction == -1) | |
155 | direction = 0; | |
156 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
157 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
158 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
159 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
160 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
161 | break; | |
162 | case ixgbe_mac_82599EB: | |
163 | if (direction == -1) { | |
164 | /* other causes */ | |
165 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
166 | index = ((queue & 1) * 8); | |
167 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
168 | ivar &= ~(0xFF << index); | |
169 | ivar |= (msix_vector << index); | |
170 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
171 | break; | |
172 | } else { | |
173 | /* tx or rx causes */ | |
174 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
175 | index = ((16 * (queue & 1)) + (8 * direction)); | |
176 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
177 | ivar &= ~(0xFF << index); | |
178 | ivar |= (msix_vector << index); | |
179 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
180 | break; | |
181 | } | |
182 | default: | |
183 | break; | |
184 | } | |
9a799d71 AK |
185 | } |
186 | ||
187 | static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter, | |
b4617240 PW |
188 | struct ixgbe_tx_buffer |
189 | *tx_buffer_info) | |
9a799d71 | 190 | { |
44df32c5 | 191 | tx_buffer_info->dma = 0; |
9a799d71 | 192 | if (tx_buffer_info->skb) { |
44df32c5 AD |
193 | skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb, |
194 | DMA_TO_DEVICE); | |
9a799d71 AK |
195 | dev_kfree_skb_any(tx_buffer_info->skb); |
196 | tx_buffer_info->skb = NULL; | |
197 | } | |
44df32c5 | 198 | tx_buffer_info->time_stamp = 0; |
9a799d71 AK |
199 | /* tx_buffer_info must be completely set up in the transmit path */ |
200 | } | |
201 | ||
202 | static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter, | |
b4617240 PW |
203 | struct ixgbe_ring *tx_ring, |
204 | unsigned int eop) | |
9a799d71 | 205 | { |
e01c31a5 | 206 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 207 | |
9a799d71 | 208 | /* Detect a transmit hang in hardware, this serializes the |
e01c31a5 | 209 | * check with the clearing of time_stamp and movement of eop */ |
9a799d71 | 210 | adapter->detect_tx_hung = false; |
44df32c5 | 211 | if (tx_ring->tx_buffer_info[eop].time_stamp && |
9a799d71 AK |
212 | time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) && |
213 | !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) { | |
214 | /* detected Tx unit hang */ | |
e01c31a5 JB |
215 | union ixgbe_adv_tx_desc *tx_desc; |
216 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
9a799d71 | 217 | DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n" |
e01c31a5 JB |
218 | " Tx Queue <%d>\n" |
219 | " TDH, TDT <%x>, <%x>\n" | |
9a799d71 AK |
220 | " next_to_use <%x>\n" |
221 | " next_to_clean <%x>\n" | |
222 | "tx_buffer_info[next_to_clean]\n" | |
223 | " time_stamp <%lx>\n" | |
e01c31a5 JB |
224 | " jiffies <%lx>\n", |
225 | tx_ring->queue_index, | |
44df32c5 AD |
226 | IXGBE_READ_REG(hw, tx_ring->head), |
227 | IXGBE_READ_REG(hw, tx_ring->tail), | |
e01c31a5 JB |
228 | tx_ring->next_to_use, eop, |
229 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
9a799d71 AK |
230 | return true; |
231 | } | |
232 | ||
233 | return false; | |
234 | } | |
235 | ||
b4617240 PW |
236 | #define IXGBE_MAX_TXD_PWR 14 |
237 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
238 | |
239 | /* Tx Descriptors needed, worst case */ | |
240 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
241 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
242 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 243 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 244 | |
e01c31a5 JB |
245 | static void ixgbe_tx_timeout(struct net_device *netdev); |
246 | ||
9a799d71 AK |
247 | /** |
248 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
249 | * @adapter: board private structure | |
e01c31a5 | 250 | * @tx_ring: tx ring to clean |
9a1a69ad JB |
251 | * |
252 | * returns true if transmit work is done | |
9a799d71 AK |
253 | **/ |
254 | static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter, | |
e01c31a5 | 255 | struct ixgbe_ring *tx_ring) |
9a799d71 | 256 | { |
e01c31a5 | 257 | struct net_device *netdev = adapter->netdev; |
12207e49 PWJ |
258 | union ixgbe_adv_tx_desc *tx_desc, *eop_desc; |
259 | struct ixgbe_tx_buffer *tx_buffer_info; | |
260 | unsigned int i, eop, count = 0; | |
e01c31a5 | 261 | unsigned int total_bytes = 0, total_packets = 0; |
9a799d71 AK |
262 | |
263 | i = tx_ring->next_to_clean; | |
12207e49 PWJ |
264 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
265 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
266 | ||
267 | while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && | |
9a1a69ad | 268 | (count < tx_ring->work_limit)) { |
12207e49 PWJ |
269 | bool cleaned = false; |
270 | for ( ; !cleaned; count++) { | |
271 | struct sk_buff *skb; | |
9a799d71 AK |
272 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); |
273 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
12207e49 | 274 | cleaned = (i == eop); |
e01c31a5 | 275 | skb = tx_buffer_info->skb; |
9a799d71 | 276 | |
12207e49 | 277 | if (cleaned && skb) { |
e092be60 | 278 | unsigned int segs, bytecount; |
e01c31a5 JB |
279 | |
280 | /* gso_segs is currently only valid for tcp */ | |
e092be60 AV |
281 | segs = skb_shinfo(skb)->gso_segs ?: 1; |
282 | /* multiply data chunks by size of headers */ | |
283 | bytecount = ((segs - 1) * skb_headlen(skb)) + | |
e01c31a5 JB |
284 | skb->len; |
285 | total_packets += segs; | |
286 | total_bytes += bytecount; | |
e092be60 | 287 | } |
e01c31a5 | 288 | |
9a799d71 | 289 | ixgbe_unmap_and_free_tx_resource(adapter, |
e01c31a5 | 290 | tx_buffer_info); |
9a799d71 | 291 | |
12207e49 PWJ |
292 | tx_desc->wb.status = 0; |
293 | ||
9a799d71 AK |
294 | i++; |
295 | if (i == tx_ring->count) | |
296 | i = 0; | |
e01c31a5 | 297 | } |
12207e49 PWJ |
298 | |
299 | eop = tx_ring->tx_buffer_info[i].next_to_watch; | |
300 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
301 | } | |
302 | ||
9a799d71 AK |
303 | tx_ring->next_to_clean = i; |
304 | ||
e092be60 | 305 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
e01c31a5 JB |
306 | if (unlikely(count && netif_carrier_ok(netdev) && |
307 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
e092be60 AV |
308 | /* Make sure that anybody stopping the queue after this |
309 | * sees the new next_to_clean. | |
310 | */ | |
311 | smp_mb(); | |
30eba97a AV |
312 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
313 | !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
314 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
e01c31a5 | 315 | ++adapter->restart_queue; |
30eba97a | 316 | } |
e092be60 | 317 | } |
9a799d71 | 318 | |
e01c31a5 JB |
319 | if (adapter->detect_tx_hung) { |
320 | if (ixgbe_check_tx_hang(adapter, tx_ring, i)) { | |
321 | /* schedule immediate reset if we believe we hung */ | |
322 | DPRINTK(PROBE, INFO, | |
323 | "tx hang %d detected, resetting adapter\n", | |
324 | adapter->tx_timeout_count + 1); | |
325 | ixgbe_tx_timeout(adapter->netdev); | |
326 | } | |
327 | } | |
9a799d71 | 328 | |
e01c31a5 | 329 | /* re-arm the interrupt */ |
835462fc NS |
330 | if (count >= tx_ring->work_limit) { |
331 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
332 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, | |
333 | tx_ring->v_idx); | |
334 | else if (tx_ring->v_idx & 0xFFFFFFFF) | |
335 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), | |
336 | tx_ring->v_idx); | |
337 | else | |
338 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), | |
339 | (tx_ring->v_idx >> 32)); | |
340 | } | |
341 | ||
9a799d71 | 342 | |
e01c31a5 JB |
343 | tx_ring->total_bytes += total_bytes; |
344 | tx_ring->total_packets += total_packets; | |
e01c31a5 | 345 | tx_ring->stats.packets += total_packets; |
12207e49 | 346 | tx_ring->stats.bytes += total_bytes; |
e01c31a5 JB |
347 | adapter->net_stats.tx_bytes += total_bytes; |
348 | adapter->net_stats.tx_packets += total_packets; | |
9a1a69ad | 349 | return (count < tx_ring->work_limit); |
9a799d71 AK |
350 | } |
351 | ||
5dd2d332 | 352 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 353 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
b4617240 | 354 | struct ixgbe_ring *rx_ring) |
bd0362dd JC |
355 | { |
356 | u32 rxctrl; | |
357 | int cpu = get_cpu(); | |
3a581073 | 358 | int q = rx_ring - adapter->rx_ring; |
bd0362dd | 359 | |
3a581073 | 360 | if (rx_ring->cpu != cpu) { |
bd0362dd | 361 | rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q)); |
e8e26350 PW |
362 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
363 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
364 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
365 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
366 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; | |
367 | rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
368 | IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); | |
369 | } | |
bd0362dd JC |
370 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
371 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
15005a32 DS |
372 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); |
373 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | | |
e8e26350 | 374 | IXGBE_DCA_RXCTRL_DESC_HSRO_EN); |
bd0362dd | 375 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); |
3a581073 | 376 | rx_ring->cpu = cpu; |
bd0362dd JC |
377 | } |
378 | put_cpu(); | |
379 | } | |
380 | ||
381 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
b4617240 | 382 | struct ixgbe_ring *tx_ring) |
bd0362dd JC |
383 | { |
384 | u32 txctrl; | |
385 | int cpu = get_cpu(); | |
3a581073 | 386 | int q = tx_ring - adapter->tx_ring; |
bd0362dd | 387 | |
3a581073 | 388 | if (tx_ring->cpu != cpu) { |
bd0362dd | 389 | txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q)); |
e8e26350 PW |
390 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
391 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; | |
392 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
393 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
394 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; | |
395 | txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
396 | IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); | |
397 | } | |
bd0362dd JC |
398 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
399 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl); | |
3a581073 | 400 | tx_ring->cpu = cpu; |
bd0362dd JC |
401 | } |
402 | put_cpu(); | |
403 | } | |
404 | ||
405 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
406 | { | |
407 | int i; | |
408 | ||
409 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
410 | return; | |
411 | ||
412 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
413 | adapter->tx_ring[i].cpu = -1; | |
414 | ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]); | |
415 | } | |
416 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
417 | adapter->rx_ring[i].cpu = -1; | |
418 | ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]); | |
419 | } | |
420 | } | |
421 | ||
422 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
423 | { | |
424 | struct net_device *netdev = dev_get_drvdata(dev); | |
425 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
426 | unsigned long event = *(unsigned long *)data; | |
427 | ||
428 | switch (event) { | |
429 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
430 | /* if we're already enabled, don't do it again */ |
431 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
432 | break; | |
bd0362dd JC |
433 | /* Always use CB2 mode, difference is masked |
434 | * in the CB driver. */ | |
435 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
652f093f | 436 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 437 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
438 | ixgbe_setup_dca(adapter); |
439 | break; | |
440 | } | |
441 | /* Fall Through since DCA is disabled. */ | |
442 | case DCA_PROVIDER_REMOVE: | |
443 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
444 | dca_remove_requester(dev); | |
445 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
446 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
447 | } | |
448 | break; | |
449 | } | |
450 | ||
652f093f | 451 | return 0; |
bd0362dd JC |
452 | } |
453 | ||
5dd2d332 | 454 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
455 | /** |
456 | * ixgbe_receive_skb - Send a completed packet up the stack | |
457 | * @adapter: board private structure | |
458 | * @skb: packet to send up | |
177db6ff MC |
459 | * @status: hardware indication of status of receive |
460 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
461 | * @rx_desc: rx descriptor | |
9a799d71 | 462 | **/ |
78b6f4ce | 463 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
b4617240 | 464 | struct sk_buff *skb, u8 status, |
fdaff1ce | 465 | struct ixgbe_ring *ring, |
177db6ff | 466 | union ixgbe_adv_rx_desc *rx_desc) |
9a799d71 | 467 | { |
78b6f4ce HX |
468 | struct ixgbe_adapter *adapter = q_vector->adapter; |
469 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
470 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
471 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 472 | |
fdaff1ce | 473 | skb_record_rx_queue(skb, ring->queue_index); |
182ff8df | 474 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { |
2f90b865 | 475 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
78b6f4ce | 476 | vlan_gro_receive(napi, adapter->vlgrp, tag, skb); |
9a799d71 | 477 | else |
78b6f4ce | 478 | napi_gro_receive(napi, skb); |
177db6ff | 479 | } else { |
182ff8df AD |
480 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
481 | vlan_hwaccel_rx(skb, adapter->vlgrp, tag); | |
482 | else | |
483 | netif_rx(skb); | |
9a799d71 AK |
484 | } |
485 | } | |
486 | ||
e59bd25d AV |
487 | /** |
488 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
489 | * @adapter: address of board private structure | |
490 | * @status_err: hardware indication of status of receive | |
491 | * @skb: skb currently being received and modified | |
492 | **/ | |
9a799d71 | 493 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
712744be | 494 | u32 status_err, struct sk_buff *skb) |
9a799d71 AK |
495 | { |
496 | skb->ip_summed = CHECKSUM_NONE; | |
497 | ||
712744be JB |
498 | /* Rx csum disabled */ |
499 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 500 | return; |
e59bd25d AV |
501 | |
502 | /* if IP and error */ | |
503 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
504 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
505 | adapter->hw_csum_rx_error++; |
506 | return; | |
507 | } | |
e59bd25d AV |
508 | |
509 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
510 | return; | |
511 | ||
512 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
513 | adapter->hw_csum_rx_error++; | |
514 | return; | |
515 | } | |
516 | ||
9a799d71 | 517 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 518 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
519 | adapter->hw_csum_rx_good++; |
520 | } | |
521 | ||
e8e26350 PW |
522 | static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw, |
523 | struct ixgbe_ring *rx_ring, u32 val) | |
524 | { | |
525 | /* | |
526 | * Force memory writes to complete before letting h/w | |
527 | * know there are new descriptors to fetch. (Only | |
528 | * applicable for weak-ordered memory model archs, | |
529 | * such as IA-64). | |
530 | */ | |
531 | wmb(); | |
532 | IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val); | |
533 | } | |
534 | ||
9a799d71 AK |
535 | /** |
536 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
537 | * @adapter: address of board private structure | |
538 | **/ | |
539 | static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter, | |
7c6e0a43 JB |
540 | struct ixgbe_ring *rx_ring, |
541 | int cleaned_count) | |
9a799d71 | 542 | { |
9a799d71 AK |
543 | struct pci_dev *pdev = adapter->pdev; |
544 | union ixgbe_adv_rx_desc *rx_desc; | |
3a581073 | 545 | struct ixgbe_rx_buffer *bi; |
9a799d71 | 546 | unsigned int i; |
e8e26350 | 547 | unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN; |
9a799d71 AK |
548 | |
549 | i = rx_ring->next_to_use; | |
3a581073 | 550 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
551 | |
552 | while (cleaned_count--) { | |
553 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
554 | ||
762f4c57 | 555 | if (!bi->page_dma && |
3a581073 | 556 | (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) { |
3a581073 | 557 | if (!bi->page) { |
762f4c57 JB |
558 | bi->page = alloc_page(GFP_ATOMIC); |
559 | if (!bi->page) { | |
560 | adapter->alloc_rx_page_failed++; | |
561 | goto no_buffers; | |
562 | } | |
563 | bi->page_offset = 0; | |
564 | } else { | |
565 | /* use a half page if we're re-using */ | |
566 | bi->page_offset ^= (PAGE_SIZE / 2); | |
9a799d71 | 567 | } |
762f4c57 JB |
568 | |
569 | bi->page_dma = pci_map_page(pdev, bi->page, | |
570 | bi->page_offset, | |
571 | (PAGE_SIZE / 2), | |
572 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
573 | } |
574 | ||
3a581073 | 575 | if (!bi->skb) { |
5ecc3614 | 576 | struct sk_buff *skb; |
e8e26350 | 577 | skb = netdev_alloc_skb(adapter->netdev, bufsz); |
9a799d71 AK |
578 | |
579 | if (!skb) { | |
580 | adapter->alloc_rx_buff_failed++; | |
581 | goto no_buffers; | |
582 | } | |
583 | ||
584 | /* | |
585 | * Make buffer alignment 2 beyond a 16 byte boundary | |
586 | * this will result in a 16 byte aligned IP header after | |
587 | * the 14 byte MAC header is removed | |
588 | */ | |
589 | skb_reserve(skb, NET_IP_ALIGN); | |
590 | ||
3a581073 | 591 | bi->skb = skb; |
e8e26350 | 592 | bi->dma = pci_map_single(pdev, skb->data, bufsz, |
3a581073 | 593 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
594 | } |
595 | /* Refresh the desc even if buffer_addrs didn't change because | |
596 | * each write-back erases this info. */ | |
597 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
3a581073 JB |
598 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
599 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 600 | } else { |
3a581073 | 601 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
9a799d71 AK |
602 | } |
603 | ||
604 | i++; | |
605 | if (i == rx_ring->count) | |
606 | i = 0; | |
3a581073 | 607 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 | 608 | } |
7c6e0a43 | 609 | |
9a799d71 AK |
610 | no_buffers: |
611 | if (rx_ring->next_to_use != i) { | |
612 | rx_ring->next_to_use = i; | |
613 | if (i-- == 0) | |
614 | i = (rx_ring->count - 1); | |
615 | ||
e8e26350 | 616 | ixgbe_release_rx_desc(&adapter->hw, rx_ring, i); |
9a799d71 AK |
617 | } |
618 | } | |
619 | ||
7c6e0a43 JB |
620 | static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc) |
621 | { | |
622 | return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
623 | } | |
624 | ||
625 | static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc) | |
626 | { | |
627 | return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
628 | } | |
629 | ||
f8212f97 AD |
630 | static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc) |
631 | { | |
632 | return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) & | |
633 | IXGBE_RXDADV_RSCCNT_MASK) >> | |
634 | IXGBE_RXDADV_RSCCNT_SHIFT; | |
635 | } | |
636 | ||
637 | /** | |
638 | * ixgbe_transform_rsc_queue - change rsc queue into a full packet | |
639 | * @skb: pointer to the last skb in the rsc queue | |
640 | * | |
641 | * This function changes a queue full of hw rsc buffers into a completed | |
642 | * packet. It uses the ->prev pointers to find the first packet and then | |
643 | * turns it into the frag list owner. | |
644 | **/ | |
645 | static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb) | |
646 | { | |
647 | unsigned int frag_list_size = 0; | |
648 | ||
649 | while (skb->prev) { | |
650 | struct sk_buff *prev = skb->prev; | |
651 | frag_list_size += skb->len; | |
652 | skb->prev = NULL; | |
653 | skb = prev; | |
654 | } | |
655 | ||
656 | skb_shinfo(skb)->frag_list = skb->next; | |
657 | skb->next = NULL; | |
658 | skb->len += frag_list_size; | |
659 | skb->data_len += frag_list_size; | |
660 | skb->truesize += frag_list_size; | |
661 | return skb; | |
662 | } | |
663 | ||
78b6f4ce | 664 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
b4617240 PW |
665 | struct ixgbe_ring *rx_ring, |
666 | int *work_done, int work_to_do) | |
9a799d71 | 667 | { |
78b6f4ce | 668 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a799d71 AK |
669 | struct pci_dev *pdev = adapter->pdev; |
670 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; | |
671 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
672 | struct sk_buff *skb; | |
f8212f97 | 673 | unsigned int i, rsc_count = 0; |
7c6e0a43 | 674 | u32 len, staterr; |
177db6ff MC |
675 | u16 hdr_info; |
676 | bool cleaned = false; | |
9a799d71 | 677 | int cleaned_count = 0; |
d2f4fbe2 | 678 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
9a799d71 AK |
679 | |
680 | i = rx_ring->next_to_clean; | |
9a799d71 AK |
681 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); |
682 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
683 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
9a799d71 AK |
684 | |
685 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 686 | u32 upper_len = 0; |
9a799d71 AK |
687 | if (*work_done >= work_to_do) |
688 | break; | |
689 | (*work_done)++; | |
690 | ||
691 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 JB |
692 | hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); |
693 | len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
762f4c57 | 694 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; |
9a799d71 AK |
695 | if (hdr_info & IXGBE_RXDADV_SPH) |
696 | adapter->rx_hdr_split++; | |
697 | if (len > IXGBE_RX_HDR_SIZE) | |
698 | len = IXGBE_RX_HDR_SIZE; | |
699 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
7c6e0a43 | 700 | } else { |
9a799d71 | 701 | len = le16_to_cpu(rx_desc->wb.upper.length); |
7c6e0a43 | 702 | } |
9a799d71 AK |
703 | |
704 | cleaned = true; | |
705 | skb = rx_buffer_info->skb; | |
706 | prefetch(skb->data - NET_IP_ALIGN); | |
707 | rx_buffer_info->skb = NULL; | |
708 | ||
709 | if (len && !skb_shinfo(skb)->nr_frags) { | |
710 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
5ecc3614 | 711 | rx_ring->rx_buf_len, |
b4617240 | 712 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
713 | skb_put(skb, len); |
714 | } | |
715 | ||
716 | if (upper_len) { | |
717 | pci_unmap_page(pdev, rx_buffer_info->page_dma, | |
762f4c57 | 718 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9a799d71 AK |
719 | rx_buffer_info->page_dma = 0; |
720 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
762f4c57 JB |
721 | rx_buffer_info->page, |
722 | rx_buffer_info->page_offset, | |
723 | upper_len); | |
724 | ||
725 | if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) || | |
726 | (page_count(rx_buffer_info->page) != 1)) | |
727 | rx_buffer_info->page = NULL; | |
728 | else | |
729 | get_page(rx_buffer_info->page); | |
9a799d71 AK |
730 | |
731 | skb->len += upper_len; | |
732 | skb->data_len += upper_len; | |
733 | skb->truesize += upper_len; | |
734 | } | |
735 | ||
736 | i++; | |
737 | if (i == rx_ring->count) | |
738 | i = 0; | |
9a799d71 AK |
739 | |
740 | next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
741 | prefetch(next_rxd); | |
9a799d71 | 742 | cleaned_count++; |
f8212f97 AD |
743 | |
744 | if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE) | |
745 | rsc_count = ixgbe_get_rsc_count(rx_desc); | |
746 | ||
747 | if (rsc_count) { | |
748 | u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >> | |
749 | IXGBE_RXDADV_NEXTP_SHIFT; | |
750 | next_buffer = &rx_ring->rx_buffer_info[nextp]; | |
751 | rx_ring->rsc_count += (rsc_count - 1); | |
752 | } else { | |
753 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
754 | } | |
755 | ||
9a799d71 | 756 | if (staterr & IXGBE_RXD_STAT_EOP) { |
f8212f97 AD |
757 | if (skb->prev) |
758 | skb = ixgbe_transform_rsc_queue(skb); | |
9a799d71 AK |
759 | rx_ring->stats.packets++; |
760 | rx_ring->stats.bytes += skb->len; | |
761 | } else { | |
f8212f97 AD |
762 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { |
763 | rx_buffer_info->skb = next_buffer->skb; | |
764 | rx_buffer_info->dma = next_buffer->dma; | |
765 | next_buffer->skb = skb; | |
766 | next_buffer->dma = 0; | |
767 | } else { | |
768 | skb->next = next_buffer->skb; | |
769 | skb->next->prev = skb; | |
770 | } | |
9a799d71 AK |
771 | adapter->non_eop_descs++; |
772 | goto next_desc; | |
773 | } | |
774 | ||
775 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { | |
776 | dev_kfree_skb_irq(skb); | |
777 | goto next_desc; | |
778 | } | |
779 | ||
780 | ixgbe_rx_checksum(adapter, staterr, skb); | |
d2f4fbe2 AV |
781 | |
782 | /* probably a little skewed due to removing CRC */ | |
783 | total_rx_bytes += skb->len; | |
784 | total_rx_packets++; | |
785 | ||
74ce8dd2 | 786 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
332d4a7d YZ |
787 | #ifdef IXGBE_FCOE |
788 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
789 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
790 | if (!ixgbe_fcoe_ddp(adapter, rx_desc, skb)) | |
791 | goto next_desc; | |
792 | #endif /* IXGBE_FCOE */ | |
fdaff1ce | 793 | ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc); |
9a799d71 AK |
794 | |
795 | next_desc: | |
796 | rx_desc->wb.upper.status_error = 0; | |
797 | ||
798 | /* return some buffers to hardware, one at a time is too slow */ | |
799 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
800 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
801 | cleaned_count = 0; | |
802 | } | |
803 | ||
804 | /* use prefetched values */ | |
805 | rx_desc = next_rxd; | |
f8212f97 | 806 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
807 | |
808 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
177db6ff MC |
809 | } |
810 | ||
9a799d71 AK |
811 | rx_ring->next_to_clean = i; |
812 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
813 | ||
814 | if (cleaned_count) | |
815 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
816 | ||
f494e8fa AV |
817 | rx_ring->total_packets += total_rx_packets; |
818 | rx_ring->total_bytes += total_rx_bytes; | |
819 | adapter->net_stats.rx_bytes += total_rx_bytes; | |
820 | adapter->net_stats.rx_packets += total_rx_packets; | |
821 | ||
9a799d71 AK |
822 | return cleaned; |
823 | } | |
824 | ||
021230d4 | 825 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
826 | /** |
827 | * ixgbe_configure_msix - Configure MSI-X hardware | |
828 | * @adapter: board private structure | |
829 | * | |
830 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
831 | * interrupts. | |
832 | **/ | |
833 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
834 | { | |
021230d4 AV |
835 | struct ixgbe_q_vector *q_vector; |
836 | int i, j, q_vectors, v_idx, r_idx; | |
837 | u32 mask; | |
9a799d71 | 838 | |
021230d4 | 839 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 840 | |
4df10466 JB |
841 | /* |
842 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
843 | * corresponding register. |
844 | */ | |
845 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
7a921c93 | 846 | q_vector = adapter->q_vector[v_idx]; |
021230d4 AV |
847 | /* XXX for_each_bit(...) */ |
848 | r_idx = find_first_bit(q_vector->rxr_idx, | |
b4617240 | 849 | adapter->num_rx_queues); |
021230d4 AV |
850 | |
851 | for (i = 0; i < q_vector->rxr_count; i++) { | |
852 | j = adapter->rx_ring[r_idx].reg_idx; | |
e8e26350 | 853 | ixgbe_set_ivar(adapter, 0, j, v_idx); |
021230d4 | 854 | r_idx = find_next_bit(q_vector->rxr_idx, |
b4617240 PW |
855 | adapter->num_rx_queues, |
856 | r_idx + 1); | |
021230d4 AV |
857 | } |
858 | r_idx = find_first_bit(q_vector->txr_idx, | |
b4617240 | 859 | adapter->num_tx_queues); |
021230d4 AV |
860 | |
861 | for (i = 0; i < q_vector->txr_count; i++) { | |
862 | j = adapter->tx_ring[r_idx].reg_idx; | |
e8e26350 | 863 | ixgbe_set_ivar(adapter, 1, j, v_idx); |
021230d4 | 864 | r_idx = find_next_bit(q_vector->txr_idx, |
b4617240 PW |
865 | adapter->num_tx_queues, |
866 | r_idx + 1); | |
021230d4 AV |
867 | } |
868 | ||
30efa5a3 | 869 | /* if this is a tx only vector halve the interrupt rate */ |
021230d4 | 870 | if (q_vector->txr_count && !q_vector->rxr_count) |
30efa5a3 | 871 | q_vector->eitr = (adapter->eitr_param >> 1); |
509ee935 | 872 | else if (q_vector->rxr_count) |
30efa5a3 JB |
873 | /* rx only */ |
874 | q_vector->eitr = adapter->eitr_param; | |
021230d4 | 875 | |
509ee935 | 876 | /* |
4df10466 | 877 | * since this is initial set up don't need to call |
509ee935 JB |
878 | * ixgbe_write_eitr helper |
879 | */ | |
021230d4 | 880 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), |
b4617240 | 881 | EITR_INTS_PER_SEC_TO_REG(q_vector->eitr)); |
9a799d71 AK |
882 | } |
883 | ||
e8e26350 PW |
884 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
885 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, | |
886 | v_idx); | |
887 | else if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
888 | ixgbe_set_ivar(adapter, -1, 1, v_idx); | |
021230d4 AV |
889 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
890 | ||
41fb9248 | 891 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 892 | mask = IXGBE_EIMS_ENABLE_MASK; |
41fb9248 | 893 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); |
021230d4 | 894 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
895 | } |
896 | ||
f494e8fa AV |
897 | enum latency_range { |
898 | lowest_latency = 0, | |
899 | low_latency = 1, | |
900 | bulk_latency = 2, | |
901 | latency_invalid = 255 | |
902 | }; | |
903 | ||
904 | /** | |
905 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
906 | * @adapter: pointer to adapter | |
907 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
908 | * @itr_setting: current throttle rate in ints/second | |
909 | * @packets: the number of packets during this measurement interval | |
910 | * @bytes: the number of bytes during this measurement interval | |
911 | * | |
912 | * Stores a new ITR value based on packets and byte | |
913 | * counts during the last interrupt. The advantage of per interrupt | |
914 | * computation is faster updates and more accurate ITR for the current | |
915 | * traffic pattern. Constants in this function were computed | |
916 | * based on theoretical maximum wire speed and thresholds were set based | |
917 | * on testing data as well as attempting to minimize response time | |
918 | * while increasing bulk throughput. | |
919 | * this functionality is controlled by the InterruptThrottleRate module | |
920 | * parameter (see ixgbe_param.c) | |
921 | **/ | |
922 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
b4617240 PW |
923 | u32 eitr, u8 itr_setting, |
924 | int packets, int bytes) | |
f494e8fa AV |
925 | { |
926 | unsigned int retval = itr_setting; | |
927 | u32 timepassed_us; | |
928 | u64 bytes_perint; | |
929 | ||
930 | if (packets == 0) | |
931 | goto update_itr_done; | |
932 | ||
933 | ||
934 | /* simple throttlerate management | |
935 | * 0-20MB/s lowest (100000 ints/s) | |
936 | * 20-100MB/s low (20000 ints/s) | |
937 | * 100-1249MB/s bulk (8000 ints/s) | |
938 | */ | |
939 | /* what was last interrupt timeslice? */ | |
940 | timepassed_us = 1000000/eitr; | |
941 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
942 | ||
943 | switch (itr_setting) { | |
944 | case lowest_latency: | |
945 | if (bytes_perint > adapter->eitr_low) | |
946 | retval = low_latency; | |
947 | break; | |
948 | case low_latency: | |
949 | if (bytes_perint > adapter->eitr_high) | |
950 | retval = bulk_latency; | |
951 | else if (bytes_perint <= adapter->eitr_low) | |
952 | retval = lowest_latency; | |
953 | break; | |
954 | case bulk_latency: | |
955 | if (bytes_perint <= adapter->eitr_high) | |
956 | retval = low_latency; | |
957 | break; | |
958 | } | |
959 | ||
960 | update_itr_done: | |
961 | return retval; | |
962 | } | |
963 | ||
509ee935 JB |
964 | /** |
965 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
966 | * @adapter: pointer to adapter struct | |
967 | * @v_idx: vector index into q_vector array | |
968 | * @itr_reg: new value to be written in *register* format, not ints/s | |
969 | * | |
970 | * This function is made to be called by ethtool and by the driver | |
971 | * when it needs to update EITR registers at runtime. Hardware | |
972 | * specific quirks/differences are taken care of here. | |
973 | */ | |
974 | void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg) | |
975 | { | |
976 | struct ixgbe_hw *hw = &adapter->hw; | |
977 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
978 | /* must write high and low 16 bits to reset counter */ | |
979 | itr_reg |= (itr_reg << 16); | |
980 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
981 | /* | |
982 | * set the WDIS bit to not clear the timer bits and cause an | |
983 | * immediate assertion of the interrupt | |
984 | */ | |
985 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
986 | } | |
987 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
988 | } | |
989 | ||
f494e8fa AV |
990 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) |
991 | { | |
992 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f494e8fa AV |
993 | u32 new_itr; |
994 | u8 current_itr, ret_itr; | |
7a921c93 | 995 | int i, r_idx, v_idx = q_vector->v_idx; |
f494e8fa AV |
996 | struct ixgbe_ring *rx_ring, *tx_ring; |
997 | ||
998 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
999 | for (i = 0; i < q_vector->txr_count; i++) { | |
1000 | tx_ring = &(adapter->tx_ring[r_idx]); | |
1001 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
1002 | q_vector->tx_itr, |
1003 | tx_ring->total_packets, | |
1004 | tx_ring->total_bytes); | |
f494e8fa AV |
1005 | /* if the result for this queue would decrease interrupt |
1006 | * rate for this vector then use that result */ | |
30efa5a3 | 1007 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
b4617240 | 1008 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 1009 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1010 | r_idx + 1); |
f494e8fa AV |
1011 | } |
1012 | ||
1013 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1014 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1015 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1016 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
1017 | q_vector->rx_itr, |
1018 | rx_ring->total_packets, | |
1019 | rx_ring->total_bytes); | |
f494e8fa AV |
1020 | /* if the result for this queue would decrease interrupt |
1021 | * rate for this vector then use that result */ | |
30efa5a3 | 1022 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
b4617240 | 1023 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 1024 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
b4617240 | 1025 | r_idx + 1); |
f494e8fa AV |
1026 | } |
1027 | ||
30efa5a3 | 1028 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1029 | |
1030 | switch (current_itr) { | |
1031 | /* counts and packets in update_itr are dependent on these numbers */ | |
1032 | case lowest_latency: | |
1033 | new_itr = 100000; | |
1034 | break; | |
1035 | case low_latency: | |
1036 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1037 | break; | |
1038 | case bulk_latency: | |
1039 | default: | |
1040 | new_itr = 8000; | |
1041 | break; | |
1042 | } | |
1043 | ||
1044 | if (new_itr != q_vector->eitr) { | |
1045 | u32 itr_reg; | |
509ee935 JB |
1046 | |
1047 | /* save the algorithm value here, not the smoothed one */ | |
1048 | q_vector->eitr = new_itr; | |
f494e8fa AV |
1049 | /* do an exponential smoothing */ |
1050 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
f494e8fa | 1051 | itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); |
509ee935 | 1052 | ixgbe_write_eitr(adapter, v_idx, itr_reg); |
f494e8fa AV |
1053 | } |
1054 | ||
1055 | return; | |
1056 | } | |
1057 | ||
0befdb3e JB |
1058 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
1059 | { | |
1060 | struct ixgbe_hw *hw = &adapter->hw; | |
1061 | ||
1062 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
1063 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
1064 | DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n"); | |
1065 | /* write to clear the interrupt */ | |
1066 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1067 | } | |
1068 | } | |
cf8280ee | 1069 | |
e8e26350 PW |
1070 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
1071 | { | |
1072 | struct ixgbe_hw *hw = &adapter->hw; | |
1073 | ||
1074 | if (eicr & IXGBE_EICR_GPI_SDP1) { | |
1075 | /* Clear the interrupt */ | |
1076 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1077 | schedule_work(&adapter->multispeed_fiber_task); | |
1078 | } else if (eicr & IXGBE_EICR_GPI_SDP2) { | |
1079 | /* Clear the interrupt */ | |
1080 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
1081 | schedule_work(&adapter->sfp_config_module_task); | |
1082 | } else { | |
1083 | /* Interrupt isn't for us... */ | |
1084 | return; | |
1085 | } | |
1086 | } | |
1087 | ||
cf8280ee JB |
1088 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
1089 | { | |
1090 | struct ixgbe_hw *hw = &adapter->hw; | |
1091 | ||
1092 | adapter->lsc_int++; | |
1093 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
1094 | adapter->link_check_timeout = jiffies; | |
1095 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1096 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
1097 | schedule_work(&adapter->watchdog_task); | |
1098 | } | |
1099 | } | |
1100 | ||
9a799d71 AK |
1101 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
1102 | { | |
1103 | struct net_device *netdev = data; | |
1104 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1105 | struct ixgbe_hw *hw = &adapter->hw; | |
54037505 DS |
1106 | u32 eicr; |
1107 | ||
1108 | /* | |
1109 | * Workaround for Silicon errata. Use clear-by-write instead | |
1110 | * of clear-by-read. Reading with EICS will return the | |
1111 | * interrupt causes without clearing, which later be done | |
1112 | * with the write to EICR. | |
1113 | */ | |
1114 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
1115 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
9a799d71 | 1116 | |
cf8280ee JB |
1117 | if (eicr & IXGBE_EICR_LSC) |
1118 | ixgbe_check_lsc(adapter); | |
d4f80882 | 1119 | |
e8e26350 PW |
1120 | if (hw->mac.type == ixgbe_mac_82598EB) |
1121 | ixgbe_check_fan_failure(adapter, eicr); | |
0befdb3e | 1122 | |
e8e26350 PW |
1123 | if (hw->mac.type == ixgbe_mac_82599EB) |
1124 | ixgbe_check_sfp_event(adapter, eicr); | |
d4f80882 AV |
1125 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1126 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
1127 | |
1128 | return IRQ_HANDLED; | |
1129 | } | |
1130 | ||
1131 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) | |
1132 | { | |
021230d4 AV |
1133 | struct ixgbe_q_vector *q_vector = data; |
1134 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1135 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
1136 | int i, r_idx; |
1137 | ||
1138 | if (!q_vector->txr_count) | |
1139 | return IRQ_HANDLED; | |
1140 | ||
1141 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1142 | for (i = 0; i < q_vector->txr_count; i++) { | |
3a581073 | 1143 | tx_ring = &(adapter->tx_ring[r_idx]); |
5dd2d332 | 1144 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1145 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1146 | ixgbe_update_tx_dca(adapter, tx_ring); |
bd0362dd | 1147 | #endif |
3a581073 JB |
1148 | tx_ring->total_bytes = 0; |
1149 | tx_ring->total_packets = 0; | |
1150 | ixgbe_clean_tx_irq(adapter, tx_ring); | |
021230d4 | 1151 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1152 | r_idx + 1); |
021230d4 | 1153 | } |
9a799d71 | 1154 | |
9a799d71 AK |
1155 | return IRQ_HANDLED; |
1156 | } | |
1157 | ||
021230d4 AV |
1158 | /** |
1159 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
1160 | * @irq: unused | |
1161 | * @data: pointer to our q_vector struct for this interrupt vector | |
1162 | **/ | |
9a799d71 AK |
1163 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
1164 | { | |
021230d4 AV |
1165 | struct ixgbe_q_vector *q_vector = data; |
1166 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1167 | struct ixgbe_ring *rx_ring; |
021230d4 | 1168 | int r_idx; |
30efa5a3 | 1169 | int i; |
021230d4 AV |
1170 | |
1171 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
30efa5a3 JB |
1172 | for (i = 0; i < q_vector->rxr_count; i++) { |
1173 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1174 | rx_ring->total_bytes = 0; | |
1175 | rx_ring->total_packets = 0; | |
1176 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1177 | r_idx + 1); | |
1178 | } | |
1179 | ||
021230d4 AV |
1180 | if (!q_vector->rxr_count) |
1181 | return IRQ_HANDLED; | |
1182 | ||
30efa5a3 | 1183 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1184 | rx_ring = &(adapter->rx_ring[r_idx]); |
021230d4 | 1185 | /* disable interrupts on this vector only */ |
835462fc NS |
1186 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
1187 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx); | |
1188 | else if (rx_ring->v_idx & 0xFFFFFFFF) | |
1189 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), rx_ring->v_idx); | |
1190 | else | |
1191 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), | |
1192 | (rx_ring->v_idx >> 32)); | |
288379f0 | 1193 | napi_schedule(&q_vector->napi); |
021230d4 AV |
1194 | |
1195 | return IRQ_HANDLED; | |
1196 | } | |
1197 | ||
1198 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
1199 | { | |
1200 | ixgbe_msix_clean_rx(irq, data); | |
1201 | ixgbe_msix_clean_tx(irq, data); | |
9a799d71 | 1202 | |
9a799d71 AK |
1203 | return IRQ_HANDLED; |
1204 | } | |
1205 | ||
835462fc NS |
1206 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
1207 | u64 qmask) | |
1208 | { | |
1209 | u32 mask; | |
1210 | ||
1211 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1212 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1213 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); | |
1214 | } else { | |
1215 | mask = (qmask & 0xFFFFFFFF); | |
1216 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask); | |
1217 | mask = (qmask >> 32); | |
1218 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask); | |
1219 | } | |
1220 | /* skip the flush */ | |
1221 | } | |
1222 | ||
021230d4 AV |
1223 | /** |
1224 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
1225 | * @napi: napi struct with our devices info in it | |
1226 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1227 | * | |
f0848276 JB |
1228 | * This function is optimized for cleaning one queue only on a single |
1229 | * q_vector!!! | |
021230d4 | 1230 | **/ |
9a799d71 AK |
1231 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
1232 | { | |
021230d4 | 1233 | struct ixgbe_q_vector *q_vector = |
b4617240 | 1234 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 1235 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 1236 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 1237 | int work_done = 0; |
021230d4 | 1238 | long r_idx; |
9a799d71 | 1239 | |
021230d4 | 1240 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1241 | rx_ring = &(adapter->rx_ring[r_idx]); |
5dd2d332 | 1242 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1243 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1244 | ixgbe_update_rx_dca(adapter, rx_ring); |
bd0362dd | 1245 | #endif |
9a799d71 | 1246 | |
78b6f4ce | 1247 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
9a799d71 | 1248 | |
021230d4 AV |
1249 | /* If all Rx work done, exit the polling mode */ |
1250 | if (work_done < budget) { | |
288379f0 | 1251 | napi_complete(napi); |
509ee935 | 1252 | if (adapter->itr_setting & 1) |
f494e8fa | 1253 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 1254 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 1255 | ixgbe_irq_enable_queues(adapter, rx_ring->v_idx); |
9a799d71 AK |
1256 | } |
1257 | ||
1258 | return work_done; | |
1259 | } | |
1260 | ||
f0848276 JB |
1261 | /** |
1262 | * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine | |
1263 | * @napi: napi struct with our devices info in it | |
1264 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1265 | * | |
1266 | * This function will clean more than one rx queue associated with a | |
1267 | * q_vector. | |
1268 | **/ | |
1269 | static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget) | |
1270 | { | |
1271 | struct ixgbe_q_vector *q_vector = | |
1272 | container_of(napi, struct ixgbe_q_vector, napi); | |
1273 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f0848276 JB |
1274 | struct ixgbe_ring *rx_ring = NULL; |
1275 | int work_done = 0, i; | |
1276 | long r_idx; | |
835462fc | 1277 | u64 enable_mask = 0; |
f0848276 JB |
1278 | |
1279 | /* attempt to distribute budget to each queue fairly, but don't allow | |
1280 | * the budget to go below 1 because we'll exit polling */ | |
1281 | budget /= (q_vector->rxr_count ?: 1); | |
1282 | budget = max(budget, 1); | |
1283 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1284 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1285 | rx_ring = &(adapter->rx_ring[r_idx]); | |
5dd2d332 | 1286 | #ifdef CONFIG_IXGBE_DCA |
f0848276 JB |
1287 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1288 | ixgbe_update_rx_dca(adapter, rx_ring); | |
1289 | #endif | |
78b6f4ce | 1290 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
f0848276 JB |
1291 | enable_mask |= rx_ring->v_idx; |
1292 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1293 | r_idx + 1); | |
1294 | } | |
1295 | ||
1296 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1297 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1298 | /* If all Rx work done, exit the polling mode */ | |
7f821875 | 1299 | if (work_done < budget) { |
288379f0 | 1300 | napi_complete(napi); |
509ee935 | 1301 | if (adapter->itr_setting & 1) |
f0848276 JB |
1302 | ixgbe_set_itr_msix(q_vector); |
1303 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
835462fc | 1304 | ixgbe_irq_enable_queues(adapter, enable_mask); |
f0848276 JB |
1305 | return 0; |
1306 | } | |
1307 | ||
1308 | return work_done; | |
1309 | } | |
021230d4 | 1310 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
b4617240 | 1311 | int r_idx) |
021230d4 | 1312 | { |
7a921c93 AD |
1313 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1314 | ||
1315 | set_bit(r_idx, q_vector->rxr_idx); | |
1316 | q_vector->rxr_count++; | |
c9c7d2e5 | 1317 | a->rx_ring[r_idx].v_idx = (u64)1 << v_idx; |
021230d4 AV |
1318 | } |
1319 | ||
1320 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
7a921c93 | 1321 | int t_idx) |
021230d4 | 1322 | { |
7a921c93 AD |
1323 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1324 | ||
1325 | set_bit(t_idx, q_vector->txr_idx); | |
1326 | q_vector->txr_count++; | |
c9c7d2e5 | 1327 | a->tx_ring[t_idx].v_idx = (u64)1 << v_idx; |
021230d4 AV |
1328 | } |
1329 | ||
9a799d71 | 1330 | /** |
021230d4 AV |
1331 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
1332 | * @adapter: board private structure to initialize | |
1333 | * @vectors: allotted vector count for descriptor rings | |
9a799d71 | 1334 | * |
021230d4 AV |
1335 | * This function maps descriptor rings to the queue-specific vectors |
1336 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
1337 | * one vector per ring/queue, but on a constrained vector budget, we | |
1338 | * group the rings as "efficiently" as possible. You would add new | |
1339 | * mapping configurations in here. | |
9a799d71 | 1340 | **/ |
021230d4 | 1341 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 1342 | int vectors) |
021230d4 AV |
1343 | { |
1344 | int v_start = 0; | |
1345 | int rxr_idx = 0, txr_idx = 0; | |
1346 | int rxr_remaining = adapter->num_rx_queues; | |
1347 | int txr_remaining = adapter->num_tx_queues; | |
1348 | int i, j; | |
1349 | int rqpv, tqpv; | |
1350 | int err = 0; | |
1351 | ||
1352 | /* No mapping required if MSI-X is disabled. */ | |
1353 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1354 | goto out; | |
9a799d71 | 1355 | |
021230d4 AV |
1356 | /* |
1357 | * The ideal configuration... | |
1358 | * We have enough vectors to map one per queue. | |
1359 | */ | |
1360 | if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) { | |
1361 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) | |
1362 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 1363 | |
021230d4 AV |
1364 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
1365 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 1366 | |
9a799d71 | 1367 | goto out; |
021230d4 | 1368 | } |
9a799d71 | 1369 | |
021230d4 AV |
1370 | /* |
1371 | * If we don't have enough vectors for a 1-to-1 | |
1372 | * mapping, we'll have to group them so there are | |
1373 | * multiple queues per vector. | |
1374 | */ | |
1375 | /* Re-adjusting *qpv takes care of the remainder. */ | |
1376 | for (i = v_start; i < vectors; i++) { | |
1377 | rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i); | |
1378 | for (j = 0; j < rqpv; j++) { | |
1379 | map_vector_to_rxq(adapter, i, rxr_idx); | |
1380 | rxr_idx++; | |
1381 | rxr_remaining--; | |
1382 | } | |
1383 | } | |
1384 | for (i = v_start; i < vectors; i++) { | |
1385 | tqpv = DIV_ROUND_UP(txr_remaining, vectors - i); | |
1386 | for (j = 0; j < tqpv; j++) { | |
1387 | map_vector_to_txq(adapter, i, txr_idx); | |
1388 | txr_idx++; | |
1389 | txr_remaining--; | |
9a799d71 | 1390 | } |
9a799d71 AK |
1391 | } |
1392 | ||
021230d4 AV |
1393 | out: |
1394 | return err; | |
1395 | } | |
1396 | ||
1397 | /** | |
1398 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
1399 | * @adapter: board private structure | |
1400 | * | |
1401 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
1402 | * interrupts from the kernel. | |
1403 | **/ | |
1404 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
1405 | { | |
1406 | struct net_device *netdev = adapter->netdev; | |
1407 | irqreturn_t (*handler)(int, void *); | |
1408 | int i, vector, q_vectors, err; | |
cb13fc20 | 1409 | int ri=0, ti=0; |
021230d4 AV |
1410 | |
1411 | /* Decrement for Other and TCP Timer vectors */ | |
1412 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1413 | ||
1414 | /* Map the Tx/Rx rings to the vectors we were allotted. */ | |
1415 | err = ixgbe_map_rings_to_vectors(adapter, q_vectors); | |
1416 | if (err) | |
1417 | goto out; | |
1418 | ||
1419 | #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \ | |
b4617240 PW |
1420 | (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \ |
1421 | &ixgbe_msix_clean_many) | |
021230d4 | 1422 | for (vector = 0; vector < q_vectors; vector++) { |
7a921c93 | 1423 | handler = SET_HANDLER(adapter->q_vector[vector]); |
cb13fc20 RO |
1424 | |
1425 | if(handler == &ixgbe_msix_clean_rx) { | |
1426 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1427 | netdev->name, "rx", ri++); | |
1428 | } | |
1429 | else if(handler == &ixgbe_msix_clean_tx) { | |
1430 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1431 | netdev->name, "tx", ti++); | |
1432 | } | |
1433 | else | |
1434 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1435 | netdev->name, "TxRx", vector); | |
1436 | ||
021230d4 | 1437 | err = request_irq(adapter->msix_entries[vector].vector, |
b4617240 | 1438 | handler, 0, adapter->name[vector], |
7a921c93 | 1439 | adapter->q_vector[vector]); |
9a799d71 AK |
1440 | if (err) { |
1441 | DPRINTK(PROBE, ERR, | |
b4617240 PW |
1442 | "request_irq failed for MSIX interrupt " |
1443 | "Error: %d\n", err); | |
021230d4 | 1444 | goto free_queue_irqs; |
9a799d71 | 1445 | } |
9a799d71 AK |
1446 | } |
1447 | ||
021230d4 AV |
1448 | sprintf(adapter->name[vector], "%s:lsc", netdev->name); |
1449 | err = request_irq(adapter->msix_entries[vector].vector, | |
b4617240 | 1450 | &ixgbe_msix_lsc, 0, adapter->name[vector], netdev); |
9a799d71 AK |
1451 | if (err) { |
1452 | DPRINTK(PROBE, ERR, | |
1453 | "request_irq for msix_lsc failed: %d\n", err); | |
021230d4 | 1454 | goto free_queue_irqs; |
9a799d71 AK |
1455 | } |
1456 | ||
9a799d71 AK |
1457 | return 0; |
1458 | ||
021230d4 AV |
1459 | free_queue_irqs: |
1460 | for (i = vector - 1; i >= 0; i--) | |
1461 | free_irq(adapter->msix_entries[--vector].vector, | |
7a921c93 | 1462 | adapter->q_vector[i]); |
021230d4 AV |
1463 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
1464 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
1465 | kfree(adapter->msix_entries); |
1466 | adapter->msix_entries = NULL; | |
021230d4 | 1467 | out: |
9a799d71 AK |
1468 | return err; |
1469 | } | |
1470 | ||
f494e8fa AV |
1471 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
1472 | { | |
7a921c93 | 1473 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
f494e8fa AV |
1474 | u8 current_itr; |
1475 | u32 new_itr = q_vector->eitr; | |
1476 | struct ixgbe_ring *rx_ring = &adapter->rx_ring[0]; | |
1477 | struct ixgbe_ring *tx_ring = &adapter->tx_ring[0]; | |
1478 | ||
30efa5a3 | 1479 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1480 | q_vector->tx_itr, |
1481 | tx_ring->total_packets, | |
1482 | tx_ring->total_bytes); | |
30efa5a3 | 1483 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1484 | q_vector->rx_itr, |
1485 | rx_ring->total_packets, | |
1486 | rx_ring->total_bytes); | |
f494e8fa | 1487 | |
30efa5a3 | 1488 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1489 | |
1490 | switch (current_itr) { | |
1491 | /* counts and packets in update_itr are dependent on these numbers */ | |
1492 | case lowest_latency: | |
1493 | new_itr = 100000; | |
1494 | break; | |
1495 | case low_latency: | |
1496 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1497 | break; | |
1498 | case bulk_latency: | |
1499 | new_itr = 8000; | |
1500 | break; | |
1501 | default: | |
1502 | break; | |
1503 | } | |
1504 | ||
1505 | if (new_itr != q_vector->eitr) { | |
1506 | u32 itr_reg; | |
509ee935 JB |
1507 | |
1508 | /* save the algorithm value here, not the smoothed one */ | |
1509 | q_vector->eitr = new_itr; | |
f494e8fa AV |
1510 | /* do an exponential smoothing */ |
1511 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
f494e8fa | 1512 | itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); |
509ee935 | 1513 | ixgbe_write_eitr(adapter, 0, itr_reg); |
f494e8fa AV |
1514 | } |
1515 | ||
1516 | return; | |
1517 | } | |
1518 | ||
79aefa45 AD |
1519 | /** |
1520 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
1521 | * @adapter: board private structure | |
1522 | **/ | |
1523 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) | |
1524 | { | |
1525 | u32 mask; | |
835462fc NS |
1526 | |
1527 | mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); | |
6ab33d51 DM |
1528 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
1529 | mask |= IXGBE_EIMS_GPI_SDP1; | |
e8e26350 | 1530 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
2a41ff81 | 1531 | mask |= IXGBE_EIMS_ECC; |
e8e26350 PW |
1532 | mask |= IXGBE_EIMS_GPI_SDP1; |
1533 | mask |= IXGBE_EIMS_GPI_SDP2; | |
1534 | } | |
1535 | ||
79aefa45 | 1536 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
835462fc | 1537 | ixgbe_irq_enable_queues(adapter, ~0); |
79aefa45 AD |
1538 | IXGBE_WRITE_FLUSH(&adapter->hw); |
1539 | } | |
021230d4 | 1540 | |
9a799d71 | 1541 | /** |
021230d4 | 1542 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
1543 | * @irq: interrupt number |
1544 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
1545 | **/ |
1546 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
1547 | { | |
1548 | struct net_device *netdev = data; | |
1549 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1550 | struct ixgbe_hw *hw = &adapter->hw; | |
7a921c93 | 1551 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
1552 | u32 eicr; |
1553 | ||
54037505 DS |
1554 | /* |
1555 | * Workaround for silicon errata. Mask the interrupts | |
1556 | * before the read of EICR. | |
1557 | */ | |
1558 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
1559 | ||
021230d4 AV |
1560 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
1561 | * therefore no explict interrupt disable is necessary */ | |
1562 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e JB |
1563 | if (!eicr) { |
1564 | /* shared interrupt alert! | |
1565 | * make sure interrupts are enabled because the read will | |
1566 | * have disabled interrupts due to EIAM */ | |
1567 | ixgbe_irq_enable(adapter); | |
9a799d71 | 1568 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 1569 | } |
9a799d71 | 1570 | |
cf8280ee JB |
1571 | if (eicr & IXGBE_EICR_LSC) |
1572 | ixgbe_check_lsc(adapter); | |
021230d4 | 1573 | |
e8e26350 PW |
1574 | if (hw->mac.type == ixgbe_mac_82599EB) |
1575 | ixgbe_check_sfp_event(adapter, eicr); | |
1576 | ||
0befdb3e JB |
1577 | ixgbe_check_fan_failure(adapter, eicr); |
1578 | ||
7a921c93 | 1579 | if (napi_schedule_prep(&(q_vector->napi))) { |
f494e8fa AV |
1580 | adapter->tx_ring[0].total_packets = 0; |
1581 | adapter->tx_ring[0].total_bytes = 0; | |
1582 | adapter->rx_ring[0].total_packets = 0; | |
1583 | adapter->rx_ring[0].total_bytes = 0; | |
021230d4 | 1584 | /* would disable interrupts here but EIAM disabled it */ |
7a921c93 | 1585 | __napi_schedule(&(q_vector->napi)); |
9a799d71 AK |
1586 | } |
1587 | ||
1588 | return IRQ_HANDLED; | |
1589 | } | |
1590 | ||
021230d4 AV |
1591 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
1592 | { | |
1593 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1594 | ||
1595 | for (i = 0; i < q_vectors; i++) { | |
7a921c93 | 1596 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; |
021230d4 AV |
1597 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); |
1598 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
1599 | q_vector->rxr_count = 0; | |
1600 | q_vector->txr_count = 0; | |
1601 | } | |
1602 | } | |
1603 | ||
9a799d71 AK |
1604 | /** |
1605 | * ixgbe_request_irq - initialize interrupts | |
1606 | * @adapter: board private structure | |
1607 | * | |
1608 | * Attempts to configure interrupts using the best available | |
1609 | * capabilities of the hardware and kernel. | |
1610 | **/ | |
021230d4 | 1611 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
1612 | { |
1613 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 1614 | int err; |
9a799d71 | 1615 | |
021230d4 AV |
1616 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
1617 | err = ixgbe_request_msix_irqs(adapter); | |
1618 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
1619 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0, | |
b4617240 | 1620 | netdev->name, netdev); |
021230d4 AV |
1621 | } else { |
1622 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED, | |
b4617240 | 1623 | netdev->name, netdev); |
9a799d71 AK |
1624 | } |
1625 | ||
9a799d71 AK |
1626 | if (err) |
1627 | DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err); | |
1628 | ||
9a799d71 AK |
1629 | return err; |
1630 | } | |
1631 | ||
1632 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
1633 | { | |
1634 | struct net_device *netdev = adapter->netdev; | |
1635 | ||
1636 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 1637 | int i, q_vectors; |
9a799d71 | 1638 | |
021230d4 AV |
1639 | q_vectors = adapter->num_msix_vectors; |
1640 | ||
1641 | i = q_vectors - 1; | |
9a799d71 | 1642 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 1643 | |
021230d4 AV |
1644 | i--; |
1645 | for (; i >= 0; i--) { | |
1646 | free_irq(adapter->msix_entries[i].vector, | |
7a921c93 | 1647 | adapter->q_vector[i]); |
021230d4 AV |
1648 | } |
1649 | ||
1650 | ixgbe_reset_q_vectors(adapter); | |
1651 | } else { | |
1652 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
1653 | } |
1654 | } | |
1655 | ||
22d5a71b JB |
1656 | /** |
1657 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
1658 | * @adapter: board private structure | |
1659 | **/ | |
1660 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
1661 | { | |
835462fc NS |
1662 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
1663 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); | |
1664 | } else { | |
1665 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); | |
1666 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 1667 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
22d5a71b JB |
1668 | } |
1669 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1670 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
1671 | int i; | |
1672 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
1673 | synchronize_irq(adapter->msix_entries[i].vector); | |
1674 | } else { | |
1675 | synchronize_irq(adapter->pdev->irq); | |
1676 | } | |
1677 | } | |
1678 | ||
9a799d71 AK |
1679 | /** |
1680 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
1681 | * | |
1682 | **/ | |
1683 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
1684 | { | |
9a799d71 AK |
1685 | struct ixgbe_hw *hw = &adapter->hw; |
1686 | ||
021230d4 | 1687 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
30efa5a3 | 1688 | EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param)); |
9a799d71 | 1689 | |
e8e26350 PW |
1690 | ixgbe_set_ivar(adapter, 0, 0, 0); |
1691 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 AV |
1692 | |
1693 | map_vector_to_rxq(adapter, 0, 0); | |
1694 | map_vector_to_txq(adapter, 0, 0); | |
1695 | ||
1696 | DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n"); | |
9a799d71 AK |
1697 | } |
1698 | ||
1699 | /** | |
3a581073 | 1700 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
1701 | * @adapter: board private structure |
1702 | * | |
1703 | * Configure the Tx unit of the MAC after a reset. | |
1704 | **/ | |
1705 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
1706 | { | |
12207e49 | 1707 | u64 tdba; |
9a799d71 | 1708 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 1709 | u32 i, j, tdlen, txctrl; |
9a799d71 AK |
1710 | |
1711 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
1712 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
e01c31a5 JB |
1713 | struct ixgbe_ring *ring = &adapter->tx_ring[i]; |
1714 | j = ring->reg_idx; | |
1715 | tdba = ring->dma; | |
1716 | tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc); | |
021230d4 | 1717 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), |
284901a9 | 1718 | (tdba & DMA_BIT_MASK(32))); |
021230d4 AV |
1719 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); |
1720 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen); | |
1721 | IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); | |
1722 | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | |
1723 | adapter->tx_ring[i].head = IXGBE_TDH(j); | |
1724 | adapter->tx_ring[i].tail = IXGBE_TDT(j); | |
1725 | /* Disable Tx Head Writeback RO bit, since this hoses | |
1726 | * bookkeeping if things aren't delivered in order. | |
1727 | */ | |
e01c31a5 | 1728 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); |
021230d4 | 1729 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; |
e01c31a5 | 1730 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); |
9a799d71 | 1731 | } |
e8e26350 PW |
1732 | if (hw->mac.type == ixgbe_mac_82599EB) { |
1733 | /* We enable 8 traffic classes, DCB only */ | |
1734 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
1735 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA | | |
1736 | IXGBE_MTQC_8TC_8TQ)); | |
1737 | } | |
9a799d71 AK |
1738 | } |
1739 | ||
e8e26350 | 1740 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c JB |
1741 | |
1742 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index) | |
1743 | { | |
1744 | struct ixgbe_ring *rx_ring; | |
1745 | u32 srrctl; | |
e8e26350 | 1746 | int queue0 = 0; |
3be1adfb AD |
1747 | unsigned long mask; |
1748 | ||
e8e26350 | 1749 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
163de42e AD |
1750 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
1751 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
1752 | if (dcb_i == 8) | |
1753 | queue0 = index >> 4; | |
1754 | else if (dcb_i == 4) | |
1755 | queue0 = index >> 5; | |
1756 | else | |
1757 | dev_err(&adapter->pdev->dev, "Invalid DCB " | |
1758 | "configuration\n"); | |
0331a832 YZ |
1759 | #ifdef IXGBE_FCOE |
1760 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
1761 | struct ixgbe_ring_feature *f; | |
1762 | ||
1763 | rx_ring = &adapter->rx_ring[queue0]; | |
1764 | f = &adapter->ring_feature[RING_F_FCOE]; | |
1765 | if ((queue0 == 0) && (index > rx_ring->reg_idx)) | |
1766 | queue0 = f->mask + index - | |
1767 | rx_ring->reg_idx - 1; | |
1768 | } | |
1769 | #endif /* IXGBE_FCOE */ | |
163de42e AD |
1770 | } else { |
1771 | queue0 = index; | |
1772 | } | |
cc41ac7c | 1773 | } else { |
3be1adfb AD |
1774 | mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask; |
1775 | queue0 = index & mask; | |
1776 | index = index & mask; | |
cc41ac7c | 1777 | } |
3be1adfb | 1778 | |
cc41ac7c JB |
1779 | rx_ring = &adapter->rx_ring[queue0]; |
1780 | ||
1781 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index)); | |
1782 | ||
1783 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
1784 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
1785 | ||
afafd5b0 AD |
1786 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
1787 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
1788 | ||
cc41ac7c | 1789 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { |
afafd5b0 AD |
1790 | #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER |
1791 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1792 | #else | |
1793 | srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1794 | #endif | |
cc41ac7c | 1795 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
cc41ac7c | 1796 | } else { |
afafd5b0 AD |
1797 | srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >> |
1798 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
cc41ac7c | 1799 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
cc41ac7c | 1800 | } |
e8e26350 | 1801 | |
cc41ac7c JB |
1802 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl); |
1803 | } | |
9a799d71 | 1804 | |
9a799d71 | 1805 | /** |
3a581073 | 1806 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset |
9a799d71 AK |
1807 | * @adapter: board private structure |
1808 | * | |
1809 | * Configure the Rx unit of the MAC after a reset. | |
1810 | **/ | |
1811 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
1812 | { | |
1813 | u64 rdba; | |
1814 | struct ixgbe_hw *hw = &adapter->hw; | |
1815 | struct net_device *netdev = adapter->netdev; | |
1816 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
021230d4 | 1817 | int i, j; |
9a799d71 | 1818 | u32 rdlen, rxctrl, rxcsum; |
7c6e0a43 JB |
1819 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, |
1820 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, | |
1821 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
9a799d71 | 1822 | u32 fctrl, hlreg0; |
509ee935 | 1823 | u32 reta = 0, mrqc = 0; |
cc41ac7c | 1824 | u32 rdrxctl; |
f8212f97 | 1825 | u32 rscctrl; |
7c6e0a43 | 1826 | int rx_buf_len; |
9a799d71 AK |
1827 | |
1828 | /* Decide whether to use packet split mode or not */ | |
762f4c57 | 1829 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; |
9a799d71 | 1830 | |
eacd73f7 YZ |
1831 | #ifdef IXGBE_FCOE |
1832 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
1833 | adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED; | |
1834 | #endif /* IXGBE_FCOE */ | |
1835 | ||
9a799d71 AK |
1836 | /* Set the RX buffer length according to the mode */ |
1837 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 1838 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
e8e26350 PW |
1839 | if (hw->mac.type == ixgbe_mac_82599EB) { |
1840 | /* PSRTYPE must be initialized in 82599 */ | |
1841 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
1842 | IXGBE_PSRTYPE_UDPHDR | | |
1843 | IXGBE_PSRTYPE_IPV4HDR | | |
dfa12f05 YZ |
1844 | IXGBE_PSRTYPE_IPV6HDR | |
1845 | IXGBE_PSRTYPE_L2HDR; | |
e8e26350 PW |
1846 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype); |
1847 | } | |
9a799d71 | 1848 | } else { |
f8212f97 AD |
1849 | if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) && |
1850 | (netdev->mtu <= ETH_DATA_LEN)) | |
7c6e0a43 | 1851 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 1852 | else |
7c6e0a43 | 1853 | rx_buf_len = ALIGN(max_frame, 1024); |
9a799d71 AK |
1854 | } |
1855 | ||
1856 | fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); | |
1857 | fctrl |= IXGBE_FCTRL_BAM; | |
021230d4 | 1858 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ |
e8e26350 | 1859 | fctrl |= IXGBE_FCTRL_PMCF; |
9a799d71 AK |
1860 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl); |
1861 | ||
1862 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
1863 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
1864 | hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; | |
1865 | else | |
1866 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
63f39bd1 YZ |
1867 | #ifdef IXGBE_FCOE |
1868 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
1869 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
1870 | #endif | |
9a799d71 AK |
1871 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); |
1872 | ||
9a799d71 AK |
1873 | rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc); |
1874 | /* disable receives while setting up the descriptors */ | |
1875 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
1876 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
1877 | ||
1878 | /* Setup the HW Rx Head and Tail Descriptor Pointers and | |
1879 | * the Base and Length of the Rx Descriptor Ring */ | |
1880 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1881 | rdba = adapter->rx_ring[i].dma; | |
7c6e0a43 | 1882 | j = adapter->rx_ring[i].reg_idx; |
284901a9 | 1883 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32))); |
7c6e0a43 JB |
1884 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); |
1885 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen); | |
1886 | IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); | |
1887 | IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); | |
1888 | adapter->rx_ring[i].head = IXGBE_RDH(j); | |
1889 | adapter->rx_ring[i].tail = IXGBE_RDT(j); | |
1890 | adapter->rx_ring[i].rx_buf_len = rx_buf_len; | |
cc41ac7c | 1891 | |
63f39bd1 YZ |
1892 | #ifdef IXGBE_FCOE |
1893 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
1894 | struct ixgbe_ring_feature *f; | |
1895 | f = &adapter->ring_feature[RING_F_FCOE]; | |
1896 | if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) && | |
1897 | (i >= f->mask) && (i < f->mask + f->indices)) | |
1898 | adapter->rx_ring[i].rx_buf_len = | |
1899 | IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
1900 | } | |
1901 | ||
1902 | #endif /* IXGBE_FCOE */ | |
cc41ac7c | 1903 | ixgbe_configure_srrctl(adapter, j); |
9a799d71 AK |
1904 | } |
1905 | ||
e8e26350 PW |
1906 | if (hw->mac.type == ixgbe_mac_82598EB) { |
1907 | /* | |
1908 | * For VMDq support of different descriptor types or | |
1909 | * buffer sizes through the use of multiple SRRCTL | |
1910 | * registers, RDRXCTL.MVMEN must be set to 1 | |
1911 | * | |
1912 | * also, the manual doesn't mention it clearly but DCA hints | |
1913 | * will only use queue 0's tags unless this bit is set. Side | |
1914 | * effects of setting this bit are only that SRRCTL must be | |
1915 | * fully programmed [0..15] | |
1916 | */ | |
2a41ff81 JB |
1917 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); |
1918 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
1919 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
2f90b865 | 1920 | } |
177db6ff | 1921 | |
e8e26350 PW |
1922 | /* Program MRQC for the distribution of queues */ |
1923 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
1924 | int mask = adapter->flags & ( | |
1925 | IXGBE_FLAG_RSS_ENABLED | |
1926 | | IXGBE_FLAG_DCB_ENABLED | |
1927 | ); | |
1928 | ||
1929 | switch (mask) { | |
1930 | case (IXGBE_FLAG_RSS_ENABLED): | |
1931 | mrqc = IXGBE_MRQC_RSSEN; | |
1932 | break; | |
1933 | case (IXGBE_FLAG_DCB_ENABLED): | |
1934 | mrqc = IXGBE_MRQC_RT8TCEN; | |
1935 | break; | |
1936 | default: | |
1937 | break; | |
1938 | } | |
1939 | } | |
021230d4 | 1940 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
9a799d71 | 1941 | /* Fill out redirection table */ |
021230d4 AV |
1942 | for (i = 0, j = 0; i < 128; i++, j++) { |
1943 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
1944 | j = 0; | |
1945 | /* reta = 4-byte sliding window of | |
1946 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
1947 | reta = (reta << 8) | (j * 0x11); | |
1948 | if ((i & 3) == 3) | |
1949 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
9a799d71 AK |
1950 | } |
1951 | ||
1952 | /* Fill out hash function seeds */ | |
1953 | for (i = 0; i < 10; i++) | |
7c6e0a43 | 1954 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); |
9a799d71 | 1955 | |
2a41ff81 JB |
1956 | if (hw->mac.type == ixgbe_mac_82598EB) |
1957 | mrqc |= IXGBE_MRQC_RSSEN; | |
9a799d71 | 1958 | /* Perform hash on these packet types */ |
2a41ff81 JB |
1959 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
1960 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
1961 | | IXGBE_MRQC_RSS_FIELD_IPV4_UDP | |
1962 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
1963 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP | |
1964 | | IXGBE_MRQC_RSS_FIELD_IPV6_UDP; | |
021230d4 | 1965 | } |
2a41ff81 | 1966 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
9a799d71 | 1967 | |
021230d4 AV |
1968 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); |
1969 | ||
1970 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED || | |
1971 | adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) { | |
1972 | /* Disable indicating checksum in descriptor, enables | |
1973 | * RSS hash */ | |
9a799d71 | 1974 | rxcsum |= IXGBE_RXCSUM_PCSD; |
9a799d71 | 1975 | } |
021230d4 AV |
1976 | if (!(rxcsum & IXGBE_RXCSUM_PCSD)) { |
1977 | /* Enable IPv4 payload checksum for UDP fragments | |
1978 | * if PCSD is not set */ | |
1979 | rxcsum |= IXGBE_RXCSUM_IPPCSE; | |
1980 | } | |
1981 | ||
1982 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
e8e26350 PW |
1983 | |
1984 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
1985 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
1986 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
f8212f97 | 1987 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; |
e8e26350 PW |
1988 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); |
1989 | } | |
f8212f97 AD |
1990 | |
1991 | if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) { | |
1992 | /* Enable 82599 HW-RSC */ | |
1993 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1994 | j = adapter->rx_ring[i].reg_idx; | |
1995 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j)); | |
1996 | rscctrl |= IXGBE_RSCCTL_RSCEN; | |
1997 | /* | |
1998 | * if packet split is enabled we can only support up | |
1999 | * to max frags + 1 descriptors. | |
2000 | */ | |
2001 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) | |
2002 | #if (MAX_SKB_FRAGS < 3) | |
2003 | rscctrl |= IXGBE_RSCCTL_MAXDESC_1; | |
2004 | #elif (MAX_SKB_FRAGS < 7) | |
2005 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2006 | #elif (MAX_SKB_FRAGS < 15) | |
2007 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2008 | #else | |
2009 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2010 | #endif | |
2011 | else | |
2012 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2013 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl); | |
2014 | } | |
2015 | /* Disable RSC for ACK packets */ | |
2016 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
2017 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
2018 | } | |
9a799d71 AK |
2019 | } |
2020 | ||
068c89b0 DS |
2021 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
2022 | { | |
2023 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2024 | struct ixgbe_hw *hw = &adapter->hw; | |
2025 | ||
2026 | /* add VID to filter table */ | |
2027 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true); | |
2028 | } | |
2029 | ||
2030 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
2031 | { | |
2032 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2033 | struct ixgbe_hw *hw = &adapter->hw; | |
2034 | ||
2035 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2036 | ixgbe_irq_disable(adapter); | |
2037 | ||
2038 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
2039 | ||
2040 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2041 | ixgbe_irq_enable(adapter); | |
2042 | ||
2043 | /* remove VID from filter table */ | |
2044 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false); | |
2045 | } | |
2046 | ||
9a799d71 | 2047 | static void ixgbe_vlan_rx_register(struct net_device *netdev, |
b4617240 | 2048 | struct vlan_group *grp) |
9a799d71 AK |
2049 | { |
2050 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2051 | u32 ctrl; | |
e8e26350 | 2052 | int i, j; |
9a799d71 | 2053 | |
d4f80882 AV |
2054 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2055 | ixgbe_irq_disable(adapter); | |
9a799d71 AK |
2056 | adapter->vlgrp = grp; |
2057 | ||
2f90b865 AD |
2058 | /* |
2059 | * For a DCB driver, always enable VLAN tag stripping so we can | |
2060 | * still receive traffic from a DCB-enabled host even if we're | |
2061 | * not in DCB mode. | |
2062 | */ | |
2063 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
2064 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
2065 | ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2066 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2067 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
2068 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
2069 | ctrl |= IXGBE_VLNCTRL_VFE; | |
9a799d71 AK |
2070 | /* enable VLAN tag insert/strip */ |
2071 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
9a799d71 AK |
2072 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; |
2073 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
e8e26350 PW |
2074 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2075 | j = adapter->rx_ring[i].reg_idx; | |
2076 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j)); | |
2077 | ctrl |= IXGBE_RXDCTL_VME; | |
2078 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl); | |
2079 | } | |
9a799d71 | 2080 | } |
e8e26350 | 2081 | ixgbe_vlan_rx_add_vid(netdev, 0); |
9a799d71 | 2082 | |
d4f80882 AV |
2083 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2084 | ixgbe_irq_enable(adapter); | |
9a799d71 AK |
2085 | } |
2086 | ||
9a799d71 AK |
2087 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
2088 | { | |
2089 | ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
2090 | ||
2091 | if (adapter->vlgrp) { | |
2092 | u16 vid; | |
2093 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
2094 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
2095 | continue; | |
2096 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
2097 | } | |
2098 | } | |
2099 | } | |
2100 | ||
2c5645cf CL |
2101 | static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq) |
2102 | { | |
2103 | struct dev_mc_list *mc_ptr; | |
2104 | u8 *addr = *mc_addr_ptr; | |
2105 | *vmdq = 0; | |
2106 | ||
2107 | mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]); | |
2108 | if (mc_ptr->next) | |
2109 | *mc_addr_ptr = mc_ptr->next->dmi_addr; | |
2110 | else | |
2111 | *mc_addr_ptr = NULL; | |
2112 | ||
2113 | return addr; | |
2114 | } | |
2115 | ||
9a799d71 | 2116 | /** |
2c5645cf | 2117 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
2118 | * @netdev: network interface device structure |
2119 | * | |
2c5645cf CL |
2120 | * The set_rx_method entry point is called whenever the unicast/multicast |
2121 | * address list or the network interface flags are updated. This routine is | |
2122 | * responsible for configuring the hardware for proper unicast, multicast and | |
2123 | * promiscuous mode. | |
9a799d71 | 2124 | **/ |
2c5645cf | 2125 | static void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
2126 | { |
2127 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2128 | struct ixgbe_hw *hw = &adapter->hw; | |
3d01625a | 2129 | u32 fctrl, vlnctrl; |
2c5645cf CL |
2130 | u8 *addr_list = NULL; |
2131 | int addr_count = 0; | |
9a799d71 AK |
2132 | |
2133 | /* Check for Promiscuous and All Multicast modes */ | |
2134 | ||
2135 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3d01625a | 2136 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
9a799d71 AK |
2137 | |
2138 | if (netdev->flags & IFF_PROMISC) { | |
2c5645cf | 2139 | hw->addr_ctrl.user_set_promisc = 1; |
9a799d71 | 2140 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
3d01625a | 2141 | vlnctrl &= ~IXGBE_VLNCTRL_VFE; |
9a799d71 | 2142 | } else { |
746b9f02 PM |
2143 | if (netdev->flags & IFF_ALLMULTI) { |
2144 | fctrl |= IXGBE_FCTRL_MPE; | |
2145 | fctrl &= ~IXGBE_FCTRL_UPE; | |
2146 | } else { | |
2147 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
2148 | } | |
3d01625a | 2149 | vlnctrl |= IXGBE_VLNCTRL_VFE; |
2c5645cf | 2150 | hw->addr_ctrl.user_set_promisc = 0; |
9a799d71 AK |
2151 | } |
2152 | ||
2153 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3d01625a | 2154 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
9a799d71 | 2155 | |
2c5645cf CL |
2156 | /* reprogram secondary unicast list */ |
2157 | addr_count = netdev->uc_count; | |
2158 | if (addr_count) | |
2159 | addr_list = netdev->uc_list->dmi_addr; | |
c44ade9e JB |
2160 | hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count, |
2161 | ixgbe_addr_list_itr); | |
9a799d71 | 2162 | |
2c5645cf CL |
2163 | /* reprogram multicast list */ |
2164 | addr_count = netdev->mc_count; | |
2165 | if (addr_count) | |
2166 | addr_list = netdev->mc_list->dmi_addr; | |
c44ade9e JB |
2167 | hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count, |
2168 | ixgbe_addr_list_itr); | |
9a799d71 AK |
2169 | } |
2170 | ||
021230d4 AV |
2171 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
2172 | { | |
2173 | int q_idx; | |
2174 | struct ixgbe_q_vector *q_vector; | |
2175 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2176 | ||
2177 | /* legacy and MSI only use one vector */ | |
2178 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2179 | q_vectors = 1; | |
2180 | ||
2181 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 2182 | struct napi_struct *napi; |
7a921c93 | 2183 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
2184 | if (!q_vector->rxr_count) |
2185 | continue; | |
f0848276 JB |
2186 | napi = &q_vector->napi; |
2187 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) && | |
2188 | (q_vector->rxr_count > 1)) | |
2189 | napi->poll = &ixgbe_clean_rxonly_many; | |
2190 | ||
2191 | napi_enable(napi); | |
021230d4 AV |
2192 | } |
2193 | } | |
2194 | ||
2195 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
2196 | { | |
2197 | int q_idx; | |
2198 | struct ixgbe_q_vector *q_vector; | |
2199 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2200 | ||
2201 | /* legacy and MSI only use one vector */ | |
2202 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2203 | q_vectors = 1; | |
2204 | ||
2205 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 2206 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
2207 | if (!q_vector->rxr_count) |
2208 | continue; | |
2209 | napi_disable(&q_vector->napi); | |
2210 | } | |
2211 | } | |
2212 | ||
7a6b6f51 | 2213 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2214 | /* |
2215 | * ixgbe_configure_dcb - Configure DCB hardware | |
2216 | * @adapter: ixgbe adapter struct | |
2217 | * | |
2218 | * This is called by the driver on open to configure the DCB hardware. | |
2219 | * This is also called by the gennetlink interface when reconfiguring | |
2220 | * the DCB state. | |
2221 | */ | |
2222 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
2223 | { | |
2224 | struct ixgbe_hw *hw = &adapter->hw; | |
2225 | u32 txdctl, vlnctrl; | |
2226 | int i, j; | |
2227 | ||
2228 | ixgbe_dcb_check_config(&adapter->dcb_cfg); | |
2229 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG); | |
2230 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG); | |
2231 | ||
2232 | /* reconfigure the hardware */ | |
2233 | ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg); | |
2234 | ||
2235 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2236 | j = adapter->tx_ring[i].reg_idx; | |
2237 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2238 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
2239 | txdctl |= 32; | |
2240 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); | |
2241 | } | |
2242 | /* Enable VLAN tag insert/strip */ | |
2243 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
2244 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2245 | vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2246 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2247 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2248 | } else if (hw->mac.type == ixgbe_mac_82599EB) { | |
2249 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
2250 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2251 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2252 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2253 | j = adapter->rx_ring[i].reg_idx; | |
2254 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2255 | vlnctrl |= IXGBE_RXDCTL_VME; | |
2256 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
2257 | } | |
2258 | } | |
2f90b865 AD |
2259 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
2260 | } | |
2261 | ||
2262 | #endif | |
9a799d71 AK |
2263 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
2264 | { | |
2265 | struct net_device *netdev = adapter->netdev; | |
2266 | int i; | |
2267 | ||
2c5645cf | 2268 | ixgbe_set_rx_mode(netdev); |
9a799d71 AK |
2269 | |
2270 | ixgbe_restore_vlan(adapter); | |
7a6b6f51 | 2271 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2272 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
2273 | netif_set_gso_max_size(netdev, 32768); | |
2274 | ixgbe_configure_dcb(adapter); | |
2275 | } else { | |
2276 | netif_set_gso_max_size(netdev, 65536); | |
2277 | } | |
2278 | #else | |
2279 | netif_set_gso_max_size(netdev, 65536); | |
2280 | #endif | |
9a799d71 | 2281 | |
eacd73f7 YZ |
2282 | #ifdef IXGBE_FCOE |
2283 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
2284 | ixgbe_configure_fcoe(adapter); | |
2285 | ||
2286 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
2287 | ixgbe_configure_tx(adapter); |
2288 | ixgbe_configure_rx(adapter); | |
2289 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2290 | ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i], | |
b4617240 | 2291 | (adapter->rx_ring[i].count - 1)); |
9a799d71 AK |
2292 | } |
2293 | ||
e8e26350 PW |
2294 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
2295 | { | |
2296 | switch (hw->phy.type) { | |
2297 | case ixgbe_phy_sfp_avago: | |
2298 | case ixgbe_phy_sfp_ftl: | |
2299 | case ixgbe_phy_sfp_intel: | |
2300 | case ixgbe_phy_sfp_unknown: | |
2301 | case ixgbe_phy_tw_tyco: | |
2302 | case ixgbe_phy_tw_unknown: | |
2303 | return true; | |
2304 | default: | |
2305 | return false; | |
2306 | } | |
2307 | } | |
2308 | ||
0ecc061d | 2309 | /** |
e8e26350 PW |
2310 | * ixgbe_sfp_link_config - set up SFP+ link |
2311 | * @adapter: pointer to private adapter struct | |
2312 | **/ | |
2313 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
2314 | { | |
2315 | struct ixgbe_hw *hw = &adapter->hw; | |
2316 | ||
2317 | if (hw->phy.multispeed_fiber) { | |
2318 | /* | |
2319 | * In multispeed fiber setups, the device may not have | |
2320 | * had a physical connection when the driver loaded. | |
2321 | * If that's the case, the initial link configuration | |
2322 | * couldn't get the MAC into 10G or 1G mode, so we'll | |
2323 | * never have a link status change interrupt fire. | |
2324 | * We need to try and force an autonegotiation | |
2325 | * session, then bring up link. | |
2326 | */ | |
2327 | hw->mac.ops.setup_sfp(hw); | |
2328 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) | |
2329 | schedule_work(&adapter->multispeed_fiber_task); | |
2330 | } else { | |
2331 | /* | |
2332 | * Direct Attach Cu and non-multispeed fiber modules | |
2333 | * still need to be configured properly prior to | |
2334 | * attempting link. | |
2335 | */ | |
2336 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK)) | |
2337 | schedule_work(&adapter->sfp_config_module_task); | |
2338 | } | |
2339 | } | |
2340 | ||
2341 | /** | |
2342 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
2343 | * @hw: pointer to private hardware struct |
2344 | * | |
2345 | * Returns 0 on success, negative on failure | |
2346 | **/ | |
e8e26350 | 2347 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
2348 | { |
2349 | u32 autoneg; | |
2350 | bool link_up = false; | |
2351 | u32 ret = IXGBE_ERR_LINK_SETUP; | |
2352 | ||
2353 | if (hw->mac.ops.check_link) | |
2354 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
2355 | ||
2356 | if (ret) | |
2357 | goto link_cfg_out; | |
2358 | ||
2359 | if (hw->mac.ops.get_link_capabilities) | |
2360 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, | |
2361 | &hw->mac.autoneg); | |
2362 | if (ret) | |
2363 | goto link_cfg_out; | |
2364 | ||
2365 | if (hw->mac.ops.setup_link_speed) | |
2366 | ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up); | |
0ecc061d PWJ |
2367 | link_cfg_out: |
2368 | return ret; | |
2369 | } | |
2370 | ||
e8e26350 PW |
2371 | #define IXGBE_MAX_RX_DESC_POLL 10 |
2372 | static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2373 | int rxr) | |
2374 | { | |
2375 | int j = adapter->rx_ring[rxr].reg_idx; | |
2376 | int k; | |
2377 | ||
2378 | for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) { | |
2379 | if (IXGBE_READ_REG(&adapter->hw, | |
2380 | IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE) | |
2381 | break; | |
2382 | else | |
2383 | msleep(1); | |
2384 | } | |
2385 | if (k >= IXGBE_MAX_RX_DESC_POLL) { | |
2386 | DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d " | |
2387 | "not set within the polling period\n", rxr); | |
2388 | } | |
2389 | ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr], | |
2390 | (adapter->rx_ring[rxr].count - 1)); | |
2391 | } | |
2392 | ||
9a799d71 AK |
2393 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) |
2394 | { | |
2395 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 2396 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 2397 | int i, j = 0; |
e8e26350 | 2398 | int num_rx_rings = adapter->num_rx_queues; |
0ecc061d | 2399 | int err; |
9a799d71 | 2400 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 | 2401 | u32 txdctl, rxdctl, mhadd; |
e8e26350 | 2402 | u32 dmatxctl; |
021230d4 | 2403 | u32 gpie; |
9a799d71 | 2404 | |
5eba3699 AV |
2405 | ixgbe_get_hw_control(adapter); |
2406 | ||
021230d4 AV |
2407 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) || |
2408 | (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) { | |
9a799d71 AK |
2409 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2410 | gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME | | |
b4617240 | 2411 | IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD); |
9a799d71 AK |
2412 | } else { |
2413 | /* MSI only */ | |
021230d4 | 2414 | gpie = 0; |
9a799d71 | 2415 | } |
021230d4 AV |
2416 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
2417 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
2418 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
9a799d71 AK |
2419 | } |
2420 | ||
021230d4 AV |
2421 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
2422 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, | |
2423 | * specifically only auto mask tx and rx interrupts */ | |
2424 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
2425 | } | |
9a799d71 | 2426 | |
0befdb3e JB |
2427 | /* Enable fan failure interrupt if media type is copper */ |
2428 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2429 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2430 | gpie |= IXGBE_SDP1_GPIEN; | |
2431 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2432 | } | |
2433 | ||
e8e26350 PW |
2434 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2435 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2436 | gpie |= IXGBE_SDP1_GPIEN; | |
2437 | gpie |= IXGBE_SDP2_GPIEN; | |
2438 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2439 | } | |
2440 | ||
63f39bd1 YZ |
2441 | #ifdef IXGBE_FCOE |
2442 | /* adjust max frame to be able to do baby jumbo for FCoE */ | |
2443 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
2444 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
2445 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
2446 | ||
2447 | #endif /* IXGBE_FCOE */ | |
021230d4 | 2448 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
9a799d71 AK |
2449 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { |
2450 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
2451 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
2452 | ||
2453 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
2454 | } | |
2455 | ||
2456 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
021230d4 AV |
2457 | j = adapter->tx_ring[i].reg_idx; |
2458 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
e01c31a5 JB |
2459 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ |
2460 | txdctl |= (8 << 16); | |
e8e26350 PW |
2461 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
2462 | } | |
2463 | ||
2464 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2465 | /* DMATXCTL.EN must be set after all Tx queue config is done */ | |
2466 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2467 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2468 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2469 | } | |
2470 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2471 | j = adapter->tx_ring[i].reg_idx; | |
2472 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
9a799d71 | 2473 | txdctl |= IXGBE_TXDCTL_ENABLE; |
021230d4 | 2474 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
9a799d71 AK |
2475 | } |
2476 | ||
e8e26350 | 2477 | for (i = 0; i < num_rx_rings; i++) { |
021230d4 AV |
2478 | j = adapter->rx_ring[i].reg_idx; |
2479 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2480 | /* enable PTHRESH=32 descriptors (half the internal cache) | |
2481 | * and HTHRESH=0 descriptors (to minimize latency on fetch), | |
2482 | * this also removes a pesky rx_no_buffer_count increment */ | |
2483 | rxdctl |= 0x0020; | |
9a799d71 | 2484 | rxdctl |= IXGBE_RXDCTL_ENABLE; |
021230d4 | 2485 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl); |
e8e26350 PW |
2486 | if (hw->mac.type == ixgbe_mac_82599EB) |
2487 | ixgbe_rx_desc_queue_enable(adapter, i); | |
9a799d71 AK |
2488 | } |
2489 | /* enable all receives */ | |
2490 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
e8e26350 PW |
2491 | if (hw->mac.type == ixgbe_mac_82598EB) |
2492 | rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN); | |
2493 | else | |
2494 | rxdctl |= IXGBE_RXCTRL_RXEN; | |
2495 | hw->mac.ops.enable_rx_dma(hw, rxdctl); | |
9a799d71 AK |
2496 | |
2497 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
2498 | ixgbe_configure_msix(adapter); | |
2499 | else | |
2500 | ixgbe_configure_msi_and_legacy(adapter); | |
2501 | ||
2502 | clear_bit(__IXGBE_DOWN, &adapter->state); | |
021230d4 AV |
2503 | ixgbe_napi_enable_all(adapter); |
2504 | ||
2505 | /* clear any pending interrupts, may auto mask */ | |
2506 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
2507 | ||
9a799d71 AK |
2508 | ixgbe_irq_enable(adapter); |
2509 | ||
bf069c97 DS |
2510 | /* |
2511 | * If this adapter has a fan, check to see if we had a failure | |
2512 | * before we enabled the interrupt. | |
2513 | */ | |
2514 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2515 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
2516 | if (esdp & IXGBE_ESDP_SDP1) | |
2517 | DPRINTK(DRV, CRIT, | |
2518 | "Fan has stopped, replace the adapter\n"); | |
2519 | } | |
2520 | ||
e8e26350 PW |
2521 | /* |
2522 | * For hot-pluggable SFP+ devices, a new SFP+ module may have | |
2523 | * arrived before interrupts were enabled. We need to kick off | |
2524 | * the SFP+ module setup first, then try to bring up link. | |
2525 | * If we're not hot-pluggable SFP+, we just need to configure link | |
2526 | * and bring it up. | |
2527 | */ | |
2528 | err = hw->phy.ops.identify(hw); | |
2529 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
2530 | DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err); | |
2531 | ixgbe_down(adapter); | |
2532 | return err; | |
2533 | } | |
2534 | ||
2535 | if (ixgbe_is_sfp(hw)) { | |
2536 | ixgbe_sfp_link_config(adapter); | |
2537 | } else { | |
2538 | err = ixgbe_non_sfp_link_config(hw); | |
2539 | if (err) | |
2540 | DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err); | |
2541 | } | |
0ecc061d | 2542 | |
1da100bb PWJ |
2543 | /* enable transmits */ |
2544 | netif_tx_start_all_queues(netdev); | |
2545 | ||
9a799d71 AK |
2546 | /* bring the link up in the watchdog, this could race with our first |
2547 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
2548 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
2549 | adapter->link_check_timeout = jiffies; | |
9a799d71 AK |
2550 | mod_timer(&adapter->watchdog_timer, jiffies); |
2551 | return 0; | |
2552 | } | |
2553 | ||
d4f80882 AV |
2554 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
2555 | { | |
2556 | WARN_ON(in_interrupt()); | |
2557 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
2558 | msleep(1); | |
2559 | ixgbe_down(adapter); | |
2560 | ixgbe_up(adapter); | |
2561 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
2562 | } | |
2563 | ||
9a799d71 AK |
2564 | int ixgbe_up(struct ixgbe_adapter *adapter) |
2565 | { | |
2566 | /* hardware has been reset, we need to reload some things */ | |
2567 | ixgbe_configure(adapter); | |
2568 | ||
2569 | return ixgbe_up_complete(adapter); | |
2570 | } | |
2571 | ||
2572 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
2573 | { | |
c44ade9e JB |
2574 | struct ixgbe_hw *hw = &adapter->hw; |
2575 | if (hw->mac.ops.init_hw(hw)) | |
2576 | dev_err(&adapter->pdev->dev, "Hardware Error\n"); | |
9a799d71 AK |
2577 | |
2578 | /* reprogram the RAR[0] in case user changed it. */ | |
c44ade9e | 2579 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
2580 | |
2581 | } | |
2582 | ||
9a799d71 AK |
2583 | /** |
2584 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
2585 | * @adapter: board private structure | |
2586 | * @rx_ring: ring to free buffers from | |
2587 | **/ | |
2588 | static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2589 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
2590 | { |
2591 | struct pci_dev *pdev = adapter->pdev; | |
2592 | unsigned long size; | |
2593 | unsigned int i; | |
2594 | ||
2595 | /* Free all the Rx ring sk_buffs */ | |
2596 | ||
2597 | for (i = 0; i < rx_ring->count; i++) { | |
2598 | struct ixgbe_rx_buffer *rx_buffer_info; | |
2599 | ||
2600 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
2601 | if (rx_buffer_info->dma) { | |
2602 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
b4617240 PW |
2603 | rx_ring->rx_buf_len, |
2604 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
2605 | rx_buffer_info->dma = 0; |
2606 | } | |
2607 | if (rx_buffer_info->skb) { | |
f8212f97 | 2608 | struct sk_buff *skb = rx_buffer_info->skb; |
9a799d71 | 2609 | rx_buffer_info->skb = NULL; |
f8212f97 AD |
2610 | do { |
2611 | struct sk_buff *this = skb; | |
2612 | skb = skb->prev; | |
2613 | dev_kfree_skb(this); | |
2614 | } while (skb); | |
9a799d71 AK |
2615 | } |
2616 | if (!rx_buffer_info->page) | |
2617 | continue; | |
762f4c57 JB |
2618 | pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2, |
2619 | PCI_DMA_FROMDEVICE); | |
9a799d71 | 2620 | rx_buffer_info->page_dma = 0; |
9a799d71 AK |
2621 | put_page(rx_buffer_info->page); |
2622 | rx_buffer_info->page = NULL; | |
762f4c57 | 2623 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
2624 | } |
2625 | ||
2626 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
2627 | memset(rx_ring->rx_buffer_info, 0, size); | |
2628 | ||
2629 | /* Zero out the descriptor ring */ | |
2630 | memset(rx_ring->desc, 0, rx_ring->size); | |
2631 | ||
2632 | rx_ring->next_to_clean = 0; | |
2633 | rx_ring->next_to_use = 0; | |
2634 | ||
9891ca7c JB |
2635 | if (rx_ring->head) |
2636 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
2637 | if (rx_ring->tail) | |
2638 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
9a799d71 AK |
2639 | } |
2640 | ||
2641 | /** | |
2642 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
2643 | * @adapter: board private structure | |
2644 | * @tx_ring: ring to be cleaned | |
2645 | **/ | |
2646 | static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2647 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
2648 | { |
2649 | struct ixgbe_tx_buffer *tx_buffer_info; | |
2650 | unsigned long size; | |
2651 | unsigned int i; | |
2652 | ||
2653 | /* Free all the Tx ring sk_buffs */ | |
2654 | ||
2655 | for (i = 0; i < tx_ring->count; i++) { | |
2656 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
2657 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
2658 | } | |
2659 | ||
2660 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
2661 | memset(tx_ring->tx_buffer_info, 0, size); | |
2662 | ||
2663 | /* Zero out the descriptor ring */ | |
2664 | memset(tx_ring->desc, 0, tx_ring->size); | |
2665 | ||
2666 | tx_ring->next_to_use = 0; | |
2667 | tx_ring->next_to_clean = 0; | |
2668 | ||
9891ca7c JB |
2669 | if (tx_ring->head) |
2670 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
2671 | if (tx_ring->tail) | |
2672 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
9a799d71 AK |
2673 | } |
2674 | ||
2675 | /** | |
021230d4 | 2676 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
2677 | * @adapter: board private structure |
2678 | **/ | |
021230d4 | 2679 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2680 | { |
2681 | int i; | |
2682 | ||
021230d4 AV |
2683 | for (i = 0; i < adapter->num_rx_queues; i++) |
2684 | ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
2685 | } |
2686 | ||
2687 | /** | |
021230d4 | 2688 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
2689 | * @adapter: board private structure |
2690 | **/ | |
021230d4 | 2691 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2692 | { |
2693 | int i; | |
2694 | ||
021230d4 AV |
2695 | for (i = 0; i < adapter->num_tx_queues; i++) |
2696 | ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
2697 | } |
2698 | ||
2699 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
2700 | { | |
2701 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 2702 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 2703 | u32 rxctrl; |
7f821875 JB |
2704 | u32 txdctl; |
2705 | int i, j; | |
9a799d71 AK |
2706 | |
2707 | /* signal that we are down to the interrupt handler */ | |
2708 | set_bit(__IXGBE_DOWN, &adapter->state); | |
2709 | ||
2710 | /* disable receives */ | |
7f821875 JB |
2711 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
2712 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 AK |
2713 | |
2714 | netif_tx_disable(netdev); | |
2715 | ||
7f821875 | 2716 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
2717 | msleep(10); |
2718 | ||
7f821875 JB |
2719 | netif_tx_stop_all_queues(netdev); |
2720 | ||
9a799d71 AK |
2721 | ixgbe_irq_disable(adapter); |
2722 | ||
021230d4 | 2723 | ixgbe_napi_disable_all(adapter); |
7f821875 | 2724 | |
9a799d71 | 2725 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 2726 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 2727 | |
7f821875 JB |
2728 | /* disable transmits in the hardware now that interrupts are off */ |
2729 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2730 | j = adapter->tx_ring[i].reg_idx; | |
2731 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2732 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), | |
2733 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); | |
2734 | } | |
88512539 PW |
2735 | /* Disable the Tx DMA engine on 82599 */ |
2736 | if (hw->mac.type == ixgbe_mac_82599EB) | |
2737 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, | |
2738 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & | |
2739 | ~IXGBE_DMATXCTL_TE)); | |
7f821875 | 2740 | |
9a799d71 | 2741 | netif_carrier_off(netdev); |
9a799d71 | 2742 | |
5dd2d332 | 2743 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 JB |
2744 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2745 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
2746 | dca_remove_requester(&adapter->pdev->dev); | |
2747 | } | |
2748 | ||
2749 | #endif | |
6f4a0e45 PL |
2750 | if (!pci_channel_offline(adapter->pdev)) |
2751 | ixgbe_reset(adapter); | |
9a799d71 AK |
2752 | ixgbe_clean_all_tx_rings(adapter); |
2753 | ixgbe_clean_all_rx_rings(adapter); | |
2754 | ||
5dd2d332 | 2755 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 JB |
2756 | /* since we reset the hardware DCA settings were cleared */ |
2757 | if (dca_add_requester(&adapter->pdev->dev) == 0) { | |
2758 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; | |
2759 | /* always use CB2 mode, difference is masked | |
2760 | * in the CB driver */ | |
b4617240 | 2761 | IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2); |
96b0e0f6 JB |
2762 | ixgbe_setup_dca(adapter); |
2763 | } | |
2764 | #endif | |
9a799d71 AK |
2765 | } |
2766 | ||
9a799d71 | 2767 | /** |
021230d4 AV |
2768 | * ixgbe_poll - NAPI Rx polling callback |
2769 | * @napi: structure for representing this polling device | |
2770 | * @budget: how many packets driver is allowed to clean | |
2771 | * | |
2772 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 2773 | **/ |
021230d4 | 2774 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 2775 | { |
9a1a69ad JB |
2776 | struct ixgbe_q_vector *q_vector = |
2777 | container_of(napi, struct ixgbe_q_vector, napi); | |
021230d4 | 2778 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a1a69ad | 2779 | int tx_clean_complete, work_done = 0; |
9a799d71 | 2780 | |
5dd2d332 | 2781 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
2782 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2783 | ixgbe_update_tx_dca(adapter, adapter->tx_ring); | |
2784 | ixgbe_update_rx_dca(adapter, adapter->rx_ring); | |
2785 | } | |
2786 | #endif | |
2787 | ||
9a1a69ad | 2788 | tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring); |
78b6f4ce | 2789 | ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget); |
9a799d71 | 2790 | |
9a1a69ad | 2791 | if (!tx_clean_complete) |
d2c7ddd6 DM |
2792 | work_done = budget; |
2793 | ||
53e52c72 DM |
2794 | /* If budget not fully consumed, exit the polling mode */ |
2795 | if (work_done < budget) { | |
288379f0 | 2796 | napi_complete(napi); |
509ee935 | 2797 | if (adapter->itr_setting & 1) |
f494e8fa | 2798 | ixgbe_set_itr(adapter); |
d4f80882 | 2799 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 2800 | ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2801 | } |
9a799d71 AK |
2802 | return work_done; |
2803 | } | |
2804 | ||
2805 | /** | |
2806 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
2807 | * @netdev: network interface device structure | |
2808 | **/ | |
2809 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
2810 | { | |
2811 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2812 | ||
2813 | /* Do the reset outside of interrupt context */ | |
2814 | schedule_work(&adapter->reset_task); | |
2815 | } | |
2816 | ||
2817 | static void ixgbe_reset_task(struct work_struct *work) | |
2818 | { | |
2819 | struct ixgbe_adapter *adapter; | |
2820 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
2821 | ||
2f90b865 AD |
2822 | /* If we're already down or resetting, just bail */ |
2823 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
2824 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
2825 | return; | |
2826 | ||
9a799d71 AK |
2827 | adapter->tx_timeout_count++; |
2828 | ||
d4f80882 | 2829 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
2830 | } |
2831 | ||
bc97114d PWJ |
2832 | #ifdef CONFIG_IXGBE_DCB |
2833 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
b9804972 | 2834 | { |
bc97114d | 2835 | bool ret = false; |
b9804972 | 2836 | |
bc97114d PWJ |
2837 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
2838 | adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3; | |
2839 | adapter->num_rx_queues = | |
2840 | adapter->ring_feature[RING_F_DCB].indices; | |
2841 | adapter->num_tx_queues = | |
2842 | adapter->ring_feature[RING_F_DCB].indices; | |
2843 | ret = true; | |
2844 | } else { | |
bc97114d PWJ |
2845 | ret = false; |
2846 | } | |
2f90b865 | 2847 | |
bc97114d PWJ |
2848 | return ret; |
2849 | } | |
2850 | #endif | |
2851 | ||
4df10466 JB |
2852 | /** |
2853 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
2854 | * @adapter: board private structure to initialize | |
2855 | * | |
2856 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
2857 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
2858 | * | |
2859 | **/ | |
bc97114d PWJ |
2860 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
2861 | { | |
2862 | bool ret = false; | |
2863 | ||
2864 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
2865 | adapter->ring_feature[RING_F_RSS].mask = 0xF; | |
2866 | adapter->num_rx_queues = | |
2867 | adapter->ring_feature[RING_F_RSS].indices; | |
2868 | adapter->num_tx_queues = | |
2869 | adapter->ring_feature[RING_F_RSS].indices; | |
2870 | ret = true; | |
2871 | } else { | |
bc97114d | 2872 | ret = false; |
b9804972 JB |
2873 | } |
2874 | ||
bc97114d PWJ |
2875 | return ret; |
2876 | } | |
2877 | ||
0331a832 YZ |
2878 | #ifdef IXGBE_FCOE |
2879 | /** | |
2880 | * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE) | |
2881 | * @adapter: board private structure to initialize | |
2882 | * | |
2883 | * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges. | |
2884 | * The ring feature mask is not used as a mask for FCoE, as it can take any 8 | |
2885 | * rx queues out of the max number of rx queues, instead, it is used as the | |
2886 | * index of the first rx queue used by FCoE. | |
2887 | * | |
2888 | **/ | |
2889 | static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter) | |
2890 | { | |
2891 | bool ret = false; | |
2892 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
2893 | ||
2894 | f->indices = min((int)num_online_cpus(), f->indices); | |
2895 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
2896 | #ifdef CONFIG_IXGBE_DCB | |
2897 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
2898 | DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n"); | |
2899 | ixgbe_set_dcb_queues(adapter); | |
2900 | } | |
2901 | #endif | |
2902 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
2903 | DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n"); | |
2904 | ixgbe_set_rss_queues(adapter); | |
2905 | } | |
2906 | /* adding FCoE rx rings to the end */ | |
2907 | f->mask = adapter->num_rx_queues; | |
2908 | adapter->num_rx_queues += f->indices; | |
2909 | if (adapter->num_tx_queues == 0) | |
2910 | adapter->num_tx_queues = f->indices; | |
2911 | ||
2912 | ret = true; | |
2913 | } | |
2914 | ||
2915 | return ret; | |
2916 | } | |
2917 | ||
2918 | #endif /* IXGBE_FCOE */ | |
4df10466 JB |
2919 | /* |
2920 | * ixgbe_set_num_queues: Allocate queues for device, feature dependant | |
2921 | * @adapter: board private structure to initialize | |
2922 | * | |
2923 | * This is the top level queue allocation routine. The order here is very | |
2924 | * important, starting with the "most" number of features turned on at once, | |
2925 | * and ending with the smallest set of features. This way large combinations | |
2926 | * can be allocated if they're turned on, and smaller combinations are the | |
2927 | * fallthrough conditions. | |
2928 | * | |
2929 | **/ | |
bc97114d PWJ |
2930 | static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
2931 | { | |
0331a832 YZ |
2932 | #ifdef IXGBE_FCOE |
2933 | if (ixgbe_set_fcoe_queues(adapter)) | |
2934 | goto done; | |
2935 | ||
2936 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
2937 | #ifdef CONFIG_IXGBE_DCB |
2938 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 2939 | goto done; |
bc97114d PWJ |
2940 | |
2941 | #endif | |
2942 | if (ixgbe_set_rss_queues(adapter)) | |
af22ab1b WF |
2943 | goto done; |
2944 | ||
2945 | /* fallback to base case */ | |
2946 | adapter->num_rx_queues = 1; | |
2947 | adapter->num_tx_queues = 1; | |
2948 | ||
2949 | done: | |
2950 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ | |
2951 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; | |
b9804972 JB |
2952 | } |
2953 | ||
021230d4 | 2954 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 2955 | int vectors) |
021230d4 AV |
2956 | { |
2957 | int err, vector_threshold; | |
2958 | ||
2959 | /* We'll want at least 3 (vector_threshold): | |
2960 | * 1) TxQ[0] Cleanup | |
2961 | * 2) RxQ[0] Cleanup | |
2962 | * 3) Other (Link Status Change, etc.) | |
2963 | * 4) TCP Timer (optional) | |
2964 | */ | |
2965 | vector_threshold = MIN_MSIX_COUNT; | |
2966 | ||
2967 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
2968 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
2969 | * Right now, we simply care about how many we'll get; we'll | |
2970 | * set them up later while requesting irq's. | |
2971 | */ | |
2972 | while (vectors >= vector_threshold) { | |
2973 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
b4617240 | 2974 | vectors); |
021230d4 AV |
2975 | if (!err) /* Success in acquiring all requested vectors. */ |
2976 | break; | |
2977 | else if (err < 0) | |
2978 | vectors = 0; /* Nasty failure, quit now */ | |
2979 | else /* err == number of vectors we should try again with */ | |
2980 | vectors = err; | |
2981 | } | |
2982 | ||
2983 | if (vectors < vector_threshold) { | |
2984 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
2985 | * This just means we'll go with either a single MSI | |
2986 | * vector or fall back to legacy interrupts. | |
2987 | */ | |
2988 | DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n"); | |
2989 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
2990 | kfree(adapter->msix_entries); | |
2991 | adapter->msix_entries = NULL; | |
021230d4 AV |
2992 | } else { |
2993 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
2994 | /* |
2995 | * Adjust for only the vectors we'll use, which is minimum | |
2996 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
2997 | * vectors we were allocated. | |
2998 | */ | |
2999 | adapter->num_msix_vectors = min(vectors, | |
3000 | adapter->max_msix_q_vectors + NON_Q_VECTORS); | |
021230d4 AV |
3001 | } |
3002 | } | |
3003 | ||
021230d4 | 3004 | /** |
bc97114d | 3005 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
3006 | * @adapter: board private structure to initialize |
3007 | * | |
bc97114d PWJ |
3008 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
3009 | * | |
021230d4 | 3010 | **/ |
bc97114d | 3011 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 3012 | { |
bc97114d PWJ |
3013 | int i; |
3014 | bool ret = false; | |
3015 | ||
3016 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
3017 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3018 | adapter->rx_ring[i].reg_idx = i; | |
3019 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3020 | adapter->tx_ring[i].reg_idx = i; | |
3021 | ret = true; | |
3022 | } else { | |
3023 | ret = false; | |
3024 | } | |
3025 | ||
3026 | return ret; | |
3027 | } | |
3028 | ||
3029 | #ifdef CONFIG_IXGBE_DCB | |
3030 | /** | |
3031 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
3032 | * @adapter: board private structure to initialize | |
3033 | * | |
3034 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
3035 | * | |
3036 | **/ | |
3037 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
3038 | { | |
3039 | int i; | |
3040 | bool ret = false; | |
3041 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
3042 | ||
3043 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
3044 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2f90b865 AD |
3045 | /* the number of queues is assumed to be symmetric */ |
3046 | for (i = 0; i < dcb_i; i++) { | |
3047 | adapter->rx_ring[i].reg_idx = i << 3; | |
3048 | adapter->tx_ring[i].reg_idx = i << 2; | |
3049 | } | |
bc97114d | 3050 | ret = true; |
e8e26350 | 3051 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
f92ef202 PW |
3052 | if (dcb_i == 8) { |
3053 | /* | |
3054 | * Tx TC0 starts at: descriptor queue 0 | |
3055 | * Tx TC1 starts at: descriptor queue 32 | |
3056 | * Tx TC2 starts at: descriptor queue 64 | |
3057 | * Tx TC3 starts at: descriptor queue 80 | |
3058 | * Tx TC4 starts at: descriptor queue 96 | |
3059 | * Tx TC5 starts at: descriptor queue 104 | |
3060 | * Tx TC6 starts at: descriptor queue 112 | |
3061 | * Tx TC7 starts at: descriptor queue 120 | |
3062 | * | |
3063 | * Rx TC0-TC7 are offset by 16 queues each | |
3064 | */ | |
3065 | for (i = 0; i < 3; i++) { | |
3066 | adapter->tx_ring[i].reg_idx = i << 5; | |
3067 | adapter->rx_ring[i].reg_idx = i << 4; | |
3068 | } | |
3069 | for ( ; i < 5; i++) { | |
3070 | adapter->tx_ring[i].reg_idx = | |
3071 | ((i + 2) << 4); | |
3072 | adapter->rx_ring[i].reg_idx = i << 4; | |
3073 | } | |
3074 | for ( ; i < dcb_i; i++) { | |
3075 | adapter->tx_ring[i].reg_idx = | |
3076 | ((i + 8) << 3); | |
3077 | adapter->rx_ring[i].reg_idx = i << 4; | |
3078 | } | |
3079 | ||
3080 | ret = true; | |
3081 | } else if (dcb_i == 4) { | |
3082 | /* | |
3083 | * Tx TC0 starts at: descriptor queue 0 | |
3084 | * Tx TC1 starts at: descriptor queue 64 | |
3085 | * Tx TC2 starts at: descriptor queue 96 | |
3086 | * Tx TC3 starts at: descriptor queue 112 | |
3087 | * | |
3088 | * Rx TC0-TC3 are offset by 32 queues each | |
3089 | */ | |
3090 | adapter->tx_ring[0].reg_idx = 0; | |
3091 | adapter->tx_ring[1].reg_idx = 64; | |
3092 | adapter->tx_ring[2].reg_idx = 96; | |
3093 | adapter->tx_ring[3].reg_idx = 112; | |
3094 | for (i = 0 ; i < dcb_i; i++) | |
3095 | adapter->rx_ring[i].reg_idx = i << 5; | |
3096 | ||
3097 | ret = true; | |
3098 | } else { | |
3099 | ret = false; | |
e8e26350 | 3100 | } |
bc97114d PWJ |
3101 | } else { |
3102 | ret = false; | |
021230d4 | 3103 | } |
bc97114d PWJ |
3104 | } else { |
3105 | ret = false; | |
021230d4 | 3106 | } |
bc97114d PWJ |
3107 | |
3108 | return ret; | |
3109 | } | |
3110 | #endif | |
3111 | ||
0331a832 YZ |
3112 | #ifdef IXGBE_FCOE |
3113 | /** | |
3114 | * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE | |
3115 | * @adapter: board private structure to initialize | |
3116 | * | |
3117 | * Cache the descriptor ring offsets for FCoE mode to the assigned rings. | |
3118 | * | |
3119 | */ | |
3120 | static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter) | |
3121 | { | |
3122 | int i, fcoe_i = 0; | |
3123 | bool ret = false; | |
3124 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
3125 | ||
3126 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
3127 | #ifdef CONFIG_IXGBE_DCB | |
3128 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
3129 | ixgbe_cache_ring_dcb(adapter); | |
3130 | fcoe_i = adapter->rx_ring[0].reg_idx + 1; | |
3131 | } | |
3132 | #endif /* CONFIG_IXGBE_DCB */ | |
3133 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
3134 | ixgbe_cache_ring_rss(adapter); | |
3135 | fcoe_i = f->mask; | |
3136 | } | |
3137 | for (i = 0; i < f->indices; i++, fcoe_i++) | |
3138 | adapter->rx_ring[f->mask + i].reg_idx = fcoe_i; | |
3139 | ret = true; | |
3140 | } | |
3141 | return ret; | |
3142 | } | |
3143 | ||
3144 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3145 | /** |
3146 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
3147 | * @adapter: board private structure to initialize | |
3148 | * | |
3149 | * Once we know the feature-set enabled for the device, we'll cache | |
3150 | * the register offset the descriptor ring is assigned to. | |
3151 | * | |
3152 | * Note, the order the various feature calls is important. It must start with | |
3153 | * the "most" features enabled at the same time, then trickle down to the | |
3154 | * least amount of features turned on at once. | |
3155 | **/ | |
3156 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
3157 | { | |
3158 | /* start with default case */ | |
3159 | adapter->rx_ring[0].reg_idx = 0; | |
3160 | adapter->tx_ring[0].reg_idx = 0; | |
3161 | ||
0331a832 YZ |
3162 | #ifdef IXGBE_FCOE |
3163 | if (ixgbe_cache_ring_fcoe(adapter)) | |
3164 | return; | |
3165 | ||
3166 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3167 | #ifdef CONFIG_IXGBE_DCB |
3168 | if (ixgbe_cache_ring_dcb(adapter)) | |
3169 | return; | |
3170 | ||
3171 | #endif | |
3172 | if (ixgbe_cache_ring_rss(adapter)) | |
3173 | return; | |
021230d4 AV |
3174 | } |
3175 | ||
9a799d71 AK |
3176 | /** |
3177 | * ixgbe_alloc_queues - Allocate memory for all rings | |
3178 | * @adapter: board private structure to initialize | |
3179 | * | |
3180 | * We allocate one ring per queue at run-time since we don't know the | |
4df10466 JB |
3181 | * number of queues at compile-time. The polling_netdev array is |
3182 | * intended for Multiqueue, but should work fine with a single queue. | |
9a799d71 | 3183 | **/ |
2f90b865 | 3184 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3185 | { |
3186 | int i; | |
3187 | ||
3188 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
b4617240 | 3189 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
9a799d71 | 3190 | if (!adapter->tx_ring) |
021230d4 | 3191 | goto err_tx_ring_allocation; |
9a799d71 AK |
3192 | |
3193 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
b4617240 | 3194 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
021230d4 AV |
3195 | if (!adapter->rx_ring) |
3196 | goto err_rx_ring_allocation; | |
9a799d71 | 3197 | |
021230d4 | 3198 | for (i = 0; i < adapter->num_tx_queues; i++) { |
b9804972 | 3199 | adapter->tx_ring[i].count = adapter->tx_ring_count; |
021230d4 AV |
3200 | adapter->tx_ring[i].queue_index = i; |
3201 | } | |
b9804972 | 3202 | |
9a799d71 | 3203 | for (i = 0; i < adapter->num_rx_queues; i++) { |
b9804972 | 3204 | adapter->rx_ring[i].count = adapter->rx_ring_count; |
021230d4 AV |
3205 | adapter->rx_ring[i].queue_index = i; |
3206 | } | |
3207 | ||
3208 | ixgbe_cache_ring_register(adapter); | |
3209 | ||
3210 | return 0; | |
3211 | ||
3212 | err_rx_ring_allocation: | |
3213 | kfree(adapter->tx_ring); | |
3214 | err_tx_ring_allocation: | |
3215 | return -ENOMEM; | |
3216 | } | |
3217 | ||
3218 | /** | |
3219 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
3220 | * @adapter: board private structure to initialize | |
3221 | * | |
3222 | * Attempt to configure the interrupts using the best available | |
3223 | * capabilities of the hardware and the kernel. | |
3224 | **/ | |
feea6a57 | 3225 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 3226 | { |
8be0e467 | 3227 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
3228 | int err = 0; |
3229 | int vector, v_budget; | |
3230 | ||
3231 | /* | |
3232 | * It's easy to be greedy for MSI-X vectors, but it really | |
3233 | * doesn't do us much good if we have a lot more vectors | |
3234 | * than CPU's. So let's be conservative and only ask for | |
3235 | * (roughly) twice the number of vectors as there are CPU's. | |
3236 | */ | |
3237 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
b4617240 | 3238 | (int)(num_online_cpus() * 2)) + NON_Q_VECTORS; |
021230d4 AV |
3239 | |
3240 | /* | |
3241 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
3242 | * hw.mac->max_msix_vectors vectors. With features |
3243 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
3244 | * descriptor queues supported by our device. Thus, we cap it off in | |
3245 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 3246 | */ |
8be0e467 | 3247 | v_budget = min(v_budget, (int)hw->mac.max_msix_vectors); |
021230d4 AV |
3248 | |
3249 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
3250 | * mean we disable MSI-X capabilities of the adapter. */ | |
3251 | adapter->msix_entries = kcalloc(v_budget, | |
b4617240 | 3252 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
3253 | if (adapter->msix_entries) { |
3254 | for (vector = 0; vector < v_budget; vector++) | |
3255 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 3256 | |
7a921c93 | 3257 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 3258 | |
7a921c93 AD |
3259 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3260 | goto out; | |
3261 | } | |
021230d4 | 3262 | |
7a921c93 AD |
3263 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
3264 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
3265 | ixgbe_set_num_queues(adapter); | |
021230d4 | 3266 | |
021230d4 AV |
3267 | err = pci_enable_msi(adapter->pdev); |
3268 | if (!err) { | |
3269 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
3270 | } else { | |
3271 | DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, " | |
b4617240 | 3272 | "falling back to legacy. Error: %d\n", err); |
021230d4 AV |
3273 | /* reset err */ |
3274 | err = 0; | |
3275 | } | |
3276 | ||
3277 | out: | |
021230d4 AV |
3278 | return err; |
3279 | } | |
3280 | ||
7a921c93 AD |
3281 | /** |
3282 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
3283 | * @adapter: board private structure to initialize | |
3284 | * | |
3285 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
3286 | * return -ENOMEM. | |
3287 | **/ | |
3288 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
3289 | { | |
3290 | int q_idx, num_q_vectors; | |
3291 | struct ixgbe_q_vector *q_vector; | |
3292 | int napi_vectors; | |
3293 | int (*poll)(struct napi_struct *, int); | |
3294 | ||
3295 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3296 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3297 | napi_vectors = adapter->num_rx_queues; | |
3298 | poll = &ixgbe_clean_rxonly; | |
3299 | } else { | |
3300 | num_q_vectors = 1; | |
3301 | napi_vectors = 1; | |
3302 | poll = &ixgbe_poll; | |
3303 | } | |
3304 | ||
3305 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
3306 | q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL); | |
3307 | if (!q_vector) | |
3308 | goto err_out; | |
3309 | q_vector->adapter = adapter; | |
3310 | q_vector->v_idx = q_idx; | |
3311 | q_vector->eitr = adapter->eitr_param; | |
3312 | if (q_idx < napi_vectors) | |
3313 | netif_napi_add(adapter->netdev, &q_vector->napi, | |
3314 | (*poll), 64); | |
3315 | adapter->q_vector[q_idx] = q_vector; | |
3316 | } | |
3317 | ||
3318 | return 0; | |
3319 | ||
3320 | err_out: | |
3321 | while (q_idx) { | |
3322 | q_idx--; | |
3323 | q_vector = adapter->q_vector[q_idx]; | |
3324 | netif_napi_del(&q_vector->napi); | |
3325 | kfree(q_vector); | |
3326 | adapter->q_vector[q_idx] = NULL; | |
3327 | } | |
3328 | return -ENOMEM; | |
3329 | } | |
3330 | ||
3331 | /** | |
3332 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
3333 | * @adapter: board private structure to initialize | |
3334 | * | |
3335 | * This function frees the memory allocated to the q_vectors. In addition if | |
3336 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
3337 | * to freeing the q_vector. | |
3338 | **/ | |
3339 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
3340 | { | |
3341 | int q_idx, num_q_vectors; | |
3342 | int napi_vectors; | |
3343 | ||
3344 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3345 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3346 | napi_vectors = adapter->num_rx_queues; | |
3347 | } else { | |
3348 | num_q_vectors = 1; | |
3349 | napi_vectors = 1; | |
3350 | } | |
3351 | ||
3352 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
3353 | struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx]; | |
3354 | ||
3355 | adapter->q_vector[q_idx] = NULL; | |
3356 | if (q_idx < napi_vectors) | |
3357 | netif_napi_del(&q_vector->napi); | |
3358 | kfree(q_vector); | |
3359 | } | |
3360 | } | |
3361 | ||
2f90b865 | 3362 | void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
3363 | { |
3364 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3365 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
3366 | pci_disable_msix(adapter->pdev); | |
3367 | kfree(adapter->msix_entries); | |
3368 | adapter->msix_entries = NULL; | |
3369 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
3370 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
3371 | pci_disable_msi(adapter->pdev); | |
3372 | } | |
3373 | return; | |
3374 | } | |
3375 | ||
3376 | /** | |
3377 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
3378 | * @adapter: board private structure to initialize | |
3379 | * | |
3380 | * We determine which interrupt scheme to use based on... | |
3381 | * - Kernel support (MSI, MSI-X) | |
3382 | * - which can be user-defined (via MODULE_PARAM) | |
3383 | * - Hardware queue count (num_*_queues) | |
3384 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
3385 | **/ | |
2f90b865 | 3386 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
3387 | { |
3388 | int err; | |
3389 | ||
3390 | /* Number of supported queues */ | |
3391 | ixgbe_set_num_queues(adapter); | |
3392 | ||
021230d4 AV |
3393 | err = ixgbe_set_interrupt_capability(adapter); |
3394 | if (err) { | |
3395 | DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n"); | |
3396 | goto err_set_interrupt; | |
9a799d71 AK |
3397 | } |
3398 | ||
7a921c93 AD |
3399 | err = ixgbe_alloc_q_vectors(adapter); |
3400 | if (err) { | |
3401 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queue " | |
3402 | "vectors\n"); | |
3403 | goto err_alloc_q_vectors; | |
3404 | } | |
3405 | ||
3406 | err = ixgbe_alloc_queues(adapter); | |
3407 | if (err) { | |
3408 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); | |
3409 | goto err_alloc_queues; | |
3410 | } | |
3411 | ||
021230d4 | 3412 | DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, " |
b4617240 PW |
3413 | "Tx Queue count = %u\n", |
3414 | (adapter->num_rx_queues > 1) ? "Enabled" : | |
3415 | "Disabled", adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
3416 | |
3417 | set_bit(__IXGBE_DOWN, &adapter->state); | |
3418 | ||
9a799d71 | 3419 | return 0; |
021230d4 | 3420 | |
7a921c93 AD |
3421 | err_alloc_queues: |
3422 | ixgbe_free_q_vectors(adapter); | |
3423 | err_alloc_q_vectors: | |
3424 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 3425 | err_set_interrupt: |
7a921c93 AD |
3426 | return err; |
3427 | } | |
3428 | ||
3429 | /** | |
3430 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
3431 | * @adapter: board private structure to clear interrupt scheme on | |
3432 | * | |
3433 | * We go through and clear interrupt specific resources and reset the structure | |
3434 | * to pre-load conditions | |
3435 | **/ | |
3436 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
3437 | { | |
021230d4 AV |
3438 | kfree(adapter->tx_ring); |
3439 | kfree(adapter->rx_ring); | |
7a921c93 AD |
3440 | adapter->tx_ring = NULL; |
3441 | adapter->rx_ring = NULL; | |
3442 | ||
3443 | ixgbe_free_q_vectors(adapter); | |
3444 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
3445 | } |
3446 | ||
c4900be0 DS |
3447 | /** |
3448 | * ixgbe_sfp_timer - worker thread to find a missing module | |
3449 | * @data: pointer to our adapter struct | |
3450 | **/ | |
3451 | static void ixgbe_sfp_timer(unsigned long data) | |
3452 | { | |
3453 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
3454 | ||
4df10466 JB |
3455 | /* |
3456 | * Do the sfp_timer outside of interrupt context due to the | |
c4900be0 DS |
3457 | * delays that sfp+ detection requires |
3458 | */ | |
3459 | schedule_work(&adapter->sfp_task); | |
3460 | } | |
3461 | ||
3462 | /** | |
3463 | * ixgbe_sfp_task - worker thread to find a missing module | |
3464 | * @work: pointer to work_struct containing our data | |
3465 | **/ | |
3466 | static void ixgbe_sfp_task(struct work_struct *work) | |
3467 | { | |
3468 | struct ixgbe_adapter *adapter = container_of(work, | |
3469 | struct ixgbe_adapter, | |
3470 | sfp_task); | |
3471 | struct ixgbe_hw *hw = &adapter->hw; | |
3472 | ||
3473 | if ((hw->phy.type == ixgbe_phy_nl) && | |
3474 | (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { | |
3475 | s32 ret = hw->phy.ops.identify_sfp(hw); | |
3476 | if (ret) | |
3477 | goto reschedule; | |
3478 | ret = hw->phy.ops.reset(hw); | |
3479 | if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
3480 | DPRINTK(PROBE, ERR, "failed to initialize because an " | |
3481 | "unsupported SFP+ module type was detected.\n" | |
3482 | "Reload the driver after installing a " | |
3483 | "supported module.\n"); | |
3484 | unregister_netdev(adapter->netdev); | |
3485 | } else { | |
3486 | DPRINTK(PROBE, INFO, "detected SFP+: %d\n", | |
3487 | hw->phy.sfp_type); | |
3488 | } | |
3489 | /* don't need this routine any more */ | |
3490 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
3491 | } | |
3492 | return; | |
3493 | reschedule: | |
3494 | if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) | |
3495 | mod_timer(&adapter->sfp_timer, | |
3496 | round_jiffies(jiffies + (2 * HZ))); | |
3497 | } | |
3498 | ||
9a799d71 AK |
3499 | /** |
3500 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
3501 | * @adapter: board private structure to initialize | |
3502 | * | |
3503 | * ixgbe_sw_init initializes the Adapter private data structure. | |
3504 | * Fields are initialized based on PCI device information and | |
3505 | * OS network device settings (MTU size). | |
3506 | **/ | |
3507 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
3508 | { | |
3509 | struct ixgbe_hw *hw = &adapter->hw; | |
3510 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 3511 | unsigned int rss; |
7a6b6f51 | 3512 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3513 | int j; |
3514 | struct tc_configuration *tc; | |
3515 | #endif | |
021230d4 | 3516 | |
c44ade9e JB |
3517 | /* PCI config space info */ |
3518 | ||
3519 | hw->vendor_id = pdev->vendor; | |
3520 | hw->device_id = pdev->device; | |
3521 | hw->revision_id = pdev->revision; | |
3522 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
3523 | hw->subsystem_device_id = pdev->subsystem_device; | |
3524 | ||
021230d4 AV |
3525 | /* Set capability flags */ |
3526 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
3527 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
3528 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 3529 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
bf069c97 DS |
3530 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3531 | if (hw->device_id == IXGBE_DEV_ID_82598AT) | |
3532 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 3533 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bf069c97 | 3534 | } else if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 3535 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
f8212f97 AD |
3536 | adapter->flags |= IXGBE_FLAG_RSC_CAPABLE; |
3537 | adapter->flags |= IXGBE_FLAG_RSC_ENABLED; | |
eacd73f7 YZ |
3538 | #ifdef IXGBE_FCOE |
3539 | adapter->flags |= IXGBE_FLAG_FCOE_ENABLED; | |
0331a832 | 3540 | adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE; |
eacd73f7 | 3541 | #endif /* IXGBE_FCOE */ |
f8212f97 | 3542 | } |
2f90b865 | 3543 | |
7a6b6f51 | 3544 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3545 | /* Configure DCB traffic classes */ |
3546 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
3547 | tc = &adapter->dcb_cfg.tc_config[j]; | |
3548 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
3549 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
3550 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
3551 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
3552 | tc->dcb_pfc = pfc_disabled; | |
3553 | } | |
3554 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
3555 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
3556 | adapter->dcb_cfg.rx_pba_cfg = pba_equal; | |
3557 | adapter->dcb_cfg.round_robin_enable = false; | |
3558 | adapter->dcb_set_bitmap = 0x00; | |
3559 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, | |
3560 | adapter->ring_feature[RING_F_DCB].indices); | |
3561 | ||
3562 | #endif | |
9a799d71 AK |
3563 | |
3564 | /* default flow control settings */ | |
cd7664f6 | 3565 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 3566 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
2b9ade93 JB |
3567 | hw->fc.high_water = IXGBE_DEFAULT_FCRTH; |
3568 | hw->fc.low_water = IXGBE_DEFAULT_FCRTL; | |
3569 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; | |
3570 | hw->fc.send_xon = true; | |
71fd570b | 3571 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 3572 | |
30efa5a3 JB |
3573 | /* enable itr by default in dynamic mode */ |
3574 | adapter->itr_setting = 1; | |
3575 | adapter->eitr_param = 20000; | |
3576 | ||
3577 | /* set defaults for eitr in MegaBytes */ | |
3578 | adapter->eitr_low = 10; | |
3579 | adapter->eitr_high = 20; | |
3580 | ||
3581 | /* set default ring sizes */ | |
3582 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
3583 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
3584 | ||
9a799d71 | 3585 | /* initialize eeprom parameters */ |
c44ade9e | 3586 | if (ixgbe_init_eeprom_params_generic(hw)) { |
9a799d71 AK |
3587 | dev_err(&pdev->dev, "EEPROM initialization failed\n"); |
3588 | return -EIO; | |
3589 | } | |
3590 | ||
021230d4 | 3591 | /* enable rx csum by default */ |
9a799d71 AK |
3592 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
3593 | ||
9a799d71 AK |
3594 | set_bit(__IXGBE_DOWN, &adapter->state); |
3595 | ||
3596 | return 0; | |
3597 | } | |
3598 | ||
3599 | /** | |
3600 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3601 | * @adapter: board private structure | |
3a581073 | 3602 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
3603 | * |
3604 | * Return 0 on success, negative on failure | |
3605 | **/ | |
3606 | int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter, | |
e01c31a5 | 3607 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
3608 | { |
3609 | struct pci_dev *pdev = adapter->pdev; | |
3610 | int size; | |
3611 | ||
3a581073 JB |
3612 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
3613 | tx_ring->tx_buffer_info = vmalloc(size); | |
e01c31a5 JB |
3614 | if (!tx_ring->tx_buffer_info) |
3615 | goto err; | |
3a581073 | 3616 | memset(tx_ring->tx_buffer_info, 0, size); |
9a799d71 AK |
3617 | |
3618 | /* round up to nearest 4K */ | |
12207e49 | 3619 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 3620 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 3621 | |
3a581073 JB |
3622 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, |
3623 | &tx_ring->dma); | |
e01c31a5 JB |
3624 | if (!tx_ring->desc) |
3625 | goto err; | |
9a799d71 | 3626 | |
3a581073 JB |
3627 | tx_ring->next_to_use = 0; |
3628 | tx_ring->next_to_clean = 0; | |
3629 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 3630 | return 0; |
e01c31a5 JB |
3631 | |
3632 | err: | |
3633 | vfree(tx_ring->tx_buffer_info); | |
3634 | tx_ring->tx_buffer_info = NULL; | |
3635 | DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit " | |
3636 | "descriptor ring\n"); | |
3637 | return -ENOMEM; | |
9a799d71 AK |
3638 | } |
3639 | ||
69888674 AD |
3640 | /** |
3641 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
3642 | * @adapter: board private structure | |
3643 | * | |
3644 | * If this function returns with an error, then it's possible one or | |
3645 | * more of the rings is populated (while the rest are not). It is the | |
3646 | * callers duty to clean those orphaned rings. | |
3647 | * | |
3648 | * Return 0 on success, negative on failure | |
3649 | **/ | |
3650 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
3651 | { | |
3652 | int i, err = 0; | |
3653 | ||
3654 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3655 | err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]); | |
3656 | if (!err) | |
3657 | continue; | |
3658 | DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i); | |
3659 | break; | |
3660 | } | |
3661 | ||
3662 | return err; | |
3663 | } | |
3664 | ||
9a799d71 AK |
3665 | /** |
3666 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3667 | * @adapter: board private structure | |
3a581073 | 3668 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
3669 | * |
3670 | * Returns 0 on success, negative on failure | |
3671 | **/ | |
3672 | int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, | |
b4617240 | 3673 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
3674 | { |
3675 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 3676 | int size; |
9a799d71 | 3677 | |
3a581073 JB |
3678 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
3679 | rx_ring->rx_buffer_info = vmalloc(size); | |
3680 | if (!rx_ring->rx_buffer_info) { | |
9a799d71 | 3681 | DPRINTK(PROBE, ERR, |
b4617240 | 3682 | "vmalloc allocation failed for the rx desc ring\n"); |
177db6ff | 3683 | goto alloc_failed; |
9a799d71 | 3684 | } |
3a581073 | 3685 | memset(rx_ring->rx_buffer_info, 0, size); |
9a799d71 | 3686 | |
9a799d71 | 3687 | /* Round up to nearest 4K */ |
3a581073 JB |
3688 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
3689 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 3690 | |
3a581073 | 3691 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma); |
9a799d71 | 3692 | |
3a581073 | 3693 | if (!rx_ring->desc) { |
9a799d71 | 3694 | DPRINTK(PROBE, ERR, |
b4617240 | 3695 | "Memory allocation failed for the rx desc ring\n"); |
3a581073 | 3696 | vfree(rx_ring->rx_buffer_info); |
177db6ff | 3697 | goto alloc_failed; |
9a799d71 AK |
3698 | } |
3699 | ||
3a581073 JB |
3700 | rx_ring->next_to_clean = 0; |
3701 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
3702 | |
3703 | return 0; | |
177db6ff MC |
3704 | |
3705 | alloc_failed: | |
177db6ff | 3706 | return -ENOMEM; |
9a799d71 AK |
3707 | } |
3708 | ||
69888674 AD |
3709 | /** |
3710 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
3711 | * @adapter: board private structure | |
3712 | * | |
3713 | * If this function returns with an error, then it's possible one or | |
3714 | * more of the rings is populated (while the rest are not). It is the | |
3715 | * callers duty to clean those orphaned rings. | |
3716 | * | |
3717 | * Return 0 on success, negative on failure | |
3718 | **/ | |
3719 | ||
3720 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) | |
3721 | { | |
3722 | int i, err = 0; | |
3723 | ||
3724 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3725 | err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]); | |
3726 | if (!err) | |
3727 | continue; | |
3728 | DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i); | |
3729 | break; | |
3730 | } | |
3731 | ||
3732 | return err; | |
3733 | } | |
3734 | ||
9a799d71 AK |
3735 | /** |
3736 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
3737 | * @adapter: board private structure | |
3738 | * @tx_ring: Tx descriptor ring for a specific queue | |
3739 | * | |
3740 | * Free all transmit software resources | |
3741 | **/ | |
c431f97e JB |
3742 | void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter, |
3743 | struct ixgbe_ring *tx_ring) | |
9a799d71 AK |
3744 | { |
3745 | struct pci_dev *pdev = adapter->pdev; | |
3746 | ||
3747 | ixgbe_clean_tx_ring(adapter, tx_ring); | |
3748 | ||
3749 | vfree(tx_ring->tx_buffer_info); | |
3750 | tx_ring->tx_buffer_info = NULL; | |
3751 | ||
3752 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
3753 | ||
3754 | tx_ring->desc = NULL; | |
3755 | } | |
3756 | ||
3757 | /** | |
3758 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
3759 | * @adapter: board private structure | |
3760 | * | |
3761 | * Free all transmit software resources | |
3762 | **/ | |
3763 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
3764 | { | |
3765 | int i; | |
3766 | ||
3767 | for (i = 0; i < adapter->num_tx_queues; i++) | |
9891ca7c JB |
3768 | if (adapter->tx_ring[i].desc) |
3769 | ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
3770 | } |
3771 | ||
3772 | /** | |
b4617240 | 3773 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
3774 | * @adapter: board private structure |
3775 | * @rx_ring: ring to clean the resources from | |
3776 | * | |
3777 | * Free all receive software resources | |
3778 | **/ | |
c431f97e JB |
3779 | void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter, |
3780 | struct ixgbe_ring *rx_ring) | |
9a799d71 AK |
3781 | { |
3782 | struct pci_dev *pdev = adapter->pdev; | |
3783 | ||
3784 | ixgbe_clean_rx_ring(adapter, rx_ring); | |
3785 | ||
3786 | vfree(rx_ring->rx_buffer_info); | |
3787 | rx_ring->rx_buffer_info = NULL; | |
3788 | ||
3789 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
3790 | ||
3791 | rx_ring->desc = NULL; | |
3792 | } | |
3793 | ||
3794 | /** | |
3795 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
3796 | * @adapter: board private structure | |
3797 | * | |
3798 | * Free all receive software resources | |
3799 | **/ | |
3800 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
3801 | { | |
3802 | int i; | |
3803 | ||
3804 | for (i = 0; i < adapter->num_rx_queues; i++) | |
9891ca7c JB |
3805 | if (adapter->rx_ring[i].desc) |
3806 | ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
3807 | } |
3808 | ||
9a799d71 AK |
3809 | /** |
3810 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
3811 | * @netdev: network interface device structure | |
3812 | * @new_mtu: new value for maximum frame size | |
3813 | * | |
3814 | * Returns 0 on success, negative on failure | |
3815 | **/ | |
3816 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
3817 | { | |
3818 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3819 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
3820 | ||
42c783c5 JB |
3821 | /* MTU < 68 is an error and causes problems on some kernels */ |
3822 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
9a799d71 AK |
3823 | return -EINVAL; |
3824 | ||
021230d4 | 3825 | DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n", |
b4617240 | 3826 | netdev->mtu, new_mtu); |
021230d4 | 3827 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
3828 | netdev->mtu = new_mtu; |
3829 | ||
d4f80882 AV |
3830 | if (netif_running(netdev)) |
3831 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
3832 | |
3833 | return 0; | |
3834 | } | |
3835 | ||
3836 | /** | |
3837 | * ixgbe_open - Called when a network interface is made active | |
3838 | * @netdev: network interface device structure | |
3839 | * | |
3840 | * Returns 0 on success, negative value on failure | |
3841 | * | |
3842 | * The open entry point is called when a network interface is made | |
3843 | * active by the system (IFF_UP). At this point all resources needed | |
3844 | * for transmit and receive operations are allocated, the interrupt | |
3845 | * handler is registered with the OS, the watchdog timer is started, | |
3846 | * and the stack is notified that the interface is ready. | |
3847 | **/ | |
3848 | static int ixgbe_open(struct net_device *netdev) | |
3849 | { | |
3850 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3851 | int err; | |
4bebfaa5 AK |
3852 | |
3853 | /* disallow open during test */ | |
3854 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
3855 | return -EBUSY; | |
9a799d71 | 3856 | |
54386467 JB |
3857 | netif_carrier_off(netdev); |
3858 | ||
9a799d71 AK |
3859 | /* allocate transmit descriptors */ |
3860 | err = ixgbe_setup_all_tx_resources(adapter); | |
3861 | if (err) | |
3862 | goto err_setup_tx; | |
3863 | ||
9a799d71 AK |
3864 | /* allocate receive descriptors */ |
3865 | err = ixgbe_setup_all_rx_resources(adapter); | |
3866 | if (err) | |
3867 | goto err_setup_rx; | |
3868 | ||
3869 | ixgbe_configure(adapter); | |
3870 | ||
021230d4 | 3871 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
3872 | if (err) |
3873 | goto err_req_irq; | |
3874 | ||
9a799d71 AK |
3875 | err = ixgbe_up_complete(adapter); |
3876 | if (err) | |
3877 | goto err_up; | |
3878 | ||
d55b53ff JK |
3879 | netif_tx_start_all_queues(netdev); |
3880 | ||
9a799d71 AK |
3881 | return 0; |
3882 | ||
3883 | err_up: | |
5eba3699 | 3884 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
3885 | ixgbe_free_irq(adapter); |
3886 | err_req_irq: | |
9a799d71 | 3887 | err_setup_rx: |
a20a1199 | 3888 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 3889 | err_setup_tx: |
a20a1199 | 3890 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
3891 | ixgbe_reset(adapter); |
3892 | ||
3893 | return err; | |
3894 | } | |
3895 | ||
3896 | /** | |
3897 | * ixgbe_close - Disables a network interface | |
3898 | * @netdev: network interface device structure | |
3899 | * | |
3900 | * Returns 0, this is not allowed to fail | |
3901 | * | |
3902 | * The close entry point is called when an interface is de-activated | |
3903 | * by the OS. The hardware is still under the drivers control, but | |
3904 | * needs to be disabled. A global MAC reset is issued to stop the | |
3905 | * hardware, and all transmit and receive resources are freed. | |
3906 | **/ | |
3907 | static int ixgbe_close(struct net_device *netdev) | |
3908 | { | |
3909 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
3910 | |
3911 | ixgbe_down(adapter); | |
3912 | ixgbe_free_irq(adapter); | |
3913 | ||
3914 | ixgbe_free_all_tx_resources(adapter); | |
3915 | ixgbe_free_all_rx_resources(adapter); | |
3916 | ||
5eba3699 | 3917 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
3918 | |
3919 | return 0; | |
3920 | } | |
3921 | ||
b3c8b4ba AD |
3922 | #ifdef CONFIG_PM |
3923 | static int ixgbe_resume(struct pci_dev *pdev) | |
3924 | { | |
3925 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3926 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3927 | u32 err; | |
3928 | ||
3929 | pci_set_power_state(pdev, PCI_D0); | |
3930 | pci_restore_state(pdev); | |
9ce77666 | 3931 | |
3932 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 3933 | if (err) { |
69888674 | 3934 | printk(KERN_ERR "ixgbe: Cannot enable PCI device from " |
b3c8b4ba AD |
3935 | "suspend\n"); |
3936 | return err; | |
3937 | } | |
3938 | pci_set_master(pdev); | |
3939 | ||
dd4d8ca6 | 3940 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
3941 | |
3942 | err = ixgbe_init_interrupt_scheme(adapter); | |
3943 | if (err) { | |
3944 | printk(KERN_ERR "ixgbe: Cannot initialize interrupts for " | |
3945 | "device\n"); | |
3946 | return err; | |
3947 | } | |
3948 | ||
b3c8b4ba AD |
3949 | ixgbe_reset(adapter); |
3950 | ||
495dce12 WJP |
3951 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
3952 | ||
b3c8b4ba AD |
3953 | if (netif_running(netdev)) { |
3954 | err = ixgbe_open(adapter->netdev); | |
3955 | if (err) | |
3956 | return err; | |
3957 | } | |
3958 | ||
3959 | netif_device_attach(netdev); | |
3960 | ||
3961 | return 0; | |
3962 | } | |
b3c8b4ba | 3963 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
3964 | |
3965 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba AD |
3966 | { |
3967 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3968 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
e8e26350 PW |
3969 | struct ixgbe_hw *hw = &adapter->hw; |
3970 | u32 ctrl, fctrl; | |
3971 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
3972 | #ifdef CONFIG_PM |
3973 | int retval = 0; | |
3974 | #endif | |
3975 | ||
3976 | netif_device_detach(netdev); | |
3977 | ||
3978 | if (netif_running(netdev)) { | |
3979 | ixgbe_down(adapter); | |
3980 | ixgbe_free_irq(adapter); | |
3981 | ixgbe_free_all_tx_resources(adapter); | |
3982 | ixgbe_free_all_rx_resources(adapter); | |
3983 | } | |
7a921c93 | 3984 | ixgbe_clear_interrupt_scheme(adapter); |
b3c8b4ba AD |
3985 | |
3986 | #ifdef CONFIG_PM | |
3987 | retval = pci_save_state(pdev); | |
3988 | if (retval) | |
3989 | return retval; | |
4df10466 | 3990 | |
b3c8b4ba | 3991 | #endif |
e8e26350 PW |
3992 | if (wufc) { |
3993 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 3994 | |
e8e26350 PW |
3995 | /* turn on all-multi mode if wake on multicast is enabled */ |
3996 | if (wufc & IXGBE_WUFC_MC) { | |
3997 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3998 | fctrl |= IXGBE_FCTRL_MPE; | |
3999 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
4000 | } | |
4001 | ||
4002 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
4003 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
4004 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
4005 | ||
4006 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
4007 | } else { | |
4008 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
4009 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
4010 | } | |
4011 | ||
dd4d8ca6 DS |
4012 | if (wufc && hw->mac.type == ixgbe_mac_82599EB) |
4013 | pci_wake_from_d3(pdev, true); | |
4014 | else | |
4015 | pci_wake_from_d3(pdev, false); | |
b3c8b4ba | 4016 | |
9d8d05ae RW |
4017 | *enable_wake = !!wufc; |
4018 | ||
b3c8b4ba AD |
4019 | ixgbe_release_hw_control(adapter); |
4020 | ||
4021 | pci_disable_device(pdev); | |
4022 | ||
9d8d05ae RW |
4023 | return 0; |
4024 | } | |
4025 | ||
4026 | #ifdef CONFIG_PM | |
4027 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
4028 | { | |
4029 | int retval; | |
4030 | bool wake; | |
4031 | ||
4032 | retval = __ixgbe_shutdown(pdev, &wake); | |
4033 | if (retval) | |
4034 | return retval; | |
4035 | ||
4036 | if (wake) { | |
4037 | pci_prepare_to_sleep(pdev); | |
4038 | } else { | |
4039 | pci_wake_from_d3(pdev, false); | |
4040 | pci_set_power_state(pdev, PCI_D3hot); | |
4041 | } | |
b3c8b4ba AD |
4042 | |
4043 | return 0; | |
4044 | } | |
9d8d05ae | 4045 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
4046 | |
4047 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
4048 | { | |
9d8d05ae RW |
4049 | bool wake; |
4050 | ||
4051 | __ixgbe_shutdown(pdev, &wake); | |
4052 | ||
4053 | if (system_state == SYSTEM_POWER_OFF) { | |
4054 | pci_wake_from_d3(pdev, wake); | |
4055 | pci_set_power_state(pdev, PCI_D3hot); | |
4056 | } | |
b3c8b4ba AD |
4057 | } |
4058 | ||
9a799d71 AK |
4059 | /** |
4060 | * ixgbe_update_stats - Update the board statistics counters. | |
4061 | * @adapter: board private structure | |
4062 | **/ | |
4063 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
4064 | { | |
4065 | struct ixgbe_hw *hw = &adapter->hw; | |
6f11eef7 AV |
4066 | u64 total_mpc = 0; |
4067 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
9a799d71 | 4068 | |
d51019a4 | 4069 | if (hw->mac.type == ixgbe_mac_82599EB) { |
f8212f97 | 4070 | u64 rsc_count = 0; |
d51019a4 PW |
4071 | for (i = 0; i < 16; i++) |
4072 | adapter->hw_rx_no_dma_resources += | |
4073 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
f8212f97 AD |
4074 | for (i = 0; i < adapter->num_rx_queues; i++) |
4075 | rsc_count += adapter->rx_ring[i].rsc_count; | |
4076 | adapter->rsc_count = rsc_count; | |
d51019a4 PW |
4077 | } |
4078 | ||
9a799d71 | 4079 | adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
6f11eef7 AV |
4080 | for (i = 0; i < 8; i++) { |
4081 | /* for packet buffers not used, the register should read 0 */ | |
4082 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
4083 | missed_rx += mpc; | |
4084 | adapter->stats.mpc[i] += mpc; | |
4085 | total_mpc += adapter->stats.mpc[i]; | |
e8e26350 PW |
4086 | if (hw->mac.type == ixgbe_mac_82598EB) |
4087 | adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
2f90b865 AD |
4088 | adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); |
4089 | adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
4090 | adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
4091 | adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
e8e26350 PW |
4092 | if (hw->mac.type == ixgbe_mac_82599EB) { |
4093 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
4094 | IXGBE_PXONRXCNT(i)); | |
4095 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
4096 | IXGBE_PXOFFRXCNT(i)); | |
4097 | adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
e8e26350 PW |
4098 | } else { |
4099 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
4100 | IXGBE_PXONRXC(i)); | |
4101 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
4102 | IXGBE_PXOFFRXC(i)); | |
4103 | } | |
2f90b865 AD |
4104 | adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw, |
4105 | IXGBE_PXONTXC(i)); | |
2f90b865 | 4106 | adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw, |
e8e26350 | 4107 | IXGBE_PXOFFTXC(i)); |
6f11eef7 AV |
4108 | } |
4109 | adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); | |
4110 | /* work around hardware counting issue */ | |
4111 | adapter->stats.gprc -= missed_rx; | |
4112 | ||
4113 | /* 82598 hardware only has a 32 bit counter in the high register */ | |
e8e26350 PW |
4114 | if (hw->mac.type == ixgbe_mac_82599EB) { |
4115 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); | |
4116 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ | |
4117 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); | |
4118 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ | |
4119 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL); | |
4120 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ | |
4121 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); | |
4122 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
6d45522c YZ |
4123 | #ifdef IXGBE_FCOE |
4124 | adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); | |
4125 | adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
4126 | adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
4127 | adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
4128 | adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
4129 | adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
4130 | #endif /* IXGBE_FCOE */ | |
e8e26350 PW |
4131 | } else { |
4132 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
4133 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
4134 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); | |
4135 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
4136 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
4137 | } | |
9a799d71 AK |
4138 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
4139 | adapter->stats.bprc += bprc; | |
4140 | adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 PW |
4141 | if (hw->mac.type == ixgbe_mac_82598EB) |
4142 | adapter->stats.mprc -= bprc; | |
9a799d71 AK |
4143 | adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC); |
4144 | adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
4145 | adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
4146 | adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
4147 | adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
4148 | adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
4149 | adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
9a799d71 | 4150 | adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); |
6f11eef7 AV |
4151 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
4152 | adapter->stats.lxontxc += lxon; | |
4153 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
4154 | adapter->stats.lxofftxc += lxoff; | |
9a799d71 AK |
4155 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4156 | adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
6f11eef7 AV |
4157 | adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); |
4158 | /* | |
4159 | * 82598 errata - tx of flow control packets is included in tx counters | |
4160 | */ | |
4161 | xon_off_tot = lxon + lxoff; | |
4162 | adapter->stats.gptc -= xon_off_tot; | |
4163 | adapter->stats.mptc -= xon_off_tot; | |
4164 | adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
9a799d71 AK |
4165 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4166 | adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
4167 | adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
9a799d71 AK |
4168 | adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR); |
4169 | adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6f11eef7 | 4170 | adapter->stats.ptc64 -= xon_off_tot; |
9a799d71 AK |
4171 | adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); |
4172 | adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
4173 | adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
4174 | adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
4175 | adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
9a799d71 AK |
4176 | adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); |
4177 | ||
4178 | /* Fill out the OS statistics structure */ | |
9a799d71 AK |
4179 | adapter->net_stats.multicast = adapter->stats.mprc; |
4180 | ||
4181 | /* Rx Errors */ | |
4182 | adapter->net_stats.rx_errors = adapter->stats.crcerrs + | |
b4617240 | 4183 | adapter->stats.rlec; |
9a799d71 AK |
4184 | adapter->net_stats.rx_dropped = 0; |
4185 | adapter->net_stats.rx_length_errors = adapter->stats.rlec; | |
4186 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; | |
6f11eef7 | 4187 | adapter->net_stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
4188 | } |
4189 | ||
4190 | /** | |
4191 | * ixgbe_watchdog - Timer Call-back | |
4192 | * @data: pointer to adapter cast into an unsigned long | |
4193 | **/ | |
4194 | static void ixgbe_watchdog(unsigned long data) | |
4195 | { | |
4196 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee JB |
4197 | struct ixgbe_hw *hw = &adapter->hw; |
4198 | ||
4199 | /* Do the watchdog outside of interrupt context due to the lovely | |
4200 | * delays that some of the newer hardware requires */ | |
4201 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
22d5a71b JB |
4202 | u64 eics = 0; |
4203 | int i; | |
4204 | ||
4205 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) | |
c9c7d2e5 | 4206 | eics |= ((u64)1 << i); |
22d5a71b | 4207 | |
cf8280ee | 4208 | /* Cause software interrupt to ensure rx rings are cleaned */ |
22d5a71b JB |
4209 | switch (hw->mac.type) { |
4210 | case ixgbe_mac_82598EB: | |
4211 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
4212 | IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics); | |
4213 | } else { | |
4214 | /* | |
4215 | * for legacy and MSI interrupts don't set any | |
4216 | * bits that are enabled for EIAM, because this | |
4217 | * operation would set *both* EIMS and EICS for | |
4218 | * any bit in EIAM | |
4219 | */ | |
4220 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
4221 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
4222 | } | |
4223 | break; | |
4224 | case ixgbe_mac_82599EB: | |
4225 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
835462fc NS |
4226 | IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(0), |
4227 | (u32)(eics & 0xFFFFFFFF)); | |
22d5a71b | 4228 | IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1), |
22d5a71b JB |
4229 | (u32)(eics >> 32)); |
4230 | } else { | |
4231 | /* | |
4232 | * for legacy and MSI interrupts don't set any | |
4233 | * bits that are enabled for EIAM, because this | |
4234 | * operation would set *both* EIMS and EICS for | |
4235 | * any bit in EIAM | |
4236 | */ | |
4237 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
4238 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
4239 | } | |
4240 | break; | |
4241 | default: | |
4242 | break; | |
cf8280ee JB |
4243 | } |
4244 | /* Reset the timer */ | |
4245 | mod_timer(&adapter->watchdog_timer, | |
4246 | round_jiffies(jiffies + 2 * HZ)); | |
4247 | } | |
9a799d71 | 4248 | |
cf8280ee JB |
4249 | schedule_work(&adapter->watchdog_task); |
4250 | } | |
4251 | ||
e8e26350 PW |
4252 | /** |
4253 | * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber | |
4254 | * @work: pointer to work_struct containing our data | |
4255 | **/ | |
4256 | static void ixgbe_multispeed_fiber_task(struct work_struct *work) | |
4257 | { | |
4258 | struct ixgbe_adapter *adapter = container_of(work, | |
4259 | struct ixgbe_adapter, | |
4260 | multispeed_fiber_task); | |
4261 | struct ixgbe_hw *hw = &adapter->hw; | |
4262 | u32 autoneg; | |
4263 | ||
4264 | adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK; | |
4265 | if (hw->mac.ops.get_link_capabilities) | |
4266 | hw->mac.ops.get_link_capabilities(hw, &autoneg, | |
4267 | &hw->mac.autoneg); | |
4268 | if (hw->mac.ops.setup_link_speed) | |
4269 | hw->mac.ops.setup_link_speed(hw, autoneg, true, true); | |
4270 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
4271 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK; | |
4272 | } | |
4273 | ||
4274 | /** | |
4275 | * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module | |
4276 | * @work: pointer to work_struct containing our data | |
4277 | **/ | |
4278 | static void ixgbe_sfp_config_module_task(struct work_struct *work) | |
4279 | { | |
4280 | struct ixgbe_adapter *adapter = container_of(work, | |
4281 | struct ixgbe_adapter, | |
4282 | sfp_config_module_task); | |
4283 | struct ixgbe_hw *hw = &adapter->hw; | |
4284 | u32 err; | |
4285 | ||
4286 | adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK; | |
4287 | err = hw->phy.ops.identify_sfp(hw); | |
4288 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
4289 | DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err); | |
4290 | ixgbe_down(adapter); | |
4291 | return; | |
4292 | } | |
4293 | hw->mac.ops.setup_sfp(hw); | |
4294 | ||
8d1c3c07 | 4295 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) |
e8e26350 PW |
4296 | /* This will also work for DA Twinax connections */ |
4297 | schedule_work(&adapter->multispeed_fiber_task); | |
4298 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK; | |
4299 | } | |
4300 | ||
cf8280ee | 4301 | /** |
69888674 AD |
4302 | * ixgbe_watchdog_task - worker thread to bring link up |
4303 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
4304 | **/ |
4305 | static void ixgbe_watchdog_task(struct work_struct *work) | |
4306 | { | |
4307 | struct ixgbe_adapter *adapter = container_of(work, | |
4308 | struct ixgbe_adapter, | |
4309 | watchdog_task); | |
4310 | struct net_device *netdev = adapter->netdev; | |
4311 | struct ixgbe_hw *hw = &adapter->hw; | |
4312 | u32 link_speed = adapter->link_speed; | |
4313 | bool link_up = adapter->link_up; | |
bc59fcda NS |
4314 | int i; |
4315 | struct ixgbe_ring *tx_ring; | |
4316 | int some_tx_pending = 0; | |
cf8280ee JB |
4317 | |
4318 | adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK; | |
4319 | ||
4320 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
4321 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
4322 | if (link_up || | |
4323 | time_after(jiffies, (adapter->link_check_timeout + | |
4324 | IXGBE_TRY_LINK_TIMEOUT))) { | |
4325 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
4326 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
4327 | } | |
4328 | adapter->link_up = link_up; | |
4329 | adapter->link_speed = link_speed; | |
4330 | } | |
9a799d71 AK |
4331 | |
4332 | if (link_up) { | |
4333 | if (!netif_carrier_ok(netdev)) { | |
e8e26350 PW |
4334 | bool flow_rx, flow_tx; |
4335 | ||
4336 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
4337 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
4338 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
4339 | flow_rx = (mflcn & IXGBE_MFLCN_RFCE); | |
4340 | flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
4341 | } else { | |
4342 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4343 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
4344 | flow_rx = (frctl & IXGBE_FCTRL_RFCE); | |
4345 | flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X); | |
4346 | } | |
4347 | ||
a46e534b JK |
4348 | printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, " |
4349 | "Flow Control: %s\n", | |
4350 | netdev->name, | |
4351 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
4352 | "10 Gbps" : | |
4353 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
4354 | "1 Gbps" : "unknown speed")), | |
e8e26350 PW |
4355 | ((flow_rx && flow_tx) ? "RX/TX" : |
4356 | (flow_rx ? "RX" : | |
4357 | (flow_tx ? "TX" : "None")))); | |
9a799d71 AK |
4358 | |
4359 | netif_carrier_on(netdev); | |
9a799d71 AK |
4360 | } else { |
4361 | /* Force detection of hung controller */ | |
4362 | adapter->detect_tx_hung = true; | |
4363 | } | |
4364 | } else { | |
cf8280ee JB |
4365 | adapter->link_up = false; |
4366 | adapter->link_speed = 0; | |
9a799d71 | 4367 | if (netif_carrier_ok(netdev)) { |
a46e534b JK |
4368 | printk(KERN_INFO "ixgbe: %s NIC Link is Down\n", |
4369 | netdev->name); | |
9a799d71 | 4370 | netif_carrier_off(netdev); |
9a799d71 AK |
4371 | } |
4372 | } | |
4373 | ||
bc59fcda NS |
4374 | if (!netif_carrier_ok(netdev)) { |
4375 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4376 | tx_ring = &adapter->tx_ring[i]; | |
4377 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { | |
4378 | some_tx_pending = 1; | |
4379 | break; | |
4380 | } | |
4381 | } | |
4382 | ||
4383 | if (some_tx_pending) { | |
4384 | /* We've lost link, so the controller stops DMA, | |
4385 | * but we've got queued Tx work that's never going | |
4386 | * to get done, so reset controller to flush Tx. | |
4387 | * (Do the reset outside of interrupt context). | |
4388 | */ | |
4389 | schedule_work(&adapter->reset_task); | |
4390 | } | |
4391 | } | |
4392 | ||
9a799d71 | 4393 | ixgbe_update_stats(adapter); |
cf8280ee | 4394 | adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK; |
9a799d71 AK |
4395 | } |
4396 | ||
9a799d71 | 4397 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
b4617240 PW |
4398 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
4399 | u32 tx_flags, u8 *hdr_len) | |
9a799d71 AK |
4400 | { |
4401 | struct ixgbe_adv_tx_context_desc *context_desc; | |
4402 | unsigned int i; | |
4403 | int err; | |
4404 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
4405 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
4406 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
4407 | |
4408 | if (skb_is_gso(skb)) { | |
4409 | if (skb_header_cloned(skb)) { | |
4410 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
4411 | if (err) | |
4412 | return err; | |
4413 | } | |
4414 | l4len = tcp_hdrlen(skb); | |
4415 | *hdr_len += l4len; | |
4416 | ||
8327d000 | 4417 | if (skb->protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
4418 | struct iphdr *iph = ip_hdr(skb); |
4419 | iph->tot_len = 0; | |
4420 | iph->check = 0; | |
4421 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
b4617240 PW |
4422 | iph->daddr, 0, |
4423 | IPPROTO_TCP, | |
4424 | 0); | |
9a799d71 AK |
4425 | adapter->hw_tso_ctxt++; |
4426 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { | |
4427 | ipv6_hdr(skb)->payload_len = 0; | |
4428 | tcp_hdr(skb)->check = | |
4429 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
b4617240 PW |
4430 | &ipv6_hdr(skb)->daddr, |
4431 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
4432 | adapter->hw_tso6_ctxt++; |
4433 | } | |
4434 | ||
4435 | i = tx_ring->next_to_use; | |
4436 | ||
4437 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4438 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
4439 | ||
4440 | /* VLAN MACLEN IPLEN */ | |
4441 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4442 | vlan_macip_lens |= | |
4443 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
4444 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
b4617240 | 4445 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
4446 | *hdr_len += skb_network_offset(skb); |
4447 | vlan_macip_lens |= | |
4448 | (skb_transport_header(skb) - skb_network_header(skb)); | |
4449 | *hdr_len += | |
4450 | (skb_transport_header(skb) - skb_network_header(skb)); | |
4451 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4452 | context_desc->seqnum_seed = 0; | |
4453 | ||
4454 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 4455 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
b4617240 | 4456 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 4457 | |
8327d000 | 4458 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
4459 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
4460 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
4461 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4462 | ||
4463 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 4464 | mss_l4len_idx = |
9a799d71 AK |
4465 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
4466 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
4467 | /* use index 1 for TSO */ |
4468 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
4469 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
4470 | ||
4471 | tx_buffer_info->time_stamp = jiffies; | |
4472 | tx_buffer_info->next_to_watch = i; | |
4473 | ||
4474 | i++; | |
4475 | if (i == tx_ring->count) | |
4476 | i = 0; | |
4477 | tx_ring->next_to_use = i; | |
4478 | ||
4479 | return true; | |
4480 | } | |
4481 | return false; | |
4482 | } | |
4483 | ||
4484 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, | |
b4617240 PW |
4485 | struct ixgbe_ring *tx_ring, |
4486 | struct sk_buff *skb, u32 tx_flags) | |
9a799d71 AK |
4487 | { |
4488 | struct ixgbe_adv_tx_context_desc *context_desc; | |
4489 | unsigned int i; | |
4490 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4491 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
4492 | ||
4493 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
4494 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
4495 | i = tx_ring->next_to_use; | |
4496 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4497 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
4498 | ||
4499 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4500 | vlan_macip_lens |= | |
4501 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
4502 | vlan_macip_lens |= (skb_network_offset(skb) << | |
b4617240 | 4503 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
4504 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
4505 | vlan_macip_lens |= (skb_transport_header(skb) - | |
b4617240 | 4506 | skb_network_header(skb)); |
9a799d71 AK |
4507 | |
4508 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4509 | context_desc->seqnum_seed = 0; | |
4510 | ||
4511 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
b4617240 | 4512 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 AK |
4513 | |
4514 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
41825d71 | 4515 | switch (skb->protocol) { |
09640e63 | 4516 | case cpu_to_be16(ETH_P_IP): |
9a799d71 | 4517 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
41825d71 AK |
4518 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
4519 | type_tucmd_mlhl |= | |
b4617240 | 4520 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
4521 | else if (ip_hdr(skb)->protocol == IPPROTO_SCTP) |
4522 | type_tucmd_mlhl |= | |
4523 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 4524 | break; |
09640e63 | 4525 | case cpu_to_be16(ETH_P_IPV6): |
41825d71 AK |
4526 | /* XXX what about other V6 headers?? */ |
4527 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
4528 | type_tucmd_mlhl |= | |
b4617240 | 4529 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
4530 | else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP) |
4531 | type_tucmd_mlhl |= | |
4532 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 4533 | break; |
41825d71 AK |
4534 | default: |
4535 | if (unlikely(net_ratelimit())) { | |
4536 | DPRINTK(PROBE, WARNING, | |
4537 | "partial checksum but proto=%x!\n", | |
4538 | skb->protocol); | |
4539 | } | |
4540 | break; | |
4541 | } | |
9a799d71 AK |
4542 | } |
4543 | ||
4544 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 4545 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
4546 | context_desc->mss_l4len_idx = 0; |
4547 | ||
4548 | tx_buffer_info->time_stamp = jiffies; | |
4549 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 4550 | |
9a799d71 AK |
4551 | adapter->hw_csum_tx_good++; |
4552 | i++; | |
4553 | if (i == tx_ring->count) | |
4554 | i = 0; | |
4555 | tx_ring->next_to_use = i; | |
4556 | ||
4557 | return true; | |
4558 | } | |
9f8cdf4f | 4559 | |
9a799d71 AK |
4560 | return false; |
4561 | } | |
4562 | ||
4563 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
b4617240 | 4564 | struct ixgbe_ring *tx_ring, |
eacd73f7 YZ |
4565 | struct sk_buff *skb, u32 tx_flags, |
4566 | unsigned int first) | |
9a799d71 AK |
4567 | { |
4568 | struct ixgbe_tx_buffer *tx_buffer_info; | |
eacd73f7 YZ |
4569 | unsigned int len; |
4570 | unsigned int total = skb->len; | |
9a799d71 AK |
4571 | unsigned int offset = 0, size, count = 0, i; |
4572 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
4573 | unsigned int f; | |
44df32c5 | 4574 | dma_addr_t *map; |
9a799d71 AK |
4575 | |
4576 | i = tx_ring->next_to_use; | |
4577 | ||
44df32c5 AD |
4578 | if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) { |
4579 | dev_err(&adapter->pdev->dev, "TX DMA map failed\n"); | |
4580 | return 0; | |
4581 | } | |
4582 | ||
4583 | map = skb_shinfo(skb)->dma_maps; | |
4584 | ||
eacd73f7 YZ |
4585 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) |
4586 | /* excluding fcoe_crc_eof for FCoE */ | |
4587 | total -= sizeof(struct fcoe_crc_eof); | |
4588 | ||
4589 | len = min(skb_headlen(skb), total); | |
9a799d71 AK |
4590 | while (len) { |
4591 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4592 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
4593 | ||
4594 | tx_buffer_info->length = size; | |
44df32c5 | 4595 | tx_buffer_info->dma = map[0] + offset; |
9a799d71 AK |
4596 | tx_buffer_info->time_stamp = jiffies; |
4597 | tx_buffer_info->next_to_watch = i; | |
4598 | ||
4599 | len -= size; | |
eacd73f7 | 4600 | total -= size; |
9a799d71 AK |
4601 | offset += size; |
4602 | count++; | |
44df32c5 AD |
4603 | |
4604 | if (len) { | |
4605 | i++; | |
4606 | if (i == tx_ring->count) | |
4607 | i = 0; | |
4608 | } | |
9a799d71 AK |
4609 | } |
4610 | ||
4611 | for (f = 0; f < nr_frags; f++) { | |
4612 | struct skb_frag_struct *frag; | |
4613 | ||
4614 | frag = &skb_shinfo(skb)->frags[f]; | |
eacd73f7 | 4615 | len = min((unsigned int)frag->size, total); |
44df32c5 | 4616 | offset = 0; |
9a799d71 AK |
4617 | |
4618 | while (len) { | |
44df32c5 AD |
4619 | i++; |
4620 | if (i == tx_ring->count) | |
4621 | i = 0; | |
4622 | ||
9a799d71 AK |
4623 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
4624 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
4625 | ||
4626 | tx_buffer_info->length = size; | |
44df32c5 | 4627 | tx_buffer_info->dma = map[f + 1] + offset; |
9a799d71 AK |
4628 | tx_buffer_info->time_stamp = jiffies; |
4629 | tx_buffer_info->next_to_watch = i; | |
4630 | ||
4631 | len -= size; | |
eacd73f7 | 4632 | total -= size; |
9a799d71 AK |
4633 | offset += size; |
4634 | count++; | |
9a799d71 | 4635 | } |
eacd73f7 YZ |
4636 | if (total == 0) |
4637 | break; | |
9a799d71 | 4638 | } |
44df32c5 | 4639 | |
9a799d71 AK |
4640 | tx_ring->tx_buffer_info[i].skb = skb; |
4641 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
4642 | ||
4643 | return count; | |
4644 | } | |
4645 | ||
4646 | static void ixgbe_tx_queue(struct ixgbe_adapter *adapter, | |
b4617240 PW |
4647 | struct ixgbe_ring *tx_ring, |
4648 | int tx_flags, int count, u32 paylen, u8 hdr_len) | |
9a799d71 AK |
4649 | { |
4650 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
4651 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4652 | u32 olinfo_status = 0, cmd_type_len = 0; | |
4653 | unsigned int i; | |
4654 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
4655 | ||
4656 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
4657 | ||
4658 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
4659 | ||
4660 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4661 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
4662 | ||
4663 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
4664 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
4665 | ||
4666 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 4667 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 4668 | |
4eeae6fd PW |
4669 | /* use index 1 context for tso */ |
4670 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
4671 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
4672 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
b4617240 | 4673 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
4674 | |
4675 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
4676 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 4677 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 4678 | |
eacd73f7 YZ |
4679 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
4680 | olinfo_status |= IXGBE_ADVTXD_CC; | |
4681 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
4682 | if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
4683 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
4684 | } | |
4685 | ||
9a799d71 AK |
4686 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); |
4687 | ||
4688 | i = tx_ring->next_to_use; | |
4689 | while (count--) { | |
4690 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4691 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); | |
4692 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); | |
4693 | tx_desc->read.cmd_type_len = | |
b4617240 | 4694 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 4695 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
4696 | i++; |
4697 | if (i == tx_ring->count) | |
4698 | i = 0; | |
4699 | } | |
4700 | ||
4701 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
4702 | ||
4703 | /* | |
4704 | * Force memory writes to complete before letting h/w | |
4705 | * know there are new descriptors to fetch. (Only | |
4706 | * applicable for weak-ordered memory model archs, | |
4707 | * such as IA-64). | |
4708 | */ | |
4709 | wmb(); | |
4710 | ||
4711 | tx_ring->next_to_use = i; | |
4712 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
4713 | } | |
4714 | ||
e092be60 | 4715 | static int __ixgbe_maybe_stop_tx(struct net_device *netdev, |
b4617240 | 4716 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
4717 | { |
4718 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4719 | ||
30eba97a | 4720 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
4721 | /* Herbert's original patch had: |
4722 | * smp_mb__after_netif_stop_queue(); | |
4723 | * but since that doesn't exist yet, just open code it. */ | |
4724 | smp_mb(); | |
4725 | ||
4726 | /* We need to check again in a case another CPU has just | |
4727 | * made room available. */ | |
4728 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
4729 | return -EBUSY; | |
4730 | ||
4731 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
af72166f | 4732 | netif_start_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
4733 | ++adapter->restart_queue; |
4734 | return 0; | |
4735 | } | |
4736 | ||
4737 | static int ixgbe_maybe_stop_tx(struct net_device *netdev, | |
b4617240 | 4738 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
4739 | { |
4740 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
4741 | return 0; | |
4742 | return __ixgbe_maybe_stop_tx(netdev, tx_ring, size); | |
4743 | } | |
4744 | ||
09a3b1f8 SH |
4745 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
4746 | { | |
4747 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
4748 | ||
4749 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
4750 | return 0; /* All traffic should default to class 0 */ | |
4751 | ||
4752 | return skb_tx_hash(dev, skb); | |
4753 | } | |
4754 | ||
9a799d71 AK |
4755 | static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
4756 | { | |
4757 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4758 | struct ixgbe_ring *tx_ring; | |
9a799d71 AK |
4759 | unsigned int first; |
4760 | unsigned int tx_flags = 0; | |
30eba97a AV |
4761 | u8 hdr_len = 0; |
4762 | int r_idx = 0, tso; | |
9a799d71 AK |
4763 | int count = 0; |
4764 | unsigned int f; | |
9f8cdf4f | 4765 | |
95615d90 | 4766 | r_idx = skb->queue_mapping; |
30eba97a | 4767 | tx_ring = &adapter->tx_ring[r_idx]; |
9a799d71 | 4768 | |
9f8cdf4f JB |
4769 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { |
4770 | tx_flags |= vlan_tx_tag_get(skb); | |
2f90b865 AD |
4771 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
4772 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
4773 | tx_flags |= (skb->queue_mapping << 13); | |
4774 | } | |
4775 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
4776 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
4777 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
4778 | tx_flags |= (skb->queue_mapping << 13); | |
9f8cdf4f JB |
4779 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; |
4780 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 4781 | } |
eacd73f7 YZ |
4782 | |
4783 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
4784 | (skb->protocol == htons(ETH_P_FCOE))) | |
4785 | tx_flags |= IXGBE_TX_FLAGS_FCOE; | |
4786 | ||
4787 | /* four things can cause us to need a context descriptor */ | |
9f8cdf4f JB |
4788 | if (skb_is_gso(skb) || |
4789 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
eacd73f7 YZ |
4790 | (tx_flags & IXGBE_TX_FLAGS_VLAN) || |
4791 | (tx_flags & IXGBE_TX_FLAGS_FCOE)) | |
9a799d71 AK |
4792 | count++; |
4793 | ||
9f8cdf4f JB |
4794 | count += TXD_USE_COUNT(skb_headlen(skb)); |
4795 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
4796 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
4797 | ||
e092be60 | 4798 | if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) { |
9a799d71 | 4799 | adapter->tx_busy++; |
9a799d71 AK |
4800 | return NETDEV_TX_BUSY; |
4801 | } | |
9a799d71 | 4802 | |
9a799d71 | 4803 | first = tx_ring->next_to_use; |
eacd73f7 YZ |
4804 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
4805 | #ifdef IXGBE_FCOE | |
4806 | /* setup tx offload for FCoE */ | |
4807 | tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
4808 | if (tso < 0) { | |
4809 | dev_kfree_skb_any(skb); | |
4810 | return NETDEV_TX_OK; | |
4811 | } | |
4812 | if (tso) | |
4813 | tx_flags |= IXGBE_TX_FLAGS_FSO; | |
4814 | #endif /* IXGBE_FCOE */ | |
4815 | } else { | |
4816 | if (skb->protocol == htons(ETH_P_IP)) | |
4817 | tx_flags |= IXGBE_TX_FLAGS_IPV4; | |
4818 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
4819 | if (tso < 0) { | |
4820 | dev_kfree_skb_any(skb); | |
4821 | return NETDEV_TX_OK; | |
4822 | } | |
9a799d71 | 4823 | |
eacd73f7 YZ |
4824 | if (tso) |
4825 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
4826 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) && | |
4827 | (skb->ip_summed == CHECKSUM_PARTIAL)) | |
4828 | tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
4829 | } | |
9a799d71 | 4830 | |
eacd73f7 | 4831 | count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first); |
44df32c5 AD |
4832 | if (count) { |
4833 | ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len, | |
4834 | hdr_len); | |
4835 | netdev->trans_start = jiffies; | |
4836 | ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED); | |
9a799d71 | 4837 | |
44df32c5 AD |
4838 | } else { |
4839 | dev_kfree_skb_any(skb); | |
4840 | tx_ring->tx_buffer_info[first].time_stamp = 0; | |
4841 | tx_ring->next_to_use = first; | |
4842 | } | |
9a799d71 AK |
4843 | |
4844 | return NETDEV_TX_OK; | |
4845 | } | |
4846 | ||
4847 | /** | |
4848 | * ixgbe_get_stats - Get System Network Statistics | |
4849 | * @netdev: network interface device structure | |
4850 | * | |
4851 | * Returns the address of the device statistics structure. | |
4852 | * The statistics are actually updated from the timer callback. | |
4853 | **/ | |
4854 | static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev) | |
4855 | { | |
4856 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4857 | ||
4858 | /* only return the current stats */ | |
4859 | return &adapter->net_stats; | |
4860 | } | |
4861 | ||
4862 | /** | |
4863 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
4864 | * @netdev: network interface device structure | |
4865 | * @p: pointer to an address structure | |
4866 | * | |
4867 | * Returns 0 on success, negative on failure | |
4868 | **/ | |
4869 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
4870 | { | |
4871 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 4872 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
4873 | struct sockaddr *addr = p; |
4874 | ||
4875 | if (!is_valid_ether_addr(addr->sa_data)) | |
4876 | return -EADDRNOTAVAIL; | |
4877 | ||
4878 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 4879 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 4880 | |
b4617240 | 4881 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
4882 | |
4883 | return 0; | |
4884 | } | |
4885 | ||
6b73e10d BH |
4886 | static int |
4887 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
4888 | { | |
4889 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4890 | struct ixgbe_hw *hw = &adapter->hw; | |
4891 | u16 value; | |
4892 | int rc; | |
4893 | ||
4894 | if (prtad != hw->phy.mdio.prtad) | |
4895 | return -EINVAL; | |
4896 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
4897 | if (!rc) | |
4898 | rc = value; | |
4899 | return rc; | |
4900 | } | |
4901 | ||
4902 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
4903 | u16 addr, u16 value) | |
4904 | { | |
4905 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4906 | struct ixgbe_hw *hw = &adapter->hw; | |
4907 | ||
4908 | if (prtad != hw->phy.mdio.prtad) | |
4909 | return -EINVAL; | |
4910 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
4911 | } | |
4912 | ||
4913 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
4914 | { | |
4915 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4916 | ||
4917 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
4918 | } | |
4919 | ||
0365e6e4 PW |
4920 | /** |
4921 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
4922 | * netdev->dev_addr_list | |
4923 | * @netdev: network interface device structure | |
4924 | * | |
4925 | * Returns non-zero on failure | |
4926 | **/ | |
4927 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
4928 | { | |
4929 | int err = 0; | |
4930 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
4931 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
4932 | ||
4933 | if (is_valid_ether_addr(mac->san_addr)) { | |
4934 | rtnl_lock(); | |
4935 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
4936 | rtnl_unlock(); | |
4937 | } | |
4938 | return err; | |
4939 | } | |
4940 | ||
4941 | /** | |
4942 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
4943 | * netdev->dev_addr_list | |
4944 | * @netdev: network interface device structure | |
4945 | * | |
4946 | * Returns non-zero on failure | |
4947 | **/ | |
4948 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
4949 | { | |
4950 | int err = 0; | |
4951 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
4952 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
4953 | ||
4954 | if (is_valid_ether_addr(mac->san_addr)) { | |
4955 | rtnl_lock(); | |
4956 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
4957 | rtnl_unlock(); | |
4958 | } | |
4959 | return err; | |
4960 | } | |
4961 | ||
9a799d71 AK |
4962 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4963 | /* | |
4964 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
4965 | * without having to re-enable interrupts. It's not called while | |
4966 | * the interrupt routine is executing. | |
4967 | */ | |
4968 | static void ixgbe_netpoll(struct net_device *netdev) | |
4969 | { | |
4970 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4971 | ||
4972 | disable_irq(adapter->pdev->irq); | |
4973 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; | |
4974 | ixgbe_intr(adapter->pdev->irq, netdev); | |
4975 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; | |
4976 | enable_irq(adapter->pdev->irq); | |
4977 | } | |
4978 | #endif | |
4979 | ||
0edc3527 SH |
4980 | static const struct net_device_ops ixgbe_netdev_ops = { |
4981 | .ndo_open = ixgbe_open, | |
4982 | .ndo_stop = ixgbe_close, | |
00829823 | 4983 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 4984 | .ndo_select_queue = ixgbe_select_queue, |
0edc3527 | 4985 | .ndo_get_stats = ixgbe_get_stats, |
e90d400c | 4986 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
4987 | .ndo_set_multicast_list = ixgbe_set_rx_mode, |
4988 | .ndo_validate_addr = eth_validate_addr, | |
4989 | .ndo_set_mac_address = ixgbe_set_mac, | |
4990 | .ndo_change_mtu = ixgbe_change_mtu, | |
4991 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
4992 | .ndo_vlan_rx_register = ixgbe_vlan_rx_register, | |
4993 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, | |
4994 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 4995 | .ndo_do_ioctl = ixgbe_ioctl, |
0edc3527 SH |
4996 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4997 | .ndo_poll_controller = ixgbe_netpoll, | |
4998 | #endif | |
332d4a7d YZ |
4999 | #ifdef IXGBE_FCOE |
5000 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
5001 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, | |
5002 | #endif /* IXGBE_FCOE */ | |
0edc3527 SH |
5003 | }; |
5004 | ||
9a799d71 AK |
5005 | /** |
5006 | * ixgbe_probe - Device Initialization Routine | |
5007 | * @pdev: PCI device information struct | |
5008 | * @ent: entry in ixgbe_pci_tbl | |
5009 | * | |
5010 | * Returns 0 on success, negative on failure | |
5011 | * | |
5012 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
5013 | * The OS initialization, configuring of the adapter private structure, | |
5014 | * and a hardware reset occur. | |
5015 | **/ | |
5016 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
b4617240 | 5017 | const struct pci_device_id *ent) |
9a799d71 AK |
5018 | { |
5019 | struct net_device *netdev; | |
5020 | struct ixgbe_adapter *adapter = NULL; | |
5021 | struct ixgbe_hw *hw; | |
5022 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
5023 | static int cards_found; |
5024 | int i, err, pci_using_dac; | |
eacd73f7 YZ |
5025 | #ifdef IXGBE_FCOE |
5026 | u16 device_caps; | |
5027 | #endif | |
c44ade9e | 5028 | u32 part_num, eec; |
9a799d71 | 5029 | |
9ce77666 | 5030 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
5031 | if (err) |
5032 | return err; | |
5033 | ||
6a35528a YH |
5034 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && |
5035 | !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
5036 | pci_using_dac = 1; |
5037 | } else { | |
284901a9 | 5038 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 5039 | if (err) { |
284901a9 | 5040 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 5041 | if (err) { |
b4617240 PW |
5042 | dev_err(&pdev->dev, "No usable DMA " |
5043 | "configuration, aborting\n"); | |
9a799d71 AK |
5044 | goto err_dma; |
5045 | } | |
5046 | } | |
5047 | pci_using_dac = 0; | |
5048 | } | |
5049 | ||
9ce77666 | 5050 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
5051 | IORESOURCE_MEM), ixgbe_driver_name); | |
9a799d71 | 5052 | if (err) { |
9ce77666 | 5053 | dev_err(&pdev->dev, |
5054 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
5055 | goto err_pci_reg; |
5056 | } | |
5057 | ||
6fabd715 PWJ |
5058 | err = pci_enable_pcie_error_reporting(pdev); |
5059 | if (err) { | |
5060 | dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " | |
5061 | "0x%x\n", err); | |
5062 | /* non-fatal, continue */ | |
5063 | } | |
5064 | ||
9a799d71 | 5065 | pci_set_master(pdev); |
fb3b27bc | 5066 | pci_save_state(pdev); |
9a799d71 | 5067 | |
30eba97a | 5068 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES); |
9a799d71 AK |
5069 | if (!netdev) { |
5070 | err = -ENOMEM; | |
5071 | goto err_alloc_etherdev; | |
5072 | } | |
5073 | ||
9a799d71 AK |
5074 | SET_NETDEV_DEV(netdev, &pdev->dev); |
5075 | ||
5076 | pci_set_drvdata(pdev, netdev); | |
5077 | adapter = netdev_priv(netdev); | |
5078 | ||
5079 | adapter->netdev = netdev; | |
5080 | adapter->pdev = pdev; | |
5081 | hw = &adapter->hw; | |
5082 | hw->back = adapter; | |
5083 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
5084 | ||
05857980 JK |
5085 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
5086 | pci_resource_len(pdev, 0)); | |
9a799d71 AK |
5087 | if (!hw->hw_addr) { |
5088 | err = -EIO; | |
5089 | goto err_ioremap; | |
5090 | } | |
5091 | ||
5092 | for (i = 1; i <= 5; i++) { | |
5093 | if (pci_resource_len(pdev, i) == 0) | |
5094 | continue; | |
5095 | } | |
5096 | ||
0edc3527 | 5097 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 5098 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 5099 | netdev->watchdog_timeo = 5 * HZ; |
9a799d71 AK |
5100 | strcpy(netdev->name, pci_name(pdev)); |
5101 | ||
9a799d71 AK |
5102 | adapter->bd_number = cards_found; |
5103 | ||
9a799d71 AK |
5104 | /* Setup hw api */ |
5105 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 5106 | hw->mac.type = ii->mac; |
9a799d71 | 5107 | |
c44ade9e JB |
5108 | /* EEPROM */ |
5109 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
5110 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
5111 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
5112 | if (!(eec & (1 << 8))) | |
5113 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
5114 | ||
5115 | /* PHY */ | |
5116 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 5117 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
5118 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
5119 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
5120 | hw->phy.mdio.mmds = 0; | |
5121 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
5122 | hw->phy.mdio.dev = netdev; | |
5123 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
5124 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 DS |
5125 | |
5126 | /* set up this timer and work struct before calling get_invariants | |
5127 | * which might start the timer | |
5128 | */ | |
5129 | init_timer(&adapter->sfp_timer); | |
5130 | adapter->sfp_timer.function = &ixgbe_sfp_timer; | |
5131 | adapter->sfp_timer.data = (unsigned long) adapter; | |
5132 | ||
5133 | INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); | |
c44ade9e | 5134 | |
e8e26350 PW |
5135 | /* multispeed fiber has its own tasklet, called from GPI SDP1 context */ |
5136 | INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task); | |
5137 | ||
5138 | /* a new SFP+ module arrival, called from GPI SDP2 context */ | |
5139 | INIT_WORK(&adapter->sfp_config_module_task, | |
5140 | ixgbe_sfp_config_module_task); | |
5141 | ||
9a799d71 | 5142 | err = ii->get_invariants(hw); |
c4900be0 DS |
5143 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
5144 | /* start a kernel thread to watch for a module to arrive */ | |
5145 | set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
5146 | mod_timer(&adapter->sfp_timer, | |
5147 | round_jiffies(jiffies + (2 * HZ))); | |
5148 | err = 0; | |
5149 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
5150 | DPRINTK(PROBE, ERR, "failed to load because an " | |
5151 | "unsupported SFP+ module type was detected.\n"); | |
9a799d71 | 5152 | goto err_hw_init; |
c4900be0 DS |
5153 | } else if (err) { |
5154 | goto err_hw_init; | |
5155 | } | |
9a799d71 AK |
5156 | |
5157 | /* setup the private structure */ | |
5158 | err = ixgbe_sw_init(adapter); | |
5159 | if (err) | |
5160 | goto err_sw_init; | |
5161 | ||
bf069c97 DS |
5162 | /* |
5163 | * If there is a fan on this device and it has failed log the | |
5164 | * failure. | |
5165 | */ | |
5166 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
5167 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
5168 | if (esdp & IXGBE_ESDP_SDP1) | |
5169 | DPRINTK(PROBE, CRIT, | |
5170 | "Fan has stopped, replace the adapter\n"); | |
5171 | } | |
5172 | ||
c44ade9e JB |
5173 | /* reset_hw fills in the perm_addr as well */ |
5174 | err = hw->mac.ops.reset_hw(hw); | |
04f165ef PW |
5175 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { |
5176 | dev_err(&adapter->pdev->dev, "failed to load because an " | |
5177 | "unsupported SFP+ module type was detected.\n"); | |
5178 | goto err_sw_init; | |
5179 | } else if (err) { | |
c44ade9e JB |
5180 | dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err); |
5181 | goto err_sw_init; | |
5182 | } | |
5183 | ||
9a799d71 | 5184 | netdev->features = NETIF_F_SG | |
b4617240 PW |
5185 | NETIF_F_IP_CSUM | |
5186 | NETIF_F_HW_VLAN_TX | | |
5187 | NETIF_F_HW_VLAN_RX | | |
5188 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 5189 | |
e9990a9c | 5190 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 5191 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 5192 | netdev->features |= NETIF_F_TSO6; |
78b6f4ce | 5193 | netdev->features |= NETIF_F_GRO; |
ad31c402 | 5194 | |
45a5ead0 JB |
5195 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
5196 | netdev->features |= NETIF_F_SCTP_CSUM; | |
5197 | ||
ad31c402 JK |
5198 | netdev->vlan_features |= NETIF_F_TSO; |
5199 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 5200 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
ad31c402 JK |
5201 | netdev->vlan_features |= NETIF_F_SG; |
5202 | ||
2f90b865 AD |
5203 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
5204 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
5205 | ||
7a6b6f51 | 5206 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
5207 | netdev->dcbnl_ops = &dcbnl_ops; |
5208 | #endif | |
5209 | ||
eacd73f7 YZ |
5210 | #ifdef IXGBE_FCOE |
5211 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
5212 | if (hw->mac.ops.get_device_caps) { | |
5213 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
5214 | if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) { | |
5215 | netdev->features |= NETIF_F_FCOE_CRC; | |
5216 | netdev->features |= NETIF_F_FSO; | |
332d4a7d | 5217 | netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1; |
eacd73f7 YZ |
5218 | } else { |
5219 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
5220 | } | |
5221 | } | |
5222 | } | |
5223 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
5224 | if (pci_using_dac) |
5225 | netdev->features |= NETIF_F_HIGHDMA; | |
5226 | ||
f8212f97 AD |
5227 | if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) |
5228 | netdev->features |= NETIF_F_LRO; | |
5229 | ||
9a799d71 | 5230 | /* make sure the EEPROM is good */ |
c44ade9e | 5231 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
9a799d71 AK |
5232 | dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); |
5233 | err = -EIO; | |
5234 | goto err_eeprom; | |
5235 | } | |
5236 | ||
5237 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
5238 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
5239 | ||
c44ade9e JB |
5240 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
5241 | dev_err(&pdev->dev, "invalid MAC address\n"); | |
9a799d71 AK |
5242 | err = -EIO; |
5243 | goto err_eeprom; | |
5244 | } | |
5245 | ||
5246 | init_timer(&adapter->watchdog_timer); | |
5247 | adapter->watchdog_timer.function = &ixgbe_watchdog; | |
5248 | adapter->watchdog_timer.data = (unsigned long)adapter; | |
5249 | ||
5250 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 5251 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 5252 | |
021230d4 AV |
5253 | err = ixgbe_init_interrupt_scheme(adapter); |
5254 | if (err) | |
5255 | goto err_sw_init; | |
9a799d71 | 5256 | |
e8e26350 PW |
5257 | switch (pdev->device) { |
5258 | case IXGBE_DEV_ID_82599_KX4: | |
495dce12 WJP |
5259 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | |
5260 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); | |
e8e26350 PW |
5261 | break; |
5262 | default: | |
5263 | adapter->wol = 0; | |
5264 | break; | |
5265 | } | |
5266 | device_init_wakeup(&adapter->pdev->dev, true); | |
5267 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); | |
5268 | ||
04f165ef PW |
5269 | /* pick up the PCI bus settings for reporting later */ |
5270 | hw->mac.ops.get_bus_info(hw); | |
5271 | ||
9a799d71 | 5272 | /* print bus type/speed/width info */ |
7c510e4b | 5273 | dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n", |
e8e26350 PW |
5274 | ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s": |
5275 | (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"), | |
5276 | ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" : | |
5277 | (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" : | |
5278 | (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" : | |
b4617240 | 5279 | "Unknown"), |
7c510e4b | 5280 | netdev->dev_addr); |
c44ade9e | 5281 | ixgbe_read_pba_num_generic(hw, &part_num); |
e8e26350 PW |
5282 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
5283 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n", | |
5284 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, | |
5285 | (part_num >> 8), (part_num & 0xff)); | |
5286 | else | |
5287 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", | |
5288 | hw->mac.type, hw->phy.type, | |
5289 | (part_num >> 8), (part_num & 0xff)); | |
9a799d71 | 5290 | |
e8e26350 | 5291 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
0c254d86 | 5292 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for " |
b4617240 PW |
5293 | "this card is not sufficient for optimal " |
5294 | "performance.\n"); | |
0c254d86 | 5295 | dev_warn(&pdev->dev, "For optimal performance a x8 " |
b4617240 | 5296 | "PCI-Express slot is required.\n"); |
0c254d86 AK |
5297 | } |
5298 | ||
34b0368c PWJ |
5299 | /* save off EEPROM version number */ |
5300 | hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version); | |
5301 | ||
9a799d71 | 5302 | /* reset the hardware with the new settings */ |
c44ade9e JB |
5303 | hw->mac.ops.start_hw(hw); |
5304 | ||
9a799d71 AK |
5305 | strcpy(netdev->name, "eth%d"); |
5306 | err = register_netdev(netdev); | |
5307 | if (err) | |
5308 | goto err_register; | |
5309 | ||
54386467 JB |
5310 | /* carrier off reporting is important to ethtool even BEFORE open */ |
5311 | netif_carrier_off(netdev); | |
5312 | ||
5dd2d332 | 5313 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 5314 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd JC |
5315 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
5316 | /* always use CB2 mode, difference is masked | |
5317 | * in the CB driver */ | |
5318 | IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2); | |
5319 | ixgbe_setup_dca(adapter); | |
5320 | } | |
5321 | #endif | |
0365e6e4 PW |
5322 | /* add san mac addr to netdev */ |
5323 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 AK |
5324 | |
5325 | dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n"); | |
5326 | cards_found++; | |
5327 | return 0; | |
5328 | ||
5329 | err_register: | |
5eba3699 | 5330 | ixgbe_release_hw_control(adapter); |
9a799d71 | 5331 | err_hw_init: |
7a921c93 | 5332 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 AK |
5333 | err_sw_init: |
5334 | err_eeprom: | |
c4900be0 DS |
5335 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
5336 | del_timer_sync(&adapter->sfp_timer); | |
5337 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
5338 | cancel_work_sync(&adapter->multispeed_fiber_task); |
5339 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
5340 | iounmap(hw->hw_addr); |
5341 | err_ioremap: | |
5342 | free_netdev(netdev); | |
5343 | err_alloc_etherdev: | |
9ce77666 | 5344 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
5345 | IORESOURCE_MEM)); | |
9a799d71 AK |
5346 | err_pci_reg: |
5347 | err_dma: | |
5348 | pci_disable_device(pdev); | |
5349 | return err; | |
5350 | } | |
5351 | ||
5352 | /** | |
5353 | * ixgbe_remove - Device Removal Routine | |
5354 | * @pdev: PCI device information struct | |
5355 | * | |
5356 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
5357 | * that it should release a PCI device. The could be caused by a | |
5358 | * Hot-Plug event, or because the driver is going to be removed from | |
5359 | * memory. | |
5360 | **/ | |
5361 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
5362 | { | |
5363 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5364 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6fabd715 | 5365 | int err; |
9a799d71 AK |
5366 | |
5367 | set_bit(__IXGBE_DOWN, &adapter->state); | |
c4900be0 DS |
5368 | /* clear the module not found bit to make sure the worker won't |
5369 | * reschedule | |
5370 | */ | |
5371 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
9a799d71 AK |
5372 | del_timer_sync(&adapter->watchdog_timer); |
5373 | ||
c4900be0 DS |
5374 | del_timer_sync(&adapter->sfp_timer); |
5375 | cancel_work_sync(&adapter->watchdog_task); | |
5376 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
5377 | cancel_work_sync(&adapter->multispeed_fiber_task); |
5378 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
5379 | flush_scheduled_work(); |
5380 | ||
5dd2d332 | 5381 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
5382 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
5383 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
5384 | dca_remove_requester(&pdev->dev); | |
5385 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
5386 | } | |
5387 | ||
5388 | #endif | |
332d4a7d YZ |
5389 | #ifdef IXGBE_FCOE |
5390 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
5391 | ixgbe_cleanup_fcoe(adapter); | |
5392 | ||
5393 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
5394 | |
5395 | /* remove the added san mac */ | |
5396 | ixgbe_del_sanmac_netdev(netdev); | |
5397 | ||
c4900be0 DS |
5398 | if (netdev->reg_state == NETREG_REGISTERED) |
5399 | unregister_netdev(netdev); | |
9a799d71 | 5400 | |
7a921c93 | 5401 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 5402 | |
021230d4 | 5403 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5404 | |
5405 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 5406 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
5407 | IORESOURCE_MEM)); | |
9a799d71 | 5408 | |
021230d4 | 5409 | DPRINTK(PROBE, INFO, "complete\n"); |
021230d4 | 5410 | |
9a799d71 AK |
5411 | free_netdev(netdev); |
5412 | ||
6fabd715 PWJ |
5413 | err = pci_disable_pcie_error_reporting(pdev); |
5414 | if (err) | |
5415 | dev_err(&pdev->dev, | |
5416 | "pci_disable_pcie_error_reporting failed 0x%x\n", err); | |
5417 | ||
9a799d71 AK |
5418 | pci_disable_device(pdev); |
5419 | } | |
5420 | ||
5421 | /** | |
5422 | * ixgbe_io_error_detected - called when PCI error is detected | |
5423 | * @pdev: Pointer to PCI device | |
5424 | * @state: The current pci connection state | |
5425 | * | |
5426 | * This function is called after a PCI bus error affecting | |
5427 | * this device has been detected. | |
5428 | */ | |
5429 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
b4617240 | 5430 | pci_channel_state_t state) |
9a799d71 AK |
5431 | { |
5432 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5433 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
5434 | |
5435 | netif_device_detach(netdev); | |
5436 | ||
3044b8d1 BL |
5437 | if (state == pci_channel_io_perm_failure) |
5438 | return PCI_ERS_RESULT_DISCONNECT; | |
5439 | ||
9a799d71 AK |
5440 | if (netif_running(netdev)) |
5441 | ixgbe_down(adapter); | |
5442 | pci_disable_device(pdev); | |
5443 | ||
b4617240 | 5444 | /* Request a slot reset. */ |
9a799d71 AK |
5445 | return PCI_ERS_RESULT_NEED_RESET; |
5446 | } | |
5447 | ||
5448 | /** | |
5449 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
5450 | * @pdev: Pointer to PCI device | |
5451 | * | |
5452 | * Restart the card from scratch, as if from a cold-boot. | |
5453 | */ | |
5454 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
5455 | { | |
5456 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5457 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
6fabd715 PWJ |
5458 | pci_ers_result_t result; |
5459 | int err; | |
9a799d71 | 5460 | |
9ce77666 | 5461 | if (pci_enable_device_mem(pdev)) { |
9a799d71 | 5462 | DPRINTK(PROBE, ERR, |
b4617240 | 5463 | "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
5464 | result = PCI_ERS_RESULT_DISCONNECT; |
5465 | } else { | |
5466 | pci_set_master(pdev); | |
5467 | pci_restore_state(pdev); | |
9a799d71 | 5468 | |
dd4d8ca6 | 5469 | pci_wake_from_d3(pdev, false); |
9a799d71 | 5470 | |
6fabd715 | 5471 | ixgbe_reset(adapter); |
88512539 | 5472 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
5473 | result = PCI_ERS_RESULT_RECOVERED; |
5474 | } | |
5475 | ||
5476 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
5477 | if (err) { | |
5478 | dev_err(&pdev->dev, | |
5479 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err); | |
5480 | /* non-fatal, continue */ | |
5481 | } | |
9a799d71 | 5482 | |
6fabd715 | 5483 | return result; |
9a799d71 AK |
5484 | } |
5485 | ||
5486 | /** | |
5487 | * ixgbe_io_resume - called when traffic can start flowing again. | |
5488 | * @pdev: Pointer to PCI device | |
5489 | * | |
5490 | * This callback is called when the error recovery driver tells us that | |
5491 | * its OK to resume normal operation. | |
5492 | */ | |
5493 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
5494 | { | |
5495 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5496 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
5497 | |
5498 | if (netif_running(netdev)) { | |
5499 | if (ixgbe_up(adapter)) { | |
5500 | DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n"); | |
5501 | return; | |
5502 | } | |
5503 | } | |
5504 | ||
5505 | netif_device_attach(netdev); | |
9a799d71 AK |
5506 | } |
5507 | ||
5508 | static struct pci_error_handlers ixgbe_err_handler = { | |
5509 | .error_detected = ixgbe_io_error_detected, | |
5510 | .slot_reset = ixgbe_io_slot_reset, | |
5511 | .resume = ixgbe_io_resume, | |
5512 | }; | |
5513 | ||
5514 | static struct pci_driver ixgbe_driver = { | |
5515 | .name = ixgbe_driver_name, | |
5516 | .id_table = ixgbe_pci_tbl, | |
5517 | .probe = ixgbe_probe, | |
5518 | .remove = __devexit_p(ixgbe_remove), | |
5519 | #ifdef CONFIG_PM | |
5520 | .suspend = ixgbe_suspend, | |
5521 | .resume = ixgbe_resume, | |
5522 | #endif | |
5523 | .shutdown = ixgbe_shutdown, | |
5524 | .err_handler = &ixgbe_err_handler | |
5525 | }; | |
5526 | ||
5527 | /** | |
5528 | * ixgbe_init_module - Driver Registration Routine | |
5529 | * | |
5530 | * ixgbe_init_module is the first routine called when the driver is | |
5531 | * loaded. All it does is register with the PCI subsystem. | |
5532 | **/ | |
5533 | static int __init ixgbe_init_module(void) | |
5534 | { | |
5535 | int ret; | |
5536 | printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name, | |
5537 | ixgbe_driver_string, ixgbe_driver_version); | |
5538 | ||
5539 | printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright); | |
5540 | ||
5dd2d332 | 5541 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 5542 | dca_register_notify(&dca_notifier); |
bd0362dd | 5543 | #endif |
5dd2d332 | 5544 | |
9a799d71 AK |
5545 | ret = pci_register_driver(&ixgbe_driver); |
5546 | return ret; | |
5547 | } | |
b4617240 | 5548 | |
9a799d71 AK |
5549 | module_init(ixgbe_init_module); |
5550 | ||
5551 | /** | |
5552 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
5553 | * | |
5554 | * ixgbe_exit_module is called just before the driver is removed | |
5555 | * from memory. | |
5556 | **/ | |
5557 | static void __exit ixgbe_exit_module(void) | |
5558 | { | |
5dd2d332 | 5559 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
5560 | dca_unregister_notify(&dca_notifier); |
5561 | #endif | |
9a799d71 AK |
5562 | pci_unregister_driver(&ixgbe_driver); |
5563 | } | |
bd0362dd | 5564 | |
5dd2d332 | 5565 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 5566 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
b4617240 | 5567 | void *p) |
bd0362dd JC |
5568 | { |
5569 | int ret_val; | |
5570 | ||
5571 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
b4617240 | 5572 | __ixgbe_notify_dca); |
bd0362dd JC |
5573 | |
5574 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
5575 | } | |
b453368d | 5576 | |
5dd2d332 | 5577 | #endif /* CONFIG_IXGBE_DCA */ |
b453368d AD |
5578 | #ifdef DEBUG |
5579 | /** | |
5580 | * ixgbe_get_hw_dev_name - return device name string | |
5581 | * used by hardware layer to print debugging information | |
5582 | **/ | |
5583 | char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw) | |
5584 | { | |
5585 | struct ixgbe_adapter *adapter = hw->back; | |
5586 | return adapter->netdev->name; | |
5587 | } | |
bd0362dd | 5588 | |
b453368d | 5589 | #endif |
9a799d71 AK |
5590 | module_exit(ixgbe_exit_module); |
5591 | ||
5592 | /* ixgbe_main.c */ |