projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
netdevice wanrouter: Convert directly reference of netdev->priv
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
b4617240 4 Copyright(c) 1999 - 2008 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42
43#include "ixgbe.h"
44#include "ixgbe_common.h"
45
46char ixgbe_driver_name[] = "ixgbe";
9c8eb720 47static const char ixgbe_driver_string[] =
b4617240 48 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 49
51ac6445 50#define DRV_VERSION "1.3.30-k2"
9c8eb720 51const char ixgbe_driver_version[] = DRV_VERSION;
b4617240 52static char ixgbe_copyright[] = "Copyright (c) 1999-2007 Intel Corporation.";
9a799d71
AK		 53
54static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 55 [board_82598] = &ixgbe_82598_info,
9a799d71
AK		 56};
57
58/* ixgbe_pci_tbl - PCI Device ID Table
59 *
60 * Wildcard entries (PCI_ANY_ID) should come last
61 * Last entry must be all 0s
62 *
63 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
64 * Class, Class Mask, private data (not used) }
65 */
66static struct pci_device_id ixgbe_pci_tbl[] = {
67 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 68 board_82598 },
9a799d71 69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 70 board_82598 },
0befdb3e
JB		 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 74 board_82598 },
8d792cd9
JB		 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
76 board_82598 },
b95f5fcb
JB		 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
78 board_82598 },
9a799d71
AK		 79
80 /* required last entry */
81 {0, }
82};
83MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
84
5dd2d332 85#ifdef CONFIG_IXGBE_DCA
bd0362dd 86static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 87 void *p);
bd0362dd
JC		 88static struct notifier_block dca_notifier = {
89 .notifier_call = ixgbe_notify_dca,
90 .next = NULL,
91 .priority = 0
92};
93#endif
94
9a799d71
AK		 95MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
96MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
97MODULE_LICENSE("GPL");
98MODULE_VERSION(DRV_VERSION);
99
100#define DEFAULT_DEBUG_LEVEL_SHIFT 3
101
5eba3699
AV		 102static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
103{
104 u32 ctrl_ext;
105
106 /* Let firmware take over control of h/w */
107 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
108 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 109 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 110}
111
112static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
113{
114 u32 ctrl_ext;
115
116 /* Let firmware know the driver has taken over */
117 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
118 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 119 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 120}
9a799d71 121
9a799d71 122static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
b4617240 123 u8 msix_vector)
9a799d71
AK		 124{
125 u32 ivar, index;
126
127 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
128 index = (int_alloc_entry >> 2) & 0x1F;
129 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
130 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
131 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
132 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
133}
134
135static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 136 struct ixgbe_tx_buffer
137 *tx_buffer_info)
9a799d71
AK		 138{
139 if (tx_buffer_info->dma) {
e01c31a5 140 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
b4617240 141 tx_buffer_info->length, PCI_DMA_TODEVICE);
9a799d71
AK		 142 tx_buffer_info->dma = 0;
143 }
144 if (tx_buffer_info->skb) {
145 dev_kfree_skb_any(tx_buffer_info->skb);
146 tx_buffer_info->skb = NULL;
147 }
148 /* tx_buffer_info must be completely set up in the transmit path */
149}
150
151static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 152 struct ixgbe_ring *tx_ring,
153 unsigned int eop)
9a799d71 154{
e01c31a5
JB		 155 struct ixgbe_hw *hw = &adapter->hw;
156 u32 head, tail;
157
9a799d71 158 /* Detect a transmit hang in hardware, this serializes the
e01c31a5
JB		 159 * check with the clearing of time_stamp and movement of eop */
160 head = IXGBE_READ_REG(hw, tx_ring->head);
161 tail = IXGBE_READ_REG(hw, tx_ring->tail);
9a799d71 162 adapter->detect_tx_hung = false;
e01c31a5
JB		 163 if ((head != tail) &&
164 tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 165 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
166 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
167 /* detected Tx unit hang */
e01c31a5
JB		 168 union ixgbe_adv_tx_desc *tx_desc;
169 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 170 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 171 " Tx Queue <%d>\n"
172 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 173 " next_to_use <%x>\n"
174 " next_to_clean <%x>\n"
175 "tx_buffer_info[next_to_clean]\n"
176 " time_stamp <%lx>\n"
e01c31a5
JB		 177 " jiffies <%lx>\n",
178 tx_ring->queue_index,
179 head, tail,
180 tx_ring->next_to_use, eop,
181 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 182 return true;
183 }
184
185 return false;
186}
187
b4617240
PW		 188#define IXGBE_MAX_TXD_PWR 14
189#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 190
191/* Tx Descriptors needed, worst case */
192#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
193 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
194#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 195 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 196
e01c31a5
JB		 197#define GET_TX_HEAD_FROM_RING(ring) (\
198 *(volatile u32 *) \
199 ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count))
200static void ixgbe_tx_timeout(struct net_device *netdev);
201
9a799d71
AK		 202/**
203 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
204 * @adapter: board private structure
e01c31a5 205 * @tx_ring: tx ring to clean
9a799d71
AK		 206 **/
207static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 208 struct ixgbe_ring *tx_ring)
9a799d71 209{
e01c31a5 210 union ixgbe_adv_tx_desc *tx_desc;
9a799d71 211 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5
JB		 212 struct net_device *netdev = adapter->netdev;
213 struct sk_buff *skb;
214 unsigned int i;
215 u32 head, oldhead;
216 unsigned int count = 0;
217 unsigned int total_bytes = 0, total_packets = 0;
9a799d71 218
e01c31a5
JB		 219 rmb();
220 head = GET_TX_HEAD_FROM_RING(tx_ring);
221 head = le32_to_cpu(head);
9a799d71 222 i = tx_ring->next_to_clean;
e01c31a5
JB		 223 while (1) {
224 while (i != head) {
9a799d71
AK		 225 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
226 tx_buffer_info = &tx_ring->tx_buffer_info[i];
e01c31a5 227 skb = tx_buffer_info->skb;
9a799d71 228
e01c31a5 229 if (skb) {
e092be60 230 unsigned int segs, bytecount;
e01c31a5
JB		 231
232 /* gso_segs is currently only valid for tcp */
e092be60
AV		 233 segs = skb_shinfo(skb)->gso_segs ?: 1;
234 /* multiply data chunks by size of headers */
235 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 236 skb->len;
237 total_packets += segs;
238 total_bytes += bytecount;
e092be60 239 }
e01c31a5 240
9a799d71 241 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 242 tx_buffer_info);
9a799d71
AK		 243
244 i++;
245 if (i == tx_ring->count)
246 i = 0;
9a799d71 247
e01c31a5
JB		 248 count++;
249 if (count == tx_ring->count)
250 goto done_cleaning;
251 }
252 oldhead = head;
253 rmb();
254 head = GET_TX_HEAD_FROM_RING(tx_ring);
255 head = le32_to_cpu(head);
256 if (head == oldhead)
257 goto done_cleaning;
258 } /* while (1) */
259
260done_cleaning:
9a799d71
AK		 261 tx_ring->next_to_clean = i;
262
e092be60 263#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 264 if (unlikely(count && netif_carrier_ok(netdev) &&
265 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 266 /* Make sure that anybody stopping the queue after this
267 * sees the new next_to_clean.
268 */
269 smp_mb();
30eba97a
AV		 270 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
271 !test_bit(__IXGBE_DOWN, &adapter->state)) {
272 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 273 ++adapter->restart_queue;
30eba97a 274 }
e092be60 275 }
9a799d71 276
e01c31a5
JB		 277 if (adapter->detect_tx_hung) {
278 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
279 /* schedule immediate reset if we believe we hung */
280 DPRINTK(PROBE, INFO,
281 "tx hang %d detected, resetting adapter\n",
282 adapter->tx_timeout_count + 1);
283 ixgbe_tx_timeout(adapter->netdev);
284 }
285 }
9a799d71 286
e01c31a5
JB		 287 /* re-arm the interrupt */
288 if ((total_packets >= tx_ring->work_limit) ||
289 (count == tx_ring->count))
290 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
9a799d71 291
e01c31a5
JB		 292 tx_ring->total_bytes += total_bytes;
293 tx_ring->total_packets += total_packets;
294 tx_ring->stats.bytes += total_bytes;
295 tx_ring->stats.packets += total_packets;
296 adapter->net_stats.tx_bytes += total_bytes;
297 adapter->net_stats.tx_packets += total_packets;
298 return (total_packets ? true : false);
9a799d71
AK		 299}
300
5dd2d332 301#ifdef CONFIG_IXGBE_DCA
bd0362dd 302static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 303 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 304{
305 u32 rxctrl;
306 int cpu = get_cpu();
3a581073 307 int q = rx_ring - adapter->rx_ring;
bd0362dd 308
3a581073 309 if (rx_ring->cpu != cpu) {
bd0362dd
JC		 310 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
311 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
96b0e0f6 312 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 313 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
314 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
315 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 316 rx_ring->cpu = cpu;
bd0362dd
JC		 317 }
318 put_cpu();
319}
320
321static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 322 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 323{
324 u32 txctrl;
325 int cpu = get_cpu();
3a581073 326 int q = tx_ring - adapter->tx_ring;
bd0362dd 327
3a581073 328 if (tx_ring->cpu != cpu) {
bd0362dd
JC		 329 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
330 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
96b0e0f6 331 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 332 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
333 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 334 tx_ring->cpu = cpu;
bd0362dd
JC		 335 }
336 put_cpu();
337}
338
339static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
340{
341 int i;
342
343 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
344 return;
345
346 for (i = 0; i < adapter->num_tx_queues; i++) {
347 adapter->tx_ring[i].cpu = -1;
348 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
349 }
350 for (i = 0; i < adapter->num_rx_queues; i++) {
351 adapter->rx_ring[i].cpu = -1;
352 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
353 }
354}
355
356static int __ixgbe_notify_dca(struct device *dev, void *data)
357{
358 struct net_device *netdev = dev_get_drvdata(dev);
359 struct ixgbe_adapter *adapter = netdev_priv(netdev);
360 unsigned long event = *(unsigned long *)data;
361
362 switch (event) {
363 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 364 /* if we're already enabled, don't do it again */
365 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
366 break;
bd0362dd
JC		 367 /* Always use CB2 mode, difference is masked
368 * in the CB driver. */
369 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 370 if (dca_add_requester(dev) == 0) {
96b0e0f6 371 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 372 ixgbe_setup_dca(adapter);
373 break;
374 }
375 /* Fall Through since DCA is disabled. */
376 case DCA_PROVIDER_REMOVE:
377 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
378 dca_remove_requester(dev);
379 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
380 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
381 }
382 break;
383 }
384
652f093f 385 return 0;
bd0362dd
JC		 386}
387
5dd2d332 388#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 389/**
390 * ixgbe_receive_skb - Send a completed packet up the stack
391 * @adapter: board private structure
392 * @skb: packet to send up
177db6ff
MC		 393 * @status: hardware indication of status of receive
394 * @rx_ring: rx descriptor ring (for a specific queue) to setup
395 * @rx_desc: rx descriptor
9a799d71
AK		 396 **/
397static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
b4617240
PW		 398 struct sk_buff *skb, u8 status,
399 struct ixgbe_ring *ring,
177db6ff 400 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 401{
177db6ff
MC		 402 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
403 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 404
177db6ff
MC		 405 if (adapter->netdev->features & NETIF_F_LRO &&
406 skb->ip_summed == CHECKSUM_UNNECESSARY) {
9a799d71 407 if (adapter->vlgrp && is_vlan)
177db6ff
MC		 408 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
409 adapter->vlgrp, tag,
410 rx_desc);
9a799d71 411 else
177db6ff
MC		 412 lro_receive_skb(&ring->lro_mgr, skb, rx_desc);
413 ring->lro_used = true;
414 } else {
415 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
416 if (adapter->vlgrp && is_vlan)
417 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
418 else
419 netif_receive_skb(skb);
420 } else {
421 if (adapter->vlgrp && is_vlan)
422 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
423 else
424 netif_rx(skb);
425 }
9a799d71
AK		 426 }
427}
428
e59bd25d
AV		 429/**
430 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
431 * @adapter: address of board private structure
432 * @status_err: hardware indication of status of receive
433 * @skb: skb currently being received and modified
434 **/
9a799d71 435static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 436 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 437{
438 skb->ip_summed = CHECKSUM_NONE;
439
712744be
JB		 440 /* Rx csum disabled */
441 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 442 return;
e59bd25d
AV		 443
444 /* if IP and error */
445 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
446 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 447 adapter->hw_csum_rx_error++;
448 return;
449 }
e59bd25d
AV		 450
451 if (!(status_err & IXGBE_RXD_STAT_L4CS))
452 return;
453
454 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
455 adapter->hw_csum_rx_error++;
456 return;
457 }
458
9a799d71 459 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 460 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 461 adapter->hw_csum_rx_good++;
462}
463
464/**
465 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
466 * @adapter: address of board private structure
467 **/
468static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 469 struct ixgbe_ring *rx_ring,
470 int cleaned_count)
9a799d71 471{
9a799d71
AK		 472 struct pci_dev *pdev = adapter->pdev;
473 union ixgbe_adv_rx_desc *rx_desc;
3a581073 474 struct ixgbe_rx_buffer *bi;
9a799d71 475 unsigned int i;
7c6e0a43 476 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 477
478 i = rx_ring->next_to_use;
3a581073 479 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 480
481 while (cleaned_count--) {
482 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
483
762f4c57 484 if (!bi->page_dma &&
3a581073 485 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 486 if (!bi->page) {
762f4c57
JB		 487 bi->page = alloc_page(GFP_ATOMIC);
488 if (!bi->page) {
489 adapter->alloc_rx_page_failed++;
490 goto no_buffers;
491 }
492 bi->page_offset = 0;
493 } else {
494 /* use a half page if we're re-using */
495 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 496 }
762f4c57
JB		 497
498 bi->page_dma = pci_map_page(pdev, bi->page,
499 bi->page_offset,
500 (PAGE_SIZE / 2),
501 PCI_DMA_FROMDEVICE);
9a799d71
AK		 502 }
503
3a581073 504 if (!bi->skb) {
74ce8dd2
JB		 505 struct sk_buff *skb = netdev_alloc_skb(adapter->netdev,
506 bufsz);
9a799d71
AK		 507
508 if (!skb) {
509 adapter->alloc_rx_buff_failed++;
510 goto no_buffers;
511 }
512
513 /*
514 * Make buffer alignment 2 beyond a 16 byte boundary
515 * this will result in a 16 byte aligned IP header after
516 * the 14 byte MAC header is removed
517 */
518 skb_reserve(skb, NET_IP_ALIGN);
519
3a581073
JB		 520 bi->skb = skb;
521 bi->dma = pci_map_single(pdev, skb->data, bufsz,
522 PCI_DMA_FROMDEVICE);
9a799d71
AK		 523 }
524 /* Refresh the desc even if buffer_addrs didn't change because
525 * each write-back erases this info. */
526 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 527 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
528 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 529 } else {
3a581073 530 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 531 }
532
533 i++;
534 if (i == rx_ring->count)
535 i = 0;
3a581073 536 bi = &rx_ring->rx_buffer_info[i];
9a799d71 537 }
7c6e0a43 538
9a799d71
AK		 539no_buffers:
540 if (rx_ring->next_to_use != i) {
541 rx_ring->next_to_use = i;
542 if (i-- == 0)
543 i = (rx_ring->count - 1);
544
545 /*
546 * Force memory writes to complete before letting h/w
547 * know there are new descriptors to fetch. (Only
548 * applicable for weak-ordered memory model archs,
549 * such as IA-64).
550 */
551 wmb();
552 writel(i, adapter->hw.hw_addr + rx_ring->tail);
553 }
554}
555
7c6e0a43
JB		 556static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
557{
558 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
559}
560
561static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
562{
563 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
564}
565
9a799d71 566static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
b4617240
PW		 567 struct ixgbe_ring *rx_ring,
568 int *work_done, int work_to_do)
9a799d71 569{
9a799d71
AK		 570 struct pci_dev *pdev = adapter->pdev;
571 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
572 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
573 struct sk_buff *skb;
574 unsigned int i;
7c6e0a43 575 u32 len, staterr;
177db6ff
MC		 576 u16 hdr_info;
577 bool cleaned = false;
9a799d71 578 int cleaned_count = 0;
d2f4fbe2 579 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 580
581 i = rx_ring->next_to_clean;
9a799d71
AK		 582 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
583 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
584 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 585
586 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 587 u32 upper_len = 0;
9a799d71
AK		 588 if (*work_done >= work_to_do)
589 break;
590 (*work_done)++;
591
592 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 593 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
594 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 595 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 596 if (hdr_info & IXGBE_RXDADV_SPH)
597 adapter->rx_hdr_split++;
598 if (len > IXGBE_RX_HDR_SIZE)
599 len = IXGBE_RX_HDR_SIZE;
600 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 601 } else {
9a799d71 602 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 603 }
9a799d71
AK		 604
605 cleaned = true;
606 skb = rx_buffer_info->skb;
607 prefetch(skb->data - NET_IP_ALIGN);
608 rx_buffer_info->skb = NULL;
609
610 if (len && !skb_shinfo(skb)->nr_frags) {
611 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 612 rx_ring->rx_buf_len + NET_IP_ALIGN,
613 PCI_DMA_FROMDEVICE);
9a799d71
AK		 614 skb_put(skb, len);
615 }
616
617 if (upper_len) {
618 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 619 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 620 rx_buffer_info->page_dma = 0;
621 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 622 rx_buffer_info->page,
623 rx_buffer_info->page_offset,
624 upper_len);
625
626 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
627 (page_count(rx_buffer_info->page) != 1))
628 rx_buffer_info->page = NULL;
629 else
630 get_page(rx_buffer_info->page);
9a799d71
AK		 631
632 skb->len += upper_len;
633 skb->data_len += upper_len;
634 skb->truesize += upper_len;
635 }
636
637 i++;
638 if (i == rx_ring->count)
639 i = 0;
640 next_buffer = &rx_ring->rx_buffer_info[i];
641
642 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
643 prefetch(next_rxd);
644
645 cleaned_count++;
646 if (staterr & IXGBE_RXD_STAT_EOP) {
647 rx_ring->stats.packets++;
648 rx_ring->stats.bytes += skb->len;
649 } else {
650 rx_buffer_info->skb = next_buffer->skb;
651 rx_buffer_info->dma = next_buffer->dma;
652 next_buffer->skb = skb;
762f4c57 653 next_buffer->dma = 0;
9a799d71
AK		 654 adapter->non_eop_descs++;
655 goto next_desc;
656 }
657
658 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
659 dev_kfree_skb_irq(skb);
660 goto next_desc;
661 }
662
663 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 664
665 /* probably a little skewed due to removing CRC */
666 total_rx_bytes += skb->len;
667 total_rx_packets++;
668
74ce8dd2 669 skb->protocol = eth_type_trans(skb, adapter->netdev);
177db6ff 670 ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 671
672next_desc:
673 rx_desc->wb.upper.status_error = 0;
674
675 /* return some buffers to hardware, one at a time is too slow */
676 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
677 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
678 cleaned_count = 0;
679 }
680
681 /* use prefetched values */
682 rx_desc = next_rxd;
683 rx_buffer_info = next_buffer;
684
685 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 686 }
687
688 if (rx_ring->lro_used) {
689 lro_flush_all(&rx_ring->lro_mgr);
690 rx_ring->lro_used = false;
9a799d71
AK		 691 }
692
693 rx_ring->next_to_clean = i;
694 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
695
696 if (cleaned_count)
697 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
698
f494e8fa
AV		 699 rx_ring->total_packets += total_rx_packets;
700 rx_ring->total_bytes += total_rx_bytes;
701 adapter->net_stats.rx_bytes += total_rx_bytes;
702 adapter->net_stats.rx_packets += total_rx_packets;
703
9a799d71
AK		 704 return cleaned;
705}
706
021230d4 707static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 708/**
709 * ixgbe_configure_msix - Configure MSI-X hardware
710 * @adapter: board private structure
711 *
712 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
713 * interrupts.
714 **/
715static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
716{
021230d4
AV		 717 struct ixgbe_q_vector *q_vector;
718 int i, j, q_vectors, v_idx, r_idx;
719 u32 mask;
9a799d71 720
021230d4 721 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 722
021230d4
AV		 723 /* Populate the IVAR table and set the ITR values to the
724 * corresponding register.
725 */
726 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
727 q_vector = &adapter->q_vector[v_idx];
728 /* XXX for_each_bit(...) */
729 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 730 adapter->num_rx_queues);
021230d4
AV		 731
732 for (i = 0; i < q_vector->rxr_count; i++) {
733 j = adapter->rx_ring[r_idx].reg_idx;
734 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
735 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 736 adapter->num_rx_queues,
737 r_idx + 1);
021230d4
AV		 738 }
739 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 740 adapter->num_tx_queues);
021230d4
AV		 741
742 for (i = 0; i < q_vector->txr_count; i++) {
743 j = adapter->tx_ring[r_idx].reg_idx;
744 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
745 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 746 adapter->num_tx_queues,
747 r_idx + 1);
021230d4
AV		 748 }
749
30efa5a3 750 /* if this is a tx only vector halve the interrupt rate */
021230d4 751 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 752 q_vector->eitr = (adapter->eitr_param >> 1);
021230d4 753 else
30efa5a3
JB		 754 /* rx only */
755 q_vector->eitr = adapter->eitr_param;
021230d4
AV		 756
757 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 758 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 759 }
760
021230d4
AV		 761 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
762 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
763
41fb9248 764 /* set up to autoclear timer, and the vectors */
021230d4 765 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 766 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 767 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 768}
769
f494e8fa
AV		 770enum latency_range {
771 lowest_latency = 0,
772 low_latency = 1,
773 bulk_latency = 2,
774 latency_invalid = 255
775};
776
777/**
778 * ixgbe_update_itr - update the dynamic ITR value based on statistics
779 * @adapter: pointer to adapter
780 * @eitr: eitr setting (ints per sec) to give last timeslice
781 * @itr_setting: current throttle rate in ints/second
782 * @packets: the number of packets during this measurement interval
783 * @bytes: the number of bytes during this measurement interval
784 *
785 * Stores a new ITR value based on packets and byte
786 * counts during the last interrupt. The advantage of per interrupt
787 * computation is faster updates and more accurate ITR for the current
788 * traffic pattern. Constants in this function were computed
789 * based on theoretical maximum wire speed and thresholds were set based
790 * on testing data as well as attempting to minimize response time
791 * while increasing bulk throughput.
792 * this functionality is controlled by the InterruptThrottleRate module
793 * parameter (see ixgbe_param.c)
794 **/
795static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 796 u32 eitr, u8 itr_setting,
797 int packets, int bytes)
f494e8fa
AV		 798{
799 unsigned int retval = itr_setting;
800 u32 timepassed_us;
801 u64 bytes_perint;
802
803 if (packets == 0)
804 goto update_itr_done;
805
806
807 /* simple throttlerate management
808 * 0-20MB/s lowest (100000 ints/s)
809 * 20-100MB/s low (20000 ints/s)
810 * 100-1249MB/s bulk (8000 ints/s)
811 */
812 /* what was last interrupt timeslice? */
813 timepassed_us = 1000000/eitr;
814 bytes_perint = bytes / timepassed_us; /* bytes/usec */
815
816 switch (itr_setting) {
817 case lowest_latency:
818 if (bytes_perint > adapter->eitr_low)
819 retval = low_latency;
820 break;
821 case low_latency:
822 if (bytes_perint > adapter->eitr_high)
823 retval = bulk_latency;
824 else if (bytes_perint <= adapter->eitr_low)
825 retval = lowest_latency;
826 break;
827 case bulk_latency:
828 if (bytes_perint <= adapter->eitr_high)
829 retval = low_latency;
830 break;
831 }
832
833update_itr_done:
834 return retval;
835}
836
837static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
838{
839 struct ixgbe_adapter *adapter = q_vector->adapter;
840 struct ixgbe_hw *hw = &adapter->hw;
841 u32 new_itr;
842 u8 current_itr, ret_itr;
843 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
b4617240 844 sizeof(struct ixgbe_q_vector);
f494e8fa
AV		 845 struct ixgbe_ring *rx_ring, *tx_ring;
846
847 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
848 for (i = 0; i < q_vector->txr_count; i++) {
849 tx_ring = &(adapter->tx_ring[r_idx]);
850 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 851 q_vector->tx_itr,
852 tx_ring->total_packets,
853 tx_ring->total_bytes);
f494e8fa
AV		 854 /* if the result for this queue would decrease interrupt
855 * rate for this vector then use that result */
30efa5a3 856 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 857 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 858 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 859 r_idx + 1);
f494e8fa
AV		 860 }
861
862 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
863 for (i = 0; i < q_vector->rxr_count; i++) {
864 rx_ring = &(adapter->rx_ring[r_idx]);
865 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 866 q_vector->rx_itr,
867 rx_ring->total_packets,
868 rx_ring->total_bytes);
f494e8fa
AV		 869 /* if the result for this queue would decrease interrupt
870 * rate for this vector then use that result */
30efa5a3 871 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 872 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 873 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 874 r_idx + 1);
f494e8fa
AV		 875 }
876
30efa5a3 877 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 878
879 switch (current_itr) {
880 /* counts and packets in update_itr are dependent on these numbers */
881 case lowest_latency:
882 new_itr = 100000;
883 break;
884 case low_latency:
885 new_itr = 20000; /* aka hwitr = ~200 */
886 break;
887 case bulk_latency:
888 default:
889 new_itr = 8000;
890 break;
891 }
892
893 if (new_itr != q_vector->eitr) {
894 u32 itr_reg;
895 /* do an exponential smoothing */
896 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
897 q_vector->eitr = new_itr;
898 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
899 /* must write high and low 16 bits to reset counter */
900 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
b4617240 901 itr_reg);
f494e8fa
AV		 902 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
903 }
904
905 return;
906}
907
0befdb3e
JB		 908static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
909{
910 struct ixgbe_hw *hw = &adapter->hw;
911
912 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
913 (eicr & IXGBE_EICR_GPI_SDP1)) {
914 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
915 /* write to clear the interrupt */
916 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
917 }
918}
cf8280ee
JB		 919
920static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
921{
922 struct ixgbe_hw *hw = &adapter->hw;
923
924 adapter->lsc_int++;
925 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
926 adapter->link_check_timeout = jiffies;
927 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
928 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
929 schedule_work(&adapter->watchdog_task);
930 }
931}
932
9a799d71
AK		 933static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
934{
935 struct net_device *netdev = data;
936 struct ixgbe_adapter *adapter = netdev_priv(netdev);
937 struct ixgbe_hw *hw = &adapter->hw;
938 u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
939
cf8280ee
JB		 940 if (eicr & IXGBE_EICR_LSC)
941 ixgbe_check_lsc(adapter);
d4f80882 942
0befdb3e
JB		 943 ixgbe_check_fan_failure(adapter, eicr);
944
d4f80882
AV		 945 if (!test_bit(__IXGBE_DOWN, &adapter->state))
946 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 947
948 return IRQ_HANDLED;
949}
950
951static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
952{
021230d4
AV		 953 struct ixgbe_q_vector *q_vector = data;
954 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 955 struct ixgbe_ring *tx_ring;
021230d4
AV		 956 int i, r_idx;
957
958 if (!q_vector->txr_count)
959 return IRQ_HANDLED;
960
961 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
962 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 963 tx_ring = &(adapter->tx_ring[r_idx]);
5dd2d332 964#ifdef CONFIG_IXGBE_DCA
bd0362dd 965 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 966 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 967#endif
3a581073
JB		 968 tx_ring->total_bytes = 0;
969 tx_ring->total_packets = 0;
970 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 971 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 972 r_idx + 1);
021230d4 973 }
9a799d71 974
9a799d71
AK		 975 return IRQ_HANDLED;
976}
977
021230d4
AV		 978/**
979 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
980 * @irq: unused
981 * @data: pointer to our q_vector struct for this interrupt vector
982 **/
9a799d71
AK		 983static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
984{
021230d4
AV		 985 struct ixgbe_q_vector *q_vector = data;
986 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 987 struct ixgbe_ring *rx_ring;
021230d4 988 int r_idx;
30efa5a3 989 int i;
021230d4
AV		 990
991 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 992 for (i = 0; i < q_vector->rxr_count; i++) {
993 rx_ring = &(adapter->rx_ring[r_idx]);
994 rx_ring->total_bytes = 0;
995 rx_ring->total_packets = 0;
996 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
997 r_idx + 1);
998 }
999
021230d4
AV		 1000 if (!q_vector->rxr_count)
1001 return IRQ_HANDLED;
1002
30efa5a3 1003 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1004 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1005 /* disable interrupts on this vector only */
3a581073 1006 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
021230d4
AV		 1007 netif_rx_schedule(adapter->netdev, &q_vector->napi);
1008
1009 return IRQ_HANDLED;
1010}
1011
1012static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1013{
1014 ixgbe_msix_clean_rx(irq, data);
1015 ixgbe_msix_clean_tx(irq, data);
9a799d71 1016
9a799d71
AK		 1017 return IRQ_HANDLED;
1018}
1019
021230d4
AV		 1020/**
1021 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1022 * @napi: napi struct with our devices info in it
1023 * @budget: amount of work driver is allowed to do this pass, in packets
1024 *
f0848276
JB		 1025 * This function is optimized for cleaning one queue only on a single
1026 * q_vector!!!
021230d4 1027 **/
9a799d71
AK		 1028static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1029{
021230d4 1030 struct ixgbe_q_vector *q_vector =
b4617240 1031 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1032 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1033 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1034 int work_done = 0;
021230d4 1035 long r_idx;
9a799d71 1036
021230d4 1037 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1038 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1039#ifdef CONFIG_IXGBE_DCA
bd0362dd 1040 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1041 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1042#endif
9a799d71 1043
3a581073 1044 ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
9a799d71 1045
021230d4
AV		 1046 /* If all Rx work done, exit the polling mode */
1047 if (work_done < budget) {
1048 netif_rx_complete(adapter->netdev, napi);
30efa5a3 1049 if (adapter->itr_setting & 3)
f494e8fa 1050 ixgbe_set_itr_msix(q_vector);
9a799d71 1051 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3a581073 1052 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
9a799d71
AK		 1053 }
1054
1055 return work_done;
1056}
1057
f0848276
JB		 1058/**
1059 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1060 * @napi: napi struct with our devices info in it
1061 * @budget: amount of work driver is allowed to do this pass, in packets
1062 *
1063 * This function will clean more than one rx queue associated with a
1064 * q_vector.
1065 **/
1066static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1067{
1068 struct ixgbe_q_vector *q_vector =
1069 container_of(napi, struct ixgbe_q_vector, napi);
1070 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1071 struct ixgbe_ring *rx_ring = NULL;
1072 int work_done = 0, i;
1073 long r_idx;
1074 u16 enable_mask = 0;
1075
1076 /* attempt to distribute budget to each queue fairly, but don't allow
1077 * the budget to go below 1 because we'll exit polling */
1078 budget /= (q_vector->rxr_count ?: 1);
1079 budget = max(budget, 1);
1080 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1081 for (i = 0; i < q_vector->rxr_count; i++) {
1082 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1083#ifdef CONFIG_IXGBE_DCA
f0848276
JB		 1084 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1085 ixgbe_update_rx_dca(adapter, rx_ring);
1086#endif
1087 ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
1088 enable_mask |= rx_ring->v_idx;
1089 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1090 r_idx + 1);
1091 }
1092
1093 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1094 rx_ring = &(adapter->rx_ring[r_idx]);
1095 /* If all Rx work done, exit the polling mode */
7f821875 1096 if (work_done < budget) {
74ce8dd2 1097 netif_rx_complete(adapter->netdev, napi);
f0848276
JB		 1098 if (adapter->itr_setting & 3)
1099 ixgbe_set_itr_msix(q_vector);
1100 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1101 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1102 return 0;
1103 }
1104
1105 return work_done;
1106}
021230d4 1107static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1108 int r_idx)
021230d4
AV		 1109{
1110 a->q_vector[v_idx].adapter = a;
1111 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1112 a->q_vector[v_idx].rxr_count++;
1113 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1114}
1115
1116static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
b4617240 1117 int r_idx)
021230d4
AV		 1118{
1119 a->q_vector[v_idx].adapter = a;
1120 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1121 a->q_vector[v_idx].txr_count++;
1122 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1123}
1124
9a799d71 1125/**
021230d4
AV		 1126 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1127 * @adapter: board private structure to initialize
1128 * @vectors: allotted vector count for descriptor rings
9a799d71 1129 *
021230d4
AV		 1130 * This function maps descriptor rings to the queue-specific vectors
1131 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1132 * one vector per ring/queue, but on a constrained vector budget, we
1133 * group the rings as "efficiently" as possible. You would add new
1134 * mapping configurations in here.
9a799d71 1135 **/
021230d4 1136static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1137 int vectors)
021230d4
AV		 1138{
1139 int v_start = 0;
1140 int rxr_idx = 0, txr_idx = 0;
1141 int rxr_remaining = adapter->num_rx_queues;
1142 int txr_remaining = adapter->num_tx_queues;
1143 int i, j;
1144 int rqpv, tqpv;
1145 int err = 0;
1146
1147 /* No mapping required if MSI-X is disabled. */
1148 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1149 goto out;
9a799d71 1150
021230d4
AV		 1151 /*
1152 * The ideal configuration...
1153 * We have enough vectors to map one per queue.
1154 */
1155 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1156 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1157 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1158
021230d4
AV		 1159 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1160 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1161
9a799d71 1162 goto out;
021230d4 1163 }
9a799d71 1164
021230d4
AV		 1165 /*
1166 * If we don't have enough vectors for a 1-to-1
1167 * mapping, we'll have to group them so there are
1168 * multiple queues per vector.
1169 */
1170 /* Re-adjusting *qpv takes care of the remainder. */
1171 for (i = v_start; i < vectors; i++) {
1172 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1173 for (j = 0; j < rqpv; j++) {
1174 map_vector_to_rxq(adapter, i, rxr_idx);
1175 rxr_idx++;
1176 rxr_remaining--;
1177 }
1178 }
1179 for (i = v_start; i < vectors; i++) {
1180 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1181 for (j = 0; j < tqpv; j++) {
1182 map_vector_to_txq(adapter, i, txr_idx);
1183 txr_idx++;
1184 txr_remaining--;
9a799d71 1185 }
9a799d71
AK		 1186 }
1187
021230d4
AV		 1188out:
1189 return err;
1190}
1191
1192/**
1193 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1194 * @adapter: board private structure
1195 *
1196 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1197 * interrupts from the kernel.
1198 **/
1199static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1200{
1201 struct net_device *netdev = adapter->netdev;
1202 irqreturn_t (*handler)(int, void *);
1203 int i, vector, q_vectors, err;
1204
1205 /* Decrement for Other and TCP Timer vectors */
1206 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1207
1208 /* Map the Tx/Rx rings to the vectors we were allotted. */
1209 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1210 if (err)
1211 goto out;
1212
1213#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1214 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1215 &ixgbe_msix_clean_many)
021230d4
AV		 1216 for (vector = 0; vector < q_vectors; vector++) {
1217 handler = SET_HANDLER(&adapter->q_vector[vector]);
1218 sprintf(adapter->name[vector], "%s:v%d-%s",
b4617240
PW		 1219 netdev->name, vector,
1220 (handler == &ixgbe_msix_clean_rx) ? "Rx" :
1221 ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx"));
021230d4 1222 err = request_irq(adapter->msix_entries[vector].vector,
b4617240
PW		 1223 handler, 0, adapter->name[vector],
1224 &(adapter->q_vector[vector]));
9a799d71
AK		 1225 if (err) {
1226 DPRINTK(PROBE, ERR,
b4617240
PW		 1227 "request_irq failed for MSIX interrupt "
1228 "Error: %d\n", err);
021230d4 1229 goto free_queue_irqs;
9a799d71 1230 }
9a799d71
AK		 1231 }
1232
021230d4
AV		 1233 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1234 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1235 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1236 if (err) {
1237 DPRINTK(PROBE, ERR,
1238 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1239 goto free_queue_irqs;
9a799d71
AK		 1240 }
1241
9a799d71
AK		 1242 return 0;
1243
021230d4
AV		 1244free_queue_irqs:
1245 for (i = vector - 1; i >= 0; i--)
1246 free_irq(adapter->msix_entries[--vector].vector,
b4617240 1247 &(adapter->q_vector[i]));
021230d4
AV		 1248 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1249 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1250 kfree(adapter->msix_entries);
1251 adapter->msix_entries = NULL;
021230d4 1252out:
9a799d71
AK		 1253 return err;
1254}
1255
f494e8fa
AV		 1256static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1257{
1258 struct ixgbe_hw *hw = &adapter->hw;
1259 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1260 u8 current_itr;
1261 u32 new_itr = q_vector->eitr;
1262 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1263 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1264
30efa5a3 1265 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1266 q_vector->tx_itr,
1267 tx_ring->total_packets,
1268 tx_ring->total_bytes);
30efa5a3 1269 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1270 q_vector->rx_itr,
1271 rx_ring->total_packets,
1272 rx_ring->total_bytes);
f494e8fa 1273
30efa5a3 1274 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1275
1276 switch (current_itr) {
1277 /* counts and packets in update_itr are dependent on these numbers */
1278 case lowest_latency:
1279 new_itr = 100000;
1280 break;
1281 case low_latency:
1282 new_itr = 20000; /* aka hwitr = ~200 */
1283 break;
1284 case bulk_latency:
1285 new_itr = 8000;
1286 break;
1287 default:
1288 break;
1289 }
1290
1291 if (new_itr != q_vector->eitr) {
1292 u32 itr_reg;
1293 /* do an exponential smoothing */
1294 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1295 q_vector->eitr = new_itr;
1296 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1297 /* must write high and low 16 bits to reset counter */
1298 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1299 }
1300
1301 return;
1302}
1303
021230d4
AV		 1304static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter);
1305
9a799d71 1306/**
021230d4 1307 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1308 * @irq: interrupt number
1309 * @data: pointer to a network interface device structure
1310 * @pt_regs: CPU registers structure
1311 **/
1312static irqreturn_t ixgbe_intr(int irq, void *data)
1313{
1314 struct net_device *netdev = data;
1315 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1316 struct ixgbe_hw *hw = &adapter->hw;
1317 u32 eicr;
1318
021230d4
AV		 1319 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1320 * therefore no explict interrupt disable is necessary */
1321 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1322 if (!eicr) {
1323 /* shared interrupt alert!
1324 * make sure interrupts are enabled because the read will
1325 * have disabled interrupts due to EIAM */
1326 ixgbe_irq_enable(adapter);
9a799d71 1327 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1328 }
9a799d71 1329
cf8280ee
JB		 1330 if (eicr & IXGBE_EICR_LSC)
1331 ixgbe_check_lsc(adapter);
021230d4 1332
0befdb3e
JB		 1333 ixgbe_check_fan_failure(adapter, eicr);
1334
021230d4 1335 if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) {
f494e8fa
AV		 1336 adapter->tx_ring[0].total_packets = 0;
1337 adapter->tx_ring[0].total_bytes = 0;
1338 adapter->rx_ring[0].total_packets = 0;
1339 adapter->rx_ring[0].total_bytes = 0;
021230d4
AV		 1340 /* would disable interrupts here but EIAM disabled it */
1341 __netif_rx_schedule(netdev, &adapter->q_vector[0].napi);
9a799d71
AK		 1342 }
1343
1344 return IRQ_HANDLED;
1345}
1346
021230d4
AV		 1347static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1348{
1349 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1350
1351 for (i = 0; i < q_vectors; i++) {
1352 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1353 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1354 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1355 q_vector->rxr_count = 0;
1356 q_vector->txr_count = 0;
1357 }
1358}
1359
9a799d71
AK		 1360/**
1361 * ixgbe_request_irq - initialize interrupts
1362 * @adapter: board private structure
1363 *
1364 * Attempts to configure interrupts using the best available
1365 * capabilities of the hardware and kernel.
1366 **/
021230d4 1367static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1368{
1369 struct net_device *netdev = adapter->netdev;
021230d4 1370 int err;
9a799d71 1371
021230d4
AV		 1372 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1373 err = ixgbe_request_msix_irqs(adapter);
1374 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1375 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1376 netdev->name, netdev);
021230d4
AV		 1377 } else {
1378 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1379 netdev->name, netdev);
9a799d71
AK		 1380 }
1381
9a799d71
AK		 1382 if (err)
1383 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1384
9a799d71
AK		 1385 return err;
1386}
1387
1388static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1389{
1390 struct net_device *netdev = adapter->netdev;
1391
1392 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1393 int i, q_vectors;
9a799d71 1394
021230d4
AV		 1395 q_vectors = adapter->num_msix_vectors;
1396
1397 i = q_vectors - 1;
9a799d71 1398 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1399
021230d4
AV		 1400 i--;
1401 for (; i >= 0; i--) {
1402 free_irq(adapter->msix_entries[i].vector,
b4617240 1403 &(adapter->q_vector[i]));
021230d4
AV		 1404 }
1405
1406 ixgbe_reset_q_vectors(adapter);
1407 } else {
1408 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1409 }
1410}
1411
1412/**
1413 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1414 * @adapter: board private structure
1415 **/
1416static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1417{
9a799d71
AK		 1418 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1419 IXGBE_WRITE_FLUSH(&adapter->hw);
021230d4
AV		 1420 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1421 int i;
1422 for (i = 0; i < adapter->num_msix_vectors; i++)
1423 synchronize_irq(adapter->msix_entries[i].vector);
1424 } else {
1425 synchronize_irq(adapter->pdev->irq);
1426 }
9a799d71
AK		 1427}
1428
1429/**
1430 * ixgbe_irq_enable - Enable default interrupt generation settings
1431 * @adapter: board private structure
1432 **/
1433static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1434{
021230d4
AV		 1435 u32 mask;
1436 mask = IXGBE_EIMS_ENABLE_MASK;
0befdb3e
JB		 1437 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1438 mask |= IXGBE_EIMS_GPI_SDP1;
021230d4 1439 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
d4f80882 1440 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1441}
1442
1443/**
1444 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1445 *
1446 **/
1447static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1448{
9a799d71
AK		 1449 struct ixgbe_hw *hw = &adapter->hw;
1450
021230d4 1451 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1452 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71
AK		 1453
1454 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
021230d4
AV		 1455 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1456
1457 map_vector_to_rxq(adapter, 0, 0);
1458 map_vector_to_txq(adapter, 0, 0);
1459
1460 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1461}
1462
1463/**
3a581073 1464 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1465 * @adapter: board private structure
1466 *
1467 * Configure the Tx unit of the MAC after a reset.
1468 **/
1469static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1470{
e01c31a5 1471 u64 tdba, tdwba;
9a799d71 1472 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1473 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1474
1475 /* Setup the HW Tx Head and Tail descriptor pointers */
1476 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1477 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1478 j = ring->reg_idx;
1479 tdba = ring->dma;
1480 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1481 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
e01c31a5 1482 (tdba & DMA_32BIT_MASK));
021230d4 1483 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
e01c31a5
JB		 1484 tdwba = ring->dma +
1485 (ring->count * sizeof(union ixgbe_adv_tx_desc));
1486 tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE;
1487 IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK);
1488 IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32));
021230d4
AV		 1489 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1490 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1491 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1492 adapter->tx_ring[i].head = IXGBE_TDH(j);
1493 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1494 /* Disable Tx Head Writeback RO bit, since this hoses
1495 * bookkeeping if things aren't delivered in order.
1496 */
e01c31a5 1497 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1498 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1499 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1500 }
9a799d71
AK		 1501}
1502
cc41ac7c
JB		 1503#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1504
1505static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1506{
1507 struct ixgbe_ring *rx_ring;
1508 u32 srrctl;
1509 int queue0;
3be1adfb
AD		 1510 unsigned long mask;
1511
1512 /* program one srrctl register per VMDq index */
1513 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
1514 long shift, len;
1515 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1516 len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8;
1517 shift = find_first_bit(&mask, len);
1518 queue0 = index & mask;
1519 index = (index & mask) >> shift;
1520 /* program one srrctl per RSS queue since RDRXCTL.MVMEN is enabled */
cc41ac7c 1521 } else {
3be1adfb
AD		 1522 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1523 queue0 = index & mask;
1524 index = index & mask;
cc41ac7c 1525 }
3be1adfb 1526
cc41ac7c
JB		 1527 rx_ring = &adapter->rx_ring[queue0];
1528
1529 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1530
1531 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1532 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1533
1534 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1535 srrctl |= IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1536 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1537 srrctl |= ((IXGBE_RX_HDR_SIZE <<
b4617240
PW		 1538 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1539 IXGBE_SRRCTL_BSIZEHDR_MASK);
cc41ac7c
JB		 1540 } else {
1541 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1542
1543 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1544 srrctl |= IXGBE_RXBUFFER_2048 >>
1545 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1546 else
1547 srrctl |= rx_ring->rx_buf_len >>
1548 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1549 }
1550 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1551}
9a799d71 1552
177db6ff
MC		 1553/**
1554 * ixgbe_get_skb_hdr - helper function for LRO header processing
1555 * @skb: pointer to sk_buff to be added to LRO packet
b4617240 1556 * @iphdr: pointer to ip header structure
177db6ff
MC		 1557 * @tcph: pointer to tcp header structure
1558 * @hdr_flags: pointer to header flags
1559 * @priv: private data
1560 **/
1561static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
1562 u64 *hdr_flags, void *priv)
1563{
1564 union ixgbe_adv_rx_desc *rx_desc = priv;
1565
1566 /* Verify that this is a valid IPv4 TCP packet */
e9990a9c
JB		 1567 if (!((ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_IPV4) &&
1568 (ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_TCP)))
177db6ff
MC		 1569 return -1;
1570
1571 /* Set network headers */
1572 skb_reset_network_header(skb);
1573 skb_set_transport_header(skb, ip_hdrlen(skb));
1574 *iphdr = ip_hdr(skb);
1575 *tcph = tcp_hdr(skb);
1576 *hdr_flags = LRO_IPV4 | LRO_TCP;
1577 return 0;
1578}
1579
cc41ac7c 1580#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
b4617240 1581 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
cc41ac7c 1582
9a799d71 1583/**
3a581073 1584 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1585 * @adapter: board private structure
1586 *
1587 * Configure the Rx unit of the MAC after a reset.
1588 **/
1589static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1590{
1591 u64 rdba;
1592 struct ixgbe_hw *hw = &adapter->hw;
1593 struct net_device *netdev = adapter->netdev;
1594 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1595 int i, j;
9a799d71 1596 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1597 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1598 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1599 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1600 u32 fctrl, hlreg0;
9a799d71 1601 u32 pages;
cc41ac7c
JB		 1602 u32 reta = 0, mrqc;
1603 u32 rdrxctl;
7c6e0a43 1604 int rx_buf_len;
9a799d71
AK		 1605
1606 /* Decide whether to use packet split mode or not */
762f4c57 1607 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1608
1609 /* Set the RX buffer length according to the mode */
1610 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1611 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71
AK		 1612 } else {
1613 if (netdev->mtu <= ETH_DATA_LEN)
7c6e0a43 1614 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1615 else
7c6e0a43 1616 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1617 }
1618
1619 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1620 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1621 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
9a799d71
AK		 1622 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1623
1624 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1625 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1626 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1627 else
1628 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1629 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1630
1631 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1632
9a799d71
AK		 1633 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1634 /* disable receives while setting up the descriptors */
1635 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1636 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1637
1638 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1639 * the Base and Length of the Rx Descriptor Ring */
1640 for (i = 0; i < adapter->num_rx_queues; i++) {
1641 rdba = adapter->rx_ring[i].dma;
7c6e0a43
JB		 1642 j = adapter->rx_ring[i].reg_idx;
1643 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1644 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1645 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1646 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1647 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1648 adapter->rx_ring[i].head = IXGBE_RDH(j);
1649 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1650 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
e9990a9c
JB		 1651 /* Intitial LRO Settings */
1652 adapter->rx_ring[i].lro_mgr.max_aggr = IXGBE_MAX_LRO_AGGREGATE;
1653 adapter->rx_ring[i].lro_mgr.max_desc = IXGBE_MAX_LRO_DESCRIPTORS;
1654 adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr;
1655 adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID;
1656 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1657 adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI;
1658 adapter->rx_ring[i].lro_mgr.dev = adapter->netdev;
1659 adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1660 adapter->rx_ring[i].lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
cc41ac7c
JB		 1661
1662 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1663 }
1664
cc41ac7c
JB		 1665 /*
1666 * For VMDq support of different descriptor types or
1667 * buffer sizes through the use of multiple SRRCTL
1668 * registers, RDRXCTL.MVMEN must be set to 1
1669 *
1670 * also, the manual doesn't mention it clearly but DCA hints
1671 * will only use queue 0's tags unless this bit is set. Side
1672 * effects of setting this bit are only that SRRCTL must be
1673 * fully programmed [0..15]
1674 */
1675 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1676 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1677 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1678
177db6ff 1679
021230d4 1680 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1681 /* Fill out redirection table */
021230d4
AV		 1682 for (i = 0, j = 0; i < 128; i++, j++) {
1683 if (j == adapter->ring_feature[RING_F_RSS].indices)
1684 j = 0;
1685 /* reta = 4-byte sliding window of
1686 * 0x00..(indices-1)(indices-1)00..etc. */
1687 reta = (reta << 8) | (j * 0x11);
1688 if ((i & 3) == 3)
1689 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1690 }
1691
1692 /* Fill out hash function seeds */
1693 for (i = 0; i < 10; i++)
7c6e0a43 1694 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71
AK		 1695
1696 mrqc = IXGBE_MRQC_RSSEN
1697 /* Perform hash on these packet types */
7c6e0a43
JB		 1698 | IXGBE_MRQC_RSS_FIELD_IPV4
1699 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1700 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1701 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1702 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1703 | IXGBE_MRQC_RSS_FIELD_IPV6
1704 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1705 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1706 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
9a799d71 1707 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
021230d4 1708 }
9a799d71 1709
021230d4
AV		 1710 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1711
1712 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1713 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1714 /* Disable indicating checksum in descriptor, enables
1715 * RSS hash */
9a799d71 1716 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1717 }
021230d4
AV		 1718 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1719 /* Enable IPv4 payload checksum for UDP fragments
1720 * if PCSD is not set */
1721 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1722 }
1723
1724 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
9a799d71
AK		 1725}
1726
1727static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 1728 struct vlan_group *grp)
9a799d71
AK		 1729{
1730 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1731 u32 ctrl;
1732
d4f80882
AV		 1733 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1734 ixgbe_irq_disable(adapter);
9a799d71
AK		 1735 adapter->vlgrp = grp;
1736
1737 if (grp) {
1738 /* enable VLAN tag insert/strip */
1739 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
746b9f02 1740 ctrl |= IXGBE_VLNCTRL_VME;
9a799d71
AK		 1741 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1742 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1743 }
1744
d4f80882
AV		 1745 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1746 ixgbe_irq_enable(adapter);
9a799d71
AK		 1747}
1748
1749static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1750{
1751 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1752 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 1753
1754 /* add VID to filter table */
c44ade9e 1755 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
9a799d71
AK		 1756}
1757
1758static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1759{
1760 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1761 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 1762
d4f80882
AV		 1763 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1764 ixgbe_irq_disable(adapter);
1765
9a799d71 1766 vlan_group_set_device(adapter->vlgrp, vid, NULL);
d4f80882
AV		 1767
1768 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1769 ixgbe_irq_enable(adapter);
9a799d71
AK		 1770
1771 /* remove VID from filter table */
c44ade9e 1772 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
9a799d71
AK		 1773}
1774
1775static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1776{
1777 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1778
1779 if (adapter->vlgrp) {
1780 u16 vid;
1781 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1782 if (!vlan_group_get_device(adapter->vlgrp, vid))
1783 continue;
1784 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1785 }
1786 }
1787}
1788
2c5645cf
CL		 1789static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1790{
1791 struct dev_mc_list *mc_ptr;
1792 u8 *addr = *mc_addr_ptr;
1793 *vmdq = 0;
1794
1795 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1796 if (mc_ptr->next)
1797 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1798 else
1799 *mc_addr_ptr = NULL;
1800
1801 return addr;
1802}
1803
9a799d71 1804/**
2c5645cf 1805 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 1806 * @netdev: network interface device structure
1807 *
2c5645cf
CL		 1808 * The set_rx_method entry point is called whenever the unicast/multicast
1809 * address list or the network interface flags are updated. This routine is
1810 * responsible for configuring the hardware for proper unicast, multicast and
1811 * promiscuous mode.
9a799d71 1812 **/
2c5645cf 1813static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 1814{
1815 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1816 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 1817 u32 fctrl, vlnctrl;
2c5645cf
CL		 1818 u8 *addr_list = NULL;
1819 int addr_count = 0;
9a799d71
AK		 1820
1821 /* Check for Promiscuous and All Multicast modes */
1822
1823 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 1824 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 1825
1826 if (netdev->flags & IFF_PROMISC) {
2c5645cf 1827 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 1828 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 1829 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 1830 } else {
746b9f02
PM		 1831 if (netdev->flags & IFF_ALLMULTI) {
1832 fctrl |= IXGBE_FCTRL_MPE;
1833 fctrl &= ~IXGBE_FCTRL_UPE;
1834 } else {
1835 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1836 }
3d01625a 1837 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 1838 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 1839 }
1840
1841 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 1842 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 1843
2c5645cf
CL		 1844 /* reprogram secondary unicast list */
1845 addr_count = netdev->uc_count;
1846 if (addr_count)
1847 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 1848 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
1849 ixgbe_addr_list_itr);
9a799d71 1850
2c5645cf
CL		 1851 /* reprogram multicast list */
1852 addr_count = netdev->mc_count;
1853 if (addr_count)
1854 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 1855 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
1856 ixgbe_addr_list_itr);
9a799d71
AK		 1857}
1858
021230d4
AV		 1859static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1860{
1861 int q_idx;
1862 struct ixgbe_q_vector *q_vector;
1863 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1864
1865 /* legacy and MSI only use one vector */
1866 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1867 q_vectors = 1;
1868
1869 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 1870 struct napi_struct *napi;
021230d4
AV		 1871 q_vector = &adapter->q_vector[q_idx];
1872 if (!q_vector->rxr_count)
1873 continue;
f0848276
JB		 1874 napi = &q_vector->napi;
1875 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
1876 (q_vector->rxr_count > 1))
1877 napi->poll = &ixgbe_clean_rxonly_many;
1878
1879 napi_enable(napi);
021230d4
AV		 1880 }
1881}
1882
1883static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1884{
1885 int q_idx;
1886 struct ixgbe_q_vector *q_vector;
1887 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1888
1889 /* legacy and MSI only use one vector */
1890 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1891 q_vectors = 1;
1892
1893 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1894 q_vector = &adapter->q_vector[q_idx];
1895 if (!q_vector->rxr_count)
1896 continue;
1897 napi_disable(&q_vector->napi);
1898 }
1899}
1900
9a799d71
AK		 1901static void ixgbe_configure(struct ixgbe_adapter *adapter)
1902{
1903 struct net_device *netdev = adapter->netdev;
1904 int i;
1905
2c5645cf 1906 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 1907
1908 ixgbe_restore_vlan(adapter);
1909
1910 ixgbe_configure_tx(adapter);
1911 ixgbe_configure_rx(adapter);
1912 for (i = 0; i < adapter->num_rx_queues; i++)
1913 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 1914 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 1915}
1916
1917static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1918{
1919 struct net_device *netdev = adapter->netdev;
9a799d71 1920 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1921 int i, j = 0;
9a799d71 1922 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4
AV		 1923 u32 txdctl, rxdctl, mhadd;
1924 u32 gpie;
9a799d71 1925
5eba3699
AV		 1926 ixgbe_get_hw_control(adapter);
1927
021230d4
AV		 1928 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1929 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 1930 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1931 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 1932 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 1933 } else {
1934 /* MSI only */
021230d4 1935 gpie = 0;
9a799d71 1936 }
021230d4
AV		 1937 /* XXX: to interrupt immediately for EICS writes, enable this */
1938 /* gpie |= IXGBE_GPIE_EIMEN; */
1939 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 1940 }
1941
021230d4
AV		 1942 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1943 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1944 * specifically only auto mask tx and rx interrupts */
1945 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1946 }
9a799d71 1947
0befdb3e
JB		 1948 /* Enable fan failure interrupt if media type is copper */
1949 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
1950 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
1951 gpie |= IXGBE_SDP1_GPIEN;
1952 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
1953 }
1954
021230d4 1955 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 1956 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1957 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1958 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
1959
1960 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
1961 }
1962
1963 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 1964 j = adapter->tx_ring[i].reg_idx;
1965 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 1966 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
1967 txdctl |= (8 << 16);
9a799d71 1968 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 1969 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 1970 }
1971
1972 for (i = 0; i < adapter->num_rx_queues; i++) {
021230d4
AV		 1973 j = adapter->rx_ring[i].reg_idx;
1974 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
1975 /* enable PTHRESH=32 descriptors (half the internal cache)
1976 * and HTHRESH=0 descriptors (to minimize latency on fetch),
1977 * this also removes a pesky rx_no_buffer_count increment */
1978 rxdctl |= 0x0020;
9a799d71 1979 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 1980 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
9a799d71
AK		 1981 }
1982 /* enable all receives */
1983 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1984 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
1985 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
1986
1987 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1988 ixgbe_configure_msix(adapter);
1989 else
1990 ixgbe_configure_msi_and_legacy(adapter);
1991
1992 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 1993 ixgbe_napi_enable_all(adapter);
1994
1995 /* clear any pending interrupts, may auto mask */
1996 IXGBE_READ_REG(hw, IXGBE_EICR);
1997
9a799d71
AK		 1998 ixgbe_irq_enable(adapter);
1999
74ad0a54
PW		 2000 /* enable transmits */
2001 netif_tx_start_all_queues(netdev);
2002
9a799d71
AK		 2003 /* bring the link up in the watchdog, this could race with our first
2004 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2005 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2006 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2007 mod_timer(&adapter->watchdog_timer, jiffies);
2008 return 0;
2009}
2010
d4f80882
AV		 2011void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2012{
2013 WARN_ON(in_interrupt());
2014 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2015 msleep(1);
2016 ixgbe_down(adapter);
2017 ixgbe_up(adapter);
2018 clear_bit(__IXGBE_RESETTING, &adapter->state);
2019}
2020
9a799d71
AK		 2021int ixgbe_up(struct ixgbe_adapter *adapter)
2022{
2023 /* hardware has been reset, we need to reload some things */
2024 ixgbe_configure(adapter);
2025
2026 return ixgbe_up_complete(adapter);
2027}
2028
2029void ixgbe_reset(struct ixgbe_adapter *adapter)
2030{
c44ade9e
JB		 2031 struct ixgbe_hw *hw = &adapter->hw;
2032 if (hw->mac.ops.init_hw(hw))
2033 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2034
2035 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2036 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2037
2038}
2039
9a799d71
AK		 2040/**
2041 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2042 * @adapter: board private structure
2043 * @rx_ring: ring to free buffers from
2044 **/
2045static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2046 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2047{
2048 struct pci_dev *pdev = adapter->pdev;
2049 unsigned long size;
2050 unsigned int i;
2051
2052 /* Free all the Rx ring sk_buffs */
2053
2054 for (i = 0; i < rx_ring->count; i++) {
2055 struct ixgbe_rx_buffer *rx_buffer_info;
2056
2057 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2058 if (rx_buffer_info->dma) {
2059 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2060 rx_ring->rx_buf_len,
2061 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2062 rx_buffer_info->dma = 0;
2063 }
2064 if (rx_buffer_info->skb) {
2065 dev_kfree_skb(rx_buffer_info->skb);
2066 rx_buffer_info->skb = NULL;
2067 }
2068 if (!rx_buffer_info->page)
2069 continue;
762f4c57
JB		 2070 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2071 PCI_DMA_FROMDEVICE);
9a799d71 2072 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2073 put_page(rx_buffer_info->page);
2074 rx_buffer_info->page = NULL;
762f4c57 2075 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2076 }
2077
2078 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2079 memset(rx_ring->rx_buffer_info, 0, size);
2080
2081 /* Zero out the descriptor ring */
2082 memset(rx_ring->desc, 0, rx_ring->size);
2083
2084 rx_ring->next_to_clean = 0;
2085 rx_ring->next_to_use = 0;
2086
2087 writel(0, adapter->hw.hw_addr + rx_ring->head);
2088 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2089}
2090
2091/**
2092 * ixgbe_clean_tx_ring - Free Tx Buffers
2093 * @adapter: board private structure
2094 * @tx_ring: ring to be cleaned
2095 **/
2096static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2097 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2098{
2099 struct ixgbe_tx_buffer *tx_buffer_info;
2100 unsigned long size;
2101 unsigned int i;
2102
2103 /* Free all the Tx ring sk_buffs */
2104
2105 for (i = 0; i < tx_ring->count; i++) {
2106 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2107 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2108 }
2109
2110 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2111 memset(tx_ring->tx_buffer_info, 0, size);
2112
2113 /* Zero out the descriptor ring */
2114 memset(tx_ring->desc, 0, tx_ring->size);
2115
2116 tx_ring->next_to_use = 0;
2117 tx_ring->next_to_clean = 0;
2118
2119 writel(0, adapter->hw.hw_addr + tx_ring->head);
2120 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2121}
2122
2123/**
021230d4 2124 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2125 * @adapter: board private structure
2126 **/
021230d4 2127static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2128{
2129 int i;
2130
021230d4
AV		 2131 for (i = 0; i < adapter->num_rx_queues; i++)
2132 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2133}
2134
2135/**
021230d4 2136 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2137 * @adapter: board private structure
2138 **/
021230d4 2139static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2140{
2141 int i;
2142
021230d4
AV		 2143 for (i = 0; i < adapter->num_tx_queues; i++)
2144 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2145}
2146
2147void ixgbe_down(struct ixgbe_adapter *adapter)
2148{
2149 struct net_device *netdev = adapter->netdev;
7f821875 2150 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2151 u32 rxctrl;
7f821875
JB		 2152 u32 txdctl;
2153 int i, j;
9a799d71
AK		 2154
2155 /* signal that we are down to the interrupt handler */
2156 set_bit(__IXGBE_DOWN, &adapter->state);
2157
2158 /* disable receives */
7f821875
JB		 2159 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2160 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2161
2162 netif_tx_disable(netdev);
2163
7f821875 2164 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2165 msleep(10);
2166
7f821875
JB		 2167 netif_tx_stop_all_queues(netdev);
2168
9a799d71
AK		 2169 ixgbe_irq_disable(adapter);
2170
021230d4 2171 ixgbe_napi_disable_all(adapter);
7f821875 2172
9a799d71 2173 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2174 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2175
7f821875
JB		 2176 /* disable transmits in the hardware now that interrupts are off */
2177 for (i = 0; i < adapter->num_tx_queues; i++) {
2178 j = adapter->tx_ring[i].reg_idx;
2179 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2180 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2181 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2182 }
2183
9a799d71 2184 netif_carrier_off(netdev);
9a799d71 2185
5dd2d332 2186#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2187 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2188 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2189 dca_remove_requester(&adapter->pdev->dev);
2190 }
2191
2192#endif
6f4a0e45
PL		 2193 if (!pci_channel_offline(adapter->pdev))
2194 ixgbe_reset(adapter);
9a799d71
AK		 2195 ixgbe_clean_all_tx_rings(adapter);
2196 ixgbe_clean_all_rx_rings(adapter);
2197
5dd2d332 2198#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2199 /* since we reset the hardware DCA settings were cleared */
2200 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2201 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2202 /* always use CB2 mode, difference is masked
2203 * in the CB driver */
b4617240 2204 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
96b0e0f6
JB		 2205 ixgbe_setup_dca(adapter);
2206 }
2207#endif
9a799d71
AK		 2208}
2209
9a799d71 2210/**
021230d4
AV		 2211 * ixgbe_poll - NAPI Rx polling callback
2212 * @napi: structure for representing this polling device
2213 * @budget: how many packets driver is allowed to clean
2214 *
2215 * This function is used for legacy and MSI, NAPI mode
9a799d71 2216 **/
021230d4 2217static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2218{
021230d4 2219 struct ixgbe_q_vector *q_vector = container_of(napi,
b4617240 2220 struct ixgbe_q_vector, napi);
021230d4 2221 struct ixgbe_adapter *adapter = q_vector->adapter;
74ce8dd2 2222 int tx_cleaned, work_done = 0;
9a799d71 2223
5dd2d332 2224#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2225 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2226 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2227 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2228 }
2229#endif
2230
d2c7ddd6 2231 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
021230d4 2232 ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget);
9a799d71 2233
d2c7ddd6
DM		 2234 if (tx_cleaned)
2235 work_done = budget;
2236
53e52c72
DM		 2237 /* If budget not fully consumed, exit the polling mode */
2238 if (work_done < budget) {
021230d4 2239 netif_rx_complete(adapter->netdev, napi);
30efa5a3 2240 if (adapter->itr_setting & 3)
f494e8fa 2241 ixgbe_set_itr(adapter);
d4f80882
AV		 2242 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2243 ixgbe_irq_enable(adapter);
9a799d71 2244 }
9a799d71
AK		 2245 return work_done;
2246}
2247
2248/**
2249 * ixgbe_tx_timeout - Respond to a Tx Hang
2250 * @netdev: network interface device structure
2251 **/
2252static void ixgbe_tx_timeout(struct net_device *netdev)
2253{
2254 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2255
2256 /* Do the reset outside of interrupt context */
2257 schedule_work(&adapter->reset_task);
2258}
2259
2260static void ixgbe_reset_task(struct work_struct *work)
2261{
2262 struct ixgbe_adapter *adapter;
2263 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2264
2265 adapter->tx_timeout_count++;
2266
d4f80882 2267 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2268}
2269
b9804972
JB		 2270static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2271{
2272 int nrq = 1, ntq = 1;
2273 int feature_mask = 0, rss_i, rss_m;
2274
2275 /* Number of supported queues */
2276 switch (adapter->hw.mac.type) {
2277 case ixgbe_mac_82598EB:
2278 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2279 rss_m = 0;
2280 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2281
2282 switch (adapter->flags & feature_mask) {
2283 case (IXGBE_FLAG_RSS_ENABLED):
2284 rss_m = 0xF;
2285 nrq = rss_i;
2286 ntq = rss_i;
2287 break;
2288 case 0:
2289 default:
2290 rss_i = 0;
2291 rss_m = 0;
2292 nrq = 1;
2293 ntq = 1;
2294 break;
2295 }
2296
2297 adapter->ring_feature[RING_F_RSS].indices = rss_i;
2298 adapter->ring_feature[RING_F_RSS].mask = rss_m;
2299 break;
2300 default:
2301 nrq = 1;
2302 ntq = 1;
2303 break;
2304 }
2305
2306 adapter->num_rx_queues = nrq;
2307 adapter->num_tx_queues = ntq;
2308}
2309
021230d4 2310static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2311 int vectors)
021230d4
AV		 2312{
2313 int err, vector_threshold;
2314
2315 /* We'll want at least 3 (vector_threshold):
2316 * 1) TxQ[0] Cleanup
2317 * 2) RxQ[0] Cleanup
2318 * 3) Other (Link Status Change, etc.)
2319 * 4) TCP Timer (optional)
2320 */
2321 vector_threshold = MIN_MSIX_COUNT;
2322
2323 /* The more we get, the more we will assign to Tx/Rx Cleanup
2324 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2325 * Right now, we simply care about how many we'll get; we'll
2326 * set them up later while requesting irq's.
2327 */
2328 while (vectors >= vector_threshold) {
2329 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2330 vectors);
021230d4
AV		 2331 if (!err) /* Success in acquiring all requested vectors. */
2332 break;
2333 else if (err < 0)
2334 vectors = 0; /* Nasty failure, quit now */
2335 else /* err == number of vectors we should try again with */
2336 vectors = err;
2337 }
2338
2339 if (vectors < vector_threshold) {
2340 /* Can't allocate enough MSI-X interrupts? Oh well.
2341 * This just means we'll go with either a single MSI
2342 * vector or fall back to legacy interrupts.
2343 */
2344 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2345 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2346 kfree(adapter->msix_entries);
2347 adapter->msix_entries = NULL;
2348 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
b9804972 2349 ixgbe_set_num_queues(adapter);
021230d4
AV		 2350 } else {
2351 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2352 adapter->num_msix_vectors = vectors;
2353 }
2354}
2355
021230d4
AV		 2356/**
2357 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2358 * @adapter: board private structure to initialize
2359 *
2360 * Once we know the feature-set enabled for the device, we'll cache
2361 * the register offset the descriptor ring is assigned to.
2362 **/
2363static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2364{
021230d4
AV		 2365 int feature_mask = 0, rss_i;
2366 int i, txr_idx, rxr_idx;
2367
2368 /* Number of supported queues */
2369 switch (adapter->hw.mac.type) {
2370 case ixgbe_mac_82598EB:
2371 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2372 txr_idx = 0;
2373 rxr_idx = 0;
2374 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2375 switch (adapter->flags & feature_mask) {
2376 case (IXGBE_FLAG_RSS_ENABLED):
2377 for (i = 0; i < adapter->num_rx_queues; i++)
2378 adapter->rx_ring[i].reg_idx = i;
2379 for (i = 0; i < adapter->num_tx_queues; i++)
2380 adapter->tx_ring[i].reg_idx = i;
2381 break;
2382 case 0:
2383 default:
2384 break;
2385 }
2386 break;
2387 default:
2388 break;
2389 }
2390}
2391
9a799d71
AK		 2392/**
2393 * ixgbe_alloc_queues - Allocate memory for all rings
2394 * @adapter: board private structure to initialize
2395 *
2396 * We allocate one ring per queue at run-time since we don't know the
2397 * number of queues at compile-time. The polling_netdev array is
2398 * intended for Multiqueue, but should work fine with a single queue.
2399 **/
2400static int __devinit ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2401{
2402 int i;
2403
2404 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 2405 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 2406 if (!adapter->tx_ring)
021230d4 2407 goto err_tx_ring_allocation;
9a799d71
AK		 2408
2409 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 2410 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 2411 if (!adapter->rx_ring)
2412 goto err_rx_ring_allocation;
9a799d71 2413
021230d4 2414 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 2415 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 2416 adapter->tx_ring[i].queue_index = i;
2417 }
b9804972 2418
9a799d71 2419 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 2420 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 2421 adapter->rx_ring[i].queue_index = i;
2422 }
2423
2424 ixgbe_cache_ring_register(adapter);
2425
2426 return 0;
2427
2428err_rx_ring_allocation:
2429 kfree(adapter->tx_ring);
2430err_tx_ring_allocation:
2431 return -ENOMEM;
2432}
2433
2434/**
2435 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2436 * @adapter: board private structure to initialize
2437 *
2438 * Attempt to configure the interrupts using the best available
2439 * capabilities of the hardware and the kernel.
2440 **/
2441static int __devinit ixgbe_set_interrupt_capability(struct ixgbe_adapter
b4617240 2442 *adapter)
021230d4
AV		 2443{
2444 int err = 0;
2445 int vector, v_budget;
2446
2447 /*
2448 * It's easy to be greedy for MSI-X vectors, but it really
2449 * doesn't do us much good if we have a lot more vectors
2450 * than CPU's. So let's be conservative and only ask for
2451 * (roughly) twice the number of vectors as there are CPU's.
2452 */
2453 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 2454 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 2455
2456 /*
2457 * At the same time, hardware can only support a maximum of
2458 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2459 * we can easily reach upwards of 64 Rx descriptor queues and
2460 * 32 Tx queues. Thus, we cap it off in those rare cases where
2461 * the cpu count also exceeds our vector limit.
2462 */
2463 v_budget = min(v_budget, MAX_MSIX_COUNT);
2464
2465 /* A failure in MSI-X entry allocation isn't fatal, but it does
2466 * mean we disable MSI-X capabilities of the adapter. */
2467 adapter->msix_entries = kcalloc(v_budget,
b4617240 2468 sizeof(struct msix_entry), GFP_KERNEL);
021230d4
AV		 2469 if (!adapter->msix_entries) {
2470 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2471 ixgbe_set_num_queues(adapter);
2472 kfree(adapter->tx_ring);
2473 kfree(adapter->rx_ring);
2474 err = ixgbe_alloc_queues(adapter);
2475 if (err) {
2476 DPRINTK(PROBE, ERR, "Unable to allocate memory "
b4617240 2477 "for queues\n");
021230d4
AV		 2478 goto out;
2479 }
2480
2481 goto try_msi;
2482 }
2483
2484 for (vector = 0; vector < v_budget; vector++)
2485 adapter->msix_entries[vector].entry = vector;
2486
2487 ixgbe_acquire_msix_vectors(adapter, v_budget);
2488
2489 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2490 goto out;
2491
2492try_msi:
2493 err = pci_enable_msi(adapter->pdev);
2494 if (!err) {
2495 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2496 } else {
2497 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 2498 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 2499 /* reset err */
2500 err = 0;
2501 }
2502
2503out:
30eba97a 2504 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 2505 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
021230d4
AV		 2506
2507 return err;
2508}
2509
2510static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2511{
2512 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2513 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2514 pci_disable_msix(adapter->pdev);
2515 kfree(adapter->msix_entries);
2516 adapter->msix_entries = NULL;
2517 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2518 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2519 pci_disable_msi(adapter->pdev);
2520 }
2521 return;
2522}
2523
2524/**
2525 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2526 * @adapter: board private structure to initialize
2527 *
2528 * We determine which interrupt scheme to use based on...
2529 * - Kernel support (MSI, MSI-X)
2530 * - which can be user-defined (via MODULE_PARAM)
2531 * - Hardware queue count (num_*_queues)
2532 * - defined by miscellaneous hardware support/features (RSS, etc.)
2533 **/
2534static int __devinit ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2535{
2536 int err;
2537
2538 /* Number of supported queues */
2539 ixgbe_set_num_queues(adapter);
2540
2541 err = ixgbe_alloc_queues(adapter);
2542 if (err) {
2543 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2544 goto err_alloc_queues;
2545 }
2546
2547 err = ixgbe_set_interrupt_capability(adapter);
2548 if (err) {
2549 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2550 goto err_set_interrupt;
9a799d71
AK		 2551 }
2552
021230d4 2553 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 2554 "Tx Queue count = %u\n",
2555 (adapter->num_rx_queues > 1) ? "Enabled" :
2556 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 2557
2558 set_bit(__IXGBE_DOWN, &adapter->state);
2559
9a799d71 2560 return 0;
021230d4
AV		 2561
2562err_set_interrupt:
2563 kfree(adapter->tx_ring);
2564 kfree(adapter->rx_ring);
2565err_alloc_queues:
2566 return err;
9a799d71
AK		 2567}
2568
2569/**
2570 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2571 * @adapter: board private structure to initialize
2572 *
2573 * ixgbe_sw_init initializes the Adapter private data structure.
2574 * Fields are initialized based on PCI device information and
2575 * OS network device settings (MTU size).
2576 **/
2577static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2578{
2579 struct ixgbe_hw *hw = &adapter->hw;
2580 struct pci_dev *pdev = adapter->pdev;
021230d4
AV		 2581 unsigned int rss;
2582
c44ade9e
JB		 2583 /* PCI config space info */
2584
2585 hw->vendor_id = pdev->vendor;
2586 hw->device_id = pdev->device;
2587 hw->revision_id = pdev->revision;
2588 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2589 hw->subsystem_device_id = pdev->subsystem_device;
2590
021230d4
AV		 2591 /* Set capability flags */
2592 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2593 adapter->ring_feature[RING_F_RSS].indices = rss;
2594 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
0befdb3e
JB		 2595 if (hw->mac.ops.get_media_type &&
2596 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper))
2597 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
9a799d71
AK		 2598
2599 /* default flow control settings */
2b9ade93
JB		 2600 hw->fc.original_type = ixgbe_fc_none;
2601 hw->fc.type = ixgbe_fc_none;
2602 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2603 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2604 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2605 hw->fc.send_xon = true;
9a799d71 2606
021230d4 2607 /* select 10G link by default */
9a799d71 2608 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
9a799d71 2609
30efa5a3
JB		 2610 /* enable itr by default in dynamic mode */
2611 adapter->itr_setting = 1;
2612 adapter->eitr_param = 20000;
2613
2614 /* set defaults for eitr in MegaBytes */
2615 adapter->eitr_low = 10;
2616 adapter->eitr_high = 20;
2617
2618 /* set default ring sizes */
2619 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
2620 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
2621
9a799d71 2622 /* initialize eeprom parameters */
c44ade9e 2623 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 2624 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2625 return -EIO;
2626 }
2627
021230d4 2628 /* enable rx csum by default */
9a799d71
AK		 2629 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2630
9a799d71
AK		 2631 set_bit(__IXGBE_DOWN, &adapter->state);
2632
2633 return 0;
2634}
2635
2636/**
2637 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2638 * @adapter: board private structure
3a581073 2639 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2640 *
2641 * Return 0 on success, negative on failure
2642 **/
2643int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 2644 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2645{
2646 struct pci_dev *pdev = adapter->pdev;
2647 int size;
2648
3a581073
JB		 2649 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2650 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 2651 if (!tx_ring->tx_buffer_info)
2652 goto err;
3a581073 2653 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 2654
2655 /* round up to nearest 4K */
e01c31a5
JB		 2656 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) +
2657 sizeof(u32);
3a581073 2658 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 2659
3a581073
JB		 2660 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2661 &tx_ring->dma);
e01c31a5
JB		 2662 if (!tx_ring->desc)
2663 goto err;
9a799d71 2664
3a581073
JB		 2665 tx_ring->next_to_use = 0;
2666 tx_ring->next_to_clean = 0;
2667 tx_ring->work_limit = tx_ring->count;
9a799d71 2668 return 0;
e01c31a5
JB		 2669
2670err:
2671 vfree(tx_ring->tx_buffer_info);
2672 tx_ring->tx_buffer_info = NULL;
2673 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
2674 "descriptor ring\n");
2675 return -ENOMEM;
9a799d71
AK		 2676}
2677
69888674
AD		 2678/**
2679 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
2680 * @adapter: board private structure
2681 *
2682 * If this function returns with an error, then it's possible one or
2683 * more of the rings is populated (while the rest are not). It is the
2684 * callers duty to clean those orphaned rings.
2685 *
2686 * Return 0 on success, negative on failure
2687 **/
2688static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2689{
2690 int i, err = 0;
2691
2692 for (i = 0; i < adapter->num_tx_queues; i++) {
2693 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2694 if (!err)
2695 continue;
2696 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
2697 break;
2698 }
2699
2700 return err;
2701}
2702
9a799d71
AK		 2703/**
2704 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2705 * @adapter: board private structure
3a581073 2706 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2707 *
2708 * Returns 0 on success, negative on failure
2709 **/
2710int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 2711 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2712{
2713 struct pci_dev *pdev = adapter->pdev;
021230d4 2714 int size;
9a799d71 2715
177db6ff 2716 size = sizeof(struct net_lro_desc) * IXGBE_MAX_LRO_DESCRIPTORS;
3a581073
JB		 2717 rx_ring->lro_mgr.lro_arr = vmalloc(size);
2718 if (!rx_ring->lro_mgr.lro_arr)
177db6ff 2719 return -ENOMEM;
3a581073 2720 memset(rx_ring->lro_mgr.lro_arr, 0, size);
177db6ff 2721
3a581073
JB		 2722 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2723 rx_ring->rx_buffer_info = vmalloc(size);
2724 if (!rx_ring->rx_buffer_info) {
9a799d71 2725 DPRINTK(PROBE, ERR,
b4617240 2726 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 2727 goto alloc_failed;
9a799d71 2728 }
3a581073 2729 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 2730
9a799d71 2731 /* Round up to nearest 4K */
3a581073
JB		 2732 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2733 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 2734
3a581073 2735 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 2736
3a581073 2737 if (!rx_ring->desc) {
9a799d71 2738 DPRINTK(PROBE, ERR,
b4617240 2739 "Memory allocation failed for the rx desc ring\n");
3a581073 2740 vfree(rx_ring->rx_buffer_info);
177db6ff 2741 goto alloc_failed;
9a799d71
AK		 2742 }
2743
3a581073
JB		 2744 rx_ring->next_to_clean = 0;
2745 rx_ring->next_to_use = 0;
9a799d71
AK		 2746
2747 return 0;
177db6ff
MC		 2748
2749alloc_failed:
3a581073
JB		 2750 vfree(rx_ring->lro_mgr.lro_arr);
2751 rx_ring->lro_mgr.lro_arr = NULL;
177db6ff 2752 return -ENOMEM;
9a799d71
AK		 2753}
2754
69888674
AD		 2755/**
2756 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
2757 * @adapter: board private structure
2758 *
2759 * If this function returns with an error, then it's possible one or
2760 * more of the rings is populated (while the rest are not). It is the
2761 * callers duty to clean those orphaned rings.
2762 *
2763 * Return 0 on success, negative on failure
2764 **/
2765
2766static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2767{
2768 int i, err = 0;
2769
2770 for (i = 0; i < adapter->num_rx_queues; i++) {
2771 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2772 if (!err)
2773 continue;
2774 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
2775 break;
2776 }
2777
2778 return err;
2779}
2780
9a799d71
AK		 2781/**
2782 * ixgbe_free_tx_resources - Free Tx Resources per Queue
2783 * @adapter: board private structure
2784 * @tx_ring: Tx descriptor ring for a specific queue
2785 *
2786 * Free all transmit software resources
2787 **/
c431f97e
JB		 2788void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
2789 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2790{
2791 struct pci_dev *pdev = adapter->pdev;
2792
2793 ixgbe_clean_tx_ring(adapter, tx_ring);
2794
2795 vfree(tx_ring->tx_buffer_info);
2796 tx_ring->tx_buffer_info = NULL;
2797
2798 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2799
2800 tx_ring->desc = NULL;
2801}
2802
2803/**
2804 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2805 * @adapter: board private structure
2806 *
2807 * Free all transmit software resources
2808 **/
2809static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
2810{
2811 int i;
2812
2813 for (i = 0; i < adapter->num_tx_queues; i++)
2814 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
2815}
2816
2817/**
b4617240 2818 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 2819 * @adapter: board private structure
2820 * @rx_ring: ring to clean the resources from
2821 *
2822 * Free all receive software resources
2823 **/
c431f97e
JB		 2824void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2825 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2826{
2827 struct pci_dev *pdev = adapter->pdev;
2828
177db6ff
MC		 2829 vfree(rx_ring->lro_mgr.lro_arr);
2830 rx_ring->lro_mgr.lro_arr = NULL;
2831
9a799d71
AK		 2832 ixgbe_clean_rx_ring(adapter, rx_ring);
2833
2834 vfree(rx_ring->rx_buffer_info);
2835 rx_ring->rx_buffer_info = NULL;
2836
2837 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2838
2839 rx_ring->desc = NULL;
2840}
2841
2842/**
2843 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
2844 * @adapter: board private structure
2845 *
2846 * Free all receive software resources
2847 **/
2848static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
2849{
2850 int i;
2851
2852 for (i = 0; i < adapter->num_rx_queues; i++)
2853 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
2854}
2855
9a799d71
AK		 2856/**
2857 * ixgbe_change_mtu - Change the Maximum Transfer Unit
2858 * @netdev: network interface device structure
2859 * @new_mtu: new value for maximum frame size
2860 *
2861 * Returns 0 on success, negative on failure
2862 **/
2863static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
2864{
2865 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2866 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2867
42c783c5
JB		 2868 /* MTU < 68 is an error and causes problems on some kernels */
2869 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 2870 return -EINVAL;
2871
021230d4 2872 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 2873 netdev->mtu, new_mtu);
021230d4 2874 /* must set new MTU before calling down or up */
9a799d71
AK		 2875 netdev->mtu = new_mtu;
2876
d4f80882
AV		 2877 if (netif_running(netdev))
2878 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2879
2880 return 0;
2881}
2882
2883/**
2884 * ixgbe_open - Called when a network interface is made active
2885 * @netdev: network interface device structure
2886 *
2887 * Returns 0 on success, negative value on failure
2888 *
2889 * The open entry point is called when a network interface is made
2890 * active by the system (IFF_UP). At this point all resources needed
2891 * for transmit and receive operations are allocated, the interrupt
2892 * handler is registered with the OS, the watchdog timer is started,
2893 * and the stack is notified that the interface is ready.
2894 **/
2895static int ixgbe_open(struct net_device *netdev)
2896{
2897 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2898 int err;
4bebfaa5
AK		 2899
2900 /* disallow open during test */
2901 if (test_bit(__IXGBE_TESTING, &adapter->state))
2902 return -EBUSY;
9a799d71 2903
9a799d71
AK		 2904 /* allocate transmit descriptors */
2905 err = ixgbe_setup_all_tx_resources(adapter);
2906 if (err)
2907 goto err_setup_tx;
2908
9a799d71
AK		 2909 /* allocate receive descriptors */
2910 err = ixgbe_setup_all_rx_resources(adapter);
2911 if (err)
2912 goto err_setup_rx;
2913
2914 ixgbe_configure(adapter);
2915
021230d4 2916 err = ixgbe_request_irq(adapter);
9a799d71
AK		 2917 if (err)
2918 goto err_req_irq;
2919
9a799d71
AK		 2920 err = ixgbe_up_complete(adapter);
2921 if (err)
2922 goto err_up;
2923
d55b53ff
JK		 2924 netif_tx_start_all_queues(netdev);
2925
9a799d71
AK		 2926 return 0;
2927
2928err_up:
5eba3699 2929 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2930 ixgbe_free_irq(adapter);
2931err_req_irq:
2932 ixgbe_free_all_rx_resources(adapter);
2933err_setup_rx:
2934 ixgbe_free_all_tx_resources(adapter);
2935err_setup_tx:
2936 ixgbe_reset(adapter);
2937
2938 return err;
2939}
2940
2941/**
2942 * ixgbe_close - Disables a network interface
2943 * @netdev: network interface device structure
2944 *
2945 * Returns 0, this is not allowed to fail
2946 *
2947 * The close entry point is called when an interface is de-activated
2948 * by the OS. The hardware is still under the drivers control, but
2949 * needs to be disabled. A global MAC reset is issued to stop the
2950 * hardware, and all transmit and receive resources are freed.
2951 **/
2952static int ixgbe_close(struct net_device *netdev)
2953{
2954 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 2955
2956 ixgbe_down(adapter);
2957 ixgbe_free_irq(adapter);
2958
2959 ixgbe_free_all_tx_resources(adapter);
2960 ixgbe_free_all_rx_resources(adapter);
2961
5eba3699 2962 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2963
2964 return 0;
2965}
2966
b3c8b4ba
AD		 2967/**
2968 * ixgbe_napi_add_all - prep napi structs for use
2969 * @adapter: private struct
2970 * helper function to napi_add each possible q_vector->napi
2971 */
2972static void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
2973{
2974 int q_idx, q_vectors;
2975 int (*poll)(struct napi_struct *, int);
2976
2977 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2978 poll = &ixgbe_clean_rxonly;
2979 /* Only enable as many vectors as we have rx queues. */
2980 q_vectors = adapter->num_rx_queues;
2981 } else {
2982 poll = &ixgbe_poll;
2983 /* only one q_vector for legacy modes */
2984 q_vectors = 1;
2985 }
2986
2987 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2988 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
2989 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
2990 }
2991}
2992
2993static void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
2994{
2995 int q_idx;
2996 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2997
2998 /* legacy and MSI only use one vector */
2999 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3000 q_vectors = 1;
3001
3002 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3003 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3004 if (!q_vector->rxr_count)
3005 continue;
3006 netif_napi_del(&q_vector->napi);
3007 }
3008}
3009
3010#ifdef CONFIG_PM
3011static int ixgbe_resume(struct pci_dev *pdev)
3012{
3013 struct net_device *netdev = pci_get_drvdata(pdev);
3014 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3015 u32 err;
3016
3017 pci_set_power_state(pdev, PCI_D0);
3018 pci_restore_state(pdev);
3019 err = pci_enable_device(pdev);
3020 if (err) {
69888674 3021 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 3022 "suspend\n");
3023 return err;
3024 }
3025 pci_set_master(pdev);
3026
3027 pci_enable_wake(pdev, PCI_D3hot, 0);
3028 pci_enable_wake(pdev, PCI_D3cold, 0);
3029
3030 err = ixgbe_init_interrupt_scheme(adapter);
3031 if (err) {
3032 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3033 "device\n");
3034 return err;
3035 }
3036
3037 ixgbe_napi_add_all(adapter);
3038 ixgbe_reset(adapter);
3039
3040 if (netif_running(netdev)) {
3041 err = ixgbe_open(adapter->netdev);
3042 if (err)
3043 return err;
3044 }
3045
3046 netif_device_attach(netdev);
3047
3048 return 0;
3049}
3050
3051#endif /* CONFIG_PM */
3052static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3053{
3054 struct net_device *netdev = pci_get_drvdata(pdev);
3055 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3056#ifdef CONFIG_PM
3057 int retval = 0;
3058#endif
3059
3060 netif_device_detach(netdev);
3061
3062 if (netif_running(netdev)) {
3063 ixgbe_down(adapter);
3064 ixgbe_free_irq(adapter);
3065 ixgbe_free_all_tx_resources(adapter);
3066 ixgbe_free_all_rx_resources(adapter);
3067 }
3068 ixgbe_reset_interrupt_capability(adapter);
3069 ixgbe_napi_del_all(adapter);
3070 kfree(adapter->tx_ring);
3071 kfree(adapter->rx_ring);
3072
3073#ifdef CONFIG_PM
3074 retval = pci_save_state(pdev);
3075 if (retval)
3076 return retval;
3077#endif
3078
3079 pci_enable_wake(pdev, PCI_D3hot, 0);
3080 pci_enable_wake(pdev, PCI_D3cold, 0);
3081
3082 ixgbe_release_hw_control(adapter);
3083
3084 pci_disable_device(pdev);
3085
3086 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3087
3088 return 0;
3089}
3090
3091static void ixgbe_shutdown(struct pci_dev *pdev)
3092{
3093 ixgbe_suspend(pdev, PMSG_SUSPEND);
3094}
3095
9a799d71
AK		 3096/**
3097 * ixgbe_update_stats - Update the board statistics counters.
3098 * @adapter: board private structure
3099 **/
3100void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3101{
3102 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 3103 u64 total_mpc = 0;
3104 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71
AK		 3105
3106 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 3107 for (i = 0; i < 8; i++) {
3108 /* for packet buffers not used, the register should read 0 */
3109 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3110 missed_rx += mpc;
3111 adapter->stats.mpc[i] += mpc;
3112 total_mpc += adapter->stats.mpc[i];
3113 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3114 }
3115 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3116 /* work around hardware counting issue */
3117 adapter->stats.gprc -= missed_rx;
3118
3119 /* 82598 hardware only has a 32 bit counter in the high register */
9a799d71 3120 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6f11eef7
AV		 3121 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3122 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
9a799d71
AK		 3123 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3124 adapter->stats.bprc += bprc;
3125 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3126 adapter->stats.mprc -= bprc;
3127 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3128 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3129 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3130 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3131 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3132 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3133 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71
AK		 3134 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3135 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
9a799d71 3136 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6f11eef7
AV		 3137 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3138 adapter->stats.lxontxc += lxon;
3139 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3140 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 3141 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3142 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 3143 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3144 /*
3145 * 82598 errata - tx of flow control packets is included in tx counters
3146 */
3147 xon_off_tot = lxon + lxoff;
3148 adapter->stats.gptc -= xon_off_tot;
3149 adapter->stats.mptc -= xon_off_tot;
3150 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 3151 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3152 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3153 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 3154 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3155 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 3156 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 3157 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3158 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3159 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3160 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3161 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 3162 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3163
3164 /* Fill out the OS statistics structure */
9a799d71
AK		 3165 adapter->net_stats.multicast = adapter->stats.mprc;
3166
3167 /* Rx Errors */
3168 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 3169 adapter->stats.rlec;
9a799d71
AK		 3170 adapter->net_stats.rx_dropped = 0;
3171 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3172 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 3173 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 3174}
3175
3176/**
3177 * ixgbe_watchdog - Timer Call-back
3178 * @data: pointer to adapter cast into an unsigned long
3179 **/
3180static void ixgbe_watchdog(unsigned long data)
3181{
3182 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 3183 struct ixgbe_hw *hw = &adapter->hw;
3184
3185 /* Do the watchdog outside of interrupt context due to the lovely
3186 * delays that some of the newer hardware requires */
3187 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3188 /* Cause software interrupt to ensure rx rings are cleaned */
3189 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3190 u32 eics =
3191 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3192 IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3193 } else {
3194 /* For legacy and MSI interrupts don't set any bits that
3195 * are enabled for EIAM, because this operation would
3196 * set *both* EIMS and EICS for any bit in EIAM */
3197 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3198 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3199 }
3200 /* Reset the timer */
3201 mod_timer(&adapter->watchdog_timer,
3202 round_jiffies(jiffies + 2 * HZ));
3203 }
9a799d71 3204
cf8280ee
JB		 3205 schedule_work(&adapter->watchdog_task);
3206}
3207
3208/**
69888674
AD		 3209 * ixgbe_watchdog_task - worker thread to bring link up
3210 * @work: pointer to work_struct containing our data
cf8280ee
JB		 3211 **/
3212static void ixgbe_watchdog_task(struct work_struct *work)
3213{
3214 struct ixgbe_adapter *adapter = container_of(work,
3215 struct ixgbe_adapter,
3216 watchdog_task);
3217 struct net_device *netdev = adapter->netdev;
3218 struct ixgbe_hw *hw = &adapter->hw;
3219 u32 link_speed = adapter->link_speed;
3220 bool link_up = adapter->link_up;
3221
3222 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3223
3224 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3225 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3226 if (link_up ||
3227 time_after(jiffies, (adapter->link_check_timeout +
3228 IXGBE_TRY_LINK_TIMEOUT))) {
3229 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3230 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3231 }
3232 adapter->link_up = link_up;
3233 adapter->link_speed = link_speed;
3234 }
9a799d71
AK		 3235
3236 if (link_up) {
3237 if (!netif_carrier_ok(netdev)) {
cf8280ee
JB		 3238 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3239 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
9a799d71
AK		 3240#define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
3241#define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
3242 DPRINTK(LINK, INFO, "NIC Link is Up %s, "
cf8280ee
JB		 3243 "Flow Control: %s\n",
3244 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3245 "10 Gbps" :
3246 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3247 "1 Gbps" : "unknown speed")),
3248 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
3249 (FLOW_RX ? "RX" :
3250 (FLOW_TX ? "TX" : "None"))));
9a799d71
AK		 3251
3252 netif_carrier_on(netdev);
9a799d71
AK		 3253 } else {
3254 /* Force detection of hung controller */
3255 adapter->detect_tx_hung = true;
3256 }
3257 } else {
cf8280ee
JB		 3258 adapter->link_up = false;
3259 adapter->link_speed = 0;
9a799d71
AK		 3260 if (netif_carrier_ok(netdev)) {
3261 DPRINTK(LINK, INFO, "NIC Link is Down\n");
3262 netif_carrier_off(netdev);
9a799d71
AK		 3263 }
3264 }
3265
3266 ixgbe_update_stats(adapter);
cf8280ee 3267 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 3268}
3269
9a799d71 3270static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 3271 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3272 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 3273{
3274 struct ixgbe_adv_tx_context_desc *context_desc;
3275 unsigned int i;
3276 int err;
3277 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 3278 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
3279 u32 mss_l4len_idx, l4len;
9a799d71
AK		 3280
3281 if (skb_is_gso(skb)) {
3282 if (skb_header_cloned(skb)) {
3283 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3284 if (err)
3285 return err;
3286 }
3287 l4len = tcp_hdrlen(skb);
3288 *hdr_len += l4len;
3289
8327d000 3290 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 3291 struct iphdr *iph = ip_hdr(skb);
3292 iph->tot_len = 0;
3293 iph->check = 0;
3294 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 3295 iph->daddr, 0,
3296 IPPROTO_TCP,
3297 0);
9a799d71
AK		 3298 adapter->hw_tso_ctxt++;
3299 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3300 ipv6_hdr(skb)->payload_len = 0;
3301 tcp_hdr(skb)->check =
3302 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 3303 &ipv6_hdr(skb)->daddr,
3304 0, IPPROTO_TCP, 0);
9a799d71
AK		 3305 adapter->hw_tso6_ctxt++;
3306 }
3307
3308 i = tx_ring->next_to_use;
3309
3310 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3311 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3312
3313 /* VLAN MACLEN IPLEN */
3314 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3315 vlan_macip_lens |=
3316 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3317 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 3318 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 3319 *hdr_len += skb_network_offset(skb);
3320 vlan_macip_lens |=
3321 (skb_transport_header(skb) - skb_network_header(skb));
3322 *hdr_len +=
3323 (skb_transport_header(skb) - skb_network_header(skb));
3324 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3325 context_desc->seqnum_seed = 0;
3326
3327 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 3328 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 3329 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 3330
8327d000 3331 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3332 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3333 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3334 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3335
3336 /* MSS L4LEN IDX */
9f8cdf4f 3337 mss_l4len_idx =
9a799d71
AK		 3338 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3339 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 3340 /* use index 1 for TSO */
3341 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 3342 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3343
3344 tx_buffer_info->time_stamp = jiffies;
3345 tx_buffer_info->next_to_watch = i;
3346
3347 i++;
3348 if (i == tx_ring->count)
3349 i = 0;
3350 tx_ring->next_to_use = i;
3351
3352 return true;
3353 }
3354 return false;
3355}
3356
3357static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 3358 struct ixgbe_ring *tx_ring,
3359 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 3360{
3361 struct ixgbe_adv_tx_context_desc *context_desc;
3362 unsigned int i;
3363 struct ixgbe_tx_buffer *tx_buffer_info;
3364 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3365
3366 if (skb->ip_summed == CHECKSUM_PARTIAL ||
3367 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3368 i = tx_ring->next_to_use;
3369 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3370 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3371
3372 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3373 vlan_macip_lens |=
3374 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3375 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 3376 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 3377 if (skb->ip_summed == CHECKSUM_PARTIAL)
3378 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 3379 skb_network_header(skb));
9a799d71
AK		 3380
3381 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3382 context_desc->seqnum_seed = 0;
3383
3384 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 3385 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 3386
3387 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71
AK		 3388 switch (skb->protocol) {
3389 case __constant_htons(ETH_P_IP):
9a799d71 3390 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 3391 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3392 type_tucmd_mlhl |=
b4617240 3393 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 3394 break;
41825d71
AK		 3395 case __constant_htons(ETH_P_IPV6):
3396 /* XXX what about other V6 headers?? */
3397 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3398 type_tucmd_mlhl |=
b4617240 3399 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 3400 break;
41825d71
AK		 3401 default:
3402 if (unlikely(net_ratelimit())) {
3403 DPRINTK(PROBE, WARNING,
3404 "partial checksum but proto=%x!\n",
3405 skb->protocol);
3406 }
3407 break;
3408 }
9a799d71
AK		 3409 }
3410
3411 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 3412 /* use index zero for tx checksum offload */
9a799d71
AK		 3413 context_desc->mss_l4len_idx = 0;
3414
3415 tx_buffer_info->time_stamp = jiffies;
3416 tx_buffer_info->next_to_watch = i;
9f8cdf4f 3417
9a799d71
AK		 3418 adapter->hw_csum_tx_good++;
3419 i++;
3420 if (i == tx_ring->count)
3421 i = 0;
3422 tx_ring->next_to_use = i;
3423
3424 return true;
3425 }
9f8cdf4f 3426
9a799d71
AK		 3427 return false;
3428}
3429
3430static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240
PW		 3431 struct ixgbe_ring *tx_ring,
3432 struct sk_buff *skb, unsigned int first)
9a799d71
AK		 3433{
3434 struct ixgbe_tx_buffer *tx_buffer_info;
3435 unsigned int len = skb->len;
3436 unsigned int offset = 0, size, count = 0, i;
3437 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3438 unsigned int f;
3439
3440 len -= skb->data_len;
3441
3442 i = tx_ring->next_to_use;
3443
3444 while (len) {
3445 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3446 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3447
3448 tx_buffer_info->length = size;
3449 tx_buffer_info->dma = pci_map_single(adapter->pdev,
b4617240
PW		 3450 skb->data + offset,
3451 size, PCI_DMA_TODEVICE);
9a799d71
AK		 3452 tx_buffer_info->time_stamp = jiffies;
3453 tx_buffer_info->next_to_watch = i;
3454
3455 len -= size;
3456 offset += size;
3457 count++;
3458 i++;
3459 if (i == tx_ring->count)
3460 i = 0;
3461 }
3462
3463 for (f = 0; f < nr_frags; f++) {
3464 struct skb_frag_struct *frag;
3465
3466 frag = &skb_shinfo(skb)->frags[f];
3467 len = frag->size;
3468 offset = frag->page_offset;
3469
3470 while (len) {
3471 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3472 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3473
3474 tx_buffer_info->length = size;
3475 tx_buffer_info->dma = pci_map_page(adapter->pdev,
b4617240
PW		 3476 frag->page,
3477 offset,
3478 size,
3479 PCI_DMA_TODEVICE);
9a799d71
AK		 3480 tx_buffer_info->time_stamp = jiffies;
3481 tx_buffer_info->next_to_watch = i;
3482
3483 len -= size;
3484 offset += size;
3485 count++;
3486 i++;
3487 if (i == tx_ring->count)
3488 i = 0;
3489 }
3490 }
3491 if (i == 0)
3492 i = tx_ring->count - 1;
3493 else
3494 i = i - 1;
3495 tx_ring->tx_buffer_info[i].skb = skb;
3496 tx_ring->tx_buffer_info[first].next_to_watch = i;
3497
3498 return count;
3499}
3500
3501static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 3502 struct ixgbe_ring *tx_ring,
3503 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 3504{
3505 union ixgbe_adv_tx_desc *tx_desc = NULL;
3506 struct ixgbe_tx_buffer *tx_buffer_info;
3507 u32 olinfo_status = 0, cmd_type_len = 0;
3508 unsigned int i;
3509 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3510
3511 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3512
3513 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3514
3515 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3516 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3517
3518 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3519 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3520
3521 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 3522 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 3523
4eeae6fd
PW		 3524 /* use index 1 context for tso */
3525 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 3526 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3527 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 3528 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 3529
3530 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3531 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 3532 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 3533
3534 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3535
3536 i = tx_ring->next_to_use;
3537 while (count--) {
3538 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3539 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3540 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3541 tx_desc->read.cmd_type_len =
b4617240 3542 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 3543 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 3544 i++;
3545 if (i == tx_ring->count)
3546 i = 0;
3547 }
3548
3549 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3550
3551 /*
3552 * Force memory writes to complete before letting h/w
3553 * know there are new descriptors to fetch. (Only
3554 * applicable for weak-ordered memory model archs,
3555 * such as IA-64).
3556 */
3557 wmb();
3558
3559 tx_ring->next_to_use = i;
3560 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3561}
3562
e092be60 3563static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 3564 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 3565{
3566 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3567
30eba97a 3568 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3569 /* Herbert's original patch had:
3570 * smp_mb__after_netif_stop_queue();
3571 * but since that doesn't exist yet, just open code it. */
3572 smp_mb();
3573
3574 /* We need to check again in a case another CPU has just
3575 * made room available. */
3576 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3577 return -EBUSY;
3578
3579 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 3580 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3581 ++adapter->restart_queue;
3582 return 0;
3583}
3584
3585static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 3586 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 3587{
3588 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3589 return 0;
3590 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3591}
3592
9a799d71
AK		 3593static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3594{
3595 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3596 struct ixgbe_ring *tx_ring;
9a799d71
AK		 3597 unsigned int first;
3598 unsigned int tx_flags = 0;
30eba97a
AV		 3599 u8 hdr_len = 0;
3600 int r_idx = 0, tso;
9a799d71
AK		 3601 int count = 0;
3602 unsigned int f;
9f8cdf4f 3603
30eba97a 3604 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
30eba97a 3605 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 3606
9f8cdf4f
JB		 3607 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3608 tx_flags |= vlan_tx_tag_get(skb);
3609 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3610 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 3611 }
9f8cdf4f
JB		 3612 /* three things can cause us to need a context descriptor */
3613 if (skb_is_gso(skb) ||
3614 (skb->ip_summed == CHECKSUM_PARTIAL) ||
3615 (tx_flags & IXGBE_TX_FLAGS_VLAN))
9a799d71
AK		 3616 count++;
3617
9f8cdf4f
JB		 3618 count += TXD_USE_COUNT(skb_headlen(skb));
3619 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 3620 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3621
e092be60 3622 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 3623 adapter->tx_busy++;
9a799d71
AK		 3624 return NETDEV_TX_BUSY;
3625 }
9a799d71 3626
8327d000 3627 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3628 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3629 first = tx_ring->next_to_use;
3630 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3631 if (tso < 0) {
3632 dev_kfree_skb_any(skb);
3633 return NETDEV_TX_OK;
3634 }
3635
3636 if (tso)
3637 tx_flags |= IXGBE_TX_FLAGS_TSO;
3638 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
b4617240 3639 (skb->ip_summed == CHECKSUM_PARTIAL))
9a799d71
AK		 3640 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3641
3642 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
b4617240
PW		 3643 ixgbe_tx_map(adapter, tx_ring, skb, first),
3644 skb->len, hdr_len);
9a799d71
AK		 3645
3646 netdev->trans_start = jiffies;
3647
e092be60 3648 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71
AK		 3649
3650 return NETDEV_TX_OK;
3651}
3652
3653/**
3654 * ixgbe_get_stats - Get System Network Statistics
3655 * @netdev: network interface device structure
3656 *
3657 * Returns the address of the device statistics structure.
3658 * The statistics are actually updated from the timer callback.
3659 **/
3660static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3661{
3662 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3663
3664 /* only return the current stats */
3665 return &adapter->net_stats;
3666}
3667
3668/**
3669 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3670 * @netdev: network interface device structure
3671 * @p: pointer to an address structure
3672 *
3673 * Returns 0 on success, negative on failure
3674 **/
3675static int ixgbe_set_mac(struct net_device *netdev, void *p)
3676{
3677 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 3678 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3679 struct sockaddr *addr = p;
3680
3681 if (!is_valid_ether_addr(addr->sa_data))
3682 return -EADDRNOTAVAIL;
3683
3684 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 3685 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 3686
b4617240 3687 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 3688
3689 return 0;
3690}
3691
3692#ifdef CONFIG_NET_POLL_CONTROLLER
3693/*
3694 * Polling 'interrupt' - used by things like netconsole to send skbs
3695 * without having to re-enable interrupts. It's not called while
3696 * the interrupt routine is executing.
3697 */
3698static void ixgbe_netpoll(struct net_device *netdev)
3699{
3700 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3701
3702 disable_irq(adapter->pdev->irq);
3703 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3704 ixgbe_intr(adapter->pdev->irq, netdev);
3705 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3706 enable_irq(adapter->pdev->irq);
3707}
3708#endif
3709
c44ade9e
JB		 3710/**
3711 * ixgbe_link_config - set up initial link with default speed and duplex
3712 * @hw: pointer to private hardware struct
3713 *
3714 * Returns 0 on success, negative on failure
3715 **/
3716static int ixgbe_link_config(struct ixgbe_hw *hw)
3717{
3718 u32 autoneg = IXGBE_LINK_SPEED_10GB_FULL;
3719
3720 /* must always autoneg for both 1G and 10G link */
3721 hw->mac.autoneg = true;
3722
0befdb3e
JB		 3723 if ((hw->mac.type == ixgbe_mac_82598EB) &&
3724 (hw->phy.media_type == ixgbe_media_type_copper))
3725 autoneg = IXGBE_LINK_SPEED_82598_AUTONEG;
3726
c44ade9e
JB		 3727 return hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3728}
3729
0edc3527
SH		 3730static const struct net_device_ops ixgbe_netdev_ops = {
3731 .ndo_open = ixgbe_open,
3732 .ndo_stop = ixgbe_close,
3733 .ndo_get_stats = ixgbe_get_stats,
3734 .ndo_set_multicast_list = ixgbe_set_rx_mode,
3735 .ndo_validate_addr = eth_validate_addr,
3736 .ndo_set_mac_address = ixgbe_set_mac,
3737 .ndo_change_mtu = ixgbe_change_mtu,
3738 .ndo_tx_timeout = ixgbe_tx_timeout,
3739 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
3740 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
3741 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
3742#ifdef CONFIG_NET_POLL_CONTROLLER
3743 .ndo_poll_controller = ixgbe_netpoll,
3744#endif
3745};
3746
9a799d71
AK		 3747/**
3748 * ixgbe_probe - Device Initialization Routine
3749 * @pdev: PCI device information struct
3750 * @ent: entry in ixgbe_pci_tbl
3751 *
3752 * Returns 0 on success, negative on failure
3753 *
3754 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3755 * The OS initialization, configuring of the adapter private structure,
3756 * and a hardware reset occur.
3757 **/
3758static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 3759 const struct pci_device_id *ent)
9a799d71
AK		 3760{
3761 struct net_device *netdev;
3762 struct ixgbe_adapter *adapter = NULL;
3763 struct ixgbe_hw *hw;
3764 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 3765 static int cards_found;
3766 int i, err, pci_using_dac;
3767 u16 link_status, link_speed, link_width;
c44ade9e 3768 u32 part_num, eec;
9a799d71
AK		 3769
3770 err = pci_enable_device(pdev);
3771 if (err)
3772 return err;
3773
3774 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3775 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3776 pci_using_dac = 1;
3777 } else {
3778 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3779 if (err) {
3780 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3781 if (err) {
b4617240
PW		 3782 dev_err(&pdev->dev, "No usable DMA "
3783 "configuration, aborting\n");
9a799d71
AK		 3784 goto err_dma;
3785 }
3786 }
3787 pci_using_dac = 0;
3788 }
3789
3790 err = pci_request_regions(pdev, ixgbe_driver_name);
3791 if (err) {
3792 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3793 goto err_pci_reg;
3794 }
3795
3796 pci_set_master(pdev);
fb3b27bc 3797 pci_save_state(pdev);
9a799d71 3798
30eba97a 3799 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 3800 if (!netdev) {
3801 err = -ENOMEM;
3802 goto err_alloc_etherdev;
3803 }
3804
9a799d71
AK		 3805 SET_NETDEV_DEV(netdev, &pdev->dev);
3806
3807 pci_set_drvdata(pdev, netdev);
3808 adapter = netdev_priv(netdev);
3809
3810 adapter->netdev = netdev;
3811 adapter->pdev = pdev;
3812 hw = &adapter->hw;
3813 hw->back = adapter;
3814 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
3815
05857980
JK		 3816 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
3817 pci_resource_len(pdev, 0));
9a799d71
AK		 3818 if (!hw->hw_addr) {
3819 err = -EIO;
3820 goto err_ioremap;
3821 }
3822
3823 for (i = 1; i <= 5; i++) {
3824 if (pci_resource_len(pdev, i) == 0)
3825 continue;
3826 }
3827
0edc3527 3828 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 3829 netdev->hard_start_xmit = &ixgbe_xmit_frame;
9a799d71 3830 ixgbe_set_ethtool_ops(netdev);
9a799d71 3831 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 3832 strcpy(netdev->name, pci_name(pdev));
3833
9a799d71
AK		 3834 adapter->bd_number = cards_found;
3835
9a799d71
AK		 3836 /* Setup hw api */
3837 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 3838 hw->mac.type = ii->mac;
9a799d71 3839
c44ade9e
JB		 3840 /* EEPROM */
3841 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
3842 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
3843 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
3844 if (!(eec & (1 << 8)))
3845 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
3846
3847 /* PHY */
3848 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
3849 /* phy->sfp_type = ixgbe_sfp_type_unknown; */
3850
9a799d71
AK		 3851 err = ii->get_invariants(hw);
3852 if (err)
3853 goto err_hw_init;
3854
3855 /* setup the private structure */
3856 err = ixgbe_sw_init(adapter);
3857 if (err)
3858 goto err_sw_init;
3859
c44ade9e
JB		 3860 /* reset_hw fills in the perm_addr as well */
3861 err = hw->mac.ops.reset_hw(hw);
3862 if (err) {
3863 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
3864 goto err_sw_init;
3865 }
3866
9a799d71 3867 netdev->features = NETIF_F_SG |
b4617240
PW		 3868 NETIF_F_IP_CSUM |
3869 NETIF_F_HW_VLAN_TX |
3870 NETIF_F_HW_VLAN_RX |
3871 NETIF_F_HW_VLAN_FILTER;
9a799d71 3872
e9990a9c 3873 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 3874 netdev->features |= NETIF_F_TSO;
9a799d71 3875 netdev->features |= NETIF_F_TSO6;
e9990a9c 3876 netdev->features |= NETIF_F_LRO;
ad31c402
JK		 3877
3878 netdev->vlan_features |= NETIF_F_TSO;
3879 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 3880 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 3881 netdev->vlan_features |= NETIF_F_SG;
3882
9a799d71
AK		 3883 if (pci_using_dac)
3884 netdev->features |= NETIF_F_HIGHDMA;
3885
9a799d71 3886 /* make sure the EEPROM is good */
c44ade9e 3887 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 3888 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
3889 err = -EIO;
3890 goto err_eeprom;
3891 }
3892
3893 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
3894 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
3895
c44ade9e
JB		 3896 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
3897 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 3898 err = -EIO;
3899 goto err_eeprom;
3900 }
3901
3902 init_timer(&adapter->watchdog_timer);
3903 adapter->watchdog_timer.function = &ixgbe_watchdog;
3904 adapter->watchdog_timer.data = (unsigned long)adapter;
3905
3906 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 3907 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 3908
021230d4
AV		 3909 err = ixgbe_init_interrupt_scheme(adapter);
3910 if (err)
3911 goto err_sw_init;
9a799d71
AK		 3912
3913 /* print bus type/speed/width info */
3914 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
3915 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
3916 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
7c510e4b 3917 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
b4617240
PW		 3918 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
3919 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
3920 "Unknown"),
3921 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
3922 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
3923 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
3924 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
3925 "Unknown"),
7c510e4b 3926 netdev->dev_addr);
c44ade9e 3927 ixgbe_read_pba_num_generic(hw, &part_num);
9a799d71 3928 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
b4617240
PW		 3929 hw->mac.type, hw->phy.type,
3930 (part_num >> 8), (part_num & 0xff));
9a799d71 3931
0c254d86
AK		 3932 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
3933 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 3934 "this card is not sufficient for optimal "
3935 "performance.\n");
0c254d86 3936 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 3937 "PCI-Express slot is required.\n");
0c254d86
AK		 3938 }
3939
9a799d71 3940 /* reset the hardware with the new settings */
c44ade9e
JB		 3941 hw->mac.ops.start_hw(hw);
3942
3943 /* link_config depends on start_hw being called at least once */
3944 err = ixgbe_link_config(hw);
3945 if (err) {
3946 dev_err(&pdev->dev, "setup_link_speed FAILED %d\n", err);
3947 goto err_register;
3948 }
9a799d71
AK		 3949
3950 netif_carrier_off(netdev);
9a799d71 3951
021230d4
AV		 3952 ixgbe_napi_add_all(adapter);
3953
9a799d71
AK		 3954 strcpy(netdev->name, "eth%d");
3955 err = register_netdev(netdev);
3956 if (err)
3957 goto err_register;
3958
5dd2d332 3959#ifdef CONFIG_IXGBE_DCA
652f093f 3960 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 3961 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
3962 /* always use CB2 mode, difference is masked
3963 * in the CB driver */
3964 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
3965 ixgbe_setup_dca(adapter);
3966 }
3967#endif
9a799d71
AK		 3968
3969 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
3970 cards_found++;
3971 return 0;
3972
3973err_register:
5eba3699 3974 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3975err_hw_init:
3976err_sw_init:
021230d4 3977 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3978err_eeprom:
3979 iounmap(hw->hw_addr);
3980err_ioremap:
3981 free_netdev(netdev);
3982err_alloc_etherdev:
3983 pci_release_regions(pdev);
3984err_pci_reg:
3985err_dma:
3986 pci_disable_device(pdev);
3987 return err;
3988}
3989
3990/**
3991 * ixgbe_remove - Device Removal Routine
3992 * @pdev: PCI device information struct
3993 *
3994 * ixgbe_remove is called by the PCI subsystem to alert the driver
3995 * that it should release a PCI device. The could be caused by a
3996 * Hot-Plug event, or because the driver is going to be removed from
3997 * memory.
3998 **/
3999static void __devexit ixgbe_remove(struct pci_dev *pdev)
4000{
4001 struct net_device *netdev = pci_get_drvdata(pdev);
4002 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4003
4004 set_bit(__IXGBE_DOWN, &adapter->state);
4005 del_timer_sync(&adapter->watchdog_timer);
4006
4007 flush_scheduled_work();
4008
5dd2d332 4009#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 4010 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4011 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4012 dca_remove_requester(&pdev->dev);
4013 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
4014 }
4015
4016#endif
9a799d71
AK		 4017 unregister_netdev(netdev);
4018
021230d4 4019 ixgbe_reset_interrupt_capability(adapter);
5eba3699 4020
021230d4 4021 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4022
4023 iounmap(adapter->hw.hw_addr);
4024 pci_release_regions(pdev);
4025
021230d4 4026 DPRINTK(PROBE, INFO, "complete\n");
b3c8b4ba 4027 ixgbe_napi_del_all(adapter);
021230d4
AV		 4028 kfree(adapter->tx_ring);
4029 kfree(adapter->rx_ring);
4030
9a799d71
AK		 4031 free_netdev(netdev);
4032
4033 pci_disable_device(pdev);
4034}
4035
4036/**
4037 * ixgbe_io_error_detected - called when PCI error is detected
4038 * @pdev: Pointer to PCI device
4039 * @state: The current pci connection state
4040 *
4041 * This function is called after a PCI bus error affecting
4042 * this device has been detected.
4043 */
4044static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 4045 pci_channel_state_t state)
9a799d71
AK		 4046{
4047 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4048 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4049
4050 netif_device_detach(netdev);
4051
4052 if (netif_running(netdev))
4053 ixgbe_down(adapter);
4054 pci_disable_device(pdev);
4055
b4617240 4056 /* Request a slot reset. */
9a799d71
AK		 4057 return PCI_ERS_RESULT_NEED_RESET;
4058}
4059
4060/**
4061 * ixgbe_io_slot_reset - called after the pci bus has been reset.
4062 * @pdev: Pointer to PCI device
4063 *
4064 * Restart the card from scratch, as if from a cold-boot.
4065 */
4066static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4067{
4068 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4069 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4070
4071 if (pci_enable_device(pdev)) {
4072 DPRINTK(PROBE, ERR,
b4617240 4073 "Cannot re-enable PCI device after reset.\n");
9a799d71
AK		 4074 return PCI_ERS_RESULT_DISCONNECT;
4075 }
4076 pci_set_master(pdev);
fb3b27bc 4077 pci_restore_state(pdev);
9a799d71
AK		 4078
4079 pci_enable_wake(pdev, PCI_D3hot, 0);
4080 pci_enable_wake(pdev, PCI_D3cold, 0);
4081
4082 ixgbe_reset(adapter);
4083
4084 return PCI_ERS_RESULT_RECOVERED;
4085}
4086
4087/**
4088 * ixgbe_io_resume - called when traffic can start flowing again.
4089 * @pdev: Pointer to PCI device
4090 *
4091 * This callback is called when the error recovery driver tells us that
4092 * its OK to resume normal operation.
4093 */
4094static void ixgbe_io_resume(struct pci_dev *pdev)
4095{
4096 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4097 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4098
4099 if (netif_running(netdev)) {
4100 if (ixgbe_up(adapter)) {
4101 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4102 return;
4103 }
4104 }
4105
4106 netif_device_attach(netdev);
9a799d71
AK		 4107}
4108
4109static struct pci_error_handlers ixgbe_err_handler = {
4110 .error_detected = ixgbe_io_error_detected,
4111 .slot_reset = ixgbe_io_slot_reset,
4112 .resume = ixgbe_io_resume,
4113};
4114
4115static struct pci_driver ixgbe_driver = {
4116 .name = ixgbe_driver_name,
4117 .id_table = ixgbe_pci_tbl,
4118 .probe = ixgbe_probe,
4119 .remove = __devexit_p(ixgbe_remove),
4120#ifdef CONFIG_PM
4121 .suspend = ixgbe_suspend,
4122 .resume = ixgbe_resume,
4123#endif
4124 .shutdown = ixgbe_shutdown,
4125 .err_handler = &ixgbe_err_handler
4126};
4127
4128/**
4129 * ixgbe_init_module - Driver Registration Routine
4130 *
4131 * ixgbe_init_module is the first routine called when the driver is
4132 * loaded. All it does is register with the PCI subsystem.
4133 **/
4134static int __init ixgbe_init_module(void)
4135{
4136 int ret;
4137 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4138 ixgbe_driver_string, ixgbe_driver_version);
4139
4140 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4141
5dd2d332 4142#ifdef CONFIG_IXGBE_DCA
bd0362dd 4143 dca_register_notify(&dca_notifier);
bd0362dd 4144#endif
5dd2d332 4145
9a799d71
AK		 4146 ret = pci_register_driver(&ixgbe_driver);
4147 return ret;
4148}
b4617240 4149
9a799d71
AK		 4150module_init(ixgbe_init_module);
4151
4152/**
4153 * ixgbe_exit_module - Driver Exit Cleanup Routine
4154 *
4155 * ixgbe_exit_module is called just before the driver is removed
4156 * from memory.
4157 **/
4158static void __exit ixgbe_exit_module(void)
4159{
5dd2d332 4160#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 4161 dca_unregister_notify(&dca_notifier);
4162#endif
9a799d71
AK		 4163 pci_unregister_driver(&ixgbe_driver);
4164}
bd0362dd 4165
5dd2d332 4166#ifdef CONFIG_IXGBE_DCA
bd0362dd 4167static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 4168 void *p)
bd0362dd
JC		 4169{
4170 int ret_val;
4171
4172 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 4173 __ixgbe_notify_dca);
bd0362dd
JC		 4174
4175 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4176}
5dd2d332 4177#endif /* CONFIG_IXGBE_DCA */
bd0362dd 4178
9a799d71
AK		 4179module_exit(ixgbe_exit_module);
4180
4181/* ixgbe_main.c */
Linux kernel - Deliverables
This page took 0.749747 seconds and 5 git commands to generate.