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ixgbe: move tx processing into NAPI context
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
eacd73f7 42#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 43
44#include "ixgbe.h"
45#include "ixgbe_common.h"
46
47char ixgbe_driver_name[] = "ixgbe";
9c8eb720 48static const char ixgbe_driver_string[] =
b4617240 49 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 50
ba98898e 51#define DRV_VERSION "2.0.24-k2"
9c8eb720 52const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 53static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 54
55static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 56 [board_82598] = &ixgbe_82598_info,
e8e26350 57 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 58};
59
60/* ixgbe_pci_tbl - PCI Device ID Table
61 *
62 * Wildcard entries (PCI_ANY_ID) should come last
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
70 board_82598 },
9a799d71 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 74 board_82598 },
0befdb3e
JB		 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 78 board_82598 },
8d792cd9
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
80 board_82598 },
c4900be0
DS		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
84 board_82598 },
b95f5fcb
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
88 board_82598 },
2f21bdd3
DS		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
90 board_82598 },
e8e26350
PW		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
92 board_82599 },
1fcf03e6
PWJ		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
94 board_82599 },
e8e26350
PW		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
96 board_82599 },
9a799d71
AK		 97
98 /* required last entry */
99 {0, }
100};
101MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
102
5dd2d332 103#ifdef CONFIG_IXGBE_DCA
bd0362dd 104static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 105 void *p);
bd0362dd
JC		 106static struct notifier_block dca_notifier = {
107 .notifier_call = ixgbe_notify_dca,
108 .next = NULL,
109 .priority = 0
110};
111#endif
112
9a799d71
AK		 113MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
114MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
115MODULE_LICENSE("GPL");
116MODULE_VERSION(DRV_VERSION);
117
118#define DEFAULT_DEBUG_LEVEL_SHIFT 3
119
5eba3699
AV		 120static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
121{
122 u32 ctrl_ext;
123
124 /* Let firmware take over control of h/w */
125 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
126 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 127 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 128}
129
130static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
131{
132 u32 ctrl_ext;
133
134 /* Let firmware know the driver has taken over */
135 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
136 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 137 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 138}
9a799d71 139
e8e26350
PW		 140/*
141 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
142 * @adapter: pointer to adapter struct
143 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
144 * @queue: queue to map the corresponding interrupt to
145 * @msix_vector: the vector to map to the corresponding queue
146 *
147 */
148static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
149 u8 queue, u8 msix_vector)
9a799d71
AK		 150{
151 u32 ivar, index;
e8e26350
PW		 152 struct ixgbe_hw *hw = &adapter->hw;
153 switch (hw->mac.type) {
154 case ixgbe_mac_82598EB:
155 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
156 if (direction == -1)
157 direction = 0;
158 index = (((direction * 64) + queue) >> 2) & 0x1F;
159 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
160 ivar &= ~(0xFF << (8 * (queue & 0x3)));
161 ivar |= (msix_vector << (8 * (queue & 0x3)));
162 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
163 break;
164 case ixgbe_mac_82599EB:
165 if (direction == -1) {
166 /* other causes */
167 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
168 index = ((queue & 1) * 8);
169 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
170 ivar &= ~(0xFF << index);
171 ivar |= (msix_vector << index);
172 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
173 break;
174 } else {
175 /* tx or rx causes */
176 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
177 index = ((16 * (queue & 1)) + (8 * direction));
178 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
179 ivar &= ~(0xFF << index);
180 ivar |= (msix_vector << index);
181 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
182 break;
183 }
184 default:
185 break;
186 }
9a799d71
AK		 187}
188
fe49f04a
AD		 189static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
190 u64 qmask)
191{
192 u32 mask;
193
194 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
195 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
196 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
197 } else {
198 mask = (qmask & 0xFFFFFFFF);
199 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
200 mask = (qmask >> 32);
201 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
202 }
203}
204
9a799d71 205static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 206 struct ixgbe_tx_buffer
207 *tx_buffer_info)
9a799d71 208{
44df32c5 209 tx_buffer_info->dma = 0;
9a799d71 210 if (tx_buffer_info->skb) {
44df32c5
AD		 211 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
212 DMA_TO_DEVICE);
9a799d71
AK		 213 dev_kfree_skb_any(tx_buffer_info->skb);
214 tx_buffer_info->skb = NULL;
215 }
44df32c5 216 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 217 /* tx_buffer_info must be completely set up in the transmit path */
218}
219
220static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 221 struct ixgbe_ring *tx_ring,
222 unsigned int eop)
9a799d71 223{
e01c31a5 224 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 225
9a799d71 226 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 227 * check with the clearing of time_stamp and movement of eop */
9a799d71 228 adapter->detect_tx_hung = false;
44df32c5 229 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 230 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
231 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
232 /* detected Tx unit hang */
e01c31a5
JB		 233 union ixgbe_adv_tx_desc *tx_desc;
234 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 235 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 236 " Tx Queue <%d>\n"
237 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 238 " next_to_use <%x>\n"
239 " next_to_clean <%x>\n"
240 "tx_buffer_info[next_to_clean]\n"
241 " time_stamp <%lx>\n"
e01c31a5
JB		 242 " jiffies <%lx>\n",
243 tx_ring->queue_index,
44df32c5
AD		 244 IXGBE_READ_REG(hw, tx_ring->head),
245 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 246 tx_ring->next_to_use, eop,
247 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 248 return true;
249 }
250
251 return false;
252}
253
b4617240
PW		 254#define IXGBE_MAX_TXD_PWR 14
255#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 256
257/* Tx Descriptors needed, worst case */
258#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
259 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
260#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 261 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 262
e01c31a5
JB		 263static void ixgbe_tx_timeout(struct net_device *netdev);
264
9a799d71
AK		 265/**
266 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 267 * @q_vector: structure containing interrupt and ring information
e01c31a5 268 * @tx_ring: tx ring to clean
9a799d71 269 **/
fe49f04a 270static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 271 struct ixgbe_ring *tx_ring)
9a799d71 272{
fe49f04a 273 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 274 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 275 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
276 struct ixgbe_tx_buffer *tx_buffer_info;
277 unsigned int i, eop, count = 0;
e01c31a5 278 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 279
280 i = tx_ring->next_to_clean;
12207e49
PWJ		 281 eop = tx_ring->tx_buffer_info[i].next_to_watch;
282 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
283
284 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 285 (count < tx_ring->work_limit)) {
12207e49
PWJ		 286 bool cleaned = false;
287 for ( ; !cleaned; count++) {
288 struct sk_buff *skb;
9a799d71
AK		 289 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
290 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 291 cleaned = (i == eop);
e01c31a5 292 skb = tx_buffer_info->skb;
9a799d71 293
12207e49 294 if (cleaned && skb) {
e092be60 295 unsigned int segs, bytecount;
e01c31a5
JB		 296
297 /* gso_segs is currently only valid for tcp */
e092be60
AV		 298 segs = skb_shinfo(skb)->gso_segs ?: 1;
299 /* multiply data chunks by size of headers */
300 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 301 skb->len;
302 total_packets += segs;
303 total_bytes += bytecount;
e092be60 304 }
e01c31a5 305
9a799d71 306 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 307 tx_buffer_info);
9a799d71 308
12207e49
PWJ		 309 tx_desc->wb.status = 0;
310
9a799d71
AK		 311 i++;
312 if (i == tx_ring->count)
313 i = 0;
e01c31a5 314 }
12207e49
PWJ		 315
316 eop = tx_ring->tx_buffer_info[i].next_to_watch;
317 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
318 }
319
9a799d71
AK		 320 tx_ring->next_to_clean = i;
321
e092be60 322#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 323 if (unlikely(count && netif_carrier_ok(netdev) &&
324 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 325 /* Make sure that anybody stopping the queue after this
326 * sees the new next_to_clean.
327 */
328 smp_mb();
30eba97a
AV		 329 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
330 !test_bit(__IXGBE_DOWN, &adapter->state)) {
331 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 332 ++adapter->restart_queue;
30eba97a 333 }
e092be60 334 }
9a799d71 335
e01c31a5
JB		 336 if (adapter->detect_tx_hung) {
337 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
338 /* schedule immediate reset if we believe we hung */
339 DPRINTK(PROBE, INFO,
340 "tx hang %d detected, resetting adapter\n",
341 adapter->tx_timeout_count + 1);
342 ixgbe_tx_timeout(adapter->netdev);
343 }
344 }
9a799d71 345
e01c31a5 346 /* re-arm the interrupt */
fe49f04a
AD		 347 if (count >= tx_ring->work_limit)
348 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 349
e01c31a5
JB		 350 tx_ring->total_bytes += total_bytes;
351 tx_ring->total_packets += total_packets;
e01c31a5 352 tx_ring->stats.packets += total_packets;
12207e49 353 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 354 adapter->net_stats.tx_bytes += total_bytes;
355 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 356 return (count < tx_ring->work_limit);
9a799d71
AK		 357}
358
5dd2d332 359#ifdef CONFIG_IXGBE_DCA
bd0362dd 360static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 361 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 362{
363 u32 rxctrl;
364 int cpu = get_cpu();
3a581073 365 int q = rx_ring - adapter->rx_ring;
bd0362dd 366
3a581073 367 if (rx_ring->cpu != cpu) {
bd0362dd 368 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 369 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
370 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
371 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
372 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
373 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
374 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
375 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
376 }
bd0362dd
JC		 377 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
378 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 379 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
380 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 381 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 382 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 383 rx_ring->cpu = cpu;
bd0362dd
JC		 384 }
385 put_cpu();
386}
387
388static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 389 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 390{
391 u32 txctrl;
392 int cpu = get_cpu();
3a581073 393 int q = tx_ring - adapter->tx_ring;
bd0362dd 394
3a581073 395 if (tx_ring->cpu != cpu) {
bd0362dd 396 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 397 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
398 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
399 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
400 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
401 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
402 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
403 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
404 }
bd0362dd
JC		 405 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
406 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 407 tx_ring->cpu = cpu;
bd0362dd
JC		 408 }
409 put_cpu();
410}
411
412static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
413{
414 int i;
415
416 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
417 return;
418
e35ec126
AD		 419 /* always use CB2 mode, difference is masked in the CB driver */
420 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
421
bd0362dd
JC		 422 for (i = 0; i < adapter->num_tx_queues; i++) {
423 adapter->tx_ring[i].cpu = -1;
424 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
425 }
426 for (i = 0; i < adapter->num_rx_queues; i++) {
427 adapter->rx_ring[i].cpu = -1;
428 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
429 }
430}
431
432static int __ixgbe_notify_dca(struct device *dev, void *data)
433{
434 struct net_device *netdev = dev_get_drvdata(dev);
435 struct ixgbe_adapter *adapter = netdev_priv(netdev);
436 unsigned long event = *(unsigned long *)data;
437
438 switch (event) {
439 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 440 /* if we're already enabled, don't do it again */
441 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
442 break;
652f093f 443 if (dca_add_requester(dev) == 0) {
96b0e0f6 444 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 445 ixgbe_setup_dca(adapter);
446 break;
447 }
448 /* Fall Through since DCA is disabled. */
449 case DCA_PROVIDER_REMOVE:
450 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
451 dca_remove_requester(dev);
452 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
453 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
454 }
455 break;
456 }
457
652f093f 458 return 0;
bd0362dd
JC		 459}
460
5dd2d332 461#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 462/**
463 * ixgbe_receive_skb - Send a completed packet up the stack
464 * @adapter: board private structure
465 * @skb: packet to send up
177db6ff
MC		 466 * @status: hardware indication of status of receive
467 * @rx_ring: rx descriptor ring (for a specific queue) to setup
468 * @rx_desc: rx descriptor
9a799d71 469 **/
78b6f4ce 470static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 471 struct sk_buff *skb, u8 status,
fdaff1ce 472 struct ixgbe_ring *ring,
177db6ff 473 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 474{
78b6f4ce
HX		 475 struct ixgbe_adapter *adapter = q_vector->adapter;
476 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 477 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
478 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 479
fdaff1ce 480 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 481 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 482 if (adapter->vlgrp && is_vlan && (tag != 0))
78b6f4ce 483 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 484 else
78b6f4ce 485 napi_gro_receive(napi, skb);
177db6ff 486 } else {
182ff8df
AD		 487 if (adapter->vlgrp && is_vlan && (tag != 0))
488 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
489 else
490 netif_rx(skb);
9a799d71
AK		 491 }
492}
493
e59bd25d
AV		 494/**
495 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
496 * @adapter: address of board private structure
497 * @status_err: hardware indication of status of receive
498 * @skb: skb currently being received and modified
499 **/
9a799d71 500static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 501 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 502{
503 skb->ip_summed = CHECKSUM_NONE;
504
712744be
JB		 505 /* Rx csum disabled */
506 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 507 return;
e59bd25d
AV		 508
509 /* if IP and error */
510 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
511 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 512 adapter->hw_csum_rx_error++;
513 return;
514 }
e59bd25d
AV		 515
516 if (!(status_err & IXGBE_RXD_STAT_L4CS))
517 return;
518
519 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
520 adapter->hw_csum_rx_error++;
521 return;
522 }
523
9a799d71 524 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 525 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 526 adapter->hw_csum_rx_good++;
527}
528
e8e26350
PW		 529static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
530 struct ixgbe_ring *rx_ring, u32 val)
531{
532 /*
533 * Force memory writes to complete before letting h/w
534 * know there are new descriptors to fetch. (Only
535 * applicable for weak-ordered memory model archs,
536 * such as IA-64).
537 */
538 wmb();
539 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
540}
541
9a799d71
AK		 542/**
543 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
544 * @adapter: address of board private structure
545 **/
546static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 547 struct ixgbe_ring *rx_ring,
548 int cleaned_count)
9a799d71 549{
9a799d71
AK		 550 struct pci_dev *pdev = adapter->pdev;
551 union ixgbe_adv_rx_desc *rx_desc;
3a581073 552 struct ixgbe_rx_buffer *bi;
9a799d71 553 unsigned int i;
e8e26350 554 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 555
556 i = rx_ring->next_to_use;
3a581073 557 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 558
559 while (cleaned_count--) {
560 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
561
762f4c57 562 if (!bi->page_dma &&
3a581073 563 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 564 if (!bi->page) {
762f4c57
JB		 565 bi->page = alloc_page(GFP_ATOMIC);
566 if (!bi->page) {
567 adapter->alloc_rx_page_failed++;
568 goto no_buffers;
569 }
570 bi->page_offset = 0;
571 } else {
572 /* use a half page if we're re-using */
573 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 574 }
762f4c57
JB		 575
576 bi->page_dma = pci_map_page(pdev, bi->page,
577 bi->page_offset,
578 (PAGE_SIZE / 2),
579 PCI_DMA_FROMDEVICE);
9a799d71
AK		 580 }
581
3a581073 582 if (!bi->skb) {
5ecc3614 583 struct sk_buff *skb;
e8e26350 584 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 585
586 if (!skb) {
587 adapter->alloc_rx_buff_failed++;
588 goto no_buffers;
589 }
590
591 /*
592 * Make buffer alignment 2 beyond a 16 byte boundary
593 * this will result in a 16 byte aligned IP header after
594 * the 14 byte MAC header is removed
595 */
596 skb_reserve(skb, NET_IP_ALIGN);
597
3a581073 598 bi->skb = skb;
e8e26350 599 bi->dma = pci_map_single(pdev, skb->data, bufsz,
3a581073 600 PCI_DMA_FROMDEVICE);
9a799d71
AK		 601 }
602 /* Refresh the desc even if buffer_addrs didn't change because
603 * each write-back erases this info. */
604 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 605 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
606 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 607 } else {
3a581073 608 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 609 }
610
611 i++;
612 if (i == rx_ring->count)
613 i = 0;
3a581073 614 bi = &rx_ring->rx_buffer_info[i];
9a799d71 615 }
7c6e0a43 616
9a799d71
AK		 617no_buffers:
618 if (rx_ring->next_to_use != i) {
619 rx_ring->next_to_use = i;
620 if (i-- == 0)
621 i = (rx_ring->count - 1);
622
e8e26350 623 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 624 }
625}
626
7c6e0a43
JB		 627static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
628{
629 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
630}
631
632static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
633{
634 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
635}
636
f8212f97
AD		 637static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
638{
639 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
640 IXGBE_RXDADV_RSCCNT_MASK) >>
641 IXGBE_RXDADV_RSCCNT_SHIFT;
642}
643
644/**
645 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
646 * @skb: pointer to the last skb in the rsc queue
647 *
648 * This function changes a queue full of hw rsc buffers into a completed
649 * packet. It uses the ->prev pointers to find the first packet and then
650 * turns it into the frag list owner.
651 **/
652static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
653{
654 unsigned int frag_list_size = 0;
655
656 while (skb->prev) {
657 struct sk_buff *prev = skb->prev;
658 frag_list_size += skb->len;
659 skb->prev = NULL;
660 skb = prev;
661 }
662
663 skb_shinfo(skb)->frag_list = skb->next;
664 skb->next = NULL;
665 skb->len += frag_list_size;
666 skb->data_len += frag_list_size;
667 skb->truesize += frag_list_size;
668 return skb;
669}
670
78b6f4ce 671static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 672 struct ixgbe_ring *rx_ring,
673 int *work_done, int work_to_do)
9a799d71 674{
78b6f4ce 675 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 676 struct pci_dev *pdev = adapter->pdev;
677 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
678 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
679 struct sk_buff *skb;
f8212f97 680 unsigned int i, rsc_count = 0;
7c6e0a43 681 u32 len, staterr;
177db6ff
MC		 682 u16 hdr_info;
683 bool cleaned = false;
9a799d71 684 int cleaned_count = 0;
d2f4fbe2 685 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 686
687 i = rx_ring->next_to_clean;
9a799d71
AK		 688 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
689 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
690 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 691
692 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 693 u32 upper_len = 0;
9a799d71
AK		 694 if (*work_done >= work_to_do)
695 break;
696 (*work_done)++;
697
698 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 699 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
700 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 701 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 702 if (hdr_info & IXGBE_RXDADV_SPH)
703 adapter->rx_hdr_split++;
704 if (len > IXGBE_RX_HDR_SIZE)
705 len = IXGBE_RX_HDR_SIZE;
706 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 707 } else {
9a799d71 708 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 709 }
9a799d71
AK		 710
711 cleaned = true;
712 skb = rx_buffer_info->skb;
713 prefetch(skb->data - NET_IP_ALIGN);
714 rx_buffer_info->skb = NULL;
715
21fa4e66 716 if (rx_buffer_info->dma) {
9a799d71 717 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 718 rx_ring->rx_buf_len,
b4617240 719 PCI_DMA_FROMDEVICE);
9a799d71
AK		 720 skb_put(skb, len);
721 }
722
723 if (upper_len) {
724 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 725 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 726 rx_buffer_info->page_dma = 0;
727 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 728 rx_buffer_info->page,
729 rx_buffer_info->page_offset,
730 upper_len);
731
732 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
733 (page_count(rx_buffer_info->page) != 1))
734 rx_buffer_info->page = NULL;
735 else
736 get_page(rx_buffer_info->page);
9a799d71
AK		 737
738 skb->len += upper_len;
739 skb->data_len += upper_len;
740 skb->truesize += upper_len;
741 }
742
743 i++;
744 if (i == rx_ring->count)
745 i = 0;
9a799d71
AK		 746
747 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
748 prefetch(next_rxd);
9a799d71 749 cleaned_count++;
f8212f97
AD		 750
751 if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE)
752 rsc_count = ixgbe_get_rsc_count(rx_desc);
753
754 if (rsc_count) {
755 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
756 IXGBE_RXDADV_NEXTP_SHIFT;
757 next_buffer = &rx_ring->rx_buffer_info[nextp];
758 rx_ring->rsc_count += (rsc_count - 1);
759 } else {
760 next_buffer = &rx_ring->rx_buffer_info[i];
761 }
762
9a799d71 763 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97
AD		 764 if (skb->prev)
765 skb = ixgbe_transform_rsc_queue(skb);
9a799d71
AK		 766 rx_ring->stats.packets++;
767 rx_ring->stats.bytes += skb->len;
768 } else {
f8212f97
AD		 769 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
770 rx_buffer_info->skb = next_buffer->skb;
771 rx_buffer_info->dma = next_buffer->dma;
772 next_buffer->skb = skb;
773 next_buffer->dma = 0;
774 } else {
775 skb->next = next_buffer->skb;
776 skb->next->prev = skb;
777 }
9a799d71
AK		 778 adapter->non_eop_descs++;
779 goto next_desc;
780 }
781
782 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
783 dev_kfree_skb_irq(skb);
784 goto next_desc;
785 }
786
787 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 788
789 /* probably a little skewed due to removing CRC */
790 total_rx_bytes += skb->len;
791 total_rx_packets++;
792
74ce8dd2 793 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 794#ifdef IXGBE_FCOE
795 /* if ddp, not passing to ULD unless for FCP_RSP or error */
796 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
797 if (!ixgbe_fcoe_ddp(adapter, rx_desc, skb))
798 goto next_desc;
799#endif /* IXGBE_FCOE */
fdaff1ce 800 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 801
802next_desc:
803 rx_desc->wb.upper.status_error = 0;
804
805 /* return some buffers to hardware, one at a time is too slow */
806 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
807 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
808 cleaned_count = 0;
809 }
810
811 /* use prefetched values */
812 rx_desc = next_rxd;
f8212f97 813 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 814
815 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 816 }
817
9a799d71
AK		 818 rx_ring->next_to_clean = i;
819 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
820
821 if (cleaned_count)
822 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
823
f494e8fa
AV		 824 rx_ring->total_packets += total_rx_packets;
825 rx_ring->total_bytes += total_rx_bytes;
826 adapter->net_stats.rx_bytes += total_rx_bytes;
827 adapter->net_stats.rx_packets += total_rx_packets;
828
9a799d71
AK		 829 return cleaned;
830}
831
021230d4 832static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 833/**
834 * ixgbe_configure_msix - Configure MSI-X hardware
835 * @adapter: board private structure
836 *
837 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
838 * interrupts.
839 **/
840static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
841{
021230d4
AV		 842 struct ixgbe_q_vector *q_vector;
843 int i, j, q_vectors, v_idx, r_idx;
844 u32 mask;
9a799d71 845
021230d4 846 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 847
4df10466
JB		 848 /*
849 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 850 * corresponding register.
851 */
852 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 853 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 854 /* XXX for_each_bit(...) */
855 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 856 adapter->num_rx_queues);
021230d4
AV		 857
858 for (i = 0; i < q_vector->rxr_count; i++) {
859 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 860 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 861 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 862 adapter->num_rx_queues,
863 r_idx + 1);
021230d4
AV		 864 }
865 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 866 adapter->num_tx_queues);
021230d4
AV		 867
868 for (i = 0; i < q_vector->txr_count; i++) {
869 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 870 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 871 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 872 adapter->num_tx_queues,
873 r_idx + 1);
021230d4
AV		 874 }
875
30efa5a3 876 /* if this is a tx only vector halve the interrupt rate */
021230d4 877 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 878 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 879 else if (q_vector->rxr_count)
30efa5a3
JB		 880 /* rx only */
881 q_vector->eitr = adapter->eitr_param;
021230d4 882
fe49f04a 883 ixgbe_write_eitr(q_vector);
9a799d71
AK		 884 }
885
e8e26350
PW		 886 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
887 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
888 v_idx);
889 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
890 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 891 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
892
41fb9248 893 /* set up to autoclear timer, and the vectors */
021230d4 894 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 895 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 896 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 897}
898
f494e8fa
AV		 899enum latency_range {
900 lowest_latency = 0,
901 low_latency = 1,
902 bulk_latency = 2,
903 latency_invalid = 255
904};
905
906/**
907 * ixgbe_update_itr - update the dynamic ITR value based on statistics
908 * @adapter: pointer to adapter
909 * @eitr: eitr setting (ints per sec) to give last timeslice
910 * @itr_setting: current throttle rate in ints/second
911 * @packets: the number of packets during this measurement interval
912 * @bytes: the number of bytes during this measurement interval
913 *
914 * Stores a new ITR value based on packets and byte
915 * counts during the last interrupt. The advantage of per interrupt
916 * computation is faster updates and more accurate ITR for the current
917 * traffic pattern. Constants in this function were computed
918 * based on theoretical maximum wire speed and thresholds were set based
919 * on testing data as well as attempting to minimize response time
920 * while increasing bulk throughput.
921 * this functionality is controlled by the InterruptThrottleRate module
922 * parameter (see ixgbe_param.c)
923 **/
924static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 925 u32 eitr, u8 itr_setting,
926 int packets, int bytes)
f494e8fa
AV		 927{
928 unsigned int retval = itr_setting;
929 u32 timepassed_us;
930 u64 bytes_perint;
931
932 if (packets == 0)
933 goto update_itr_done;
934
935
936 /* simple throttlerate management
937 * 0-20MB/s lowest (100000 ints/s)
938 * 20-100MB/s low (20000 ints/s)
939 * 100-1249MB/s bulk (8000 ints/s)
940 */
941 /* what was last interrupt timeslice? */
942 timepassed_us = 1000000/eitr;
943 bytes_perint = bytes / timepassed_us; /* bytes/usec */
944
945 switch (itr_setting) {
946 case lowest_latency:
947 if (bytes_perint > adapter->eitr_low)
948 retval = low_latency;
949 break;
950 case low_latency:
951 if (bytes_perint > adapter->eitr_high)
952 retval = bulk_latency;
953 else if (bytes_perint <= adapter->eitr_low)
954 retval = lowest_latency;
955 break;
956 case bulk_latency:
957 if (bytes_perint <= adapter->eitr_high)
958 retval = low_latency;
959 break;
960 }
961
962update_itr_done:
963 return retval;
964}
965
509ee935
JB		 966/**
967 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 968 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 969 *
970 * This function is made to be called by ethtool and by the driver
971 * when it needs to update EITR registers at runtime. Hardware
972 * specific quirks/differences are taken care of here.
973 */
fe49f04a 974void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 975{
fe49f04a 976 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 977 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 978 int v_idx = q_vector->v_idx;
979 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
980
509ee935
JB		 981 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
982 /* must write high and low 16 bits to reset counter */
983 itr_reg |= (itr_reg << 16);
984 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
985 /*
986 * set the WDIS bit to not clear the timer bits and cause an
987 * immediate assertion of the interrupt
988 */
989 itr_reg |= IXGBE_EITR_CNT_WDIS;
990 }
991 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
992}
993
f494e8fa
AV		 994static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
995{
996 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 997 u32 new_itr;
998 u8 current_itr, ret_itr;
fe49f04a 999 int i, r_idx;
f494e8fa
AV		 1000 struct ixgbe_ring *rx_ring, *tx_ring;
1001
1002 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1003 for (i = 0; i < q_vector->txr_count; i++) {
1004 tx_ring = &(adapter->tx_ring[r_idx]);
1005 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1006 q_vector->tx_itr,
1007 tx_ring->total_packets,
1008 tx_ring->total_bytes);
f494e8fa
AV		 1009 /* if the result for this queue would decrease interrupt
1010 * rate for this vector then use that result */
30efa5a3 1011 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1012 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1013 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1014 r_idx + 1);
f494e8fa
AV		 1015 }
1016
1017 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1018 for (i = 0; i < q_vector->rxr_count; i++) {
1019 rx_ring = &(adapter->rx_ring[r_idx]);
1020 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1021 q_vector->rx_itr,
1022 rx_ring->total_packets,
1023 rx_ring->total_bytes);
f494e8fa
AV		 1024 /* if the result for this queue would decrease interrupt
1025 * rate for this vector then use that result */
30efa5a3 1026 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1027 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1028 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1029 r_idx + 1);
f494e8fa
AV		 1030 }
1031
30efa5a3 1032 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1033
1034 switch (current_itr) {
1035 /* counts and packets in update_itr are dependent on these numbers */
1036 case lowest_latency:
1037 new_itr = 100000;
1038 break;
1039 case low_latency:
1040 new_itr = 20000; /* aka hwitr = ~200 */
1041 break;
1042 case bulk_latency:
1043 default:
1044 new_itr = 8000;
1045 break;
1046 }
1047
1048 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1049 /* do an exponential smoothing */
1050 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1051
1052 /* save the algorithm value here, not the smoothed one */
1053 q_vector->eitr = new_itr;
fe49f04a
AD		 1054
1055 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1056 }
1057
1058 return;
1059}
1060
0befdb3e
JB		 1061static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1062{
1063 struct ixgbe_hw *hw = &adapter->hw;
1064
1065 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1066 (eicr & IXGBE_EICR_GPI_SDP1)) {
1067 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1068 /* write to clear the interrupt */
1069 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1070 }
1071}
cf8280ee 1072
e8e26350
PW		 1073static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1074{
1075 struct ixgbe_hw *hw = &adapter->hw;
1076
1077 if (eicr & IXGBE_EICR_GPI_SDP1) {
1078 /* Clear the interrupt */
1079 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1080 schedule_work(&adapter->multispeed_fiber_task);
1081 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1082 /* Clear the interrupt */
1083 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1084 schedule_work(&adapter->sfp_config_module_task);
1085 } else {
1086 /* Interrupt isn't for us... */
1087 return;
1088 }
1089}
1090
cf8280ee
JB		 1091static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1092{
1093 struct ixgbe_hw *hw = &adapter->hw;
1094
1095 adapter->lsc_int++;
1096 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1097 adapter->link_check_timeout = jiffies;
1098 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1099 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1100 schedule_work(&adapter->watchdog_task);
1101 }
1102}
1103
9a799d71
AK		 1104static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1105{
1106 struct net_device *netdev = data;
1107 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1108 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1109 u32 eicr;
1110
1111 /*
1112 * Workaround for Silicon errata. Use clear-by-write instead
1113 * of clear-by-read. Reading with EICS will return the
1114 * interrupt causes without clearing, which later be done
1115 * with the write to EICR.
1116 */
1117 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1118 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1119
cf8280ee
JB		 1120 if (eicr & IXGBE_EICR_LSC)
1121 ixgbe_check_lsc(adapter);
d4f80882 1122
e8e26350
PW		 1123 if (hw->mac.type == ixgbe_mac_82598EB)
1124 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1125
e8e26350
PW		 1126 if (hw->mac.type == ixgbe_mac_82599EB)
1127 ixgbe_check_sfp_event(adapter, eicr);
d4f80882
AV		 1128 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1129 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1130
1131 return IRQ_HANDLED;
1132}
1133
fe49f04a
AD		 1134static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1135 u64 qmask)
1136{
1137 u32 mask;
1138
1139 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1140 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1141 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1142 } else {
1143 mask = (qmask & 0xFFFFFFFF);
1144 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1145 mask = (qmask >> 32);
1146 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1147 }
1148 /* skip the flush */
1149}
1150
1151static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1152 u64 qmask)
1153{
1154 u32 mask;
1155
1156 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1157 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1158 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1159 } else {
1160 mask = (qmask & 0xFFFFFFFF);
1161 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1162 mask = (qmask >> 32);
1163 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1164 }
1165 /* skip the flush */
1166}
1167
9a799d71
AK		 1168static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1169{
021230d4
AV		 1170 struct ixgbe_q_vector *q_vector = data;
1171 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1172 struct ixgbe_ring *tx_ring;
021230d4
AV		 1173 int i, r_idx;
1174
1175 if (!q_vector->txr_count)
1176 return IRQ_HANDLED;
1177
1178 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1179 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1180 tx_ring = &(adapter->tx_ring[r_idx]);
3a581073
JB		 1181 tx_ring->total_bytes = 0;
1182 tx_ring->total_packets = 0;
021230d4 1183 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1184 r_idx + 1);
021230d4 1185 }
9a799d71 1186
91281fd3
AD		 1187 /* disable interrupts on this vector only */
1188 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1189 napi_schedule(&q_vector->napi);
1190
9a799d71
AK		 1191 return IRQ_HANDLED;
1192}
1193
021230d4
AV		 1194/**
1195 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1196 * @irq: unused
1197 * @data: pointer to our q_vector struct for this interrupt vector
1198 **/
9a799d71
AK		 1199static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1200{
021230d4
AV		 1201 struct ixgbe_q_vector *q_vector = data;
1202 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1203 struct ixgbe_ring *rx_ring;
021230d4 1204 int r_idx;
30efa5a3 1205 int i;
021230d4
AV		 1206
1207 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1208 for (i = 0; i < q_vector->rxr_count; i++) {
1209 rx_ring = &(adapter->rx_ring[r_idx]);
1210 rx_ring->total_bytes = 0;
1211 rx_ring->total_packets = 0;
1212 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1213 r_idx + 1);
1214 }
1215
021230d4
AV		 1216 if (!q_vector->rxr_count)
1217 return IRQ_HANDLED;
1218
30efa5a3 1219 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1220 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1221 /* disable interrupts on this vector only */
fe49f04a 1222 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
288379f0 1223 napi_schedule(&q_vector->napi);
021230d4
AV		 1224
1225 return IRQ_HANDLED;
1226}
1227
1228static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1229{
91281fd3
AD		 1230 struct ixgbe_q_vector *q_vector = data;
1231 struct ixgbe_adapter *adapter = q_vector->adapter;
1232 struct ixgbe_ring *ring;
1233 int r_idx;
1234 int i;
1235
1236 if (!q_vector->txr_count && !q_vector->rxr_count)
1237 return IRQ_HANDLED;
1238
1239 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1240 for (i = 0; i < q_vector->txr_count; i++) {
1241 ring = &(adapter->tx_ring[r_idx]);
1242 ring->total_bytes = 0;
1243 ring->total_packets = 0;
1244 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1245 r_idx + 1);
1246 }
1247
1248 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1249 for (i = 0; i < q_vector->rxr_count; i++) {
1250 ring = &(adapter->rx_ring[r_idx]);
1251 ring->total_bytes = 0;
1252 ring->total_packets = 0;
1253 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1254 r_idx + 1);
1255 }
1256
1257 /* disable interrupts on this vector only */
1258 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1259 napi_schedule(&q_vector->napi);
9a799d71 1260
9a799d71
AK		 1261 return IRQ_HANDLED;
1262}
1263
021230d4
AV		 1264/**
1265 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1266 * @napi: napi struct with our devices info in it
1267 * @budget: amount of work driver is allowed to do this pass, in packets
1268 *
f0848276
JB		 1269 * This function is optimized for cleaning one queue only on a single
1270 * q_vector!!!
021230d4 1271 **/
9a799d71
AK		 1272static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1273{
021230d4 1274 struct ixgbe_q_vector *q_vector =
b4617240 1275 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1276 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1277 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1278 int work_done = 0;
021230d4 1279 long r_idx;
9a799d71 1280
021230d4 1281 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1282 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1283#ifdef CONFIG_IXGBE_DCA
bd0362dd 1284 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1285 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1286#endif
9a799d71 1287
78b6f4ce 1288 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1289
021230d4
AV		 1290 /* If all Rx work done, exit the polling mode */
1291 if (work_done < budget) {
288379f0 1292 napi_complete(napi);
509ee935 1293 if (adapter->itr_setting & 1)
f494e8fa 1294 ixgbe_set_itr_msix(q_vector);
9a799d71 1295 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1296 ixgbe_irq_enable_queues(adapter,
1297 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1298 }
1299
1300 return work_done;
1301}
1302
f0848276 1303/**
91281fd3 1304 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1305 * @napi: napi struct with our devices info in it
1306 * @budget: amount of work driver is allowed to do this pass, in packets
1307 *
1308 * This function will clean more than one rx queue associated with a
1309 * q_vector.
1310 **/
91281fd3 1311static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1312{
1313 struct ixgbe_q_vector *q_vector =
1314 container_of(napi, struct ixgbe_q_vector, napi);
1315 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1316 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1317 int work_done = 0, i;
1318 long r_idx;
91281fd3
AD		 1319 bool tx_clean_complete = true;
1320
1321 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1322 for (i = 0; i < q_vector->txr_count; i++) {
1323 ring = &(adapter->tx_ring[r_idx]);
1324#ifdef CONFIG_IXGBE_DCA
1325 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1326 ixgbe_update_tx_dca(adapter, ring);
1327#endif
1328 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1329 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1330 r_idx + 1);
1331 }
f0848276
JB		 1332
1333 /* attempt to distribute budget to each queue fairly, but don't allow
1334 * the budget to go below 1 because we'll exit polling */
1335 budget /= (q_vector->rxr_count ?: 1);
1336 budget = max(budget, 1);
1337 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1338 for (i = 0; i < q_vector->rxr_count; i++) {
91281fd3 1339 ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1340#ifdef CONFIG_IXGBE_DCA
f0848276 1341 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1342 ixgbe_update_rx_dca(adapter, ring);
f0848276 1343#endif
91281fd3 1344 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1345 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1346 r_idx + 1);
1347 }
1348
1349 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
91281fd3 1350 ring = &(adapter->rx_ring[r_idx]);
f0848276 1351 /* If all Rx work done, exit the polling mode */
7f821875 1352 if (work_done < budget) {
288379f0 1353 napi_complete(napi);
509ee935 1354 if (adapter->itr_setting & 1)
f0848276
JB		 1355 ixgbe_set_itr_msix(q_vector);
1356 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1357 ixgbe_irq_enable_queues(adapter,
1358 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1359 return 0;
1360 }
1361
1362 return work_done;
1363}
91281fd3
AD		 1364
1365/**
1366 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1367 * @napi: napi struct with our devices info in it
1368 * @budget: amount of work driver is allowed to do this pass, in packets
1369 *
1370 * This function is optimized for cleaning one queue only on a single
1371 * q_vector!!!
1372 **/
1373static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1374{
1375 struct ixgbe_q_vector *q_vector =
1376 container_of(napi, struct ixgbe_q_vector, napi);
1377 struct ixgbe_adapter *adapter = q_vector->adapter;
1378 struct ixgbe_ring *tx_ring = NULL;
1379 int work_done = 0;
1380 long r_idx;
1381
1382 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1383 tx_ring = &(adapter->tx_ring[r_idx]);
1384#ifdef CONFIG_IXGBE_DCA
1385 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1386 ixgbe_update_tx_dca(adapter, tx_ring);
1387#endif
1388
1389 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1390 work_done = budget;
1391
1392 /* If all Rx work done, exit the polling mode */
1393 if (work_done < budget) {
1394 napi_complete(napi);
1395 if (adapter->itr_setting & 1)
1396 ixgbe_set_itr_msix(q_vector);
1397 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1398 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1399 }
1400
1401 return work_done;
1402}
1403
021230d4 1404static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1405 int r_idx)
021230d4 1406{
7a921c93
AD		 1407 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1408
1409 set_bit(r_idx, q_vector->rxr_idx);
1410 q_vector->rxr_count++;
021230d4
AV		 1411}
1412
1413static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1414 int t_idx)
021230d4 1415{
7a921c93
AD		 1416 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1417
1418 set_bit(t_idx, q_vector->txr_idx);
1419 q_vector->txr_count++;
021230d4
AV		 1420}
1421
9a799d71 1422/**
021230d4
AV		 1423 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1424 * @adapter: board private structure to initialize
1425 * @vectors: allotted vector count for descriptor rings
9a799d71 1426 *
021230d4
AV		 1427 * This function maps descriptor rings to the queue-specific vectors
1428 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1429 * one vector per ring/queue, but on a constrained vector budget, we
1430 * group the rings as "efficiently" as possible. You would add new
1431 * mapping configurations in here.
9a799d71 1432 **/
021230d4 1433static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1434 int vectors)
021230d4
AV		 1435{
1436 int v_start = 0;
1437 int rxr_idx = 0, txr_idx = 0;
1438 int rxr_remaining = adapter->num_rx_queues;
1439 int txr_remaining = adapter->num_tx_queues;
1440 int i, j;
1441 int rqpv, tqpv;
1442 int err = 0;
1443
1444 /* No mapping required if MSI-X is disabled. */
1445 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1446 goto out;
9a799d71 1447
021230d4
AV		 1448 /*
1449 * The ideal configuration...
1450 * We have enough vectors to map one per queue.
1451 */
1452 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1453 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1454 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1455
021230d4
AV		 1456 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1457 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1458
9a799d71 1459 goto out;
021230d4 1460 }
9a799d71 1461
021230d4
AV		 1462 /*
1463 * If we don't have enough vectors for a 1-to-1
1464 * mapping, we'll have to group them so there are
1465 * multiple queues per vector.
1466 */
1467 /* Re-adjusting *qpv takes care of the remainder. */
1468 for (i = v_start; i < vectors; i++) {
1469 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1470 for (j = 0; j < rqpv; j++) {
1471 map_vector_to_rxq(adapter, i, rxr_idx);
1472 rxr_idx++;
1473 rxr_remaining--;
1474 }
1475 }
1476 for (i = v_start; i < vectors; i++) {
1477 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1478 for (j = 0; j < tqpv; j++) {
1479 map_vector_to_txq(adapter, i, txr_idx);
1480 txr_idx++;
1481 txr_remaining--;
9a799d71 1482 }
9a799d71
AK		 1483 }
1484
021230d4
AV		 1485out:
1486 return err;
1487}
1488
1489/**
1490 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1491 * @adapter: board private structure
1492 *
1493 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1494 * interrupts from the kernel.
1495 **/
1496static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1497{
1498 struct net_device *netdev = adapter->netdev;
1499 irqreturn_t (*handler)(int, void *);
1500 int i, vector, q_vectors, err;
cb13fc20 1501 int ri=0, ti=0;
021230d4
AV		 1502
1503 /* Decrement for Other and TCP Timer vectors */
1504 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1505
1506 /* Map the Tx/Rx rings to the vectors we were allotted. */
1507 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1508 if (err)
1509 goto out;
1510
1511#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1512 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1513 &ixgbe_msix_clean_many)
021230d4 1514 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1515 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1516
1517 if(handler == &ixgbe_msix_clean_rx) {
1518 sprintf(adapter->name[vector], "%s-%s-%d",
1519 netdev->name, "rx", ri++);
1520 }
1521 else if(handler == &ixgbe_msix_clean_tx) {
1522 sprintf(adapter->name[vector], "%s-%s-%d",
1523 netdev->name, "tx", ti++);
1524 }
1525 else
1526 sprintf(adapter->name[vector], "%s-%s-%d",
1527 netdev->name, "TxRx", vector);
1528
021230d4 1529 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1530 handler, 0, adapter->name[vector],
7a921c93 1531 adapter->q_vector[vector]);
9a799d71
AK		 1532 if (err) {
1533 DPRINTK(PROBE, ERR,
b4617240
PW		 1534 "request_irq failed for MSIX interrupt "
1535 "Error: %d\n", err);
021230d4 1536 goto free_queue_irqs;
9a799d71 1537 }
9a799d71
AK		 1538 }
1539
021230d4
AV		 1540 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1541 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1542 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1543 if (err) {
1544 DPRINTK(PROBE, ERR,
1545 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1546 goto free_queue_irqs;
9a799d71
AK		 1547 }
1548
9a799d71
AK		 1549 return 0;
1550
021230d4
AV		 1551free_queue_irqs:
1552 for (i = vector - 1; i >= 0; i--)
1553 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1554 adapter->q_vector[i]);
021230d4
AV		 1555 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1556 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1557 kfree(adapter->msix_entries);
1558 adapter->msix_entries = NULL;
021230d4 1559out:
9a799d71
AK		 1560 return err;
1561}
1562
f494e8fa
AV		 1563static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1564{
7a921c93 1565 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1566 u8 current_itr;
1567 u32 new_itr = q_vector->eitr;
1568 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1569 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1570
30efa5a3 1571 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1572 q_vector->tx_itr,
1573 tx_ring->total_packets,
1574 tx_ring->total_bytes);
30efa5a3 1575 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1576 q_vector->rx_itr,
1577 rx_ring->total_packets,
1578 rx_ring->total_bytes);
f494e8fa 1579
30efa5a3 1580 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1581
1582 switch (current_itr) {
1583 /* counts and packets in update_itr are dependent on these numbers */
1584 case lowest_latency:
1585 new_itr = 100000;
1586 break;
1587 case low_latency:
1588 new_itr = 20000; /* aka hwitr = ~200 */
1589 break;
1590 case bulk_latency:
1591 new_itr = 8000;
1592 break;
1593 default:
1594 break;
1595 }
1596
1597 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1598 /* do an exponential smoothing */
1599 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1600
1601 /* save the algorithm value here, not the smoothed one */
1602 q_vector->eitr = new_itr;
fe49f04a
AD		 1603
1604 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1605 }
1606
1607 return;
1608}
1609
79aefa45
AD		 1610/**
1611 * ixgbe_irq_enable - Enable default interrupt generation settings
1612 * @adapter: board private structure
1613 **/
1614static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1615{
1616 u32 mask;
835462fc
NS		 1617
1618 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1619 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1620 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1621 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1622 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1623 mask |= IXGBE_EIMS_GPI_SDP1;
1624 mask |= IXGBE_EIMS_GPI_SDP2;
1625 }
1626
79aefa45 1627 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1628 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1629 IXGBE_WRITE_FLUSH(&adapter->hw);
1630}
021230d4 1631
9a799d71 1632/**
021230d4 1633 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1634 * @irq: interrupt number
1635 * @data: pointer to a network interface device structure
9a799d71
AK		 1636 **/
1637static irqreturn_t ixgbe_intr(int irq, void *data)
1638{
1639 struct net_device *netdev = data;
1640 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1641 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1642 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1643 u32 eicr;
1644
54037505
DS		 1645 /*
1646 * Workaround for silicon errata. Mask the interrupts
1647 * before the read of EICR.
1648 */
1649 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1650
021230d4
AV		 1651 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1652 * therefore no explict interrupt disable is necessary */
1653 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1654 if (!eicr) {
1655 /* shared interrupt alert!
1656 * make sure interrupts are enabled because the read will
1657 * have disabled interrupts due to EIAM */
1658 ixgbe_irq_enable(adapter);
9a799d71 1659 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1660 }
9a799d71 1661
cf8280ee
JB		 1662 if (eicr & IXGBE_EICR_LSC)
1663 ixgbe_check_lsc(adapter);
021230d4 1664
e8e26350
PW		 1665 if (hw->mac.type == ixgbe_mac_82599EB)
1666 ixgbe_check_sfp_event(adapter, eicr);
1667
0befdb3e
JB		 1668 ixgbe_check_fan_failure(adapter, eicr);
1669
7a921c93 1670 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1671 adapter->tx_ring[0].total_packets = 0;
1672 adapter->tx_ring[0].total_bytes = 0;
1673 adapter->rx_ring[0].total_packets = 0;
1674 adapter->rx_ring[0].total_bytes = 0;
021230d4 1675 /* would disable interrupts here but EIAM disabled it */
7a921c93 1676 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1677 }
1678
1679 return IRQ_HANDLED;
1680}
1681
021230d4
AV		 1682static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1683{
1684 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1685
1686 for (i = 0; i < q_vectors; i++) {
7a921c93 1687 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1688 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1689 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1690 q_vector->rxr_count = 0;
1691 q_vector->txr_count = 0;
1692 }
1693}
1694
9a799d71
AK		 1695/**
1696 * ixgbe_request_irq - initialize interrupts
1697 * @adapter: board private structure
1698 *
1699 * Attempts to configure interrupts using the best available
1700 * capabilities of the hardware and kernel.
1701 **/
021230d4 1702static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1703{
1704 struct net_device *netdev = adapter->netdev;
021230d4 1705 int err;
9a799d71 1706
021230d4
AV		 1707 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1708 err = ixgbe_request_msix_irqs(adapter);
1709 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1710 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1711 netdev->name, netdev);
021230d4
AV		 1712 } else {
1713 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1714 netdev->name, netdev);
9a799d71
AK		 1715 }
1716
9a799d71
AK		 1717 if (err)
1718 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1719
9a799d71
AK		 1720 return err;
1721}
1722
1723static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1724{
1725 struct net_device *netdev = adapter->netdev;
1726
1727 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1728 int i, q_vectors;
9a799d71 1729
021230d4
AV		 1730 q_vectors = adapter->num_msix_vectors;
1731
1732 i = q_vectors - 1;
9a799d71 1733 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1734
021230d4
AV		 1735 i--;
1736 for (; i >= 0; i--) {
1737 free_irq(adapter->msix_entries[i].vector,
7a921c93 1738 adapter->q_vector[i]);
021230d4
AV		 1739 }
1740
1741 ixgbe_reset_q_vectors(adapter);
1742 } else {
1743 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1744 }
1745}
1746
22d5a71b
JB		 1747/**
1748 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1749 * @adapter: board private structure
1750 **/
1751static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1752{
835462fc
NS		 1753 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1754 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1755 } else {
1756 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1757 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1758 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1759 }
1760 IXGBE_WRITE_FLUSH(&adapter->hw);
1761 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1762 int i;
1763 for (i = 0; i < adapter->num_msix_vectors; i++)
1764 synchronize_irq(adapter->msix_entries[i].vector);
1765 } else {
1766 synchronize_irq(adapter->pdev->irq);
1767 }
1768}
1769
9a799d71
AK		 1770/**
1771 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1772 *
1773 **/
1774static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1775{
9a799d71
AK		 1776 struct ixgbe_hw *hw = &adapter->hw;
1777
021230d4 1778 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1779 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1780
e8e26350
PW		 1781 ixgbe_set_ivar(adapter, 0, 0, 0);
1782 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1783
1784 map_vector_to_rxq(adapter, 0, 0);
1785 map_vector_to_txq(adapter, 0, 0);
1786
1787 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1788}
1789
1790/**
3a581073 1791 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1792 * @adapter: board private structure
1793 *
1794 * Configure the Tx unit of the MAC after a reset.
1795 **/
1796static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1797{
12207e49 1798 u64 tdba;
9a799d71 1799 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1800 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1801
1802 /* Setup the HW Tx Head and Tail descriptor pointers */
1803 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1804 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1805 j = ring->reg_idx;
1806 tdba = ring->dma;
1807 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1808 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1809 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1810 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1811 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1812 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1813 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1814 adapter->tx_ring[i].head = IXGBE_TDH(j);
1815 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1816 /* Disable Tx Head Writeback RO bit, since this hoses
1817 * bookkeeping if things aren't delivered in order.
1818 */
e01c31a5 1819 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1820 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1821 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1822 }
e8e26350
PW		 1823 if (hw->mac.type == ixgbe_mac_82599EB) {
1824 /* We enable 8 traffic classes, DCB only */
1825 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1826 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1827 IXGBE_MTQC_8TC_8TQ));
1828 }
9a799d71
AK		 1829}
1830
e8e26350 1831#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c
JB		 1832
1833static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1834{
1835 struct ixgbe_ring *rx_ring;
1836 u32 srrctl;
e8e26350 1837 int queue0 = 0;
3be1adfb 1838 unsigned long mask;
0cefafad 1839 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 1840
e8e26350 1841 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
163de42e 1842 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
0cefafad 1843 int dcb_i = feature[RING_F_DCB].indices;
163de42e
AD		 1844 if (dcb_i == 8)
1845 queue0 = index >> 4;
1846 else if (dcb_i == 4)
1847 queue0 = index >> 5;
1848 else
1849 dev_err(&adapter->pdev->dev, "Invalid DCB "
1850 "configuration\n");
0331a832
YZ		 1851#ifdef IXGBE_FCOE
1852 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1853 struct ixgbe_ring_feature *f;
1854
1855 rx_ring = &adapter->rx_ring[queue0];
1856 f = &adapter->ring_feature[RING_F_FCOE];
1857 if ((queue0 == 0) && (index > rx_ring->reg_idx))
1858 queue0 = f->mask + index -
1859 rx_ring->reg_idx - 1;
1860 }
1861#endif /* IXGBE_FCOE */
163de42e
AD		 1862 } else {
1863 queue0 = index;
1864 }
cc41ac7c 1865 } else {
0cefafad 1866 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb
AD		 1867 queue0 = index & mask;
1868 index = index & mask;
cc41ac7c 1869 }
3be1adfb 1870
cc41ac7c
JB		 1871 rx_ring = &adapter->rx_ring[queue0];
1872
1873 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1874
1875 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1876 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1877
afafd5b0
AD		 1878 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1879 IXGBE_SRRCTL_BSIZEHDR_MASK;
1880
cc41ac7c 1881 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
afafd5b0
AD		 1882#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1883 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1884#else
1885 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1886#endif
cc41ac7c 1887 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 1888 } else {
afafd5b0
AD		 1889 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1890 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 1891 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 1892 }
e8e26350 1893
cc41ac7c
JB		 1894 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1895}
9a799d71 1896
0cefafad
JB		 1897static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1898{
1899 u32 mrqc = 0;
1900 int mask;
1901
1902 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1903 return mrqc;
1904
1905 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1906#ifdef CONFIG_IXGBE_DCB
1907 | IXGBE_FLAG_DCB_ENABLED
1908#endif
1909 );
1910
1911 switch (mask) {
1912 case (IXGBE_FLAG_RSS_ENABLED):
1913 mrqc = IXGBE_MRQC_RSSEN;
1914 break;
1915#ifdef CONFIG_IXGBE_DCB
1916 case (IXGBE_FLAG_DCB_ENABLED):
1917 mrqc = IXGBE_MRQC_RT8TCEN;
1918 break;
1919#endif /* CONFIG_IXGBE_DCB */
1920 default:
1921 break;
1922 }
1923
1924 return mrqc;
1925}
1926
9a799d71 1927/**
3a581073 1928 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1929 * @adapter: board private structure
1930 *
1931 * Configure the Rx unit of the MAC after a reset.
1932 **/
1933static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1934{
1935 u64 rdba;
1936 struct ixgbe_hw *hw = &adapter->hw;
1937 struct net_device *netdev = adapter->netdev;
1938 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1939 int i, j;
9a799d71 1940 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1941 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1942 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1943 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1944 u32 fctrl, hlreg0;
509ee935 1945 u32 reta = 0, mrqc = 0;
cc41ac7c 1946 u32 rdrxctl;
f8212f97 1947 u32 rscctrl;
7c6e0a43 1948 int rx_buf_len;
9a799d71
AK		 1949
1950 /* Decide whether to use packet split mode or not */
762f4c57 1951 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 1952
eacd73f7
YZ		 1953#ifdef IXGBE_FCOE
1954 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
1955 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1956#endif /* IXGBE_FCOE */
1957
9a799d71
AK		 1958 /* Set the RX buffer length according to the mode */
1959 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1960 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 1961 if (hw->mac.type == ixgbe_mac_82599EB) {
1962 /* PSRTYPE must be initialized in 82599 */
1963 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1964 IXGBE_PSRTYPE_UDPHDR |
1965 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 1966 IXGBE_PSRTYPE_IPV6HDR |
1967 IXGBE_PSRTYPE_L2HDR;
e8e26350
PW		 1968 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1969 }
9a799d71 1970 } else {
f8212f97
AD		 1971 if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) &&
1972 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 1973 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1974 else
7c6e0a43 1975 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1976 }
1977
1978 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1979 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1980 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 1981 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 1982 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1983
1984 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1985 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1986 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1987 else
1988 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1
YZ		 1989#ifdef IXGBE_FCOE
1990 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
1991 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1992#endif
9a799d71
AK		 1993 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1994
9a799d71
AK		 1995 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1996 /* disable receives while setting up the descriptors */
1997 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1998 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1999
0cefafad
JB		 2000 /*
2001 * Setup the HW Rx Head and Tail Descriptor Pointers and
2002 * the Base and Length of the Rx Descriptor Ring
2003 */
9a799d71
AK		 2004 for (i = 0; i < adapter->num_rx_queues; i++) {
2005 rdba = adapter->rx_ring[i].dma;
7c6e0a43 2006 j = adapter->rx_ring[i].reg_idx;
284901a9 2007 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2008 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2009 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2010 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2011 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2012 adapter->rx_ring[i].head = IXGBE_RDH(j);
2013 adapter->rx_ring[i].tail = IXGBE_RDT(j);
2014 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
cc41ac7c 2015
63f39bd1
YZ		 2016#ifdef IXGBE_FCOE
2017 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2018 struct ixgbe_ring_feature *f;
2019 f = &adapter->ring_feature[RING_F_FCOE];
2020 if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
2021 (i >= f->mask) && (i < f->mask + f->indices))
2022 adapter->rx_ring[i].rx_buf_len =
2023 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2024 }
2025
2026#endif /* IXGBE_FCOE */
cc41ac7c 2027 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 2028 }
2029
e8e26350
PW		 2030 if (hw->mac.type == ixgbe_mac_82598EB) {
2031 /*
2032 * For VMDq support of different descriptor types or
2033 * buffer sizes through the use of multiple SRRCTL
2034 * registers, RDRXCTL.MVMEN must be set to 1
2035 *
2036 * also, the manual doesn't mention it clearly but DCA hints
2037 * will only use queue 0's tags unless this bit is set. Side
2038 * effects of setting this bit are only that SRRCTL must be
2039 * fully programmed [0..15]
2040 */
2a41ff81
JB		 2041 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2042 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2043 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2044 }
177db6ff 2045
e8e26350 2046 /* Program MRQC for the distribution of queues */
0cefafad 2047 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2048
021230d4 2049 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2050 /* Fill out redirection table */
021230d4
AV		 2051 for (i = 0, j = 0; i < 128; i++, j++) {
2052 if (j == adapter->ring_feature[RING_F_RSS].indices)
2053 j = 0;
2054 /* reta = 4-byte sliding window of
2055 * 0x00..(indices-1)(indices-1)00..etc. */
2056 reta = (reta << 8) | (j * 0x11);
2057 if ((i & 3) == 3)
2058 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2059 }
2060
2061 /* Fill out hash function seeds */
2062 for (i = 0; i < 10; i++)
7c6e0a43 2063 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2064
2a41ff81
JB		 2065 if (hw->mac.type == ixgbe_mac_82598EB)
2066 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2067 /* Perform hash on these packet types */
2a41ff81
JB		 2068 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2069 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2070 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2071 | IXGBE_MRQC_RSS_FIELD_IPV6
2072 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2073 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2074 }
2a41ff81 2075 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2076
021230d4
AV		 2077 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2078
2079 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2080 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2081 /* Disable indicating checksum in descriptor, enables
2082 * RSS hash */
9a799d71 2083 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2084 }
021230d4
AV		 2085 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2086 /* Enable IPv4 payload checksum for UDP fragments
2087 * if PCSD is not set */
2088 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2089 }
2090
2091 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2092
2093 if (hw->mac.type == ixgbe_mac_82599EB) {
2094 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2095 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2096 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2097 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2098 }
f8212f97
AD		 2099
2100 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) {
2101 /* Enable 82599 HW-RSC */
2102 for (i = 0; i < adapter->num_rx_queues; i++) {
2103 j = adapter->rx_ring[i].reg_idx;
2104 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2105 rscctrl |= IXGBE_RSCCTL_RSCEN;
2106 /*
e76678dd
AD		 2107 * we must limit the number of descriptors so that the
2108 * total size of max desc * buf_len is not greater
2109 * than 65535
f8212f97 2110 */
e76678dd
AD		 2111 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2112#if (MAX_SKB_FRAGS > 16)
2113 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2114#elif (MAX_SKB_FRAGS > 8)
f8212f97 2115 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
e76678dd
AD		 2116#elif (MAX_SKB_FRAGS > 4)
2117 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
f8212f97 2118#else
e76678dd 2119 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
f8212f97 2120#endif
e76678dd
AD		 2121 } else {
2122 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2123 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2124 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2125 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2126 else
2127 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2128 }
f8212f97
AD		 2129 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2130 }
2131 /* Disable RSC for ACK packets */
2132 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2133 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2134 }
9a799d71
AK		 2135}
2136
068c89b0
DS		 2137static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2138{
2139 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2140 struct ixgbe_hw *hw = &adapter->hw;
2141
2142 /* add VID to filter table */
2143 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2144}
2145
2146static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2147{
2148 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2149 struct ixgbe_hw *hw = &adapter->hw;
2150
2151 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2152 ixgbe_irq_disable(adapter);
2153
2154 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2155
2156 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2157 ixgbe_irq_enable(adapter);
2158
2159 /* remove VID from filter table */
2160 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2161}
2162
9a799d71 2163static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2164 struct vlan_group *grp)
9a799d71
AK		 2165{
2166 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2167 u32 ctrl;
e8e26350 2168 int i, j;
9a799d71 2169
d4f80882
AV		 2170 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2171 ixgbe_irq_disable(adapter);
9a799d71
AK		 2172 adapter->vlgrp = grp;
2173
2f90b865
AD		 2174 /*
2175 * For a DCB driver, always enable VLAN tag stripping so we can
2176 * still receive traffic from a DCB-enabled host even if we're
2177 * not in DCB mode.
2178 */
2179 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 2180 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2181 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2182 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2183 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2184 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2185 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 2186 /* enable VLAN tag insert/strip */
2187 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 2188 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2189 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 2190 for (i = 0; i < adapter->num_rx_queues; i++) {
2191 j = adapter->rx_ring[i].reg_idx;
2192 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2193 ctrl |= IXGBE_RXDCTL_VME;
2194 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2195 }
9a799d71 2196 }
e8e26350 2197 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2198
d4f80882
AV		 2199 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2200 ixgbe_irq_enable(adapter);
9a799d71
AK		 2201}
2202
9a799d71
AK		 2203static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2204{
2205 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2206
2207 if (adapter->vlgrp) {
2208 u16 vid;
2209 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2210 if (!vlan_group_get_device(adapter->vlgrp, vid))
2211 continue;
2212 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2213 }
2214 }
2215}
2216
2c5645cf
CL		 2217static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2218{
2219 struct dev_mc_list *mc_ptr;
2220 u8 *addr = *mc_addr_ptr;
2221 *vmdq = 0;
2222
2223 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2224 if (mc_ptr->next)
2225 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2226 else
2227 *mc_addr_ptr = NULL;
2228
2229 return addr;
2230}
2231
9a799d71 2232/**
2c5645cf 2233 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2234 * @netdev: network interface device structure
2235 *
2c5645cf
CL		 2236 * The set_rx_method entry point is called whenever the unicast/multicast
2237 * address list or the network interface flags are updated. This routine is
2238 * responsible for configuring the hardware for proper unicast, multicast and
2239 * promiscuous mode.
9a799d71 2240 **/
2c5645cf 2241static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2242{
2243 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2244 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2245 u32 fctrl, vlnctrl;
2c5645cf
CL		 2246 u8 *addr_list = NULL;
2247 int addr_count = 0;
9a799d71
AK		 2248
2249 /* Check for Promiscuous and All Multicast modes */
2250
2251 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2252 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2253
2254 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2255 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2256 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2257 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2258 } else {
746b9f02
PM		 2259 if (netdev->flags & IFF_ALLMULTI) {
2260 fctrl |= IXGBE_FCTRL_MPE;
2261 fctrl &= ~IXGBE_FCTRL_UPE;
2262 } else {
2263 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2264 }
3d01625a 2265 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2266 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2267 }
2268
2269 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2270 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2271
2c5645cf 2272 /* reprogram secondary unicast list */
ccffad25 2273 hw->mac.ops.update_uc_addr_list(hw, &netdev->uc_list);
9a799d71 2274
2c5645cf
CL		 2275 /* reprogram multicast list */
2276 addr_count = netdev->mc_count;
2277 if (addr_count)
2278 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2279 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2280 ixgbe_addr_list_itr);
9a799d71
AK		 2281}
2282
021230d4
AV		 2283static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2284{
2285 int q_idx;
2286 struct ixgbe_q_vector *q_vector;
2287 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2288
2289 /* legacy and MSI only use one vector */
2290 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2291 q_vectors = 1;
2292
2293 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2294 struct napi_struct *napi;
7a921c93 2295 q_vector = adapter->q_vector[q_idx];
f0848276 2296 napi = &q_vector->napi;
91281fd3
AD		 2297 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2298 if (!q_vector->rxr_count || !q_vector->txr_count) {
2299 if (q_vector->txr_count == 1)
2300 napi->poll = &ixgbe_clean_txonly;
2301 else if (q_vector->rxr_count == 1)
2302 napi->poll = &ixgbe_clean_rxonly;
2303 }
2304 }
f0848276
JB		 2305
2306 napi_enable(napi);
021230d4
AV		 2307 }
2308}
2309
2310static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2311{
2312 int q_idx;
2313 struct ixgbe_q_vector *q_vector;
2314 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2315
2316 /* legacy and MSI only use one vector */
2317 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2318 q_vectors = 1;
2319
2320 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2321 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2322 napi_disable(&q_vector->napi);
2323 }
2324}
2325
7a6b6f51 2326#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2327/*
2328 * ixgbe_configure_dcb - Configure DCB hardware
2329 * @adapter: ixgbe adapter struct
2330 *
2331 * This is called by the driver on open to configure the DCB hardware.
2332 * This is also called by the gennetlink interface when reconfiguring
2333 * the DCB state.
2334 */
2335static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2336{
2337 struct ixgbe_hw *hw = &adapter->hw;
2338 u32 txdctl, vlnctrl;
2339 int i, j;
2340
2341 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2342 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2343 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2344
2345 /* reconfigure the hardware */
2346 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2347
2348 for (i = 0; i < adapter->num_tx_queues; i++) {
2349 j = adapter->tx_ring[i].reg_idx;
2350 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2351 /* PThresh workaround for Tx hang with DFP enabled. */
2352 txdctl |= 32;
2353 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2354 }
2355 /* Enable VLAN tag insert/strip */
2356 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2357 if (hw->mac.type == ixgbe_mac_82598EB) {
2358 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2359 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2360 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2361 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2362 vlnctrl |= IXGBE_VLNCTRL_VFE;
2363 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2364 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2365 for (i = 0; i < adapter->num_rx_queues; i++) {
2366 j = adapter->rx_ring[i].reg_idx;
2367 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2368 vlnctrl |= IXGBE_RXDCTL_VME;
2369 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2370 }
2371 }
2f90b865
AD		 2372 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2373}
2374
2375#endif
9a799d71
AK		 2376static void ixgbe_configure(struct ixgbe_adapter *adapter)
2377{
2378 struct net_device *netdev = adapter->netdev;
2379 int i;
2380
2c5645cf 2381 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2382
2383 ixgbe_restore_vlan(adapter);
7a6b6f51 2384#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2385 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2386 netif_set_gso_max_size(netdev, 32768);
2387 ixgbe_configure_dcb(adapter);
2388 } else {
2389 netif_set_gso_max_size(netdev, 65536);
2390 }
2391#else
2392 netif_set_gso_max_size(netdev, 65536);
2393#endif
9a799d71 2394
eacd73f7
YZ		 2395#ifdef IXGBE_FCOE
2396 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2397 ixgbe_configure_fcoe(adapter);
2398
2399#endif /* IXGBE_FCOE */
9a799d71
AK		 2400 ixgbe_configure_tx(adapter);
2401 ixgbe_configure_rx(adapter);
2402 for (i = 0; i < adapter->num_rx_queues; i++)
2403 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2404 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2405}
2406
e8e26350
PW		 2407static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2408{
2409 switch (hw->phy.type) {
2410 case ixgbe_phy_sfp_avago:
2411 case ixgbe_phy_sfp_ftl:
2412 case ixgbe_phy_sfp_intel:
2413 case ixgbe_phy_sfp_unknown:
2414 case ixgbe_phy_tw_tyco:
2415 case ixgbe_phy_tw_unknown:
2416 return true;
2417 default:
2418 return false;
2419 }
2420}
2421
0ecc061d 2422/**
e8e26350
PW		 2423 * ixgbe_sfp_link_config - set up SFP+ link
2424 * @adapter: pointer to private adapter struct
2425 **/
2426static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2427{
2428 struct ixgbe_hw *hw = &adapter->hw;
2429
2430 if (hw->phy.multispeed_fiber) {
2431 /*
2432 * In multispeed fiber setups, the device may not have
2433 * had a physical connection when the driver loaded.
2434 * If that's the case, the initial link configuration
2435 * couldn't get the MAC into 10G or 1G mode, so we'll
2436 * never have a link status change interrupt fire.
2437 * We need to try and force an autonegotiation
2438 * session, then bring up link.
2439 */
2440 hw->mac.ops.setup_sfp(hw);
2441 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2442 schedule_work(&adapter->multispeed_fiber_task);
2443 } else {
2444 /*
2445 * Direct Attach Cu and non-multispeed fiber modules
2446 * still need to be configured properly prior to
2447 * attempting link.
2448 */
2449 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2450 schedule_work(&adapter->sfp_config_module_task);
2451 }
2452}
2453
2454/**
2455 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2456 * @hw: pointer to private hardware struct
2457 *
2458 * Returns 0 on success, negative on failure
2459 **/
e8e26350 2460static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2461{
2462 u32 autoneg;
2463 bool link_up = false;
2464 u32 ret = IXGBE_ERR_LINK_SETUP;
2465
2466 if (hw->mac.ops.check_link)
2467 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2468
2469 if (ret)
2470 goto link_cfg_out;
2471
2472 if (hw->mac.ops.get_link_capabilities)
2473 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2474 &hw->mac.autoneg);
2475 if (ret)
2476 goto link_cfg_out;
2477
2478 if (hw->mac.ops.setup_link_speed)
2479 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
0ecc061d
PWJ		 2480link_cfg_out:
2481 return ret;
2482}
2483
e8e26350
PW		 2484#define IXGBE_MAX_RX_DESC_POLL 10
2485static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2486 int rxr)
2487{
2488 int j = adapter->rx_ring[rxr].reg_idx;
2489 int k;
2490
2491 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2492 if (IXGBE_READ_REG(&adapter->hw,
2493 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2494 break;
2495 else
2496 msleep(1);
2497 }
2498 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2499 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2500 "not set within the polling period\n", rxr);
2501 }
2502 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2503 (adapter->rx_ring[rxr].count - 1));
2504}
2505
9a799d71
AK		 2506static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2507{
2508 struct net_device *netdev = adapter->netdev;
9a799d71 2509 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2510 int i, j = 0;
e8e26350 2511 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2512 int err;
9a799d71 2513 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2514 u32 txdctl, rxdctl, mhadd;
e8e26350 2515 u32 dmatxctl;
021230d4 2516 u32 gpie;
9a799d71 2517
5eba3699
AV		 2518 ixgbe_get_hw_control(adapter);
2519
021230d4
AV		 2520 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2521 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2522 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2523 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2524 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2525 } else {
2526 /* MSI only */
021230d4 2527 gpie = 0;
9a799d71 2528 }
021230d4
AV		 2529 /* XXX: to interrupt immediately for EICS writes, enable this */
2530 /* gpie |= IXGBE_GPIE_EIMEN; */
2531 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2532 }
2533
021230d4
AV		 2534 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2535 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2536 * specifically only auto mask tx and rx interrupts */
2537 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2538 }
9a799d71 2539
0befdb3e
JB		 2540 /* Enable fan failure interrupt if media type is copper */
2541 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2542 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2543 gpie |= IXGBE_SDP1_GPIEN;
2544 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2545 }
2546
e8e26350
PW		 2547 if (hw->mac.type == ixgbe_mac_82599EB) {
2548 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2549 gpie |= IXGBE_SDP1_GPIEN;
2550 gpie |= IXGBE_SDP2_GPIEN;
2551 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2552 }
2553
63f39bd1
YZ		 2554#ifdef IXGBE_FCOE
2555 /* adjust max frame to be able to do baby jumbo for FCoE */
2556 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2557 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2558 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2559
2560#endif /* IXGBE_FCOE */
021230d4 2561 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2562 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2563 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2564 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2565
2566 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2567 }
2568
2569 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2570 j = adapter->tx_ring[i].reg_idx;
2571 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2572 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2573 txdctl |= (8 << 16);
e8e26350
PW		 2574 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2575 }
2576
2577 if (hw->mac.type == ixgbe_mac_82599EB) {
2578 /* DMATXCTL.EN must be set after all Tx queue config is done */
2579 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2580 dmatxctl |= IXGBE_DMATXCTL_TE;
2581 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2582 }
2583 for (i = 0; i < adapter->num_tx_queues; i++) {
2584 j = adapter->tx_ring[i].reg_idx;
2585 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2586 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2587 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2588 }
2589
e8e26350 2590 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2591 j = adapter->rx_ring[i].reg_idx;
2592 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2593 /* enable PTHRESH=32 descriptors (half the internal cache)
2594 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2595 * this also removes a pesky rx_no_buffer_count increment */
2596 rxdctl |= 0x0020;
9a799d71 2597 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2598 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2599 if (hw->mac.type == ixgbe_mac_82599EB)
2600 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2601 }
2602 /* enable all receives */
2603 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2604 if (hw->mac.type == ixgbe_mac_82598EB)
2605 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2606 else
2607 rxdctl |= IXGBE_RXCTRL_RXEN;
2608 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2609
2610 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2611 ixgbe_configure_msix(adapter);
2612 else
2613 ixgbe_configure_msi_and_legacy(adapter);
2614
2615 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2616 ixgbe_napi_enable_all(adapter);
2617
2618 /* clear any pending interrupts, may auto mask */
2619 IXGBE_READ_REG(hw, IXGBE_EICR);
2620
9a799d71
AK		 2621 ixgbe_irq_enable(adapter);
2622
bf069c97
DS		 2623 /*
2624 * If this adapter has a fan, check to see if we had a failure
2625 * before we enabled the interrupt.
2626 */
2627 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2628 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2629 if (esdp & IXGBE_ESDP_SDP1)
2630 DPRINTK(DRV, CRIT,
2631 "Fan has stopped, replace the adapter\n");
2632 }
2633
e8e26350
PW		 2634 /*
2635 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2636 * arrived before interrupts were enabled. We need to kick off
2637 * the SFP+ module setup first, then try to bring up link.
2638 * If we're not hot-pluggable SFP+, we just need to configure link
2639 * and bring it up.
2640 */
2641 err = hw->phy.ops.identify(hw);
2642 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2643 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2644 ixgbe_down(adapter);
2645 return err;
2646 }
2647
2648 if (ixgbe_is_sfp(hw)) {
2649 ixgbe_sfp_link_config(adapter);
2650 } else {
2651 err = ixgbe_non_sfp_link_config(hw);
2652 if (err)
2653 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2654 }
0ecc061d 2655
1da100bb
PWJ		 2656 /* enable transmits */
2657 netif_tx_start_all_queues(netdev);
2658
9a799d71
AK		 2659 /* bring the link up in the watchdog, this could race with our first
2660 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2661 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2662 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2663 mod_timer(&adapter->watchdog_timer, jiffies);
2664 return 0;
2665}
2666
d4f80882
AV		 2667void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2668{
2669 WARN_ON(in_interrupt());
2670 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2671 msleep(1);
2672 ixgbe_down(adapter);
2673 ixgbe_up(adapter);
2674 clear_bit(__IXGBE_RESETTING, &adapter->state);
2675}
2676
9a799d71
AK		 2677int ixgbe_up(struct ixgbe_adapter *adapter)
2678{
2679 /* hardware has been reset, we need to reload some things */
2680 ixgbe_configure(adapter);
2681
2682 return ixgbe_up_complete(adapter);
2683}
2684
2685void ixgbe_reset(struct ixgbe_adapter *adapter)
2686{
c44ade9e 2687 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 2688 int err;
2689
2690 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 2691 switch (err) {
2692 case 0:
2693 case IXGBE_ERR_SFP_NOT_PRESENT:
2694 break;
2695 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2696 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2697 break;
2698 default:
2699 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2700 }
9a799d71
AK		 2701
2702 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2703 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2704}
2705
9a799d71
AK		 2706/**
2707 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2708 * @adapter: board private structure
2709 * @rx_ring: ring to free buffers from
2710 **/
2711static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2712 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2713{
2714 struct pci_dev *pdev = adapter->pdev;
2715 unsigned long size;
2716 unsigned int i;
2717
2718 /* Free all the Rx ring sk_buffs */
2719
2720 for (i = 0; i < rx_ring->count; i++) {
2721 struct ixgbe_rx_buffer *rx_buffer_info;
2722
2723 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2724 if (rx_buffer_info->dma) {
2725 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2726 rx_ring->rx_buf_len,
2727 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2728 rx_buffer_info->dma = 0;
2729 }
2730 if (rx_buffer_info->skb) {
f8212f97 2731 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2732 rx_buffer_info->skb = NULL;
f8212f97
AD		 2733 do {
2734 struct sk_buff *this = skb;
2735 skb = skb->prev;
2736 dev_kfree_skb(this);
2737 } while (skb);
9a799d71
AK		 2738 }
2739 if (!rx_buffer_info->page)
2740 continue;
762f4c57
JB		 2741 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2742 PCI_DMA_FROMDEVICE);
9a799d71 2743 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2744 put_page(rx_buffer_info->page);
2745 rx_buffer_info->page = NULL;
762f4c57 2746 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2747 }
2748
2749 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2750 memset(rx_ring->rx_buffer_info, 0, size);
2751
2752 /* Zero out the descriptor ring */
2753 memset(rx_ring->desc, 0, rx_ring->size);
2754
2755 rx_ring->next_to_clean = 0;
2756 rx_ring->next_to_use = 0;
2757
9891ca7c
JB		 2758 if (rx_ring->head)
2759 writel(0, adapter->hw.hw_addr + rx_ring->head);
2760 if (rx_ring->tail)
2761 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2762}
2763
2764/**
2765 * ixgbe_clean_tx_ring - Free Tx Buffers
2766 * @adapter: board private structure
2767 * @tx_ring: ring to be cleaned
2768 **/
2769static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2770 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2771{
2772 struct ixgbe_tx_buffer *tx_buffer_info;
2773 unsigned long size;
2774 unsigned int i;
2775
2776 /* Free all the Tx ring sk_buffs */
2777
2778 for (i = 0; i < tx_ring->count; i++) {
2779 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2780 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2781 }
2782
2783 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2784 memset(tx_ring->tx_buffer_info, 0, size);
2785
2786 /* Zero out the descriptor ring */
2787 memset(tx_ring->desc, 0, tx_ring->size);
2788
2789 tx_ring->next_to_use = 0;
2790 tx_ring->next_to_clean = 0;
2791
9891ca7c
JB		 2792 if (tx_ring->head)
2793 writel(0, adapter->hw.hw_addr + tx_ring->head);
2794 if (tx_ring->tail)
2795 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2796}
2797
2798/**
021230d4 2799 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2800 * @adapter: board private structure
2801 **/
021230d4 2802static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2803{
2804 int i;
2805
021230d4
AV		 2806 for (i = 0; i < adapter->num_rx_queues; i++)
2807 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2808}
2809
2810/**
021230d4 2811 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2812 * @adapter: board private structure
2813 **/
021230d4 2814static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2815{
2816 int i;
2817
021230d4
AV		 2818 for (i = 0; i < adapter->num_tx_queues; i++)
2819 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2820}
2821
2822void ixgbe_down(struct ixgbe_adapter *adapter)
2823{
2824 struct net_device *netdev = adapter->netdev;
7f821875 2825 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2826 u32 rxctrl;
7f821875
JB		 2827 u32 txdctl;
2828 int i, j;
9a799d71
AK		 2829
2830 /* signal that we are down to the interrupt handler */
2831 set_bit(__IXGBE_DOWN, &adapter->state);
2832
2833 /* disable receives */
7f821875
JB		 2834 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2835 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2836
2837 netif_tx_disable(netdev);
2838
7f821875 2839 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2840 msleep(10);
2841
7f821875
JB		 2842 netif_tx_stop_all_queues(netdev);
2843
9a799d71
AK		 2844 ixgbe_irq_disable(adapter);
2845
021230d4 2846 ixgbe_napi_disable_all(adapter);
7f821875 2847
9a799d71 2848 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2849 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2850
7f821875
JB		 2851 /* disable transmits in the hardware now that interrupts are off */
2852 for (i = 0; i < adapter->num_tx_queues; i++) {
2853 j = adapter->tx_ring[i].reg_idx;
2854 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2855 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2856 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2857 }
88512539
PW		 2858 /* Disable the Tx DMA engine on 82599 */
2859 if (hw->mac.type == ixgbe_mac_82599EB)
2860 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2861 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2862 ~IXGBE_DMATXCTL_TE));
7f821875 2863
9a799d71 2864 netif_carrier_off(netdev);
9a799d71 2865
6f4a0e45
PL		 2866 if (!pci_channel_offline(adapter->pdev))
2867 ixgbe_reset(adapter);
9a799d71
AK		 2868 ixgbe_clean_all_tx_rings(adapter);
2869 ixgbe_clean_all_rx_rings(adapter);
2870
5dd2d332 2871#ifdef CONFIG_IXGBE_DCA
96b0e0f6 2872 /* since we reset the hardware DCA settings were cleared */
e35ec126 2873 ixgbe_setup_dca(adapter);
96b0e0f6 2874#endif
9a799d71
AK		 2875}
2876
9a799d71 2877/**
021230d4
AV		 2878 * ixgbe_poll - NAPI Rx polling callback
2879 * @napi: structure for representing this polling device
2880 * @budget: how many packets driver is allowed to clean
2881 *
2882 * This function is used for legacy and MSI, NAPI mode
9a799d71 2883 **/
021230d4 2884static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2885{
9a1a69ad
JB		 2886 struct ixgbe_q_vector *q_vector =
2887 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2888 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2889 int tx_clean_complete, work_done = 0;
9a799d71 2890
5dd2d332 2891#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2892 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2893 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2894 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2895 }
2896#endif
2897
fe49f04a 2898 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
78b6f4ce 2899 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2900
9a1a69ad 2901 if (!tx_clean_complete)
d2c7ddd6
DM		 2902 work_done = budget;
2903
53e52c72
DM		 2904 /* If budget not fully consumed, exit the polling mode */
2905 if (work_done < budget) {
288379f0 2906 napi_complete(napi);
509ee935 2907 if (adapter->itr_setting & 1)
f494e8fa 2908 ixgbe_set_itr(adapter);
d4f80882 2909 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 2910 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 2911 }
9a799d71
AK		 2912 return work_done;
2913}
2914
2915/**
2916 * ixgbe_tx_timeout - Respond to a Tx Hang
2917 * @netdev: network interface device structure
2918 **/
2919static void ixgbe_tx_timeout(struct net_device *netdev)
2920{
2921 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2922
2923 /* Do the reset outside of interrupt context */
2924 schedule_work(&adapter->reset_task);
2925}
2926
2927static void ixgbe_reset_task(struct work_struct *work)
2928{
2929 struct ixgbe_adapter *adapter;
2930 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2931
2f90b865
AD		 2932 /* If we're already down or resetting, just bail */
2933 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2934 test_bit(__IXGBE_RESETTING, &adapter->state))
2935 return;
2936
9a799d71
AK		 2937 adapter->tx_timeout_count++;
2938
d4f80882 2939 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2940}
2941
bc97114d
PWJ		 2942#ifdef CONFIG_IXGBE_DCB
2943static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 2944{
bc97114d 2945 bool ret = false;
0cefafad 2946 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 2947
0cefafad
JB		 2948 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2949 return ret;
2950
2951 f->mask = 0x7 << 3;
2952 adapter->num_rx_queues = f->indices;
2953 adapter->num_tx_queues = f->indices;
2954 ret = true;
2f90b865 2955
bc97114d
PWJ		 2956 return ret;
2957}
2958#endif
2959
4df10466
JB		 2960/**
2961 * ixgbe_set_rss_queues: Allocate queues for RSS
2962 * @adapter: board private structure to initialize
2963 *
2964 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
2965 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2966 *
2967 **/
bc97114d
PWJ		 2968static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2969{
2970 bool ret = false;
0cefafad 2971 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 2972
2973 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 2974 f->mask = 0xF;
2975 adapter->num_rx_queues = f->indices;
2976 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 2977 ret = true;
2978 } else {
bc97114d 2979 ret = false;
b9804972
JB		 2980 }
2981
bc97114d
PWJ		 2982 return ret;
2983}
2984
0331a832
YZ		 2985#ifdef IXGBE_FCOE
2986/**
2987 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
2988 * @adapter: board private structure to initialize
2989 *
2990 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
2991 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
2992 * rx queues out of the max number of rx queues, instead, it is used as the
2993 * index of the first rx queue used by FCoE.
2994 *
2995 **/
2996static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
2997{
2998 bool ret = false;
2999 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3000
3001 f->indices = min((int)num_online_cpus(), f->indices);
3002 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3003#ifdef CONFIG_IXGBE_DCB
3004 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3005 DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
3006 ixgbe_set_dcb_queues(adapter);
3007 }
3008#endif
3009 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3010 DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
3011 ixgbe_set_rss_queues(adapter);
3012 }
3013 /* adding FCoE rx rings to the end */
3014 f->mask = adapter->num_rx_queues;
3015 adapter->num_rx_queues += f->indices;
3016 if (adapter->num_tx_queues == 0)
3017 adapter->num_tx_queues = f->indices;
3018
3019 ret = true;
3020 }
3021
3022 return ret;
3023}
3024
3025#endif /* IXGBE_FCOE */
4df10466
JB		 3026/*
3027 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3028 * @adapter: board private structure to initialize
3029 *
3030 * This is the top level queue allocation routine. The order here is very
3031 * important, starting with the "most" number of features turned on at once,
3032 * and ending with the smallest set of features. This way large combinations
3033 * can be allocated if they're turned on, and smaller combinations are the
3034 * fallthrough conditions.
3035 *
3036 **/
bc97114d
PWJ		 3037static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3038{
0331a832
YZ		 3039#ifdef IXGBE_FCOE
3040 if (ixgbe_set_fcoe_queues(adapter))
3041 goto done;
3042
3043#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3044#ifdef CONFIG_IXGBE_DCB
3045 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3046 goto done;
bc97114d
PWJ		 3047
3048#endif
3049 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3050 goto done;
3051
3052 /* fallback to base case */
3053 adapter->num_rx_queues = 1;
3054 adapter->num_tx_queues = 1;
3055
3056done:
3057 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3058 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3059}
3060
021230d4 3061static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3062 int vectors)
021230d4
AV		 3063{
3064 int err, vector_threshold;
3065
3066 /* We'll want at least 3 (vector_threshold):
3067 * 1) TxQ[0] Cleanup
3068 * 2) RxQ[0] Cleanup
3069 * 3) Other (Link Status Change, etc.)
3070 * 4) TCP Timer (optional)
3071 */
3072 vector_threshold = MIN_MSIX_COUNT;
3073
3074 /* The more we get, the more we will assign to Tx/Rx Cleanup
3075 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3076 * Right now, we simply care about how many we'll get; we'll
3077 * set them up later while requesting irq's.
3078 */
3079 while (vectors >= vector_threshold) {
3080 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3081 vectors);
021230d4
AV		 3082 if (!err) /* Success in acquiring all requested vectors. */
3083 break;
3084 else if (err < 0)
3085 vectors = 0; /* Nasty failure, quit now */
3086 else /* err == number of vectors we should try again with */
3087 vectors = err;
3088 }
3089
3090 if (vectors < vector_threshold) {
3091 /* Can't allocate enough MSI-X interrupts? Oh well.
3092 * This just means we'll go with either a single MSI
3093 * vector or fall back to legacy interrupts.
3094 */
3095 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3096 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3097 kfree(adapter->msix_entries);
3098 adapter->msix_entries = NULL;
021230d4
AV		 3099 } else {
3100 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3101 /*
3102 * Adjust for only the vectors we'll use, which is minimum
3103 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3104 * vectors we were allocated.
3105 */
3106 adapter->num_msix_vectors = min(vectors,
3107 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3108 }
3109}
3110
021230d4 3111/**
bc97114d 3112 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3113 * @adapter: board private structure to initialize
3114 *
bc97114d
PWJ		 3115 * Cache the descriptor ring offsets for RSS to the assigned rings.
3116 *
021230d4 3117 **/
bc97114d 3118static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3119{
bc97114d
PWJ		 3120 int i;
3121 bool ret = false;
3122
3123 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3124 for (i = 0; i < adapter->num_rx_queues; i++)
3125 adapter->rx_ring[i].reg_idx = i;
3126 for (i = 0; i < adapter->num_tx_queues; i++)
3127 adapter->tx_ring[i].reg_idx = i;
3128 ret = true;
3129 } else {
3130 ret = false;
3131 }
3132
3133 return ret;
3134}
3135
3136#ifdef CONFIG_IXGBE_DCB
3137/**
3138 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3139 * @adapter: board private structure to initialize
3140 *
3141 * Cache the descriptor ring offsets for DCB to the assigned rings.
3142 *
3143 **/
3144static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3145{
3146 int i;
3147 bool ret = false;
3148 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3149
3150 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3151 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3152 /* the number of queues is assumed to be symmetric */
3153 for (i = 0; i < dcb_i; i++) {
3154 adapter->rx_ring[i].reg_idx = i << 3;
3155 adapter->tx_ring[i].reg_idx = i << 2;
3156 }
bc97114d 3157 ret = true;
e8e26350 3158 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3159 if (dcb_i == 8) {
3160 /*
3161 * Tx TC0 starts at: descriptor queue 0
3162 * Tx TC1 starts at: descriptor queue 32
3163 * Tx TC2 starts at: descriptor queue 64
3164 * Tx TC3 starts at: descriptor queue 80
3165 * Tx TC4 starts at: descriptor queue 96
3166 * Tx TC5 starts at: descriptor queue 104
3167 * Tx TC6 starts at: descriptor queue 112
3168 * Tx TC7 starts at: descriptor queue 120
3169 *
3170 * Rx TC0-TC7 are offset by 16 queues each
3171 */
3172 for (i = 0; i < 3; i++) {
3173 adapter->tx_ring[i].reg_idx = i << 5;
3174 adapter->rx_ring[i].reg_idx = i << 4;
3175 }
3176 for ( ; i < 5; i++) {
3177 adapter->tx_ring[i].reg_idx =
3178 ((i + 2) << 4);
3179 adapter->rx_ring[i].reg_idx = i << 4;
3180 }
3181 for ( ; i < dcb_i; i++) {
3182 adapter->tx_ring[i].reg_idx =
3183 ((i + 8) << 3);
3184 adapter->rx_ring[i].reg_idx = i << 4;
3185 }
3186
3187 ret = true;
3188 } else if (dcb_i == 4) {
3189 /*
3190 * Tx TC0 starts at: descriptor queue 0
3191 * Tx TC1 starts at: descriptor queue 64
3192 * Tx TC2 starts at: descriptor queue 96
3193 * Tx TC3 starts at: descriptor queue 112
3194 *
3195 * Rx TC0-TC3 are offset by 32 queues each
3196 */
3197 adapter->tx_ring[0].reg_idx = 0;
3198 adapter->tx_ring[1].reg_idx = 64;
3199 adapter->tx_ring[2].reg_idx = 96;
3200 adapter->tx_ring[3].reg_idx = 112;
3201 for (i = 0 ; i < dcb_i; i++)
3202 adapter->rx_ring[i].reg_idx = i << 5;
3203
3204 ret = true;
3205 } else {
3206 ret = false;
e8e26350 3207 }
bc97114d
PWJ		 3208 } else {
3209 ret = false;
021230d4 3210 }
bc97114d
PWJ		 3211 } else {
3212 ret = false;
021230d4 3213 }
bc97114d
PWJ		 3214
3215 return ret;
3216}
3217#endif
3218
0331a832
YZ		 3219#ifdef IXGBE_FCOE
3220/**
3221 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3222 * @adapter: board private structure to initialize
3223 *
3224 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3225 *
3226 */
3227static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3228{
3229 int i, fcoe_i = 0;
3230 bool ret = false;
3231 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3232
3233 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3234#ifdef CONFIG_IXGBE_DCB
3235 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3236 ixgbe_cache_ring_dcb(adapter);
3237 fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3238 }
3239#endif /* CONFIG_IXGBE_DCB */
3240 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3241 ixgbe_cache_ring_rss(adapter);
3242 fcoe_i = f->mask;
3243 }
3244 for (i = 0; i < f->indices; i++, fcoe_i++)
3245 adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3246 ret = true;
3247 }
3248 return ret;
3249}
3250
3251#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3252/**
3253 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3254 * @adapter: board private structure to initialize
3255 *
3256 * Once we know the feature-set enabled for the device, we'll cache
3257 * the register offset the descriptor ring is assigned to.
3258 *
3259 * Note, the order the various feature calls is important. It must start with
3260 * the "most" features enabled at the same time, then trickle down to the
3261 * least amount of features turned on at once.
3262 **/
3263static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3264{
3265 /* start with default case */
3266 adapter->rx_ring[0].reg_idx = 0;
3267 adapter->tx_ring[0].reg_idx = 0;
3268
0331a832
YZ		 3269#ifdef IXGBE_FCOE
3270 if (ixgbe_cache_ring_fcoe(adapter))
3271 return;
3272
3273#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3274#ifdef CONFIG_IXGBE_DCB
3275 if (ixgbe_cache_ring_dcb(adapter))
3276 return;
3277
3278#endif
3279 if (ixgbe_cache_ring_rss(adapter))
3280 return;
021230d4
AV		 3281}
3282
9a799d71
AK		 3283/**
3284 * ixgbe_alloc_queues - Allocate memory for all rings
3285 * @adapter: board private structure to initialize
3286 *
3287 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3288 * number of queues at compile-time. The polling_netdev array is
3289 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3290 **/
2f90b865 3291static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3292{
3293 int i;
3294
3295 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3296 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3297 if (!adapter->tx_ring)
021230d4 3298 goto err_tx_ring_allocation;
9a799d71
AK		 3299
3300 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3301 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3302 if (!adapter->rx_ring)
3303 goto err_rx_ring_allocation;
9a799d71 3304
021230d4 3305 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3306 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3307 adapter->tx_ring[i].queue_index = i;
3308 }
b9804972 3309
9a799d71 3310 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3311 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3312 adapter->rx_ring[i].queue_index = i;
3313 }
3314
3315 ixgbe_cache_ring_register(adapter);
3316
3317 return 0;
3318
3319err_rx_ring_allocation:
3320 kfree(adapter->tx_ring);
3321err_tx_ring_allocation:
3322 return -ENOMEM;
3323}
3324
3325/**
3326 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3327 * @adapter: board private structure to initialize
3328 *
3329 * Attempt to configure the interrupts using the best available
3330 * capabilities of the hardware and the kernel.
3331 **/
feea6a57 3332static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3333{
8be0e467 3334 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3335 int err = 0;
3336 int vector, v_budget;
3337
3338 /*
3339 * It's easy to be greedy for MSI-X vectors, but it really
3340 * doesn't do us much good if we have a lot more vectors
3341 * than CPU's. So let's be conservative and only ask for
3342 * (roughly) twice the number of vectors as there are CPU's.
3343 */
3344 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 3345 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 3346
3347 /*
3348 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3349 * hw.mac->max_msix_vectors vectors. With features
3350 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3351 * descriptor queues supported by our device. Thus, we cap it off in
3352 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3353 */
8be0e467 3354 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3355
3356 /* A failure in MSI-X entry allocation isn't fatal, but it does
3357 * mean we disable MSI-X capabilities of the adapter. */
3358 adapter->msix_entries = kcalloc(v_budget,
b4617240 3359 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3360 if (adapter->msix_entries) {
3361 for (vector = 0; vector < v_budget; vector++)
3362 adapter->msix_entries[vector].entry = vector;
021230d4 3363
7a921c93 3364 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3365
7a921c93
AD		 3366 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3367 goto out;
3368 }
021230d4 3369
7a921c93
AD		 3370 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3371 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3372 ixgbe_set_num_queues(adapter);
021230d4 3373
021230d4
AV		 3374 err = pci_enable_msi(adapter->pdev);
3375 if (!err) {
3376 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3377 } else {
3378 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3379 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3380 /* reset err */
3381 err = 0;
3382 }
3383
3384out:
021230d4
AV		 3385 return err;
3386}
3387
7a921c93
AD		 3388/**
3389 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3390 * @adapter: board private structure to initialize
3391 *
3392 * We allocate one q_vector per queue interrupt. If allocation fails we
3393 * return -ENOMEM.
3394 **/
3395static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3396{
3397 int q_idx, num_q_vectors;
3398 struct ixgbe_q_vector *q_vector;
3399 int napi_vectors;
3400 int (*poll)(struct napi_struct *, int);
3401
3402 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3403 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3404 napi_vectors = adapter->num_rx_queues;
91281fd3 3405 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 3406 } else {
3407 num_q_vectors = 1;
3408 napi_vectors = 1;
3409 poll = &ixgbe_poll;
3410 }
3411
3412 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3413 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3414 if (!q_vector)
3415 goto err_out;
3416 q_vector->adapter = adapter;
7a921c93 3417 q_vector->eitr = adapter->eitr_param;
fe49f04a 3418 q_vector->v_idx = q_idx;
91281fd3 3419 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 3420 adapter->q_vector[q_idx] = q_vector;
3421 }
3422
3423 return 0;
3424
3425err_out:
3426 while (q_idx) {
3427 q_idx--;
3428 q_vector = adapter->q_vector[q_idx];
3429 netif_napi_del(&q_vector->napi);
3430 kfree(q_vector);
3431 adapter->q_vector[q_idx] = NULL;
3432 }
3433 return -ENOMEM;
3434}
3435
3436/**
3437 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3438 * @adapter: board private structure to initialize
3439 *
3440 * This function frees the memory allocated to the q_vectors. In addition if
3441 * NAPI is enabled it will delete any references to the NAPI struct prior
3442 * to freeing the q_vector.
3443 **/
3444static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3445{
3446 int q_idx, num_q_vectors;
7a921c93 3447
91281fd3 3448 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 3449 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 3450 else
7a921c93 3451 num_q_vectors = 1;
7a921c93
AD		 3452
3453 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3454 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 3455 adapter->q_vector[q_idx] = NULL;
91281fd3 3456 netif_napi_del(&q_vector->napi);
7a921c93
AD		 3457 kfree(q_vector);
3458 }
3459}
3460
2f90b865 3461void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3462{
3463 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3464 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3465 pci_disable_msix(adapter->pdev);
3466 kfree(adapter->msix_entries);
3467 adapter->msix_entries = NULL;
3468 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3469 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3470 pci_disable_msi(adapter->pdev);
3471 }
3472 return;
3473}
3474
3475/**
3476 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3477 * @adapter: board private structure to initialize
3478 *
3479 * We determine which interrupt scheme to use based on...
3480 * - Kernel support (MSI, MSI-X)
3481 * - which can be user-defined (via MODULE_PARAM)
3482 * - Hardware queue count (num_*_queues)
3483 * - defined by miscellaneous hardware support/features (RSS, etc.)
3484 **/
2f90b865 3485int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3486{
3487 int err;
3488
3489 /* Number of supported queues */
3490 ixgbe_set_num_queues(adapter);
3491
021230d4
AV		 3492 err = ixgbe_set_interrupt_capability(adapter);
3493 if (err) {
3494 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3495 goto err_set_interrupt;
9a799d71
AK		 3496 }
3497
7a921c93
AD		 3498 err = ixgbe_alloc_q_vectors(adapter);
3499 if (err) {
3500 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3501 "vectors\n");
3502 goto err_alloc_q_vectors;
3503 }
3504
3505 err = ixgbe_alloc_queues(adapter);
3506 if (err) {
3507 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3508 goto err_alloc_queues;
3509 }
3510
021230d4 3511 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3512 "Tx Queue count = %u\n",
3513 (adapter->num_rx_queues > 1) ? "Enabled" :
3514 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3515
3516 set_bit(__IXGBE_DOWN, &adapter->state);
3517
9a799d71 3518 return 0;
021230d4 3519
7a921c93
AD		 3520err_alloc_queues:
3521 ixgbe_free_q_vectors(adapter);
3522err_alloc_q_vectors:
3523 ixgbe_reset_interrupt_capability(adapter);
021230d4 3524err_set_interrupt:
7a921c93
AD		 3525 return err;
3526}
3527
3528/**
3529 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3530 * @adapter: board private structure to clear interrupt scheme on
3531 *
3532 * We go through and clear interrupt specific resources and reset the structure
3533 * to pre-load conditions
3534 **/
3535void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3536{
021230d4
AV		 3537 kfree(adapter->tx_ring);
3538 kfree(adapter->rx_ring);
7a921c93
AD		 3539 adapter->tx_ring = NULL;
3540 adapter->rx_ring = NULL;
3541
3542 ixgbe_free_q_vectors(adapter);
3543 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3544}
3545
c4900be0
DS		 3546/**
3547 * ixgbe_sfp_timer - worker thread to find a missing module
3548 * @data: pointer to our adapter struct
3549 **/
3550static void ixgbe_sfp_timer(unsigned long data)
3551{
3552 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3553
4df10466
JB		 3554 /*
3555 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3556 * delays that sfp+ detection requires
3557 */
3558 schedule_work(&adapter->sfp_task);
3559}
3560
3561/**
3562 * ixgbe_sfp_task - worker thread to find a missing module
3563 * @work: pointer to work_struct containing our data
3564 **/
3565static void ixgbe_sfp_task(struct work_struct *work)
3566{
3567 struct ixgbe_adapter *adapter = container_of(work,
3568 struct ixgbe_adapter,
3569 sfp_task);
3570 struct ixgbe_hw *hw = &adapter->hw;
3571
3572 if ((hw->phy.type == ixgbe_phy_nl) &&
3573 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3574 s32 ret = hw->phy.ops.identify_sfp(hw);
3575 if (ret)
3576 goto reschedule;
3577 ret = hw->phy.ops.reset(hw);
3578 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3579 DPRINTK(PROBE, ERR, "failed to initialize because an "
3580 "unsupported SFP+ module type was detected.\n"
3581 "Reload the driver after installing a "
3582 "supported module.\n");
3583 unregister_netdev(adapter->netdev);
3584 } else {
3585 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3586 hw->phy.sfp_type);
3587 }
3588 /* don't need this routine any more */
3589 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3590 }
3591 return;
3592reschedule:
3593 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3594 mod_timer(&adapter->sfp_timer,
3595 round_jiffies(jiffies + (2 * HZ)));
3596}
3597
9a799d71
AK		 3598/**
3599 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3600 * @adapter: board private structure to initialize
3601 *
3602 * ixgbe_sw_init initializes the Adapter private data structure.
3603 * Fields are initialized based on PCI device information and
3604 * OS network device settings (MTU size).
3605 **/
3606static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3607{
3608 struct ixgbe_hw *hw = &adapter->hw;
3609 struct pci_dev *pdev = adapter->pdev;
021230d4 3610 unsigned int rss;
7a6b6f51 3611#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3612 int j;
3613 struct tc_configuration *tc;
3614#endif
021230d4 3615
c44ade9e
JB		 3616 /* PCI config space info */
3617
3618 hw->vendor_id = pdev->vendor;
3619 hw->device_id = pdev->device;
3620 hw->revision_id = pdev->revision;
3621 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3622 hw->subsystem_device_id = pdev->subsystem_device;
3623
021230d4
AV		 3624 /* Set capability flags */
3625 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3626 adapter->ring_feature[RING_F_RSS].indices = rss;
3627 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3628 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 3629 if (hw->mac.type == ixgbe_mac_82598EB) {
3630 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3631 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 3632 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 3633 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3634 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
f8212f97
AD		 3635 adapter->flags |= IXGBE_FLAG_RSC_CAPABLE;
3636 adapter->flags |= IXGBE_FLAG_RSC_ENABLED;
eacd73f7
YZ		 3637#ifdef IXGBE_FCOE
3638 adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
0331a832 3639 adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE;
eacd73f7 3640#endif /* IXGBE_FCOE */
f8212f97 3641 }
2f90b865 3642
7a6b6f51 3643#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3644 /* Configure DCB traffic classes */
3645 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3646 tc = &adapter->dcb_cfg.tc_config[j];
3647 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3648 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3649 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3650 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3651 tc->dcb_pfc = pfc_disabled;
3652 }
3653 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3654 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3655 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 3656 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 3657 adapter->dcb_cfg.round_robin_enable = false;
3658 adapter->dcb_set_bitmap = 0x00;
3659 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3660 adapter->ring_feature[RING_F_DCB].indices);
3661
3662#endif
9a799d71
AK		 3663
3664 /* default flow control settings */
cd7664f6 3665 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3666 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 3667#ifdef CONFIG_DCB
3668 adapter->last_lfc_mode = hw->fc.current_mode;
3669#endif
2b9ade93
JB		 3670 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3671 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3672 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3673 hw->fc.send_xon = true;
71fd570b 3674 hw->fc.disable_fc_autoneg = false;
9a799d71 3675
30efa5a3
JB		 3676 /* enable itr by default in dynamic mode */
3677 adapter->itr_setting = 1;
3678 adapter->eitr_param = 20000;
3679
3680 /* set defaults for eitr in MegaBytes */
3681 adapter->eitr_low = 10;
3682 adapter->eitr_high = 20;
3683
3684 /* set default ring sizes */
3685 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3686 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3687
9a799d71 3688 /* initialize eeprom parameters */
c44ade9e 3689 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3690 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3691 return -EIO;
3692 }
3693
021230d4 3694 /* enable rx csum by default */
9a799d71
AK		 3695 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3696
9a799d71
AK		 3697 set_bit(__IXGBE_DOWN, &adapter->state);
3698
3699 return 0;
3700}
3701
3702/**
3703 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3704 * @adapter: board private structure
3a581073 3705 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3706 *
3707 * Return 0 on success, negative on failure
3708 **/
3709int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3710 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3711{
3712 struct pci_dev *pdev = adapter->pdev;
3713 int size;
3714
3a581073
JB		 3715 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3716 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3717 if (!tx_ring->tx_buffer_info)
3718 goto err;
3a581073 3719 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3720
3721 /* round up to nearest 4K */
12207e49 3722 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3723 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3724
3a581073
JB		 3725 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3726 &tx_ring->dma);
e01c31a5
JB		 3727 if (!tx_ring->desc)
3728 goto err;
9a799d71 3729
3a581073
JB		 3730 tx_ring->next_to_use = 0;
3731 tx_ring->next_to_clean = 0;
3732 tx_ring->work_limit = tx_ring->count;
9a799d71 3733 return 0;
e01c31a5
JB		 3734
3735err:
3736 vfree(tx_ring->tx_buffer_info);
3737 tx_ring->tx_buffer_info = NULL;
3738 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3739 "descriptor ring\n");
3740 return -ENOMEM;
9a799d71
AK		 3741}
3742
69888674
AD		 3743/**
3744 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3745 * @adapter: board private structure
3746 *
3747 * If this function returns with an error, then it's possible one or
3748 * more of the rings is populated (while the rest are not). It is the
3749 * callers duty to clean those orphaned rings.
3750 *
3751 * Return 0 on success, negative on failure
3752 **/
3753static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3754{
3755 int i, err = 0;
3756
3757 for (i = 0; i < adapter->num_tx_queues; i++) {
3758 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3759 if (!err)
3760 continue;
3761 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3762 break;
3763 }
3764
3765 return err;
3766}
3767
9a799d71
AK		 3768/**
3769 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3770 * @adapter: board private structure
3a581073 3771 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3772 *
3773 * Returns 0 on success, negative on failure
3774 **/
3775int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3776 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3777{
3778 struct pci_dev *pdev = adapter->pdev;
021230d4 3779 int size;
9a799d71 3780
3a581073
JB		 3781 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3782 rx_ring->rx_buffer_info = vmalloc(size);
3783 if (!rx_ring->rx_buffer_info) {
9a799d71 3784 DPRINTK(PROBE, ERR,
b4617240 3785 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3786 goto alloc_failed;
9a799d71 3787 }
3a581073 3788 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3789
9a799d71 3790 /* Round up to nearest 4K */
3a581073
JB		 3791 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3792 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3793
3a581073 3794 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3795
3a581073 3796 if (!rx_ring->desc) {
9a799d71 3797 DPRINTK(PROBE, ERR,
b4617240 3798 "Memory allocation failed for the rx desc ring\n");
3a581073 3799 vfree(rx_ring->rx_buffer_info);
177db6ff 3800 goto alloc_failed;
9a799d71
AK		 3801 }
3802
3a581073
JB		 3803 rx_ring->next_to_clean = 0;
3804 rx_ring->next_to_use = 0;
9a799d71
AK		 3805
3806 return 0;
177db6ff
MC		 3807
3808alloc_failed:
177db6ff 3809 return -ENOMEM;
9a799d71
AK		 3810}
3811
69888674
AD		 3812/**
3813 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3814 * @adapter: board private structure
3815 *
3816 * If this function returns with an error, then it's possible one or
3817 * more of the rings is populated (while the rest are not). It is the
3818 * callers duty to clean those orphaned rings.
3819 *
3820 * Return 0 on success, negative on failure
3821 **/
3822
3823static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3824{
3825 int i, err = 0;
3826
3827 for (i = 0; i < adapter->num_rx_queues; i++) {
3828 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3829 if (!err)
3830 continue;
3831 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3832 break;
3833 }
3834
3835 return err;
3836}
3837
9a799d71
AK		 3838/**
3839 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3840 * @adapter: board private structure
3841 * @tx_ring: Tx descriptor ring for a specific queue
3842 *
3843 * Free all transmit software resources
3844 **/
c431f97e
JB		 3845void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3846 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3847{
3848 struct pci_dev *pdev = adapter->pdev;
3849
3850 ixgbe_clean_tx_ring(adapter, tx_ring);
3851
3852 vfree(tx_ring->tx_buffer_info);
3853 tx_ring->tx_buffer_info = NULL;
3854
3855 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3856
3857 tx_ring->desc = NULL;
3858}
3859
3860/**
3861 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3862 * @adapter: board private structure
3863 *
3864 * Free all transmit software resources
3865 **/
3866static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3867{
3868 int i;
3869
3870 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 3871 if (adapter->tx_ring[i].desc)
3872 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 3873}
3874
3875/**
b4617240 3876 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 3877 * @adapter: board private structure
3878 * @rx_ring: ring to clean the resources from
3879 *
3880 * Free all receive software resources
3881 **/
c431f97e
JB		 3882void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3883 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3884{
3885 struct pci_dev *pdev = adapter->pdev;
3886
3887 ixgbe_clean_rx_ring(adapter, rx_ring);
3888
3889 vfree(rx_ring->rx_buffer_info);
3890 rx_ring->rx_buffer_info = NULL;
3891
3892 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3893
3894 rx_ring->desc = NULL;
3895}
3896
3897/**
3898 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3899 * @adapter: board private structure
3900 *
3901 * Free all receive software resources
3902 **/
3903static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3904{
3905 int i;
3906
3907 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 3908 if (adapter->rx_ring[i].desc)
3909 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 3910}
3911
9a799d71
AK		 3912/**
3913 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3914 * @netdev: network interface device structure
3915 * @new_mtu: new value for maximum frame size
3916 *
3917 * Returns 0 on success, negative on failure
3918 **/
3919static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3920{
3921 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3922 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3923
42c783c5
JB		 3924 /* MTU < 68 is an error and causes problems on some kernels */
3925 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 3926 return -EINVAL;
3927
021230d4 3928 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 3929 netdev->mtu, new_mtu);
021230d4 3930 /* must set new MTU before calling down or up */
9a799d71
AK		 3931 netdev->mtu = new_mtu;
3932
d4f80882
AV		 3933 if (netif_running(netdev))
3934 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3935
3936 return 0;
3937}
3938
3939/**
3940 * ixgbe_open - Called when a network interface is made active
3941 * @netdev: network interface device structure
3942 *
3943 * Returns 0 on success, negative value on failure
3944 *
3945 * The open entry point is called when a network interface is made
3946 * active by the system (IFF_UP). At this point all resources needed
3947 * for transmit and receive operations are allocated, the interrupt
3948 * handler is registered with the OS, the watchdog timer is started,
3949 * and the stack is notified that the interface is ready.
3950 **/
3951static int ixgbe_open(struct net_device *netdev)
3952{
3953 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3954 int err;
4bebfaa5
AK		 3955
3956 /* disallow open during test */
3957 if (test_bit(__IXGBE_TESTING, &adapter->state))
3958 return -EBUSY;
9a799d71 3959
54386467
JB		 3960 netif_carrier_off(netdev);
3961
9a799d71
AK		 3962 /* allocate transmit descriptors */
3963 err = ixgbe_setup_all_tx_resources(adapter);
3964 if (err)
3965 goto err_setup_tx;
3966
9a799d71
AK		 3967 /* allocate receive descriptors */
3968 err = ixgbe_setup_all_rx_resources(adapter);
3969 if (err)
3970 goto err_setup_rx;
3971
3972 ixgbe_configure(adapter);
3973
021230d4 3974 err = ixgbe_request_irq(adapter);
9a799d71
AK		 3975 if (err)
3976 goto err_req_irq;
3977
9a799d71
AK		 3978 err = ixgbe_up_complete(adapter);
3979 if (err)
3980 goto err_up;
3981
d55b53ff
JK		 3982 netif_tx_start_all_queues(netdev);
3983
9a799d71
AK		 3984 return 0;
3985
3986err_up:
5eba3699 3987 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3988 ixgbe_free_irq(adapter);
3989err_req_irq:
9a799d71 3990err_setup_rx:
a20a1199 3991 ixgbe_free_all_rx_resources(adapter);
9a799d71 3992err_setup_tx:
a20a1199 3993 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 3994 ixgbe_reset(adapter);
3995
3996 return err;
3997}
3998
3999/**
4000 * ixgbe_close - Disables a network interface
4001 * @netdev: network interface device structure
4002 *
4003 * Returns 0, this is not allowed to fail
4004 *
4005 * The close entry point is called when an interface is de-activated
4006 * by the OS. The hardware is still under the drivers control, but
4007 * needs to be disabled. A global MAC reset is issued to stop the
4008 * hardware, and all transmit and receive resources are freed.
4009 **/
4010static int ixgbe_close(struct net_device *netdev)
4011{
4012 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4013
4014 ixgbe_down(adapter);
4015 ixgbe_free_irq(adapter);
4016
4017 ixgbe_free_all_tx_resources(adapter);
4018 ixgbe_free_all_rx_resources(adapter);
4019
5eba3699 4020 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4021
4022 return 0;
4023}
4024
b3c8b4ba
AD		 4025#ifdef CONFIG_PM
4026static int ixgbe_resume(struct pci_dev *pdev)
4027{
4028 struct net_device *netdev = pci_get_drvdata(pdev);
4029 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4030 u32 err;
4031
4032 pci_set_power_state(pdev, PCI_D0);
4033 pci_restore_state(pdev);
9ce77666 4034
4035 err = pci_enable_device_mem(pdev);
b3c8b4ba 4036 if (err) {
69888674 4037 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4038 "suspend\n");
4039 return err;
4040 }
4041 pci_set_master(pdev);
4042
dd4d8ca6 4043 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4044
4045 err = ixgbe_init_interrupt_scheme(adapter);
4046 if (err) {
4047 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4048 "device\n");
4049 return err;
4050 }
4051
b3c8b4ba
AD		 4052 ixgbe_reset(adapter);
4053
495dce12
WJP		 4054 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4055
b3c8b4ba
AD		 4056 if (netif_running(netdev)) {
4057 err = ixgbe_open(adapter->netdev);
4058 if (err)
4059 return err;
4060 }
4061
4062 netif_device_attach(netdev);
4063
4064 return 0;
4065}
b3c8b4ba 4066#endif /* CONFIG_PM */
9d8d05ae
RW		 4067
4068static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4069{
4070 struct net_device *netdev = pci_get_drvdata(pdev);
4071 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4072 struct ixgbe_hw *hw = &adapter->hw;
4073 u32 ctrl, fctrl;
4074 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4075#ifdef CONFIG_PM
4076 int retval = 0;
4077#endif
4078
4079 netif_device_detach(netdev);
4080
4081 if (netif_running(netdev)) {
4082 ixgbe_down(adapter);
4083 ixgbe_free_irq(adapter);
4084 ixgbe_free_all_tx_resources(adapter);
4085 ixgbe_free_all_rx_resources(adapter);
4086 }
7a921c93 4087 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4088
4089#ifdef CONFIG_PM
4090 retval = pci_save_state(pdev);
4091 if (retval)
4092 return retval;
4df10466 4093
b3c8b4ba 4094#endif
e8e26350
PW		 4095 if (wufc) {
4096 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4097
e8e26350
PW		 4098 /* turn on all-multi mode if wake on multicast is enabled */
4099 if (wufc & IXGBE_WUFC_MC) {
4100 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4101 fctrl |= IXGBE_FCTRL_MPE;
4102 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4103 }
4104
4105 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4106 ctrl |= IXGBE_CTRL_GIO_DIS;
4107 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4108
4109 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4110 } else {
4111 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4112 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4113 }
4114
dd4d8ca6
DS		 4115 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4116 pci_wake_from_d3(pdev, true);
4117 else
4118 pci_wake_from_d3(pdev, false);
b3c8b4ba 4119
9d8d05ae
RW		 4120 *enable_wake = !!wufc;
4121
b3c8b4ba
AD		 4122 ixgbe_release_hw_control(adapter);
4123
4124 pci_disable_device(pdev);
4125
9d8d05ae
RW		 4126 return 0;
4127}
4128
4129#ifdef CONFIG_PM
4130static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4131{
4132 int retval;
4133 bool wake;
4134
4135 retval = __ixgbe_shutdown(pdev, &wake);
4136 if (retval)
4137 return retval;
4138
4139 if (wake) {
4140 pci_prepare_to_sleep(pdev);
4141 } else {
4142 pci_wake_from_d3(pdev, false);
4143 pci_set_power_state(pdev, PCI_D3hot);
4144 }
b3c8b4ba
AD		 4145
4146 return 0;
4147}
9d8d05ae 4148#endif /* CONFIG_PM */
b3c8b4ba
AD		 4149
4150static void ixgbe_shutdown(struct pci_dev *pdev)
4151{
9d8d05ae
RW		 4152 bool wake;
4153
4154 __ixgbe_shutdown(pdev, &wake);
4155
4156 if (system_state == SYSTEM_POWER_OFF) {
4157 pci_wake_from_d3(pdev, wake);
4158 pci_set_power_state(pdev, PCI_D3hot);
4159 }
b3c8b4ba
AD		 4160}
4161
9a799d71
AK		 4162/**
4163 * ixgbe_update_stats - Update the board statistics counters.
4164 * @adapter: board private structure
4165 **/
4166void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4167{
4168 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4169 u64 total_mpc = 0;
4170 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 4171
d51019a4 4172 if (hw->mac.type == ixgbe_mac_82599EB) {
f8212f97 4173 u64 rsc_count = 0;
d51019a4
PW		 4174 for (i = 0; i < 16; i++)
4175 adapter->hw_rx_no_dma_resources +=
4176 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
f8212f97
AD		 4177 for (i = 0; i < adapter->num_rx_queues; i++)
4178 rsc_count += adapter->rx_ring[i].rsc_count;
4179 adapter->rsc_count = rsc_count;
d51019a4
PW		 4180 }
4181
9a799d71 4182 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4183 for (i = 0; i < 8; i++) {
4184 /* for packet buffers not used, the register should read 0 */
4185 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4186 missed_rx += mpc;
4187 adapter->stats.mpc[i] += mpc;
4188 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4189 if (hw->mac.type == ixgbe_mac_82598EB)
4190 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4191 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4192 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4193 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4194 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4195 if (hw->mac.type == ixgbe_mac_82599EB) {
4196 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4197 IXGBE_PXONRXCNT(i));
4198 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4199 IXGBE_PXOFFRXCNT(i));
4200 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4201 } else {
4202 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4203 IXGBE_PXONRXC(i));
4204 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4205 IXGBE_PXOFFRXC(i));
4206 }
2f90b865
AD		 4207 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4208 IXGBE_PXONTXC(i));
2f90b865 4209 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4210 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4211 }
4212 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4213 /* work around hardware counting issue */
4214 adapter->stats.gprc -= missed_rx;
4215
4216 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 4217 if (hw->mac.type == ixgbe_mac_82599EB) {
4218 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4219 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4220 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4221 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4222 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4223 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4224 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4225 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
6d45522c
YZ		 4226#ifdef IXGBE_FCOE
4227 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4228 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4229 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4230 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4231 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4232 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4233#endif /* IXGBE_FCOE */
e8e26350
PW		 4234 } else {
4235 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4236 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4237 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4238 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4239 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4240 }
9a799d71
AK		 4241 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4242 adapter->stats.bprc += bprc;
4243 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4244 if (hw->mac.type == ixgbe_mac_82598EB)
4245 adapter->stats.mprc -= bprc;
9a799d71
AK		 4246 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4247 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4248 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4249 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4250 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4251 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4252 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4253 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4254 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4255 adapter->stats.lxontxc += lxon;
4256 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4257 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4258 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4259 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4260 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4261 /*
4262 * 82598 errata - tx of flow control packets is included in tx counters
4263 */
4264 xon_off_tot = lxon + lxoff;
4265 adapter->stats.gptc -= xon_off_tot;
4266 adapter->stats.mptc -= xon_off_tot;
4267 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4268 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4269 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4270 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4271 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4272 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4273 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4274 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4275 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4276 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4277 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4278 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4279 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4280
4281 /* Fill out the OS statistics structure */
9a799d71
AK		 4282 adapter->net_stats.multicast = adapter->stats.mprc;
4283
4284 /* Rx Errors */
4285 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 4286 adapter->stats.rlec;
9a799d71
AK		 4287 adapter->net_stats.rx_dropped = 0;
4288 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4289 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 4290 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4291}
4292
4293/**
4294 * ixgbe_watchdog - Timer Call-back
4295 * @data: pointer to adapter cast into an unsigned long
4296 **/
4297static void ixgbe_watchdog(unsigned long data)
4298{
4299 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 4300 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 4301 u64 eics = 0;
4302 int i;
cf8280ee 4303
fe49f04a
AD		 4304 /*
4305 * Do the watchdog outside of interrupt context due to the lovely
4306 * delays that some of the newer hardware requires
4307 */
22d5a71b 4308
fe49f04a
AD		 4309 if (test_bit(__IXGBE_DOWN, &adapter->state))
4310 goto watchdog_short_circuit;
22d5a71b 4311
fe49f04a
AD		 4312 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4313 /*
4314 * for legacy and MSI interrupts don't set any bits
4315 * that are enabled for EIAM, because this operation
4316 * would set *both* EIMS and EICS for any bit in EIAM
4317 */
4318 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4319 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4320 goto watchdog_reschedule;
4321 }
4322
4323 /* get one bit for every active tx/rx interrupt vector */
4324 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4325 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4326 if (qv->rxr_count || qv->txr_count)
4327 eics |= ((u64)1 << i);
cf8280ee 4328 }
9a799d71 4329
fe49f04a
AD		 4330 /* Cause software interrupt to ensure rx rings are cleaned */
4331 ixgbe_irq_rearm_queues(adapter, eics);
4332
4333watchdog_reschedule:
4334 /* Reset the timer */
4335 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4336
4337watchdog_short_circuit:
cf8280ee
JB		 4338 schedule_work(&adapter->watchdog_task);
4339}
4340
e8e26350
PW		 4341/**
4342 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4343 * @work: pointer to work_struct containing our data
4344 **/
4345static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4346{
4347 struct ixgbe_adapter *adapter = container_of(work,
4348 struct ixgbe_adapter,
4349 multispeed_fiber_task);
4350 struct ixgbe_hw *hw = &adapter->hw;
4351 u32 autoneg;
4352
4353 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4354 if (hw->mac.ops.get_link_capabilities)
4355 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4356 &hw->mac.autoneg);
4357 if (hw->mac.ops.setup_link_speed)
4358 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4359 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4360 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4361}
4362
4363/**
4364 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4365 * @work: pointer to work_struct containing our data
4366 **/
4367static void ixgbe_sfp_config_module_task(struct work_struct *work)
4368{
4369 struct ixgbe_adapter *adapter = container_of(work,
4370 struct ixgbe_adapter,
4371 sfp_config_module_task);
4372 struct ixgbe_hw *hw = &adapter->hw;
4373 u32 err;
4374
4375 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4376 err = hw->phy.ops.identify_sfp(hw);
4377 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4378 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
4379 ixgbe_down(adapter);
4380 return;
4381 }
4382 hw->mac.ops.setup_sfp(hw);
4383
8d1c3c07 4384 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4385 /* This will also work for DA Twinax connections */
4386 schedule_work(&adapter->multispeed_fiber_task);
4387 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4388}
4389
cf8280ee 4390/**
69888674
AD		 4391 * ixgbe_watchdog_task - worker thread to bring link up
4392 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4393 **/
4394static void ixgbe_watchdog_task(struct work_struct *work)
4395{
4396 struct ixgbe_adapter *adapter = container_of(work,
4397 struct ixgbe_adapter,
4398 watchdog_task);
4399 struct net_device *netdev = adapter->netdev;
4400 struct ixgbe_hw *hw = &adapter->hw;
4401 u32 link_speed = adapter->link_speed;
4402 bool link_up = adapter->link_up;
bc59fcda
NS		 4403 int i;
4404 struct ixgbe_ring *tx_ring;
4405 int some_tx_pending = 0;
cf8280ee
JB		 4406
4407 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4408
4409 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4410 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 4411 if (link_up) {
4412#ifdef CONFIG_DCB
4413 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4414 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 4415 hw->mac.ops.fc_enable(hw, i);
264857b8 4416 } else {
620fa036 4417 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4418 }
4419#else
620fa036 4420 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4421#endif
4422 }
4423
cf8280ee
JB		 4424 if (link_up ||
4425 time_after(jiffies, (adapter->link_check_timeout +
4426 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 4427 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 4428 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 4429 }
4430 adapter->link_up = link_up;
4431 adapter->link_speed = link_speed;
4432 }
9a799d71
AK		 4433
4434 if (link_up) {
4435 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4436 bool flow_rx, flow_tx;
4437
4438 if (hw->mac.type == ixgbe_mac_82599EB) {
4439 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4440 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4441 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4442 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4443 } else {
4444 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4445 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4446 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4447 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4448 }
4449
a46e534b
JK		 4450 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4451 "Flow Control: %s\n",
4452 netdev->name,
4453 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4454 "10 Gbps" :
4455 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4456 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4457 ((flow_rx && flow_tx) ? "RX/TX" :
4458 (flow_rx ? "RX" :
4459 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4460
4461 netif_carrier_on(netdev);
9a799d71
AK		 4462 } else {
4463 /* Force detection of hung controller */
4464 adapter->detect_tx_hung = true;
4465 }
4466 } else {
cf8280ee
JB		 4467 adapter->link_up = false;
4468 adapter->link_speed = 0;
9a799d71 4469 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4470 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4471 netdev->name);
9a799d71 4472 netif_carrier_off(netdev);
9a799d71
AK		 4473 }
4474 }
4475
bc59fcda
NS		 4476 if (!netif_carrier_ok(netdev)) {
4477 for (i = 0; i < adapter->num_tx_queues; i++) {
4478 tx_ring = &adapter->tx_ring[i];
4479 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4480 some_tx_pending = 1;
4481 break;
4482 }
4483 }
4484
4485 if (some_tx_pending) {
4486 /* We've lost link, so the controller stops DMA,
4487 * but we've got queued Tx work that's never going
4488 * to get done, so reset controller to flush Tx.
4489 * (Do the reset outside of interrupt context).
4490 */
4491 schedule_work(&adapter->reset_task);
4492 }
4493 }
4494
9a799d71 4495 ixgbe_update_stats(adapter);
cf8280ee 4496 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4497}
4498
9a799d71 4499static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4500 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4501 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4502{
4503 struct ixgbe_adv_tx_context_desc *context_desc;
4504 unsigned int i;
4505 int err;
4506 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4507 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4508 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4509
4510 if (skb_is_gso(skb)) {
4511 if (skb_header_cloned(skb)) {
4512 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4513 if (err)
4514 return err;
4515 }
4516 l4len = tcp_hdrlen(skb);
4517 *hdr_len += l4len;
4518
8327d000 4519 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4520 struct iphdr *iph = ip_hdr(skb);
4521 iph->tot_len = 0;
4522 iph->check = 0;
4523 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4524 iph->daddr, 0,
4525 IPPROTO_TCP,
4526 0);
9a799d71
AK		 4527 adapter->hw_tso_ctxt++;
4528 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4529 ipv6_hdr(skb)->payload_len = 0;
4530 tcp_hdr(skb)->check =
4531 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4532 &ipv6_hdr(skb)->daddr,
4533 0, IPPROTO_TCP, 0);
9a799d71
AK		 4534 adapter->hw_tso6_ctxt++;
4535 }
4536
4537 i = tx_ring->next_to_use;
4538
4539 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4540 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4541
4542 /* VLAN MACLEN IPLEN */
4543 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4544 vlan_macip_lens |=
4545 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4546 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4547 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4548 *hdr_len += skb_network_offset(skb);
4549 vlan_macip_lens |=
4550 (skb_transport_header(skb) - skb_network_header(skb));
4551 *hdr_len +=
4552 (skb_transport_header(skb) - skb_network_header(skb));
4553 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4554 context_desc->seqnum_seed = 0;
4555
4556 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4557 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4558 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4559
8327d000 4560 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4561 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4562 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4563 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4564
4565 /* MSS L4LEN IDX */
9f8cdf4f 4566 mss_l4len_idx =
9a799d71
AK		 4567 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4568 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4569 /* use index 1 for TSO */
4570 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4571 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4572
4573 tx_buffer_info->time_stamp = jiffies;
4574 tx_buffer_info->next_to_watch = i;
4575
4576 i++;
4577 if (i == tx_ring->count)
4578 i = 0;
4579 tx_ring->next_to_use = i;
4580
4581 return true;
4582 }
4583 return false;
4584}
4585
4586static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4587 struct ixgbe_ring *tx_ring,
4588 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4589{
4590 struct ixgbe_adv_tx_context_desc *context_desc;
4591 unsigned int i;
4592 struct ixgbe_tx_buffer *tx_buffer_info;
4593 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4594
4595 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4596 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4597 i = tx_ring->next_to_use;
4598 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4599 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4600
4601 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4602 vlan_macip_lens |=
4603 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4604 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4605 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4606 if (skb->ip_summed == CHECKSUM_PARTIAL)
4607 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4608 skb_network_header(skb));
9a799d71
AK		 4609
4610 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4611 context_desc->seqnum_seed = 0;
4612
4613 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4614 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4615
4616 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4617 switch (skb->protocol) {
09640e63 4618 case cpu_to_be16(ETH_P_IP):
9a799d71 4619 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4620 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4621 type_tucmd_mlhl |=
b4617240 4622 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4623 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4624 type_tucmd_mlhl |=
4625 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4626 break;
09640e63 4627 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4628 /* XXX what about other V6 headers?? */
4629 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4630 type_tucmd_mlhl |=
b4617240 4631 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4632 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4633 type_tucmd_mlhl |=
4634 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4635 break;
41825d71
AK		 4636 default:
4637 if (unlikely(net_ratelimit())) {
4638 DPRINTK(PROBE, WARNING,
4639 "partial checksum but proto=%x!\n",
4640 skb->protocol);
4641 }
4642 break;
4643 }
9a799d71
AK		 4644 }
4645
4646 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4647 /* use index zero for tx checksum offload */
9a799d71
AK		 4648 context_desc->mss_l4len_idx = 0;
4649
4650 tx_buffer_info->time_stamp = jiffies;
4651 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4652
9a799d71
AK		 4653 adapter->hw_csum_tx_good++;
4654 i++;
4655 if (i == tx_ring->count)
4656 i = 0;
4657 tx_ring->next_to_use = i;
4658
4659 return true;
4660 }
9f8cdf4f 4661
9a799d71
AK		 4662 return false;
4663}
4664
4665static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 4666 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 4667 struct sk_buff *skb, u32 tx_flags,
4668 unsigned int first)
9a799d71
AK		 4669{
4670 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 4671 unsigned int len;
4672 unsigned int total = skb->len;
9a799d71
AK		 4673 unsigned int offset = 0, size, count = 0, i;
4674 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4675 unsigned int f;
44df32c5 4676 dma_addr_t *map;
9a799d71
AK		 4677
4678 i = tx_ring->next_to_use;
4679
44df32c5
AD		 4680 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4681 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4682 return 0;
4683 }
4684
4685 map = skb_shinfo(skb)->dma_maps;
4686
eacd73f7
YZ		 4687 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4688 /* excluding fcoe_crc_eof for FCoE */
4689 total -= sizeof(struct fcoe_crc_eof);
4690
4691 len = min(skb_headlen(skb), total);
9a799d71
AK		 4692 while (len) {
4693 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4694 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4695
4696 tx_buffer_info->length = size;
44df32c5 4697 tx_buffer_info->dma = map[0] + offset;
9a799d71
AK		 4698 tx_buffer_info->time_stamp = jiffies;
4699 tx_buffer_info->next_to_watch = i;
4700
4701 len -= size;
eacd73f7 4702 total -= size;
9a799d71
AK		 4703 offset += size;
4704 count++;
44df32c5
AD		 4705
4706 if (len) {
4707 i++;
4708 if (i == tx_ring->count)
4709 i = 0;
4710 }
9a799d71
AK		 4711 }
4712
4713 for (f = 0; f < nr_frags; f++) {
4714 struct skb_frag_struct *frag;
4715
4716 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 4717 len = min((unsigned int)frag->size, total);
44df32c5 4718 offset = 0;
9a799d71
AK		 4719
4720 while (len) {
44df32c5
AD		 4721 i++;
4722 if (i == tx_ring->count)
4723 i = 0;
4724
9a799d71
AK		 4725 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4726 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4727
4728 tx_buffer_info->length = size;
44df32c5 4729 tx_buffer_info->dma = map[f + 1] + offset;
9a799d71
AK		 4730 tx_buffer_info->time_stamp = jiffies;
4731 tx_buffer_info->next_to_watch = i;
4732
4733 len -= size;
eacd73f7 4734 total -= size;
9a799d71
AK		 4735 offset += size;
4736 count++;
9a799d71 4737 }
eacd73f7
YZ		 4738 if (total == 0)
4739 break;
9a799d71 4740 }
44df32c5 4741
9a799d71
AK		 4742 tx_ring->tx_buffer_info[i].skb = skb;
4743 tx_ring->tx_buffer_info[first].next_to_watch = i;
4744
4745 return count;
4746}
4747
4748static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4749 struct ixgbe_ring *tx_ring,
4750 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4751{
4752 union ixgbe_adv_tx_desc *tx_desc = NULL;
4753 struct ixgbe_tx_buffer *tx_buffer_info;
4754 u32 olinfo_status = 0, cmd_type_len = 0;
4755 unsigned int i;
4756 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4757
4758 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4759
4760 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4761
4762 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4763 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4764
4765 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4766 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4767
4768 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4769 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4770
4eeae6fd
PW		 4771 /* use index 1 context for tso */
4772 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4773 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4774 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 4775 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4776
4777 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4778 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4779 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4780
eacd73f7
YZ		 4781 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4782 olinfo_status |= IXGBE_ADVTXD_CC;
4783 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4784 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4785 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4786 }
4787
9a799d71
AK		 4788 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4789
4790 i = tx_ring->next_to_use;
4791 while (count--) {
4792 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4793 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4794 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4795 tx_desc->read.cmd_type_len =
b4617240 4796 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 4797 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 4798 i++;
4799 if (i == tx_ring->count)
4800 i = 0;
4801 }
4802
4803 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4804
4805 /*
4806 * Force memory writes to complete before letting h/w
4807 * know there are new descriptors to fetch. (Only
4808 * applicable for weak-ordered memory model archs,
4809 * such as IA-64).
4810 */
4811 wmb();
4812
4813 tx_ring->next_to_use = i;
4814 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4815}
4816
e092be60 4817static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4818 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4819{
4820 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4821
30eba97a 4822 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4823 /* Herbert's original patch had:
4824 * smp_mb__after_netif_stop_queue();
4825 * but since that doesn't exist yet, just open code it. */
4826 smp_mb();
4827
4828 /* We need to check again in a case another CPU has just
4829 * made room available. */
4830 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4831 return -EBUSY;
4832
4833 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 4834 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4835 ++adapter->restart_queue;
4836 return 0;
4837}
4838
4839static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4840 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4841{
4842 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4843 return 0;
4844 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4845}
4846
09a3b1f8
SH		 4847static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4848{
4849 struct ixgbe_adapter *adapter = netdev_priv(dev);
4850
4851 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4852 return 0; /* All traffic should default to class 0 */
4853
4854 return skb_tx_hash(dev, skb);
4855}
4856
9a799d71
AK		 4857static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4858{
4859 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4860 struct ixgbe_ring *tx_ring;
9a799d71
AK		 4861 unsigned int first;
4862 unsigned int tx_flags = 0;
30eba97a
AV		 4863 u8 hdr_len = 0;
4864 int r_idx = 0, tso;
9a799d71
AK		 4865 int count = 0;
4866 unsigned int f;
9f8cdf4f 4867
95615d90 4868 r_idx = skb->queue_mapping;
30eba97a 4869 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 4870
9f8cdf4f
JB		 4871 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4872 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 4873 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4874 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4875 tx_flags |= (skb->queue_mapping << 13);
4876 }
4877 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4878 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4879 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4880 tx_flags |= (skb->queue_mapping << 13);
9f8cdf4f
JB		 4881 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4882 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 4883 }
eacd73f7
YZ		 4884
4885 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4886 (skb->protocol == htons(ETH_P_FCOE)))
4887 tx_flags |= IXGBE_TX_FLAGS_FCOE;
4888
4889 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 4890 if (skb_is_gso(skb) ||
4891 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 4892 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
4893 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 4894 count++;
4895
9f8cdf4f
JB		 4896 count += TXD_USE_COUNT(skb_headlen(skb));
4897 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 4898 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4899
e092be60 4900 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 4901 adapter->tx_busy++;
9a799d71
AK		 4902 return NETDEV_TX_BUSY;
4903 }
9a799d71 4904
9a799d71 4905 first = tx_ring->next_to_use;
eacd73f7
YZ		 4906 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4907#ifdef IXGBE_FCOE
4908 /* setup tx offload for FCoE */
4909 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4910 if (tso < 0) {
4911 dev_kfree_skb_any(skb);
4912 return NETDEV_TX_OK;
4913 }
4914 if (tso)
4915 tx_flags |= IXGBE_TX_FLAGS_FSO;
4916#endif /* IXGBE_FCOE */
4917 } else {
4918 if (skb->protocol == htons(ETH_P_IP))
4919 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4920 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4921 if (tso < 0) {
4922 dev_kfree_skb_any(skb);
4923 return NETDEV_TX_OK;
4924 }
9a799d71 4925
eacd73f7
YZ		 4926 if (tso)
4927 tx_flags |= IXGBE_TX_FLAGS_TSO;
4928 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
4929 (skb->ip_summed == CHECKSUM_PARTIAL))
4930 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4931 }
9a799d71 4932
eacd73f7 4933 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5
AD		 4934 if (count) {
4935 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4936 hdr_len);
44df32c5 4937 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 4938
44df32c5
AD		 4939 } else {
4940 dev_kfree_skb_any(skb);
4941 tx_ring->tx_buffer_info[first].time_stamp = 0;
4942 tx_ring->next_to_use = first;
4943 }
9a799d71
AK		 4944
4945 return NETDEV_TX_OK;
4946}
4947
4948/**
4949 * ixgbe_get_stats - Get System Network Statistics
4950 * @netdev: network interface device structure
4951 *
4952 * Returns the address of the device statistics structure.
4953 * The statistics are actually updated from the timer callback.
4954 **/
4955static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4956{
4957 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4958
4959 /* only return the current stats */
4960 return &adapter->net_stats;
4961}
4962
4963/**
4964 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4965 * @netdev: network interface device structure
4966 * @p: pointer to an address structure
4967 *
4968 * Returns 0 on success, negative on failure
4969 **/
4970static int ixgbe_set_mac(struct net_device *netdev, void *p)
4971{
4972 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 4973 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 4974 struct sockaddr *addr = p;
4975
4976 if (!is_valid_ether_addr(addr->sa_data))
4977 return -EADDRNOTAVAIL;
4978
4979 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 4980 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 4981
b4617240 4982 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 4983
4984 return 0;
4985}
4986
6b73e10d
BH		 4987static int
4988ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
4989{
4990 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4991 struct ixgbe_hw *hw = &adapter->hw;
4992 u16 value;
4993 int rc;
4994
4995 if (prtad != hw->phy.mdio.prtad)
4996 return -EINVAL;
4997 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
4998 if (!rc)
4999 rc = value;
5000 return rc;
5001}
5002
5003static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5004 u16 addr, u16 value)
5005{
5006 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5007 struct ixgbe_hw *hw = &adapter->hw;
5008
5009 if (prtad != hw->phy.mdio.prtad)
5010 return -EINVAL;
5011 return hw->phy.ops.write_reg(hw, addr, devad, value);
5012}
5013
5014static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5015{
5016 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5017
5018 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5019}
5020
0365e6e4
PW		 5021/**
5022 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5023 * netdev->dev_addr_list
5024 * @netdev: network interface device structure
5025 *
5026 * Returns non-zero on failure
5027 **/
5028static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5029{
5030 int err = 0;
5031 struct ixgbe_adapter *adapter = netdev_priv(dev);
5032 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5033
5034 if (is_valid_ether_addr(mac->san_addr)) {
5035 rtnl_lock();
5036 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5037 rtnl_unlock();
5038 }
5039 return err;
5040}
5041
5042/**
5043 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5044 * netdev->dev_addr_list
5045 * @netdev: network interface device structure
5046 *
5047 * Returns non-zero on failure
5048 **/
5049static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5050{
5051 int err = 0;
5052 struct ixgbe_adapter *adapter = netdev_priv(dev);
5053 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5054
5055 if (is_valid_ether_addr(mac->san_addr)) {
5056 rtnl_lock();
5057 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5058 rtnl_unlock();
5059 }
5060 return err;
5061}
5062
9a799d71
AK		 5063#ifdef CONFIG_NET_POLL_CONTROLLER
5064/*
5065 * Polling 'interrupt' - used by things like netconsole to send skbs
5066 * without having to re-enable interrupts. It's not called while
5067 * the interrupt routine is executing.
5068 */
5069static void ixgbe_netpoll(struct net_device *netdev)
5070{
5071 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5072
5073 disable_irq(adapter->pdev->irq);
5074 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5075 ixgbe_intr(adapter->pdev->irq, netdev);
5076 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5077 enable_irq(adapter->pdev->irq);
5078}
5079#endif
5080
0edc3527
SH		 5081static const struct net_device_ops ixgbe_netdev_ops = {
5082 .ndo_open = ixgbe_open,
5083 .ndo_stop = ixgbe_close,
00829823 5084 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5085 .ndo_select_queue = ixgbe_select_queue,
0edc3527 5086 .ndo_get_stats = ixgbe_get_stats,
e90d400c 5087 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5088 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5089 .ndo_validate_addr = eth_validate_addr,
5090 .ndo_set_mac_address = ixgbe_set_mac,
5091 .ndo_change_mtu = ixgbe_change_mtu,
5092 .ndo_tx_timeout = ixgbe_tx_timeout,
5093 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5094 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5095 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5096 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5097#ifdef CONFIG_NET_POLL_CONTROLLER
5098 .ndo_poll_controller = ixgbe_netpoll,
5099#endif
332d4a7d
YZ		 5100#ifdef IXGBE_FCOE
5101 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5102 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5103#endif /* IXGBE_FCOE */
0edc3527
SH		 5104};
5105
9a799d71
AK		 5106/**
5107 * ixgbe_probe - Device Initialization Routine
5108 * @pdev: PCI device information struct
5109 * @ent: entry in ixgbe_pci_tbl
5110 *
5111 * Returns 0 on success, negative on failure
5112 *
5113 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5114 * The OS initialization, configuring of the adapter private structure,
5115 * and a hardware reset occur.
5116 **/
5117static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5118 const struct pci_device_id *ent)
9a799d71
AK		 5119{
5120 struct net_device *netdev;
5121 struct ixgbe_adapter *adapter = NULL;
5122 struct ixgbe_hw *hw;
5123 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5124 static int cards_found;
5125 int i, err, pci_using_dac;
eacd73f7
YZ		 5126#ifdef IXGBE_FCOE
5127 u16 device_caps;
5128#endif
c44ade9e 5129 u32 part_num, eec;
9a799d71 5130
9ce77666 5131 err = pci_enable_device_mem(pdev);
9a799d71
AK		 5132 if (err)
5133 return err;
5134
6a35528a
YH		 5135 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5136 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 5137 pci_using_dac = 1;
5138 } else {
284901a9 5139 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5140 if (err) {
284901a9 5141 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5142 if (err) {
b4617240
PW		 5143 dev_err(&pdev->dev, "No usable DMA "
5144 "configuration, aborting\n");
9a799d71
AK		 5145 goto err_dma;
5146 }
5147 }
5148 pci_using_dac = 0;
5149 }
5150
9ce77666 5151 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5152 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 5153 if (err) {
9ce77666 5154 dev_err(&pdev->dev,
5155 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 5156 goto err_pci_reg;
5157 }
5158
6fabd715
PWJ		 5159 err = pci_enable_pcie_error_reporting(pdev);
5160 if (err) {
5161 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5162 "0x%x\n", err);
5163 /* non-fatal, continue */
5164 }
5165
9a799d71 5166 pci_set_master(pdev);
fb3b27bc 5167 pci_save_state(pdev);
9a799d71 5168
30eba97a 5169 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 5170 if (!netdev) {
5171 err = -ENOMEM;
5172 goto err_alloc_etherdev;
5173 }
5174
9a799d71
AK		 5175 SET_NETDEV_DEV(netdev, &pdev->dev);
5176
5177 pci_set_drvdata(pdev, netdev);
5178 adapter = netdev_priv(netdev);
5179
5180 adapter->netdev = netdev;
5181 adapter->pdev = pdev;
5182 hw = &adapter->hw;
5183 hw->back = adapter;
5184 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5185
05857980
JK		 5186 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5187 pci_resource_len(pdev, 0));
9a799d71
AK		 5188 if (!hw->hw_addr) {
5189 err = -EIO;
5190 goto err_ioremap;
5191 }
5192
5193 for (i = 1; i <= 5; i++) {
5194 if (pci_resource_len(pdev, i) == 0)
5195 continue;
5196 }
5197
0edc3527 5198 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 5199 ixgbe_set_ethtool_ops(netdev);
9a799d71 5200 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 5201 strcpy(netdev->name, pci_name(pdev));
5202
9a799d71
AK		 5203 adapter->bd_number = cards_found;
5204
9a799d71
AK		 5205 /* Setup hw api */
5206 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 5207 hw->mac.type = ii->mac;
9a799d71 5208
c44ade9e
JB		 5209 /* EEPROM */
5210 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5211 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5212 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5213 if (!(eec & (1 << 8)))
5214 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5215
5216 /* PHY */
5217 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 5218 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 5219 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5220 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5221 hw->phy.mdio.mmds = 0;
5222 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5223 hw->phy.mdio.dev = netdev;
5224 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5225 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 5226
5227 /* set up this timer and work struct before calling get_invariants
5228 * which might start the timer
5229 */
5230 init_timer(&adapter->sfp_timer);
5231 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5232 adapter->sfp_timer.data = (unsigned long) adapter;
5233
5234 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 5235
e8e26350
PW		 5236 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5237 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5238
5239 /* a new SFP+ module arrival, called from GPI SDP2 context */
5240 INIT_WORK(&adapter->sfp_config_module_task,
5241 ixgbe_sfp_config_module_task);
5242
8ca783ab 5243 ii->get_invariants(hw);
9a799d71
AK		 5244
5245 /* setup the private structure */
5246 err = ixgbe_sw_init(adapter);
5247 if (err)
5248 goto err_sw_init;
5249
bf069c97
DS		 5250 /*
5251 * If there is a fan on this device and it has failed log the
5252 * failure.
5253 */
5254 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5255 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5256 if (esdp & IXGBE_ESDP_SDP1)
5257 DPRINTK(PROBE, CRIT,
5258 "Fan has stopped, replace the adapter\n");
5259 }
5260
c44ade9e
JB		 5261 /* reset_hw fills in the perm_addr as well */
5262 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 5263 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5264 hw->mac.type == ixgbe_mac_82598EB) {
5265 /*
5266 * Start a kernel thread to watch for a module to arrive.
5267 * Only do this for 82598, since 82599 will generate
5268 * interrupts on module arrival.
5269 */
5270 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5271 mod_timer(&adapter->sfp_timer,
5272 round_jiffies(jiffies + (2 * HZ)));
5273 err = 0;
5274 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
04f165ef
PW		 5275 dev_err(&adapter->pdev->dev, "failed to load because an "
5276 "unsupported SFP+ module type was detected.\n");
5277 goto err_sw_init;
5278 } else if (err) {
c44ade9e
JB		 5279 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5280 goto err_sw_init;
5281 }
5282
9a799d71 5283 netdev->features = NETIF_F_SG |
b4617240
PW		 5284 NETIF_F_IP_CSUM |
5285 NETIF_F_HW_VLAN_TX |
5286 NETIF_F_HW_VLAN_RX |
5287 NETIF_F_HW_VLAN_FILTER;
9a799d71 5288
e9990a9c 5289 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 5290 netdev->features |= NETIF_F_TSO;
9a799d71 5291 netdev->features |= NETIF_F_TSO6;
78b6f4ce 5292 netdev->features |= NETIF_F_GRO;
ad31c402 5293
45a5ead0
JB		 5294 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5295 netdev->features |= NETIF_F_SCTP_CSUM;
5296
ad31c402
JK		 5297 netdev->vlan_features |= NETIF_F_TSO;
5298 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 5299 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 5300 netdev->vlan_features |= NETIF_F_SG;
5301
2f90b865
AD		 5302 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5303 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5304
7a6b6f51 5305#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5306 netdev->dcbnl_ops = &dcbnl_ops;
5307#endif
5308
eacd73f7
YZ		 5309#ifdef IXGBE_FCOE
5310 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
5311 if (hw->mac.ops.get_device_caps) {
5312 hw->mac.ops.get_device_caps(hw, &device_caps);
5313 if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) {
5314 netdev->features |= NETIF_F_FCOE_CRC;
5315 netdev->features |= NETIF_F_FSO;
332d4a7d 5316 netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1;
eacd73f7
YZ		 5317 } else {
5318 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5319 }
5320 }
5321 }
5322#endif /* IXGBE_FCOE */
9a799d71
AK		 5323 if (pci_using_dac)
5324 netdev->features |= NETIF_F_HIGHDMA;
5325
f8212f97
AD		 5326 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED)
5327 netdev->features |= NETIF_F_LRO;
5328
9a799d71 5329 /* make sure the EEPROM is good */
c44ade9e 5330 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 5331 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5332 err = -EIO;
5333 goto err_eeprom;
5334 }
5335
5336 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5337 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5338
c44ade9e
JB		 5339 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5340 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 5341 err = -EIO;
5342 goto err_eeprom;
5343 }
5344
5345 init_timer(&adapter->watchdog_timer);
5346 adapter->watchdog_timer.function = &ixgbe_watchdog;
5347 adapter->watchdog_timer.data = (unsigned long)adapter;
5348
5349 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 5350 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 5351
021230d4
AV		 5352 err = ixgbe_init_interrupt_scheme(adapter);
5353 if (err)
5354 goto err_sw_init;
9a799d71 5355
e8e26350
PW		 5356 switch (pdev->device) {
5357 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 5358 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5359 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
bdf0a550
PWJ		 5360 /* Enable ACPI wakeup in GRC */
5361 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5362 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
e8e26350
PW		 5363 break;
5364 default:
5365 adapter->wol = 0;
5366 break;
5367 }
5368 device_init_wakeup(&adapter->pdev->dev, true);
5369 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5370
04f165ef
PW		 5371 /* pick up the PCI bus settings for reporting later */
5372 hw->mac.ops.get_bus_info(hw);
5373
9a799d71 5374 /* print bus type/speed/width info */
7c510e4b 5375 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 5376 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5377 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5378 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5379 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5380 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 5381 "Unknown"),
7c510e4b 5382 netdev->dev_addr);
c44ade9e 5383 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 5384 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5385 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5386 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5387 (part_num >> 8), (part_num & 0xff));
5388 else
5389 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5390 hw->mac.type, hw->phy.type,
5391 (part_num >> 8), (part_num & 0xff));
9a799d71 5392
e8e26350 5393 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 5394 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 5395 "this card is not sufficient for optimal "
5396 "performance.\n");
0c254d86 5397 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 5398 "PCI-Express slot is required.\n");
0c254d86
AK		 5399 }
5400
34b0368c
PWJ		 5401 /* save off EEPROM version number */
5402 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5403
9a799d71 5404 /* reset the hardware with the new settings */
c44ade9e
JB		 5405 hw->mac.ops.start_hw(hw);
5406
9a799d71
AK		 5407 strcpy(netdev->name, "eth%d");
5408 err = register_netdev(netdev);
5409 if (err)
5410 goto err_register;
5411
54386467
JB		 5412 /* carrier off reporting is important to ethtool even BEFORE open */
5413 netif_carrier_off(netdev);
5414
5dd2d332 5415#ifdef CONFIG_IXGBE_DCA
652f093f 5416 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 5417 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 5418 ixgbe_setup_dca(adapter);
5419 }
5420#endif
0365e6e4
PW		 5421 /* add san mac addr to netdev */
5422 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 5423
5424 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5425 cards_found++;
5426 return 0;
5427
5428err_register:
5eba3699 5429 ixgbe_release_hw_control(adapter);
7a921c93 5430 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 5431err_sw_init:
5432err_eeprom:
c4900be0
DS		 5433 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5434 del_timer_sync(&adapter->sfp_timer);
5435 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5436 cancel_work_sync(&adapter->multispeed_fiber_task);
5437 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5438 iounmap(hw->hw_addr);
5439err_ioremap:
5440 free_netdev(netdev);
5441err_alloc_etherdev:
9ce77666 5442 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5443 IORESOURCE_MEM));
9a799d71
AK		 5444err_pci_reg:
5445err_dma:
5446 pci_disable_device(pdev);
5447 return err;
5448}
5449
5450/**
5451 * ixgbe_remove - Device Removal Routine
5452 * @pdev: PCI device information struct
5453 *
5454 * ixgbe_remove is called by the PCI subsystem to alert the driver
5455 * that it should release a PCI device. The could be caused by a
5456 * Hot-Plug event, or because the driver is going to be removed from
5457 * memory.
5458 **/
5459static void __devexit ixgbe_remove(struct pci_dev *pdev)
5460{
5461 struct net_device *netdev = pci_get_drvdata(pdev);
5462 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 5463 int err;
9a799d71
AK		 5464
5465 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5466 /* clear the module not found bit to make sure the worker won't
5467 * reschedule
5468 */
5469 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5470 del_timer_sync(&adapter->watchdog_timer);
5471
c4900be0
DS		 5472 del_timer_sync(&adapter->sfp_timer);
5473 cancel_work_sync(&adapter->watchdog_task);
5474 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5475 cancel_work_sync(&adapter->multispeed_fiber_task);
5476 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5477 flush_scheduled_work();
5478
5dd2d332 5479#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5480 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5481 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5482 dca_remove_requester(&pdev->dev);
5483 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5484 }
5485
5486#endif
332d4a7d
YZ		 5487#ifdef IXGBE_FCOE
5488 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5489 ixgbe_cleanup_fcoe(adapter);
5490
5491#endif /* IXGBE_FCOE */
0365e6e4
PW		 5492
5493 /* remove the added san mac */
5494 ixgbe_del_sanmac_netdev(netdev);
5495
c4900be0
DS		 5496 if (netdev->reg_state == NETREG_REGISTERED)
5497 unregister_netdev(netdev);
9a799d71 5498
7a921c93 5499 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 5500
021230d4 5501 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5502
5503 iounmap(adapter->hw.hw_addr);
9ce77666 5504 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5505 IORESOURCE_MEM));
9a799d71 5506
021230d4 5507 DPRINTK(PROBE, INFO, "complete\n");
021230d4 5508
9a799d71
AK		 5509 free_netdev(netdev);
5510
6fabd715
PWJ		 5511 err = pci_disable_pcie_error_reporting(pdev);
5512 if (err)
5513 dev_err(&pdev->dev,
5514 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5515
9a799d71
AK		 5516 pci_disable_device(pdev);
5517}
5518
5519/**
5520 * ixgbe_io_error_detected - called when PCI error is detected
5521 * @pdev: Pointer to PCI device
5522 * @state: The current pci connection state
5523 *
5524 * This function is called after a PCI bus error affecting
5525 * this device has been detected.
5526 */
5527static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 5528 pci_channel_state_t state)
9a799d71
AK		 5529{
5530 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5531 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5532
5533 netif_device_detach(netdev);
5534
3044b8d1
BL		 5535 if (state == pci_channel_io_perm_failure)
5536 return PCI_ERS_RESULT_DISCONNECT;
5537
9a799d71
AK		 5538 if (netif_running(netdev))
5539 ixgbe_down(adapter);
5540 pci_disable_device(pdev);
5541
b4617240 5542 /* Request a slot reset. */
9a799d71
AK		 5543 return PCI_ERS_RESULT_NEED_RESET;
5544}
5545
5546/**
5547 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5548 * @pdev: Pointer to PCI device
5549 *
5550 * Restart the card from scratch, as if from a cold-boot.
5551 */
5552static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5553{
5554 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5555 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 5556 pci_ers_result_t result;
5557 int err;
9a799d71 5558
9ce77666 5559 if (pci_enable_device_mem(pdev)) {
9a799d71 5560 DPRINTK(PROBE, ERR,
b4617240 5561 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 5562 result = PCI_ERS_RESULT_DISCONNECT;
5563 } else {
5564 pci_set_master(pdev);
5565 pci_restore_state(pdev);
9a799d71 5566
dd4d8ca6 5567 pci_wake_from_d3(pdev, false);
9a799d71 5568
6fabd715 5569 ixgbe_reset(adapter);
88512539 5570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 5571 result = PCI_ERS_RESULT_RECOVERED;
5572 }
5573
5574 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5575 if (err) {
5576 dev_err(&pdev->dev,
5577 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5578 /* non-fatal, continue */
5579 }
9a799d71 5580
6fabd715 5581 return result;
9a799d71
AK		 5582}
5583
5584/**
5585 * ixgbe_io_resume - called when traffic can start flowing again.
5586 * @pdev: Pointer to PCI device
5587 *
5588 * This callback is called when the error recovery driver tells us that
5589 * its OK to resume normal operation.
5590 */
5591static void ixgbe_io_resume(struct pci_dev *pdev)
5592{
5593 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5594 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5595
5596 if (netif_running(netdev)) {
5597 if (ixgbe_up(adapter)) {
5598 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5599 return;
5600 }
5601 }
5602
5603 netif_device_attach(netdev);
9a799d71
AK		 5604}
5605
5606static struct pci_error_handlers ixgbe_err_handler = {
5607 .error_detected = ixgbe_io_error_detected,
5608 .slot_reset = ixgbe_io_slot_reset,
5609 .resume = ixgbe_io_resume,
5610};
5611
5612static struct pci_driver ixgbe_driver = {
5613 .name = ixgbe_driver_name,
5614 .id_table = ixgbe_pci_tbl,
5615 .probe = ixgbe_probe,
5616 .remove = __devexit_p(ixgbe_remove),
5617#ifdef CONFIG_PM
5618 .suspend = ixgbe_suspend,
5619 .resume = ixgbe_resume,
5620#endif
5621 .shutdown = ixgbe_shutdown,
5622 .err_handler = &ixgbe_err_handler
5623};
5624
5625/**
5626 * ixgbe_init_module - Driver Registration Routine
5627 *
5628 * ixgbe_init_module is the first routine called when the driver is
5629 * loaded. All it does is register with the PCI subsystem.
5630 **/
5631static int __init ixgbe_init_module(void)
5632{
5633 int ret;
5634 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5635 ixgbe_driver_string, ixgbe_driver_version);
5636
5637 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5638
5dd2d332 5639#ifdef CONFIG_IXGBE_DCA
bd0362dd 5640 dca_register_notify(&dca_notifier);
bd0362dd 5641#endif
5dd2d332 5642
9a799d71
AK		 5643 ret = pci_register_driver(&ixgbe_driver);
5644 return ret;
5645}
b4617240 5646
9a799d71
AK		 5647module_init(ixgbe_init_module);
5648
5649/**
5650 * ixgbe_exit_module - Driver Exit Cleanup Routine
5651 *
5652 * ixgbe_exit_module is called just before the driver is removed
5653 * from memory.
5654 **/
5655static void __exit ixgbe_exit_module(void)
5656{
5dd2d332 5657#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5658 dca_unregister_notify(&dca_notifier);
5659#endif
9a799d71
AK		 5660 pci_unregister_driver(&ixgbe_driver);
5661}
bd0362dd 5662
5dd2d332 5663#ifdef CONFIG_IXGBE_DCA
bd0362dd 5664static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 5665 void *p)
bd0362dd
JC		 5666{
5667 int ret_val;
5668
5669 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 5670 __ixgbe_notify_dca);
bd0362dd
JC		 5671
5672 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5673}
b453368d 5674
5dd2d332 5675#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 5676#ifdef DEBUG
5677/**
5678 * ixgbe_get_hw_dev_name - return device name string
5679 * used by hardware layer to print debugging information
5680 **/
5681char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5682{
5683 struct ixgbe_adapter *adapter = hw->back;
5684 return adapter->netdev->name;
5685}
bd0362dd 5686
b453368d 5687#endif
9a799d71
AK		 5688module_exit(ixgbe_exit_module);
5689
5690/* ixgbe_main.c */
Linux kernel - Deliverables
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