projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgbe: Fix the Tx clean logic to return proper status
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42
43#include "ixgbe.h"
44#include "ixgbe_common.h"
45
46char ixgbe_driver_name[] = "ixgbe";
9c8eb720 47static const char ixgbe_driver_string[] =
b4617240 48 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 49
e8e26350 50#define DRV_VERSION "2.0.8-k2"
9c8eb720 51const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 52static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 53
54static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 55 [board_82598] = &ixgbe_82598_info,
e8e26350 56 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 57};
58
59/* ixgbe_pci_tbl - PCI Device ID Table
60 *
61 * Wildcard entries (PCI_ANY_ID) should come last
62 * Last entry must be all 0s
63 *
64 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
65 * Class, Class Mask, private data (not used) }
66 */
67static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 68 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
69 board_82598 },
9a799d71 70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 71 board_82598 },
9a799d71 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 73 board_82598 },
0befdb3e
JB		 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
75 board_82598 },
9a799d71 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 77 board_82598 },
8d792cd9
JB		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
79 board_82598 },
c4900be0
DS		 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
83 board_82598 },
b95f5fcb
JB		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
85 board_82598 },
c4900be0
DS		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
87 board_82598 },
2f21bdd3
DS		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
89 board_82598 },
e8e26350
PW		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
91 board_82599 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
93 board_82599 },
9a799d71
AK		 94
95 /* required last entry */
96 {0, }
97};
98MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
99
5dd2d332 100#ifdef CONFIG_IXGBE_DCA
bd0362dd 101static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 102 void *p);
bd0362dd
JC		 103static struct notifier_block dca_notifier = {
104 .notifier_call = ixgbe_notify_dca,
105 .next = NULL,
106 .priority = 0
107};
108#endif
109
9a799d71
AK		 110MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
111MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
112MODULE_LICENSE("GPL");
113MODULE_VERSION(DRV_VERSION);
114
115#define DEFAULT_DEBUG_LEVEL_SHIFT 3
116
5eba3699
AV		 117static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
118{
119 u32 ctrl_ext;
120
121 /* Let firmware take over control of h/w */
122 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
123 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 124 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 125}
126
127static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
128{
129 u32 ctrl_ext;
130
131 /* Let firmware know the driver has taken over */
132 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 134 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 135}
9a799d71 136
e8e26350
PW		 137/*
138 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
139 * @adapter: pointer to adapter struct
140 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
141 * @queue: queue to map the corresponding interrupt to
142 * @msix_vector: the vector to map to the corresponding queue
143 *
144 */
145static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
146 u8 queue, u8 msix_vector)
9a799d71
AK		 147{
148 u32 ivar, index;
e8e26350
PW		 149 struct ixgbe_hw *hw = &adapter->hw;
150 switch (hw->mac.type) {
151 case ixgbe_mac_82598EB:
152 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
153 if (direction == -1)
154 direction = 0;
155 index = (((direction * 64) + queue) >> 2) & 0x1F;
156 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
157 ivar &= ~(0xFF << (8 * (queue & 0x3)));
158 ivar |= (msix_vector << (8 * (queue & 0x3)));
159 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
160 break;
161 case ixgbe_mac_82599EB:
162 if (direction == -1) {
163 /* other causes */
164 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
165 index = ((queue & 1) * 8);
166 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
167 ivar &= ~(0xFF << index);
168 ivar |= (msix_vector << index);
169 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
170 break;
171 } else {
172 /* tx or rx causes */
173 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
174 index = ((16 * (queue & 1)) + (8 * direction));
175 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
176 ivar &= ~(0xFF << index);
177 ivar |= (msix_vector << index);
178 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
179 break;
180 }
181 default:
182 break;
183 }
9a799d71
AK		 184}
185
186static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 187 struct ixgbe_tx_buffer
188 *tx_buffer_info)
9a799d71
AK		 189{
190 if (tx_buffer_info->dma) {
e01c31a5 191 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
b4617240 192 tx_buffer_info->length, PCI_DMA_TODEVICE);
9a799d71
AK		 193 tx_buffer_info->dma = 0;
194 }
195 if (tx_buffer_info->skb) {
196 dev_kfree_skb_any(tx_buffer_info->skb);
197 tx_buffer_info->skb = NULL;
198 }
199 /* tx_buffer_info must be completely set up in the transmit path */
200}
201
202static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 203 struct ixgbe_ring *tx_ring,
204 unsigned int eop)
9a799d71 205{
e01c31a5
JB		 206 struct ixgbe_hw *hw = &adapter->hw;
207 u32 head, tail;
208
9a799d71 209 /* Detect a transmit hang in hardware, this serializes the
e01c31a5
JB		 210 * check with the clearing of time_stamp and movement of eop */
211 head = IXGBE_READ_REG(hw, tx_ring->head);
212 tail = IXGBE_READ_REG(hw, tx_ring->tail);
9a799d71 213 adapter->detect_tx_hung = false;
e01c31a5
JB		 214 if ((head != tail) &&
215 tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 216 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
217 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
218 /* detected Tx unit hang */
e01c31a5
JB		 219 union ixgbe_adv_tx_desc *tx_desc;
220 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 221 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 222 " Tx Queue <%d>\n"
223 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 224 " next_to_use <%x>\n"
225 " next_to_clean <%x>\n"
226 "tx_buffer_info[next_to_clean]\n"
227 " time_stamp <%lx>\n"
e01c31a5
JB		 228 " jiffies <%lx>\n",
229 tx_ring->queue_index,
230 head, tail,
231 tx_ring->next_to_use, eop,
232 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 233 return true;
234 }
235
236 return false;
237}
238
b4617240
PW		 239#define IXGBE_MAX_TXD_PWR 14
240#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 241
242/* Tx Descriptors needed, worst case */
243#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
244 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
245#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 246 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 247
e01c31a5
JB		 248static void ixgbe_tx_timeout(struct net_device *netdev);
249
9a799d71
AK		 250/**
251 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
252 * @adapter: board private structure
e01c31a5 253 * @tx_ring: tx ring to clean
9a1a69ad
JB		 254 *
255 * returns true if transmit work is done
9a799d71
AK		 256 **/
257static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 258 struct ixgbe_ring *tx_ring)
9a799d71 259{
e01c31a5 260 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 261 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
262 struct ixgbe_tx_buffer *tx_buffer_info;
263 unsigned int i, eop, count = 0;
e01c31a5 264 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 265
266 i = tx_ring->next_to_clean;
12207e49
PWJ		 267 eop = tx_ring->tx_buffer_info[i].next_to_watch;
268 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
269
270 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 271 (count < tx_ring->work_limit)) {
12207e49
PWJ		 272 bool cleaned = false;
273 for ( ; !cleaned; count++) {
274 struct sk_buff *skb;
9a799d71
AK		 275 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
276 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 277 cleaned = (i == eop);
e01c31a5 278 skb = tx_buffer_info->skb;
9a799d71 279
12207e49 280 if (cleaned && skb) {
e092be60 281 unsigned int segs, bytecount;
e01c31a5
JB		 282
283 /* gso_segs is currently only valid for tcp */
e092be60
AV		 284 segs = skb_shinfo(skb)->gso_segs ?: 1;
285 /* multiply data chunks by size of headers */
286 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 287 skb->len;
288 total_packets += segs;
289 total_bytes += bytecount;
e092be60 290 }
e01c31a5 291
9a799d71 292 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 293 tx_buffer_info);
9a799d71 294
12207e49
PWJ		 295 tx_desc->wb.status = 0;
296
9a799d71
AK		 297 i++;
298 if (i == tx_ring->count)
299 i = 0;
e01c31a5 300 }
12207e49
PWJ		 301
302 eop = tx_ring->tx_buffer_info[i].next_to_watch;
303 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
304 }
305
9a799d71
AK		 306 tx_ring->next_to_clean = i;
307
e092be60 308#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 309 if (unlikely(count && netif_carrier_ok(netdev) &&
310 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 311 /* Make sure that anybody stopping the queue after this
312 * sees the new next_to_clean.
313 */
314 smp_mb();
30eba97a
AV		 315 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
316 !test_bit(__IXGBE_DOWN, &adapter->state)) {
317 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 318 ++adapter->restart_queue;
30eba97a 319 }
e092be60 320 }
9a799d71 321
e01c31a5
JB		 322 if (adapter->detect_tx_hung) {
323 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
324 /* schedule immediate reset if we believe we hung */
325 DPRINTK(PROBE, INFO,
326 "tx hang %d detected, resetting adapter\n",
327 adapter->tx_timeout_count + 1);
328 ixgbe_tx_timeout(adapter->netdev);
329 }
330 }
9a799d71 331
e01c31a5 332 /* re-arm the interrupt */
9a1a69ad 333 if (count >= tx_ring->work_limit)
e01c31a5 334 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
9a799d71 335
e01c31a5
JB		 336 tx_ring->total_bytes += total_bytes;
337 tx_ring->total_packets += total_packets;
e01c31a5 338 tx_ring->stats.packets += total_packets;
12207e49 339 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 340 adapter->net_stats.tx_bytes += total_bytes;
341 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 342 return (count < tx_ring->work_limit);
9a799d71
AK		 343}
344
5dd2d332 345#ifdef CONFIG_IXGBE_DCA
bd0362dd 346static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 347 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 348{
349 u32 rxctrl;
350 int cpu = get_cpu();
3a581073 351 int q = rx_ring - adapter->rx_ring;
bd0362dd 352
3a581073 353 if (rx_ring->cpu != cpu) {
bd0362dd 354 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 355 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
356 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
357 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
358 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
359 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
360 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
361 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
362 }
bd0362dd
JC		 363 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
364 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 365 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
366 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 367 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 368 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 369 rx_ring->cpu = cpu;
bd0362dd
JC		 370 }
371 put_cpu();
372}
373
374static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 375 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 376{
377 u32 txctrl;
378 int cpu = get_cpu();
3a581073 379 int q = tx_ring - adapter->tx_ring;
bd0362dd 380
3a581073 381 if (tx_ring->cpu != cpu) {
bd0362dd 382 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 383 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
384 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
385 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
386 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
387 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
388 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
389 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
390 }
bd0362dd
JC		 391 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
392 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 393 tx_ring->cpu = cpu;
bd0362dd
JC		 394 }
395 put_cpu();
396}
397
398static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
399{
400 int i;
401
402 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
403 return;
404
405 for (i = 0; i < adapter->num_tx_queues; i++) {
406 adapter->tx_ring[i].cpu = -1;
407 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
408 }
409 for (i = 0; i < adapter->num_rx_queues; i++) {
410 adapter->rx_ring[i].cpu = -1;
411 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
412 }
413}
414
415static int __ixgbe_notify_dca(struct device *dev, void *data)
416{
417 struct net_device *netdev = dev_get_drvdata(dev);
418 struct ixgbe_adapter *adapter = netdev_priv(netdev);
419 unsigned long event = *(unsigned long *)data;
420
421 switch (event) {
422 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 423 /* if we're already enabled, don't do it again */
424 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
425 break;
bd0362dd
JC		 426 /* Always use CB2 mode, difference is masked
427 * in the CB driver. */
428 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 429 if (dca_add_requester(dev) == 0) {
96b0e0f6 430 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 431 ixgbe_setup_dca(adapter);
432 break;
433 }
434 /* Fall Through since DCA is disabled. */
435 case DCA_PROVIDER_REMOVE:
436 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
437 dca_remove_requester(dev);
438 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
439 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
440 }
441 break;
442 }
443
652f093f 444 return 0;
bd0362dd
JC		 445}
446
5dd2d332 447#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 448/**
449 * ixgbe_receive_skb - Send a completed packet up the stack
450 * @adapter: board private structure
451 * @skb: packet to send up
177db6ff
MC		 452 * @status: hardware indication of status of receive
453 * @rx_ring: rx descriptor ring (for a specific queue) to setup
454 * @rx_desc: rx descriptor
9a799d71 455 **/
78b6f4ce 456static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 457 struct sk_buff *skb, u8 status,
177db6ff 458 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 459{
78b6f4ce
HX		 460 struct ixgbe_adapter *adapter = q_vector->adapter;
461 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 462 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
463 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 464
0c8dfc83 465 skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]);
78b6f4ce 466 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
2f90b865 467 if (adapter->vlgrp && is_vlan && (tag != 0))
78b6f4ce 468 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 469 else
78b6f4ce 470 napi_gro_receive(napi, skb);
177db6ff
MC		 471 } else {
472 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 473 if (adapter->vlgrp && is_vlan && (tag != 0))
177db6ff
MC		 474 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
475 else
476 netif_receive_skb(skb);
477 } else {
2f90b865 478 if (adapter->vlgrp && is_vlan && (tag != 0))
177db6ff
MC		 479 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
480 else
481 netif_rx(skb);
482 }
9a799d71
AK		 483 }
484}
485
e59bd25d
AV		 486/**
487 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
488 * @adapter: address of board private structure
489 * @status_err: hardware indication of status of receive
490 * @skb: skb currently being received and modified
491 **/
9a799d71 492static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 493 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 494{
495 skb->ip_summed = CHECKSUM_NONE;
496
712744be
JB		 497 /* Rx csum disabled */
498 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 499 return;
e59bd25d
AV		 500
501 /* if IP and error */
502 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
503 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 504 adapter->hw_csum_rx_error++;
505 return;
506 }
e59bd25d
AV		 507
508 if (!(status_err & IXGBE_RXD_STAT_L4CS))
509 return;
510
511 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
512 adapter->hw_csum_rx_error++;
513 return;
514 }
515
9a799d71 516 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 517 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 518 adapter->hw_csum_rx_good++;
519}
520
e8e26350
PW		 521static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
522 struct ixgbe_ring *rx_ring, u32 val)
523{
524 /*
525 * Force memory writes to complete before letting h/w
526 * know there are new descriptors to fetch. (Only
527 * applicable for weak-ordered memory model archs,
528 * such as IA-64).
529 */
530 wmb();
531 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
532}
533
9a799d71
AK		 534/**
535 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
536 * @adapter: address of board private structure
537 **/
538static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 539 struct ixgbe_ring *rx_ring,
540 int cleaned_count)
9a799d71 541{
9a799d71
AK		 542 struct pci_dev *pdev = adapter->pdev;
543 union ixgbe_adv_rx_desc *rx_desc;
3a581073 544 struct ixgbe_rx_buffer *bi;
9a799d71 545 unsigned int i;
e8e26350 546 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 547
548 i = rx_ring->next_to_use;
3a581073 549 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 550
551 while (cleaned_count--) {
552 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
553
762f4c57 554 if (!bi->page_dma &&
3a581073 555 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 556 if (!bi->page) {
762f4c57
JB		 557 bi->page = alloc_page(GFP_ATOMIC);
558 if (!bi->page) {
559 adapter->alloc_rx_page_failed++;
560 goto no_buffers;
561 }
562 bi->page_offset = 0;
563 } else {
564 /* use a half page if we're re-using */
565 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 566 }
762f4c57
JB		 567
568 bi->page_dma = pci_map_page(pdev, bi->page,
569 bi->page_offset,
570 (PAGE_SIZE / 2),
571 PCI_DMA_FROMDEVICE);
9a799d71
AK		 572 }
573
3a581073 574 if (!bi->skb) {
5ecc3614 575 struct sk_buff *skb;
e8e26350 576 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 577
578 if (!skb) {
579 adapter->alloc_rx_buff_failed++;
580 goto no_buffers;
581 }
582
583 /*
584 * Make buffer alignment 2 beyond a 16 byte boundary
585 * this will result in a 16 byte aligned IP header after
586 * the 14 byte MAC header is removed
587 */
588 skb_reserve(skb, NET_IP_ALIGN);
589
3a581073 590 bi->skb = skb;
e8e26350 591 bi->dma = pci_map_single(pdev, skb->data, bufsz,
3a581073 592 PCI_DMA_FROMDEVICE);
9a799d71
AK		 593 }
594 /* Refresh the desc even if buffer_addrs didn't change because
595 * each write-back erases this info. */
596 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 597 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
598 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 599 } else {
3a581073 600 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 601 }
602
603 i++;
604 if (i == rx_ring->count)
605 i = 0;
3a581073 606 bi = &rx_ring->rx_buffer_info[i];
9a799d71 607 }
7c6e0a43 608
9a799d71
AK		 609no_buffers:
610 if (rx_ring->next_to_use != i) {
611 rx_ring->next_to_use = i;
612 if (i-- == 0)
613 i = (rx_ring->count - 1);
614
e8e26350 615 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 616 }
617}
618
7c6e0a43
JB		 619static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
620{
621 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
622}
623
624static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
625{
626 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
627}
628
78b6f4ce 629static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 630 struct ixgbe_ring *rx_ring,
631 int *work_done, int work_to_do)
9a799d71 632{
78b6f4ce 633 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 634 struct pci_dev *pdev = adapter->pdev;
635 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
636 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
637 struct sk_buff *skb;
638 unsigned int i;
7c6e0a43 639 u32 len, staterr;
177db6ff
MC		 640 u16 hdr_info;
641 bool cleaned = false;
9a799d71 642 int cleaned_count = 0;
d2f4fbe2 643 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 644
645 i = rx_ring->next_to_clean;
9a799d71
AK		 646 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
647 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
648 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 649
650 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 651 u32 upper_len = 0;
9a799d71
AK		 652 if (*work_done >= work_to_do)
653 break;
654 (*work_done)++;
655
656 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 657 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
658 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 659 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 660 if (hdr_info & IXGBE_RXDADV_SPH)
661 adapter->rx_hdr_split++;
662 if (len > IXGBE_RX_HDR_SIZE)
663 len = IXGBE_RX_HDR_SIZE;
664 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 665 } else {
9a799d71 666 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 667 }
9a799d71
AK		 668
669 cleaned = true;
670 skb = rx_buffer_info->skb;
671 prefetch(skb->data - NET_IP_ALIGN);
672 rx_buffer_info->skb = NULL;
673
674 if (len && !skb_shinfo(skb)->nr_frags) {
675 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 676 rx_ring->rx_buf_len,
b4617240 677 PCI_DMA_FROMDEVICE);
9a799d71
AK		 678 skb_put(skb, len);
679 }
680
681 if (upper_len) {
682 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 683 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 684 rx_buffer_info->page_dma = 0;
685 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 686 rx_buffer_info->page,
687 rx_buffer_info->page_offset,
688 upper_len);
689
690 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
691 (page_count(rx_buffer_info->page) != 1))
692 rx_buffer_info->page = NULL;
693 else
694 get_page(rx_buffer_info->page);
9a799d71
AK		 695
696 skb->len += upper_len;
697 skb->data_len += upper_len;
698 skb->truesize += upper_len;
699 }
700
701 i++;
702 if (i == rx_ring->count)
703 i = 0;
704 next_buffer = &rx_ring->rx_buffer_info[i];
705
706 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
707 prefetch(next_rxd);
708
709 cleaned_count++;
710 if (staterr & IXGBE_RXD_STAT_EOP) {
711 rx_ring->stats.packets++;
712 rx_ring->stats.bytes += skb->len;
713 } else {
714 rx_buffer_info->skb = next_buffer->skb;
715 rx_buffer_info->dma = next_buffer->dma;
716 next_buffer->skb = skb;
762f4c57 717 next_buffer->dma = 0;
9a799d71
AK		 718 adapter->non_eop_descs++;
719 goto next_desc;
720 }
721
722 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
723 dev_kfree_skb_irq(skb);
724 goto next_desc;
725 }
726
727 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 728
729 /* probably a little skewed due to removing CRC */
730 total_rx_bytes += skb->len;
731 total_rx_packets++;
732
74ce8dd2 733 skb->protocol = eth_type_trans(skb, adapter->netdev);
78b6f4ce 734 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
9a799d71
AK		 735
736next_desc:
737 rx_desc->wb.upper.status_error = 0;
738
739 /* return some buffers to hardware, one at a time is too slow */
740 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
741 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
742 cleaned_count = 0;
743 }
744
745 /* use prefetched values */
746 rx_desc = next_rxd;
747 rx_buffer_info = next_buffer;
748
749 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 750 }
751
9a799d71
AK		 752 rx_ring->next_to_clean = i;
753 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
754
755 if (cleaned_count)
756 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
757
f494e8fa
AV		 758 rx_ring->total_packets += total_rx_packets;
759 rx_ring->total_bytes += total_rx_bytes;
760 adapter->net_stats.rx_bytes += total_rx_bytes;
761 adapter->net_stats.rx_packets += total_rx_packets;
762
9a799d71
AK		 763 return cleaned;
764}
765
021230d4 766static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 767/**
768 * ixgbe_configure_msix - Configure MSI-X hardware
769 * @adapter: board private structure
770 *
771 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
772 * interrupts.
773 **/
774static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
775{
021230d4
AV		 776 struct ixgbe_q_vector *q_vector;
777 int i, j, q_vectors, v_idx, r_idx;
778 u32 mask;
9a799d71 779
021230d4 780 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 781
021230d4
AV		 782 /* Populate the IVAR table and set the ITR values to the
783 * corresponding register.
784 */
785 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
786 q_vector = &adapter->q_vector[v_idx];
787 /* XXX for_each_bit(...) */
788 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 789 adapter->num_rx_queues);
021230d4
AV		 790
791 for (i = 0; i < q_vector->rxr_count; i++) {
792 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 793 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 794 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 795 adapter->num_rx_queues,
796 r_idx + 1);
021230d4
AV		 797 }
798 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 799 adapter->num_tx_queues);
021230d4
AV		 800
801 for (i = 0; i < q_vector->txr_count; i++) {
802 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 803 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 804 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 805 adapter->num_tx_queues,
806 r_idx + 1);
021230d4
AV		 807 }
808
30efa5a3 809 /* if this is a tx only vector halve the interrupt rate */
021230d4 810 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 811 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 812 else if (q_vector->rxr_count)
30efa5a3
JB		 813 /* rx only */
814 q_vector->eitr = adapter->eitr_param;
021230d4 815
509ee935
JB		 816 /*
817 * since ths is initial set up don't need to call
818 * ixgbe_write_eitr helper
819 */
021230d4 820 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 821 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 822 }
823
e8e26350
PW		 824 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
825 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
826 v_idx);
827 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
828 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 829 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
830
41fb9248 831 /* set up to autoclear timer, and the vectors */
021230d4 832 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 833 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 834 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 835}
836
f494e8fa
AV		 837enum latency_range {
838 lowest_latency = 0,
839 low_latency = 1,
840 bulk_latency = 2,
841 latency_invalid = 255
842};
843
844/**
845 * ixgbe_update_itr - update the dynamic ITR value based on statistics
846 * @adapter: pointer to adapter
847 * @eitr: eitr setting (ints per sec) to give last timeslice
848 * @itr_setting: current throttle rate in ints/second
849 * @packets: the number of packets during this measurement interval
850 * @bytes: the number of bytes during this measurement interval
851 *
852 * Stores a new ITR value based on packets and byte
853 * counts during the last interrupt. The advantage of per interrupt
854 * computation is faster updates and more accurate ITR for the current
855 * traffic pattern. Constants in this function were computed
856 * based on theoretical maximum wire speed and thresholds were set based
857 * on testing data as well as attempting to minimize response time
858 * while increasing bulk throughput.
859 * this functionality is controlled by the InterruptThrottleRate module
860 * parameter (see ixgbe_param.c)
861 **/
862static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 863 u32 eitr, u8 itr_setting,
864 int packets, int bytes)
f494e8fa
AV		 865{
866 unsigned int retval = itr_setting;
867 u32 timepassed_us;
868 u64 bytes_perint;
869
870 if (packets == 0)
871 goto update_itr_done;
872
873
874 /* simple throttlerate management
875 * 0-20MB/s lowest (100000 ints/s)
876 * 20-100MB/s low (20000 ints/s)
877 * 100-1249MB/s bulk (8000 ints/s)
878 */
879 /* what was last interrupt timeslice? */
880 timepassed_us = 1000000/eitr;
881 bytes_perint = bytes / timepassed_us; /* bytes/usec */
882
883 switch (itr_setting) {
884 case lowest_latency:
885 if (bytes_perint > adapter->eitr_low)
886 retval = low_latency;
887 break;
888 case low_latency:
889 if (bytes_perint > adapter->eitr_high)
890 retval = bulk_latency;
891 else if (bytes_perint <= adapter->eitr_low)
892 retval = lowest_latency;
893 break;
894 case bulk_latency:
895 if (bytes_perint <= adapter->eitr_high)
896 retval = low_latency;
897 break;
898 }
899
900update_itr_done:
901 return retval;
902}
903
509ee935
JB		 904/**
905 * ixgbe_write_eitr - write EITR register in hardware specific way
906 * @adapter: pointer to adapter struct
907 * @v_idx: vector index into q_vector array
908 * @itr_reg: new value to be written in *register* format, not ints/s
909 *
910 * This function is made to be called by ethtool and by the driver
911 * when it needs to update EITR registers at runtime. Hardware
912 * specific quirks/differences are taken care of here.
913 */
914void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
915{
916 struct ixgbe_hw *hw = &adapter->hw;
917 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
918 /* must write high and low 16 bits to reset counter */
919 itr_reg |= (itr_reg << 16);
920 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
921 /*
922 * set the WDIS bit to not clear the timer bits and cause an
923 * immediate assertion of the interrupt
924 */
925 itr_reg |= IXGBE_EITR_CNT_WDIS;
926 }
927 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
928}
929
f494e8fa
AV		 930static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
931{
932 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 933 u32 new_itr;
934 u8 current_itr, ret_itr;
935 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
b4617240 936 sizeof(struct ixgbe_q_vector);
f494e8fa
AV		 937 struct ixgbe_ring *rx_ring, *tx_ring;
938
939 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
940 for (i = 0; i < q_vector->txr_count; i++) {
941 tx_ring = &(adapter->tx_ring[r_idx]);
942 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 943 q_vector->tx_itr,
944 tx_ring->total_packets,
945 tx_ring->total_bytes);
f494e8fa
AV		 946 /* if the result for this queue would decrease interrupt
947 * rate for this vector then use that result */
30efa5a3 948 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 949 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 950 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 951 r_idx + 1);
f494e8fa
AV		 952 }
953
954 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
955 for (i = 0; i < q_vector->rxr_count; i++) {
956 rx_ring = &(adapter->rx_ring[r_idx]);
957 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 958 q_vector->rx_itr,
959 rx_ring->total_packets,
960 rx_ring->total_bytes);
f494e8fa
AV		 961 /* if the result for this queue would decrease interrupt
962 * rate for this vector then use that result */
30efa5a3 963 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 964 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 965 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 966 r_idx + 1);
f494e8fa
AV		 967 }
968
30efa5a3 969 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 970
971 switch (current_itr) {
972 /* counts and packets in update_itr are dependent on these numbers */
973 case lowest_latency:
974 new_itr = 100000;
975 break;
976 case low_latency:
977 new_itr = 20000; /* aka hwitr = ~200 */
978 break;
979 case bulk_latency:
980 default:
981 new_itr = 8000;
982 break;
983 }
984
985 if (new_itr != q_vector->eitr) {
986 u32 itr_reg;
509ee935
JB		 987
988 /* save the algorithm value here, not the smoothed one */
989 q_vector->eitr = new_itr;
f494e8fa
AV		 990 /* do an exponential smoothing */
991 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 992 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 993 ixgbe_write_eitr(adapter, v_idx, itr_reg);
f494e8fa
AV		 994 }
995
996 return;
997}
998
0befdb3e
JB		 999static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1000{
1001 struct ixgbe_hw *hw = &adapter->hw;
1002
1003 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1004 (eicr & IXGBE_EICR_GPI_SDP1)) {
1005 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1006 /* write to clear the interrupt */
1007 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1008 }
1009}
cf8280ee 1010
e8e26350
PW		 1011static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1012{
1013 struct ixgbe_hw *hw = &adapter->hw;
1014
1015 if (eicr & IXGBE_EICR_GPI_SDP1) {
1016 /* Clear the interrupt */
1017 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1018 schedule_work(&adapter->multispeed_fiber_task);
1019 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1020 /* Clear the interrupt */
1021 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1022 schedule_work(&adapter->sfp_config_module_task);
1023 } else {
1024 /* Interrupt isn't for us... */
1025 return;
1026 }
1027}
1028
cf8280ee
JB		 1029static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1030{
1031 struct ixgbe_hw *hw = &adapter->hw;
1032
1033 adapter->lsc_int++;
1034 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1035 adapter->link_check_timeout = jiffies;
1036 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1037 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1038 schedule_work(&adapter->watchdog_task);
1039 }
1040}
1041
9a799d71
AK		 1042static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1043{
1044 struct net_device *netdev = data;
1045 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1046 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1047 u32 eicr;
1048
1049 /*
1050 * Workaround for Silicon errata. Use clear-by-write instead
1051 * of clear-by-read. Reading with EICS will return the
1052 * interrupt causes without clearing, which later be done
1053 * with the write to EICR.
1054 */
1055 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1056 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1057
cf8280ee
JB		 1058 if (eicr & IXGBE_EICR_LSC)
1059 ixgbe_check_lsc(adapter);
d4f80882 1060
e8e26350
PW		 1061 if (hw->mac.type == ixgbe_mac_82598EB)
1062 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1063
e8e26350
PW		 1064 if (hw->mac.type == ixgbe_mac_82599EB)
1065 ixgbe_check_sfp_event(adapter, eicr);
d4f80882
AV		 1066 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1067 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1068
1069 return IRQ_HANDLED;
1070}
1071
1072static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1073{
021230d4
AV		 1074 struct ixgbe_q_vector *q_vector = data;
1075 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1076 struct ixgbe_ring *tx_ring;
021230d4
AV		 1077 int i, r_idx;
1078
1079 if (!q_vector->txr_count)
1080 return IRQ_HANDLED;
1081
1082 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1083 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1084 tx_ring = &(adapter->tx_ring[r_idx]);
5dd2d332 1085#ifdef CONFIG_IXGBE_DCA
bd0362dd 1086 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1087 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 1088#endif
3a581073
JB		 1089 tx_ring->total_bytes = 0;
1090 tx_ring->total_packets = 0;
1091 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 1092 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1093 r_idx + 1);
021230d4 1094 }
9a799d71 1095
9a799d71
AK		 1096 return IRQ_HANDLED;
1097}
1098
021230d4
AV		 1099/**
1100 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1101 * @irq: unused
1102 * @data: pointer to our q_vector struct for this interrupt vector
1103 **/
9a799d71
AK		 1104static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1105{
021230d4
AV		 1106 struct ixgbe_q_vector *q_vector = data;
1107 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1108 struct ixgbe_ring *rx_ring;
021230d4 1109 int r_idx;
30efa5a3 1110 int i;
021230d4
AV		 1111
1112 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1113 for (i = 0; i < q_vector->rxr_count; i++) {
1114 rx_ring = &(adapter->rx_ring[r_idx]);
1115 rx_ring->total_bytes = 0;
1116 rx_ring->total_packets = 0;
1117 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1118 r_idx + 1);
1119 }
1120
021230d4
AV		 1121 if (!q_vector->rxr_count)
1122 return IRQ_HANDLED;
1123
30efa5a3 1124 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1125 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1126 /* disable interrupts on this vector only */
3a581073 1127 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
288379f0 1128 napi_schedule(&q_vector->napi);
021230d4
AV		 1129
1130 return IRQ_HANDLED;
1131}
1132
1133static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1134{
1135 ixgbe_msix_clean_rx(irq, data);
1136 ixgbe_msix_clean_tx(irq, data);
9a799d71 1137
9a799d71
AK		 1138 return IRQ_HANDLED;
1139}
1140
021230d4
AV		 1141/**
1142 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1143 * @napi: napi struct with our devices info in it
1144 * @budget: amount of work driver is allowed to do this pass, in packets
1145 *
f0848276
JB		 1146 * This function is optimized for cleaning one queue only on a single
1147 * q_vector!!!
021230d4 1148 **/
9a799d71
AK		 1149static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1150{
021230d4 1151 struct ixgbe_q_vector *q_vector =
b4617240 1152 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1153 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1154 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1155 int work_done = 0;
021230d4 1156 long r_idx;
9a799d71 1157
021230d4 1158 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1159 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1160#ifdef CONFIG_IXGBE_DCA
bd0362dd 1161 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1162 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1163#endif
9a799d71 1164
78b6f4ce 1165 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1166
021230d4
AV		 1167 /* If all Rx work done, exit the polling mode */
1168 if (work_done < budget) {
288379f0 1169 napi_complete(napi);
509ee935 1170 if (adapter->itr_setting & 1)
f494e8fa 1171 ixgbe_set_itr_msix(q_vector);
9a799d71 1172 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3a581073 1173 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
9a799d71
AK		 1174 }
1175
1176 return work_done;
1177}
1178
f0848276
JB		 1179/**
1180 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1181 * @napi: napi struct with our devices info in it
1182 * @budget: amount of work driver is allowed to do this pass, in packets
1183 *
1184 * This function will clean more than one rx queue associated with a
1185 * q_vector.
1186 **/
1187static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1188{
1189 struct ixgbe_q_vector *q_vector =
1190 container_of(napi, struct ixgbe_q_vector, napi);
1191 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1192 struct ixgbe_ring *rx_ring = NULL;
1193 int work_done = 0, i;
1194 long r_idx;
1195 u16 enable_mask = 0;
1196
1197 /* attempt to distribute budget to each queue fairly, but don't allow
1198 * the budget to go below 1 because we'll exit polling */
1199 budget /= (q_vector->rxr_count ?: 1);
1200 budget = max(budget, 1);
1201 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1202 for (i = 0; i < q_vector->rxr_count; i++) {
1203 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1204#ifdef CONFIG_IXGBE_DCA
f0848276
JB		 1205 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1206 ixgbe_update_rx_dca(adapter, rx_ring);
1207#endif
78b6f4ce 1208 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
f0848276
JB		 1209 enable_mask |= rx_ring->v_idx;
1210 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1211 r_idx + 1);
1212 }
1213
1214 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1215 rx_ring = &(adapter->rx_ring[r_idx]);
1216 /* If all Rx work done, exit the polling mode */
7f821875 1217 if (work_done < budget) {
288379f0 1218 napi_complete(napi);
509ee935 1219 if (adapter->itr_setting & 1)
f0848276
JB		 1220 ixgbe_set_itr_msix(q_vector);
1221 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1222 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1223 return 0;
1224 }
1225
1226 return work_done;
1227}
021230d4 1228static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1229 int r_idx)
021230d4
AV		 1230{
1231 a->q_vector[v_idx].adapter = a;
1232 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1233 a->q_vector[v_idx].rxr_count++;
1234 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1235}
1236
1237static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
b4617240 1238 int r_idx)
021230d4
AV		 1239{
1240 a->q_vector[v_idx].adapter = a;
1241 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1242 a->q_vector[v_idx].txr_count++;
1243 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1244}
1245
9a799d71 1246/**
021230d4
AV		 1247 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1248 * @adapter: board private structure to initialize
1249 * @vectors: allotted vector count for descriptor rings
9a799d71 1250 *
021230d4
AV		 1251 * This function maps descriptor rings to the queue-specific vectors
1252 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1253 * one vector per ring/queue, but on a constrained vector budget, we
1254 * group the rings as "efficiently" as possible. You would add new
1255 * mapping configurations in here.
9a799d71 1256 **/
021230d4 1257static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1258 int vectors)
021230d4
AV		 1259{
1260 int v_start = 0;
1261 int rxr_idx = 0, txr_idx = 0;
1262 int rxr_remaining = adapter->num_rx_queues;
1263 int txr_remaining = adapter->num_tx_queues;
1264 int i, j;
1265 int rqpv, tqpv;
1266 int err = 0;
1267
1268 /* No mapping required if MSI-X is disabled. */
1269 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1270 goto out;
9a799d71 1271
021230d4
AV		 1272 /*
1273 * The ideal configuration...
1274 * We have enough vectors to map one per queue.
1275 */
1276 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1277 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1278 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1279
021230d4
AV		 1280 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1281 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1282
9a799d71 1283 goto out;
021230d4 1284 }
9a799d71 1285
021230d4
AV		 1286 /*
1287 * If we don't have enough vectors for a 1-to-1
1288 * mapping, we'll have to group them so there are
1289 * multiple queues per vector.
1290 */
1291 /* Re-adjusting *qpv takes care of the remainder. */
1292 for (i = v_start; i < vectors; i++) {
1293 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1294 for (j = 0; j < rqpv; j++) {
1295 map_vector_to_rxq(adapter, i, rxr_idx);
1296 rxr_idx++;
1297 rxr_remaining--;
1298 }
1299 }
1300 for (i = v_start; i < vectors; i++) {
1301 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1302 for (j = 0; j < tqpv; j++) {
1303 map_vector_to_txq(adapter, i, txr_idx);
1304 txr_idx++;
1305 txr_remaining--;
9a799d71 1306 }
9a799d71
AK		 1307 }
1308
021230d4
AV		 1309out:
1310 return err;
1311}
1312
1313/**
1314 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1315 * @adapter: board private structure
1316 *
1317 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1318 * interrupts from the kernel.
1319 **/
1320static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1321{
1322 struct net_device *netdev = adapter->netdev;
1323 irqreturn_t (*handler)(int, void *);
1324 int i, vector, q_vectors, err;
cb13fc20 1325 int ri=0, ti=0;
021230d4
AV		 1326
1327 /* Decrement for Other and TCP Timer vectors */
1328 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1329
1330 /* Map the Tx/Rx rings to the vectors we were allotted. */
1331 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1332 if (err)
1333 goto out;
1334
1335#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1336 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1337 &ixgbe_msix_clean_many)
021230d4
AV		 1338 for (vector = 0; vector < q_vectors; vector++) {
1339 handler = SET_HANDLER(&adapter->q_vector[vector]);
cb13fc20
RO		 1340
1341 if(handler == &ixgbe_msix_clean_rx) {
1342 sprintf(adapter->name[vector], "%s-%s-%d",
1343 netdev->name, "rx", ri++);
1344 }
1345 else if(handler == &ixgbe_msix_clean_tx) {
1346 sprintf(adapter->name[vector], "%s-%s-%d",
1347 netdev->name, "tx", ti++);
1348 }
1349 else
1350 sprintf(adapter->name[vector], "%s-%s-%d",
1351 netdev->name, "TxRx", vector);
1352
021230d4 1353 err = request_irq(adapter->msix_entries[vector].vector,
b4617240
PW		 1354 handler, 0, adapter->name[vector],
1355 &(adapter->q_vector[vector]));
9a799d71
AK		 1356 if (err) {
1357 DPRINTK(PROBE, ERR,
b4617240
PW		 1358 "request_irq failed for MSIX interrupt "
1359 "Error: %d\n", err);
021230d4 1360 goto free_queue_irqs;
9a799d71 1361 }
9a799d71
AK		 1362 }
1363
021230d4
AV		 1364 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1365 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1366 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1367 if (err) {
1368 DPRINTK(PROBE, ERR,
1369 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1370 goto free_queue_irqs;
9a799d71
AK		 1371 }
1372
9a799d71
AK		 1373 return 0;
1374
021230d4
AV		 1375free_queue_irqs:
1376 for (i = vector - 1; i >= 0; i--)
1377 free_irq(adapter->msix_entries[--vector].vector,
b4617240 1378 &(adapter->q_vector[i]));
021230d4
AV		 1379 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1380 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1381 kfree(adapter->msix_entries);
1382 adapter->msix_entries = NULL;
021230d4 1383out:
9a799d71
AK		 1384 return err;
1385}
1386
f494e8fa
AV		 1387static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1388{
f494e8fa
AV		 1389 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1390 u8 current_itr;
1391 u32 new_itr = q_vector->eitr;
1392 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1393 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1394
30efa5a3 1395 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1396 q_vector->tx_itr,
1397 tx_ring->total_packets,
1398 tx_ring->total_bytes);
30efa5a3 1399 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1400 q_vector->rx_itr,
1401 rx_ring->total_packets,
1402 rx_ring->total_bytes);
f494e8fa 1403
30efa5a3 1404 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1405
1406 switch (current_itr) {
1407 /* counts and packets in update_itr are dependent on these numbers */
1408 case lowest_latency:
1409 new_itr = 100000;
1410 break;
1411 case low_latency:
1412 new_itr = 20000; /* aka hwitr = ~200 */
1413 break;
1414 case bulk_latency:
1415 new_itr = 8000;
1416 break;
1417 default:
1418 break;
1419 }
1420
1421 if (new_itr != q_vector->eitr) {
1422 u32 itr_reg;
509ee935
JB		 1423
1424 /* save the algorithm value here, not the smoothed one */
1425 q_vector->eitr = new_itr;
f494e8fa
AV		 1426 /* do an exponential smoothing */
1427 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1428 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1429 ixgbe_write_eitr(adapter, 0, itr_reg);
f494e8fa
AV		 1430 }
1431
1432 return;
1433}
1434
79aefa45
AD		 1435/**
1436 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1437 * @adapter: board private structure
1438 **/
1439static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1440{
1441 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
e8e26350
PW		 1442 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1443 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1444 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(2), ~0);
1445 }
79aefa45
AD		 1446 IXGBE_WRITE_FLUSH(&adapter->hw);
1447 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1448 int i;
1449 for (i = 0; i < adapter->num_msix_vectors; i++)
1450 synchronize_irq(adapter->msix_entries[i].vector);
1451 } else {
1452 synchronize_irq(adapter->pdev->irq);
1453 }
1454}
1455
1456/**
1457 * ixgbe_irq_enable - Enable default interrupt generation settings
1458 * @adapter: board private structure
1459 **/
1460static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1461{
1462 u32 mask;
1463 mask = IXGBE_EIMS_ENABLE_MASK;
6ab33d51
DM		 1464 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1465 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350
PW		 1466 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1467 mask |= IXGBE_EIMS_GPI_SDP1;
1468 mask |= IXGBE_EIMS_GPI_SDP2;
1469 }
1470
79aefa45 1471 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
e8e26350
PW		 1472 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1473 /* enable the rest of the queue vectors */
1474 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1),
1475 (IXGBE_EIMS_RTX_QUEUE << 16));
1476 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(2),
1477 ((IXGBE_EIMS_RTX_QUEUE << 16) |
1478 IXGBE_EIMS_RTX_QUEUE));
1479 }
79aefa45
AD		 1480 IXGBE_WRITE_FLUSH(&adapter->hw);
1481}
021230d4 1482
9a799d71 1483/**
021230d4 1484 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1485 * @irq: interrupt number
1486 * @data: pointer to a network interface device structure
9a799d71
AK		 1487 **/
1488static irqreturn_t ixgbe_intr(int irq, void *data)
1489{
1490 struct net_device *netdev = data;
1491 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1492 struct ixgbe_hw *hw = &adapter->hw;
1493 u32 eicr;
1494
54037505
DS		 1495 /*
1496 * Workaround for silicon errata. Mask the interrupts
1497 * before the read of EICR.
1498 */
1499 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1500
021230d4
AV		 1501 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1502 * therefore no explict interrupt disable is necessary */
1503 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1504 if (!eicr) {
1505 /* shared interrupt alert!
1506 * make sure interrupts are enabled because the read will
1507 * have disabled interrupts due to EIAM */
1508 ixgbe_irq_enable(adapter);
9a799d71 1509 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1510 }
9a799d71 1511
cf8280ee
JB		 1512 if (eicr & IXGBE_EICR_LSC)
1513 ixgbe_check_lsc(adapter);
021230d4 1514
e8e26350
PW		 1515 if (hw->mac.type == ixgbe_mac_82599EB)
1516 ixgbe_check_sfp_event(adapter, eicr);
1517
0befdb3e
JB		 1518 ixgbe_check_fan_failure(adapter, eicr);
1519
288379f0 1520 if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
f494e8fa
AV		 1521 adapter->tx_ring[0].total_packets = 0;
1522 adapter->tx_ring[0].total_bytes = 0;
1523 adapter->rx_ring[0].total_packets = 0;
1524 adapter->rx_ring[0].total_bytes = 0;
021230d4 1525 /* would disable interrupts here but EIAM disabled it */
288379f0 1526 __napi_schedule(&adapter->q_vector[0].napi);
9a799d71
AK		 1527 }
1528
1529 return IRQ_HANDLED;
1530}
1531
021230d4
AV		 1532static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1533{
1534 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1535
1536 for (i = 0; i < q_vectors; i++) {
1537 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1538 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1539 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1540 q_vector->rxr_count = 0;
1541 q_vector->txr_count = 0;
1542 }
1543}
1544
9a799d71
AK		 1545/**
1546 * ixgbe_request_irq - initialize interrupts
1547 * @adapter: board private structure
1548 *
1549 * Attempts to configure interrupts using the best available
1550 * capabilities of the hardware and kernel.
1551 **/
021230d4 1552static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1553{
1554 struct net_device *netdev = adapter->netdev;
021230d4 1555 int err;
9a799d71 1556
021230d4
AV		 1557 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1558 err = ixgbe_request_msix_irqs(adapter);
1559 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1560 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1561 netdev->name, netdev);
021230d4
AV		 1562 } else {
1563 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1564 netdev->name, netdev);
9a799d71
AK		 1565 }
1566
9a799d71
AK		 1567 if (err)
1568 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1569
9a799d71
AK		 1570 return err;
1571}
1572
1573static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1574{
1575 struct net_device *netdev = adapter->netdev;
1576
1577 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1578 int i, q_vectors;
9a799d71 1579
021230d4
AV		 1580 q_vectors = adapter->num_msix_vectors;
1581
1582 i = q_vectors - 1;
9a799d71 1583 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1584
021230d4
AV		 1585 i--;
1586 for (; i >= 0; i--) {
1587 free_irq(adapter->msix_entries[i].vector,
b4617240 1588 &(adapter->q_vector[i]));
021230d4
AV		 1589 }
1590
1591 ixgbe_reset_q_vectors(adapter);
1592 } else {
1593 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1594 }
1595}
1596
9a799d71
AK		 1597/**
1598 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1599 *
1600 **/
1601static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1602{
9a799d71
AK		 1603 struct ixgbe_hw *hw = &adapter->hw;
1604
021230d4 1605 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1606 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1607
e8e26350
PW		 1608 ixgbe_set_ivar(adapter, 0, 0, 0);
1609 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1610
1611 map_vector_to_rxq(adapter, 0, 0);
1612 map_vector_to_txq(adapter, 0, 0);
1613
1614 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1615}
1616
1617/**
3a581073 1618 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1619 * @adapter: board private structure
1620 *
1621 * Configure the Tx unit of the MAC after a reset.
1622 **/
1623static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1624{
12207e49 1625 u64 tdba;
9a799d71 1626 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1627 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1628
1629 /* Setup the HW Tx Head and Tail descriptor pointers */
1630 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1631 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1632 j = ring->reg_idx;
1633 tdba = ring->dma;
1634 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1635 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
e01c31a5 1636 (tdba & DMA_32BIT_MASK));
021230d4
AV		 1637 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1638 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1639 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1640 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1641 adapter->tx_ring[i].head = IXGBE_TDH(j);
1642 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1643 /* Disable Tx Head Writeback RO bit, since this hoses
1644 * bookkeeping if things aren't delivered in order.
1645 */
e01c31a5 1646 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1647 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1648 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1649 }
e8e26350
PW		 1650 if (hw->mac.type == ixgbe_mac_82599EB) {
1651 /* We enable 8 traffic classes, DCB only */
1652 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1653 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1654 IXGBE_MTQC_8TC_8TQ));
1655 }
9a799d71
AK		 1656}
1657
e8e26350 1658#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c
JB		 1659
1660static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1661{
1662 struct ixgbe_ring *rx_ring;
1663 u32 srrctl;
e8e26350 1664 int queue0 = 0;
3be1adfb
AD		 1665 unsigned long mask;
1666
e8e26350
PW		 1667 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1668 queue0 = index;
cc41ac7c 1669 } else {
3be1adfb
AD		 1670 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1671 queue0 = index & mask;
1672 index = index & mask;
cc41ac7c 1673 }
3be1adfb 1674
cc41ac7c
JB		 1675 rx_ring = &adapter->rx_ring[queue0];
1676
1677 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1678
1679 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1680 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1681
1682 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
32344a39
JB		 1683 u16 bufsz = IXGBE_RXBUFFER_2048;
1684 /* grow the amount we can receive on large page machines */
1685 if (bufsz < (PAGE_SIZE / 2))
1686 bufsz = (PAGE_SIZE / 2);
1687 /* cap the bufsz at our largest descriptor size */
1688 bufsz = min((u16)IXGBE_MAX_RXBUFFER, bufsz);
1689
1690 srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c
JB		 1691 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1692 srrctl |= ((IXGBE_RX_HDR_SIZE <<
b4617240
PW		 1693 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1694 IXGBE_SRRCTL_BSIZEHDR_MASK);
cc41ac7c
JB		 1695 } else {
1696 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1697
1698 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1699 srrctl |= IXGBE_RXBUFFER_2048 >>
1700 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1701 else
1702 srrctl |= rx_ring->rx_buf_len >>
1703 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1704 }
e8e26350 1705
cc41ac7c
JB		 1706 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1707}
9a799d71 1708
9a799d71 1709/**
3a581073 1710 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1711 * @adapter: board private structure
1712 *
1713 * Configure the Rx unit of the MAC after a reset.
1714 **/
1715static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1716{
1717 u64 rdba;
1718 struct ixgbe_hw *hw = &adapter->hw;
1719 struct net_device *netdev = adapter->netdev;
1720 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1721 int i, j;
9a799d71 1722 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1723 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1724 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1725 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1726 u32 fctrl, hlreg0;
509ee935 1727 u32 reta = 0, mrqc = 0;
cc41ac7c 1728 u32 rdrxctl;
7c6e0a43 1729 int rx_buf_len;
9a799d71
AK		 1730
1731 /* Decide whether to use packet split mode or not */
762f4c57 1732 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1733
1734 /* Set the RX buffer length according to the mode */
1735 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1736 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 1737 if (hw->mac.type == ixgbe_mac_82599EB) {
1738 /* PSRTYPE must be initialized in 82599 */
1739 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1740 IXGBE_PSRTYPE_UDPHDR |
1741 IXGBE_PSRTYPE_IPV4HDR |
1742 IXGBE_PSRTYPE_IPV6HDR;
1743 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1744 }
9a799d71
AK		 1745 } else {
1746 if (netdev->mtu <= ETH_DATA_LEN)
7c6e0a43 1747 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1748 else
7c6e0a43 1749 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1750 }
1751
1752 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1753 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1754 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 1755 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 1756 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1757
1758 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1759 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1760 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1761 else
1762 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1763 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1764
9a799d71
AK		 1765 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1766 /* disable receives while setting up the descriptors */
1767 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1768 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1769
1770 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1771 * the Base and Length of the Rx Descriptor Ring */
1772 for (i = 0; i < adapter->num_rx_queues; i++) {
1773 rdba = adapter->rx_ring[i].dma;
7c6e0a43
JB		 1774 j = adapter->rx_ring[i].reg_idx;
1775 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1776 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1777 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1778 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1779 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1780 adapter->rx_ring[i].head = IXGBE_RDH(j);
1781 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1782 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
cc41ac7c
JB		 1783
1784 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1785 }
1786
e8e26350
PW		 1787 if (hw->mac.type == ixgbe_mac_82598EB) {
1788 /*
1789 * For VMDq support of different descriptor types or
1790 * buffer sizes through the use of multiple SRRCTL
1791 * registers, RDRXCTL.MVMEN must be set to 1
1792 *
1793 * also, the manual doesn't mention it clearly but DCA hints
1794 * will only use queue 0's tags unless this bit is set. Side
1795 * effects of setting this bit are only that SRRCTL must be
1796 * fully programmed [0..15]
1797 */
1798 if (adapter->flags &
1799 (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED)) {
1800 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1801 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1802 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1803 }
2f90b865 1804 }
177db6ff 1805
e8e26350
PW		 1806 /* Program MRQC for the distribution of queues */
1807 if (hw->mac.type == ixgbe_mac_82599EB) {
1808 int mask = adapter->flags & (
1809 IXGBE_FLAG_RSS_ENABLED
1810 | IXGBE_FLAG_DCB_ENABLED
1811 );
1812
1813 switch (mask) {
1814 case (IXGBE_FLAG_RSS_ENABLED):
1815 mrqc = IXGBE_MRQC_RSSEN;
1816 break;
1817 case (IXGBE_FLAG_DCB_ENABLED):
1818 mrqc = IXGBE_MRQC_RT8TCEN;
1819 break;
1820 default:
1821 break;
1822 }
1823 }
021230d4 1824 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1825 /* Fill out redirection table */
021230d4
AV		 1826 for (i = 0, j = 0; i < 128; i++, j++) {
1827 if (j == adapter->ring_feature[RING_F_RSS].indices)
1828 j = 0;
1829 /* reta = 4-byte sliding window of
1830 * 0x00..(indices-1)(indices-1)00..etc. */
1831 reta = (reta << 8) | (j * 0x11);
1832 if ((i & 3) == 3)
1833 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1834 }
1835
1836 /* Fill out hash function seeds */
1837 for (i = 0; i < 10; i++)
7c6e0a43 1838 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71
AK		 1839
1840 mrqc = IXGBE_MRQC_RSSEN
1841 /* Perform hash on these packet types */
7c6e0a43
JB		 1842 | IXGBE_MRQC_RSS_FIELD_IPV4
1843 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1844 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
7c6e0a43
JB		 1845 | IXGBE_MRQC_RSS_FIELD_IPV6
1846 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
e8e26350 1847 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
9a799d71 1848 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
021230d4 1849 }
9a799d71 1850
021230d4
AV		 1851 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1852
1853 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1854 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1855 /* Disable indicating checksum in descriptor, enables
1856 * RSS hash */
9a799d71 1857 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1858 }
021230d4
AV		 1859 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1860 /* Enable IPv4 payload checksum for UDP fragments
1861 * if PCSD is not set */
1862 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1863 }
1864
1865 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 1866
1867 if (hw->mac.type == ixgbe_mac_82599EB) {
1868 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1869 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
1870 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1871 }
9a799d71
AK		 1872}
1873
068c89b0
DS		 1874static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1875{
1876 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1877 struct ixgbe_hw *hw = &adapter->hw;
1878
1879 /* add VID to filter table */
1880 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1881}
1882
1883static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1884{
1885 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1886 struct ixgbe_hw *hw = &adapter->hw;
1887
1888 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1889 ixgbe_irq_disable(adapter);
1890
1891 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1892
1893 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1894 ixgbe_irq_enable(adapter);
1895
1896 /* remove VID from filter table */
1897 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1898}
1899
9a799d71 1900static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 1901 struct vlan_group *grp)
9a799d71
AK		 1902{
1903 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1904 u32 ctrl;
e8e26350 1905 int i, j;
9a799d71 1906
d4f80882
AV		 1907 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1908 ixgbe_irq_disable(adapter);
9a799d71
AK		 1909 adapter->vlgrp = grp;
1910
2f90b865
AD		 1911 /*
1912 * For a DCB driver, always enable VLAN tag stripping so we can
1913 * still receive traffic from a DCB-enabled host even if we're
1914 * not in DCB mode.
1915 */
1916 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 1917 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1918 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1919 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1920 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1921 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1922 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 1923 /* enable VLAN tag insert/strip */
1924 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 1925 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1926 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 1927 for (i = 0; i < adapter->num_rx_queues; i++) {
1928 j = adapter->rx_ring[i].reg_idx;
1929 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
1930 ctrl |= IXGBE_RXDCTL_VME;
1931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
1932 }
9a799d71 1933 }
e8e26350 1934 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 1935
d4f80882
AV		 1936 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1937 ixgbe_irq_enable(adapter);
9a799d71
AK		 1938}
1939
9a799d71
AK		 1940static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1941{
1942 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1943
1944 if (adapter->vlgrp) {
1945 u16 vid;
1946 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1947 if (!vlan_group_get_device(adapter->vlgrp, vid))
1948 continue;
1949 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1950 }
1951 }
1952}
1953
2c5645cf
CL		 1954static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1955{
1956 struct dev_mc_list *mc_ptr;
1957 u8 *addr = *mc_addr_ptr;
1958 *vmdq = 0;
1959
1960 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1961 if (mc_ptr->next)
1962 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1963 else
1964 *mc_addr_ptr = NULL;
1965
1966 return addr;
1967}
1968
9a799d71 1969/**
2c5645cf 1970 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 1971 * @netdev: network interface device structure
1972 *
2c5645cf
CL		 1973 * The set_rx_method entry point is called whenever the unicast/multicast
1974 * address list or the network interface flags are updated. This routine is
1975 * responsible for configuring the hardware for proper unicast, multicast and
1976 * promiscuous mode.
9a799d71 1977 **/
2c5645cf 1978static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 1979{
1980 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1981 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 1982 u32 fctrl, vlnctrl;
2c5645cf
CL		 1983 u8 *addr_list = NULL;
1984 int addr_count = 0;
9a799d71
AK		 1985
1986 /* Check for Promiscuous and All Multicast modes */
1987
1988 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 1989 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 1990
1991 if (netdev->flags & IFF_PROMISC) {
2c5645cf 1992 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 1993 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 1994 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 1995 } else {
746b9f02
PM		 1996 if (netdev->flags & IFF_ALLMULTI) {
1997 fctrl |= IXGBE_FCTRL_MPE;
1998 fctrl &= ~IXGBE_FCTRL_UPE;
1999 } else {
2000 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2001 }
3d01625a 2002 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2003 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2004 }
2005
2006 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2007 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2008
2c5645cf
CL		 2009 /* reprogram secondary unicast list */
2010 addr_count = netdev->uc_count;
2011 if (addr_count)
2012 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 2013 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2014 ixgbe_addr_list_itr);
9a799d71 2015
2c5645cf
CL		 2016 /* reprogram multicast list */
2017 addr_count = netdev->mc_count;
2018 if (addr_count)
2019 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2020 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2021 ixgbe_addr_list_itr);
9a799d71
AK		 2022}
2023
021230d4
AV		 2024static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2025{
2026 int q_idx;
2027 struct ixgbe_q_vector *q_vector;
2028 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2029
2030 /* legacy and MSI only use one vector */
2031 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2032 q_vectors = 1;
2033
2034 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2035 struct napi_struct *napi;
021230d4
AV		 2036 q_vector = &adapter->q_vector[q_idx];
2037 if (!q_vector->rxr_count)
2038 continue;
f0848276
JB		 2039 napi = &q_vector->napi;
2040 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2041 (q_vector->rxr_count > 1))
2042 napi->poll = &ixgbe_clean_rxonly_many;
2043
2044 napi_enable(napi);
021230d4
AV		 2045 }
2046}
2047
2048static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2049{
2050 int q_idx;
2051 struct ixgbe_q_vector *q_vector;
2052 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2053
2054 /* legacy and MSI only use one vector */
2055 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2056 q_vectors = 1;
2057
2058 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2059 q_vector = &adapter->q_vector[q_idx];
2060 if (!q_vector->rxr_count)
2061 continue;
2062 napi_disable(&q_vector->napi);
2063 }
2064}
2065
7a6b6f51 2066#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2067/*
2068 * ixgbe_configure_dcb - Configure DCB hardware
2069 * @adapter: ixgbe adapter struct
2070 *
2071 * This is called by the driver on open to configure the DCB hardware.
2072 * This is also called by the gennetlink interface when reconfiguring
2073 * the DCB state.
2074 */
2075static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2076{
2077 struct ixgbe_hw *hw = &adapter->hw;
2078 u32 txdctl, vlnctrl;
2079 int i, j;
2080
2081 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2082 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2083 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2084
2085 /* reconfigure the hardware */
2086 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2087
2088 for (i = 0; i < adapter->num_tx_queues; i++) {
2089 j = adapter->tx_ring[i].reg_idx;
2090 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2091 /* PThresh workaround for Tx hang with DFP enabled. */
2092 txdctl |= 32;
2093 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2094 }
2095 /* Enable VLAN tag insert/strip */
2096 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2097 if (hw->mac.type == ixgbe_mac_82598EB) {
2098 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2099 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2100 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2101 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2102 vlnctrl |= IXGBE_VLNCTRL_VFE;
2103 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2104 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2105 for (i = 0; i < adapter->num_rx_queues; i++) {
2106 j = adapter->rx_ring[i].reg_idx;
2107 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2108 vlnctrl |= IXGBE_RXDCTL_VME;
2109 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2110 }
2111 }
2f90b865
AD		 2112 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2113}
2114
2115#endif
9a799d71
AK		 2116static void ixgbe_configure(struct ixgbe_adapter *adapter)
2117{
2118 struct net_device *netdev = adapter->netdev;
2119 int i;
2120
2c5645cf 2121 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2122
2123 ixgbe_restore_vlan(adapter);
7a6b6f51 2124#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2125 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2126 netif_set_gso_max_size(netdev, 32768);
2127 ixgbe_configure_dcb(adapter);
2128 } else {
2129 netif_set_gso_max_size(netdev, 65536);
2130 }
2131#else
2132 netif_set_gso_max_size(netdev, 65536);
2133#endif
9a799d71
AK		 2134
2135 ixgbe_configure_tx(adapter);
2136 ixgbe_configure_rx(adapter);
2137 for (i = 0; i < adapter->num_rx_queues; i++)
2138 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2139 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2140}
2141
e8e26350
PW		 2142static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2143{
2144 switch (hw->phy.type) {
2145 case ixgbe_phy_sfp_avago:
2146 case ixgbe_phy_sfp_ftl:
2147 case ixgbe_phy_sfp_intel:
2148 case ixgbe_phy_sfp_unknown:
2149 case ixgbe_phy_tw_tyco:
2150 case ixgbe_phy_tw_unknown:
2151 return true;
2152 default:
2153 return false;
2154 }
2155}
2156
0ecc061d 2157/**
e8e26350
PW		 2158 * ixgbe_sfp_link_config - set up SFP+ link
2159 * @adapter: pointer to private adapter struct
2160 **/
2161static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2162{
2163 struct ixgbe_hw *hw = &adapter->hw;
2164
2165 if (hw->phy.multispeed_fiber) {
2166 /*
2167 * In multispeed fiber setups, the device may not have
2168 * had a physical connection when the driver loaded.
2169 * If that's the case, the initial link configuration
2170 * couldn't get the MAC into 10G or 1G mode, so we'll
2171 * never have a link status change interrupt fire.
2172 * We need to try and force an autonegotiation
2173 * session, then bring up link.
2174 */
2175 hw->mac.ops.setup_sfp(hw);
2176 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2177 schedule_work(&adapter->multispeed_fiber_task);
2178 } else {
2179 /*
2180 * Direct Attach Cu and non-multispeed fiber modules
2181 * still need to be configured properly prior to
2182 * attempting link.
2183 */
2184 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2185 schedule_work(&adapter->sfp_config_module_task);
2186 }
2187}
2188
2189/**
2190 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2191 * @hw: pointer to private hardware struct
2192 *
2193 * Returns 0 on success, negative on failure
2194 **/
e8e26350 2195static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2196{
2197 u32 autoneg;
2198 bool link_up = false;
2199 u32 ret = IXGBE_ERR_LINK_SETUP;
2200
2201 if (hw->mac.ops.check_link)
2202 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2203
2204 if (ret)
2205 goto link_cfg_out;
2206
2207 if (hw->mac.ops.get_link_capabilities)
2208 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2209 &hw->mac.autoneg);
2210 if (ret)
2211 goto link_cfg_out;
2212
2213 if (hw->mac.ops.setup_link_speed)
2214 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
0ecc061d
PWJ		 2215link_cfg_out:
2216 return ret;
2217}
2218
e8e26350
PW		 2219#define IXGBE_MAX_RX_DESC_POLL 10
2220static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2221 int rxr)
2222{
2223 int j = adapter->rx_ring[rxr].reg_idx;
2224 int k;
2225
2226 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2227 if (IXGBE_READ_REG(&adapter->hw,
2228 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2229 break;
2230 else
2231 msleep(1);
2232 }
2233 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2234 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2235 "not set within the polling period\n", rxr);
2236 }
2237 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2238 (adapter->rx_ring[rxr].count - 1));
2239}
2240
9a799d71
AK		 2241static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2242{
2243 struct net_device *netdev = adapter->netdev;
9a799d71 2244 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2245 int i, j = 0;
e8e26350 2246 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2247 int err;
9a799d71 2248 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2249 u32 txdctl, rxdctl, mhadd;
e8e26350 2250 u32 dmatxctl;
021230d4 2251 u32 gpie;
9a799d71 2252
5eba3699
AV		 2253 ixgbe_get_hw_control(adapter);
2254
021230d4
AV		 2255 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2256 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2257 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2258 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2259 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2260 } else {
2261 /* MSI only */
021230d4 2262 gpie = 0;
9a799d71 2263 }
021230d4
AV		 2264 /* XXX: to interrupt immediately for EICS writes, enable this */
2265 /* gpie |= IXGBE_GPIE_EIMEN; */
2266 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2267 }
2268
021230d4
AV		 2269 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2270 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2271 * specifically only auto mask tx and rx interrupts */
2272 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2273 }
9a799d71 2274
0befdb3e
JB		 2275 /* Enable fan failure interrupt if media type is copper */
2276 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2277 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2278 gpie |= IXGBE_SDP1_GPIEN;
2279 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2280 }
2281
e8e26350
PW		 2282 if (hw->mac.type == ixgbe_mac_82599EB) {
2283 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2284 gpie |= IXGBE_SDP1_GPIEN;
2285 gpie |= IXGBE_SDP2_GPIEN;
2286 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2287 }
2288
021230d4 2289 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2290 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2291 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2292 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2293
2294 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2295 }
2296
2297 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2298 j = adapter->tx_ring[i].reg_idx;
2299 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2300 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2301 txdctl |= (8 << 16);
e8e26350
PW		 2302 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2303 }
2304
2305 if (hw->mac.type == ixgbe_mac_82599EB) {
2306 /* DMATXCTL.EN must be set after all Tx queue config is done */
2307 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2308 dmatxctl |= IXGBE_DMATXCTL_TE;
2309 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2310 }
2311 for (i = 0; i < adapter->num_tx_queues; i++) {
2312 j = adapter->tx_ring[i].reg_idx;
2313 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2314 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2315 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2316 }
2317
e8e26350 2318 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2319 j = adapter->rx_ring[i].reg_idx;
2320 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2321 /* enable PTHRESH=32 descriptors (half the internal cache)
2322 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2323 * this also removes a pesky rx_no_buffer_count increment */
2324 rxdctl |= 0x0020;
9a799d71 2325 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2326 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2327 if (hw->mac.type == ixgbe_mac_82599EB)
2328 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2329 }
2330 /* enable all receives */
2331 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2332 if (hw->mac.type == ixgbe_mac_82598EB)
2333 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2334 else
2335 rxdctl |= IXGBE_RXCTRL_RXEN;
2336 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2337
2338 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2339 ixgbe_configure_msix(adapter);
2340 else
2341 ixgbe_configure_msi_and_legacy(adapter);
2342
2343 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2344 ixgbe_napi_enable_all(adapter);
2345
2346 /* clear any pending interrupts, may auto mask */
2347 IXGBE_READ_REG(hw, IXGBE_EICR);
2348
9a799d71
AK		 2349 ixgbe_irq_enable(adapter);
2350
e8e26350
PW		 2351 /*
2352 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2353 * arrived before interrupts were enabled. We need to kick off
2354 * the SFP+ module setup first, then try to bring up link.
2355 * If we're not hot-pluggable SFP+, we just need to configure link
2356 * and bring it up.
2357 */
2358 err = hw->phy.ops.identify(hw);
2359 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2360 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2361 ixgbe_down(adapter);
2362 return err;
2363 }
2364
2365 if (ixgbe_is_sfp(hw)) {
2366 ixgbe_sfp_link_config(adapter);
2367 } else {
2368 err = ixgbe_non_sfp_link_config(hw);
2369 if (err)
2370 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2371 }
0ecc061d 2372
1da100bb
PWJ		 2373 /* enable transmits */
2374 netif_tx_start_all_queues(netdev);
2375
9a799d71
AK		 2376 /* bring the link up in the watchdog, this could race with our first
2377 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2378 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2379 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2380 mod_timer(&adapter->watchdog_timer, jiffies);
2381 return 0;
2382}
2383
d4f80882
AV		 2384void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2385{
2386 WARN_ON(in_interrupt());
2387 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2388 msleep(1);
2389 ixgbe_down(adapter);
2390 ixgbe_up(adapter);
2391 clear_bit(__IXGBE_RESETTING, &adapter->state);
2392}
2393
9a799d71
AK		 2394int ixgbe_up(struct ixgbe_adapter *adapter)
2395{
2396 /* hardware has been reset, we need to reload some things */
2397 ixgbe_configure(adapter);
2398
4dd64df8
JB		 2399 ixgbe_napi_add_all(adapter);
2400
9a799d71
AK		 2401 return ixgbe_up_complete(adapter);
2402}
2403
2404void ixgbe_reset(struct ixgbe_adapter *adapter)
2405{
c44ade9e
JB		 2406 struct ixgbe_hw *hw = &adapter->hw;
2407 if (hw->mac.ops.init_hw(hw))
2408 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2409
2410 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2411 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2412
2413}
2414
9a799d71
AK		 2415/**
2416 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2417 * @adapter: board private structure
2418 * @rx_ring: ring to free buffers from
2419 **/
2420static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2421 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2422{
2423 struct pci_dev *pdev = adapter->pdev;
2424 unsigned long size;
2425 unsigned int i;
2426
2427 /* Free all the Rx ring sk_buffs */
2428
2429 for (i = 0; i < rx_ring->count; i++) {
2430 struct ixgbe_rx_buffer *rx_buffer_info;
2431
2432 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2433 if (rx_buffer_info->dma) {
2434 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2435 rx_ring->rx_buf_len,
2436 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2437 rx_buffer_info->dma = 0;
2438 }
2439 if (rx_buffer_info->skb) {
2440 dev_kfree_skb(rx_buffer_info->skb);
2441 rx_buffer_info->skb = NULL;
2442 }
2443 if (!rx_buffer_info->page)
2444 continue;
762f4c57
JB		 2445 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2446 PCI_DMA_FROMDEVICE);
9a799d71 2447 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2448 put_page(rx_buffer_info->page);
2449 rx_buffer_info->page = NULL;
762f4c57 2450 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2451 }
2452
2453 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2454 memset(rx_ring->rx_buffer_info, 0, size);
2455
2456 /* Zero out the descriptor ring */
2457 memset(rx_ring->desc, 0, rx_ring->size);
2458
2459 rx_ring->next_to_clean = 0;
2460 rx_ring->next_to_use = 0;
2461
2462 writel(0, adapter->hw.hw_addr + rx_ring->head);
2463 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2464}
2465
2466/**
2467 * ixgbe_clean_tx_ring - Free Tx Buffers
2468 * @adapter: board private structure
2469 * @tx_ring: ring to be cleaned
2470 **/
2471static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2472 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2473{
2474 struct ixgbe_tx_buffer *tx_buffer_info;
2475 unsigned long size;
2476 unsigned int i;
2477
2478 /* Free all the Tx ring sk_buffs */
2479
2480 for (i = 0; i < tx_ring->count; i++) {
2481 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2482 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2483 }
2484
2485 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2486 memset(tx_ring->tx_buffer_info, 0, size);
2487
2488 /* Zero out the descriptor ring */
2489 memset(tx_ring->desc, 0, tx_ring->size);
2490
2491 tx_ring->next_to_use = 0;
2492 tx_ring->next_to_clean = 0;
2493
2494 writel(0, adapter->hw.hw_addr + tx_ring->head);
2495 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2496}
2497
2498/**
021230d4 2499 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2500 * @adapter: board private structure
2501 **/
021230d4 2502static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2503{
2504 int i;
2505
021230d4
AV		 2506 for (i = 0; i < adapter->num_rx_queues; i++)
2507 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2508}
2509
2510/**
021230d4 2511 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2512 * @adapter: board private structure
2513 **/
021230d4 2514static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2515{
2516 int i;
2517
021230d4
AV		 2518 for (i = 0; i < adapter->num_tx_queues; i++)
2519 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2520}
2521
2522void ixgbe_down(struct ixgbe_adapter *adapter)
2523{
2524 struct net_device *netdev = adapter->netdev;
7f821875 2525 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2526 u32 rxctrl;
7f821875
JB		 2527 u32 txdctl;
2528 int i, j;
9a799d71
AK		 2529
2530 /* signal that we are down to the interrupt handler */
2531 set_bit(__IXGBE_DOWN, &adapter->state);
2532
2533 /* disable receives */
7f821875
JB		 2534 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2535 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2536
2537 netif_tx_disable(netdev);
2538
7f821875 2539 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2540 msleep(10);
2541
7f821875
JB		 2542 netif_tx_stop_all_queues(netdev);
2543
9a799d71
AK		 2544 ixgbe_irq_disable(adapter);
2545
021230d4 2546 ixgbe_napi_disable_all(adapter);
7f821875 2547
9a799d71 2548 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2549 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2550
7f821875
JB		 2551 /* disable transmits in the hardware now that interrupts are off */
2552 for (i = 0; i < adapter->num_tx_queues; i++) {
2553 j = adapter->tx_ring[i].reg_idx;
2554 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2555 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2556 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2557 }
2558
9a799d71 2559 netif_carrier_off(netdev);
9a799d71 2560
5dd2d332 2561#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2562 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2563 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2564 dca_remove_requester(&adapter->pdev->dev);
2565 }
2566
2567#endif
6f4a0e45
PL		 2568 if (!pci_channel_offline(adapter->pdev))
2569 ixgbe_reset(adapter);
9a799d71
AK		 2570 ixgbe_clean_all_tx_rings(adapter);
2571 ixgbe_clean_all_rx_rings(adapter);
2572
5dd2d332 2573#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2574 /* since we reset the hardware DCA settings were cleared */
2575 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2576 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2577 /* always use CB2 mode, difference is masked
2578 * in the CB driver */
b4617240 2579 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
96b0e0f6
JB		 2580 ixgbe_setup_dca(adapter);
2581 }
2582#endif
9a799d71
AK		 2583}
2584
9a799d71 2585/**
021230d4
AV		 2586 * ixgbe_poll - NAPI Rx polling callback
2587 * @napi: structure for representing this polling device
2588 * @budget: how many packets driver is allowed to clean
2589 *
2590 * This function is used for legacy and MSI, NAPI mode
9a799d71 2591 **/
021230d4 2592static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2593{
9a1a69ad
JB		 2594 struct ixgbe_q_vector *q_vector =
2595 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2596 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2597 int tx_clean_complete, work_done = 0;
9a799d71 2598
5dd2d332 2599#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2600 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2601 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2602 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2603 }
2604#endif
2605
9a1a69ad 2606 tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
78b6f4ce 2607 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2608
9a1a69ad 2609 if (!tx_clean_complete)
d2c7ddd6
DM		 2610 work_done = budget;
2611
53e52c72
DM		 2612 /* If budget not fully consumed, exit the polling mode */
2613 if (work_done < budget) {
288379f0 2614 napi_complete(napi);
509ee935 2615 if (adapter->itr_setting & 1)
f494e8fa 2616 ixgbe_set_itr(adapter);
d4f80882
AV		 2617 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2618 ixgbe_irq_enable(adapter);
9a799d71 2619 }
9a799d71
AK		 2620 return work_done;
2621}
2622
2623/**
2624 * ixgbe_tx_timeout - Respond to a Tx Hang
2625 * @netdev: network interface device structure
2626 **/
2627static void ixgbe_tx_timeout(struct net_device *netdev)
2628{
2629 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2630
2631 /* Do the reset outside of interrupt context */
2632 schedule_work(&adapter->reset_task);
2633}
2634
2635static void ixgbe_reset_task(struct work_struct *work)
2636{
2637 struct ixgbe_adapter *adapter;
2638 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2639
2f90b865
AD		 2640 /* If we're already down or resetting, just bail */
2641 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2642 test_bit(__IXGBE_RESETTING, &adapter->state))
2643 return;
2644
9a799d71
AK		 2645 adapter->tx_timeout_count++;
2646
d4f80882 2647 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2648}
2649
bc97114d
PWJ		 2650#ifdef CONFIG_IXGBE_DCB
2651static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 2652{
bc97114d 2653 bool ret = false;
b9804972 2654
bc97114d
PWJ		 2655 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2656 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2657 adapter->num_rx_queues =
2658 adapter->ring_feature[RING_F_DCB].indices;
2659 adapter->num_tx_queues =
2660 adapter->ring_feature[RING_F_DCB].indices;
2661 ret = true;
2662 } else {
bc97114d
PWJ		 2663 ret = false;
2664 }
2f90b865 2665
bc97114d
PWJ		 2666 return ret;
2667}
2668#endif
2669
2670static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2671{
2672 bool ret = false;
2673
2674 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2675 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2676 adapter->num_rx_queues =
2677 adapter->ring_feature[RING_F_RSS].indices;
2678 adapter->num_tx_queues =
2679 adapter->ring_feature[RING_F_RSS].indices;
2680 ret = true;
2681 } else {
bc97114d 2682 ret = false;
b9804972
JB		 2683 }
2684
bc97114d
PWJ		 2685 return ret;
2686}
2687
2688static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2689{
2690 /* Start with base case */
2691 adapter->num_rx_queues = 1;
2692 adapter->num_tx_queues = 1;
2693
2694#ifdef CONFIG_IXGBE_DCB
2695 if (ixgbe_set_dcb_queues(adapter))
2696 return;
2697
2698#endif
2699 if (ixgbe_set_rss_queues(adapter))
2700 return;
b9804972
JB		 2701}
2702
021230d4 2703static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2704 int vectors)
021230d4
AV		 2705{
2706 int err, vector_threshold;
2707
2708 /* We'll want at least 3 (vector_threshold):
2709 * 1) TxQ[0] Cleanup
2710 * 2) RxQ[0] Cleanup
2711 * 3) Other (Link Status Change, etc.)
2712 * 4) TCP Timer (optional)
2713 */
2714 vector_threshold = MIN_MSIX_COUNT;
2715
2716 /* The more we get, the more we will assign to Tx/Rx Cleanup
2717 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2718 * Right now, we simply care about how many we'll get; we'll
2719 * set them up later while requesting irq's.
2720 */
2721 while (vectors >= vector_threshold) {
2722 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2723 vectors);
021230d4
AV		 2724 if (!err) /* Success in acquiring all requested vectors. */
2725 break;
2726 else if (err < 0)
2727 vectors = 0; /* Nasty failure, quit now */
2728 else /* err == number of vectors we should try again with */
2729 vectors = err;
2730 }
2731
2732 if (vectors < vector_threshold) {
2733 /* Can't allocate enough MSI-X interrupts? Oh well.
2734 * This just means we'll go with either a single MSI
2735 * vector or fall back to legacy interrupts.
2736 */
2737 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2738 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2739 kfree(adapter->msix_entries);
2740 adapter->msix_entries = NULL;
2f90b865 2741 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4 2742 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
b9804972 2743 ixgbe_set_num_queues(adapter);
021230d4
AV		 2744 } else {
2745 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 2746 /*
2747 * Adjust for only the vectors we'll use, which is minimum
2748 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2749 * vectors we were allocated.
2750 */
2751 adapter->num_msix_vectors = min(vectors,
2752 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 2753 }
2754}
2755
021230d4 2756/**
bc97114d 2757 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 2758 * @adapter: board private structure to initialize
2759 *
bc97114d
PWJ		 2760 * Cache the descriptor ring offsets for RSS to the assigned rings.
2761 *
021230d4 2762 **/
bc97114d 2763static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 2764{
bc97114d
PWJ		 2765 int i;
2766 bool ret = false;
2767
2768 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2769 for (i = 0; i < adapter->num_rx_queues; i++)
2770 adapter->rx_ring[i].reg_idx = i;
2771 for (i = 0; i < adapter->num_tx_queues; i++)
2772 adapter->tx_ring[i].reg_idx = i;
2773 ret = true;
2774 } else {
2775 ret = false;
2776 }
2777
2778 return ret;
2779}
2780
2781#ifdef CONFIG_IXGBE_DCB
2782/**
2783 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2784 * @adapter: board private structure to initialize
2785 *
2786 * Cache the descriptor ring offsets for DCB to the assigned rings.
2787 *
2788 **/
2789static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2790{
2791 int i;
2792 bool ret = false;
2793 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2794
2795 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2796 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 2797 /* the number of queues is assumed to be symmetric */
2798 for (i = 0; i < dcb_i; i++) {
2799 adapter->rx_ring[i].reg_idx = i << 3;
2800 adapter->tx_ring[i].reg_idx = i << 2;
2801 }
bc97114d 2802 ret = true;
e8e26350
PW		 2803 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2804 for (i = 0; i < dcb_i; i++) {
2805 adapter->rx_ring[i].reg_idx = i << 4;
2806 adapter->tx_ring[i].reg_idx = i << 4;
2807 }
2808 ret = true;
bc97114d
PWJ		 2809 } else {
2810 ret = false;
021230d4 2811 }
bc97114d
PWJ		 2812 } else {
2813 ret = false;
021230d4 2814 }
bc97114d
PWJ		 2815
2816 return ret;
2817}
2818#endif
2819
2820/**
2821 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2822 * @adapter: board private structure to initialize
2823 *
2824 * Once we know the feature-set enabled for the device, we'll cache
2825 * the register offset the descriptor ring is assigned to.
2826 *
2827 * Note, the order the various feature calls is important. It must start with
2828 * the "most" features enabled at the same time, then trickle down to the
2829 * least amount of features turned on at once.
2830 **/
2831static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2832{
2833 /* start with default case */
2834 adapter->rx_ring[0].reg_idx = 0;
2835 adapter->tx_ring[0].reg_idx = 0;
2836
2837#ifdef CONFIG_IXGBE_DCB
2838 if (ixgbe_cache_ring_dcb(adapter))
2839 return;
2840
2841#endif
2842 if (ixgbe_cache_ring_rss(adapter))
2843 return;
021230d4
AV		 2844}
2845
9a799d71
AK		 2846/**
2847 * ixgbe_alloc_queues - Allocate memory for all rings
2848 * @adapter: board private structure to initialize
2849 *
2850 * We allocate one ring per queue at run-time since we don't know the
a4d2f34b 2851 * number of queues at compile-time.
9a799d71 2852 **/
2f90b865 2853static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 2854{
2855 int i;
2856
2857 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 2858 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 2859 if (!adapter->tx_ring)
021230d4 2860 goto err_tx_ring_allocation;
9a799d71
AK		 2861
2862 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 2863 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 2864 if (!adapter->rx_ring)
2865 goto err_rx_ring_allocation;
9a799d71 2866
021230d4 2867 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 2868 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 2869 adapter->tx_ring[i].queue_index = i;
2870 }
b9804972 2871
9a799d71 2872 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 2873 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 2874 adapter->rx_ring[i].queue_index = i;
2875 }
2876
2877 ixgbe_cache_ring_register(adapter);
2878
2879 return 0;
2880
2881err_rx_ring_allocation:
2882 kfree(adapter->tx_ring);
2883err_tx_ring_allocation:
2884 return -ENOMEM;
2885}
2886
2887/**
2888 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2889 * @adapter: board private structure to initialize
2890 *
2891 * Attempt to configure the interrupts using the best available
2892 * capabilities of the hardware and the kernel.
2893 **/
feea6a57 2894static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 2895{
2896 int err = 0;
2897 int vector, v_budget;
2898
2899 /*
2900 * It's easy to be greedy for MSI-X vectors, but it really
2901 * doesn't do us much good if we have a lot more vectors
2902 * than CPU's. So let's be conservative and only ask for
2903 * (roughly) twice the number of vectors as there are CPU's.
2904 */
2905 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 2906 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 2907
2908 /*
2909 * At the same time, hardware can only support a maximum of
2910 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2911 * we can easily reach upwards of 64 Rx descriptor queues and
2912 * 32 Tx queues. Thus, we cap it off in those rare cases where
2913 * the cpu count also exceeds our vector limit.
2914 */
2915 v_budget = min(v_budget, MAX_MSIX_COUNT);
2916
2917 /* A failure in MSI-X entry allocation isn't fatal, but it does
2918 * mean we disable MSI-X capabilities of the adapter. */
2919 adapter->msix_entries = kcalloc(v_budget,
b4617240 2920 sizeof(struct msix_entry), GFP_KERNEL);
021230d4 2921 if (!adapter->msix_entries) {
2f90b865 2922 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4
AV		 2923 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2924 ixgbe_set_num_queues(adapter);
2925 kfree(adapter->tx_ring);
2926 kfree(adapter->rx_ring);
2927 err = ixgbe_alloc_queues(adapter);
2928 if (err) {
2929 DPRINTK(PROBE, ERR, "Unable to allocate memory "
b4617240 2930 "for queues\n");
021230d4
AV		 2931 goto out;
2932 }
2933
2934 goto try_msi;
2935 }
2936
2937 for (vector = 0; vector < v_budget; vector++)
2938 adapter->msix_entries[vector].entry = vector;
2939
2940 ixgbe_acquire_msix_vectors(adapter, v_budget);
2941
2942 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2943 goto out;
2944
2945try_msi:
2946 err = pci_enable_msi(adapter->pdev);
2947 if (!err) {
2948 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2949 } else {
2950 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 2951 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 2952 /* reset err */
2953 err = 0;
2954 }
2955
2956out:
30eba97a 2957 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 2958 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
021230d4
AV		 2959
2960 return err;
2961}
2962
2f90b865 2963void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 2964{
2965 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2966 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2967 pci_disable_msix(adapter->pdev);
2968 kfree(adapter->msix_entries);
2969 adapter->msix_entries = NULL;
2970 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2971 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2972 pci_disable_msi(adapter->pdev);
2973 }
2974 return;
2975}
2976
2977/**
2978 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2979 * @adapter: board private structure to initialize
2980 *
2981 * We determine which interrupt scheme to use based on...
2982 * - Kernel support (MSI, MSI-X)
2983 * - which can be user-defined (via MODULE_PARAM)
2984 * - Hardware queue count (num_*_queues)
2985 * - defined by miscellaneous hardware support/features (RSS, etc.)
2986 **/
2f90b865 2987int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 2988{
2989 int err;
2990
2991 /* Number of supported queues */
2992 ixgbe_set_num_queues(adapter);
2993
2994 err = ixgbe_alloc_queues(adapter);
2995 if (err) {
2996 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2997 goto err_alloc_queues;
2998 }
2999
3000 err = ixgbe_set_interrupt_capability(adapter);
3001 if (err) {
3002 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3003 goto err_set_interrupt;
9a799d71
AK		 3004 }
3005
021230d4 3006 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3007 "Tx Queue count = %u\n",
3008 (adapter->num_rx_queues > 1) ? "Enabled" :
3009 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3010
3011 set_bit(__IXGBE_DOWN, &adapter->state);
3012
9a799d71 3013 return 0;
021230d4
AV		 3014
3015err_set_interrupt:
3016 kfree(adapter->tx_ring);
3017 kfree(adapter->rx_ring);
3018err_alloc_queues:
3019 return err;
9a799d71
AK		 3020}
3021
c4900be0
DS		 3022/**
3023 * ixgbe_sfp_timer - worker thread to find a missing module
3024 * @data: pointer to our adapter struct
3025 **/
3026static void ixgbe_sfp_timer(unsigned long data)
3027{
3028 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3029
3030 /* Do the sfp_timer outside of interrupt context due to the
3031 * delays that sfp+ detection requires
3032 */
3033 schedule_work(&adapter->sfp_task);
3034}
3035
3036/**
3037 * ixgbe_sfp_task - worker thread to find a missing module
3038 * @work: pointer to work_struct containing our data
3039 **/
3040static void ixgbe_sfp_task(struct work_struct *work)
3041{
3042 struct ixgbe_adapter *adapter = container_of(work,
3043 struct ixgbe_adapter,
3044 sfp_task);
3045 struct ixgbe_hw *hw = &adapter->hw;
3046
3047 if ((hw->phy.type == ixgbe_phy_nl) &&
3048 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3049 s32 ret = hw->phy.ops.identify_sfp(hw);
3050 if (ret)
3051 goto reschedule;
3052 ret = hw->phy.ops.reset(hw);
3053 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3054 DPRINTK(PROBE, ERR, "failed to initialize because an "
3055 "unsupported SFP+ module type was detected.\n"
3056 "Reload the driver after installing a "
3057 "supported module.\n");
3058 unregister_netdev(adapter->netdev);
3059 } else {
3060 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3061 hw->phy.sfp_type);
3062 }
3063 /* don't need this routine any more */
3064 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3065 }
3066 return;
3067reschedule:
3068 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3069 mod_timer(&adapter->sfp_timer,
3070 round_jiffies(jiffies + (2 * HZ)));
3071}
3072
9a799d71
AK		 3073/**
3074 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3075 * @adapter: board private structure to initialize
3076 *
3077 * ixgbe_sw_init initializes the Adapter private data structure.
3078 * Fields are initialized based on PCI device information and
3079 * OS network device settings (MTU size).
3080 **/
3081static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3082{
3083 struct ixgbe_hw *hw = &adapter->hw;
3084 struct pci_dev *pdev = adapter->pdev;
021230d4 3085 unsigned int rss;
7a6b6f51 3086#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3087 int j;
3088 struct tc_configuration *tc;
3089#endif
021230d4 3090
c44ade9e
JB		 3091 /* PCI config space info */
3092
3093 hw->vendor_id = pdev->vendor;
3094 hw->device_id = pdev->device;
3095 hw->revision_id = pdev->revision;
3096 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3097 hw->subsystem_device_id = pdev->subsystem_device;
3098
021230d4
AV		 3099 /* Set capability flags */
3100 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3101 adapter->ring_feature[RING_F_RSS].indices = rss;
3102 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3103 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
e8e26350
PW		 3104 if (hw->mac.type == ixgbe_mac_82598EB)
3105 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3106 else if (hw->mac.type == ixgbe_mac_82599EB)
3107 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
2f90b865 3108
7a6b6f51 3109#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3110 /* Configure DCB traffic classes */
3111 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3112 tc = &adapter->dcb_cfg.tc_config[j];
3113 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3114 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3115 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3116 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3117 tc->dcb_pfc = pfc_disabled;
3118 }
3119 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3120 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3121 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3122 adapter->dcb_cfg.round_robin_enable = false;
3123 adapter->dcb_set_bitmap = 0x00;
3124 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3125 adapter->ring_feature[RING_F_DCB].indices);
3126
3127#endif
9a799d71
AK		 3128
3129 /* default flow control settings */
0ecc061d 3130 hw->fc.requested_mode = ixgbe_fc_none;
2b9ade93
JB		 3131 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3132 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3133 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3134 hw->fc.send_xon = true;
9a799d71 3135
30efa5a3
JB		 3136 /* enable itr by default in dynamic mode */
3137 adapter->itr_setting = 1;
3138 adapter->eitr_param = 20000;
3139
3140 /* set defaults for eitr in MegaBytes */
3141 adapter->eitr_low = 10;
3142 adapter->eitr_high = 20;
3143
3144 /* set default ring sizes */
3145 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3146 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3147
9a799d71 3148 /* initialize eeprom parameters */
c44ade9e 3149 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3150 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3151 return -EIO;
3152 }
3153
021230d4 3154 /* enable rx csum by default */
9a799d71
AK		 3155 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3156
9a799d71
AK		 3157 set_bit(__IXGBE_DOWN, &adapter->state);
3158
3159 return 0;
3160}
3161
3162/**
3163 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3164 * @adapter: board private structure
3a581073 3165 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3166 *
3167 * Return 0 on success, negative on failure
3168 **/
3169int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3170 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3171{
3172 struct pci_dev *pdev = adapter->pdev;
3173 int size;
3174
3a581073
JB		 3175 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3176 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3177 if (!tx_ring->tx_buffer_info)
3178 goto err;
3a581073 3179 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3180
3181 /* round up to nearest 4K */
12207e49 3182 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3183 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3184
3a581073
JB		 3185 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3186 &tx_ring->dma);
e01c31a5
JB		 3187 if (!tx_ring->desc)
3188 goto err;
9a799d71 3189
3a581073
JB		 3190 tx_ring->next_to_use = 0;
3191 tx_ring->next_to_clean = 0;
3192 tx_ring->work_limit = tx_ring->count;
9a799d71 3193 return 0;
e01c31a5
JB		 3194
3195err:
3196 vfree(tx_ring->tx_buffer_info);
3197 tx_ring->tx_buffer_info = NULL;
3198 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3199 "descriptor ring\n");
3200 return -ENOMEM;
9a799d71
AK		 3201}
3202
69888674
AD		 3203/**
3204 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3205 * @adapter: board private structure
3206 *
3207 * If this function returns with an error, then it's possible one or
3208 * more of the rings is populated (while the rest are not). It is the
3209 * callers duty to clean those orphaned rings.
3210 *
3211 * Return 0 on success, negative on failure
3212 **/
3213static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3214{
3215 int i, err = 0;
3216
3217 for (i = 0; i < adapter->num_tx_queues; i++) {
3218 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3219 if (!err)
3220 continue;
3221 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3222 break;
3223 }
3224
3225 return err;
3226}
3227
9a799d71
AK		 3228/**
3229 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3230 * @adapter: board private structure
3a581073 3231 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3232 *
3233 * Returns 0 on success, negative on failure
3234 **/
3235int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3236 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3237{
3238 struct pci_dev *pdev = adapter->pdev;
021230d4 3239 int size;
9a799d71 3240
3a581073
JB		 3241 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3242 rx_ring->rx_buffer_info = vmalloc(size);
3243 if (!rx_ring->rx_buffer_info) {
9a799d71 3244 DPRINTK(PROBE, ERR,
b4617240 3245 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3246 goto alloc_failed;
9a799d71 3247 }
3a581073 3248 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3249
9a799d71 3250 /* Round up to nearest 4K */
3a581073
JB		 3251 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3252 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3253
3a581073 3254 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3255
3a581073 3256 if (!rx_ring->desc) {
9a799d71 3257 DPRINTK(PROBE, ERR,
b4617240 3258 "Memory allocation failed for the rx desc ring\n");
3a581073 3259 vfree(rx_ring->rx_buffer_info);
177db6ff 3260 goto alloc_failed;
9a799d71
AK		 3261 }
3262
3a581073
JB		 3263 rx_ring->next_to_clean = 0;
3264 rx_ring->next_to_use = 0;
9a799d71
AK		 3265
3266 return 0;
177db6ff
MC		 3267
3268alloc_failed:
177db6ff 3269 return -ENOMEM;
9a799d71
AK		 3270}
3271
69888674
AD		 3272/**
3273 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3274 * @adapter: board private structure
3275 *
3276 * If this function returns with an error, then it's possible one or
3277 * more of the rings is populated (while the rest are not). It is the
3278 * callers duty to clean those orphaned rings.
3279 *
3280 * Return 0 on success, negative on failure
3281 **/
3282
3283static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3284{
3285 int i, err = 0;
3286
3287 for (i = 0; i < adapter->num_rx_queues; i++) {
3288 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3289 if (!err)
3290 continue;
3291 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3292 break;
3293 }
3294
3295 return err;
3296}
3297
9a799d71
AK		 3298/**
3299 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3300 * @adapter: board private structure
3301 * @tx_ring: Tx descriptor ring for a specific queue
3302 *
3303 * Free all transmit software resources
3304 **/
c431f97e
JB		 3305void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3306 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3307{
3308 struct pci_dev *pdev = adapter->pdev;
3309
3310 ixgbe_clean_tx_ring(adapter, tx_ring);
3311
3312 vfree(tx_ring->tx_buffer_info);
3313 tx_ring->tx_buffer_info = NULL;
3314
3315 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3316
3317 tx_ring->desc = NULL;
3318}
3319
3320/**
3321 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3322 * @adapter: board private structure
3323 *
3324 * Free all transmit software resources
3325 **/
3326static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3327{
3328 int i;
3329
3330 for (i = 0; i < adapter->num_tx_queues; i++)
3331 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
3332}
3333
3334/**
b4617240 3335 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 3336 * @adapter: board private structure
3337 * @rx_ring: ring to clean the resources from
3338 *
3339 * Free all receive software resources
3340 **/
c431f97e
JB		 3341void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3342 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3343{
3344 struct pci_dev *pdev = adapter->pdev;
3345
3346 ixgbe_clean_rx_ring(adapter, rx_ring);
3347
3348 vfree(rx_ring->rx_buffer_info);
3349 rx_ring->rx_buffer_info = NULL;
3350
3351 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3352
3353 rx_ring->desc = NULL;
3354}
3355
3356/**
3357 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3358 * @adapter: board private structure
3359 *
3360 * Free all receive software resources
3361 **/
3362static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3363{
3364 int i;
3365
3366 for (i = 0; i < adapter->num_rx_queues; i++)
3367 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3368}
3369
9a799d71
AK		 3370/**
3371 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3372 * @netdev: network interface device structure
3373 * @new_mtu: new value for maximum frame size
3374 *
3375 * Returns 0 on success, negative on failure
3376 **/
3377static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3378{
3379 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3380 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3381
42c783c5
JB		 3382 /* MTU < 68 is an error and causes problems on some kernels */
3383 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 3384 return -EINVAL;
3385
021230d4 3386 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 3387 netdev->mtu, new_mtu);
021230d4 3388 /* must set new MTU before calling down or up */
9a799d71
AK		 3389 netdev->mtu = new_mtu;
3390
d4f80882
AV		 3391 if (netif_running(netdev))
3392 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3393
3394 return 0;
3395}
3396
3397/**
3398 * ixgbe_open - Called when a network interface is made active
3399 * @netdev: network interface device structure
3400 *
3401 * Returns 0 on success, negative value on failure
3402 *
3403 * The open entry point is called when a network interface is made
3404 * active by the system (IFF_UP). At this point all resources needed
3405 * for transmit and receive operations are allocated, the interrupt
3406 * handler is registered with the OS, the watchdog timer is started,
3407 * and the stack is notified that the interface is ready.
3408 **/
3409static int ixgbe_open(struct net_device *netdev)
3410{
3411 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3412 int err;
4bebfaa5
AK		 3413
3414 /* disallow open during test */
3415 if (test_bit(__IXGBE_TESTING, &adapter->state))
3416 return -EBUSY;
9a799d71 3417
9a799d71
AK		 3418 /* allocate transmit descriptors */
3419 err = ixgbe_setup_all_tx_resources(adapter);
3420 if (err)
3421 goto err_setup_tx;
3422
9a799d71
AK		 3423 /* allocate receive descriptors */
3424 err = ixgbe_setup_all_rx_resources(adapter);
3425 if (err)
3426 goto err_setup_rx;
3427
3428 ixgbe_configure(adapter);
3429
4dd64df8
JB		 3430 ixgbe_napi_add_all(adapter);
3431
021230d4 3432 err = ixgbe_request_irq(adapter);
9a799d71
AK		 3433 if (err)
3434 goto err_req_irq;
3435
9a799d71
AK		 3436 err = ixgbe_up_complete(adapter);
3437 if (err)
3438 goto err_up;
3439
d55b53ff
JK		 3440 netif_tx_start_all_queues(netdev);
3441
9a799d71
AK		 3442 return 0;
3443
3444err_up:
5eba3699 3445 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3446 ixgbe_free_irq(adapter);
3447err_req_irq:
3448 ixgbe_free_all_rx_resources(adapter);
3449err_setup_rx:
3450 ixgbe_free_all_tx_resources(adapter);
3451err_setup_tx:
3452 ixgbe_reset(adapter);
3453
3454 return err;
3455}
3456
3457/**
3458 * ixgbe_close - Disables a network interface
3459 * @netdev: network interface device structure
3460 *
3461 * Returns 0, this is not allowed to fail
3462 *
3463 * The close entry point is called when an interface is de-activated
3464 * by the OS. The hardware is still under the drivers control, but
3465 * needs to be disabled. A global MAC reset is issued to stop the
3466 * hardware, and all transmit and receive resources are freed.
3467 **/
3468static int ixgbe_close(struct net_device *netdev)
3469{
3470 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 3471
3472 ixgbe_down(adapter);
3473 ixgbe_free_irq(adapter);
3474
3475 ixgbe_free_all_tx_resources(adapter);
3476 ixgbe_free_all_rx_resources(adapter);
3477
5eba3699 3478 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3479
3480 return 0;
3481}
3482
b3c8b4ba
AD		 3483/**
3484 * ixgbe_napi_add_all - prep napi structs for use
3485 * @adapter: private struct
4dd64df8 3486 *
b3c8b4ba
AD		 3487 * helper function to napi_add each possible q_vector->napi
3488 */
2f90b865 3489void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3490{
3491 int q_idx, q_vectors;
7adf1525 3492 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 3493 int (*poll)(struct napi_struct *, int);
3494
7adf1525
PWJ		 3495 /* check if we already have our netdev->napi_list populated */
3496 if (&netdev->napi_list != netdev->napi_list.next)
3497 return;
3498
b3c8b4ba
AD		 3499 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3500 poll = &ixgbe_clean_rxonly;
3501 /* Only enable as many vectors as we have rx queues. */
3502 q_vectors = adapter->num_rx_queues;
3503 } else {
3504 poll = &ixgbe_poll;
3505 /* only one q_vector for legacy modes */
3506 q_vectors = 1;
3507 }
3508
3509 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3510 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3511 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3512 }
3513}
3514
2f90b865 3515void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3516{
3517 int q_idx;
3518 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3519
3520 /* legacy and MSI only use one vector */
3521 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3522 q_vectors = 1;
3523
3524 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3525 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3526 if (!q_vector->rxr_count)
3527 continue;
3528 netif_napi_del(&q_vector->napi);
3529 }
3530}
3531
3532#ifdef CONFIG_PM
3533static int ixgbe_resume(struct pci_dev *pdev)
3534{
3535 struct net_device *netdev = pci_get_drvdata(pdev);
3536 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3537 u32 err;
3538
3539 pci_set_power_state(pdev, PCI_D0);
3540 pci_restore_state(pdev);
3541 err = pci_enable_device(pdev);
3542 if (err) {
69888674 3543 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 3544 "suspend\n");
3545 return err;
3546 }
3547 pci_set_master(pdev);
3548
3549 pci_enable_wake(pdev, PCI_D3hot, 0);
3550 pci_enable_wake(pdev, PCI_D3cold, 0);
3551
3552 err = ixgbe_init_interrupt_scheme(adapter);
3553 if (err) {
3554 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3555 "device\n");
3556 return err;
3557 }
3558
b3c8b4ba
AD		 3559 ixgbe_reset(adapter);
3560
3561 if (netif_running(netdev)) {
3562 err = ixgbe_open(adapter->netdev);
3563 if (err)
3564 return err;
3565 }
3566
3567 netif_device_attach(netdev);
3568
3569 return 0;
3570}
3571
3572#endif /* CONFIG_PM */
3573static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3574{
3575 struct net_device *netdev = pci_get_drvdata(pdev);
3576 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 3577 struct ixgbe_hw *hw = &adapter->hw;
3578 u32 ctrl, fctrl;
3579 u32 wufc = adapter->wol;
b3c8b4ba
AD		 3580#ifdef CONFIG_PM
3581 int retval = 0;
3582#endif
3583
3584 netif_device_detach(netdev);
3585
3586 if (netif_running(netdev)) {
3587 ixgbe_down(adapter);
3588 ixgbe_free_irq(adapter);
3589 ixgbe_free_all_tx_resources(adapter);
3590 ixgbe_free_all_rx_resources(adapter);
3591 }
3592 ixgbe_reset_interrupt_capability(adapter);
3593 ixgbe_napi_del_all(adapter);
7adf1525 3594 INIT_LIST_HEAD(&netdev->napi_list);
b3c8b4ba
AD		 3595 kfree(adapter->tx_ring);
3596 kfree(adapter->rx_ring);
3597
3598#ifdef CONFIG_PM
3599 retval = pci_save_state(pdev);
3600 if (retval)
3601 return retval;
3602#endif
e8e26350
PW		 3603 if (wufc) {
3604 ixgbe_set_rx_mode(netdev);
b3c8b4ba 3605
e8e26350
PW		 3606 /* turn on all-multi mode if wake on multicast is enabled */
3607 if (wufc & IXGBE_WUFC_MC) {
3608 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3609 fctrl |= IXGBE_FCTRL_MPE;
3610 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3611 }
3612
3613 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3614 ctrl |= IXGBE_CTRL_GIO_DIS;
3615 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3616
3617 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
3618 } else {
3619 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
3620 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
3621 }
3622
3623 if (wufc && hw->mac.type == ixgbe_mac_82599EB) {
3624 pci_enable_wake(pdev, PCI_D3hot, 1);
3625 pci_enable_wake(pdev, PCI_D3cold, 1);
3626 } else {
3627 pci_enable_wake(pdev, PCI_D3hot, 0);
3628 pci_enable_wake(pdev, PCI_D3cold, 0);
3629 }
b3c8b4ba
AD		 3630
3631 ixgbe_release_hw_control(adapter);
3632
3633 pci_disable_device(pdev);
3634
3635 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3636
3637 return 0;
3638}
3639
3640static void ixgbe_shutdown(struct pci_dev *pdev)
3641{
3642 ixgbe_suspend(pdev, PMSG_SUSPEND);
3643}
3644
9a799d71
AK		 3645/**
3646 * ixgbe_update_stats - Update the board statistics counters.
3647 * @adapter: board private structure
3648 **/
3649void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3650{
3651 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 3652 u64 total_mpc = 0;
3653 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 3654
d51019a4
PW		 3655 if (hw->mac.type == ixgbe_mac_82599EB) {
3656 for (i = 0; i < 16; i++)
3657 adapter->hw_rx_no_dma_resources +=
3658 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3659 }
3660
9a799d71 3661 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 3662 for (i = 0; i < 8; i++) {
3663 /* for packet buffers not used, the register should read 0 */
3664 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3665 missed_rx += mpc;
3666 adapter->stats.mpc[i] += mpc;
3667 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 3668 if (hw->mac.type == ixgbe_mac_82598EB)
3669 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 3670 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3671 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3672 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3673 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 3674 if (hw->mac.type == ixgbe_mac_82599EB) {
3675 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3676 IXGBE_PXONRXCNT(i));
3677 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3678 IXGBE_PXOFFRXCNT(i));
3679 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 3680 } else {
3681 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3682 IXGBE_PXONRXC(i));
3683 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3684 IXGBE_PXOFFRXC(i));
3685 }
2f90b865
AD		 3686 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3687 IXGBE_PXONTXC(i));
2f90b865 3688 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 3689 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 3690 }
3691 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3692 /* work around hardware counting issue */
3693 adapter->stats.gprc -= missed_rx;
3694
3695 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 3696 if (hw->mac.type == ixgbe_mac_82599EB) {
3697 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3698 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
3699 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3700 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
3701 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3702 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
3703 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3704 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3705 } else {
3706 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3707 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3708 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3709 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3710 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3711 }
9a799d71
AK		 3712 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3713 adapter->stats.bprc += bprc;
3714 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 3715 if (hw->mac.type == ixgbe_mac_82598EB)
3716 adapter->stats.mprc -= bprc;
9a799d71
AK		 3717 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3718 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3719 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3720 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3721 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3722 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3723 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 3724 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 3725 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3726 adapter->stats.lxontxc += lxon;
3727 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3728 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 3729 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3730 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 3731 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3732 /*
3733 * 82598 errata - tx of flow control packets is included in tx counters
3734 */
3735 xon_off_tot = lxon + lxoff;
3736 adapter->stats.gptc -= xon_off_tot;
3737 adapter->stats.mptc -= xon_off_tot;
3738 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 3739 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3740 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3741 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 3742 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3743 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 3744 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 3745 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3746 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3747 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3748 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3749 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 3750 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3751
3752 /* Fill out the OS statistics structure */
9a799d71
AK		 3753 adapter->net_stats.multicast = adapter->stats.mprc;
3754
3755 /* Rx Errors */
3756 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 3757 adapter->stats.rlec;
9a799d71
AK		 3758 adapter->net_stats.rx_dropped = 0;
3759 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3760 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 3761 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 3762}
3763
3764/**
3765 * ixgbe_watchdog - Timer Call-back
3766 * @data: pointer to adapter cast into an unsigned long
3767 **/
3768static void ixgbe_watchdog(unsigned long data)
3769{
3770 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 3771 struct ixgbe_hw *hw = &adapter->hw;
3772
3773 /* Do the watchdog outside of interrupt context due to the lovely
3774 * delays that some of the newer hardware requires */
3775 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3776 /* Cause software interrupt to ensure rx rings are cleaned */
3777 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3778 u32 eics =
3779 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3780 IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3781 } else {
3782 /* For legacy and MSI interrupts don't set any bits that
3783 * are enabled for EIAM, because this operation would
3784 * set *both* EIMS and EICS for any bit in EIAM */
3785 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3786 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3787 }
3788 /* Reset the timer */
3789 mod_timer(&adapter->watchdog_timer,
3790 round_jiffies(jiffies + 2 * HZ));
3791 }
9a799d71 3792
cf8280ee
JB		 3793 schedule_work(&adapter->watchdog_task);
3794}
3795
e8e26350
PW		 3796/**
3797 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
3798 * @work: pointer to work_struct containing our data
3799 **/
3800static void ixgbe_multispeed_fiber_task(struct work_struct *work)
3801{
3802 struct ixgbe_adapter *adapter = container_of(work,
3803 struct ixgbe_adapter,
3804 multispeed_fiber_task);
3805 struct ixgbe_hw *hw = &adapter->hw;
3806 u32 autoneg;
3807
3808 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
3809 if (hw->mac.ops.get_link_capabilities)
3810 hw->mac.ops.get_link_capabilities(hw, &autoneg,
3811 &hw->mac.autoneg);
3812 if (hw->mac.ops.setup_link_speed)
3813 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3814 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3815 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
3816}
3817
3818/**
3819 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
3820 * @work: pointer to work_struct containing our data
3821 **/
3822static void ixgbe_sfp_config_module_task(struct work_struct *work)
3823{
3824 struct ixgbe_adapter *adapter = container_of(work,
3825 struct ixgbe_adapter,
3826 sfp_config_module_task);
3827 struct ixgbe_hw *hw = &adapter->hw;
3828 u32 err;
3829
3830 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
3831 err = hw->phy.ops.identify_sfp(hw);
3832 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3833 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
3834 ixgbe_down(adapter);
3835 return;
3836 }
3837 hw->mac.ops.setup_sfp(hw);
3838
3839 if (!adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)
3840 /* This will also work for DA Twinax connections */
3841 schedule_work(&adapter->multispeed_fiber_task);
3842 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
3843}
3844
cf8280ee 3845/**
69888674
AD		 3846 * ixgbe_watchdog_task - worker thread to bring link up
3847 * @work: pointer to work_struct containing our data
cf8280ee
JB		 3848 **/
3849static void ixgbe_watchdog_task(struct work_struct *work)
3850{
3851 struct ixgbe_adapter *adapter = container_of(work,
3852 struct ixgbe_adapter,
3853 watchdog_task);
3854 struct net_device *netdev = adapter->netdev;
3855 struct ixgbe_hw *hw = &adapter->hw;
3856 u32 link_speed = adapter->link_speed;
3857 bool link_up = adapter->link_up;
3858
3859 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3860
3861 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3862 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3863 if (link_up ||
3864 time_after(jiffies, (adapter->link_check_timeout +
3865 IXGBE_TRY_LINK_TIMEOUT))) {
3866 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3867 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3868 }
3869 adapter->link_up = link_up;
3870 adapter->link_speed = link_speed;
3871 }
9a799d71
AK		 3872
3873 if (link_up) {
3874 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 3875 bool flow_rx, flow_tx;
3876
3877 if (hw->mac.type == ixgbe_mac_82599EB) {
3878 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3879 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3880 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
3881 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
3882 } else {
3883 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3884 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
3885 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
3886 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
3887 }
3888
a46e534b
JK		 3889 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
3890 "Flow Control: %s\n",
3891 netdev->name,
3892 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3893 "10 Gbps" :
3894 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3895 "1 Gbps" : "unknown speed")),
e8e26350
PW		 3896 ((flow_rx && flow_tx) ? "RX/TX" :
3897 (flow_rx ? "RX" :
3898 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 3899
3900 netif_carrier_on(netdev);
9a799d71
AK		 3901 } else {
3902 /* Force detection of hung controller */
3903 adapter->detect_tx_hung = true;
3904 }
3905 } else {
cf8280ee
JB		 3906 adapter->link_up = false;
3907 adapter->link_speed = 0;
9a799d71 3908 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 3909 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
3910 netdev->name);
9a799d71 3911 netif_carrier_off(netdev);
9a799d71
AK		 3912 }
3913 }
3914
3915 ixgbe_update_stats(adapter);
cf8280ee 3916 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 3917}
3918
9a799d71 3919static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 3920 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3921 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 3922{
3923 struct ixgbe_adv_tx_context_desc *context_desc;
3924 unsigned int i;
3925 int err;
3926 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 3927 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
3928 u32 mss_l4len_idx, l4len;
9a799d71
AK		 3929
3930 if (skb_is_gso(skb)) {
3931 if (skb_header_cloned(skb)) {
3932 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3933 if (err)
3934 return err;
3935 }
3936 l4len = tcp_hdrlen(skb);
3937 *hdr_len += l4len;
3938
8327d000 3939 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 3940 struct iphdr *iph = ip_hdr(skb);
3941 iph->tot_len = 0;
3942 iph->check = 0;
3943 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 3944 iph->daddr, 0,
3945 IPPROTO_TCP,
3946 0);
9a799d71
AK		 3947 adapter->hw_tso_ctxt++;
3948 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3949 ipv6_hdr(skb)->payload_len = 0;
3950 tcp_hdr(skb)->check =
3951 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 3952 &ipv6_hdr(skb)->daddr,
3953 0, IPPROTO_TCP, 0);
9a799d71
AK		 3954 adapter->hw_tso6_ctxt++;
3955 }
3956
3957 i = tx_ring->next_to_use;
3958
3959 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3960 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3961
3962 /* VLAN MACLEN IPLEN */
3963 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3964 vlan_macip_lens |=
3965 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3966 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 3967 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 3968 *hdr_len += skb_network_offset(skb);
3969 vlan_macip_lens |=
3970 (skb_transport_header(skb) - skb_network_header(skb));
3971 *hdr_len +=
3972 (skb_transport_header(skb) - skb_network_header(skb));
3973 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3974 context_desc->seqnum_seed = 0;
3975
3976 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 3977 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 3978 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 3979
8327d000 3980 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3981 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3982 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3983 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3984
3985 /* MSS L4LEN IDX */
9f8cdf4f 3986 mss_l4len_idx =
9a799d71
AK		 3987 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3988 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 3989 /* use index 1 for TSO */
3990 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 3991 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3992
3993 tx_buffer_info->time_stamp = jiffies;
3994 tx_buffer_info->next_to_watch = i;
3995
3996 i++;
3997 if (i == tx_ring->count)
3998 i = 0;
3999 tx_ring->next_to_use = i;
4000
4001 return true;
4002 }
4003 return false;
4004}
4005
4006static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4007 struct ixgbe_ring *tx_ring,
4008 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4009{
4010 struct ixgbe_adv_tx_context_desc *context_desc;
4011 unsigned int i;
4012 struct ixgbe_tx_buffer *tx_buffer_info;
4013 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4014
4015 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4016 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4017 i = tx_ring->next_to_use;
4018 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4019 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4020
4021 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4022 vlan_macip_lens |=
4023 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4024 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4025 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4026 if (skb->ip_summed == CHECKSUM_PARTIAL)
4027 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4028 skb_network_header(skb));
9a799d71
AK		 4029
4030 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4031 context_desc->seqnum_seed = 0;
4032
4033 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4034 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4035
4036 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4037 switch (skb->protocol) {
09640e63 4038 case cpu_to_be16(ETH_P_IP):
9a799d71 4039 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4040 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4041 type_tucmd_mlhl |=
b4617240 4042 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 4043 break;
09640e63 4044 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4045 /* XXX what about other V6 headers?? */
4046 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4047 type_tucmd_mlhl |=
b4617240 4048 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 4049 break;
41825d71
AK		 4050 default:
4051 if (unlikely(net_ratelimit())) {
4052 DPRINTK(PROBE, WARNING,
4053 "partial checksum but proto=%x!\n",
4054 skb->protocol);
4055 }
4056 break;
4057 }
9a799d71
AK		 4058 }
4059
4060 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4061 /* use index zero for tx checksum offload */
9a799d71
AK		 4062 context_desc->mss_l4len_idx = 0;
4063
4064 tx_buffer_info->time_stamp = jiffies;
4065 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4066
9a799d71
AK		 4067 adapter->hw_csum_tx_good++;
4068 i++;
4069 if (i == tx_ring->count)
4070 i = 0;
4071 tx_ring->next_to_use = i;
4072
4073 return true;
4074 }
9f8cdf4f 4075
9a799d71
AK		 4076 return false;
4077}
4078
4079static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240
PW		 4080 struct ixgbe_ring *tx_ring,
4081 struct sk_buff *skb, unsigned int first)
9a799d71
AK		 4082{
4083 struct ixgbe_tx_buffer *tx_buffer_info;
4084 unsigned int len = skb->len;
4085 unsigned int offset = 0, size, count = 0, i;
4086 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4087 unsigned int f;
4088
4089 len -= skb->data_len;
4090
4091 i = tx_ring->next_to_use;
4092
4093 while (len) {
4094 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4095 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4096
4097 tx_buffer_info->length = size;
4098 tx_buffer_info->dma = pci_map_single(adapter->pdev,
b4617240
PW		 4099 skb->data + offset,
4100 size, PCI_DMA_TODEVICE);
9a799d71
AK		 4101 tx_buffer_info->time_stamp = jiffies;
4102 tx_buffer_info->next_to_watch = i;
4103
4104 len -= size;
4105 offset += size;
4106 count++;
4107 i++;
4108 if (i == tx_ring->count)
4109 i = 0;
4110 }
4111
4112 for (f = 0; f < nr_frags; f++) {
4113 struct skb_frag_struct *frag;
4114
4115 frag = &skb_shinfo(skb)->frags[f];
4116 len = frag->size;
4117 offset = frag->page_offset;
4118
4119 while (len) {
4120 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4121 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4122
4123 tx_buffer_info->length = size;
4124 tx_buffer_info->dma = pci_map_page(adapter->pdev,
b4617240
PW		 4125 frag->page,
4126 offset,
4127 size,
4128 PCI_DMA_TODEVICE);
9a799d71
AK		 4129 tx_buffer_info->time_stamp = jiffies;
4130 tx_buffer_info->next_to_watch = i;
4131
4132 len -= size;
4133 offset += size;
4134 count++;
4135 i++;
4136 if (i == tx_ring->count)
4137 i = 0;
4138 }
4139 }
4140 if (i == 0)
4141 i = tx_ring->count - 1;
4142 else
4143 i = i - 1;
4144 tx_ring->tx_buffer_info[i].skb = skb;
4145 tx_ring->tx_buffer_info[first].next_to_watch = i;
4146
4147 return count;
4148}
4149
4150static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4151 struct ixgbe_ring *tx_ring,
4152 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4153{
4154 union ixgbe_adv_tx_desc *tx_desc = NULL;
4155 struct ixgbe_tx_buffer *tx_buffer_info;
4156 u32 olinfo_status = 0, cmd_type_len = 0;
4157 unsigned int i;
4158 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4159
4160 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4161
4162 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4163
4164 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4165 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4166
4167 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4168 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4169
4170 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4171 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4172
4eeae6fd
PW		 4173 /* use index 1 context for tso */
4174 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4175 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4176 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 4177 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4178
4179 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4180 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4181 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4182
4183 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4184
4185 i = tx_ring->next_to_use;
4186 while (count--) {
4187 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4188 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4189 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4190 tx_desc->read.cmd_type_len =
b4617240 4191 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 4192 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 4193 i++;
4194 if (i == tx_ring->count)
4195 i = 0;
4196 }
4197
4198 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4199
4200 /*
4201 * Force memory writes to complete before letting h/w
4202 * know there are new descriptors to fetch. (Only
4203 * applicable for weak-ordered memory model archs,
4204 * such as IA-64).
4205 */
4206 wmb();
4207
4208 tx_ring->next_to_use = i;
4209 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4210}
4211
e092be60 4212static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4213 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4214{
4215 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4216
30eba97a 4217 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4218 /* Herbert's original patch had:
4219 * smp_mb__after_netif_stop_queue();
4220 * but since that doesn't exist yet, just open code it. */
4221 smp_mb();
4222
4223 /* We need to check again in a case another CPU has just
4224 * made room available. */
4225 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4226 return -EBUSY;
4227
4228 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 4229 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4230 ++adapter->restart_queue;
4231 return 0;
4232}
4233
4234static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4235 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4236{
4237 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4238 return 0;
4239 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4240}
4241
9a799d71
AK		 4242static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4243{
4244 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4245 struct ixgbe_ring *tx_ring;
9a799d71
AK		 4246 unsigned int first;
4247 unsigned int tx_flags = 0;
30eba97a
AV		 4248 u8 hdr_len = 0;
4249 int r_idx = 0, tso;
9a799d71
AK		 4250 int count = 0;
4251 unsigned int f;
9f8cdf4f 4252
30eba97a 4253 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
30eba97a 4254 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 4255
9f8cdf4f
JB		 4256 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4257 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 4258 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4259 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4260 tx_flags |= (skb->queue_mapping << 13);
4261 }
4262 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4263 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4264 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4265 tx_flags |= (skb->queue_mapping << 13);
9f8cdf4f
JB		 4266 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4267 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 4268 }
9f8cdf4f
JB		 4269 /* three things can cause us to need a context descriptor */
4270 if (skb_is_gso(skb) ||
4271 (skb->ip_summed == CHECKSUM_PARTIAL) ||
4272 (tx_flags & IXGBE_TX_FLAGS_VLAN))
9a799d71
AK		 4273 count++;
4274
9f8cdf4f
JB		 4275 count += TXD_USE_COUNT(skb_headlen(skb));
4276 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 4277 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4278
e092be60 4279 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 4280 adapter->tx_busy++;
9a799d71
AK		 4281 return NETDEV_TX_BUSY;
4282 }
9a799d71 4283
8327d000 4284 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4285 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4286 first = tx_ring->next_to_use;
4287 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4288 if (tso < 0) {
4289 dev_kfree_skb_any(skb);
4290 return NETDEV_TX_OK;
4291 }
4292
4293 if (tso)
4294 tx_flags |= IXGBE_TX_FLAGS_TSO;
4295 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
b4617240 4296 (skb->ip_summed == CHECKSUM_PARTIAL))
9a799d71
AK		 4297 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4298
4299 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
b4617240
PW		 4300 ixgbe_tx_map(adapter, tx_ring, skb, first),
4301 skb->len, hdr_len);
9a799d71
AK		 4302
4303 netdev->trans_start = jiffies;
4304
e092be60 4305 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71
AK		 4306
4307 return NETDEV_TX_OK;
4308}
4309
4310/**
4311 * ixgbe_get_stats - Get System Network Statistics
4312 * @netdev: network interface device structure
4313 *
4314 * Returns the address of the device statistics structure.
4315 * The statistics are actually updated from the timer callback.
4316 **/
4317static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4318{
4319 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4320
4321 /* only return the current stats */
4322 return &adapter->net_stats;
4323}
4324
4325/**
4326 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4327 * @netdev: network interface device structure
4328 * @p: pointer to an address structure
4329 *
4330 * Returns 0 on success, negative on failure
4331 **/
4332static int ixgbe_set_mac(struct net_device *netdev, void *p)
4333{
4334 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 4335 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 4336 struct sockaddr *addr = p;
4337
4338 if (!is_valid_ether_addr(addr->sa_data))
4339 return -EADDRNOTAVAIL;
4340
4341 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 4342 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 4343
b4617240 4344 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 4345
4346 return 0;
4347}
4348
4349#ifdef CONFIG_NET_POLL_CONTROLLER
4350/*
4351 * Polling 'interrupt' - used by things like netconsole to send skbs
4352 * without having to re-enable interrupts. It's not called while
4353 * the interrupt routine is executing.
4354 */
4355static void ixgbe_netpoll(struct net_device *netdev)
4356{
4357 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4358
4359 disable_irq(adapter->pdev->irq);
4360 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4361 ixgbe_intr(adapter->pdev->irq, netdev);
4362 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
4363 enable_irq(adapter->pdev->irq);
4364}
4365#endif
4366
0edc3527
SH		 4367static const struct net_device_ops ixgbe_netdev_ops = {
4368 .ndo_open = ixgbe_open,
4369 .ndo_stop = ixgbe_close,
00829823 4370 .ndo_start_xmit = ixgbe_xmit_frame,
0edc3527
SH		 4371 .ndo_get_stats = ixgbe_get_stats,
4372 .ndo_set_multicast_list = ixgbe_set_rx_mode,
4373 .ndo_validate_addr = eth_validate_addr,
4374 .ndo_set_mac_address = ixgbe_set_mac,
4375 .ndo_change_mtu = ixgbe_change_mtu,
4376 .ndo_tx_timeout = ixgbe_tx_timeout,
4377 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
4378 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
4379 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
4380#ifdef CONFIG_NET_POLL_CONTROLLER
4381 .ndo_poll_controller = ixgbe_netpoll,
4382#endif
4383};
4384
9a799d71
AK		 4385/**
4386 * ixgbe_probe - Device Initialization Routine
4387 * @pdev: PCI device information struct
4388 * @ent: entry in ixgbe_pci_tbl
4389 *
4390 * Returns 0 on success, negative on failure
4391 *
4392 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
4393 * The OS initialization, configuring of the adapter private structure,
4394 * and a hardware reset occur.
4395 **/
4396static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 4397 const struct pci_device_id *ent)
9a799d71
AK		 4398{
4399 struct net_device *netdev;
4400 struct ixgbe_adapter *adapter = NULL;
4401 struct ixgbe_hw *hw;
4402 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 4403 static int cards_found;
4404 int i, err, pci_using_dac;
e8e26350 4405 u16 pm_value = 0;
c44ade9e 4406 u32 part_num, eec;
9a799d71
AK		 4407
4408 err = pci_enable_device(pdev);
4409 if (err)
4410 return err;
4411
4412 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
4413 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
4414 pci_using_dac = 1;
4415 } else {
4416 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4417 if (err) {
4418 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
4419 if (err) {
b4617240
PW		 4420 dev_err(&pdev->dev, "No usable DMA "
4421 "configuration, aborting\n");
9a799d71
AK		 4422 goto err_dma;
4423 }
4424 }
4425 pci_using_dac = 0;
4426 }
4427
4428 err = pci_request_regions(pdev, ixgbe_driver_name);
4429 if (err) {
4430 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
4431 goto err_pci_reg;
4432 }
4433
6fabd715
PWJ		 4434 err = pci_enable_pcie_error_reporting(pdev);
4435 if (err) {
4436 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4437 "0x%x\n", err);
4438 /* non-fatal, continue */
4439 }
4440
9a799d71 4441 pci_set_master(pdev);
fb3b27bc 4442 pci_save_state(pdev);
9a799d71 4443
30eba97a 4444 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 4445 if (!netdev) {
4446 err = -ENOMEM;
4447 goto err_alloc_etherdev;
4448 }
4449
9a799d71
AK		 4450 SET_NETDEV_DEV(netdev, &pdev->dev);
4451
4452 pci_set_drvdata(pdev, netdev);
4453 adapter = netdev_priv(netdev);
4454
4455 adapter->netdev = netdev;
4456 adapter->pdev = pdev;
4457 hw = &adapter->hw;
4458 hw->back = adapter;
4459 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4460
05857980
JK		 4461 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4462 pci_resource_len(pdev, 0));
9a799d71
AK		 4463 if (!hw->hw_addr) {
4464 err = -EIO;
4465 goto err_ioremap;
4466 }
4467
4468 for (i = 1; i <= 5; i++) {
4469 if (pci_resource_len(pdev, i) == 0)
4470 continue;
4471 }
4472
0edc3527 4473 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 4474 ixgbe_set_ethtool_ops(netdev);
9a799d71 4475 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 4476 strcpy(netdev->name, pci_name(pdev));
4477
9a799d71
AK		 4478 adapter->bd_number = cards_found;
4479
9a799d71
AK		 4480 /* Setup hw api */
4481 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 4482 hw->mac.type = ii->mac;
9a799d71 4483
c44ade9e
JB		 4484 /* EEPROM */
4485 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4486 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4487 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4488 if (!(eec & (1 << 8)))
4489 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4490
4491 /* PHY */
4492 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0
DS		 4493 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4494
4495 /* set up this timer and work struct before calling get_invariants
4496 * which might start the timer
4497 */
4498 init_timer(&adapter->sfp_timer);
4499 adapter->sfp_timer.function = &ixgbe_sfp_timer;
4500 adapter->sfp_timer.data = (unsigned long) adapter;
4501
4502 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 4503
e8e26350
PW		 4504 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
4505 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
4506
4507 /* a new SFP+ module arrival, called from GPI SDP2 context */
4508 INIT_WORK(&adapter->sfp_config_module_task,
4509 ixgbe_sfp_config_module_task);
4510
9a799d71 4511 err = ii->get_invariants(hw);
c4900be0
DS		 4512 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4513 /* start a kernel thread to watch for a module to arrive */
4514 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4515 mod_timer(&adapter->sfp_timer,
4516 round_jiffies(jiffies + (2 * HZ)));
4517 err = 0;
4518 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4519 DPRINTK(PROBE, ERR, "failed to load because an "
4520 "unsupported SFP+ module type was detected.\n");
9a799d71 4521 goto err_hw_init;
c4900be0
DS		 4522 } else if (err) {
4523 goto err_hw_init;
4524 }
9a799d71
AK		 4525
4526 /* setup the private structure */
4527 err = ixgbe_sw_init(adapter);
4528 if (err)
4529 goto err_sw_init;
4530
c44ade9e
JB		 4531 /* reset_hw fills in the perm_addr as well */
4532 err = hw->mac.ops.reset_hw(hw);
4533 if (err) {
4534 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4535 goto err_sw_init;
4536 }
4537
9a799d71 4538 netdev->features = NETIF_F_SG |
b4617240
PW		 4539 NETIF_F_IP_CSUM |
4540 NETIF_F_HW_VLAN_TX |
4541 NETIF_F_HW_VLAN_RX |
4542 NETIF_F_HW_VLAN_FILTER;
9a799d71 4543
e9990a9c 4544 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 4545 netdev->features |= NETIF_F_TSO;
9a799d71 4546 netdev->features |= NETIF_F_TSO6;
78b6f4ce 4547 netdev->features |= NETIF_F_GRO;
ad31c402
JK		 4548
4549 netdev->vlan_features |= NETIF_F_TSO;
4550 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 4551 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 4552 netdev->vlan_features |= NETIF_F_SG;
4553
2f90b865
AD		 4554 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4555 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4556
7a6b6f51 4557#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4558 netdev->dcbnl_ops = &dcbnl_ops;
4559#endif
4560
9a799d71
AK		 4561 if (pci_using_dac)
4562 netdev->features |= NETIF_F_HIGHDMA;
4563
9a799d71 4564 /* make sure the EEPROM is good */
c44ade9e 4565 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 4566 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4567 err = -EIO;
4568 goto err_eeprom;
4569 }
4570
4571 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4572 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4573
c44ade9e
JB		 4574 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4575 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 4576 err = -EIO;
4577 goto err_eeprom;
4578 }
4579
4580 init_timer(&adapter->watchdog_timer);
4581 adapter->watchdog_timer.function = &ixgbe_watchdog;
4582 adapter->watchdog_timer.data = (unsigned long)adapter;
4583
4584 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 4585 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 4586
021230d4
AV		 4587 err = ixgbe_init_interrupt_scheme(adapter);
4588 if (err)
4589 goto err_sw_init;
9a799d71 4590
e8e26350
PW		 4591 switch (pdev->device) {
4592 case IXGBE_DEV_ID_82599_KX4:
4593#define IXGBE_PCIE_PMCSR 0x44
4594 adapter->wol = IXGBE_WUFC_MAG;
4595 pci_read_config_word(pdev, IXGBE_PCIE_PMCSR, &pm_value);
4596 pci_write_config_word(pdev, IXGBE_PCIE_PMCSR,
4597 (pm_value | (1 << 8)));
4598 break;
4599 default:
4600 adapter->wol = 0;
4601 break;
4602 }
4603 device_init_wakeup(&adapter->pdev->dev, true);
4604 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
4605
9a799d71 4606 /* print bus type/speed/width info */
7c510e4b 4607 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 4608 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
4609 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
4610 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
4611 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
4612 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 4613 "Unknown"),
7c510e4b 4614 netdev->dev_addr);
c44ade9e 4615 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 4616 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
4617 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
4618 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
4619 (part_num >> 8), (part_num & 0xff));
4620 else
4621 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
4622 hw->mac.type, hw->phy.type,
4623 (part_num >> 8), (part_num & 0xff));
9a799d71 4624
e8e26350 4625 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 4626 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 4627 "this card is not sufficient for optimal "
4628 "performance.\n");
0c254d86 4629 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 4630 "PCI-Express slot is required.\n");
0c254d86
AK		 4631 }
4632
34b0368c
PWJ		 4633 /* save off EEPROM version number */
4634 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
4635
9a799d71 4636 /* reset the hardware with the new settings */
c44ade9e
JB		 4637 hw->mac.ops.start_hw(hw);
4638
9a799d71 4639 netif_carrier_off(netdev);
9a799d71
AK		 4640
4641 strcpy(netdev->name, "eth%d");
4642 err = register_netdev(netdev);
4643 if (err)
4644 goto err_register;
4645
5dd2d332 4646#ifdef CONFIG_IXGBE_DCA
652f093f 4647 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 4648 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4649 /* always use CB2 mode, difference is masked
4650 * in the CB driver */
4651 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4652 ixgbe_setup_dca(adapter);
4653 }
4654#endif
9a799d71
AK		 4655
4656 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4657 cards_found++;
4658 return 0;
4659
4660err_register:
5eba3699 4661 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4662err_hw_init:
4663err_sw_init:
021230d4 4664 ixgbe_reset_interrupt_capability(adapter);
9a799d71 4665err_eeprom:
c4900be0
DS		 4666 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4667 del_timer_sync(&adapter->sfp_timer);
4668 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 4669 cancel_work_sync(&adapter->multispeed_fiber_task);
4670 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 4671 iounmap(hw->hw_addr);
4672err_ioremap:
4673 free_netdev(netdev);
4674err_alloc_etherdev:
4675 pci_release_regions(pdev);
4676err_pci_reg:
4677err_dma:
4678 pci_disable_device(pdev);
4679 return err;
4680}
4681
4682/**
4683 * ixgbe_remove - Device Removal Routine
4684 * @pdev: PCI device information struct
4685 *
4686 * ixgbe_remove is called by the PCI subsystem to alert the driver
4687 * that it should release a PCI device. The could be caused by a
4688 * Hot-Plug event, or because the driver is going to be removed from
4689 * memory.
4690 **/
4691static void __devexit ixgbe_remove(struct pci_dev *pdev)
4692{
4693 struct net_device *netdev = pci_get_drvdata(pdev);
4694 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 4695 int err;
9a799d71
AK		 4696
4697 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 4698 /* clear the module not found bit to make sure the worker won't
4699 * reschedule
4700 */
4701 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 4702 del_timer_sync(&adapter->watchdog_timer);
4703
c4900be0
DS		 4704 del_timer_sync(&adapter->sfp_timer);
4705 cancel_work_sync(&adapter->watchdog_task);
4706 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 4707 cancel_work_sync(&adapter->multispeed_fiber_task);
4708 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 4709 flush_scheduled_work();
4710
5dd2d332 4711#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 4712 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4713 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4714 dca_remove_requester(&pdev->dev);
4715 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
4716 }
4717
4718#endif
c4900be0
DS		 4719 if (netdev->reg_state == NETREG_REGISTERED)
4720 unregister_netdev(netdev);
9a799d71 4721
021230d4 4722 ixgbe_reset_interrupt_capability(adapter);
5eba3699 4723
021230d4 4724 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4725
4726 iounmap(adapter->hw.hw_addr);
4727 pci_release_regions(pdev);
4728
021230d4
AV		 4729 DPRINTK(PROBE, INFO, "complete\n");
4730 kfree(adapter->tx_ring);
4731 kfree(adapter->rx_ring);
4732
9a799d71
AK		 4733 free_netdev(netdev);
4734
6fabd715
PWJ		 4735 err = pci_disable_pcie_error_reporting(pdev);
4736 if (err)
4737 dev_err(&pdev->dev,
4738 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
4739
9a799d71
AK		 4740 pci_disable_device(pdev);
4741}
4742
4743/**
4744 * ixgbe_io_error_detected - called when PCI error is detected
4745 * @pdev: Pointer to PCI device
4746 * @state: The current pci connection state
4747 *
4748 * This function is called after a PCI bus error affecting
4749 * this device has been detected.
4750 */
4751static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 4752 pci_channel_state_t state)
9a799d71
AK		 4753{
4754 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4755 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4756
4757 netif_device_detach(netdev);
4758
4759 if (netif_running(netdev))
4760 ixgbe_down(adapter);
4761 pci_disable_device(pdev);
4762
b4617240 4763 /* Request a slot reset. */
9a799d71
AK		 4764 return PCI_ERS_RESULT_NEED_RESET;
4765}
4766
4767/**
4768 * ixgbe_io_slot_reset - called after the pci bus has been reset.
4769 * @pdev: Pointer to PCI device
4770 *
4771 * Restart the card from scratch, as if from a cold-boot.
4772 */
4773static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4774{
4775 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4776 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 4777 pci_ers_result_t result;
4778 int err;
9a799d71
AK		 4779
4780 if (pci_enable_device(pdev)) {
4781 DPRINTK(PROBE, ERR,
b4617240 4782 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 4783 result = PCI_ERS_RESULT_DISCONNECT;
4784 } else {
4785 pci_set_master(pdev);
4786 pci_restore_state(pdev);
9a799d71 4787
6fabd715
PWJ		 4788 pci_enable_wake(pdev, PCI_D3hot, 0);
4789 pci_enable_wake(pdev, PCI_D3cold, 0);
9a799d71 4790
6fabd715
PWJ		 4791 ixgbe_reset(adapter);
4792
4793 result = PCI_ERS_RESULT_RECOVERED;
4794 }
4795
4796 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4797 if (err) {
4798 dev_err(&pdev->dev,
4799 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
4800 /* non-fatal, continue */
4801 }
9a799d71 4802
6fabd715 4803 return result;
9a799d71
AK		 4804}
4805
4806/**
4807 * ixgbe_io_resume - called when traffic can start flowing again.
4808 * @pdev: Pointer to PCI device
4809 *
4810 * This callback is called when the error recovery driver tells us that
4811 * its OK to resume normal operation.
4812 */
4813static void ixgbe_io_resume(struct pci_dev *pdev)
4814{
4815 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4816 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4817
4818 if (netif_running(netdev)) {
4819 if (ixgbe_up(adapter)) {
4820 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4821 return;
4822 }
4823 }
4824
4825 netif_device_attach(netdev);
9a799d71
AK		 4826}
4827
4828static struct pci_error_handlers ixgbe_err_handler = {
4829 .error_detected = ixgbe_io_error_detected,
4830 .slot_reset = ixgbe_io_slot_reset,
4831 .resume = ixgbe_io_resume,
4832};
4833
4834static struct pci_driver ixgbe_driver = {
4835 .name = ixgbe_driver_name,
4836 .id_table = ixgbe_pci_tbl,
4837 .probe = ixgbe_probe,
4838 .remove = __devexit_p(ixgbe_remove),
4839#ifdef CONFIG_PM
4840 .suspend = ixgbe_suspend,
4841 .resume = ixgbe_resume,
4842#endif
4843 .shutdown = ixgbe_shutdown,
4844 .err_handler = &ixgbe_err_handler
4845};
4846
4847/**
4848 * ixgbe_init_module - Driver Registration Routine
4849 *
4850 * ixgbe_init_module is the first routine called when the driver is
4851 * loaded. All it does is register with the PCI subsystem.
4852 **/
4853static int __init ixgbe_init_module(void)
4854{
4855 int ret;
4856 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4857 ixgbe_driver_string, ixgbe_driver_version);
4858
4859 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4860
5dd2d332 4861#ifdef CONFIG_IXGBE_DCA
bd0362dd 4862 dca_register_notify(&dca_notifier);
bd0362dd 4863#endif
5dd2d332 4864
9a799d71
AK		 4865 ret = pci_register_driver(&ixgbe_driver);
4866 return ret;
4867}
b4617240 4868
9a799d71
AK		 4869module_init(ixgbe_init_module);
4870
4871/**
4872 * ixgbe_exit_module - Driver Exit Cleanup Routine
4873 *
4874 * ixgbe_exit_module is called just before the driver is removed
4875 * from memory.
4876 **/
4877static void __exit ixgbe_exit_module(void)
4878{
5dd2d332 4879#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 4880 dca_unregister_notify(&dca_notifier);
4881#endif
9a799d71
AK		 4882 pci_unregister_driver(&ixgbe_driver);
4883}
bd0362dd 4884
5dd2d332 4885#ifdef CONFIG_IXGBE_DCA
bd0362dd 4886static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 4887 void *p)
bd0362dd
JC		 4888{
4889 int ret_val;
4890
4891 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 4892 __ixgbe_notify_dca);
bd0362dd
JC		 4893
4894 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4895}
5dd2d332 4896#endif /* CONFIG_IXGBE_DCA */
bd0362dd 4897
9a799d71
AK		 4898module_exit(ixgbe_exit_module);
4899
4900/* ixgbe_main.c */
Linux kernel - Deliverables
This page took 0.691857 seconds and 5 git commands to generate.