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ixgbe: DCB and perfect filters can coexist
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
60127865 38#include <linux/pkt_sched.h>
9a799d71 39#include <linux/ipv6.h>
5a0e3ad6 40#include <linux/slab.h>
9a799d71
AK		 41#include <net/checksum.h>
42#include <net/ip6_checksum.h>
43#include <linux/ethtool.h>
44#include <linux/if_vlan.h>
70c71606 45#include <linux/prefetch.h>
eacd73f7 46#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 47
48#include "ixgbe.h"
49#include "ixgbe_common.h"
ee5f784a 50#include "ixgbe_dcb_82599.h"
1cdd1ec8 51#include "ixgbe_sriov.h"
9a799d71
AK		 52
53char ixgbe_driver_name[] = "ixgbe";
9c8eb720 54static const char ixgbe_driver_string[] =
e8e9f696 55 "Intel(R) 10 Gigabit PCI Express Network Driver";
75e3d3c6 56#define MAJ 3
c89c7112
DS		 57#define MIN 3
58#define BUILD 8
75e3d3c6
JK		 59#define KFIX 2
60#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
61 __stringify(BUILD) "-k" __stringify(KFIX)
9c8eb720 62const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 63static const char ixgbe_copyright[] =
64 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 65
66static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 67 [board_82598] = &ixgbe_82598_info,
e8e26350 68 [board_82599] = &ixgbe_82599_info,
fe15e8e1 69 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 70};
71
72/* ixgbe_pci_tbl - PCI Device ID Table
73 *
74 * Wildcard entries (PCI_ANY_ID) should come last
75 * Last entry must be all 0s
76 *
77 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
78 * Class, Class Mask, private data (not used) }
79 */
a3aa1884 80static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 84 board_82598 },
9a799d71 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 86 board_82598 },
0befdb3e
JB		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
88 board_82598 },
3845bec0
PWJ		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
90 board_82598 },
9a799d71 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 92 board_82598 },
8d792cd9
JB		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
94 board_82598 },
c4900be0
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
96 board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
98 board_82598 },
b95f5fcb
JB		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
100 board_82598 },
c4900be0
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
102 board_82598 },
2f21bdd3
DS		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
104 board_82598 },
e8e26350
PW		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
106 board_82599 },
1fcf03e6
PWJ		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
108 board_82599 },
74757d49
DS		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
110 board_82599 },
e8e26350
PW		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
112 board_82599 },
38ad1c8e
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
114 board_82599 },
dbfec662
DS		 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
116 board_82599 },
8911184f
PWJ		 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
118 board_82599 },
dbffcb21
DS		 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
120 board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
122 board_82599 },
119fc60a
MC		 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
124 board_82599 },
312eb931
DS		 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
126 board_82599 },
b93a2226 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
d994653d 128 board_X540 },
4c40ef02
ET		 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
130 board_82599 },
4f6290cf
DS		 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
132 board_82599 },
9a799d71
AK		 133
134 /* required last entry */
135 {0, }
136};
137MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
138
5dd2d332 139#ifdef CONFIG_IXGBE_DCA
bd0362dd 140static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 141 void *p);
bd0362dd
JC		 142static struct notifier_block dca_notifier = {
143 .notifier_call = ixgbe_notify_dca,
144 .next = NULL,
145 .priority = 0
146};
147#endif
148
1cdd1ec8
GR		 149#ifdef CONFIG_PCI_IOV
150static unsigned int max_vfs;
151module_param(max_vfs, uint, 0);
e8e9f696
JP		 152MODULE_PARM_DESC(max_vfs,
153 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 154#endif /* CONFIG_PCI_IOV */
155
9a799d71
AK		 156MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
157MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
158MODULE_LICENSE("GPL");
159MODULE_VERSION(DRV_VERSION);
160
161#define DEFAULT_DEBUG_LEVEL_SHIFT 3
162
1cdd1ec8
GR		 163static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
164{
165 struct ixgbe_hw *hw = &adapter->hw;
166 u32 gcr;
167 u32 gpie;
168 u32 vmdctl;
169
170#ifdef CONFIG_PCI_IOV
171 /* disable iov and allow time for transactions to clear */
172 pci_disable_sriov(adapter->pdev);
173#endif
174
175 /* turn off device IOV mode */
176 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
177 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
178 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
179 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
180 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
181 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
182
183 /* set default pool back to 0 */
184 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
185 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
186 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
187
188 /* take a breather then clean up driver data */
189 msleep(100);
e8e9f696
JP		 190
191 kfree(adapter->vfinfo);
1cdd1ec8
GR		 192 adapter->vfinfo = NULL;
193
194 adapter->num_vfs = 0;
195 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
196}
197
7086400d
AD		 198static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
199{
200 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
202 schedule_work(&adapter->service_task);
203}
204
205static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
206{
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
208
209 /* flush memory to make sure state is correct before next watchog */
210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
212}
213
dcd79aeb
TI		 214struct ixgbe_reg_info {
215 u32 ofs;
216 char *name;
217};
218
219static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
220
221 /* General Registers */
222 {IXGBE_CTRL, "CTRL"},
223 {IXGBE_STATUS, "STATUS"},
224 {IXGBE_CTRL_EXT, "CTRL_EXT"},
225
226 /* Interrupt Registers */
227 {IXGBE_EICR, "EICR"},
228
229 /* RX Registers */
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
238
239 /* TX Registers */
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
246
247 /* List Terminator */
248 {}
249};
250
251
252/*
253 * ixgbe_regdump - register printout routine
254 */
255static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
256{
257 int i = 0, j = 0;
258 char rname[16];
259 u32 regs[64];
260
261 switch (reginfo->ofs) {
262 case IXGBE_SRRCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
265 break;
266 case IXGBE_DCA_RXCTRL(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
269 break;
270 case IXGBE_RDLEN(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
273 break;
274 case IXGBE_RDH(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
277 break;
278 case IXGBE_RDT(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
281 break;
282 case IXGBE_RXDCTL(0):
283 for (i = 0; i < 64; i++)
284 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
285 break;
286 case IXGBE_RDBAL(0):
287 for (i = 0; i < 64; i++)
288 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
289 break;
290 case IXGBE_RDBAH(0):
291 for (i = 0; i < 64; i++)
292 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
293 break;
294 case IXGBE_TDBAL(0):
295 for (i = 0; i < 64; i++)
296 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
297 break;
298 case IXGBE_TDBAH(0):
299 for (i = 0; i < 64; i++)
300 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
301 break;
302 case IXGBE_TDLEN(0):
303 for (i = 0; i < 64; i++)
304 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
305 break;
306 case IXGBE_TDH(0):
307 for (i = 0; i < 64; i++)
308 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
309 break;
310 case IXGBE_TDT(0):
311 for (i = 0; i < 64; i++)
312 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
313 break;
314 case IXGBE_TXDCTL(0):
315 for (i = 0; i < 64; i++)
316 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
317 break;
318 default:
c7689578 319 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 320 IXGBE_READ_REG(hw, reginfo->ofs));
321 return;
322 }
323
324 for (i = 0; i < 8; i++) {
325 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 326 pr_err("%-15s", rname);
dcd79aeb 327 for (j = 0; j < 8; j++)
c7689578
JP		 328 pr_cont(" %08x", regs[i*8+j]);
329 pr_cont("\n");
dcd79aeb
TI		 330 }
331
332}
333
334/*
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
336 */
337static void ixgbe_dump(struct ixgbe_adapter *adapter)
338{
339 struct net_device *netdev = adapter->netdev;
340 struct ixgbe_hw *hw = &adapter->hw;
341 struct ixgbe_reg_info *reginfo;
342 int n = 0;
343 struct ixgbe_ring *tx_ring;
344 struct ixgbe_tx_buffer *tx_buffer_info;
345 union ixgbe_adv_tx_desc *tx_desc;
346 struct my_u0 { u64 a; u64 b; } *u0;
347 struct ixgbe_ring *rx_ring;
348 union ixgbe_adv_rx_desc *rx_desc;
349 struct ixgbe_rx_buffer *rx_buffer_info;
350 u32 staterr;
351 int i = 0;
352
353 if (!netif_msg_hw(adapter))
354 return;
355
356 /* Print netdevice Info */
357 if (netdev) {
358 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 359 pr_info("Device Name state "
dcd79aeb 360 "trans_start last_rx\n");
c7689578
JP		 361 pr_info("%-15s %016lX %016lX %016lX\n",
362 netdev->name,
363 netdev->state,
364 netdev->trans_start,
365 netdev->last_rx);
dcd79aeb
TI		 366 }
367
368 /* Print Registers */
369 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 370 pr_info(" Register Name Value\n");
dcd79aeb
TI		 371 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
372 reginfo->name; reginfo++) {
373 ixgbe_regdump(hw, reginfo);
374 }
375
376 /* Print TX Ring Summary */
377 if (!netdev || !netif_running(netdev))
378 goto exit;
379
380 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 381 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 382 for (n = 0; n < adapter->num_tx_queues; n++) {
383 tx_ring = adapter->tx_ring[n];
384 tx_buffer_info =
385 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 386 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 387 n, tx_ring->next_to_use, tx_ring->next_to_clean,
388 (u64)tx_buffer_info->dma,
389 tx_buffer_info->length,
390 tx_buffer_info->next_to_watch,
391 (u64)tx_buffer_info->time_stamp);
392 }
393
394 /* Print TX Rings */
395 if (!netif_msg_tx_done(adapter))
396 goto rx_ring_summary;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
399
400 /* Transmit Descriptor Formats
401 *
402 * Advanced Transmit Descriptor
403 * +--------------------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +--------------------------------------------------------------+
406 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
407 * +--------------------------------------------------------------+
408 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
409 */
410
411 for (n = 0; n < adapter->num_tx_queues; n++) {
412 tx_ring = adapter->tx_ring[n];
c7689578
JP		 413 pr_info("------------------------------------\n");
414 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
415 pr_info("------------------------------------\n");
416 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 417 "[PlPOIdStDDt Ln] [bi->dma ] "
418 "leng ntw timestamp bi->skb\n");
419
420 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 421 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 422 tx_buffer_info = &tx_ring->tx_buffer_info[i];
423 u0 = (struct my_u0 *)tx_desc;
c7689578 424 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 425 " %04X %3X %016llX %p", i,
426 le64_to_cpu(u0->a),
427 le64_to_cpu(u0->b),
428 (u64)tx_buffer_info->dma,
429 tx_buffer_info->length,
430 tx_buffer_info->next_to_watch,
431 (u64)tx_buffer_info->time_stamp,
432 tx_buffer_info->skb);
433 if (i == tx_ring->next_to_use &&
434 i == tx_ring->next_to_clean)
c7689578 435 pr_cont(" NTC/U\n");
dcd79aeb 436 else if (i == tx_ring->next_to_use)
c7689578 437 pr_cont(" NTU\n");
dcd79aeb 438 else if (i == tx_ring->next_to_clean)
c7689578 439 pr_cont(" NTC\n");
dcd79aeb 440 else
c7689578 441 pr_cont("\n");
dcd79aeb
TI		 442
443 if (netif_msg_pktdata(adapter) &&
444 tx_buffer_info->dma != 0)
445 print_hex_dump(KERN_INFO, "",
446 DUMP_PREFIX_ADDRESS, 16, 1,
447 phys_to_virt(tx_buffer_info->dma),
448 tx_buffer_info->length, true);
449 }
450 }
451
452 /* Print RX Rings Summary */
453rx_ring_summary:
454 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 455 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 456 for (n = 0; n < adapter->num_rx_queues; n++) {
457 rx_ring = adapter->rx_ring[n];
c7689578
JP		 458 pr_info("%5d %5X %5X\n",
459 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 460 }
461
462 /* Print RX Rings */
463 if (!netif_msg_rx_status(adapter))
464 goto exit;
465
466 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
467
468 /* Advanced Receive Descriptor (Read) Format
469 * 63 1 0
470 * +-----------------------------------------------------+
471 * 0 | Packet Buffer Address [63:1] |A0/NSE|
472 * +----------------------------------------------+------+
473 * 8 | Header Buffer Address [63:1] | DD |
474 * +-----------------------------------------------------+
475 *
476 *
477 * Advanced Receive Descriptor (Write-Back) Format
478 *
479 * 63 48 47 32 31 30 21 20 16 15 4 3 0
480 * +------------------------------------------------------+
481 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
482 * | Checksum Ident | | | | Type | Type |
483 * +------------------------------------------------------+
484 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
485 * +------------------------------------------------------+
486 * 63 48 47 32 31 20 19 0
487 */
488 for (n = 0; n < adapter->num_rx_queues; n++) {
489 rx_ring = adapter->rx_ring[n];
c7689578
JP		 490 pr_info("------------------------------------\n");
491 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
492 pr_info("------------------------------------\n");
493 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 494 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
495 "<-- Adv Rx Read format\n");
c7689578 496 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 497 "[vl er S cks ln] ---------------- [bi->skb] "
498 "<-- Adv Rx Write-Back format\n");
499
500 for (i = 0; i < rx_ring->count; i++) {
501 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 502 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 503 u0 = (struct my_u0 *)rx_desc;
504 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
505 if (staterr & IXGBE_RXD_STAT_DD) {
506 /* Descriptor Done */
c7689578 507 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 508 "%016llX ---------------- %p", i,
509 le64_to_cpu(u0->a),
510 le64_to_cpu(u0->b),
511 rx_buffer_info->skb);
512 } else {
c7689578 513 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 514 "%016llX %016llX %p", i,
515 le64_to_cpu(u0->a),
516 le64_to_cpu(u0->b),
517 (u64)rx_buffer_info->dma,
518 rx_buffer_info->skb);
519
520 if (netif_msg_pktdata(adapter)) {
521 print_hex_dump(KERN_INFO, "",
522 DUMP_PREFIX_ADDRESS, 16, 1,
523 phys_to_virt(rx_buffer_info->dma),
524 rx_ring->rx_buf_len, true);
525
526 if (rx_ring->rx_buf_len
527 < IXGBE_RXBUFFER_2048)
528 print_hex_dump(KERN_INFO, "",
529 DUMP_PREFIX_ADDRESS, 16, 1,
530 phys_to_virt(
531 rx_buffer_info->page_dma +
532 rx_buffer_info->page_offset
533 ),
534 PAGE_SIZE/2, true);
535 }
536 }
537
538 if (i == rx_ring->next_to_use)
c7689578 539 pr_cont(" NTU\n");
dcd79aeb 540 else if (i == rx_ring->next_to_clean)
c7689578 541 pr_cont(" NTC\n");
dcd79aeb 542 else
c7689578 543 pr_cont("\n");
dcd79aeb
TI		 544
545 }
546 }
547
548exit:
549 return;
550}
551
5eba3699
AV		 552static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
553{
554 u32 ctrl_ext;
555
556 /* Let firmware take over control of h/w */
557 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
558 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 559 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 560}
561
562static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
563{
564 u32 ctrl_ext;
565
566 /* Let firmware know the driver has taken over */
567 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
568 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 569 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 570}
9a799d71 571
e8e26350
PW		 572/*
573 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
574 * @adapter: pointer to adapter struct
575 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
576 * @queue: queue to map the corresponding interrupt to
577 * @msix_vector: the vector to map to the corresponding queue
578 *
579 */
580static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 581 u8 queue, u8 msix_vector)
9a799d71
AK		 582{
583 u32 ivar, index;
e8e26350
PW		 584 struct ixgbe_hw *hw = &adapter->hw;
585 switch (hw->mac.type) {
586 case ixgbe_mac_82598EB:
587 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
588 if (direction == -1)
589 direction = 0;
590 index = (((direction * 64) + queue) >> 2) & 0x1F;
591 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
592 ivar &= ~(0xFF << (8 * (queue & 0x3)));
593 ivar |= (msix_vector << (8 * (queue & 0x3)));
594 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
595 break;
596 case ixgbe_mac_82599EB:
b93a2226 597 case ixgbe_mac_X540:
e8e26350
PW		 598 if (direction == -1) {
599 /* other causes */
600 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
601 index = ((queue & 1) * 8);
602 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
603 ivar &= ~(0xFF << index);
604 ivar |= (msix_vector << index);
605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
606 break;
607 } else {
608 /* tx or rx causes */
609 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
610 index = ((16 * (queue & 1)) + (8 * direction));
611 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
612 ivar &= ~(0xFF << index);
613 ivar |= (msix_vector << index);
614 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
615 break;
616 }
617 default:
618 break;
619 }
9a799d71
AK		 620}
621
fe49f04a 622static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 623 u64 qmask)
fe49f04a
AD		 624{
625 u32 mask;
626
bd508178
AD		 627 switch (adapter->hw.mac.type) {
628 case ixgbe_mac_82598EB:
fe49f04a
AD		 629 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
630 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 631 break;
632 case ixgbe_mac_82599EB:
b93a2226 633 case ixgbe_mac_X540:
fe49f04a
AD		 634 mask = (qmask & 0xFFFFFFFF);
635 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
636 mask = (qmask >> 32);
637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 638 break;
639 default:
640 break;
fe49f04a
AD		 641 }
642}
643
b6ec895e
AD		 644void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
645 struct ixgbe_tx_buffer *tx_buffer_info)
9a799d71 646{
e5a43549
AD		 647 if (tx_buffer_info->dma) {
648 if (tx_buffer_info->mapped_as_page)
b6ec895e 649 dma_unmap_page(tx_ring->dev,
e5a43549
AD		 650 tx_buffer_info->dma,
651 tx_buffer_info->length,
1b507730 652 DMA_TO_DEVICE);
e5a43549 653 else
b6ec895e 654 dma_unmap_single(tx_ring->dev,
e5a43549
AD		 655 tx_buffer_info->dma,
656 tx_buffer_info->length,
1b507730 657 DMA_TO_DEVICE);
e5a43549
AD		 658 tx_buffer_info->dma = 0;
659 }
9a799d71
AK		 660 if (tx_buffer_info->skb) {
661 dev_kfree_skb_any(tx_buffer_info->skb);
662 tx_buffer_info->skb = NULL;
663 }
44df32c5 664 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 665 /* tx_buffer_info must be completely set up in the transmit path */
666}
667
26f23d82 668/**
c84d324c
JF		 669 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
670 * @adapter: driver private struct
671 * @index: reg idx of queue to query (0-127)
26f23d82 672 *
25985edc 673 * Helper function to determine the traffic index for a particular
c84d324c 674 * register index.
26f23d82 675 *
c84d324c 676 * Returns : a tc index for use in range 0-7, or 0-3
26f23d82 677 */
3b2ee943 678static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
26f23d82 679{
c84d324c 680 int tc = -1;
e5b64635 681 int dcb_i = netdev_get_num_tc(adapter->netdev);
26f23d82 682
c84d324c
JF		 683 /* if DCB is not enabled the queues have no TC */
684 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
685 return tc;
26f23d82 686
c84d324c
JF		 687 /* check valid range */
688 if (reg_idx >= adapter->hw.mac.max_tx_queues)
689 return tc;
690
691 switch (adapter->hw.mac.type) {
692 case ixgbe_mac_82598EB:
693 tc = reg_idx >> 2;
694 break;
695 default:
696 if (dcb_i != 4 && dcb_i != 8)
6837e895 697 break;
c84d324c
JF		 698
699 /* if VMDq is enabled the lowest order bits determine TC */
700 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
701 IXGBE_FLAG_VMDQ_ENABLED)) {
702 tc = reg_idx & (dcb_i - 1);
703 break;
704 }
705
706 /*
707 * Convert the reg_idx into the correct TC. This bitmask
708 * targets the last full 32 ring traffic class and assigns
709 * it a value of 1. From there the rest of the rings are
710 * based on shifting the mask further up to include the
711 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
712 * will only ever be 8 or 4 and that reg_idx will never
713 * be greater then 128. The code without the power of 2
714 * optimizations would be:
715 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
716 */
717 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
718 tc >>= 9 - (reg_idx >> 5);
719 }
720
721 return tc;
722}
723
724static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
725{
726 struct ixgbe_hw *hw = &adapter->hw;
727 struct ixgbe_hw_stats *hwstats = &adapter->stats;
728 u32 data = 0;
729 u32 xoff[8] = {0};
730 int i;
731
732 if ((hw->fc.current_mode == ixgbe_fc_full) ||
733 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
734 switch (hw->mac.type) {
735 case ixgbe_mac_82598EB:
736 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 737 break;
738 default:
c84d324c
JF		 739 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
740 }
741 hwstats->lxoffrxc += data;
742
743 /* refill credits (no tx hang) if we received xoff */
744 if (!data)
745 return;
746
747 for (i = 0; i < adapter->num_tx_queues; i++)
748 clear_bit(__IXGBE_HANG_CHECK_ARMED,
749 &adapter->tx_ring[i]->state);
750 return;
751 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
752 return;
753
754 /* update stats for each tc, only valid with PFC enabled */
755 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
756 switch (hw->mac.type) {
757 case ixgbe_mac_82598EB:
758 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 759 break;
c84d324c
JF		 760 default:
761 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 762 }
c84d324c
JF		 763 hwstats->pxoffrxc[i] += xoff[i];
764 }
765
766 /* disarm tx queues that have received xoff frames */
767 for (i = 0; i < adapter->num_tx_queues; i++) {
768 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
769 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
770
771 if (xoff[tc])
772 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 773 }
26f23d82
YZ		 774}
775
c84d324c 776static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 777{
c84d324c
JF		 778 return ring->tx_stats.completed;
779}
780
781static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
782{
783 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 784 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 785
c84d324c
JF		 786 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
787 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
788
789 if (head != tail)
790 return (head < tail) ?
791 tail - head : (tail + ring->count - head);
792
793 return 0;
794}
795
796static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
797{
798 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
799 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
800 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
801 bool ret = false;
802
7d637bcc 803 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 804
805 /*
806 * Check for a hung queue, but be thorough. This verifies
807 * that a transmit has been completed since the previous
808 * check AND there is at least one packet pending. The
809 * ARMED bit is set to indicate a potential hang. The
810 * bit is cleared if a pause frame is received to remove
811 * false hang detection due to PFC or 802.3x frames. By
812 * requiring this to fail twice we avoid races with
813 * pfc clearing the ARMED bit and conditions where we
814 * run the check_tx_hang logic with a transmit completion
815 * pending but without time to complete it yet.
816 */
817 if ((tx_done_old == tx_done) && tx_pending) {
818 /* make sure it is true for two checks in a row */
819 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
820 &tx_ring->state);
821 } else {
822 /* update completed stats and continue */
823 tx_ring->tx_stats.tx_done_old = tx_done;
824 /* reset the countdown */
825 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 826 }
827
c84d324c 828 return ret;
9a799d71
AK		 829}
830
b4617240
PW		 831#define IXGBE_MAX_TXD_PWR 14
832#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 833
834/* Tx Descriptors needed, worst case */
835#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
836 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
837#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 838 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 839
c83c6cbd
AD		 840/**
841 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
842 * @adapter: driver private struct
843 **/
844static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
845{
846
847 /* Do the reset outside of interrupt context */
848 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
849 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
850 ixgbe_service_event_schedule(adapter);
851 }
852}
e01c31a5 853
9a799d71
AK		 854/**
855 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 856 * @q_vector: structure containing interrupt and ring information
e01c31a5 857 * @tx_ring: tx ring to clean
9a799d71 858 **/
fe49f04a 859static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 860 struct ixgbe_ring *tx_ring)
9a799d71 861{
fe49f04a 862 struct ixgbe_adapter *adapter = q_vector->adapter;
12207e49
PWJ		 863 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
864 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5 865 unsigned int total_bytes = 0, total_packets = 0;
b953799e 866 u16 i, eop, count = 0;
9a799d71
AK		 867
868 i = tx_ring->next_to_clean;
12207e49 869 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 870 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 871
872 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 873 (count < tx_ring->work_limit)) {
12207e49 874 bool cleaned = false;
2d0bb1c1 875 rmb(); /* read buffer_info after eop_desc */
12207e49 876 for ( ; !cleaned; count++) {
31f05a2d 877 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 878 tx_buffer_info = &tx_ring->tx_buffer_info[i];
8ad494b0
AD		 879
880 tx_desc->wb.status = 0;
12207e49 881 cleaned = (i == eop);
9a799d71 882
8ad494b0
AD		 883 i++;
884 if (i == tx_ring->count)
885 i = 0;
e01c31a5 886
8ad494b0
AD		 887 if (cleaned && tx_buffer_info->skb) {
888 total_bytes += tx_buffer_info->bytecount;
889 total_packets += tx_buffer_info->gso_segs;
e092be60 890 }
e01c31a5 891
b6ec895e 892 ixgbe_unmap_and_free_tx_resource(tx_ring,
e8e9f696 893 tx_buffer_info);
e01c31a5 894 }
12207e49 895
c84d324c 896 tx_ring->tx_stats.completed++;
12207e49 897 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 898 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 899 }
900
9a799d71 901 tx_ring->next_to_clean = i;
b953799e
AD		 902 tx_ring->total_bytes += total_bytes;
903 tx_ring->total_packets += total_packets;
904 u64_stats_update_begin(&tx_ring->syncp);
905 tx_ring->stats.packets += total_packets;
906 tx_ring->stats.bytes += total_bytes;
907 u64_stats_update_end(&tx_ring->syncp);
908
c84d324c
JF		 909 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
910 /* schedule immediate reset if we believe we hung */
911 struct ixgbe_hw *hw = &adapter->hw;
912 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
913 e_err(drv, "Detected Tx Unit Hang\n"
914 " Tx Queue <%d>\n"
915 " TDH, TDT <%x>, <%x>\n"
916 " next_to_use <%x>\n"
917 " next_to_clean <%x>\n"
918 "tx_buffer_info[next_to_clean]\n"
919 " time_stamp <%lx>\n"
920 " jiffies <%lx>\n",
921 tx_ring->queue_index,
922 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
923 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
924 tx_ring->next_to_use, eop,
925 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
926
927 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
928
929 e_info(probe,
930 "tx hang %d detected on queue %d, resetting adapter\n",
931 adapter->tx_timeout_count + 1, tx_ring->queue_index);
932
b953799e 933 /* schedule immediate reset if we believe we hung */
c83c6cbd 934 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 935
936 /* the adapter is about to reset, no point in enabling stuff */
937 return true;
938 }
9a799d71 939
e092be60 940#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
fc77dc3c 941 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
e8e9f696 942 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 943 /* Make sure that anybody stopping the queue after this
944 * sees the new next_to_clean.
945 */
946 smp_mb();
fc77dc3c 947 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 948 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 949 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 950 ++tx_ring->tx_stats.restart_queue;
30eba97a 951 }
e092be60 952 }
9a799d71 953
807540ba 954 return count < tx_ring->work_limit;
9a799d71
AK		 955}
956
5dd2d332 957#ifdef CONFIG_IXGBE_DCA
bd0362dd 958static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 959 struct ixgbe_ring *rx_ring,
960 int cpu)
bd0362dd 961{
33cf09c9 962 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 963 u32 rxctrl;
33cf09c9
AD		 964 u8 reg_idx = rx_ring->reg_idx;
965
966 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
967 switch (hw->mac.type) {
968 case ixgbe_mac_82598EB:
969 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
970 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
971 break;
972 case ixgbe_mac_82599EB:
b93a2226 973 case ixgbe_mac_X540:
33cf09c9
AD		 974 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
975 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
976 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
977 break;
978 default:
979 break;
bd0362dd 980 }
33cf09c9
AD		 981 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
982 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
983 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 984 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 985}
986
987static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 988 struct ixgbe_ring *tx_ring,
989 int cpu)
bd0362dd 990{
33cf09c9 991 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 992 u32 txctrl;
33cf09c9
AD		 993 u8 reg_idx = tx_ring->reg_idx;
994
995 switch (hw->mac.type) {
996 case ixgbe_mac_82598EB:
997 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
998 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
999 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
1000 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 1001 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
1002 break;
1003 case ixgbe_mac_82599EB:
b93a2226 1004 case ixgbe_mac_X540:
33cf09c9
AD		 1005 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
1006 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
1007 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
1008 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
1009 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 1010 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
1011 break;
1012 default:
1013 break;
1014 }
1015}
1016
1017static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1018{
1019 struct ixgbe_adapter *adapter = q_vector->adapter;
bd0362dd 1020 int cpu = get_cpu();
33cf09c9
AD		 1021 long r_idx;
1022 int i;
bd0362dd 1023
33cf09c9
AD		 1024 if (q_vector->cpu == cpu)
1025 goto out_no_update;
1026
1027 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1028 for (i = 0; i < q_vector->txr_count; i++) {
1029 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
1030 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1031 r_idx + 1);
bd0362dd 1032 }
33cf09c9
AD		 1033
1034 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1035 for (i = 0; i < q_vector->rxr_count; i++) {
1036 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1037 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1038 r_idx + 1);
1039 }
1040
1041 q_vector->cpu = cpu;
1042out_no_update:
bd0362dd
JC		 1043 put_cpu();
1044}
1045
1046static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1047{
33cf09c9 1048 int num_q_vectors;
bd0362dd
JC		 1049 int i;
1050
1051 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1052 return;
1053
e35ec126
AD		 1054 /* always use CB2 mode, difference is masked in the CB driver */
1055 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1056
33cf09c9
AD		 1057 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1058 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1059 else
1060 num_q_vectors = 1;
1061
1062 for (i = 0; i < num_q_vectors; i++) {
1063 adapter->q_vector[i]->cpu = -1;
1064 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1065 }
1066}
1067
1068static int __ixgbe_notify_dca(struct device *dev, void *data)
1069{
c60fbb00 1070 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1071 unsigned long event = *(unsigned long *)data;
1072
33cf09c9
AD		 1073 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1074 return 0;
1075
bd0362dd
JC		 1076 switch (event) {
1077 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1078 /* if we're already enabled, don't do it again */
1079 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1080 break;
652f093f 1081 if (dca_add_requester(dev) == 0) {
96b0e0f6 1082 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1083 ixgbe_setup_dca(adapter);
1084 break;
1085 }
1086 /* Fall Through since DCA is disabled. */
1087 case DCA_PROVIDER_REMOVE:
1088 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1089 dca_remove_requester(dev);
1090 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1091 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1092 }
1093 break;
1094 }
1095
652f093f 1096 return 0;
bd0362dd 1097}
5dd2d332 1098#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 1099
1100static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1101 struct sk_buff *skb)
1102{
1103 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1104}
1105
9a799d71
AK		 1106/**
1107 * ixgbe_receive_skb - Send a completed packet up the stack
1108 * @adapter: board private structure
1109 * @skb: packet to send up
177db6ff
MC		 1110 * @status: hardware indication of status of receive
1111 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1112 * @rx_desc: rx descriptor
9a799d71 1113 **/
78b6f4ce 1114static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1115 struct sk_buff *skb, u8 status,
1116 struct ixgbe_ring *ring,
1117 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1118{
78b6f4ce
HX		 1119 struct ixgbe_adapter *adapter = q_vector->adapter;
1120 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1121 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1122 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1123
f62bbb5e
JG		 1124 if (is_vlan && (tag & VLAN_VID_MASK))
1125 __vlan_hwaccel_put_tag(skb, tag);
1126
1127 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1128 napi_gro_receive(napi, skb);
1129 else
1130 netif_rx(skb);
9a799d71
AK		 1131}
1132
e59bd25d
AV		 1133/**
1134 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1135 * @adapter: address of board private structure
1136 * @status_err: hardware indication of status of receive
1137 * @skb: skb currently being received and modified
1138 **/
9a799d71 1139static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 1140 union ixgbe_adv_rx_desc *rx_desc,
1141 struct sk_buff *skb)
9a799d71 1142{
8bae1b2b
DS		 1143 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1144
bc8acf2c 1145 skb_checksum_none_assert(skb);
9a799d71 1146
712744be
JB		 1147 /* Rx csum disabled */
1148 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1149 return;
e59bd25d
AV		 1150
1151 /* if IP and error */
1152 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1153 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1154 adapter->hw_csum_rx_error++;
1155 return;
1156 }
e59bd25d
AV		 1157
1158 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1159 return;
1160
1161 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1162 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1163
1164 /*
1165 * 82599 errata, UDP frames with a 0 checksum can be marked as
1166 * checksum errors.
1167 */
1168 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1169 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1170 return;
1171
e59bd25d
AV		 1172 adapter->hw_csum_rx_error++;
1173 return;
1174 }
1175
9a799d71 1176 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1177 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1178}
1179
84ea2591 1180static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1181{
1182 /*
1183 * Force memory writes to complete before letting h/w
1184 * know there are new descriptors to fetch. (Only
1185 * applicable for weak-ordered memory model archs,
1186 * such as IA-64).
1187 */
1188 wmb();
84ea2591 1189 writel(val, rx_ring->tail);
e8e26350
PW		 1190}
1191
9a799d71
AK		 1192/**
1193 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1194 * @rx_ring: ring to place buffers on
1195 * @cleaned_count: number of buffers to replace
9a799d71 1196 **/
fc77dc3c 1197void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1198{
9a799d71 1199 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1200 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1201 struct sk_buff *skb;
1202 u16 i = rx_ring->next_to_use;
9a799d71 1203
fc77dc3c
AD		 1204 /* do nothing if no valid netdev defined */
1205 if (!rx_ring->netdev)
1206 return;
1207
9a799d71 1208 while (cleaned_count--) {
31f05a2d 1209 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1210 bi = &rx_ring->rx_buffer_info[i];
1211 skb = bi->skb;
9a799d71 1212
d5f398ed 1213 if (!skb) {
fc77dc3c 1214 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1215 rx_ring->rx_buf_len);
9a799d71 1216 if (!skb) {
5b7da515 1217 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1218 goto no_buffers;
1219 }
d716a7d8
AD		 1220 /* initialize queue mapping */
1221 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1222 bi->skb = skb;
d716a7d8 1223 }
9a799d71 1224
d716a7d8 1225 if (!bi->dma) {
b6ec895e 1226 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1227 skb->data,
e8e9f696 1228 rx_ring->rx_buf_len,
1b507730 1229 DMA_FROM_DEVICE);
b6ec895e 1230 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1231 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1232 bi->dma = 0;
1233 goto no_buffers;
1234 }
9a799d71 1235 }
d5f398ed 1236
7d637bcc 1237 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1238 if (!bi->page) {
fc77dc3c 1239 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1240 if (!bi->page) {
5b7da515 1241 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1242 goto no_buffers;
1243 }
1244 }
1245
1246 if (!bi->page_dma) {
1247 /* use a half page if we're re-using */
1248 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1249 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1250 bi->page,
1251 bi->page_offset,
1252 PAGE_SIZE / 2,
1253 DMA_FROM_DEVICE);
b6ec895e 1254 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1255 bi->page_dma)) {
5b7da515 1256 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1257 bi->page_dma = 0;
1258 goto no_buffers;
1259 }
1260 }
1261
1262 /* Refresh the desc even if buffer_addrs didn't change
1263 * because each write-back erases this info. */
3a581073
JB		 1264 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1265 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1266 } else {
3a581073 1267 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1268 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1269 }
1270
1271 i++;
1272 if (i == rx_ring->count)
1273 i = 0;
9a799d71 1274 }
7c6e0a43 1275
9a799d71
AK		 1276no_buffers:
1277 if (rx_ring->next_to_use != i) {
1278 rx_ring->next_to_use = i;
84ea2591 1279 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1280 }
1281}
1282
c267fc16 1283static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1284{
c267fc16
AD		 1285 /* HW will not DMA in data larger than the given buffer, even if it
1286 * parses the (NFS, of course) header to be larger. In that case, it
1287 * fills the header buffer and spills the rest into the page.
1288 */
1289 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1290 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1291 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1292 if (hlen > IXGBE_RX_HDR_SIZE)
1293 hlen = IXGBE_RX_HDR_SIZE;
1294 return hlen;
7c6e0a43
JB		 1295}
1296
f8212f97
AD		 1297/**
1298 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1299 * @skb: pointer to the last skb in the rsc queue
1300 *
1301 * This function changes a queue full of hw rsc buffers into a completed
1302 * packet. It uses the ->prev pointers to find the first packet and then
1303 * turns it into the frag list owner.
1304 **/
aa80175a 1305static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1306{
1307 unsigned int frag_list_size = 0;
aa80175a 1308 unsigned int skb_cnt = 1;
f8212f97
AD		 1309
1310 while (skb->prev) {
1311 struct sk_buff *prev = skb->prev;
1312 frag_list_size += skb->len;
1313 skb->prev = NULL;
1314 skb = prev;
aa80175a 1315 skb_cnt++;
f8212f97
AD		 1316 }
1317
1318 skb_shinfo(skb)->frag_list = skb->next;
1319 skb->next = NULL;
1320 skb->len += frag_list_size;
1321 skb->data_len += frag_list_size;
1322 skb->truesize += frag_list_size;
aa80175a
AD		 1323 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1324
f8212f97
AD		 1325 return skb;
1326}
1327
aa80175a
AD		 1328static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1329{
1330 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1331 IXGBE_RXDADV_RSCCNT_MASK);
1332}
43634e82 1333
c267fc16 1334static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1335 struct ixgbe_ring *rx_ring,
1336 int *work_done, int work_to_do)
9a799d71 1337{
78b6f4ce 1338 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1339 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1340 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1341 struct sk_buff *skb;
d2f4fbe2 1342 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1343 const int current_node = numa_node_id();
3d8fd385
YZ		 1344#ifdef IXGBE_FCOE
1345 int ddp_bytes = 0;
1346#endif /* IXGBE_FCOE */
c267fc16
AD		 1347 u32 staterr;
1348 u16 i;
1349 u16 cleaned_count = 0;
aa80175a 1350 bool pkt_is_rsc = false;
9a799d71
AK		 1351
1352 i = rx_ring->next_to_clean;
31f05a2d 1353 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1354 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1355
1356 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1357 u32 upper_len = 0;
9a799d71 1358
3c945e5b 1359 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1360
c267fc16
AD		 1361 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1362
9a799d71 1363 skb = rx_buffer_info->skb;
9a799d71 1364 rx_buffer_info->skb = NULL;
c267fc16 1365 prefetch(skb->data);
9a799d71 1366
c267fc16 1367 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1368 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16
AD		 1369
1370 /* if this is a skb from previous receive DMA will be 0 */
21fa4e66 1371 if (rx_buffer_info->dma) {
c267fc16 1372 u16 hlen;
aa80175a 1373 if (pkt_is_rsc &&
c267fc16
AD		 1374 !(staterr & IXGBE_RXD_STAT_EOP) &&
1375 !skb->prev) {
43634e82
MC		 1376 /*
1377 * When HWRSC is enabled, delay unmapping
1378 * of the first packet. It carries the
1379 * header information, HW may still
1380 * access the header after the writeback.
1381 * Only unmap it when EOP is reached
1382 */
e8171aaa 1383 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1384 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1385 } else {
b6ec895e 1386 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1387 rx_buffer_info->dma,
1388 rx_ring->rx_buf_len,
1389 DMA_FROM_DEVICE);
e8171aaa 1390 }
4f57ca6e 1391 rx_buffer_info->dma = 0;
c267fc16
AD		 1392
1393 if (ring_is_ps_enabled(rx_ring)) {
1394 hlen = ixgbe_get_hlen(rx_desc);
1395 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1396 } else {
1397 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1398 }
1399
1400 skb_put(skb, hlen);
1401 } else {
1402 /* assume packet split since header is unmapped */
1403 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1404 }
1405
1406 if (upper_len) {
b6ec895e
AD		 1407 dma_unmap_page(rx_ring->dev,
1408 rx_buffer_info->page_dma,
1409 PAGE_SIZE / 2,
1410 DMA_FROM_DEVICE);
9a799d71
AK		 1411 rx_buffer_info->page_dma = 0;
1412 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1413 rx_buffer_info->page,
1414 rx_buffer_info->page_offset,
1415 upper_len);
762f4c57 1416
c267fc16
AD		 1417 if ((page_count(rx_buffer_info->page) == 1) &&
1418 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1419 get_page(rx_buffer_info->page);
c267fc16
AD		 1420 else
1421 rx_buffer_info->page = NULL;
9a799d71
AK		 1422
1423 skb->len += upper_len;
1424 skb->data_len += upper_len;
1425 skb->truesize += upper_len;
1426 }
1427
1428 i++;
1429 if (i == rx_ring->count)
1430 i = 0;
9a799d71 1431
31f05a2d 1432 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1433 prefetch(next_rxd);
9a799d71 1434 cleaned_count++;
f8212f97 1435
aa80175a 1436 if (pkt_is_rsc) {
f8212f97
AD		 1437 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1438 IXGBE_RXDADV_NEXTP_SHIFT;
1439 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1440 } else {
1441 next_buffer = &rx_ring->rx_buffer_info[i];
1442 }
1443
c267fc16 1444 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1445 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1446 rx_buffer_info->skb = next_buffer->skb;
1447 rx_buffer_info->dma = next_buffer->dma;
1448 next_buffer->skb = skb;
1449 next_buffer->dma = 0;
1450 } else {
1451 skb->next = next_buffer->skb;
1452 skb->next->prev = skb;
1453 }
5b7da515 1454 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1455 goto next_desc;
1456 }
1457
aa80175a
AD		 1458 if (skb->prev) {
1459 skb = ixgbe_transform_rsc_queue(skb);
1460 /* if we got here without RSC the packet is invalid */
1461 if (!pkt_is_rsc) {
1462 __pskb_trim(skb, 0);
1463 rx_buffer_info->skb = skb;
1464 goto next_desc;
1465 }
1466 }
c267fc16
AD		 1467
1468 if (ring_is_rsc_enabled(rx_ring)) {
1469 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1470 dma_unmap_single(rx_ring->dev,
1471 IXGBE_RSC_CB(skb)->dma,
1472 rx_ring->rx_buf_len,
1473 DMA_FROM_DEVICE);
1474 IXGBE_RSC_CB(skb)->dma = 0;
1475 IXGBE_RSC_CB(skb)->delay_unmap = false;
1476 }
aa80175a
AD		 1477 }
1478 if (pkt_is_rsc) {
c267fc16
AD		 1479 if (ring_is_ps_enabled(rx_ring))
1480 rx_ring->rx_stats.rsc_count +=
aa80175a 1481 skb_shinfo(skb)->nr_frags;
c267fc16 1482 else
aa80175a
AD		 1483 rx_ring->rx_stats.rsc_count +=
1484 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1485 rx_ring->rx_stats.rsc_flush++;
1486 }
1487
1488 /* ERR_MASK will only have valid bits if EOP set */
9a799d71 1489 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
c267fc16
AD		 1490 /* trim packet back to size 0 and recycle it */
1491 __pskb_trim(skb, 0);
1492 rx_buffer_info->skb = skb;
9a799d71
AK		 1493 goto next_desc;
1494 }
1495
8bae1b2b 1496 ixgbe_rx_checksum(adapter, rx_desc, skb);
67a74ee2
ET		 1497 if (adapter->netdev->features & NETIF_F_RXHASH)
1498 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1499
1500 /* probably a little skewed due to removing CRC */
1501 total_rx_bytes += skb->len;
1502 total_rx_packets++;
1503
fc77dc3c 1504 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1505#ifdef IXGBE_FCOE
1506 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1507 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1508 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1509 if (!ddp_bytes)
332d4a7d 1510 goto next_desc;
3d8fd385 1511 }
332d4a7d 1512#endif /* IXGBE_FCOE */
fdaff1ce 1513 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1514
1515next_desc:
1516 rx_desc->wb.upper.status_error = 0;
1517
c267fc16
AD		 1518 (*work_done)++;
1519 if (*work_done >= work_to_do)
1520 break;
1521
9a799d71
AK		 1522 /* return some buffers to hardware, one at a time is too slow */
1523 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1524 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1525 cleaned_count = 0;
1526 }
1527
1528 /* use prefetched values */
1529 rx_desc = next_rxd;
9a799d71 1530 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1531 }
1532
9a799d71
AK		 1533 rx_ring->next_to_clean = i;
1534 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1535
1536 if (cleaned_count)
fc77dc3c 1537 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1538
3d8fd385
YZ		 1539#ifdef IXGBE_FCOE
1540 /* include DDPed FCoE data */
1541 if (ddp_bytes > 0) {
1542 unsigned int mss;
1543
fc77dc3c 1544 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1545 sizeof(struct fc_frame_header) -
1546 sizeof(struct fcoe_crc_eof);
1547 if (mss > 512)
1548 mss &= ~511;
1549 total_rx_bytes += ddp_bytes;
1550 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1551 }
1552#endif /* IXGBE_FCOE */
1553
f494e8fa
AV		 1554 rx_ring->total_packets += total_rx_packets;
1555 rx_ring->total_bytes += total_rx_bytes;
c267fc16
AD		 1556 u64_stats_update_begin(&rx_ring->syncp);
1557 rx_ring->stats.packets += total_rx_packets;
1558 rx_ring->stats.bytes += total_rx_bytes;
1559 u64_stats_update_end(&rx_ring->syncp);
9a799d71
AK		 1560}
1561
021230d4 1562static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1563/**
1564 * ixgbe_configure_msix - Configure MSI-X hardware
1565 * @adapter: board private structure
1566 *
1567 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1568 * interrupts.
1569 **/
1570static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1571{
021230d4 1572 struct ixgbe_q_vector *q_vector;
bf29ee6c 1573 int i, q_vectors, v_idx, r_idx;
021230d4 1574 u32 mask;
9a799d71 1575
021230d4 1576 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1577
4df10466
JB		 1578 /*
1579 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1580 * corresponding register.
1581 */
1582 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1583 q_vector = adapter->q_vector[v_idx];
984b3f57 1584 /* XXX for_each_set_bit(...) */
021230d4 1585 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1586 adapter->num_rx_queues);
021230d4
AV		 1587
1588 for (i = 0; i < q_vector->rxr_count; i++) {
bf29ee6c
AD		 1589 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1590 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
021230d4 1591 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1592 adapter->num_rx_queues,
1593 r_idx + 1);
021230d4
AV		 1594 }
1595 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1596 adapter->num_tx_queues);
021230d4
AV		 1597
1598 for (i = 0; i < q_vector->txr_count; i++) {
bf29ee6c
AD		 1599 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1600 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
021230d4 1601 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1602 adapter->num_tx_queues,
1603 r_idx + 1);
021230d4
AV		 1604 }
1605
021230d4 1606 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1607 /* tx only */
1608 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1609 else if (q_vector->rxr_count)
f7554a2b
NS		 1610 /* rx or mixed */
1611 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1612
fe49f04a 1613 ixgbe_write_eitr(q_vector);
b25ebfd2
PW		 1614 /* If Flow Director is enabled, set interrupt affinity */
1615 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1616 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1617 /*
1618 * Allocate the affinity_hint cpumask, assign the mask
1619 * for this vector, and set our affinity_hint for
1620 * this irq.
1621 */
1622 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1623 GFP_KERNEL))
1624 return;
1625 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1626 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1627 q_vector->affinity_mask);
1628 }
9a799d71
AK		 1629 }
1630
bd508178
AD		 1631 switch (adapter->hw.mac.type) {
1632 case ixgbe_mac_82598EB:
e8e26350 1633 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1634 v_idx);
bd508178
AD		 1635 break;
1636 case ixgbe_mac_82599EB:
b93a2226 1637 case ixgbe_mac_X540:
e8e26350 1638 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178
AD		 1639 break;
1640
1641 default:
1642 break;
1643 }
021230d4
AV		 1644 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1645
41fb9248 1646 /* set up to autoclear timer, and the vectors */
021230d4 1647 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1648 if (adapter->num_vfs)
1649 mask &= ~(IXGBE_EIMS_OTHER |
1650 IXGBE_EIMS_MAILBOX |
1651 IXGBE_EIMS_LSC);
1652 else
1653 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1654 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1655}
1656
f494e8fa
AV		 1657enum latency_range {
1658 lowest_latency = 0,
1659 low_latency = 1,
1660 bulk_latency = 2,
1661 latency_invalid = 255
1662};
1663
1664/**
1665 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1666 * @adapter: pointer to adapter
1667 * @eitr: eitr setting (ints per sec) to give last timeslice
1668 * @itr_setting: current throttle rate in ints/second
1669 * @packets: the number of packets during this measurement interval
1670 * @bytes: the number of bytes during this measurement interval
1671 *
1672 * Stores a new ITR value based on packets and byte
1673 * counts during the last interrupt. The advantage of per interrupt
1674 * computation is faster updates and more accurate ITR for the current
1675 * traffic pattern. Constants in this function were computed
1676 * based on theoretical maximum wire speed and thresholds were set based
1677 * on testing data as well as attempting to minimize response time
1678 * while increasing bulk throughput.
1679 * this functionality is controlled by the InterruptThrottleRate module
1680 * parameter (see ixgbe_param.c)
1681 **/
1682static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1683 u32 eitr, u8 itr_setting,
1684 int packets, int bytes)
f494e8fa
AV		 1685{
1686 unsigned int retval = itr_setting;
1687 u32 timepassed_us;
1688 u64 bytes_perint;
1689
1690 if (packets == 0)
1691 goto update_itr_done;
1692
1693
1694 /* simple throttlerate management
1695 * 0-20MB/s lowest (100000 ints/s)
1696 * 20-100MB/s low (20000 ints/s)
1697 * 100-1249MB/s bulk (8000 ints/s)
1698 */
1699 /* what was last interrupt timeslice? */
1700 timepassed_us = 1000000/eitr;
1701 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1702
1703 switch (itr_setting) {
1704 case lowest_latency:
1705 if (bytes_perint > adapter->eitr_low)
1706 retval = low_latency;
1707 break;
1708 case low_latency:
1709 if (bytes_perint > adapter->eitr_high)
1710 retval = bulk_latency;
1711 else if (bytes_perint <= adapter->eitr_low)
1712 retval = lowest_latency;
1713 break;
1714 case bulk_latency:
1715 if (bytes_perint <= adapter->eitr_high)
1716 retval = low_latency;
1717 break;
1718 }
1719
1720update_itr_done:
1721 return retval;
1722}
1723
509ee935
JB		 1724/**
1725 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1726 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1727 *
1728 * This function is made to be called by ethtool and by the driver
1729 * when it needs to update EITR registers at runtime. Hardware
1730 * specific quirks/differences are taken care of here.
1731 */
fe49f04a 1732void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1733{
fe49f04a 1734 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1735 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1736 int v_idx = q_vector->v_idx;
1737 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1738
bd508178
AD		 1739 switch (adapter->hw.mac.type) {
1740 case ixgbe_mac_82598EB:
509ee935
JB		 1741 /* must write high and low 16 bits to reset counter */
1742 itr_reg |= (itr_reg << 16);
bd508178
AD		 1743 break;
1744 case ixgbe_mac_82599EB:
b93a2226 1745 case ixgbe_mac_X540:
f8d1dcaf 1746 /*
b93a2226 1747 * 82599 and X540 can support a value of zero, so allow it for
f8d1dcaf
JB		 1748 * max interrupt rate, but there is an errata where it can
1749 * not be zero with RSC
1750 */
1751 if (itr_reg == 8 &&
1752 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1753 itr_reg = 0;
1754
509ee935
JB		 1755 /*
1756 * set the WDIS bit to not clear the timer bits and cause an
1757 * immediate assertion of the interrupt
1758 */
1759 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1760 break;
1761 default:
1762 break;
509ee935
JB		 1763 }
1764 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1765}
1766
f494e8fa
AV		 1767static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1768{
1769 struct ixgbe_adapter *adapter = q_vector->adapter;
125601bf 1770 int i, r_idx;
f494e8fa
AV		 1771 u32 new_itr;
1772 u8 current_itr, ret_itr;
f494e8fa
AV		 1773
1774 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1775 for (i = 0; i < q_vector->txr_count; i++) {
125601bf 1776 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1777 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1778 q_vector->tx_itr,
1779 tx_ring->total_packets,
1780 tx_ring->total_bytes);
f494e8fa
AV		 1781 /* if the result for this queue would decrease interrupt
1782 * rate for this vector then use that result */
30efa5a3 1783 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1784 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1785 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1786 r_idx + 1);
f494e8fa
AV		 1787 }
1788
1789 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1790 for (i = 0; i < q_vector->rxr_count; i++) {
125601bf 1791 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1792 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1793 q_vector->rx_itr,
1794 rx_ring->total_packets,
1795 rx_ring->total_bytes);
f494e8fa
AV		 1796 /* if the result for this queue would decrease interrupt
1797 * rate for this vector then use that result */
30efa5a3 1798 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1799 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1800 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1801 r_idx + 1);
f494e8fa
AV		 1802 }
1803
30efa5a3 1804 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1805
1806 switch (current_itr) {
1807 /* counts and packets in update_itr are dependent on these numbers */
1808 case lowest_latency:
1809 new_itr = 100000;
1810 break;
1811 case low_latency:
1812 new_itr = 20000; /* aka hwitr = ~200 */
1813 break;
1814 case bulk_latency:
1815 default:
1816 new_itr = 8000;
1817 break;
1818 }
1819
1820 if (new_itr != q_vector->eitr) {
fe49f04a 1821 /* do an exponential smoothing */
125601bf 1822 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935
JB		 1823
1824 /* save the algorithm value here, not the smoothed one */
1825 q_vector->eitr = new_itr;
fe49f04a
AD		 1826
1827 ixgbe_write_eitr(q_vector);
f494e8fa 1828 }
f494e8fa
AV		 1829}
1830
119fc60a 1831/**
f0f9778d
AD		 1832 * ixgbe_check_overtemp_subtask - check for over tempurature
1833 * @adapter: pointer to adapter
119fc60a 1834 **/
f0f9778d 1835static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1836{
119fc60a
MC		 1837 struct ixgbe_hw *hw = &adapter->hw;
1838 u32 eicr = adapter->interrupt_event;
1839
f0f9778d 1840 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1841 return;
1842
f0f9778d
AD		 1843 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1844 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1845 return;
1846
1847 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1848
7ca647bd 1849 switch (hw->device_id) {
f0f9778d
AD		 1850 case IXGBE_DEV_ID_82599_T3_LOM:
1851 /*
1852 * Since the warning interrupt is for both ports
1853 * we don't have to check if:
1854 * - This interrupt wasn't for our port.
1855 * - We may have missed the interrupt so always have to
1856 * check if we got a LSC
1857 */
1858 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1859 !(eicr & IXGBE_EICR_LSC))
1860 return;
1861
1862 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1863 u32 autoneg;
1864 bool link_up = false;
7ca647bd 1865
7ca647bd
JP		 1866 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1867
f0f9778d
AD		 1868 if (link_up)
1869 return;
1870 }
1871
1872 /* Check if this is not due to overtemp */
1873 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1874 return;
1875
1876 break;
7ca647bd
JP		 1877 default:
1878 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1879 return;
7ca647bd 1880 break;
119fc60a 1881 }
7ca647bd
JP		 1882 e_crit(drv,
1883 "Network adapter has been stopped because it has over heated. "
1884 "Restart the computer. If the problem persists, "
1885 "power off the system and replace the adapter\n");
f0f9778d
AD		 1886
1887 adapter->interrupt_event = 0;
119fc60a
MC		 1888}
1889
0befdb3e
JB		 1890static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1891{
1892 struct ixgbe_hw *hw = &adapter->hw;
1893
1894 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1895 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1896 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1897 /* write to clear the interrupt */
1898 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1899 }
1900}
cf8280ee 1901
e8e26350
PW		 1902static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1903{
1904 struct ixgbe_hw *hw = &adapter->hw;
1905
73c4b7cd
AD		 1906 if (eicr & IXGBE_EICR_GPI_SDP2) {
1907 /* Clear the interrupt */
1908 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 1909 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1910 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1911 ixgbe_service_event_schedule(adapter);
1912 }
73c4b7cd
AD		 1913 }
1914
e8e26350
PW		 1915 if (eicr & IXGBE_EICR_GPI_SDP1) {
1916 /* Clear the interrupt */
1917 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 1918 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1919 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1920 ixgbe_service_event_schedule(adapter);
1921 }
e8e26350
PW		 1922 }
1923}
1924
cf8280ee
JB		 1925static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1926{
1927 struct ixgbe_hw *hw = &adapter->hw;
1928
1929 adapter->lsc_int++;
1930 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1931 adapter->link_check_timeout = jiffies;
1932 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1933 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1934 IXGBE_WRITE_FLUSH(hw);
93c52dd0 1935 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 1936 }
1937}
1938
9a799d71
AK		 1939static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1940{
1941 struct net_device *netdev = data;
1942 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1943 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1944 u32 eicr;
1945
1946 /*
1947 * Workaround for Silicon errata. Use clear-by-write instead
1948 * of clear-by-read. Reading with EICS will return the
1949 * interrupt causes without clearing, which later be done
1950 * with the write to EICR.
1951 */
1952 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1953 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1954
cf8280ee
JB		 1955 if (eicr & IXGBE_EICR_LSC)
1956 ixgbe_check_lsc(adapter);
d4f80882 1957
1cdd1ec8
GR		 1958 if (eicr & IXGBE_EICR_MAILBOX)
1959 ixgbe_msg_task(adapter);
1960
bd508178
AD		 1961 switch (hw->mac.type) {
1962 case ixgbe_mac_82599EB:
b93a2226 1963 case ixgbe_mac_X540:
c4cf55e5
PWJ		 1964 /* Handle Flow Director Full threshold interrupt */
1965 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 1966 int reinit_count = 0;
c4cf55e5 1967 int i;
c4cf55e5 1968 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 1969 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 1970 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 1971 &ring->state))
1972 reinit_count++;
1973 }
1974 if (reinit_count) {
1975 /* no more flow director interrupts until after init */
1976 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1977 eicr &= ~IXGBE_EICR_FLOW_DIR;
1978 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1979 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1980 }
1981 }
f0f9778d
AD		 1982 ixgbe_check_sfp_event(adapter, eicr);
1983 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1984 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1985 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1986 adapter->interrupt_event = eicr;
1987 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1988 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1989 }
1990 }
bd508178
AD		 1991 break;
1992 default:
1993 break;
c4cf55e5 1994 }
bd508178
AD		 1995
1996 ixgbe_check_fan_failure(adapter, eicr);
1997
7086400d 1998 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 1999 if (!test_bit(__IXGBE_DOWN, &adapter->state))
7086400d
AD		 2000 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
2001 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
9a799d71
AK		 2002
2003 return IRQ_HANDLED;
2004}
2005
fe49f04a
AD		 2006static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2007 u64 qmask)
2008{
2009 u32 mask;
bd508178 2010 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2011
bd508178
AD		 2012 switch (hw->mac.type) {
2013 case ixgbe_mac_82598EB:
fe49f04a 2014 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2015 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2016 break;
2017 case ixgbe_mac_82599EB:
b93a2226 2018 case ixgbe_mac_X540:
fe49f04a 2019 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2020 if (mask)
2021 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2022 mask = (qmask >> 32);
bd508178
AD		 2023 if (mask)
2024 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2025 break;
2026 default:
2027 break;
fe49f04a
AD		 2028 }
2029 /* skip the flush */
2030}
2031
2032static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2033 u64 qmask)
fe49f04a
AD		 2034{
2035 u32 mask;
bd508178 2036 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2037
bd508178
AD		 2038 switch (hw->mac.type) {
2039 case ixgbe_mac_82598EB:
fe49f04a 2040 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2041 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2042 break;
2043 case ixgbe_mac_82599EB:
b93a2226 2044 case ixgbe_mac_X540:
fe49f04a 2045 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2046 if (mask)
2047 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2048 mask = (qmask >> 32);
bd508178
AD		 2049 if (mask)
2050 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2051 break;
2052 default:
2053 break;
fe49f04a
AD		 2054 }
2055 /* skip the flush */
2056}
2057
9a799d71
AK		 2058static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
2059{
021230d4
AV		 2060 struct ixgbe_q_vector *q_vector = data;
2061 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2062 struct ixgbe_ring *tx_ring;
021230d4
AV		 2063 int i, r_idx;
2064
2065 if (!q_vector->txr_count)
2066 return IRQ_HANDLED;
2067
2068 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2069 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2070 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 2071 tx_ring->total_bytes = 0;
2072 tx_ring->total_packets = 0;
021230d4 2073 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2074 r_idx + 1);
021230d4 2075 }
9a799d71 2076
9b471446 2077 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 2078 napi_schedule(&q_vector->napi);
2079
9a799d71
AK		 2080 return IRQ_HANDLED;
2081}
2082
021230d4
AV		 2083/**
2084 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2085 * @irq: unused
2086 * @data: pointer to our q_vector struct for this interrupt vector
2087 **/
9a799d71
AK		 2088static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2089{
021230d4
AV		 2090 struct ixgbe_q_vector *q_vector = data;
2091 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2092 struct ixgbe_ring *rx_ring;
021230d4 2093 int r_idx;
30efa5a3 2094 int i;
021230d4 2095
33cf09c9
AD		 2096#ifdef CONFIG_IXGBE_DCA
2097 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2098 ixgbe_update_dca(q_vector);
2099#endif
2100
021230d4 2101 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
33cf09c9 2102 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2103 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 2104 rx_ring->total_bytes = 0;
2105 rx_ring->total_packets = 0;
2106 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2107 r_idx + 1);
30efa5a3
JB		 2108 }
2109
021230d4
AV		 2110 if (!q_vector->rxr_count)
2111 return IRQ_HANDLED;
2112
9b471446 2113 /* EIAM disabled interrupts (on this vector) for us */
288379f0 2114 napi_schedule(&q_vector->napi);
021230d4
AV		 2115
2116 return IRQ_HANDLED;
2117}
2118
2119static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2120{
91281fd3
AD		 2121 struct ixgbe_q_vector *q_vector = data;
2122 struct ixgbe_adapter *adapter = q_vector->adapter;
2123 struct ixgbe_ring *ring;
2124 int r_idx;
2125 int i;
2126
2127 if (!q_vector->txr_count && !q_vector->rxr_count)
2128 return IRQ_HANDLED;
2129
2130 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2131 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2132 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2133 ring->total_bytes = 0;
2134 ring->total_packets = 0;
2135 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2136 r_idx + 1);
91281fd3
AD		 2137 }
2138
2139 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2140 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2141 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 2142 ring->total_bytes = 0;
2143 ring->total_packets = 0;
2144 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2145 r_idx + 1);
91281fd3
AD		 2146 }
2147
9b471446 2148 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2149 napi_schedule(&q_vector->napi);
9a799d71 2150
9a799d71
AK		 2151 return IRQ_HANDLED;
2152}
2153
021230d4
AV		 2154/**
2155 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2156 * @napi: napi struct with our devices info in it
2157 * @budget: amount of work driver is allowed to do this pass, in packets
2158 *
f0848276
JB		 2159 * This function is optimized for cleaning one queue only on a single
2160 * q_vector!!!
021230d4 2161 **/
9a799d71
AK		 2162static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2163{
021230d4 2164 struct ixgbe_q_vector *q_vector =
e8e9f696 2165 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2166 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 2167 struct ixgbe_ring *rx_ring = NULL;
9a799d71 2168 int work_done = 0;
021230d4 2169 long r_idx;
9a799d71 2170
5dd2d332 2171#ifdef CONFIG_IXGBE_DCA
bd0362dd 2172 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2173 ixgbe_update_dca(q_vector);
bd0362dd 2174#endif
9a799d71 2175
33cf09c9
AD		 2176 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2177 rx_ring = adapter->rx_ring[r_idx];
2178
78b6f4ce 2179 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 2180
021230d4
AV		 2181 /* If all Rx work done, exit the polling mode */
2182 if (work_done < budget) {
288379f0 2183 napi_complete(napi);
f7554a2b 2184 if (adapter->rx_itr_setting & 1)
f494e8fa 2185 ixgbe_set_itr_msix(q_vector);
9a799d71 2186 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2187 ixgbe_irq_enable_queues(adapter,
e8e9f696 2188 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 2189 }
2190
2191 return work_done;
2192}
2193
f0848276 2194/**
91281fd3 2195 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 2196 * @napi: napi struct with our devices info in it
2197 * @budget: amount of work driver is allowed to do this pass, in packets
2198 *
2199 * This function will clean more than one rx queue associated with a
2200 * q_vector.
2201 **/
91281fd3 2202static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 2203{
2204 struct ixgbe_q_vector *q_vector =
e8e9f696 2205 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 2206 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 2207 struct ixgbe_ring *ring = NULL;
f0848276
JB		 2208 int work_done = 0, i;
2209 long r_idx;
91281fd3
AD		 2210 bool tx_clean_complete = true;
2211
33cf09c9
AD		 2212#ifdef CONFIG_IXGBE_DCA
2213 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2214 ixgbe_update_dca(q_vector);
2215#endif
2216
91281fd3
AD		 2217 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2218 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2219 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2220 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2221 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2222 r_idx + 1);
91281fd3 2223 }
f0848276
JB		 2224
2225 /* attempt to distribute budget to each queue fairly, but don't allow
2226 * the budget to go below 1 because we'll exit polling */
2227 budget /= (q_vector->rxr_count ?: 1);
2228 budget = max(budget, 1);
2229 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2230 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2231 ring = adapter->rx_ring[r_idx];
91281fd3 2232 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 2233 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2234 r_idx + 1);
f0848276
JB		 2235 }
2236
2237 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 2238 ring = adapter->rx_ring[r_idx];
f0848276 2239 /* If all Rx work done, exit the polling mode */
7f821875 2240 if (work_done < budget) {
288379f0 2241 napi_complete(napi);
f7554a2b 2242 if (adapter->rx_itr_setting & 1)
f0848276
JB		 2243 ixgbe_set_itr_msix(q_vector);
2244 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2245 ixgbe_irq_enable_queues(adapter,
e8e9f696 2246 ((u64)1 << q_vector->v_idx));
f0848276
JB		 2247 return 0;
2248 }
2249
2250 return work_done;
2251}
91281fd3
AD		 2252
2253/**
2254 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2255 * @napi: napi struct with our devices info in it
2256 * @budget: amount of work driver is allowed to do this pass, in packets
2257 *
2258 * This function is optimized for cleaning one queue only on a single
2259 * q_vector!!!
2260 **/
2261static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2262{
2263 struct ixgbe_q_vector *q_vector =
e8e9f696 2264 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2265 struct ixgbe_adapter *adapter = q_vector->adapter;
2266 struct ixgbe_ring *tx_ring = NULL;
2267 int work_done = 0;
2268 long r_idx;
2269
91281fd3
AD		 2270#ifdef CONFIG_IXGBE_DCA
2271 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2272 ixgbe_update_dca(q_vector);
91281fd3
AD		 2273#endif
2274
33cf09c9
AD		 2275 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2276 tx_ring = adapter->tx_ring[r_idx];
2277
91281fd3
AD		 2278 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2279 work_done = budget;
2280
f7554a2b 2281 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2282 if (work_done < budget) {
2283 napi_complete(napi);
f7554a2b 2284 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2285 ixgbe_set_itr_msix(q_vector);
2286 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2287 ixgbe_irq_enable_queues(adapter,
2288 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2289 }
2290
2291 return work_done;
2292}
2293
021230d4 2294static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2295 int r_idx)
021230d4 2296{
7a921c93 2297 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2298 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93
AD		 2299
2300 set_bit(r_idx, q_vector->rxr_idx);
2301 q_vector->rxr_count++;
2274543f 2302 rx_ring->q_vector = q_vector;
021230d4
AV		 2303}
2304
2305static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2306 int t_idx)
021230d4 2307{
7a921c93 2308 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2309 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93
AD		 2310
2311 set_bit(t_idx, q_vector->txr_idx);
2312 q_vector->txr_count++;
2274543f 2313 tx_ring->q_vector = q_vector;
021230d4
AV		 2314}
2315
9a799d71 2316/**
021230d4
AV		 2317 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2318 * @adapter: board private structure to initialize
9a799d71 2319 *
021230d4
AV		 2320 * This function maps descriptor rings to the queue-specific vectors
2321 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2322 * one vector per ring/queue, but on a constrained vector budget, we
2323 * group the rings as "efficiently" as possible. You would add new
2324 * mapping configurations in here.
9a799d71 2325 **/
d0759ebb 2326static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2327{
d0759ebb 2328 int q_vectors;
021230d4
AV		 2329 int v_start = 0;
2330 int rxr_idx = 0, txr_idx = 0;
2331 int rxr_remaining = adapter->num_rx_queues;
2332 int txr_remaining = adapter->num_tx_queues;
2333 int i, j;
2334 int rqpv, tqpv;
2335 int err = 0;
2336
2337 /* No mapping required if MSI-X is disabled. */
2338 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2339 goto out;
9a799d71 2340
d0759ebb
AD		 2341 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2342
021230d4
AV		 2343 /*
2344 * The ideal configuration...
2345 * We have enough vectors to map one per queue.
2346 */
d0759ebb 2347 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
021230d4
AV		 2348 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2349 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2350
021230d4
AV		 2351 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2352 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2353
9a799d71 2354 goto out;
021230d4 2355 }
9a799d71 2356
021230d4
AV		 2357 /*
2358 * If we don't have enough vectors for a 1-to-1
2359 * mapping, we'll have to group them so there are
2360 * multiple queues per vector.
2361 */
2362 /* Re-adjusting *qpv takes care of the remainder. */
d0759ebb
AD		 2363 for (i = v_start; i < q_vectors; i++) {
2364 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
021230d4
AV		 2365 for (j = 0; j < rqpv; j++) {
2366 map_vector_to_rxq(adapter, i, rxr_idx);
2367 rxr_idx++;
2368 rxr_remaining--;
2369 }
d0759ebb 2370 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
021230d4
AV		 2371 for (j = 0; j < tqpv; j++) {
2372 map_vector_to_txq(adapter, i, txr_idx);
2373 txr_idx++;
2374 txr_remaining--;
9a799d71 2375 }
9a799d71 2376 }
021230d4
AV		 2377out:
2378 return err;
2379}
2380
2381/**
2382 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2383 * @adapter: board private structure
2384 *
2385 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2386 * interrupts from the kernel.
2387 **/
2388static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2389{
2390 struct net_device *netdev = adapter->netdev;
2391 irqreturn_t (*handler)(int, void *);
2392 int i, vector, q_vectors, err;
e8e9f696 2393 int ri = 0, ti = 0;
021230d4
AV		 2394
2395 /* Decrement for Other and TCP Timer vectors */
2396 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2397
d0759ebb 2398 err = ixgbe_map_rings_to_vectors(adapter);
021230d4 2399 if (err)
d0759ebb 2400 return err;
021230d4 2401
d0759ebb
AD		 2402#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2403 ? &ixgbe_msix_clean_many : \
2404 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2405 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2406 NULL)
021230d4 2407 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb
AD		 2408 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2409 handler = SET_HANDLER(q_vector);
cb13fc20 2410
e8e9f696 2411 if (handler == &ixgbe_msix_clean_rx) {
9fe93afd
DS		 2412 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2413 "%s-%s-%d", netdev->name, "rx", ri++);
e8e9f696 2414 } else if (handler == &ixgbe_msix_clean_tx) {
9fe93afd
DS		 2415 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2416 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb 2417 } else if (handler == &ixgbe_msix_clean_many) {
9fe93afd
DS		 2418 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2419 "%s-%s-%d", netdev->name, "TxRx", ri++);
32aa77a4 2420 ti++;
d0759ebb
AD		 2421 } else {
2422 /* skip this unused q_vector */
2423 continue;
32aa77a4 2424 }
021230d4 2425 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb
AD		 2426 handler, 0, q_vector->name,
2427 q_vector);
9a799d71 2428 if (err) {
396e799c 2429 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2430 "Error: %d\n", err);
021230d4 2431 goto free_queue_irqs;
9a799d71 2432 }
9a799d71
AK		 2433 }
2434
d0759ebb 2435 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
021230d4 2436 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb 2437 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
9a799d71 2438 if (err) {
396e799c 2439 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2440 goto free_queue_irqs;
9a799d71
AK		 2441 }
2442
9a799d71
AK		 2443 return 0;
2444
021230d4
AV		 2445free_queue_irqs:
2446 for (i = vector - 1; i >= 0; i--)
2447 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2448 adapter->q_vector[i]);
021230d4
AV		 2449 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2450 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2451 kfree(adapter->msix_entries);
2452 adapter->msix_entries = NULL;
9a799d71
AK		 2453 return err;
2454}
2455
f494e8fa
AV		 2456static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2457{
7a921c93 2458 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
4a0b9ca0
PW		 2459 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2460 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
125601bf
AD		 2461 u32 new_itr = q_vector->eitr;
2462 u8 current_itr;
f494e8fa 2463
30efa5a3 2464 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2465 q_vector->tx_itr,
2466 tx_ring->total_packets,
2467 tx_ring->total_bytes);
30efa5a3 2468 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2469 q_vector->rx_itr,
2470 rx_ring->total_packets,
2471 rx_ring->total_bytes);
f494e8fa 2472
30efa5a3 2473 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2474
2475 switch (current_itr) {
2476 /* counts and packets in update_itr are dependent on these numbers */
2477 case lowest_latency:
2478 new_itr = 100000;
2479 break;
2480 case low_latency:
2481 new_itr = 20000; /* aka hwitr = ~200 */
2482 break;
2483 case bulk_latency:
2484 new_itr = 8000;
2485 break;
2486 default:
2487 break;
2488 }
2489
2490 if (new_itr != q_vector->eitr) {
fe49f04a 2491 /* do an exponential smoothing */
125601bf 2492 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935 2493
125601bf 2494 /* save the algorithm value here */
509ee935 2495 q_vector->eitr = new_itr;
fe49f04a
AD		 2496
2497 ixgbe_write_eitr(q_vector);
f494e8fa 2498 }
f494e8fa
AV		 2499}
2500
79aefa45
AD		 2501/**
2502 * ixgbe_irq_enable - Enable default interrupt generation settings
2503 * @adapter: board private structure
2504 **/
6af3b9eb
ET		 2505static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2506 bool flush)
79aefa45
AD		 2507{
2508 u32 mask;
835462fc
NS		 2509
2510 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2511 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2512 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2513 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2514 mask |= IXGBE_EIMS_GPI_SDP1;
bd508178
AD		 2515 switch (adapter->hw.mac.type) {
2516 case ixgbe_mac_82599EB:
b93a2226 2517 case ixgbe_mac_X540:
2a41ff81 2518 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2519 mask |= IXGBE_EIMS_GPI_SDP1;
2520 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2521 if (adapter->num_vfs)
2522 mask |= IXGBE_EIMS_MAILBOX;
bd508178
AD		 2523 break;
2524 default:
2525 break;
e8e26350 2526 }
c4cf55e5
PWJ		 2527 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2528 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2529 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2530
79aefa45 2531 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2532 if (queues)
2533 ixgbe_irq_enable_queues(adapter, ~0);
2534 if (flush)
2535 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2536
2537 if (adapter->num_vfs > 32) {
2538 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2539 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2540 }
79aefa45 2541}
021230d4 2542
9a799d71 2543/**
021230d4 2544 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2545 * @irq: interrupt number
2546 * @data: pointer to a network interface device structure
9a799d71
AK		 2547 **/
2548static irqreturn_t ixgbe_intr(int irq, void *data)
2549{
2550 struct net_device *netdev = data;
2551 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2552 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2553 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2554 u32 eicr;
2555
54037505 2556 /*
6af3b9eb 2557 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2558 * before the read of EICR.
2559 */
2560 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2561
021230d4
AV		 2562 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2563 * therefore no explict interrupt disable is necessary */
2564 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2565 if (!eicr) {
6af3b9eb
ET		 2566 /*
2567 * shared interrupt alert!
f47cf66e 2568 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2569 * have disabled interrupts due to EIAM
2570 * finish the workaround of silicon errata on 82598. Unmask
2571 * the interrupt that we masked before the EICR read.
2572 */
2573 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2574 ixgbe_irq_enable(adapter, true, true);
9a799d71 2575 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2576 }
9a799d71 2577
cf8280ee
JB		 2578 if (eicr & IXGBE_EICR_LSC)
2579 ixgbe_check_lsc(adapter);
021230d4 2580
bd508178
AD		 2581 switch (hw->mac.type) {
2582 case ixgbe_mac_82599EB:
e8e26350 2583 ixgbe_check_sfp_event(adapter, eicr);
bd508178
AD		 2584 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2585 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
f0f9778d
AD		 2586 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2587 adapter->interrupt_event = eicr;
2588 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2589 ixgbe_service_event_schedule(adapter);
2590 }
bd508178
AD		 2591 }
2592 break;
2593 default:
2594 break;
2595 }
e8e26350 2596
0befdb3e
JB		 2597 ixgbe_check_fan_failure(adapter, eicr);
2598
7a921c93 2599 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2600 adapter->tx_ring[0]->total_packets = 0;
2601 adapter->tx_ring[0]->total_bytes = 0;
2602 adapter->rx_ring[0]->total_packets = 0;
2603 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2604 /* would disable interrupts here but EIAM disabled it */
7a921c93 2605 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2606 }
2607
6af3b9eb
ET		 2608 /*
2609 * re-enable link(maybe) and non-queue interrupts, no flush.
2610 * ixgbe_poll will re-enable the queue interrupts
2611 */
2612
2613 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2614 ixgbe_irq_enable(adapter, false, false);
2615
9a799d71
AK		 2616 return IRQ_HANDLED;
2617}
2618
021230d4
AV		 2619static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2620{
2621 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2622
2623 for (i = 0; i < q_vectors; i++) {
7a921c93 2624 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2625 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2626 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2627 q_vector->rxr_count = 0;
2628 q_vector->txr_count = 0;
2629 }
2630}
2631
9a799d71
AK		 2632/**
2633 * ixgbe_request_irq - initialize interrupts
2634 * @adapter: board private structure
2635 *
2636 * Attempts to configure interrupts using the best available
2637 * capabilities of the hardware and kernel.
2638 **/
021230d4 2639static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2640{
2641 struct net_device *netdev = adapter->netdev;
021230d4 2642 int err;
9a799d71 2643
021230d4
AV		 2644 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2645 err = ixgbe_request_msix_irqs(adapter);
2646 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2647 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2648 netdev->name, netdev);
021230d4 2649 } else {
a0607fd3 2650 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2651 netdev->name, netdev);
9a799d71
AK		 2652 }
2653
9a799d71 2654 if (err)
396e799c 2655 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2656
9a799d71
AK		 2657 return err;
2658}
2659
2660static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2661{
2662 struct net_device *netdev = adapter->netdev;
2663
2664 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2665 int i, q_vectors;
9a799d71 2666
021230d4
AV		 2667 q_vectors = adapter->num_msix_vectors;
2668
2669 i = q_vectors - 1;
9a799d71 2670 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2671
021230d4
AV		 2672 i--;
2673 for (; i >= 0; i--) {
894ff7cf
AD		 2674 /* free only the irqs that were actually requested */
2675 if (!adapter->q_vector[i]->rxr_count &&
2676 !adapter->q_vector[i]->txr_count)
2677 continue;
2678
021230d4 2679 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2680 adapter->q_vector[i]);
021230d4
AV		 2681 }
2682
2683 ixgbe_reset_q_vectors(adapter);
2684 } else {
2685 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2686 }
2687}
2688
22d5a71b
JB		 2689/**
2690 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2691 * @adapter: board private structure
2692 **/
2693static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2694{
bd508178
AD		 2695 switch (adapter->hw.mac.type) {
2696 case ixgbe_mac_82598EB:
835462fc 2697 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2698 break;
2699 case ixgbe_mac_82599EB:
b93a2226 2700 case ixgbe_mac_X540:
835462fc
NS		 2701 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2702 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2703 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2704 if (adapter->num_vfs > 32)
2705 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
bd508178
AD		 2706 break;
2707 default:
2708 break;
22d5a71b
JB		 2709 }
2710 IXGBE_WRITE_FLUSH(&adapter->hw);
2711 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2712 int i;
2713 for (i = 0; i < adapter->num_msix_vectors; i++)
2714 synchronize_irq(adapter->msix_entries[i].vector);
2715 } else {
2716 synchronize_irq(adapter->pdev->irq);
2717 }
2718}
2719
9a799d71
AK		 2720/**
2721 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2722 *
2723 **/
2724static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2725{
9a799d71
AK		 2726 struct ixgbe_hw *hw = &adapter->hw;
2727
021230d4 2728 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2729 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2730
e8e26350
PW		 2731 ixgbe_set_ivar(adapter, 0, 0, 0);
2732 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2733
2734 map_vector_to_rxq(adapter, 0, 0);
2735 map_vector_to_txq(adapter, 0, 0);
2736
396e799c 2737 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2738}
2739
43e69bf0
AD		 2740/**
2741 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2742 * @adapter: board private structure
2743 * @ring: structure containing ring specific data
2744 *
2745 * Configure the Tx descriptor ring after a reset.
2746 **/
84418e3b
AD		 2747void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2748 struct ixgbe_ring *ring)
43e69bf0
AD		 2749{
2750 struct ixgbe_hw *hw = &adapter->hw;
2751 u64 tdba = ring->dma;
2f1860b8
AD		 2752 int wait_loop = 10;
2753 u32 txdctl;
bf29ee6c 2754 u8 reg_idx = ring->reg_idx;
43e69bf0 2755
2f1860b8
AD		 2756 /* disable queue to avoid issues while updating state */
2757 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2758 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2759 txdctl & ~IXGBE_TXDCTL_ENABLE);
2760 IXGBE_WRITE_FLUSH(hw);
2761
43e69bf0 2762 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2763 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2764 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2765 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2766 ring->count * sizeof(union ixgbe_adv_tx_desc));
2767 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2768 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2769 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2770
2f1860b8
AD		 2771 /* configure fetching thresholds */
2772 if (adapter->rx_itr_setting == 0) {
2773 /* cannot set wthresh when itr==0 */
2774 txdctl &= ~0x007F0000;
2775 } else {
2776 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2777 txdctl |= (8 << 16);
2778 }
2779 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2780 /* PThresh workaround for Tx hang with DFP enabled. */
2781 txdctl |= 32;
2782 }
2783
2784 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2785 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2786 adapter->atr_sample_rate) {
2787 ring->atr_sample_rate = adapter->atr_sample_rate;
2788 ring->atr_count = 0;
2789 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2790 } else {
2791 ring->atr_sample_rate = 0;
2792 }
2f1860b8 2793
c84d324c
JF		 2794 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2795
2f1860b8
AD		 2796 /* enable queue */
2797 txdctl |= IXGBE_TXDCTL_ENABLE;
2798 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2799
2800 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2801 if (hw->mac.type == ixgbe_mac_82598EB &&
2802 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2803 return;
2804
2805 /* poll to verify queue is enabled */
2806 do {
032b4325 2807 usleep_range(1000, 2000);
2f1860b8
AD		 2808 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2809 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2810 if (!wait_loop)
2811 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2812}
2813
120ff942
AD		 2814static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2815{
2816 struct ixgbe_hw *hw = &adapter->hw;
2817 u32 rttdcs;
72a32f1f 2818 u32 reg;
8b1c0b24 2819 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2820
2821 if (hw->mac.type == ixgbe_mac_82598EB)
2822 return;
2823
2824 /* disable the arbiter while setting MTQC */
2825 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2826 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2827 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2828
2829 /* set transmit pool layout */
8b1c0b24 2830 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2831 case (IXGBE_FLAG_SRIOV_ENABLED):
2832 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2833 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2834 break;
8b1c0b24
JF		 2835 default:
2836 if (!tcs)
2837 reg = IXGBE_MTQC_64Q_1PB;
2838 else if (tcs <= 4)
2839 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2840 else
2841 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2842
8b1c0b24 2843 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2844
8b1c0b24
JF		 2845 /* Enable Security TX Buffer IFG for multiple pb */
2846 if (tcs) {
2847 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2848 reg |= IXGBE_SECTX_DCB;
2849 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2850 }
120ff942
AD		 2851 break;
2852 }
2853
2854 /* re-enable the arbiter */
2855 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2856 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2857}
2858
9a799d71 2859/**
3a581073 2860 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2861 * @adapter: board private structure
2862 *
2863 * Configure the Tx unit of the MAC after a reset.
2864 **/
2865static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2866{
2f1860b8
AD		 2867 struct ixgbe_hw *hw = &adapter->hw;
2868 u32 dmatxctl;
43e69bf0 2869 u32 i;
9a799d71 2870
2f1860b8
AD		 2871 ixgbe_setup_mtqc(adapter);
2872
2873 if (hw->mac.type != ixgbe_mac_82598EB) {
2874 /* DMATXCTL.EN must be before Tx queues are enabled */
2875 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2876 dmatxctl |= IXGBE_DMATXCTL_TE;
2877 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2878 }
2879
9a799d71 2880 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2881 for (i = 0; i < adapter->num_tx_queues; i++)
2882 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2883}
2884
e8e26350 2885#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2886
a6616b42 2887static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2888 struct ixgbe_ring *rx_ring)
cc41ac7c 2889{
cc41ac7c 2890 u32 srrctl;
bf29ee6c 2891 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2892
bd508178
AD		 2893 switch (adapter->hw.mac.type) {
2894 case ixgbe_mac_82598EB: {
2895 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2896 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2897 reg_idx = reg_idx & mask;
cc41ac7c 2898 }
bd508178
AD		 2899 break;
2900 case ixgbe_mac_82599EB:
b93a2226 2901 case ixgbe_mac_X540:
bd508178
AD		 2902 default:
2903 break;
2904 }
2905
bf29ee6c 2906 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2907
2908 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2909 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2910 if (adapter->num_vfs)
2911 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2912
afafd5b0
AD		 2913 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2914 IXGBE_SRRCTL_BSIZEHDR_MASK;
2915
7d637bcc 2916 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2917#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2918 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2919#else
2920 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2921#endif
cc41ac7c 2922 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2923 } else {
afafd5b0
AD		 2924 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2925 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2926 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2927 }
e8e26350 2928
bf29ee6c 2929 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2930}
9a799d71 2931
05abb126 2932static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2933{
05abb126
AD		 2934 struct ixgbe_hw *hw = &adapter->hw;
2935 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2936 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2937 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2938 u32 mrqc = 0, reta = 0;
2939 u32 rxcsum;
2940 int i, j;
8b1c0b24 2941 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2942 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2943
2944 if (tcs)
2945 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2946
05abb126
AD		 2947 /* Fill out hash function seeds */
2948 for (i = 0; i < 10; i++)
2949 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2950
2951 /* Fill out redirection table */
2952 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2953 if (j == maxq)
05abb126
AD		 2954 j = 0;
2955 /* reta = 4-byte sliding window of
2956 * 0x00..(indices-1)(indices-1)00..etc. */
2957 reta = (reta << 8) | (j * 0x11);
2958 if ((i & 3) == 3)
2959 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2960 }
0cefafad 2961
05abb126
AD		 2962 /* Disable indicating checksum in descriptor, enables RSS hash */
2963 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2964 rxcsum |= IXGBE_RXCSUM_PCSD;
2965 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2966
8b1c0b24
JF		 2967 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2968 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2969 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2970 } else {
2971 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2972 | IXGBE_FLAG_SRIOV_ENABLED);
2973
2974 switch (mask) {
2975 case (IXGBE_FLAG_RSS_ENABLED):
2976 if (!tcs)
2977 mrqc = IXGBE_MRQC_RSSEN;
2978 else if (tcs <= 4)
2979 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2980 else
2981 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2982 break;
2983 case (IXGBE_FLAG_SRIOV_ENABLED):
2984 mrqc = IXGBE_MRQC_VMDQEN;
2985 break;
2986 default:
2987 break;
2988 }
0cefafad
JB		 2989 }
2990
05abb126
AD		 2991 /* Perform hash on these packet types */
2992 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2993 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2994 | IXGBE_MRQC_RSS_FIELD_IPV6
2995 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2996
2997 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2998}
2999
b93a2226
DS		 3000/**
3001 * ixgbe_clear_rscctl - disable RSC for the indicated ring
3002 * @adapter: address of board private structure
3003 * @ring: structure containing ring specific data
3004 **/
3005void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
3006 struct ixgbe_ring *ring)
3007{
3008 struct ixgbe_hw *hw = &adapter->hw;
3009 u32 rscctrl;
3010 u8 reg_idx = ring->reg_idx;
3011
3012 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3013 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
3014 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3015}
3016
bb5a9ad2
NS		 3017/**
3018 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3019 * @adapter: address of board private structure
3020 * @index: index of ring to set
bb5a9ad2 3021 **/
b93a2226 3022void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3023 struct ixgbe_ring *ring)
bb5a9ad2 3024{
bb5a9ad2 3025 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3026 u32 rscctrl;
edd2ea55 3027 int rx_buf_len;
bf29ee6c 3028 u8 reg_idx = ring->reg_idx;
7367096a 3029
7d637bcc 3030 if (!ring_is_rsc_enabled(ring))
7367096a 3031 return;
bb5a9ad2 3032
7367096a
AD		 3033 rx_buf_len = ring->rx_buf_len;
3034 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3035 rscctrl |= IXGBE_RSCCTL_RSCEN;
3036 /*
3037 * we must limit the number of descriptors so that the
3038 * total size of max desc * buf_len is not greater
3039 * than 65535
3040 */
7d637bcc 3041 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 3042#if (MAX_SKB_FRAGS > 16)
3043 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3044#elif (MAX_SKB_FRAGS > 8)
3045 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
3046#elif (MAX_SKB_FRAGS > 4)
3047 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
3048#else
3049 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
3050#endif
3051 } else {
3052 if (rx_buf_len < IXGBE_RXBUFFER_4096)
3053 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3054 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
3055 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
3056 else
3057 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
3058 }
7367096a 3059 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3060}
3061
9e10e045
AD		 3062/**
3063 * ixgbe_set_uta - Set unicast filter table address
3064 * @adapter: board private structure
3065 *
3066 * The unicast table address is a register array of 32-bit registers.
3067 * The table is meant to be used in a way similar to how the MTA is used
3068 * however due to certain limitations in the hardware it is necessary to
3069 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
3070 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
3071 **/
3072static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
3073{
3074 struct ixgbe_hw *hw = &adapter->hw;
3075 int i;
3076
3077 /* The UTA table only exists on 82599 hardware and newer */
3078 if (hw->mac.type < ixgbe_mac_82599EB)
3079 return;
3080
3081 /* we only need to do this if VMDq is enabled */
3082 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3083 return;
3084
3085 for (i = 0; i < 128; i++)
3086 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3087}
3088
3089#define IXGBE_MAX_RX_DESC_POLL 10
3090static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3091 struct ixgbe_ring *ring)
3092{
3093 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3094 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3095 u32 rxdctl;
bf29ee6c 3096 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3097
3098 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3099 if (hw->mac.type == ixgbe_mac_82598EB &&
3100 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3101 return;
3102
3103 do {
032b4325 3104 usleep_range(1000, 2000);
9e10e045
AD		 3105 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3106 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3107
3108 if (!wait_loop) {
3109 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3110 "the polling period\n", reg_idx);
3111 }
3112}
3113
2d39d576
YZ		 3114void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3115 struct ixgbe_ring *ring)
3116{
3117 struct ixgbe_hw *hw = &adapter->hw;
3118 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3119 u32 rxdctl;
3120 u8 reg_idx = ring->reg_idx;
3121
3122 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3123 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3124
3125 /* write value back with RXDCTL.ENABLE bit cleared */
3126 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3127
3128 if (hw->mac.type == ixgbe_mac_82598EB &&
3129 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3130 return;
3131
3132 /* the hardware may take up to 100us to really disable the rx queue */
3133 do {
3134 udelay(10);
3135 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3136 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3137
3138 if (!wait_loop) {
3139 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3140 "the polling period\n", reg_idx);
3141 }
3142}
3143
84418e3b
AD		 3144void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3145 struct ixgbe_ring *ring)
acd37177
AD		 3146{
3147 struct ixgbe_hw *hw = &adapter->hw;
3148 u64 rdba = ring->dma;
9e10e045 3149 u32 rxdctl;
bf29ee6c 3150 u8 reg_idx = ring->reg_idx;
acd37177 3151
9e10e045
AD		 3152 /* disable queue to avoid issues while updating state */
3153 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3154 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3155
acd37177
AD		 3156 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3157 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3158 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3159 ring->count * sizeof(union ixgbe_adv_rx_desc));
3160 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3161 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3162 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3163
3164 ixgbe_configure_srrctl(adapter, ring);
3165 ixgbe_configure_rscctl(adapter, ring);
3166
e9f98072
GR		 3167 /* If operating in IOV mode set RLPML for X540 */
3168 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3169 hw->mac.type == ixgbe_mac_X540) {
3170 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3171 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3172 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3173 }
3174
9e10e045
AD		 3175 if (hw->mac.type == ixgbe_mac_82598EB) {
3176 /*
3177 * enable cache line friendly hardware writes:
3178 * PTHRESH=32 descriptors (half the internal cache),
3179 * this also removes ugly rx_no_buffer_count increment
3180 * HTHRESH=4 descriptors (to minimize latency on fetch)
3181 * WTHRESH=8 burst writeback up to two cache lines
3182 */
3183 rxdctl &= ~0x3FFFFF;
3184 rxdctl |= 0x080420;
3185 }
3186
3187 /* enable receive descriptor ring */
3188 rxdctl |= IXGBE_RXDCTL_ENABLE;
3189 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3190
3191 ixgbe_rx_desc_queue_enable(adapter, ring);
fc77dc3c 3192 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 3193}
3194
48654521
AD		 3195static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3196{
3197 struct ixgbe_hw *hw = &adapter->hw;
3198 int p;
3199
3200 /* PSRTYPE must be initialized in non 82598 adapters */
3201 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3202 IXGBE_PSRTYPE_UDPHDR |
3203 IXGBE_PSRTYPE_IPV4HDR |
48654521 3204 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3205 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3206
3207 if (hw->mac.type == ixgbe_mac_82598EB)
3208 return;
3209
3210 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3211 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3212
3213 for (p = 0; p < adapter->num_rx_pools; p++)
3214 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3215 psrtype);
3216}
3217
f5b4a52e
AD		 3218static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3219{
3220 struct ixgbe_hw *hw = &adapter->hw;
3221 u32 gcr_ext;
3222 u32 vt_reg_bits;
3223 u32 reg_offset, vf_shift;
3224 u32 vmdctl;
3225
3226 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3227 return;
3228
3229 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3230 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3231 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3232 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3233
3234 vf_shift = adapter->num_vfs % 32;
3235 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3236
3237 /* Enable only the PF's pool for Tx/Rx */
3238 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3239 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3240 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3241 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3242 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3243
3244 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3245 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3246
3247 /*
3248 * Set up VF register offsets for selected VT Mode,
3249 * i.e. 32 or 64 VFs for SR-IOV
3250 */
3251 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3252 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3253 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3254 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3255
3256 /* enable Tx loopback for VF/PF communication */
3257 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 3258 /* Enable MAC Anti-Spoofing */
a1cbb15c
GR		 3259 hw->mac.ops.set_mac_anti_spoofing(hw,
3260 (adapter->antispoofing_enabled =
3261 (adapter->num_vfs != 0)),
a985b6c3 3262 adapter->num_vfs);
f5b4a52e
AD		 3263}
3264
477de6ed 3265static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3266{
9a799d71
AK		 3267 struct ixgbe_hw *hw = &adapter->hw;
3268 struct net_device *netdev = adapter->netdev;
3269 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3270 int rx_buf_len;
477de6ed
AD		 3271 struct ixgbe_ring *rx_ring;
3272 int i;
3273 u32 mhadd, hlreg0;
48654521 3274
9a799d71 3275 /* Decide whether to use packet split mode or not */
a124339a
DS		 3276 /* On by default */
3277 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3278
1cdd1ec8 3279 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 3280 if (adapter->num_vfs)
3281 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3282
3283 /* Disable packet split due to 82599 erratum #45 */
3284 if (hw->mac.type == ixgbe_mac_82599EB)
3285 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 3286
3287 /* Set the RX buffer length according to the mode */
3288 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 3289 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 3290 } else {
0c19d6af 3291 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 3292 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 3293 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 3294 else
477de6ed 3295 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 3296 }
3297
63f39bd1 3298#ifdef IXGBE_FCOE
477de6ed
AD		 3299 /* adjust max frame to be able to do baby jumbo for FCoE */
3300 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3301 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3302 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3303
477de6ed
AD		 3304#endif /* IXGBE_FCOE */
3305 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3306 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3307 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3308 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3309
3310 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3311 }
3312
3313 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3314 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3315 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3316 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3317
0cefafad
JB		 3318 /*
3319 * Setup the HW Rx Head and Tail Descriptor Pointers and
3320 * the Base and Length of the Rx Descriptor Ring
3321 */
9a799d71 3322 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3323 rx_ring = adapter->rx_ring[i];
a6616b42 3324 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3325
6e455b89 3326 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3327 set_ring_ps_enabled(rx_ring);
3328 else
3329 clear_ring_ps_enabled(rx_ring);
3330
3331 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3332 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3333 else
7d637bcc 3334 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3335
63f39bd1 3336#ifdef IXGBE_FCOE
e8e9f696 3337 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3338 struct ixgbe_ring_feature *f;
3339 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3340 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3341 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3342 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3343 rx_ring->rx_buf_len =
e8e9f696 3344 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3345 } else if (!ring_is_rsc_enabled(rx_ring) &&
3346 !ring_is_ps_enabled(rx_ring)) {
3347 rx_ring->rx_buf_len =
3348 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3349 }
63f39bd1 3350 }
63f39bd1 3351#endif /* IXGBE_FCOE */
477de6ed 3352 }
477de6ed
AD		 3353}
3354
7367096a
AD		 3355static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3356{
3357 struct ixgbe_hw *hw = &adapter->hw;
3358 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3359
3360 switch (hw->mac.type) {
3361 case ixgbe_mac_82598EB:
3362 /*
3363 * For VMDq support of different descriptor types or
3364 * buffer sizes through the use of multiple SRRCTL
3365 * registers, RDRXCTL.MVMEN must be set to 1
3366 *
3367 * also, the manual doesn't mention it clearly but DCA hints
3368 * will only use queue 0's tags unless this bit is set. Side
3369 * effects of setting this bit are only that SRRCTL must be
3370 * fully programmed [0..15]
3371 */
3372 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3373 break;
3374 case ixgbe_mac_82599EB:
b93a2226 3375 case ixgbe_mac_X540:
7367096a
AD		 3376 /* Disable RSC for ACK packets */
3377 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3378 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3379 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3380 /* hardware requires some bits to be set by default */
3381 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3382 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3383 break;
3384 default:
3385 /* We should do nothing since we don't know this hardware */
3386 return;
3387 }
3388
3389 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3390}
3391
477de6ed
AD		 3392/**
3393 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3394 * @adapter: board private structure
3395 *
3396 * Configure the Rx unit of the MAC after a reset.
3397 **/
3398static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3399{
3400 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3401 int i;
3402 u32 rxctrl;
477de6ed
AD		 3403
3404 /* disable receives while setting up the descriptors */
3405 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3406 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3407
3408 ixgbe_setup_psrtype(adapter);
7367096a 3409 ixgbe_setup_rdrxctl(adapter);
477de6ed 3410
9e10e045 3411 /* Program registers for the distribution of queues */
f5b4a52e 3412 ixgbe_setup_mrqc(adapter);
f5b4a52e 3413
9e10e045
AD		 3414 ixgbe_set_uta(adapter);
3415
477de6ed
AD		 3416 /* set_rx_buffer_len must be called before ring initialization */
3417 ixgbe_set_rx_buffer_len(adapter);
3418
3419 /*
3420 * Setup the HW Rx Head and Tail Descriptor Pointers and
3421 * the Base and Length of the Rx Descriptor Ring
3422 */
9e10e045
AD		 3423 for (i = 0; i < adapter->num_rx_queues; i++)
3424 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3425
9e10e045
AD		 3426 /* disable drop enable for 82598 parts */
3427 if (hw->mac.type == ixgbe_mac_82598EB)
3428 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3429
3430 /* enable all receives */
3431 rxctrl |= IXGBE_RXCTRL_RXEN;
3432 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3433}
3434
068c89b0
DS		 3435static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3436{
3437 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3438 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3439 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3440
3441 /* add VID to filter table */
1ada1b1b 3442 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3443 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3444}
3445
3446static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3447{
3448 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3449 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3450 int pool_ndx = adapter->num_vfs;
068c89b0 3451
068c89b0 3452 /* remove VID from filter table */
1ada1b1b 3453 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3454 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3455}
3456
5f6c0181
JB		 3457/**
3458 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3459 * @adapter: driver data
3460 */
3461static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3462{
3463 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3464 u32 vlnctrl;
3465
3466 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3467 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3468 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3469}
3470
3471/**
3472 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3473 * @adapter: driver data
3474 */
3475static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3476{
3477 struct ixgbe_hw *hw = &adapter->hw;
3478 u32 vlnctrl;
3479
3480 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3481 vlnctrl |= IXGBE_VLNCTRL_VFE;
3482 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3483 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3484}
3485
3486/**
3487 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3488 * @adapter: driver data
3489 */
3490static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3491{
3492 struct ixgbe_hw *hw = &adapter->hw;
3493 u32 vlnctrl;
5f6c0181
JB		 3494 int i, j;
3495
3496 switch (hw->mac.type) {
3497 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3498 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3499 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3500 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3501 break;
3502 case ixgbe_mac_82599EB:
b93a2226 3503 case ixgbe_mac_X540:
5f6c0181
JB		 3504 for (i = 0; i < adapter->num_rx_queues; i++) {
3505 j = adapter->rx_ring[i]->reg_idx;
3506 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3507 vlnctrl &= ~IXGBE_RXDCTL_VME;
3508 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3509 }
3510 break;
3511 default:
3512 break;
3513 }
3514}
3515
3516/**
f62bbb5e 3517 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3518 * @adapter: driver data
3519 */
f62bbb5e 3520static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3521{
3522 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3523 u32 vlnctrl;
5f6c0181
JB		 3524 int i, j;
3525
3526 switch (hw->mac.type) {
3527 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3528 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3529 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3530 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3531 break;
3532 case ixgbe_mac_82599EB:
b93a2226 3533 case ixgbe_mac_X540:
5f6c0181
JB		 3534 for (i = 0; i < adapter->num_rx_queues; i++) {
3535 j = adapter->rx_ring[i]->reg_idx;
3536 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3537 vlnctrl |= IXGBE_RXDCTL_VME;
3538 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3539 }
3540 break;
3541 default:
3542 break;
3543 }
3544}
3545
9a799d71
AK		 3546static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3547{
f62bbb5e 3548 u16 vid;
9a799d71 3549
f62bbb5e
JG		 3550 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3551
3552 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3553 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3554}
3555
2850062a
AD		 3556/**
3557 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3558 * @netdev: network interface device structure
3559 *
3560 * Writes unicast address list to the RAR table.
3561 * Returns: -ENOMEM on failure/insufficient address space
3562 * 0 on no addresses written
3563 * X on writing X addresses to the RAR table
3564 **/
3565static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3566{
3567 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3568 struct ixgbe_hw *hw = &adapter->hw;
3569 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3570 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3571 int count = 0;
3572
3573 /* return ENOMEM indicating insufficient memory for addresses */
3574 if (netdev_uc_count(netdev) > rar_entries)
3575 return -ENOMEM;
3576
3577 if (!netdev_uc_empty(netdev) && rar_entries) {
3578 struct netdev_hw_addr *ha;
3579 /* return error if we do not support writing to RAR table */
3580 if (!hw->mac.ops.set_rar)
3581 return -ENOMEM;
3582
3583 netdev_for_each_uc_addr(ha, netdev) {
3584 if (!rar_entries)
3585 break;
3586 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3587 vfn, IXGBE_RAH_AV);
3588 count++;
3589 }
3590 }
3591 /* write the addresses in reverse order to avoid write combining */
3592 for (; rar_entries > 0 ; rar_entries--)
3593 hw->mac.ops.clear_rar(hw, rar_entries);
3594
3595 return count;
3596}
3597
9a799d71 3598/**
2c5645cf 3599 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3600 * @netdev: network interface device structure
3601 *
2c5645cf
CL		 3602 * The set_rx_method entry point is called whenever the unicast/multicast
3603 * address list or the network interface flags are updated. This routine is
3604 * responsible for configuring the hardware for proper unicast, multicast and
3605 * promiscuous mode.
9a799d71 3606 **/
7f870475 3607void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3608{
3609 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3610 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3611 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3612 int count;
9a799d71
AK		 3613
3614 /* Check for Promiscuous and All Multicast modes */
3615
3616 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3617
f5dc442b
AD		 3618 /* set all bits that we expect to always be set */
3619 fctrl |= IXGBE_FCTRL_BAM;
3620 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3621 fctrl |= IXGBE_FCTRL_PMCF;
3622
2850062a
AD		 3623 /* clear the bits we are changing the status of */
3624 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3625
9a799d71 3626 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3627 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3628 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3629 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3630 /* don't hardware filter vlans in promisc mode */
3631 ixgbe_vlan_filter_disable(adapter);
9a799d71 3632 } else {
746b9f02
PM		 3633 if (netdev->flags & IFF_ALLMULTI) {
3634 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3635 vmolr |= IXGBE_VMOLR_MPE;
3636 } else {
3637 /*
3638 * Write addresses to the MTA, if the attempt fails
25985edc 3639 * then we should just turn on promiscuous mode so
2850062a
AD		 3640 * that we can at least receive multicast traffic
3641 */
3642 hw->mac.ops.update_mc_addr_list(hw, netdev);
3643 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3644 }
5f6c0181 3645 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3646 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3647 /*
3648 * Write addresses to available RAR registers, if there is not
3649 * sufficient space to store all the addresses then enable
25985edc 3650 * unicast promiscuous mode
2850062a
AD		 3651 */
3652 count = ixgbe_write_uc_addr_list(netdev);
3653 if (count < 0) {
3654 fctrl |= IXGBE_FCTRL_UPE;
3655 vmolr |= IXGBE_VMOLR_ROPE;
3656 }
9a799d71
AK		 3657 }
3658
2850062a 3659 if (adapter->num_vfs) {
1cdd1ec8 3660 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3661 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3662 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3663 IXGBE_VMOLR_ROPE);
3664 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3665 }
3666
3667 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3668
3669 if (netdev->features & NETIF_F_HW_VLAN_RX)
3670 ixgbe_vlan_strip_enable(adapter);
3671 else
3672 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3673}
3674
021230d4
AV		 3675static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3676{
3677 int q_idx;
3678 struct ixgbe_q_vector *q_vector;
3679 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3680
3681 /* legacy and MSI only use one vector */
3682 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3683 q_vectors = 1;
3684
3685 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3686 struct napi_struct *napi;
7a921c93 3687 q_vector = adapter->q_vector[q_idx];
f0848276 3688 napi = &q_vector->napi;
91281fd3
AD		 3689 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3690 if (!q_vector->rxr_count || !q_vector->txr_count) {
3691 if (q_vector->txr_count == 1)
3692 napi->poll = &ixgbe_clean_txonly;
3693 else if (q_vector->rxr_count == 1)
3694 napi->poll = &ixgbe_clean_rxonly;
3695 }
3696 }
f0848276
JB		 3697
3698 napi_enable(napi);
021230d4
AV		 3699 }
3700}
3701
3702static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3703{
3704 int q_idx;
3705 struct ixgbe_q_vector *q_vector;
3706 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3707
3708 /* legacy and MSI only use one vector */
3709 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3710 q_vectors = 1;
3711
3712 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3713 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3714 napi_disable(&q_vector->napi);
3715 }
3716}
3717
7a6b6f51 3718#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3719/*
3720 * ixgbe_configure_dcb - Configure DCB hardware
3721 * @adapter: ixgbe adapter struct
3722 *
3723 * This is called by the driver on open to configure the DCB hardware.
3724 * This is also called by the gennetlink interface when reconfiguring
3725 * the DCB state.
3726 */
3727static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3728{
3729 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3730 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3731
67ebd791
AD		 3732 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3733 if (hw->mac.type == ixgbe_mac_82598EB)
3734 netif_set_gso_max_size(adapter->netdev, 65536);
3735 return;
3736 }
3737
3738 if (hw->mac.type == ixgbe_mac_82598EB)
3739 netif_set_gso_max_size(adapter->netdev, 32768);
3740
2f90b865 3741
2f90b865 3742 /* Enable VLAN tag insert/strip */
f62bbb5e 3743 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3744
2f90b865 3745 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3746
3747 /* reconfigure the hardware */
6f70f6ac 3748 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3749#ifdef CONFIG_FCOE
3750 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3751 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3752#endif
3753 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3754 DCB_TX_CONFIG);
3755 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3756 DCB_RX_CONFIG);
3757 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3758 } else {
3759 struct net_device *dev = adapter->netdev;
3760
3761 if (adapter->ixgbe_ieee_ets)
3762 dev->dcbnl_ops->ieee_setets(dev,
3763 adapter->ixgbe_ieee_ets);
3764 if (adapter->ixgbe_ieee_pfc)
3765 dev->dcbnl_ops->ieee_setpfc(dev,
3766 adapter->ixgbe_ieee_pfc);
3767 }
8187cd48
JF		 3768
3769 /* Enable RSS Hash per TC */
3770 if (hw->mac.type != ixgbe_mac_82598EB) {
3771 int i;
3772 u32 reg = 0;
3773
3774 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3775 u8 msb = 0;
3776 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3777
3778 while (cnt >>= 1)
3779 msb++;
3780
3781 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3782 }
3783 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3784 }
2f90b865
AD		 3785}
3786
3787#endif
80605c65
JF		 3788
3789static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3790{
3791 int hdrm = 0;
3792 int num_tc = netdev_get_num_tc(adapter->netdev);
3793 struct ixgbe_hw *hw = &adapter->hw;
3794
3795 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3796 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3797 hdrm = 64 << adapter->fdir_pballoc;
3798
3799 hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3800}
3801
9a799d71
AK		 3802static void ixgbe_configure(struct ixgbe_adapter *adapter)
3803{
3804 struct net_device *netdev = adapter->netdev;
c4cf55e5 3805 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3806 int i;
3807
80605c65 3808 ixgbe_configure_pb(adapter);
7a6b6f51 3809#ifdef CONFIG_IXGBE_DCB
67ebd791 3810 ixgbe_configure_dcb(adapter);
2f90b865 3811#endif
9a799d71 3812
f62bbb5e
JG		 3813 ixgbe_set_rx_mode(netdev);
3814 ixgbe_restore_vlan(adapter);
3815
eacd73f7
YZ		 3816#ifdef IXGBE_FCOE
3817 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3818 ixgbe_configure_fcoe(adapter);
3819
3820#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3821 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3822 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3823 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3824 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3825 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3826 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3827 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3828 }
933d41f1 3829 ixgbe_configure_virtualization(adapter);
c4cf55e5 3830
9a799d71
AK		 3831 ixgbe_configure_tx(adapter);
3832 ixgbe_configure_rx(adapter);
9a799d71
AK		 3833}
3834
e8e26350
PW		 3835static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3836{
3837 switch (hw->phy.type) {
3838 case ixgbe_phy_sfp_avago:
3839 case ixgbe_phy_sfp_ftl:
3840 case ixgbe_phy_sfp_intel:
3841 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3842 case ixgbe_phy_sfp_passive_tyco:
3843 case ixgbe_phy_sfp_passive_unknown:
3844 case ixgbe_phy_sfp_active_unknown:
3845 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3846 return true;
3847 default:
3848 return false;
3849 }
3850}
3851
0ecc061d 3852/**
e8e26350
PW		 3853 * ixgbe_sfp_link_config - set up SFP+ link
3854 * @adapter: pointer to private adapter struct
3855 **/
3856static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3857{
7086400d
AD		 3858 /*
3859 * We are assuming the worst case scenerio here, and that
3860 * is that an SFP was inserted/removed after the reset
3861 * but before SFP detection was enabled. As such the best
3862 * solution is to just start searching as soon as we start
3863 */
3864 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3865 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3866
7086400d 3867 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3868}
3869
3870/**
3871 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3872 * @hw: pointer to private hardware struct
3873 *
3874 * Returns 0 on success, negative on failure
3875 **/
e8e26350 3876static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3877{
3878 u32 autoneg;
8620a103 3879 bool negotiation, link_up = false;
0ecc061d
PWJ		 3880 u32 ret = IXGBE_ERR_LINK_SETUP;
3881
3882 if (hw->mac.ops.check_link)
3883 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3884
3885 if (ret)
3886 goto link_cfg_out;
3887
0b0c2b31
ET		 3888 autoneg = hw->phy.autoneg_advertised;
3889 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3890 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3891 &negotiation);
0ecc061d
PWJ		 3892 if (ret)
3893 goto link_cfg_out;
3894
8620a103
MC		 3895 if (hw->mac.ops.setup_link)
3896 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3897link_cfg_out:
3898 return ret;
3899}
3900
a34bcfff 3901static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3902{
9a799d71 3903 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3904 u32 gpie = 0;
9a799d71 3905
9b471446 3906 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3907 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3908 IXGBE_GPIE_OCD;
3909 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3910 /*
3911 * use EIAM to auto-mask when MSI-X interrupt is asserted
3912 * this saves a register write for every interrupt
3913 */
3914 switch (hw->mac.type) {
3915 case ixgbe_mac_82598EB:
3916 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3917 break;
9b471446 3918 case ixgbe_mac_82599EB:
b93a2226
DS		 3919 case ixgbe_mac_X540:
3920 default:
9b471446
JB		 3921 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3922 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3923 break;
3924 }
3925 } else {
021230d4
AV		 3926 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3927 * specifically only auto mask tx and rx interrupts */
3928 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3929 }
9a799d71 3930
a34bcfff
AD		 3931 /* XXX: to interrupt immediately for EICS writes, enable this */
3932 /* gpie |= IXGBE_GPIE_EIMEN; */
3933
3934 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3935 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3936 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3937 }
3938
a34bcfff
AD		 3939 /* Enable fan failure interrupt */
3940 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3941 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3942
2698b208 3943 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3944 gpie |= IXGBE_SDP1_GPIEN;
3945 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3946 }
a34bcfff
AD		 3947
3948 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3949}
3950
3951static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3952{
3953 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3954 int err;
a34bcfff
AD		 3955 u32 ctrl_ext;
3956
3957 ixgbe_get_hw_control(adapter);
3958 ixgbe_setup_gpie(adapter);
e8e26350 3959
9a799d71
AK		 3960 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3961 ixgbe_configure_msix(adapter);
3962 else
3963 ixgbe_configure_msi_and_legacy(adapter);
3964
c6ecf39a
DS		 3965 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3966 if (hw->mac.ops.enable_tx_laser &&
3967 ((hw->phy.multispeed_fiber) ||
9f911707 3968 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3969 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3970 hw->mac.ops.enable_tx_laser(hw);
3971
9a799d71 3972 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3973 ixgbe_napi_enable_all(adapter);
3974
73c4b7cd
AD		 3975 if (ixgbe_is_sfp(hw)) {
3976 ixgbe_sfp_link_config(adapter);
3977 } else {
3978 err = ixgbe_non_sfp_link_config(hw);
3979 if (err)
3980 e_err(probe, "link_config FAILED %d\n", err);
3981 }
3982
021230d4
AV		 3983 /* clear any pending interrupts, may auto mask */
3984 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3985 ixgbe_irq_enable(adapter, true, true);
9a799d71 3986
bf069c97
DS		 3987 /*
3988 * If this adapter has a fan, check to see if we had a failure
3989 * before we enabled the interrupt.
3990 */
3991 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3992 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3993 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3994 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3995 }
3996
1da100bb 3997 /* enable transmits */
477de6ed 3998 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3999
9a799d71
AK		 4000 /* bring the link up in the watchdog, this could race with our first
4001 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4002 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4003 adapter->link_check_timeout = jiffies;
7086400d 4004 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4005
4006 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4007 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4008 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4009 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4010
9a799d71
AK		 4011 return 0;
4012}
4013
d4f80882
AV		 4014void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4015{
4016 WARN_ON(in_interrupt());
7086400d
AD		 4017 /* put off any impending NetWatchDogTimeout */
4018 adapter->netdev->trans_start = jiffies;
4019
d4f80882 4020 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4021 usleep_range(1000, 2000);
d4f80882 4022 ixgbe_down(adapter);
5809a1ae
GR		 4023 /*
4024 * If SR-IOV enabled then wait a bit before bringing the adapter
4025 * back up to give the VFs time to respond to the reset. The
4026 * two second wait is based upon the watchdog timer cycle in
4027 * the VF driver.
4028 */
4029 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4030 msleep(2000);
d4f80882
AV		 4031 ixgbe_up(adapter);
4032 clear_bit(__IXGBE_RESETTING, &adapter->state);
4033}
4034
9a799d71
AK		 4035int ixgbe_up(struct ixgbe_adapter *adapter)
4036{
4037 /* hardware has been reset, we need to reload some things */
4038 ixgbe_configure(adapter);
4039
4040 return ixgbe_up_complete(adapter);
4041}
4042
4043void ixgbe_reset(struct ixgbe_adapter *adapter)
4044{
c44ade9e 4045 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4046 int err;
4047
7086400d
AD		 4048 /* lock SFP init bit to prevent race conditions with the watchdog */
4049 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4050 usleep_range(1000, 2000);
4051
4052 /* clear all SFP and link config related flags while holding SFP_INIT */
4053 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4054 IXGBE_FLAG2_SFP_NEEDS_RESET);
4055 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4056
8ca783ab 4057 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4058 switch (err) {
4059 case 0:
4060 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4061 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4062 break;
4063 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4064 e_dev_err("master disable timed out\n");
da4dd0f7 4065 break;
794caeb2
PWJ		 4066 case IXGBE_ERR_EEPROM_VERSION:
4067 /* We are running on a pre-production device, log a warning */
849c4542
ET		 4068 e_dev_warn("This device is a pre-production adapter/LOM. "
4069 "Please be aware there may be issuesassociated with "
4070 "your hardware. If you are experiencing problems "
4071 "please contact your Intel or hardware "
4072 "representative who provided you with this "
4073 "hardware.\n");
794caeb2 4074 break;
da4dd0f7 4075 default:
849c4542 4076 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4077 }
9a799d71 4078
7086400d
AD		 4079 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4080
9a799d71 4081 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 4082 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4083 IXGBE_RAH_AV);
9a799d71
AK		 4084}
4085
9a799d71
AK		 4086/**
4087 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4088 * @rx_ring: ring to free buffers from
4089 **/
b6ec895e 4090static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4091{
b6ec895e 4092 struct device *dev = rx_ring->dev;
9a799d71 4093 unsigned long size;
b6ec895e 4094 u16 i;
9a799d71 4095
84418e3b
AD		 4096 /* ring already cleared, nothing to do */
4097 if (!rx_ring->rx_buffer_info)
4098 return;
9a799d71 4099
84418e3b 4100 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 4101 for (i = 0; i < rx_ring->count; i++) {
4102 struct ixgbe_rx_buffer *rx_buffer_info;
4103
4104 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4105 if (rx_buffer_info->dma) {
b6ec895e 4106 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 4107 rx_ring->rx_buf_len,
1b507730 4108 DMA_FROM_DEVICE);
9a799d71
AK		 4109 rx_buffer_info->dma = 0;
4110 }
4111 if (rx_buffer_info->skb) {
f8212f97 4112 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 4113 rx_buffer_info->skb = NULL;
f8212f97
AD		 4114 do {
4115 struct sk_buff *this = skb;
e8171aaa 4116 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 4117 dma_unmap_single(dev,
1b507730 4118 IXGBE_RSC_CB(this)->dma,
e8e9f696 4119 rx_ring->rx_buf_len,
1b507730 4120 DMA_FROM_DEVICE);
fd3686a8 4121 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 4122 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 4123 }
f8212f97
AD		 4124 skb = skb->prev;
4125 dev_kfree_skb(this);
4126 } while (skb);
9a799d71
AK		 4127 }
4128 if (!rx_buffer_info->page)
4129 continue;
4f57ca6e 4130 if (rx_buffer_info->page_dma) {
b6ec895e 4131 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 4132 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 4133 rx_buffer_info->page_dma = 0;
4134 }
9a799d71
AK		 4135 put_page(rx_buffer_info->page);
4136 rx_buffer_info->page = NULL;
762f4c57 4137 rx_buffer_info->page_offset = 0;
9a799d71
AK		 4138 }
4139
4140 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4141 memset(rx_ring->rx_buffer_info, 0, size);
4142
4143 /* Zero out the descriptor ring */
4144 memset(rx_ring->desc, 0, rx_ring->size);
4145
4146 rx_ring->next_to_clean = 0;
4147 rx_ring->next_to_use = 0;
9a799d71
AK		 4148}
4149
4150/**
4151 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4152 * @tx_ring: ring to be cleaned
4153 **/
b6ec895e 4154static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4155{
4156 struct ixgbe_tx_buffer *tx_buffer_info;
4157 unsigned long size;
b6ec895e 4158 u16 i;
9a799d71 4159
84418e3b
AD		 4160 /* ring already cleared, nothing to do */
4161 if (!tx_ring->tx_buffer_info)
4162 return;
9a799d71 4163
84418e3b 4164 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4165 for (i = 0; i < tx_ring->count; i++) {
4166 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4167 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4168 }
4169
4170 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4171 memset(tx_ring->tx_buffer_info, 0, size);
4172
4173 /* Zero out the descriptor ring */
4174 memset(tx_ring->desc, 0, tx_ring->size);
4175
4176 tx_ring->next_to_use = 0;
4177 tx_ring->next_to_clean = 0;
9a799d71
AK		 4178}
4179
4180/**
021230d4 4181 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4182 * @adapter: board private structure
4183 **/
021230d4 4184static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4185{
4186 int i;
4187
021230d4 4188 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4189 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4190}
4191
4192/**
021230d4 4193 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4194 * @adapter: board private structure
4195 **/
021230d4 4196static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4197{
4198 int i;
4199
021230d4 4200 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4201 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4202}
4203
4204void ixgbe_down(struct ixgbe_adapter *adapter)
4205{
4206 struct net_device *netdev = adapter->netdev;
7f821875 4207 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4208 u32 rxctrl;
bf29ee6c 4209 int i;
b25ebfd2 4210 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 4211
4212 /* signal that we are down to the interrupt handler */
4213 set_bit(__IXGBE_DOWN, &adapter->state);
4214
4215 /* disable receives */
7f821875
JB		 4216 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4217 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4218
2d39d576
YZ		 4219 /* disable all enabled rx queues */
4220 for (i = 0; i < adapter->num_rx_queues; i++)
4221 /* this call also flushes the previous write */
4222 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4223
032b4325 4224 usleep_range(10000, 20000);
9a799d71 4225
7f821875
JB		 4226 netif_tx_stop_all_queues(netdev);
4227
7086400d 4228 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4229 netif_carrier_off(netdev);
4230 netif_tx_disable(netdev);
4231
4232 ixgbe_irq_disable(adapter);
4233
4234 ixgbe_napi_disable_all(adapter);
4235
d034acf1
AD		 4236 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4237 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4238 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4239
4240 del_timer_sync(&adapter->service_timer);
4241
34cecbbf
AD		 4242 /* disable receive for all VFs and wait one second */
4243 if (adapter->num_vfs) {
4244 /* ping all the active vfs to let them know we are going down */
4245 ixgbe_ping_all_vfs(adapter);
4246
4247 /* Disable all VFTE/VFRE TX/RX */
4248 ixgbe_disable_tx_rx(adapter);
4249
4250 /* Mark all the VFs as inactive */
4251 for (i = 0 ; i < adapter->num_vfs; i++)
4252 adapter->vfinfo[i].clear_to_send = 0;
4253 }
4254
b25ebfd2
PW		 4255 /* Cleanup the affinity_hint CPU mask memory and callback */
4256 for (i = 0; i < num_q_vectors; i++) {
4257 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4258 /* clear the affinity_mask in the IRQ descriptor */
4259 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4260 /* release the CPU mask memory */
4261 free_cpumask_var(q_vector->affinity_mask);
4262 }
4263
7f821875
JB		 4264 /* disable transmits in the hardware now that interrupts are off */
4265 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4266 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4267 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4268 }
34cecbbf
AD		 4269
4270 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4271 switch (hw->mac.type) {
4272 case ixgbe_mac_82599EB:
b93a2226 4273 case ixgbe_mac_X540:
88512539 4274 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4275 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4276 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4277 break;
4278 default:
4279 break;
4280 }
7f821875 4281
6f4a0e45
PL		 4282 if (!pci_channel_offline(adapter->pdev))
4283 ixgbe_reset(adapter);
c6ecf39a
DS		 4284
4285 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4286 if (hw->mac.ops.disable_tx_laser &&
4287 ((hw->phy.multispeed_fiber) ||
9f911707 4288 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4289 (hw->mac.type == ixgbe_mac_82599EB))))
4290 hw->mac.ops.disable_tx_laser(hw);
4291
9a799d71
AK		 4292 ixgbe_clean_all_tx_rings(adapter);
4293 ixgbe_clean_all_rx_rings(adapter);
4294
5dd2d332 4295#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4296 /* since we reset the hardware DCA settings were cleared */
e35ec126 4297 ixgbe_setup_dca(adapter);
96b0e0f6 4298#endif
9a799d71
AK		 4299}
4300
9a799d71 4301/**
021230d4
AV		 4302 * ixgbe_poll - NAPI Rx polling callback
4303 * @napi: structure for representing this polling device
4304 * @budget: how many packets driver is allowed to clean
4305 *
4306 * This function is used for legacy and MSI, NAPI mode
9a799d71 4307 **/
021230d4 4308static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4309{
9a1a69ad 4310 struct ixgbe_q_vector *q_vector =
e8e9f696 4311 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4312 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 4313 int tx_clean_complete, work_done = 0;
9a799d71 4314
5dd2d332 4315#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4316 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4317 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4318#endif
4319
4a0b9ca0
PW		 4320 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4321 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 4322
9a1a69ad 4323 if (!tx_clean_complete)
d2c7ddd6
DM		 4324 work_done = budget;
4325
53e52c72
DM		 4326 /* If budget not fully consumed, exit the polling mode */
4327 if (work_done < budget) {
288379f0 4328 napi_complete(napi);
f7554a2b 4329 if (adapter->rx_itr_setting & 1)
f494e8fa 4330 ixgbe_set_itr(adapter);
d4f80882 4331 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 4332 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 4333 }
9a799d71
AK		 4334 return work_done;
4335}
4336
4337/**
4338 * ixgbe_tx_timeout - Respond to a Tx Hang
4339 * @netdev: network interface device structure
4340 **/
4341static void ixgbe_tx_timeout(struct net_device *netdev)
4342{
4343 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4344
4345 /* Do the reset outside of interrupt context */
c83c6cbd 4346 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4347}
4348
4df10466
JB		 4349/**
4350 * ixgbe_set_rss_queues: Allocate queues for RSS
4351 * @adapter: board private structure to initialize
4352 *
4353 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4354 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4355 *
4356 **/
bc97114d
PWJ		 4357static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4358{
4359 bool ret = false;
0cefafad 4360 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4361
4362 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4363 f->mask = 0xF;
4364 adapter->num_rx_queues = f->indices;
4365 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4366 ret = true;
4367 } else {
bc97114d 4368 ret = false;
b9804972
JB		 4369 }
4370
bc97114d
PWJ		 4371 return ret;
4372}
4373
c4cf55e5
PWJ		 4374/**
4375 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4376 * @adapter: board private structure to initialize
4377 *
4378 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4379 * to the original CPU that initiated the Tx session. This runs in addition
4380 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4381 * Rx load across CPUs using RSS.
4382 *
4383 **/
e8e9f696 4384static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4385{
4386 bool ret = false;
4387 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4388
4389 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4390 f_fdir->mask = 0;
4391
4392 /* Flow Director must have RSS enabled */
4393 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4394 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4395 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4396 adapter->num_tx_queues = f_fdir->indices;
4397 adapter->num_rx_queues = f_fdir->indices;
4398 ret = true;
4399 } else {
4400 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4401 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4402 }
4403 return ret;
4404}
4405
0331a832
YZ		 4406#ifdef IXGBE_FCOE
4407/**
4408 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4409 * @adapter: board private structure to initialize
4410 *
4411 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4412 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4413 * rx queues out of the max number of rx queues, instead, it is used as the
4414 * index of the first rx queue used by FCoE.
4415 *
4416 **/
4417static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4418{
0331a832
YZ		 4419 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4420
e5b64635
JF		 4421 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4422 return false;
4423
e901acd6 4424 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4425
e901acd6
JF		 4426 adapter->num_rx_queues = 1;
4427 adapter->num_tx_queues = 1;
e5b64635 4428
e901acd6
JF		 4429 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4430 e_info(probe, "FCoE enabled with RSS\n");
4431 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4432 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4433 ixgbe_set_fdir_queues(adapter);
4434 else
4435 ixgbe_set_rss_queues(adapter);
e5b64635 4436 }
e901acd6
JF		 4437 /* adding FCoE rx rings to the end */
4438 f->mask = adapter->num_rx_queues;
4439 adapter->num_rx_queues += f->indices;
4440 adapter->num_tx_queues += f->indices;
0331a832 4441
e5b64635
JF		 4442 return true;
4443}
4444#endif /* IXGBE_FCOE */
4445
e901acd6
JF		 4446/* Artificial max queue cap per traffic class in DCB mode */
4447#define DCB_QUEUE_CAP 8
4448
e5b64635
JF		 4449#ifdef CONFIG_IXGBE_DCB
4450static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4451{
e901acd6
JF		 4452 int per_tc_q, q, i, offset = 0;
4453 struct net_device *dev = adapter->netdev;
4454 int tcs = netdev_get_num_tc(dev);
e5b64635 4455
e901acd6
JF		 4456 if (!tcs)
4457 return false;
e5b64635 4458
e901acd6
JF		 4459 /* Map queue offset and counts onto allocated tx queues */
4460 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4461 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4462
8b1c0b24 4463 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4464 netdev_set_prio_tc_map(dev, i, i);
4465 netdev_set_tc_queue(dev, i, q, offset);
4466 offset += q;
0331a832
YZ		 4467 }
4468
e901acd6
JF		 4469 adapter->num_tx_queues = q * tcs;
4470 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4471
4472#ifdef IXGBE_FCOE
e901acd6
JF		 4473 /* FCoE enabled queues require special configuration indexed
4474 * by feature specific indices and mask. Here we map FCoE
4475 * indices onto the DCB queue pairs allowing FCoE to own
4476 * configuration later.
e5b64635 4477 */
e901acd6
JF		 4478 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4479 int tc;
4480 struct ixgbe_ring_feature *f =
4481 &adapter->ring_feature[RING_F_FCOE];
4482
4483 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4484 f->indices = dev->tc_to_txq[tc].count;
4485 f->mask = dev->tc_to_txq[tc].offset;
4486 }
e5b64635
JF		 4487#endif
4488
e901acd6 4489 return true;
0331a832 4490}
e5b64635 4491#endif
0331a832 4492
1cdd1ec8
GR		 4493/**
4494 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4495 * @adapter: board private structure to initialize
4496 *
4497 * IOV doesn't actually use anything, so just NAK the
4498 * request for now and let the other queue routines
4499 * figure out what to do.
4500 */
4501static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4502{
4503 return false;
4504}
4505
4df10466 4506/*
25985edc 4507 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4508 * @adapter: board private structure to initialize
4509 *
4510 * This is the top level queue allocation routine. The order here is very
4511 * important, starting with the "most" number of features turned on at once,
4512 * and ending with the smallest set of features. This way large combinations
4513 * can be allocated if they're turned on, and smaller combinations are the
4514 * fallthrough conditions.
4515 *
4516 **/
847f53ff 4517static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4518{
1cdd1ec8
GR		 4519 /* Start with base case */
4520 adapter->num_rx_queues = 1;
4521 adapter->num_tx_queues = 1;
4522 adapter->num_rx_pools = adapter->num_rx_queues;
4523 adapter->num_rx_queues_per_pool = 1;
4524
4525 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4526 goto done;
1cdd1ec8 4527
bc97114d
PWJ		 4528#ifdef CONFIG_IXGBE_DCB
4529 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4530 goto done;
bc97114d
PWJ		 4531
4532#endif
e5b64635
JF		 4533#ifdef IXGBE_FCOE
4534 if (ixgbe_set_fcoe_queues(adapter))
4535 goto done;
4536
4537#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4538 if (ixgbe_set_fdir_queues(adapter))
4539 goto done;
4540
bc97114d 4541 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4542 goto done;
4543
4544 /* fallback to base case */
4545 adapter->num_rx_queues = 1;
4546 adapter->num_tx_queues = 1;
4547
4548done:
847f53ff 4549 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4550 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4551 return netif_set_real_num_rx_queues(adapter->netdev,
4552 adapter->num_rx_queues);
b9804972
JB		 4553}
4554
021230d4 4555static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4556 int vectors)
021230d4
AV		 4557{
4558 int err, vector_threshold;
4559
4560 /* We'll want at least 3 (vector_threshold):
4561 * 1) TxQ[0] Cleanup
4562 * 2) RxQ[0] Cleanup
4563 * 3) Other (Link Status Change, etc.)
4564 * 4) TCP Timer (optional)
4565 */
4566 vector_threshold = MIN_MSIX_COUNT;
4567
4568 /* The more we get, the more we will assign to Tx/Rx Cleanup
4569 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4570 * Right now, we simply care about how many we'll get; we'll
4571 * set them up later while requesting irq's.
4572 */
4573 while (vectors >= vector_threshold) {
4574 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4575 vectors);
021230d4
AV		 4576 if (!err) /* Success in acquiring all requested vectors. */
4577 break;
4578 else if (err < 0)
4579 vectors = 0; /* Nasty failure, quit now */
4580 else /* err == number of vectors we should try again with */
4581 vectors = err;
4582 }
4583
4584 if (vectors < vector_threshold) {
4585 /* Can't allocate enough MSI-X interrupts? Oh well.
4586 * This just means we'll go with either a single MSI
4587 * vector or fall back to legacy interrupts.
4588 */
849c4542
ET		 4589 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4590 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4591 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4592 kfree(adapter->msix_entries);
4593 adapter->msix_entries = NULL;
021230d4
AV		 4594 } else {
4595 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4596 /*
4597 * Adjust for only the vectors we'll use, which is minimum
4598 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4599 * vectors we were allocated.
4600 */
4601 adapter->num_msix_vectors = min(vectors,
e8e9f696 4602 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4603 }
4604}
4605
021230d4 4606/**
bc97114d 4607 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4608 * @adapter: board private structure to initialize
4609 *
bc97114d
PWJ		 4610 * Cache the descriptor ring offsets for RSS to the assigned rings.
4611 *
021230d4 4612 **/
bc97114d 4613static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4614{
bc97114d 4615 int i;
bc97114d 4616
9d6b758f
AD		 4617 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4618 return false;
bc97114d 4619
9d6b758f
AD		 4620 for (i = 0; i < adapter->num_rx_queues; i++)
4621 adapter->rx_ring[i]->reg_idx = i;
4622 for (i = 0; i < adapter->num_tx_queues; i++)
4623 adapter->tx_ring[i]->reg_idx = i;
4624
4625 return true;
bc97114d
PWJ		 4626}
4627
4628#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4629
4630/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4631static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4632 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4633{
4634 struct net_device *dev = adapter->netdev;
4635 struct ixgbe_hw *hw = &adapter->hw;
4636 u8 num_tcs = netdev_get_num_tc(dev);
4637
4638 *tx = 0;
4639 *rx = 0;
4640
4641 switch (hw->mac.type) {
4642 case ixgbe_mac_82598EB:
aba70d5e
JF		 4643 *tx = tc << 2;
4644 *rx = tc << 3;
e5b64635
JF		 4645 break;
4646 case ixgbe_mac_82599EB:
4647 case ixgbe_mac_X540:
4648 if (num_tcs == 8) {
4649 if (tc < 3) {
4650 *tx = tc << 5;
4651 *rx = tc << 4;
4652 } else if (tc < 5) {
4653 *tx = ((tc + 2) << 4);
4654 *rx = tc << 4;
4655 } else if (tc < num_tcs) {
4656 *tx = ((tc + 8) << 3);
4657 *rx = tc << 4;
4658 }
4659 } else if (num_tcs == 4) {
4660 *rx = tc << 5;
4661 switch (tc) {
4662 case 0:
4663 *tx = 0;
4664 break;
4665 case 1:
4666 *tx = 64;
4667 break;
4668 case 2:
4669 *tx = 96;
4670 break;
4671 case 3:
4672 *tx = 112;
4673 break;
4674 default:
4675 break;
4676 }
4677 }
4678 break;
4679 default:
4680 break;
4681 }
4682}
4683
bc97114d
PWJ		 4684/**
4685 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4686 * @adapter: board private structure to initialize
4687 *
4688 * Cache the descriptor ring offsets for DCB to the assigned rings.
4689 *
4690 **/
4691static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4692{
e5b64635
JF		 4693 struct net_device *dev = adapter->netdev;
4694 int i, j, k;
4695 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4696
8b1c0b24 4697 if (!num_tcs)
bd508178 4698 return false;
f92ef202 4699
e5b64635
JF		 4700 for (i = 0, k = 0; i < num_tcs; i++) {
4701 unsigned int tx_s, rx_s;
4702 u16 count = dev->tc_to_txq[i].count;
4703
4704 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4705 for (j = 0; j < count; j++, k++) {
4706 adapter->tx_ring[k]->reg_idx = tx_s + j;
4707 adapter->rx_ring[k]->reg_idx = rx_s + j;
4708 adapter->tx_ring[k]->dcb_tc = i;
4709 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4710 }
021230d4 4711 }
e5b64635
JF		 4712
4713 return true;
bc97114d
PWJ		 4714}
4715#endif
4716
c4cf55e5
PWJ		 4717/**
4718 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4719 * @adapter: board private structure to initialize
4720 *
4721 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4722 *
4723 **/
e8e9f696 4724static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4725{
4726 int i;
4727 bool ret = false;
4728
4729 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4730 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4731 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4732 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4733 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4734 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4735 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4736 ret = true;
4737 }
4738
4739 return ret;
4740}
4741
0331a832
YZ		 4742#ifdef IXGBE_FCOE
4743/**
4744 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4745 * @adapter: board private structure to initialize
4746 *
4747 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4748 *
4749 */
4750static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4751{
0331a832 4752 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4753 int i;
4754 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4755
4756 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4757 return false;
0331a832 4758
bf29ee6c
AD		 4759 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4760 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4761 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4762 ixgbe_cache_ring_fdir(adapter);
4763 else
4764 ixgbe_cache_ring_rss(adapter);
8faa2a78 4765
bf29ee6c
AD		 4766 fcoe_rx_i = f->mask;
4767 fcoe_tx_i = f->mask;
0331a832 4768 }
bf29ee6c
AD		 4769 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4770 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4771 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4772 }
4773 return true;
0331a832
YZ		 4774}
4775
4776#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4777/**
4778 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4779 * @adapter: board private structure to initialize
4780 *
4781 * SR-IOV doesn't use any descriptor rings but changes the default if
4782 * no other mapping is used.
4783 *
4784 */
4785static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4786{
4a0b9ca0
PW		 4787 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4788 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4789 if (adapter->num_vfs)
4790 return true;
4791 else
4792 return false;
4793}
4794
bc97114d
PWJ		 4795/**
4796 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4797 * @adapter: board private structure to initialize
4798 *
4799 * Once we know the feature-set enabled for the device, we'll cache
4800 * the register offset the descriptor ring is assigned to.
4801 *
4802 * Note, the order the various feature calls is important. It must start with
4803 * the "most" features enabled at the same time, then trickle down to the
4804 * least amount of features turned on at once.
4805 **/
4806static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4807{
4808 /* start with default case */
4a0b9ca0
PW		 4809 adapter->rx_ring[0]->reg_idx = 0;
4810 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4811
1cdd1ec8
GR		 4812 if (ixgbe_cache_ring_sriov(adapter))
4813 return;
4814
e5b64635
JF		 4815#ifdef CONFIG_IXGBE_DCB
4816 if (ixgbe_cache_ring_dcb(adapter))
4817 return;
4818#endif
4819
0331a832
YZ		 4820#ifdef IXGBE_FCOE
4821 if (ixgbe_cache_ring_fcoe(adapter))
4822 return;
0331a832 4823#endif /* IXGBE_FCOE */
bc97114d 4824
c4cf55e5
PWJ		 4825 if (ixgbe_cache_ring_fdir(adapter))
4826 return;
4827
bc97114d
PWJ		 4828 if (ixgbe_cache_ring_rss(adapter))
4829 return;
021230d4
AV		 4830}
4831
9a799d71
AK		 4832/**
4833 * ixgbe_alloc_queues - Allocate memory for all rings
4834 * @adapter: board private structure to initialize
4835 *
4836 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4837 * number of queues at compile-time. The polling_netdev array is
4838 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4839 **/
2f90b865 4840static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4841{
e2ddeba9 4842 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4843
e2ddeba9
ED		 4844 if (nid < 0 || !node_online(nid))
4845 nid = first_online_node;
4846
4847 for (; tx < adapter->num_tx_queues; tx++) {
4848 struct ixgbe_ring *ring;
4849
4850 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4851 if (!ring)
e2ddeba9 4852 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4853 if (!ring)
e2ddeba9 4854 goto err_allocation;
4a0b9ca0 4855 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4856 ring->queue_index = tx;
4857 ring->numa_node = nid;
b6ec895e 4858 ring->dev = &adapter->pdev->dev;
fc77dc3c 4859 ring->netdev = adapter->netdev;
4a0b9ca0 4860
e2ddeba9 4861 adapter->tx_ring[tx] = ring;
021230d4 4862 }
b9804972 4863
e2ddeba9
ED		 4864 for (; rx < adapter->num_rx_queues; rx++) {
4865 struct ixgbe_ring *ring;
4a0b9ca0 4866
e2ddeba9 4867 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4868 if (!ring)
e2ddeba9 4869 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4870 if (!ring)
e2ddeba9
ED		 4871 goto err_allocation;
4872 ring->count = adapter->rx_ring_count;
4873 ring->queue_index = rx;
4874 ring->numa_node = nid;
b6ec895e 4875 ring->dev = &adapter->pdev->dev;
fc77dc3c 4876 ring->netdev = adapter->netdev;
4a0b9ca0 4877
e2ddeba9 4878 adapter->rx_ring[rx] = ring;
021230d4
AV		 4879 }
4880
4881 ixgbe_cache_ring_register(adapter);
4882
4883 return 0;
4884
e2ddeba9
ED		 4885err_allocation:
4886 while (tx)
4887 kfree(adapter->tx_ring[--tx]);
4888
4889 while (rx)
4890 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4891 return -ENOMEM;
4892}
4893
4894/**
4895 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4896 * @adapter: board private structure to initialize
4897 *
4898 * Attempt to configure the interrupts using the best available
4899 * capabilities of the hardware and the kernel.
4900 **/
feea6a57 4901static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4902{
8be0e467 4903 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4904 int err = 0;
4905 int vector, v_budget;
4906
4907 /*
4908 * It's easy to be greedy for MSI-X vectors, but it really
4909 * doesn't do us much good if we have a lot more vectors
4910 * than CPU's. So let's be conservative and only ask for
342bde1b 4911 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4912 */
4913 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4914 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4915
4916 /*
4917 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4918 * hw.mac->max_msix_vectors vectors. With features
4919 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4920 * descriptor queues supported by our device. Thus, we cap it off in
4921 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4922 */
8be0e467 4923 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4924
4925 /* A failure in MSI-X entry allocation isn't fatal, but it does
4926 * mean we disable MSI-X capabilities of the adapter. */
4927 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4928 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4929 if (adapter->msix_entries) {
4930 for (vector = 0; vector < v_budget; vector++)
4931 adapter->msix_entries[vector].entry = vector;
021230d4 4932
7a921c93 4933 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4934
7a921c93
AD		 4935 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4936 goto out;
4937 }
26d27844 4938
7a921c93
AD		 4939 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4940 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
45b9f509
AD		 4941 if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4942 IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4943 e_err(probe,
4944 "Flow Director is not supported while multiple "
4945 "queues are disabled. Disabling Flow Director\n");
4946 }
c4cf55e5
PWJ		 4947 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4948 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4949 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4950 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4951 ixgbe_disable_sriov(adapter);
4952
847f53ff
BH		 4953 err = ixgbe_set_num_queues(adapter);
4954 if (err)
4955 return err;
021230d4 4956
021230d4
AV		 4957 err = pci_enable_msi(adapter->pdev);
4958 if (!err) {
4959 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4960 } else {
849c4542
ET		 4961 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4962 "Unable to allocate MSI interrupt, "
4963 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4964 /* reset err */
4965 err = 0;
4966 }
4967
4968out:
021230d4
AV		 4969 return err;
4970}
4971
7a921c93
AD		 4972/**
4973 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4974 * @adapter: board private structure to initialize
4975 *
4976 * We allocate one q_vector per queue interrupt. If allocation fails we
4977 * return -ENOMEM.
4978 **/
4979static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4980{
4981 int q_idx, num_q_vectors;
4982 struct ixgbe_q_vector *q_vector;
7a921c93
AD		 4983 int (*poll)(struct napi_struct *, int);
4984
4985 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4986 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4987 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4988 } else {
4989 num_q_vectors = 1;
7a921c93
AD		 4990 poll = &ixgbe_poll;
4991 }
4992
4993 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4994 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4995 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4996 if (!q_vector)
4997 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4998 GFP_KERNEL);
7a921c93
AD		 4999 if (!q_vector)
5000 goto err_out;
5001 q_vector->adapter = adapter;
f7554a2b
NS		 5002 if (q_vector->txr_count && !q_vector->rxr_count)
5003 q_vector->eitr = adapter->tx_eitr_param;
5004 else
5005 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 5006 q_vector->v_idx = q_idx;
91281fd3 5007 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 5008 adapter->q_vector[q_idx] = q_vector;
5009 }
5010
5011 return 0;
5012
5013err_out:
5014 while (q_idx) {
5015 q_idx--;
5016 q_vector = adapter->q_vector[q_idx];
5017 netif_napi_del(&q_vector->napi);
5018 kfree(q_vector);
5019 adapter->q_vector[q_idx] = NULL;
5020 }
5021 return -ENOMEM;
5022}
5023
5024/**
5025 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5026 * @adapter: board private structure to initialize
5027 *
5028 * This function frees the memory allocated to the q_vectors. In addition if
5029 * NAPI is enabled it will delete any references to the NAPI struct prior
5030 * to freeing the q_vector.
5031 **/
5032static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5033{
5034 int q_idx, num_q_vectors;
7a921c93 5035
91281fd3 5036 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 5037 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 5038 else
7a921c93 5039 num_q_vectors = 1;
7a921c93
AD		 5040
5041 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5042 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 5043 adapter->q_vector[q_idx] = NULL;
91281fd3 5044 netif_napi_del(&q_vector->napi);
7a921c93
AD		 5045 kfree(q_vector);
5046 }
5047}
5048
7b25cdba 5049static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 5050{
5051 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5052 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5053 pci_disable_msix(adapter->pdev);
5054 kfree(adapter->msix_entries);
5055 adapter->msix_entries = NULL;
5056 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5057 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5058 pci_disable_msi(adapter->pdev);
5059 }
021230d4
AV		 5060}
5061
5062/**
5063 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5064 * @adapter: board private structure to initialize
5065 *
5066 * We determine which interrupt scheme to use based on...
5067 * - Kernel support (MSI, MSI-X)
5068 * - which can be user-defined (via MODULE_PARAM)
5069 * - Hardware queue count (num_*_queues)
5070 * - defined by miscellaneous hardware support/features (RSS, etc.)
5071 **/
2f90b865 5072int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 5073{
5074 int err;
5075
5076 /* Number of supported queues */
847f53ff
BH		 5077 err = ixgbe_set_num_queues(adapter);
5078 if (err)
5079 return err;
021230d4 5080
021230d4
AV		 5081 err = ixgbe_set_interrupt_capability(adapter);
5082 if (err) {
849c4542 5083 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 5084 goto err_set_interrupt;
9a799d71
AK		 5085 }
5086
7a921c93
AD		 5087 err = ixgbe_alloc_q_vectors(adapter);
5088 if (err) {
849c4542 5089 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 5090 goto err_alloc_q_vectors;
5091 }
5092
5093 err = ixgbe_alloc_queues(adapter);
5094 if (err) {
849c4542 5095 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 5096 goto err_alloc_queues;
5097 }
5098
849c4542 5099 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 5100 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5101 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 5102
5103 set_bit(__IXGBE_DOWN, &adapter->state);
5104
9a799d71 5105 return 0;
021230d4 5106
7a921c93
AD		 5107err_alloc_queues:
5108 ixgbe_free_q_vectors(adapter);
5109err_alloc_q_vectors:
5110 ixgbe_reset_interrupt_capability(adapter);
021230d4 5111err_set_interrupt:
7a921c93
AD		 5112 return err;
5113}
5114
5115/**
5116 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5117 * @adapter: board private structure to clear interrupt scheme on
5118 *
5119 * We go through and clear interrupt specific resources and reset the structure
5120 * to pre-load conditions
5121 **/
5122void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5123{
4a0b9ca0
PW		 5124 int i;
5125
5126 for (i = 0; i < adapter->num_tx_queues; i++) {
5127 kfree(adapter->tx_ring[i]);
5128 adapter->tx_ring[i] = NULL;
5129 }
5130 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 5131 struct ixgbe_ring *ring = adapter->rx_ring[i];
5132
5133 /* ixgbe_get_stats64() might access this ring, we must wait
5134 * a grace period before freeing it.
5135 */
bcec8b65 5136 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 5137 adapter->rx_ring[i] = NULL;
5138 }
7a921c93 5139
b8eb3a10
DS		 5140 adapter->num_tx_queues = 0;
5141 adapter->num_rx_queues = 0;
5142
7a921c93
AD		 5143 ixgbe_free_q_vectors(adapter);
5144 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5145}
5146
5147/**
5148 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5149 * @adapter: board private structure to initialize
5150 *
5151 * ixgbe_sw_init initializes the Adapter private data structure.
5152 * Fields are initialized based on PCI device information and
5153 * OS network device settings (MTU size).
5154 **/
5155static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5156{
5157 struct ixgbe_hw *hw = &adapter->hw;
5158 struct pci_dev *pdev = adapter->pdev;
9a713e7c 5159 struct net_device *dev = adapter->netdev;
021230d4 5160 unsigned int rss;
7a6b6f51 5161#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5162 int j;
5163 struct tc_configuration *tc;
5164#endif
16b61beb 5165 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 5166
c44ade9e
JB		 5167 /* PCI config space info */
5168
5169 hw->vendor_id = pdev->vendor;
5170 hw->device_id = pdev->device;
5171 hw->revision_id = pdev->revision;
5172 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5173 hw->subsystem_device_id = pdev->subsystem_device;
5174
021230d4
AV		 5175 /* Set capability flags */
5176 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5177 adapter->ring_feature[RING_F_RSS].indices = rss;
5178 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 5179 switch (hw->mac.type) {
5180 case ixgbe_mac_82598EB:
bf069c97
DS		 5181 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5182 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5183 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178
AD		 5184 break;
5185 case ixgbe_mac_82599EB:
b93a2226 5186 case ixgbe_mac_X540:
e8e26350 5187 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5188 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5189 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5190 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5191 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5192 /* n-tuple support exists, always init our spinlock */
5193 spin_lock_init(&adapter->fdir_perfect_lock);
5194 /* Flow Director hash filters enabled */
5195 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5196 adapter->atr_sample_rate = 20;
c4cf55e5 5197 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5198 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 5199 adapter->fdir_pballoc = 0;
eacd73f7 5200#ifdef IXGBE_FCOE
0d551589
YZ		 5201 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5202 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5203 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5204#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 5205 /* Default traffic class to use for FCoE */
5206 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 5207 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5208#endif
eacd73f7 5209#endif /* IXGBE_FCOE */
bd508178
AD		 5210 break;
5211 default:
5212 break;
f8212f97 5213 }
2f90b865 5214
7a6b6f51 5215#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5216 /* Configure DCB traffic classes */
5217 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5218 tc = &adapter->dcb_cfg.tc_config[j];
5219 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5220 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5221 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5222 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5223 tc->dcb_pfc = pfc_disabled;
5224 }
5225 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5226 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5227 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5228 adapter->dcb_set_bitmap = 0x00;
3032309b 5229 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5230 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5231 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5232
5233#endif
9a799d71
AK		 5234
5235 /* default flow control settings */
cd7664f6 5236 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5237 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5238#ifdef CONFIG_DCB
5239 adapter->last_lfc_mode = hw->fc.current_mode;
5240#endif
16b61beb
JF		 5241 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5242 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 5243 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5244 hw->fc.send_xon = true;
71fd570b 5245 hw->fc.disable_fc_autoneg = false;
9a799d71 5246
30efa5a3 5247 /* enable itr by default in dynamic mode */
f7554a2b
NS		 5248 adapter->rx_itr_setting = 1;
5249 adapter->rx_eitr_param = 20000;
5250 adapter->tx_itr_setting = 1;
5251 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 5252
5253 /* set defaults for eitr in MegaBytes */
5254 adapter->eitr_low = 10;
5255 adapter->eitr_high = 20;
5256
5257 /* set default ring sizes */
5258 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5259 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5260
9a799d71 5261 /* initialize eeprom parameters */
c44ade9e 5262 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5263 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5264 return -EIO;
5265 }
5266
021230d4 5267 /* enable rx csum by default */
9a799d71
AK		 5268 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5269
1a6c14a2
JB		 5270 /* get assigned NUMA node */
5271 adapter->node = dev_to_node(&pdev->dev);
5272
9a799d71
AK		 5273 set_bit(__IXGBE_DOWN, &adapter->state);
5274
5275 return 0;
5276}
5277
5278/**
5279 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5280 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5281 *
5282 * Return 0 on success, negative on failure
5283 **/
b6ec895e 5284int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5285{
b6ec895e 5286 struct device *dev = tx_ring->dev;
9a799d71
AK		 5287 int size;
5288
3a581073 5289 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5290 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5291 if (!tx_ring->tx_buffer_info)
89bf67f1 5292 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5293 if (!tx_ring->tx_buffer_info)
5294 goto err;
9a799d71
AK		 5295
5296 /* round up to nearest 4K */
12207e49 5297 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5298 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5299
b6ec895e 5300 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5301 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5302 if (!tx_ring->desc)
5303 goto err;
9a799d71 5304
3a581073
JB		 5305 tx_ring->next_to_use = 0;
5306 tx_ring->next_to_clean = 0;
5307 tx_ring->work_limit = tx_ring->count;
9a799d71 5308 return 0;
e01c31a5
JB		 5309
5310err:
5311 vfree(tx_ring->tx_buffer_info);
5312 tx_ring->tx_buffer_info = NULL;
b6ec895e 5313 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5314 return -ENOMEM;
9a799d71
AK		 5315}
5316
69888674
AD		 5317/**
5318 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5319 * @adapter: board private structure
5320 *
5321 * If this function returns with an error, then it's possible one or
5322 * more of the rings is populated (while the rest are not). It is the
5323 * callers duty to clean those orphaned rings.
5324 *
5325 * Return 0 on success, negative on failure
5326 **/
5327static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5328{
5329 int i, err = 0;
5330
5331 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5332 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5333 if (!err)
5334 continue;
396e799c 5335 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5336 break;
5337 }
5338
5339 return err;
5340}
5341
9a799d71
AK		 5342/**
5343 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5344 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5345 *
5346 * Returns 0 on success, negative on failure
5347 **/
b6ec895e 5348int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5349{
b6ec895e 5350 struct device *dev = rx_ring->dev;
021230d4 5351 int size;
9a799d71 5352
3a581073 5353 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5354 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5355 if (!rx_ring->rx_buffer_info)
89bf67f1 5356 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5357 if (!rx_ring->rx_buffer_info)
5358 goto err;
9a799d71 5359
9a799d71 5360 /* Round up to nearest 4K */
3a581073
JB		 5361 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5362 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5363
b6ec895e 5364 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5365 &rx_ring->dma, GFP_KERNEL);
9a799d71 5366
b6ec895e
AD		 5367 if (!rx_ring->desc)
5368 goto err;
9a799d71 5369
3a581073
JB		 5370 rx_ring->next_to_clean = 0;
5371 rx_ring->next_to_use = 0;
9a799d71
AK		 5372
5373 return 0;
b6ec895e
AD		 5374err:
5375 vfree(rx_ring->rx_buffer_info);
5376 rx_ring->rx_buffer_info = NULL;
5377 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5378 return -ENOMEM;
9a799d71
AK		 5379}
5380
69888674
AD		 5381/**
5382 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5383 * @adapter: board private structure
5384 *
5385 * If this function returns with an error, then it's possible one or
5386 * more of the rings is populated (while the rest are not). It is the
5387 * callers duty to clean those orphaned rings.
5388 *
5389 * Return 0 on success, negative on failure
5390 **/
69888674
AD		 5391static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5392{
5393 int i, err = 0;
5394
5395 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5396 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5397 if (!err)
5398 continue;
396e799c 5399 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5400 break;
5401 }
5402
5403 return err;
5404}
5405
9a799d71
AK		 5406/**
5407 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5408 * @tx_ring: Tx descriptor ring for a specific queue
5409 *
5410 * Free all transmit software resources
5411 **/
b6ec895e 5412void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5413{
b6ec895e 5414 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5415
5416 vfree(tx_ring->tx_buffer_info);
5417 tx_ring->tx_buffer_info = NULL;
5418
b6ec895e
AD		 5419 /* if not set, then don't free */
5420 if (!tx_ring->desc)
5421 return;
5422
5423 dma_free_coherent(tx_ring->dev, tx_ring->size,
5424 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5425
5426 tx_ring->desc = NULL;
5427}
5428
5429/**
5430 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5431 * @adapter: board private structure
5432 *
5433 * Free all transmit software resources
5434 **/
5435static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5436{
5437 int i;
5438
5439 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5440 if (adapter->tx_ring[i]->desc)
b6ec895e 5441 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5442}
5443
5444/**
b4617240 5445 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5446 * @rx_ring: ring to clean the resources from
5447 *
5448 * Free all receive software resources
5449 **/
b6ec895e 5450void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5451{
b6ec895e 5452 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5453
5454 vfree(rx_ring->rx_buffer_info);
5455 rx_ring->rx_buffer_info = NULL;
5456
b6ec895e
AD		 5457 /* if not set, then don't free */
5458 if (!rx_ring->desc)
5459 return;
5460
5461 dma_free_coherent(rx_ring->dev, rx_ring->size,
5462 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5463
5464 rx_ring->desc = NULL;
5465}
5466
5467/**
5468 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5469 * @adapter: board private structure
5470 *
5471 * Free all receive software resources
5472 **/
5473static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5474{
5475 int i;
5476
5477 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5478 if (adapter->rx_ring[i]->desc)
b6ec895e 5479 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5480}
5481
9a799d71
AK		 5482/**
5483 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5484 * @netdev: network interface device structure
5485 * @new_mtu: new value for maximum frame size
5486 *
5487 * Returns 0 on success, negative on failure
5488 **/
5489static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5490{
5491 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5492 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5493 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5494
42c783c5 5495 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5496 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5497 hw->mac.type != ixgbe_mac_X540) {
5498 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5499 return -EINVAL;
5500 } else {
5501 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5502 return -EINVAL;
5503 }
9a799d71 5504
396e799c 5505 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5506 /* must set new MTU before calling down or up */
9a799d71
AK		 5507 netdev->mtu = new_mtu;
5508
16b61beb
JF		 5509 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5510 hw->fc.low_water = FC_LOW_WATER(max_frame);
5511
d4f80882
AV		 5512 if (netif_running(netdev))
5513 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5514
5515 return 0;
5516}
5517
5518/**
5519 * ixgbe_open - Called when a network interface is made active
5520 * @netdev: network interface device structure
5521 *
5522 * Returns 0 on success, negative value on failure
5523 *
5524 * The open entry point is called when a network interface is made
5525 * active by the system (IFF_UP). At this point all resources needed
5526 * for transmit and receive operations are allocated, the interrupt
5527 * handler is registered with the OS, the watchdog timer is started,
5528 * and the stack is notified that the interface is ready.
5529 **/
5530static int ixgbe_open(struct net_device *netdev)
5531{
5532 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5533 int err;
4bebfaa5
AK		 5534
5535 /* disallow open during test */
5536 if (test_bit(__IXGBE_TESTING, &adapter->state))
5537 return -EBUSY;
9a799d71 5538
54386467
JB		 5539 netif_carrier_off(netdev);
5540
9a799d71
AK		 5541 /* allocate transmit descriptors */
5542 err = ixgbe_setup_all_tx_resources(adapter);
5543 if (err)
5544 goto err_setup_tx;
5545
9a799d71
AK		 5546 /* allocate receive descriptors */
5547 err = ixgbe_setup_all_rx_resources(adapter);
5548 if (err)
5549 goto err_setup_rx;
5550
5551 ixgbe_configure(adapter);
5552
021230d4 5553 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5554 if (err)
5555 goto err_req_irq;
5556
9a799d71
AK		 5557 err = ixgbe_up_complete(adapter);
5558 if (err)
5559 goto err_up;
5560
d55b53ff
JK		 5561 netif_tx_start_all_queues(netdev);
5562
9a799d71
AK		 5563 return 0;
5564
5565err_up:
5eba3699 5566 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5567 ixgbe_free_irq(adapter);
5568err_req_irq:
9a799d71 5569err_setup_rx:
a20a1199 5570 ixgbe_free_all_rx_resources(adapter);
9a799d71 5571err_setup_tx:
a20a1199 5572 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5573 ixgbe_reset(adapter);
5574
5575 return err;
5576}
5577
5578/**
5579 * ixgbe_close - Disables a network interface
5580 * @netdev: network interface device structure
5581 *
5582 * Returns 0, this is not allowed to fail
5583 *
5584 * The close entry point is called when an interface is de-activated
5585 * by the OS. The hardware is still under the drivers control, but
5586 * needs to be disabled. A global MAC reset is issued to stop the
5587 * hardware, and all transmit and receive resources are freed.
5588 **/
5589static int ixgbe_close(struct net_device *netdev)
5590{
5591 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5592
5593 ixgbe_down(adapter);
5594 ixgbe_free_irq(adapter);
5595
5596 ixgbe_free_all_tx_resources(adapter);
5597 ixgbe_free_all_rx_resources(adapter);
5598
5eba3699 5599 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5600
5601 return 0;
5602}
5603
b3c8b4ba
AD		 5604#ifdef CONFIG_PM
5605static int ixgbe_resume(struct pci_dev *pdev)
5606{
c60fbb00
AD		 5607 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5608 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5609 u32 err;
5610
5611 pci_set_power_state(pdev, PCI_D0);
5612 pci_restore_state(pdev);
656ab817
DS		 5613 /*
5614 * pci_restore_state clears dev->state_saved so call
5615 * pci_save_state to restore it.
5616 */
5617 pci_save_state(pdev);
9ce77666 5618
5619 err = pci_enable_device_mem(pdev);
b3c8b4ba 5620 if (err) {
849c4542 5621 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5622 return err;
5623 }
5624 pci_set_master(pdev);
5625
dd4d8ca6 5626 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5627
5628 err = ixgbe_init_interrupt_scheme(adapter);
5629 if (err) {
849c4542 5630 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5631 return err;
5632 }
5633
b3c8b4ba
AD		 5634 ixgbe_reset(adapter);
5635
495dce12
WJP		 5636 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5637
b3c8b4ba 5638 if (netif_running(netdev)) {
c60fbb00 5639 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5640 if (err)
5641 return err;
5642 }
5643
5644 netif_device_attach(netdev);
5645
5646 return 0;
5647}
b3c8b4ba 5648#endif /* CONFIG_PM */
9d8d05ae
RW		 5649
5650static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5651{
c60fbb00
AD		 5652 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5653 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5654 struct ixgbe_hw *hw = &adapter->hw;
5655 u32 ctrl, fctrl;
5656 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5657#ifdef CONFIG_PM
5658 int retval = 0;
5659#endif
5660
5661 netif_device_detach(netdev);
5662
5663 if (netif_running(netdev)) {
5664 ixgbe_down(adapter);
5665 ixgbe_free_irq(adapter);
5666 ixgbe_free_all_tx_resources(adapter);
5667 ixgbe_free_all_rx_resources(adapter);
5668 }
b3c8b4ba 5669
5f5ae6fc 5670 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5671#ifdef CONFIG_DCB
5672 kfree(adapter->ixgbe_ieee_pfc);
5673 kfree(adapter->ixgbe_ieee_ets);
5674#endif
5f5ae6fc 5675
b3c8b4ba
AD		 5676#ifdef CONFIG_PM
5677 retval = pci_save_state(pdev);
5678 if (retval)
5679 return retval;
4df10466 5680
b3c8b4ba 5681#endif
e8e26350
PW		 5682 if (wufc) {
5683 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5684
e8e26350
PW		 5685 /* turn on all-multi mode if wake on multicast is enabled */
5686 if (wufc & IXGBE_WUFC_MC) {
5687 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5688 fctrl |= IXGBE_FCTRL_MPE;
5689 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5690 }
5691
5692 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5693 ctrl |= IXGBE_CTRL_GIO_DIS;
5694 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5695
5696 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5697 } else {
5698 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5699 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5700 }
5701
bd508178
AD		 5702 switch (hw->mac.type) {
5703 case ixgbe_mac_82598EB:
dd4d8ca6 5704 pci_wake_from_d3(pdev, false);
bd508178
AD		 5705 break;
5706 case ixgbe_mac_82599EB:
b93a2226 5707 case ixgbe_mac_X540:
bd508178
AD		 5708 pci_wake_from_d3(pdev, !!wufc);
5709 break;
5710 default:
5711 break;
5712 }
b3c8b4ba 5713
9d8d05ae
RW		 5714 *enable_wake = !!wufc;
5715
b3c8b4ba
AD		 5716 ixgbe_release_hw_control(adapter);
5717
5718 pci_disable_device(pdev);
5719
9d8d05ae
RW		 5720 return 0;
5721}
5722
5723#ifdef CONFIG_PM
5724static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5725{
5726 int retval;
5727 bool wake;
5728
5729 retval = __ixgbe_shutdown(pdev, &wake);
5730 if (retval)
5731 return retval;
5732
5733 if (wake) {
5734 pci_prepare_to_sleep(pdev);
5735 } else {
5736 pci_wake_from_d3(pdev, false);
5737 pci_set_power_state(pdev, PCI_D3hot);
5738 }
b3c8b4ba
AD		 5739
5740 return 0;
5741}
9d8d05ae 5742#endif /* CONFIG_PM */
b3c8b4ba
AD		 5743
5744static void ixgbe_shutdown(struct pci_dev *pdev)
5745{
9d8d05ae
RW		 5746 bool wake;
5747
5748 __ixgbe_shutdown(pdev, &wake);
5749
5750 if (system_state == SYSTEM_POWER_OFF) {
5751 pci_wake_from_d3(pdev, wake);
5752 pci_set_power_state(pdev, PCI_D3hot);
5753 }
b3c8b4ba
AD		 5754}
5755
9a799d71
AK		 5756/**
5757 * ixgbe_update_stats - Update the board statistics counters.
5758 * @adapter: board private structure
5759 **/
5760void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5761{
2d86f139 5762 struct net_device *netdev = adapter->netdev;
9a799d71 5763 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5764 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5765 u64 total_mpc = 0;
5766 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5767 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5768 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5769 u64 bytes = 0, packets = 0;
9a799d71 5770
d08935c2
DS		 5771 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5772 test_bit(__IXGBE_RESETTING, &adapter->state))
5773 return;
5774
94b982b2 5775 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5776 u64 rsc_count = 0;
94b982b2 5777 u64 rsc_flush = 0;
d51019a4
PW		 5778 for (i = 0; i < 16; i++)
5779 adapter->hw_rx_no_dma_resources +=
7ca647bd 5780 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5781 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5782 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5783 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5784 }
5785 adapter->rsc_total_count = rsc_count;
5786 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5787 }
5788
5b7da515
AD		 5789 for (i = 0; i < adapter->num_rx_queues; i++) {
5790 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5791 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5792 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5793 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5794 bytes += rx_ring->stats.bytes;
5795 packets += rx_ring->stats.packets;
5796 }
5797 adapter->non_eop_descs = non_eop_descs;
5798 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5799 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5800 netdev->stats.rx_bytes = bytes;
5801 netdev->stats.rx_packets = packets;
5802
5803 bytes = 0;
5804 packets = 0;
7ca3bc58 5805 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5806 for (i = 0; i < adapter->num_tx_queues; i++) {
5807 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5808 restart_queue += tx_ring->tx_stats.restart_queue;
5809 tx_busy += tx_ring->tx_stats.tx_busy;
5810 bytes += tx_ring->stats.bytes;
5811 packets += tx_ring->stats.packets;
5812 }
eb985f09 5813 adapter->restart_queue = restart_queue;
5b7da515
AD		 5814 adapter->tx_busy = tx_busy;
5815 netdev->stats.tx_bytes = bytes;
5816 netdev->stats.tx_packets = packets;
7ca3bc58 5817
7ca647bd 5818 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5819 for (i = 0; i < 8; i++) {
5820 /* for packet buffers not used, the register should read 0 */
5821 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5822 missed_rx += mpc;
7ca647bd
JP		 5823 hwstats->mpc[i] += mpc;
5824 total_mpc += hwstats->mpc[i];
e8e26350 5825 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5826 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5827 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5828 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5829 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5830 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
bd508178
AD		 5831 switch (hw->mac.type) {
5832 case ixgbe_mac_82598EB:
7ca647bd
JP		 5833 hwstats->pxonrxc[i] +=
5834 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5835 break;
5836 case ixgbe_mac_82599EB:
b93a2226 5837 case ixgbe_mac_X540:
bd508178
AD		 5838 hwstats->pxonrxc[i] +=
5839 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5840 break;
5841 default:
5842 break;
e8e26350 5843 }
7ca647bd
JP		 5844 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5845 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5846 }
7ca647bd 5847 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5848 /* work around hardware counting issue */
7ca647bd 5849 hwstats->gprc -= missed_rx;
6f11eef7 5850
c84d324c
JF		 5851 ixgbe_update_xoff_received(adapter);
5852
6f11eef7 5853 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5854 switch (hw->mac.type) {
5855 case ixgbe_mac_82598EB:
5856 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5857 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5858 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5859 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5860 break;
b93a2226 5861 case ixgbe_mac_X540:
58f6bcf9
ET		 5862 /* OS2BMC stats are X540 only*/
5863 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5864 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5865 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5866 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5867 case ixgbe_mac_82599EB:
7ca647bd 5868 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5869 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5870 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5871 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5872 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5873 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5874 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5875 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5876 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5877#ifdef IXGBE_FCOE
7ca647bd
JP		 5878 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5879 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5880 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5881 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5882 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5883 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5884#endif /* IXGBE_FCOE */
bd508178
AD		 5885 break;
5886 default:
5887 break;
e8e26350 5888 }
9a799d71 5889 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5890 hwstats->bprc += bprc;
5891 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5892 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5893 hwstats->mprc -= bprc;
5894 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5895 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5896 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5897 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5898 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5899 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5900 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5901 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5902 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5903 hwstats->lxontxc += lxon;
6f11eef7 5904 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5905 hwstats->lxofftxc += lxoff;
5906 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5907 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5908 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5909 /*
5910 * 82598 errata - tx of flow control packets is included in tx counters
5911 */
5912 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5913 hwstats->gptc -= xon_off_tot;
5914 hwstats->mptc -= xon_off_tot;
5915 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5916 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5917 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5918 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5919 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5920 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5921 hwstats->ptc64 -= xon_off_tot;
5922 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5923 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5924 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5925 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5926 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5927 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5928
5929 /* Fill out the OS statistics structure */
7ca647bd 5930 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5931
5932 /* Rx Errors */
7ca647bd 5933 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5934 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5935 netdev->stats.rx_length_errors = hwstats->rlec;
5936 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5937 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5938}
5939
5940/**
d034acf1
AD		 5941 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5942 * @adapter - pointer to the device adapter structure
9a799d71 5943 **/
d034acf1 5944static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5945{
cf8280ee 5946 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5947 int i;
cf8280ee 5948
d034acf1
AD		 5949 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5950 return;
5951
5952 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5953
d034acf1 5954 /* if interface is down do nothing */
fe49f04a 5955 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5956 return;
5957
5958 /* do nothing if we are not using signature filters */
5959 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5960 return;
5961
5962 adapter->fdir_overflow++;
5963
93c52dd0
AD		 5964 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5965 for (i = 0; i < adapter->num_tx_queues; i++)
5966 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5967 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5968 /* re-enable flow director interrupts */
5969 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5970 } else {
5971 e_err(probe, "failed to finish FDIR re-initialization, "
5972 "ignored adding FDIR ATR filters\n");
5973 }
93c52dd0
AD		 5974}
5975
5976/**
5977 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5978 * @adapter - pointer to the device adapter structure
5979 *
5980 * This function serves two purposes. First it strobes the interrupt lines
5981 * in order to make certain interrupts are occuring. Secondly it sets the
5982 * bits needed to check for TX hangs. As a result we should immediately
5983 * determine if a hang has occured.
5984 */
5985static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5986{
cf8280ee 5987 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5988 u64 eics = 0;
5989 int i;
cf8280ee 5990
93c52dd0
AD		 5991 /* If we're down or resetting, just bail */
5992 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5993 test_bit(__IXGBE_RESETTING, &adapter->state))
5994 return;
22d5a71b 5995
93c52dd0
AD		 5996 /* Force detection of hung controller */
5997 if (netif_carrier_ok(adapter->netdev)) {
5998 for (i = 0; i < adapter->num_tx_queues; i++)
5999 set_check_for_tx_hang(adapter->tx_ring[i]);
6000 }
22d5a71b 6001
fe49f04a
AD		 6002 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6003 /*
6004 * for legacy and MSI interrupts don't set any bits
6005 * that are enabled for EIAM, because this operation
6006 * would set *both* EIMS and EICS for any bit in EIAM
6007 */
6008 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6009 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6010 } else {
6011 /* get one bit for every active tx/rx interrupt vector */
6012 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6013 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6014 if (qv->rxr_count || qv->txr_count)
6015 eics |= ((u64)1 << i);
6016 }
cf8280ee 6017 }
9a799d71 6018
93c52dd0 6019 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6020 ixgbe_irq_rearm_queues(adapter, eics);
6021
cf8280ee
JB		 6022}
6023
e8e26350 6024/**
93c52dd0
AD		 6025 * ixgbe_watchdog_update_link - update the link status
6026 * @adapter - pointer to the device adapter structure
6027 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 6028 **/
93c52dd0 6029static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6030{
e8e26350 6031 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6032 u32 link_speed = adapter->link_speed;
6033 bool link_up = adapter->link_up;
c4cf55e5 6034 int i;
e8e26350 6035
93c52dd0
AD		 6036 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6037 return;
6038
6039 if (hw->mac.ops.check_link) {
6040 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6041 } else {
93c52dd0
AD		 6042 /* always assume link is up, if no check link function */
6043 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6044 link_up = true;
c4cf55e5 6045 }
93c52dd0
AD		 6046 if (link_up) {
6047 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6048 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6049 hw->mac.ops.fc_enable(hw, i);
6050 } else {
6051 hw->mac.ops.fc_enable(hw, 0);
6052 }
6053 }
6054
6055 if (link_up ||
6056 time_after(jiffies, (adapter->link_check_timeout +
6057 IXGBE_TRY_LINK_TIMEOUT))) {
6058 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6059 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6060 IXGBE_WRITE_FLUSH(hw);
6061 }
6062
6063 adapter->link_up = link_up;
6064 adapter->link_speed = link_speed;
e8e26350
PW		 6065}
6066
6067/**
93c52dd0
AD		 6068 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6069 * print link up message
6070 * @adapter - pointer to the device adapter structure
e8e26350 6071 **/
93c52dd0 6072static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6073{
93c52dd0 6074 struct net_device *netdev = adapter->netdev;
e8e26350 6075 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6076 u32 link_speed = adapter->link_speed;
6077 bool flow_rx, flow_tx;
e8e26350 6078
93c52dd0
AD		 6079 /* only continue if link was previously down */
6080 if (netif_carrier_ok(netdev))
a985b6c3 6081 return;
63d6e1d8 6082
93c52dd0 6083 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6084
93c52dd0
AD		 6085 switch (hw->mac.type) {
6086 case ixgbe_mac_82598EB: {
6087 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6088 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6089 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6090 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6091 }
6092 break;
6093 case ixgbe_mac_X540:
6094 case ixgbe_mac_82599EB: {
6095 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6096 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6097 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6098 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6099 }
6100 break;
6101 default:
6102 flow_tx = false;
6103 flow_rx = false;
6104 break;
e8e26350 6105 }
93c52dd0
AD		 6106 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6107 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6108 "10 Gbps" :
6109 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6110 "1 Gbps" :
6111 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6112 "100 Mbps" :
6113 "unknown speed"))),
6114 ((flow_rx && flow_tx) ? "RX/TX" :
6115 (flow_rx ? "RX" :
6116 (flow_tx ? "TX" : "None"))));
e8e26350 6117
93c52dd0
AD		 6118 netif_carrier_on(netdev);
6119#ifdef HAVE_IPLINK_VF_CONFIG
6120 ixgbe_check_vf_rate_limit(adapter);
6121#endif /* HAVE_IPLINK_VF_CONFIG */
e8e26350
PW		 6122}
6123
c4cf55e5 6124/**
93c52dd0
AD		 6125 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6126 * print link down message
6127 * @adapter - pointer to the adapter structure
c4cf55e5 6128 **/
93c52dd0 6129static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 6130{
cf8280ee 6131 struct net_device *netdev = adapter->netdev;
c4cf55e5 6132 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6133
93c52dd0
AD		 6134 adapter->link_up = false;
6135 adapter->link_speed = 0;
cf8280ee 6136
93c52dd0
AD		 6137 /* only continue if link was up previously */
6138 if (!netif_carrier_ok(netdev))
6139 return;
264857b8 6140
93c52dd0
AD		 6141 /* poll for SFP+ cable when link is down */
6142 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6143 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6144
93c52dd0
AD		 6145 e_info(drv, "NIC Link is Down\n");
6146 netif_carrier_off(netdev);
6147}
e8e26350 6148
93c52dd0
AD		 6149/**
6150 * ixgbe_watchdog_flush_tx - flush queues on link down
6151 * @adapter - pointer to the device adapter structure
6152 **/
6153static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6154{
c4cf55e5 6155 int i;
93c52dd0 6156 int some_tx_pending = 0;
c4cf55e5 6157
93c52dd0 6158 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6159 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6160 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6161 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6162 some_tx_pending = 1;
6163 break;
6164 }
6165 }
6166
6167 if (some_tx_pending) {
6168 /* We've lost link, so the controller stops DMA,
6169 * but we've got queued Tx work that's never going
6170 * to get done, so reset controller to flush Tx.
6171 * (Do the reset outside of interrupt context).
6172 */
c83c6cbd 6173 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6174 }
c4cf55e5 6175 }
c4cf55e5
PWJ		 6176}
6177
a985b6c3
GR		 6178static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6179{
6180 u32 ssvpc;
6181
6182 /* Do not perform spoof check for 82598 */
6183 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6184 return;
6185
6186 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6187
6188 /*
6189 * ssvpc register is cleared on read, if zero then no
6190 * spoofed packets in the last interval.
6191 */
6192 if (!ssvpc)
6193 return;
6194
6195 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6196}
6197
93c52dd0
AD		 6198/**
6199 * ixgbe_watchdog_subtask - check and bring link up
6200 * @adapter - pointer to the device adapter structure
6201 **/
6202static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6203{
6204 /* if interface is down do nothing */
6205 if (test_bit(__IXGBE_DOWN, &adapter->state))
6206 return;
6207
6208 ixgbe_watchdog_update_link(adapter);
6209
6210 if (adapter->link_up)
6211 ixgbe_watchdog_link_is_up(adapter);
6212 else
6213 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6214
a985b6c3 6215 ixgbe_spoof_check(adapter);
9a799d71 6216 ixgbe_update_stats(adapter);
93c52dd0
AD		 6217
6218 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6219}
10eec955 6220
cf8280ee 6221/**
7086400d
AD		 6222 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6223 * @adapter - the ixgbe adapter structure
cf8280ee 6224 **/
7086400d 6225static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6226{
cf8280ee 6227 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6228 s32 err;
cf8280ee 6229
7086400d
AD		 6230 /* not searching for SFP so there is nothing to do here */
6231 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6232 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6233 return;
10eec955 6234
7086400d
AD		 6235 /* someone else is in init, wait until next service event */
6236 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6237 return;
cf8280ee 6238
7086400d
AD		 6239 err = hw->phy.ops.identify_sfp(hw);
6240 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6241 goto sfp_out;
264857b8 6242
7086400d
AD		 6243 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6244 /* If no cable is present, then we need to reset
6245 * the next time we find a good cable. */
6246 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6247 }
9a799d71 6248
7086400d
AD		 6249 /* exit on error */
6250 if (err)
6251 goto sfp_out;
e8e26350 6252
7086400d
AD		 6253 /* exit if reset not needed */
6254 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6255 goto sfp_out;
9a799d71 6256
7086400d 6257 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6258
7086400d
AD		 6259 /*
6260 * A module may be identified correctly, but the EEPROM may not have
6261 * support for that module. setup_sfp() will fail in that case, so
6262 * we should not allow that module to load.
6263 */
6264 if (hw->mac.type == ixgbe_mac_82598EB)
6265 err = hw->phy.ops.reset(hw);
6266 else
6267 err = hw->mac.ops.setup_sfp(hw);
6268
6269 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6270 goto sfp_out;
6271
6272 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6273 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6274
6275sfp_out:
6276 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6277
6278 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6279 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6280 e_dev_err("failed to initialize because an unsupported "
6281 "SFP+ module type was detected.\n");
6282 e_dev_err("Reload the driver after installing a "
6283 "supported module.\n");
6284 unregister_netdev(adapter->netdev);
bc59fcda 6285 }
7086400d 6286}
bc59fcda 6287
7086400d
AD		 6288/**
6289 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6290 * @adapter - the ixgbe adapter structure
6291 **/
6292static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6293{
6294 struct ixgbe_hw *hw = &adapter->hw;
6295 u32 autoneg;
6296 bool negotiation;
6297
6298 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6299 return;
6300
6301 /* someone else is in init, wait until next service event */
6302 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6303 return;
6304
6305 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6306
6307 autoneg = hw->phy.autoneg_advertised;
6308 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6309 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6310 hw->mac.autotry_restart = false;
6311 if (hw->mac.ops.setup_link)
6312 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6313
6314 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6315 adapter->link_check_timeout = jiffies;
6316 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6317}
6318
6319/**
6320 * ixgbe_service_timer - Timer Call-back
6321 * @data: pointer to adapter cast into an unsigned long
6322 **/
6323static void ixgbe_service_timer(unsigned long data)
6324{
6325 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6326 unsigned long next_event_offset;
6327
6328 /* poll faster when waiting for link */
6329 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6330 next_event_offset = HZ / 10;
6331 else
6332 next_event_offset = HZ * 2;
6333
6334 /* Reset the timer */
6335 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6336
6337 ixgbe_service_event_schedule(adapter);
6338}
6339
c83c6cbd
AD		 6340static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6341{
6342 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6343 return;
6344
6345 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6346
6347 /* If we're already down or resetting, just bail */
6348 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6349 test_bit(__IXGBE_RESETTING, &adapter->state))
6350 return;
6351
6352 ixgbe_dump(adapter);
6353 netdev_err(adapter->netdev, "Reset adapter\n");
6354 adapter->tx_timeout_count++;
6355
6356 ixgbe_reinit_locked(adapter);
6357}
6358
7086400d
AD		 6359/**
6360 * ixgbe_service_task - manages and runs subtasks
6361 * @work: pointer to work_struct containing our data
6362 **/
6363static void ixgbe_service_task(struct work_struct *work)
6364{
6365 struct ixgbe_adapter *adapter = container_of(work,
6366 struct ixgbe_adapter,
6367 service_task);
6368
c83c6cbd 6369 ixgbe_reset_subtask(adapter);
7086400d
AD		 6370 ixgbe_sfp_detection_subtask(adapter);
6371 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6372 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6373 ixgbe_watchdog_subtask(adapter);
d034acf1 6374 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6375 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6376
6377 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6378}
6379
9a799d71 6380static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696 6381 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5e09a105 6382 u32 tx_flags, u8 *hdr_len, __be16 protocol)
9a799d71
AK		 6383{
6384 struct ixgbe_adv_tx_context_desc *context_desc;
6385 unsigned int i;
6386 int err;
6387 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 6388 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6389 u32 mss_l4len_idx, l4len;
9a799d71
AK		 6390
6391 if (skb_is_gso(skb)) {
6392 if (skb_header_cloned(skb)) {
6393 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6394 if (err)
6395 return err;
6396 }
6397 l4len = tcp_hdrlen(skb);
6398 *hdr_len += l4len;
6399
5e09a105 6400 if (protocol == htons(ETH_P_IP)) {
9a799d71
AK		 6401 struct iphdr *iph = ip_hdr(skb);
6402 iph->tot_len = 0;
6403 iph->check = 0;
6404 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 6405 iph->daddr, 0,
6406 IPPROTO_TCP,
6407 0);
8e1e8a47 6408 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 6409 ipv6_hdr(skb)->payload_len = 0;
6410 tcp_hdr(skb)->check =
6411 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 6412 &ipv6_hdr(skb)->daddr,
6413 0, IPPROTO_TCP, 0);
9a799d71
AK		 6414 }
6415
6416 i = tx_ring->next_to_use;
6417
6418 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6419 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6420
6421 /* VLAN MACLEN IPLEN */
6422 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6423 vlan_macip_lens |=
6424 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6425 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 6426 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6427 *hdr_len += skb_network_offset(skb);
6428 vlan_macip_lens |=
6429 (skb_transport_header(skb) - skb_network_header(skb));
6430 *hdr_len +=
6431 (skb_transport_header(skb) - skb_network_header(skb));
6432 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6433 context_desc->seqnum_seed = 0;
6434
6435 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 6436 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 6437 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6438
5e09a105 6439 if (protocol == htons(ETH_P_IP))
9a799d71
AK		 6440 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6441 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6442 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6443
6444 /* MSS L4LEN IDX */
9f8cdf4f 6445 mss_l4len_idx =
9a799d71
AK		 6446 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6447 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 6448 /* use index 1 for TSO */
6449 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6450 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6451
6452 tx_buffer_info->time_stamp = jiffies;
6453 tx_buffer_info->next_to_watch = i;
6454
6455 i++;
6456 if (i == tx_ring->count)
6457 i = 0;
6458 tx_ring->next_to_use = i;
6459
6460 return true;
6461 }
6462 return false;
6463}
6464
5e09a105
HZ		 6465static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6466 __be16 protocol)
7ca647bd
JP		 6467{
6468 u32 rtn = 0;
7ca647bd
JP		 6469
6470 switch (protocol) {
6471 case cpu_to_be16(ETH_P_IP):
6472 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6473 switch (ip_hdr(skb)->protocol) {
6474 case IPPROTO_TCP:
6475 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6476 break;
6477 case IPPROTO_SCTP:
6478 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6479 break;
6480 }
6481 break;
6482 case cpu_to_be16(ETH_P_IPV6):
6483 /* XXX what about other V6 headers?? */
6484 switch (ipv6_hdr(skb)->nexthdr) {
6485 case IPPROTO_TCP:
6486 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6487 break;
6488 case IPPROTO_SCTP:
6489 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6490 break;
6491 }
6492 break;
6493 default:
6494 if (unlikely(net_ratelimit()))
6495 e_warn(probe, "partial checksum but proto=%x!\n",
5e09a105 6496 protocol);
7ca647bd
JP		 6497 break;
6498 }
6499
6500 return rtn;
6501}
6502
9a799d71 6503static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696 6504 struct ixgbe_ring *tx_ring,
5e09a105
HZ		 6505 struct sk_buff *skb, u32 tx_flags,
6506 __be16 protocol)
9a799d71
AK		 6507{
6508 struct ixgbe_adv_tx_context_desc *context_desc;
6509 unsigned int i;
6510 struct ixgbe_tx_buffer *tx_buffer_info;
6511 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6512
6513 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6514 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6515 i = tx_ring->next_to_use;
6516 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6517 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6518
6519 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6520 vlan_macip_lens |=
6521 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6522 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 6523 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6524 if (skb->ip_summed == CHECKSUM_PARTIAL)
6525 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 6526 skb_network_header(skb));
9a799d71
AK		 6527
6528 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6529 context_desc->seqnum_seed = 0;
6530
6531 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 6532 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6533
7ca647bd 6534 if (skb->ip_summed == CHECKSUM_PARTIAL)
5e09a105 6535 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
9a799d71
AK		 6536
6537 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 6538 /* use index zero for tx checksum offload */
9a799d71
AK		 6539 context_desc->mss_l4len_idx = 0;
6540
6541 tx_buffer_info->time_stamp = jiffies;
6542 tx_buffer_info->next_to_watch = i;
9f8cdf4f 6543
9a799d71
AK		 6544 i++;
6545 if (i == tx_ring->count)
6546 i = 0;
6547 tx_ring->next_to_use = i;
6548
6549 return true;
6550 }
9f8cdf4f 6551
9a799d71
AK		 6552 return false;
6553}
6554
6555static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6556 struct ixgbe_ring *tx_ring,
6557 struct sk_buff *skb, u32 tx_flags,
8ad494b0 6558 unsigned int first, const u8 hdr_len)
9a799d71 6559{
b6ec895e 6560 struct device *dev = tx_ring->dev;
9a799d71 6561 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6562 unsigned int len;
6563 unsigned int total = skb->len;
9a799d71
AK		 6564 unsigned int offset = 0, size, count = 0, i;
6565 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6566 unsigned int f;
8ad494b0
AD		 6567 unsigned int bytecount = skb->len;
6568 u16 gso_segs = 1;
9a799d71
AK		 6569
6570 i = tx_ring->next_to_use;
6571
eacd73f7
YZ		 6572 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6573 /* excluding fcoe_crc_eof for FCoE */
6574 total -= sizeof(struct fcoe_crc_eof);
6575
6576 len = min(skb_headlen(skb), total);
9a799d71
AK		 6577 while (len) {
6578 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6579 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6580
6581 tx_buffer_info->length = size;
e5a43549 6582 tx_buffer_info->mapped_as_page = false;
b6ec895e 6583 tx_buffer_info->dma = dma_map_single(dev,
e5a43549 6584 skb->data + offset,
1b507730 6585 size, DMA_TO_DEVICE);
b6ec895e 6586 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6587 goto dma_error;
9a799d71
AK		 6588 tx_buffer_info->time_stamp = jiffies;
6589 tx_buffer_info->next_to_watch = i;
6590
6591 len -= size;
eacd73f7 6592 total -= size;
9a799d71
AK		 6593 offset += size;
6594 count++;
44df32c5
AD		 6595
6596 if (len) {
6597 i++;
6598 if (i == tx_ring->count)
6599 i = 0;
6600 }
9a799d71
AK		 6601 }
6602
6603 for (f = 0; f < nr_frags; f++) {
6604 struct skb_frag_struct *frag;
6605
6606 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6607 len = min((unsigned int)frag->size, total);
e5a43549 6608 offset = frag->page_offset;
9a799d71
AK		 6609
6610 while (len) {
44df32c5
AD		 6611 i++;
6612 if (i == tx_ring->count)
6613 i = 0;
6614
9a799d71
AK		 6615 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6616 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6617
6618 tx_buffer_info->length = size;
b6ec895e 6619 tx_buffer_info->dma = dma_map_page(dev,
e5a43549
AD		 6620 frag->page,
6621 offset, size,
1b507730 6622 DMA_TO_DEVICE);
e5a43549 6623 tx_buffer_info->mapped_as_page = true;
b6ec895e 6624 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6625 goto dma_error;
9a799d71
AK		 6626 tx_buffer_info->time_stamp = jiffies;
6627 tx_buffer_info->next_to_watch = i;
6628
6629 len -= size;
eacd73f7 6630 total -= size;
9a799d71
AK		 6631 offset += size;
6632 count++;
9a799d71 6633 }
eacd73f7
YZ		 6634 if (total == 0)
6635 break;
9a799d71 6636 }
44df32c5 6637
8ad494b0
AD		 6638 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6639 gso_segs = skb_shinfo(skb)->gso_segs;
6640#ifdef IXGBE_FCOE
6641 /* adjust for FCoE Sequence Offload */
6642 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6643 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6644 skb_shinfo(skb)->gso_size);
6645#endif /* IXGBE_FCOE */
6646 bytecount += (gso_segs - 1) * hdr_len;
6647
6648 /* multiply data chunks by size of headers */
6649 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6650 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
9a799d71
AK		 6651 tx_ring->tx_buffer_info[i].skb = skb;
6652 tx_ring->tx_buffer_info[first].next_to_watch = i;
6653
e5a43549
AD		 6654 return count;
6655
6656dma_error:
849c4542 6657 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6658
6659 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6660 tx_buffer_info->dma = 0;
6661 tx_buffer_info->time_stamp = 0;
6662 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6663 if (count)
6664 count--;
e5a43549
AD		 6665
6666 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6667 while (count--) {
e8e9f696 6668 if (i == 0)
e5a43549 6669 i += tx_ring->count;
c1fa347f 6670 i--;
e5a43549 6671 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 6672 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
e5a43549
AD		 6673 }
6674
e44d38e1 6675 return 0;
9a799d71
AK		 6676}
6677
84ea2591 6678static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
e8e9f696 6679 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6680{
6681 union ixgbe_adv_tx_desc *tx_desc = NULL;
6682 struct ixgbe_tx_buffer *tx_buffer_info;
6683 u32 olinfo_status = 0, cmd_type_len = 0;
6684 unsigned int i;
6685 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6686
6687 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6688
6689 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6690
6691 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6692 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6693
6694 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6695 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6696
6697 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6698 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6699
4eeae6fd
PW		 6700 /* use index 1 context for tso */
6701 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6702 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6703 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6704 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6705
6706 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6707 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6708 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6709
eacd73f7
YZ		 6710 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6711 olinfo_status |= IXGBE_ADVTXD_CC;
6712 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6713 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6714 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6715 }
6716
9a799d71
AK		 6717 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6718
6719 i = tx_ring->next_to_use;
6720 while (count--) {
6721 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6722 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6723 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6724 tx_desc->read.cmd_type_len =
e8e9f696 6725 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6726 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6727 i++;
6728 if (i == tx_ring->count)
6729 i = 0;
6730 }
6731
6732 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6733
6734 /*
6735 * Force memory writes to complete before letting h/w
6736 * know there are new descriptors to fetch. (Only
6737 * applicable for weak-ordered memory model archs,
6738 * such as IA-64).
6739 */
6740 wmb();
6741
6742 tx_ring->next_to_use = i;
84ea2591 6743 writel(i, tx_ring->tail);
9a799d71
AK		 6744}
6745
69830529
AD		 6746static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6747 u32 tx_flags, __be16 protocol)
6748{
6749 struct ixgbe_q_vector *q_vector = ring->q_vector;
6750 union ixgbe_atr_hash_dword input = { .dword = 0 };
6751 union ixgbe_atr_hash_dword common = { .dword = 0 };
6752 union {
6753 unsigned char *network;
6754 struct iphdr *ipv4;
6755 struct ipv6hdr *ipv6;
6756 } hdr;
ee9e0f0b 6757 struct tcphdr *th;
905e4a41 6758 __be16 vlan_id;
c4cf55e5 6759
69830529
AD		 6760 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6761 if (!q_vector)
6762 return;
6763
6764 /* do nothing if sampling is disabled */
6765 if (!ring->atr_sample_rate)
d3ead241 6766 return;
c4cf55e5 6767
69830529 6768 ring->atr_count++;
c4cf55e5 6769
69830529
AD		 6770 /* snag network header to get L4 type and address */
6771 hdr.network = skb_network_header(skb);
6772
6773 /* Currently only IPv4/IPv6 with TCP is supported */
6774 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6775 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6776 (protocol != __constant_htons(ETH_P_IP) ||
6777 hdr.ipv4->protocol != IPPROTO_TCP))
6778 return;
ee9e0f0b
AD		 6779
6780 th = tcp_hdr(skb);
c4cf55e5 6781
69830529
AD		 6782 /* skip this packet since the socket is closing */
6783 if (th->fin)
6784 return;
6785
6786 /* sample on all syn packets or once every atr sample count */
6787 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6788 return;
6789
6790 /* reset sample count */
6791 ring->atr_count = 0;
6792
6793 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6794
6795 /*
6796 * src and dst are inverted, think how the receiver sees them
6797 *
6798 * The input is broken into two sections, a non-compressed section
6799 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6800 * is XORed together and stored in the compressed dword.
6801 */
6802 input.formatted.vlan_id = vlan_id;
6803
6804 /*
6805 * since src port and flex bytes occupy the same word XOR them together
6806 * and write the value to source port portion of compressed dword
6807 */
6808 if (vlan_id)
6809 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6810 else
6811 common.port.src ^= th->dest ^ protocol;
6812 common.port.dst ^= th->source;
6813
6814 if (protocol == __constant_htons(ETH_P_IP)) {
6815 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6816 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6817 } else {
6818 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6819 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6820 hdr.ipv6->saddr.s6_addr32[1] ^
6821 hdr.ipv6->saddr.s6_addr32[2] ^
6822 hdr.ipv6->saddr.s6_addr32[3] ^
6823 hdr.ipv6->daddr.s6_addr32[0] ^
6824 hdr.ipv6->daddr.s6_addr32[1] ^
6825 hdr.ipv6->daddr.s6_addr32[2] ^
6826 hdr.ipv6->daddr.s6_addr32[3];
6827 }
c4cf55e5
PWJ		 6828
6829 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6830 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6831 input, common, ring->queue_index);
c4cf55e5
PWJ		 6832}
6833
fc77dc3c 6834static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60 6835{
fc77dc3c 6836 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6837 /* Herbert's original patch had:
6838 * smp_mb__after_netif_stop_queue();
6839 * but since that doesn't exist yet, just open code it. */
6840 smp_mb();
6841
6842 /* We need to check again in a case another CPU has just
6843 * made room available. */
6844 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6845 return -EBUSY;
6846
6847 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6848 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6849 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6850 return 0;
6851}
6852
fc77dc3c 6853static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6854{
6855 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6856 return 0;
fc77dc3c 6857 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6858}
6859
09a3b1f8
SH		 6860static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6861{
6862 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6863 int txq = smp_processor_id();
56075a98 6864#ifdef IXGBE_FCOE
5e09a105
HZ		 6865 __be16 protocol;
6866
6867 protocol = vlan_get_protocol(skb);
6868
e5b64635
JF		 6869 if (((protocol == htons(ETH_P_FCOE)) ||
6870 (protocol == htons(ETH_P_FIP))) &&
6871 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6872 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6873 txq += adapter->ring_feature[RING_F_FCOE].mask;
6874 return txq;
56075a98
JF		 6875 }
6876#endif
6877
fdd3d631
KK		 6878 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6879 while (unlikely(txq >= dev->real_num_tx_queues))
6880 txq -= dev->real_num_tx_queues;
5f715823 6881 return txq;
fdd3d631 6882 }
c4cf55e5 6883
09a3b1f8
SH		 6884 return skb_tx_hash(dev, skb);
6885}
6886
fc77dc3c 6887netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6888 struct ixgbe_adapter *adapter,
6889 struct ixgbe_ring *tx_ring)
9a799d71 6890{
9a799d71
AK		 6891 unsigned int first;
6892 unsigned int tx_flags = 0;
30eba97a 6893 u8 hdr_len = 0;
5f715823 6894 int tso;
9a799d71
AK		 6895 int count = 0;
6896 unsigned int f;
5e09a105
HZ		 6897 __be16 protocol;
6898
6899 protocol = vlan_get_protocol(skb);
9f8cdf4f 6900
eab6d18d 6901 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6902 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6903 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6904 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
e5b64635 6905 tx_flags |= tx_ring->dcb_tc << 13;
2f90b865
AD		 6906 }
6907 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6908 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6909 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6910 skb->priority != TC_PRIO_CONTROL) {
e5b64635 6911 tx_flags |= tx_ring->dcb_tc << 13;
2ea186ae
JF		 6912 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6913 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6914 }
eacd73f7 6915
09ad1cc0 6916#ifdef IXGBE_FCOE
56075a98
JF		 6917 /* for FCoE with DCB, we force the priority to what
6918 * was specified by the switch */
6919 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
e5b64635
JF		 6920 (protocol == htons(ETH_P_FCOE)))
6921 tx_flags |= IXGBE_TX_FLAGS_FCOE;
ca77cd59
RL		 6922#endif
6923
eacd73f7 6924 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6925 if (skb_is_gso(skb) ||
6926 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6927 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6928 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6929 count++;
6930
9f8cdf4f
JB		 6931 count += TXD_USE_COUNT(skb_headlen(skb));
6932 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6933 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6934
fc77dc3c 6935 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
5b7da515 6936 tx_ring->tx_stats.tx_busy++;
9a799d71
AK		 6937 return NETDEV_TX_BUSY;
6938 }
9a799d71 6939
9a799d71 6940 first = tx_ring->next_to_use;
eacd73f7
YZ		 6941 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6942#ifdef IXGBE_FCOE
6943 /* setup tx offload for FCoE */
6944 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6945 if (tso < 0) {
6946 dev_kfree_skb_any(skb);
6947 return NETDEV_TX_OK;
6948 }
6949 if (tso)
6950 tx_flags |= IXGBE_TX_FLAGS_FSO;
6951#endif /* IXGBE_FCOE */
6952 } else {
5e09a105 6953 if (protocol == htons(ETH_P_IP))
eacd73f7 6954 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5e09a105
HZ		 6955 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6956 protocol);
eacd73f7
YZ		 6957 if (tso < 0) {
6958 dev_kfree_skb_any(skb);
6959 return NETDEV_TX_OK;
6960 }
9a799d71 6961
eacd73f7
YZ		 6962 if (tso)
6963 tx_flags |= IXGBE_TX_FLAGS_TSO;
5e09a105
HZ		 6964 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6965 protocol) &&
eacd73f7
YZ		 6966 (skb->ip_summed == CHECKSUM_PARTIAL))
6967 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6968 }
9a799d71 6969
8ad494b0 6970 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
44df32c5 6971 if (count) {
c4cf55e5 6972 /* add the ATR filter if ATR is on */
69830529
AD		 6973 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6974 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
84ea2591 6975 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
fc77dc3c 6976 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71 6977
44df32c5
AD		 6978 } else {
6979 dev_kfree_skb_any(skb);
6980 tx_ring->tx_buffer_info[first].time_stamp = 0;
6981 tx_ring->next_to_use = first;
6982 }
9a799d71
AK		 6983
6984 return NETDEV_TX_OK;
6985}
6986
84418e3b
AD		 6987static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6988{
6989 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6990 struct ixgbe_ring *tx_ring;
6991
6992 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6993 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6994}
6995
9a799d71
AK		 6996/**
6997 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6998 * @netdev: network interface device structure
6999 * @p: pointer to an address structure
7000 *
7001 * Returns 0 on success, negative on failure
7002 **/
7003static int ixgbe_set_mac(struct net_device *netdev, void *p)
7004{
7005 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7006 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7007 struct sockaddr *addr = p;
7008
7009 if (!is_valid_ether_addr(addr->sa_data))
7010 return -EADDRNOTAVAIL;
7011
7012 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7013 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7014
1cdd1ec8
GR		 7015 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
7016 IXGBE_RAH_AV);
9a799d71
AK		 7017
7018 return 0;
7019}
7020
6b73e10d
BH		 7021static int
7022ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7023{
7024 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7025 struct ixgbe_hw *hw = &adapter->hw;
7026 u16 value;
7027 int rc;
7028
7029 if (prtad != hw->phy.mdio.prtad)
7030 return -EINVAL;
7031 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7032 if (!rc)
7033 rc = value;
7034 return rc;
7035}
7036
7037static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7038 u16 addr, u16 value)
7039{
7040 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7041 struct ixgbe_hw *hw = &adapter->hw;
7042
7043 if (prtad != hw->phy.mdio.prtad)
7044 return -EINVAL;
7045 return hw->phy.ops.write_reg(hw, addr, devad, value);
7046}
7047
7048static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7049{
7050 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7051
7052 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7053}
7054
0365e6e4
PW		 7055/**
7056 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7057 * netdev->dev_addrs
0365e6e4
PW		 7058 * @netdev: network interface device structure
7059 *
7060 * Returns non-zero on failure
7061 **/
7062static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7063{
7064 int err = 0;
7065 struct ixgbe_adapter *adapter = netdev_priv(dev);
7066 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7067
7068 if (is_valid_ether_addr(mac->san_addr)) {
7069 rtnl_lock();
7070 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7071 rtnl_unlock();
7072 }
7073 return err;
7074}
7075
7076/**
7077 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7078 * netdev->dev_addrs
0365e6e4
PW		 7079 * @netdev: network interface device structure
7080 *
7081 * Returns non-zero on failure
7082 **/
7083static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7084{
7085 int err = 0;
7086 struct ixgbe_adapter *adapter = netdev_priv(dev);
7087 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7088
7089 if (is_valid_ether_addr(mac->san_addr)) {
7090 rtnl_lock();
7091 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7092 rtnl_unlock();
7093 }
7094 return err;
7095}
7096
9a799d71
AK		 7097#ifdef CONFIG_NET_POLL_CONTROLLER
7098/*
7099 * Polling 'interrupt' - used by things like netconsole to send skbs
7100 * without having to re-enable interrupts. It's not called while
7101 * the interrupt routine is executing.
7102 */
7103static void ixgbe_netpoll(struct net_device *netdev)
7104{
7105 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7106 int i;
9a799d71 7107
1a647bd2
AD		 7108 /* if interface is down do nothing */
7109 if (test_bit(__IXGBE_DOWN, &adapter->state))
7110 return;
7111
9a799d71 7112 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7113 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7114 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7115 for (i = 0; i < num_q_vectors; i++) {
7116 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7117 ixgbe_msix_clean_many(0, q_vector);
7118 }
7119 } else {
7120 ixgbe_intr(adapter->pdev->irq, netdev);
7121 }
9a799d71 7122 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7123}
7124#endif
7125
de1036b1
ED		 7126static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7127 struct rtnl_link_stats64 *stats)
7128{
7129 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7130 int i;
7131
1a51502b 7132 rcu_read_lock();
de1036b1 7133 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7134 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7135 u64 bytes, packets;
7136 unsigned int start;
7137
1a51502b
ED		 7138 if (ring) {
7139 do {
7140 start = u64_stats_fetch_begin_bh(&ring->syncp);
7141 packets = ring->stats.packets;
7142 bytes = ring->stats.bytes;
7143 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7144 stats->rx_packets += packets;
7145 stats->rx_bytes += bytes;
7146 }
de1036b1 7147 }
1ac9ad13
ED		 7148
7149 for (i = 0; i < adapter->num_tx_queues; i++) {
7150 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7151 u64 bytes, packets;
7152 unsigned int start;
7153
7154 if (ring) {
7155 do {
7156 start = u64_stats_fetch_begin_bh(&ring->syncp);
7157 packets = ring->stats.packets;
7158 bytes = ring->stats.bytes;
7159 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7160 stats->tx_packets += packets;
7161 stats->tx_bytes += bytes;
7162 }
7163 }
1a51502b 7164 rcu_read_unlock();
de1036b1
ED		 7165 /* following stats updated by ixgbe_watchdog_task() */
7166 stats->multicast = netdev->stats.multicast;
7167 stats->rx_errors = netdev->stats.rx_errors;
7168 stats->rx_length_errors = netdev->stats.rx_length_errors;
7169 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7170 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7171 return stats;
7172}
7173
8b1c0b24
JF		 7174/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7175 * #adapter: pointer to ixgbe_adapter
7176 * @tc: number of traffic classes currently enabled
7177 *
7178 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7179 * 802.1Q priority maps to a packet buffer that exists.
7180 */
7181static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7182{
7183 struct ixgbe_hw *hw = &adapter->hw;
7184 u32 reg, rsave;
7185 int i;
7186
7187 /* 82598 have a static priority to TC mapping that can not
7188 * be changed so no validation is needed.
7189 */
7190 if (hw->mac.type == ixgbe_mac_82598EB)
7191 return;
7192
7193 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7194 rsave = reg;
7195
7196 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7197 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7198
7199 /* If up2tc is out of bounds default to zero */
7200 if (up2tc > tc)
7201 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7202 }
7203
7204 if (reg != rsave)
7205 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7206
7207 return;
7208}
7209
7210
7211/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7212 * classes.
7213 *
7214 * @netdev: net device to configure
7215 * @tc: number of traffic classes to enable
7216 */
7217int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7218{
8b1c0b24
JF		 7219 struct ixgbe_adapter *adapter = netdev_priv(dev);
7220 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24
JF		 7221
7222 /* If DCB is anabled do not remove traffic classes, multiple
7223 * traffic classes are required to implement DCB
7224 */
7225 if (!tc && (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7226 return 0;
7227
7228 /* Hardware supports up to 8 traffic classes */
7229 if (tc > MAX_TRAFFIC_CLASS ||
7230 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7231 return -EINVAL;
7232
7233 /* Hardware has to reinitialize queues and interrupts to
7234 * match packet buffer alignment. Unfortunantly, the
7235 * hardware is not flexible enough to do this dynamically.
7236 */
7237 if (netif_running(dev))
7238 ixgbe_close(dev);
7239 ixgbe_clear_interrupt_scheme(adapter);
7240
7241 if (tc)
7242 netdev_set_num_tc(dev, tc);
7243 else
7244 netdev_reset_tc(dev);
7245
8b1c0b24
JF		 7246 ixgbe_init_interrupt_scheme(adapter);
7247 ixgbe_validate_rtr(adapter, tc);
7248 if (netif_running(dev))
7249 ixgbe_open(dev);
7250
7251 return 0;
7252}
de1036b1 7253
0edc3527 7254static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7255 .ndo_open = ixgbe_open,
0edc3527 7256 .ndo_stop = ixgbe_close,
00829823 7257 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7258 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7259 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7260 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7261 .ndo_validate_addr = eth_validate_addr,
7262 .ndo_set_mac_address = ixgbe_set_mac,
7263 .ndo_change_mtu = ixgbe_change_mtu,
7264 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7265 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7266 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7267 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7268 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7269 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7270 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7271 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7272 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7273 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7274#ifdef CONFIG_NET_POLL_CONTROLLER
7275 .ndo_poll_controller = ixgbe_netpoll,
7276#endif
332d4a7d
YZ		 7277#ifdef IXGBE_FCOE
7278 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7279 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7280 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7281 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7282 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7283 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7284#endif /* IXGBE_FCOE */
0edc3527
SH		 7285};
7286
1cdd1ec8
GR		 7287static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7288 const struct ixgbe_info *ii)
7289{
7290#ifdef CONFIG_PCI_IOV
7291 struct ixgbe_hw *hw = &adapter->hw;
7292 int err;
a1cbb15c
GR		 7293 int num_vf_macvlans, i;
7294 struct vf_macvlans *mv_list;
1cdd1ec8 7295
3377eba7 7296 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
1cdd1ec8
GR		 7297 return;
7298
7299 /* The 82599 supports up to 64 VFs per physical function
7300 * but this implementation limits allocation to 63 so that
7301 * basic networking resources are still available to the
7302 * physical function
7303 */
7304 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7305 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7306 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7307 if (err) {
396e799c 7308 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 7309 goto err_novfs;
7310 }
a1cbb15c
GR		 7311
7312 num_vf_macvlans = hw->mac.num_rar_entries -
7313 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7314
7315 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7316 sizeof(struct vf_macvlans),
7317 GFP_KERNEL);
7318 if (mv_list) {
7319 /* Initialize list of VF macvlans */
7320 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7321 for (i = 0; i < num_vf_macvlans; i++) {
7322 mv_list->vf = -1;
7323 mv_list->free = true;
7324 mv_list->rar_entry = hw->mac.num_rar_entries -
7325 (i + adapter->num_vfs + 1);
7326 list_add(&mv_list->l, &adapter->vf_mvs.l);
7327 mv_list++;
7328 }
7329 }
7330
1cdd1ec8
GR		 7331 /* If call to enable VFs succeeded then allocate memory
7332 * for per VF control structures.
7333 */
7334 adapter->vfinfo =
7335 kcalloc(adapter->num_vfs,
7336 sizeof(struct vf_data_storage), GFP_KERNEL);
7337 if (adapter->vfinfo) {
7338 /* Now that we're sure SR-IOV is enabled
7339 * and memory allocated set up the mailbox parameters
7340 */
7341 ixgbe_init_mbx_params_pf(hw);
7342 memcpy(&hw->mbx.ops, ii->mbx_ops,
7343 sizeof(hw->mbx.ops));
7344
7345 /* Disable RSC when in SR-IOV mode */
7346 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7347 IXGBE_FLAG2_RSC_ENABLED);
7348 return;
7349 }
7350
7351 /* Oh oh */
396e799c
ET		 7352 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7353 "SRIOV disabled\n");
1cdd1ec8
GR		 7354 pci_disable_sriov(adapter->pdev);
7355
7356err_novfs:
7357 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7358 adapter->num_vfs = 0;
7359#endif /* CONFIG_PCI_IOV */
7360}
7361
9a799d71
AK		 7362/**
7363 * ixgbe_probe - Device Initialization Routine
7364 * @pdev: PCI device information struct
7365 * @ent: entry in ixgbe_pci_tbl
7366 *
7367 * Returns 0 on success, negative on failure
7368 *
7369 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7370 * The OS initialization, configuring of the adapter private structure,
7371 * and a hardware reset occur.
7372 **/
7373static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7374 const struct pci_device_id *ent)
9a799d71
AK		 7375{
7376 struct net_device *netdev;
7377 struct ixgbe_adapter *adapter = NULL;
7378 struct ixgbe_hw *hw;
7379 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7380 static int cards_found;
7381 int i, err, pci_using_dac;
289700db 7382 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7383 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7384#ifdef IXGBE_FCOE
7385 u16 device_caps;
7386#endif
289700db 7387 u32 eec;
9a799d71 7388
bded64a7
AG		 7389 /* Catch broken hardware that put the wrong VF device ID in
7390 * the PCIe SR-IOV capability.
7391 */
7392 if (pdev->is_virtfn) {
7393 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7394 pci_name(pdev), pdev->vendor, pdev->device);
7395 return -EINVAL;
7396 }
7397
9ce77666 7398 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7399 if (err)
7400 return err;
7401
1b507730
NN		 7402 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7403 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7404 pci_using_dac = 1;
7405 } else {
1b507730 7406 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7407 if (err) {
1b507730
NN		 7408 err = dma_set_coherent_mask(&pdev->dev,
7409 DMA_BIT_MASK(32));
9a799d71 7410 if (err) {
b8bc0421
DC		 7411 dev_err(&pdev->dev,
7412 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7413 goto err_dma;
7414 }
7415 }
7416 pci_using_dac = 0;
7417 }
7418
9ce77666 7419 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7420 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7421 if (err) {
b8bc0421
DC		 7422 dev_err(&pdev->dev,
7423 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7424 goto err_pci_reg;
7425 }
7426
19d5afd4 7427 pci_enable_pcie_error_reporting(pdev);
6fabd715 7428
9a799d71 7429 pci_set_master(pdev);
fb3b27bc 7430 pci_save_state(pdev);
9a799d71 7431
e901acd6
JF		 7432#ifdef CONFIG_IXGBE_DCB
7433 indices *= MAX_TRAFFIC_CLASS;
7434#endif
7435
c85a2618
JF		 7436 if (ii->mac == ixgbe_mac_82598EB)
7437 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7438 else
7439 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7440
e901acd6 7441#ifdef IXGBE_FCOE
c85a2618
JF		 7442 indices += min_t(unsigned int, num_possible_cpus(),
7443 IXGBE_MAX_FCOE_INDICES);
7444#endif
c85a2618 7445 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7446 if (!netdev) {
7447 err = -ENOMEM;
7448 goto err_alloc_etherdev;
7449 }
7450
9a799d71
AK		 7451 SET_NETDEV_DEV(netdev, &pdev->dev);
7452
9a799d71 7453 adapter = netdev_priv(netdev);
c60fbb00 7454 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7455
7456 adapter->netdev = netdev;
7457 adapter->pdev = pdev;
7458 hw = &adapter->hw;
7459 hw->back = adapter;
7460 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7461
05857980 7462 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7463 pci_resource_len(pdev, 0));
9a799d71
AK		 7464 if (!hw->hw_addr) {
7465 err = -EIO;
7466 goto err_ioremap;
7467 }
7468
7469 for (i = 1; i <= 5; i++) {
7470 if (pci_resource_len(pdev, i) == 0)
7471 continue;
7472 }
7473
0edc3527 7474 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7475 ixgbe_set_ethtool_ops(netdev);
9a799d71 7476 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7477 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7478
9a799d71
AK		 7479 adapter->bd_number = cards_found;
7480
9a799d71
AK		 7481 /* Setup hw api */
7482 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7483 hw->mac.type = ii->mac;
9a799d71 7484
c44ade9e
JB		 7485 /* EEPROM */
7486 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7487 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7488 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7489 if (!(eec & (1 << 8)))
7490 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7491
7492 /* PHY */
7493 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7494 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7495 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7496 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7497 hw->phy.mdio.mmds = 0;
7498 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7499 hw->phy.mdio.dev = netdev;
7500 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7501 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7502
8ca783ab 7503 ii->get_invariants(hw);
9a799d71
AK		 7504
7505 /* setup the private structure */
7506 err = ixgbe_sw_init(adapter);
7507 if (err)
7508 goto err_sw_init;
7509
e86bff0e 7510 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7511 switch (adapter->hw.mac.type) {
7512 case ixgbe_mac_82599EB:
7513 case ixgbe_mac_X540:
e86bff0e 7514 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7515 break;
7516 default:
7517 break;
7518 }
e86bff0e 7519
bf069c97
DS		 7520 /*
7521 * If there is a fan on this device and it has failed log the
7522 * failure.
7523 */
7524 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7525 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7526 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7527 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7528 }
7529
c44ade9e 7530 /* reset_hw fills in the perm_addr as well */
119fc60a 7531 hw->phy.reset_if_overtemp = true;
c44ade9e 7532 err = hw->mac.ops.reset_hw(hw);
119fc60a 7533 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7534 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7535 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7536 err = 0;
7537 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7538 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7539 "module type was detected.\n");
7540 e_dev_err("Reload the driver after installing a supported "
7541 "module.\n");
04f165ef
PW		 7542 goto err_sw_init;
7543 } else if (err) {
849c4542 7544 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7545 goto err_sw_init;
7546 }
7547
1cdd1ec8
GR		 7548 ixgbe_probe_vf(adapter, ii);
7549
396e799c 7550 netdev->features = NETIF_F_SG |
e8e9f696
JP		 7551 NETIF_F_IP_CSUM |
7552 NETIF_F_HW_VLAN_TX |
7553 NETIF_F_HW_VLAN_RX |
7554 NETIF_F_HW_VLAN_FILTER;
9a799d71 7555
e9990a9c 7556 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 7557 netdev->features |= NETIF_F_TSO;
9a799d71 7558 netdev->features |= NETIF_F_TSO6;
78b6f4ce 7559 netdev->features |= NETIF_F_GRO;
67a74ee2 7560 netdev->features |= NETIF_F_RXHASH;
ad31c402 7561
58be7666
DS		 7562 switch (adapter->hw.mac.type) {
7563 case ixgbe_mac_82599EB:
7564 case ixgbe_mac_X540:
45a5ead0 7565 netdev->features |= NETIF_F_SCTP_CSUM;
58be7666
DS		 7566 break;
7567 default:
7568 break;
7569 }
45a5ead0 7570
ad31c402
JK		 7571 netdev->vlan_features |= NETIF_F_TSO;
7572 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7573 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7574 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7575 netdev->vlan_features |= NETIF_F_SG;
7576
1cdd1ec8
GR		 7577 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7578 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7579 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7580
7a6b6f51 7581#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7582 netdev->dcbnl_ops = &dcbnl_ops;
7583#endif
7584
eacd73f7 7585#ifdef IXGBE_FCOE
0d551589 7586 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7587 if (hw->mac.ops.get_device_caps) {
7588 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7589 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7590 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7591 }
7592 }
5e09d7f6
YZ		 7593 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7594 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7595 netdev->vlan_features |= NETIF_F_FSO;
7596 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7597 }
eacd73f7 7598#endif /* IXGBE_FCOE */
7b872a55 7599 if (pci_using_dac) {
9a799d71 7600 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7601 netdev->vlan_features |= NETIF_F_HIGHDMA;
7602 }
9a799d71 7603
0c19d6af 7604 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7605 netdev->features |= NETIF_F_LRO;
7606
9a799d71 7607 /* make sure the EEPROM is good */
c44ade9e 7608 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7609 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7610 err = -EIO;
7611 goto err_eeprom;
7612 }
7613
7614 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7615 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7616
c44ade9e 7617 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7618 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7619 err = -EIO;
7620 goto err_eeprom;
7621 }
7622
c6ecf39a
DS		 7623 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7624 if (hw->mac.ops.disable_tx_laser &&
7625 ((hw->phy.multispeed_fiber) ||
9f911707 7626 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 7627 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 7628 hw->mac.ops.disable_tx_laser(hw);
7629
7086400d
AD		 7630 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7631 (unsigned long) adapter);
9a799d71 7632
7086400d
AD		 7633 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7634 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7635
021230d4
AV		 7636 err = ixgbe_init_interrupt_scheme(adapter);
7637 if (err)
7638 goto err_sw_init;
9a799d71 7639
67a74ee2
ET		 7640 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7641 netdev->features &= ~NETIF_F_RXHASH;
7642
e8e26350 7643 switch (pdev->device) {
0b077fea
DS		 7644 case IXGBE_DEV_ID_82599_SFP:
7645 /* Only this subdevice supports WOL */
7646 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7647 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7648 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7649 break;
50d6c681
AD		 7650 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7651 /* All except this subdevice support WOL */
0b077fea
DS		 7652 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7653 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7654 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7655 break;
e8e26350 7656 case IXGBE_DEV_ID_82599_KX4:
495dce12 7657 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 7658 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 7659 break;
7660 default:
7661 adapter->wol = 0;
7662 break;
7663 }
e8e26350
PW		 7664 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7665
04f165ef
PW		 7666 /* pick up the PCI bus settings for reporting later */
7667 hw->mac.ops.get_bus_info(hw);
7668
9a799d71 7669 /* print bus type/speed/width info */
849c4542 7670 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7671 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7672 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7673 "Unknown"),
7674 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7675 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7676 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7677 "Unknown"),
7678 netdev->dev_addr);
289700db
DS		 7679
7680 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7681 if (err)
9fe93afd 7682 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7683 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7684 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7685 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7686 part_str);
e8e26350 7687 else
289700db
DS		 7688 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7689 hw->mac.type, hw->phy.type, part_str);
9a799d71 7690
e8e26350 7691 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7692 e_dev_warn("PCI-Express bandwidth available for this card is "
7693 "not sufficient for optimal performance.\n");
7694 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7695 "is required.\n");
0c254d86
AK		 7696 }
7697
34b0368c
PWJ		 7698 /* save off EEPROM version number */
7699 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7700
9a799d71 7701 /* reset the hardware with the new settings */
794caeb2 7702 err = hw->mac.ops.start_hw(hw);
c44ade9e 7703
794caeb2
PWJ		 7704 if (err == IXGBE_ERR_EEPROM_VERSION) {
7705 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7706 e_dev_warn("This device is a pre-production adapter/LOM. "
7707 "Please be aware there may be issues associated "
7708 "with your hardware. If you are experiencing "
7709 "problems please contact your Intel or hardware "
7710 "representative who provided you with this "
7711 "hardware.\n");
794caeb2 7712 }
9a799d71
AK		 7713 strcpy(netdev->name, "eth%d");
7714 err = register_netdev(netdev);
7715 if (err)
7716 goto err_register;
7717
54386467
JB		 7718 /* carrier off reporting is important to ethtool even BEFORE open */
7719 netif_carrier_off(netdev);
7720
5dd2d332 7721#ifdef CONFIG_IXGBE_DCA
652f093f 7722 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7723 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7724 ixgbe_setup_dca(adapter);
7725 }
7726#endif
1cdd1ec8 7727 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7728 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7729 for (i = 0; i < adapter->num_vfs; i++)
7730 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7731 }
7732
0365e6e4
PW		 7733 /* add san mac addr to netdev */
7734 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7735
849c4542 7736 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7737 cards_found++;
7738 return 0;
7739
7740err_register:
5eba3699 7741 ixgbe_release_hw_control(adapter);
7a921c93 7742 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7743err_sw_init:
7744err_eeprom:
1cdd1ec8
GR		 7745 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7746 ixgbe_disable_sriov(adapter);
7086400d 7747 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7748 iounmap(hw->hw_addr);
7749err_ioremap:
7750 free_netdev(netdev);
7751err_alloc_etherdev:
e8e9f696
JP		 7752 pci_release_selected_regions(pdev,
7753 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7754err_pci_reg:
7755err_dma:
7756 pci_disable_device(pdev);
7757 return err;
7758}
7759
7760/**
7761 * ixgbe_remove - Device Removal Routine
7762 * @pdev: PCI device information struct
7763 *
7764 * ixgbe_remove is called by the PCI subsystem to alert the driver
7765 * that it should release a PCI device. The could be caused by a
7766 * Hot-Plug event, or because the driver is going to be removed from
7767 * memory.
7768 **/
7769static void __devexit ixgbe_remove(struct pci_dev *pdev)
7770{
c60fbb00
AD		 7771 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7772 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7773
7774 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7775 cancel_work_sync(&adapter->service_task);
9a799d71 7776
5dd2d332 7777#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7778 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7779 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7780 dca_remove_requester(&pdev->dev);
7781 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7782 }
7783
7784#endif
332d4a7d
YZ		 7785#ifdef IXGBE_FCOE
7786 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7787 ixgbe_cleanup_fcoe(adapter);
7788
7789#endif /* IXGBE_FCOE */
0365e6e4
PW		 7790
7791 /* remove the added san mac */
7792 ixgbe_del_sanmac_netdev(netdev);
7793
c4900be0
DS		 7794 if (netdev->reg_state == NETREG_REGISTERED)
7795 unregister_netdev(netdev);
9a799d71 7796
1cdd1ec8
GR		 7797 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7798 ixgbe_disable_sriov(adapter);
7799
7a921c93 7800 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7801
021230d4 7802 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7803
7804 iounmap(adapter->hw.hw_addr);
9ce77666 7805 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7806 IORESOURCE_MEM));
9a799d71 7807
849c4542 7808 e_dev_info("complete\n");
021230d4 7809
9a799d71
AK		 7810 free_netdev(netdev);
7811
19d5afd4 7812 pci_disable_pcie_error_reporting(pdev);
6fabd715 7813
9a799d71
AK		 7814 pci_disable_device(pdev);
7815}
7816
7817/**
7818 * ixgbe_io_error_detected - called when PCI error is detected
7819 * @pdev: Pointer to PCI device
7820 * @state: The current pci connection state
7821 *
7822 * This function is called after a PCI bus error affecting
7823 * this device has been detected.
7824 */
7825static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7826 pci_channel_state_t state)
9a799d71 7827{
c60fbb00
AD		 7828 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7829 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7830
7831 netif_device_detach(netdev);
7832
3044b8d1
BL		 7833 if (state == pci_channel_io_perm_failure)
7834 return PCI_ERS_RESULT_DISCONNECT;
7835
9a799d71
AK		 7836 if (netif_running(netdev))
7837 ixgbe_down(adapter);
7838 pci_disable_device(pdev);
7839
b4617240 7840 /* Request a slot reset. */
9a799d71
AK		 7841 return PCI_ERS_RESULT_NEED_RESET;
7842}
7843
7844/**
7845 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7846 * @pdev: Pointer to PCI device
7847 *
7848 * Restart the card from scratch, as if from a cold-boot.
7849 */
7850static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7851{
c60fbb00 7852 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7853 pci_ers_result_t result;
7854 int err;
9a799d71 7855
9ce77666 7856 if (pci_enable_device_mem(pdev)) {
396e799c 7857 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7858 result = PCI_ERS_RESULT_DISCONNECT;
7859 } else {
7860 pci_set_master(pdev);
7861 pci_restore_state(pdev);
c0e1f68b 7862 pci_save_state(pdev);
9a799d71 7863
dd4d8ca6 7864 pci_wake_from_d3(pdev, false);
9a799d71 7865
6fabd715 7866 ixgbe_reset(adapter);
88512539 7867 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7868 result = PCI_ERS_RESULT_RECOVERED;
7869 }
7870
7871 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7872 if (err) {
849c4542
ET		 7873 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7874 "failed 0x%0x\n", err);
6fabd715
PWJ		 7875 /* non-fatal, continue */
7876 }
9a799d71 7877
6fabd715 7878 return result;
9a799d71
AK		 7879}
7880
7881/**
7882 * ixgbe_io_resume - called when traffic can start flowing again.
7883 * @pdev: Pointer to PCI device
7884 *
7885 * This callback is called when the error recovery driver tells us that
7886 * its OK to resume normal operation.
7887 */
7888static void ixgbe_io_resume(struct pci_dev *pdev)
7889{
c60fbb00
AD		 7890 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7891 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7892
7893 if (netif_running(netdev)) {
7894 if (ixgbe_up(adapter)) {
396e799c 7895 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7896 return;
7897 }
7898 }
7899
7900 netif_device_attach(netdev);
9a799d71
AK		 7901}
7902
7903static struct pci_error_handlers ixgbe_err_handler = {
7904 .error_detected = ixgbe_io_error_detected,
7905 .slot_reset = ixgbe_io_slot_reset,
7906 .resume = ixgbe_io_resume,
7907};
7908
7909static struct pci_driver ixgbe_driver = {
7910 .name = ixgbe_driver_name,
7911 .id_table = ixgbe_pci_tbl,
7912 .probe = ixgbe_probe,
7913 .remove = __devexit_p(ixgbe_remove),
7914#ifdef CONFIG_PM
7915 .suspend = ixgbe_suspend,
7916 .resume = ixgbe_resume,
7917#endif
7918 .shutdown = ixgbe_shutdown,
7919 .err_handler = &ixgbe_err_handler
7920};
7921
7922/**
7923 * ixgbe_init_module - Driver Registration Routine
7924 *
7925 * ixgbe_init_module is the first routine called when the driver is
7926 * loaded. All it does is register with the PCI subsystem.
7927 **/
7928static int __init ixgbe_init_module(void)
7929{
7930 int ret;
c7689578 7931 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7932 pr_info("%s\n", ixgbe_copyright);
9a799d71 7933
5dd2d332 7934#ifdef CONFIG_IXGBE_DCA
bd0362dd 7935 dca_register_notify(&dca_notifier);
bd0362dd 7936#endif
5dd2d332 7937
9a799d71
AK		 7938 ret = pci_register_driver(&ixgbe_driver);
7939 return ret;
7940}
b4617240 7941
9a799d71
AK		 7942module_init(ixgbe_init_module);
7943
7944/**
7945 * ixgbe_exit_module - Driver Exit Cleanup Routine
7946 *
7947 * ixgbe_exit_module is called just before the driver is removed
7948 * from memory.
7949 **/
7950static void __exit ixgbe_exit_module(void)
7951{
5dd2d332 7952#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7953 dca_unregister_notify(&dca_notifier);
7954#endif
9a799d71 7955 pci_unregister_driver(&ixgbe_driver);
1a51502b 7956 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7957}
bd0362dd 7958
5dd2d332 7959#ifdef CONFIG_IXGBE_DCA
bd0362dd 7960static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7961 void *p)
bd0362dd
JC		 7962{
7963 int ret_val;
7964
7965 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7966 __ixgbe_notify_dca);
bd0362dd
JC		 7967
7968 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7969}
b453368d 7970
5dd2d332 7971#endif /* CONFIG_IXGBE_DCA */
849c4542 7972
9a799d71
AK		 7973module_exit(ixgbe_exit_module);
7974
7975/* ixgbe_main.c */
Linux kernel - Deliverables
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