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ixgbe: correctly add and remove napi queues
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
b4617240 4 Copyright(c) 1999 - 2008 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42
43#include "ixgbe.h"
44#include "ixgbe_common.h"
45
46char ixgbe_driver_name[] = "ixgbe";
9c8eb720 47static const char ixgbe_driver_string[] =
b4617240 48 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 49
51ac6445 50#define DRV_VERSION "1.3.30-k2"
9c8eb720 51const char ixgbe_driver_version[] = DRV_VERSION;
b4617240 52static char ixgbe_copyright[] = "Copyright (c) 1999-2007 Intel Corporation.";
9a799d71
AK		 53
54static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 55 [board_82598] = &ixgbe_82598_info,
9a799d71
AK		 56};
57
58/* ixgbe_pci_tbl - PCI Device ID Table
59 *
60 * Wildcard entries (PCI_ANY_ID) should come last
61 * Last entry must be all 0s
62 *
63 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
64 * Class, Class Mask, private data (not used) }
65 */
66static struct pci_device_id ixgbe_pci_tbl[] = {
67 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 68 board_82598 },
9a799d71 69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 70 board_82598 },
9a799d71 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 72 board_82598 },
8d792cd9
JB		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
74 board_82598 },
b95f5fcb
JB		 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
76 board_82598 },
9a799d71
AK		 77
78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
82
a1f96ee7 83#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd 84static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 85 void *p);
bd0362dd
JC		 86static struct notifier_block dca_notifier = {
87 .notifier_call = ixgbe_notify_dca,
88 .next = NULL,
89 .priority = 0
90};
91#endif
92
9a799d71
AK		 93MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
94MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
95MODULE_LICENSE("GPL");
96MODULE_VERSION(DRV_VERSION);
97
98#define DEFAULT_DEBUG_LEVEL_SHIFT 3
99
5eba3699
AV		 100static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
101{
102 u32 ctrl_ext;
103
104 /* Let firmware take over control of h/w */
105 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
106 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 107 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 108}
109
110static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
111{
112 u32 ctrl_ext;
113
114 /* Let firmware know the driver has taken over */
115 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
116 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 117 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 118}
9a799d71
AK		 119
120#ifdef DEBUG
121/**
122 * ixgbe_get_hw_dev_name - return device name string
123 * used by hardware layer to print debugging information
124 **/
125char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
126{
127 struct ixgbe_adapter *adapter = hw->back;
128 struct net_device *netdev = adapter->netdev;
129 return netdev->name;
130}
131#endif
132
133static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
b4617240 134 u8 msix_vector)
9a799d71
AK		 135{
136 u32 ivar, index;
137
138 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
139 index = (int_alloc_entry >> 2) & 0x1F;
140 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
141 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
142 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
143 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
144}
145
146static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 147 struct ixgbe_tx_buffer
148 *tx_buffer_info)
9a799d71
AK		 149{
150 if (tx_buffer_info->dma) {
e01c31a5 151 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
b4617240 152 tx_buffer_info->length, PCI_DMA_TODEVICE);
9a799d71
AK		 153 tx_buffer_info->dma = 0;
154 }
155 if (tx_buffer_info->skb) {
156 dev_kfree_skb_any(tx_buffer_info->skb);
157 tx_buffer_info->skb = NULL;
158 }
159 /* tx_buffer_info must be completely set up in the transmit path */
160}
161
162static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 163 struct ixgbe_ring *tx_ring,
164 unsigned int eop)
9a799d71 165{
e01c31a5
JB		 166 struct ixgbe_hw *hw = &adapter->hw;
167 u32 head, tail;
168
9a799d71 169 /* Detect a transmit hang in hardware, this serializes the
e01c31a5
JB		 170 * check with the clearing of time_stamp and movement of eop */
171 head = IXGBE_READ_REG(hw, tx_ring->head);
172 tail = IXGBE_READ_REG(hw, tx_ring->tail);
9a799d71 173 adapter->detect_tx_hung = false;
e01c31a5
JB		 174 if ((head != tail) &&
175 tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 176 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
177 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
178 /* detected Tx unit hang */
e01c31a5
JB		 179 union ixgbe_adv_tx_desc *tx_desc;
180 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 181 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 182 " Tx Queue <%d>\n"
183 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 184 " next_to_use <%x>\n"
185 " next_to_clean <%x>\n"
186 "tx_buffer_info[next_to_clean]\n"
187 " time_stamp <%lx>\n"
e01c31a5
JB		 188 " jiffies <%lx>\n",
189 tx_ring->queue_index,
190 head, tail,
191 tx_ring->next_to_use, eop,
192 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 193 return true;
194 }
195
196 return false;
197}
198
b4617240
PW		 199#define IXGBE_MAX_TXD_PWR 14
200#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 201
202/* Tx Descriptors needed, worst case */
203#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
204 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
205#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 206 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 207
e01c31a5
JB		 208#define GET_TX_HEAD_FROM_RING(ring) (\
209 *(volatile u32 *) \
210 ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count))
211static void ixgbe_tx_timeout(struct net_device *netdev);
212
9a799d71
AK		 213/**
214 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
215 * @adapter: board private structure
e01c31a5 216 * @tx_ring: tx ring to clean
9a799d71
AK		 217 **/
218static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 219 struct ixgbe_ring *tx_ring)
9a799d71 220{
e01c31a5 221 union ixgbe_adv_tx_desc *tx_desc;
9a799d71 222 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5
JB		 223 struct net_device *netdev = adapter->netdev;
224 struct sk_buff *skb;
225 unsigned int i;
226 u32 head, oldhead;
227 unsigned int count = 0;
228 unsigned int total_bytes = 0, total_packets = 0;
9a799d71 229
e01c31a5
JB		 230 rmb();
231 head = GET_TX_HEAD_FROM_RING(tx_ring);
232 head = le32_to_cpu(head);
9a799d71 233 i = tx_ring->next_to_clean;
e01c31a5
JB		 234 while (1) {
235 while (i != head) {
9a799d71
AK		 236 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
237 tx_buffer_info = &tx_ring->tx_buffer_info[i];
e01c31a5 238 skb = tx_buffer_info->skb;
9a799d71 239
e01c31a5 240 if (skb) {
e092be60 241 unsigned int segs, bytecount;
e01c31a5
JB		 242
243 /* gso_segs is currently only valid for tcp */
e092be60
AV		 244 segs = skb_shinfo(skb)->gso_segs ?: 1;
245 /* multiply data chunks by size of headers */
246 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 247 skb->len;
248 total_packets += segs;
249 total_bytes += bytecount;
e092be60 250 }
e01c31a5 251
9a799d71 252 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 253 tx_buffer_info);
9a799d71
AK		 254
255 i++;
256 if (i == tx_ring->count)
257 i = 0;
9a799d71 258
e01c31a5
JB		 259 count++;
260 if (count == tx_ring->count)
261 goto done_cleaning;
262 }
263 oldhead = head;
264 rmb();
265 head = GET_TX_HEAD_FROM_RING(tx_ring);
266 head = le32_to_cpu(head);
267 if (head == oldhead)
268 goto done_cleaning;
269 } /* while (1) */
270
271done_cleaning:
9a799d71
AK		 272 tx_ring->next_to_clean = i;
273
e092be60 274#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 275 if (unlikely(count && netif_carrier_ok(netdev) &&
276 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 277 /* Make sure that anybody stopping the queue after this
278 * sees the new next_to_clean.
279 */
280 smp_mb();
30eba97a
AV		 281 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
282 !test_bit(__IXGBE_DOWN, &adapter->state)) {
283 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 284 ++adapter->restart_queue;
30eba97a 285 }
e092be60 286 }
9a799d71 287
e01c31a5
JB		 288 if (adapter->detect_tx_hung) {
289 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
290 /* schedule immediate reset if we believe we hung */
291 DPRINTK(PROBE, INFO,
292 "tx hang %d detected, resetting adapter\n",
293 adapter->tx_timeout_count + 1);
294 ixgbe_tx_timeout(adapter->netdev);
295 }
296 }
9a799d71 297
e01c31a5
JB		 298 /* re-arm the interrupt */
299 if ((total_packets >= tx_ring->work_limit) ||
300 (count == tx_ring->count))
301 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
9a799d71 302
e01c31a5
JB		 303 tx_ring->total_bytes += total_bytes;
304 tx_ring->total_packets += total_packets;
305 tx_ring->stats.bytes += total_bytes;
306 tx_ring->stats.packets += total_packets;
307 adapter->net_stats.tx_bytes += total_bytes;
308 adapter->net_stats.tx_packets += total_packets;
309 return (total_packets ? true : false);
9a799d71
AK		 310}
311
a1f96ee7 312#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd 313static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 314 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 315{
316 u32 rxctrl;
317 int cpu = get_cpu();
3a581073 318 int q = rx_ring - adapter->rx_ring;
bd0362dd 319
3a581073 320 if (rx_ring->cpu != cpu) {
bd0362dd
JC		 321 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
322 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
96b0e0f6 323 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 324 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
325 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
326 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 327 rx_ring->cpu = cpu;
bd0362dd
JC		 328 }
329 put_cpu();
330}
331
332static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 333 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 334{
335 u32 txctrl;
336 int cpu = get_cpu();
3a581073 337 int q = tx_ring - adapter->tx_ring;
bd0362dd 338
3a581073 339 if (tx_ring->cpu != cpu) {
bd0362dd
JC		 340 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
341 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
96b0e0f6 342 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 343 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
344 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 345 tx_ring->cpu = cpu;
bd0362dd
JC		 346 }
347 put_cpu();
348}
349
350static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
351{
352 int i;
353
354 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
355 return;
356
357 for (i = 0; i < adapter->num_tx_queues; i++) {
358 adapter->tx_ring[i].cpu = -1;
359 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
360 }
361 for (i = 0; i < adapter->num_rx_queues; i++) {
362 adapter->rx_ring[i].cpu = -1;
363 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
364 }
365}
366
367static int __ixgbe_notify_dca(struct device *dev, void *data)
368{
369 struct net_device *netdev = dev_get_drvdata(dev);
370 struct ixgbe_adapter *adapter = netdev_priv(netdev);
371 unsigned long event = *(unsigned long *)data;
372
373 switch (event) {
374 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 375 /* if we're already enabled, don't do it again */
376 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
377 break;
bd0362dd
JC		 378 /* Always use CB2 mode, difference is masked
379 * in the CB driver. */
380 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 381 if (dca_add_requester(dev) == 0) {
96b0e0f6 382 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 383 ixgbe_setup_dca(adapter);
384 break;
385 }
386 /* Fall Through since DCA is disabled. */
387 case DCA_PROVIDER_REMOVE:
388 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
389 dca_remove_requester(dev);
390 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
392 }
393 break;
394 }
395
652f093f 396 return 0;
bd0362dd
JC		 397}
398
96b0e0f6 399#endif /* CONFIG_DCA or CONFIG_DCA_MODULE */
9a799d71
AK		 400/**
401 * ixgbe_receive_skb - Send a completed packet up the stack
402 * @adapter: board private structure
403 * @skb: packet to send up
177db6ff
MC		 404 * @status: hardware indication of status of receive
405 * @rx_ring: rx descriptor ring (for a specific queue) to setup
406 * @rx_desc: rx descriptor
9a799d71
AK		 407 **/
408static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
b4617240
PW		 409 struct sk_buff *skb, u8 status,
410 struct ixgbe_ring *ring,
177db6ff 411 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 412{
177db6ff
MC		 413 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
414 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 415
177db6ff
MC		 416 if (adapter->netdev->features & NETIF_F_LRO &&
417 skb->ip_summed == CHECKSUM_UNNECESSARY) {
9a799d71 418 if (adapter->vlgrp && is_vlan)
177db6ff
MC		 419 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
420 adapter->vlgrp, tag,
421 rx_desc);
9a799d71 422 else
177db6ff
MC		 423 lro_receive_skb(&ring->lro_mgr, skb, rx_desc);
424 ring->lro_used = true;
425 } else {
426 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
427 if (adapter->vlgrp && is_vlan)
428 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
429 else
430 netif_receive_skb(skb);
431 } else {
432 if (adapter->vlgrp && is_vlan)
433 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
434 else
435 netif_rx(skb);
436 }
9a799d71
AK		 437 }
438}
439
e59bd25d
AV		 440/**
441 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
442 * @adapter: address of board private structure
443 * @status_err: hardware indication of status of receive
444 * @skb: skb currently being received and modified
445 **/
9a799d71 446static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 447 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 448{
449 skb->ip_summed = CHECKSUM_NONE;
450
712744be
JB		 451 /* Rx csum disabled */
452 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 453 return;
e59bd25d
AV		 454
455 /* if IP and error */
456 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
457 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 458 adapter->hw_csum_rx_error++;
459 return;
460 }
e59bd25d
AV		 461
462 if (!(status_err & IXGBE_RXD_STAT_L4CS))
463 return;
464
465 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
466 adapter->hw_csum_rx_error++;
467 return;
468 }
469
9a799d71 470 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 471 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 472 adapter->hw_csum_rx_good++;
473}
474
475/**
476 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
477 * @adapter: address of board private structure
478 **/
479static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 480 struct ixgbe_ring *rx_ring,
481 int cleaned_count)
9a799d71 482{
9a799d71
AK		 483 struct pci_dev *pdev = adapter->pdev;
484 union ixgbe_adv_rx_desc *rx_desc;
3a581073 485 struct ixgbe_rx_buffer *bi;
9a799d71 486 unsigned int i;
7c6e0a43 487 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 488
489 i = rx_ring->next_to_use;
3a581073 490 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 491
492 while (cleaned_count--) {
493 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
494
762f4c57 495 if (!bi->page_dma &&
3a581073 496 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 497 if (!bi->page) {
762f4c57
JB		 498 bi->page = alloc_page(GFP_ATOMIC);
499 if (!bi->page) {
500 adapter->alloc_rx_page_failed++;
501 goto no_buffers;
502 }
503 bi->page_offset = 0;
504 } else {
505 /* use a half page if we're re-using */
506 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 507 }
762f4c57
JB		 508
509 bi->page_dma = pci_map_page(pdev, bi->page,
510 bi->page_offset,
511 (PAGE_SIZE / 2),
512 PCI_DMA_FROMDEVICE);
9a799d71
AK		 513 }
514
3a581073 515 if (!bi->skb) {
74ce8dd2
JB		 516 struct sk_buff *skb = netdev_alloc_skb(adapter->netdev,
517 bufsz);
9a799d71
AK		 518
519 if (!skb) {
520 adapter->alloc_rx_buff_failed++;
521 goto no_buffers;
522 }
523
524 /*
525 * Make buffer alignment 2 beyond a 16 byte boundary
526 * this will result in a 16 byte aligned IP header after
527 * the 14 byte MAC header is removed
528 */
529 skb_reserve(skb, NET_IP_ALIGN);
530
3a581073
JB		 531 bi->skb = skb;
532 bi->dma = pci_map_single(pdev, skb->data, bufsz,
533 PCI_DMA_FROMDEVICE);
9a799d71
AK		 534 }
535 /* Refresh the desc even if buffer_addrs didn't change because
536 * each write-back erases this info. */
537 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 538 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
539 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 540 } else {
3a581073 541 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 542 }
543
544 i++;
545 if (i == rx_ring->count)
546 i = 0;
3a581073 547 bi = &rx_ring->rx_buffer_info[i];
9a799d71 548 }
7c6e0a43 549
9a799d71
AK		 550no_buffers:
551 if (rx_ring->next_to_use != i) {
552 rx_ring->next_to_use = i;
553 if (i-- == 0)
554 i = (rx_ring->count - 1);
555
556 /*
557 * Force memory writes to complete before letting h/w
558 * know there are new descriptors to fetch. (Only
559 * applicable for weak-ordered memory model archs,
560 * such as IA-64).
561 */
562 wmb();
563 writel(i, adapter->hw.hw_addr + rx_ring->tail);
564 }
565}
566
7c6e0a43
JB		 567static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
568{
569 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
570}
571
572static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
573{
574 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
575}
576
9a799d71 577static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
b4617240
PW		 578 struct ixgbe_ring *rx_ring,
579 int *work_done, int work_to_do)
9a799d71 580{
9a799d71
AK		 581 struct pci_dev *pdev = adapter->pdev;
582 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
583 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
584 struct sk_buff *skb;
585 unsigned int i;
7c6e0a43 586 u32 len, staterr;
177db6ff
MC		 587 u16 hdr_info;
588 bool cleaned = false;
9a799d71 589 int cleaned_count = 0;
d2f4fbe2 590 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 591
592 i = rx_ring->next_to_clean;
9a799d71
AK		 593 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
594 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
595 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 596
597 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 598 u32 upper_len = 0;
9a799d71
AK		 599 if (*work_done >= work_to_do)
600 break;
601 (*work_done)++;
602
603 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 604 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
605 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 606 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 607 if (hdr_info & IXGBE_RXDADV_SPH)
608 adapter->rx_hdr_split++;
609 if (len > IXGBE_RX_HDR_SIZE)
610 len = IXGBE_RX_HDR_SIZE;
611 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 612 } else {
9a799d71 613 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 614 }
9a799d71
AK		 615
616 cleaned = true;
617 skb = rx_buffer_info->skb;
618 prefetch(skb->data - NET_IP_ALIGN);
619 rx_buffer_info->skb = NULL;
620
621 if (len && !skb_shinfo(skb)->nr_frags) {
622 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 623 rx_ring->rx_buf_len + NET_IP_ALIGN,
624 PCI_DMA_FROMDEVICE);
9a799d71
AK		 625 skb_put(skb, len);
626 }
627
628 if (upper_len) {
629 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 630 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 631 rx_buffer_info->page_dma = 0;
632 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 633 rx_buffer_info->page,
634 rx_buffer_info->page_offset,
635 upper_len);
636
637 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
638 (page_count(rx_buffer_info->page) != 1))
639 rx_buffer_info->page = NULL;
640 else
641 get_page(rx_buffer_info->page);
9a799d71
AK		 642
643 skb->len += upper_len;
644 skb->data_len += upper_len;
645 skb->truesize += upper_len;
646 }
647
648 i++;
649 if (i == rx_ring->count)
650 i = 0;
651 next_buffer = &rx_ring->rx_buffer_info[i];
652
653 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
654 prefetch(next_rxd);
655
656 cleaned_count++;
657 if (staterr & IXGBE_RXD_STAT_EOP) {
658 rx_ring->stats.packets++;
659 rx_ring->stats.bytes += skb->len;
660 } else {
661 rx_buffer_info->skb = next_buffer->skb;
662 rx_buffer_info->dma = next_buffer->dma;
663 next_buffer->skb = skb;
762f4c57 664 next_buffer->dma = 0;
9a799d71
AK		 665 adapter->non_eop_descs++;
666 goto next_desc;
667 }
668
669 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
670 dev_kfree_skb_irq(skb);
671 goto next_desc;
672 }
673
674 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 675
676 /* probably a little skewed due to removing CRC */
677 total_rx_bytes += skb->len;
678 total_rx_packets++;
679
74ce8dd2 680 skb->protocol = eth_type_trans(skb, adapter->netdev);
177db6ff 681 ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc);
74ce8dd2 682 adapter->netdev->last_rx = jiffies;
9a799d71
AK		 683
684next_desc:
685 rx_desc->wb.upper.status_error = 0;
686
687 /* return some buffers to hardware, one at a time is too slow */
688 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
689 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
690 cleaned_count = 0;
691 }
692
693 /* use prefetched values */
694 rx_desc = next_rxd;
695 rx_buffer_info = next_buffer;
696
697 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 698 }
699
700 if (rx_ring->lro_used) {
701 lro_flush_all(&rx_ring->lro_mgr);
702 rx_ring->lro_used = false;
9a799d71
AK		 703 }
704
705 rx_ring->next_to_clean = i;
706 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
707
708 if (cleaned_count)
709 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
710
f494e8fa
AV		 711 rx_ring->total_packets += total_rx_packets;
712 rx_ring->total_bytes += total_rx_bytes;
713 adapter->net_stats.rx_bytes += total_rx_bytes;
714 adapter->net_stats.rx_packets += total_rx_packets;
715
9a799d71
AK		 716 return cleaned;
717}
718
021230d4 719static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 720/**
721 * ixgbe_configure_msix - Configure MSI-X hardware
722 * @adapter: board private structure
723 *
724 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
725 * interrupts.
726 **/
727static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
728{
021230d4
AV		 729 struct ixgbe_q_vector *q_vector;
730 int i, j, q_vectors, v_idx, r_idx;
731 u32 mask;
9a799d71 732
021230d4 733 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 734
021230d4
AV		 735 /* Populate the IVAR table and set the ITR values to the
736 * corresponding register.
737 */
738 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
739 q_vector = &adapter->q_vector[v_idx];
740 /* XXX for_each_bit(...) */
741 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 742 adapter->num_rx_queues);
021230d4
AV		 743
744 for (i = 0; i < q_vector->rxr_count; i++) {
745 j = adapter->rx_ring[r_idx].reg_idx;
746 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
747 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 748 adapter->num_rx_queues,
749 r_idx + 1);
021230d4
AV		 750 }
751 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 752 adapter->num_tx_queues);
021230d4
AV		 753
754 for (i = 0; i < q_vector->txr_count; i++) {
755 j = adapter->tx_ring[r_idx].reg_idx;
756 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
757 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 758 adapter->num_tx_queues,
759 r_idx + 1);
021230d4
AV		 760 }
761
30efa5a3 762 /* if this is a tx only vector halve the interrupt rate */
021230d4 763 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 764 q_vector->eitr = (adapter->eitr_param >> 1);
021230d4 765 else
30efa5a3
JB		 766 /* rx only */
767 q_vector->eitr = adapter->eitr_param;
021230d4
AV		 768
769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 770 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 771 }
772
021230d4
AV		 773 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
775
41fb9248 776 /* set up to autoclear timer, and the vectors */
021230d4 777 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 778 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 779 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 780}
781
f494e8fa
AV		 782enum latency_range {
783 lowest_latency = 0,
784 low_latency = 1,
785 bulk_latency = 2,
786 latency_invalid = 255
787};
788
789/**
790 * ixgbe_update_itr - update the dynamic ITR value based on statistics
791 * @adapter: pointer to adapter
792 * @eitr: eitr setting (ints per sec) to give last timeslice
793 * @itr_setting: current throttle rate in ints/second
794 * @packets: the number of packets during this measurement interval
795 * @bytes: the number of bytes during this measurement interval
796 *
797 * Stores a new ITR value based on packets and byte
798 * counts during the last interrupt. The advantage of per interrupt
799 * computation is faster updates and more accurate ITR for the current
800 * traffic pattern. Constants in this function were computed
801 * based on theoretical maximum wire speed and thresholds were set based
802 * on testing data as well as attempting to minimize response time
803 * while increasing bulk throughput.
804 * this functionality is controlled by the InterruptThrottleRate module
805 * parameter (see ixgbe_param.c)
806 **/
807static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 808 u32 eitr, u8 itr_setting,
809 int packets, int bytes)
f494e8fa
AV		 810{
811 unsigned int retval = itr_setting;
812 u32 timepassed_us;
813 u64 bytes_perint;
814
815 if (packets == 0)
816 goto update_itr_done;
817
818
819 /* simple throttlerate management
820 * 0-20MB/s lowest (100000 ints/s)
821 * 20-100MB/s low (20000 ints/s)
822 * 100-1249MB/s bulk (8000 ints/s)
823 */
824 /* what was last interrupt timeslice? */
825 timepassed_us = 1000000/eitr;
826 bytes_perint = bytes / timepassed_us; /* bytes/usec */
827
828 switch (itr_setting) {
829 case lowest_latency:
830 if (bytes_perint > adapter->eitr_low)
831 retval = low_latency;
832 break;
833 case low_latency:
834 if (bytes_perint > adapter->eitr_high)
835 retval = bulk_latency;
836 else if (bytes_perint <= adapter->eitr_low)
837 retval = lowest_latency;
838 break;
839 case bulk_latency:
840 if (bytes_perint <= adapter->eitr_high)
841 retval = low_latency;
842 break;
843 }
844
845update_itr_done:
846 return retval;
847}
848
849static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
850{
851 struct ixgbe_adapter *adapter = q_vector->adapter;
852 struct ixgbe_hw *hw = &adapter->hw;
853 u32 new_itr;
854 u8 current_itr, ret_itr;
855 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
b4617240 856 sizeof(struct ixgbe_q_vector);
f494e8fa
AV		 857 struct ixgbe_ring *rx_ring, *tx_ring;
858
859 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
860 for (i = 0; i < q_vector->txr_count; i++) {
861 tx_ring = &(adapter->tx_ring[r_idx]);
862 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 863 q_vector->tx_itr,
864 tx_ring->total_packets,
865 tx_ring->total_bytes);
f494e8fa
AV		 866 /* if the result for this queue would decrease interrupt
867 * rate for this vector then use that result */
30efa5a3 868 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 869 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 870 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 871 r_idx + 1);
f494e8fa
AV		 872 }
873
874 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
875 for (i = 0; i < q_vector->rxr_count; i++) {
876 rx_ring = &(adapter->rx_ring[r_idx]);
877 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 878 q_vector->rx_itr,
879 rx_ring->total_packets,
880 rx_ring->total_bytes);
f494e8fa
AV		 881 /* if the result for this queue would decrease interrupt
882 * rate for this vector then use that result */
30efa5a3 883 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 884 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 885 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 886 r_idx + 1);
f494e8fa
AV		 887 }
888
30efa5a3 889 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 890
891 switch (current_itr) {
892 /* counts and packets in update_itr are dependent on these numbers */
893 case lowest_latency:
894 new_itr = 100000;
895 break;
896 case low_latency:
897 new_itr = 20000; /* aka hwitr = ~200 */
898 break;
899 case bulk_latency:
900 default:
901 new_itr = 8000;
902 break;
903 }
904
905 if (new_itr != q_vector->eitr) {
906 u32 itr_reg;
907 /* do an exponential smoothing */
908 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
909 q_vector->eitr = new_itr;
910 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
911 /* must write high and low 16 bits to reset counter */
912 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
b4617240 913 itr_reg);
f494e8fa
AV		 914 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
915 }
916
917 return;
918}
919
cf8280ee
JB		 920
921static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
922{
923 struct ixgbe_hw *hw = &adapter->hw;
924
925 adapter->lsc_int++;
926 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
927 adapter->link_check_timeout = jiffies;
928 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
929 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
930 schedule_work(&adapter->watchdog_task);
931 }
932}
933
9a799d71
AK		 934static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
935{
936 struct net_device *netdev = data;
937 struct ixgbe_adapter *adapter = netdev_priv(netdev);
938 struct ixgbe_hw *hw = &adapter->hw;
939 u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
940
cf8280ee
JB		 941 if (eicr & IXGBE_EICR_LSC)
942 ixgbe_check_lsc(adapter);
d4f80882
AV		 943
944 if (!test_bit(__IXGBE_DOWN, &adapter->state))
945 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 946
947 return IRQ_HANDLED;
948}
949
950static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
951{
021230d4
AV		 952 struct ixgbe_q_vector *q_vector = data;
953 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 954 struct ixgbe_ring *tx_ring;
021230d4
AV		 955 int i, r_idx;
956
957 if (!q_vector->txr_count)
958 return IRQ_HANDLED;
959
960 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
961 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 962 tx_ring = &(adapter->tx_ring[r_idx]);
a1f96ee7 963#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd 964 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 965 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 966#endif
3a581073
JB		 967 tx_ring->total_bytes = 0;
968 tx_ring->total_packets = 0;
969 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 970 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 971 r_idx + 1);
021230d4 972 }
9a799d71 973
9a799d71
AK		 974 return IRQ_HANDLED;
975}
976
021230d4
AV		 977/**
978 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
979 * @irq: unused
980 * @data: pointer to our q_vector struct for this interrupt vector
981 **/
9a799d71
AK		 982static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
983{
021230d4
AV		 984 struct ixgbe_q_vector *q_vector = data;
985 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 986 struct ixgbe_ring *rx_ring;
021230d4 987 int r_idx;
30efa5a3 988 int i;
021230d4
AV		 989
990 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 991 for (i = 0; i < q_vector->rxr_count; i++) {
992 rx_ring = &(adapter->rx_ring[r_idx]);
993 rx_ring->total_bytes = 0;
994 rx_ring->total_packets = 0;
995 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
996 r_idx + 1);
997 }
998
021230d4
AV		 999 if (!q_vector->rxr_count)
1000 return IRQ_HANDLED;
1001
30efa5a3 1002 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1003 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1004 /* disable interrupts on this vector only */
3a581073 1005 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
021230d4
AV		 1006 netif_rx_schedule(adapter->netdev, &q_vector->napi);
1007
1008 return IRQ_HANDLED;
1009}
1010
1011static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1012{
1013 ixgbe_msix_clean_rx(irq, data);
1014 ixgbe_msix_clean_tx(irq, data);
9a799d71 1015
9a799d71
AK		 1016 return IRQ_HANDLED;
1017}
1018
021230d4
AV		 1019/**
1020 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1021 * @napi: napi struct with our devices info in it
1022 * @budget: amount of work driver is allowed to do this pass, in packets
1023 *
f0848276
JB		 1024 * This function is optimized for cleaning one queue only on a single
1025 * q_vector!!!
021230d4 1026 **/
9a799d71
AK		 1027static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1028{
021230d4 1029 struct ixgbe_q_vector *q_vector =
b4617240 1030 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1031 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1032 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1033 int work_done = 0;
021230d4 1034 long r_idx;
9a799d71 1035
021230d4 1036 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1037 rx_ring = &(adapter->rx_ring[r_idx]);
a1f96ee7 1038#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd 1039 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1040 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1041#endif
9a799d71 1042
3a581073 1043 ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
9a799d71 1044
021230d4
AV		 1045 /* If all Rx work done, exit the polling mode */
1046 if (work_done < budget) {
1047 netif_rx_complete(adapter->netdev, napi);
30efa5a3 1048 if (adapter->itr_setting & 3)
f494e8fa 1049 ixgbe_set_itr_msix(q_vector);
9a799d71 1050 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3a581073 1051 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
9a799d71
AK		 1052 }
1053
1054 return work_done;
1055}
1056
f0848276
JB		 1057/**
1058 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1059 * @napi: napi struct with our devices info in it
1060 * @budget: amount of work driver is allowed to do this pass, in packets
1061 *
1062 * This function will clean more than one rx queue associated with a
1063 * q_vector.
1064 **/
1065static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1066{
1067 struct ixgbe_q_vector *q_vector =
1068 container_of(napi, struct ixgbe_q_vector, napi);
1069 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1070 struct ixgbe_ring *rx_ring = NULL;
1071 int work_done = 0, i;
1072 long r_idx;
1073 u16 enable_mask = 0;
1074
1075 /* attempt to distribute budget to each queue fairly, but don't allow
1076 * the budget to go below 1 because we'll exit polling */
1077 budget /= (q_vector->rxr_count ?: 1);
1078 budget = max(budget, 1);
1079 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1080 for (i = 0; i < q_vector->rxr_count; i++) {
1081 rx_ring = &(adapter->rx_ring[r_idx]);
1082#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
1083 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1084 ixgbe_update_rx_dca(adapter, rx_ring);
1085#endif
1086 ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
1087 enable_mask |= rx_ring->v_idx;
1088 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1089 r_idx + 1);
1090 }
1091
1092 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1093 rx_ring = &(adapter->rx_ring[r_idx]);
1094 /* If all Rx work done, exit the polling mode */
7f821875 1095 if (work_done < budget) {
74ce8dd2 1096 netif_rx_complete(adapter->netdev, napi);
f0848276
JB		 1097 if (adapter->itr_setting & 3)
1098 ixgbe_set_itr_msix(q_vector);
1099 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1100 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1101 return 0;
1102 }
1103
1104 return work_done;
1105}
021230d4 1106static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1107 int r_idx)
021230d4
AV		 1108{
1109 a->q_vector[v_idx].adapter = a;
1110 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1111 a->q_vector[v_idx].rxr_count++;
1112 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1113}
1114
1115static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
b4617240 1116 int r_idx)
021230d4
AV		 1117{
1118 a->q_vector[v_idx].adapter = a;
1119 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1120 a->q_vector[v_idx].txr_count++;
1121 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1122}
1123
9a799d71 1124/**
021230d4
AV		 1125 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1126 * @adapter: board private structure to initialize
1127 * @vectors: allotted vector count for descriptor rings
9a799d71 1128 *
021230d4
AV		 1129 * This function maps descriptor rings to the queue-specific vectors
1130 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1131 * one vector per ring/queue, but on a constrained vector budget, we
1132 * group the rings as "efficiently" as possible. You would add new
1133 * mapping configurations in here.
9a799d71 1134 **/
021230d4 1135static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1136 int vectors)
021230d4
AV		 1137{
1138 int v_start = 0;
1139 int rxr_idx = 0, txr_idx = 0;
1140 int rxr_remaining = adapter->num_rx_queues;
1141 int txr_remaining = adapter->num_tx_queues;
1142 int i, j;
1143 int rqpv, tqpv;
1144 int err = 0;
1145
1146 /* No mapping required if MSI-X is disabled. */
1147 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1148 goto out;
9a799d71 1149
021230d4
AV		 1150 /*
1151 * The ideal configuration...
1152 * We have enough vectors to map one per queue.
1153 */
1154 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1155 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1156 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1157
021230d4
AV		 1158 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1159 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1160
9a799d71 1161 goto out;
021230d4 1162 }
9a799d71 1163
021230d4
AV		 1164 /*
1165 * If we don't have enough vectors for a 1-to-1
1166 * mapping, we'll have to group them so there are
1167 * multiple queues per vector.
1168 */
1169 /* Re-adjusting *qpv takes care of the remainder. */
1170 for (i = v_start; i < vectors; i++) {
1171 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1172 for (j = 0; j < rqpv; j++) {
1173 map_vector_to_rxq(adapter, i, rxr_idx);
1174 rxr_idx++;
1175 rxr_remaining--;
1176 }
1177 }
1178 for (i = v_start; i < vectors; i++) {
1179 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1180 for (j = 0; j < tqpv; j++) {
1181 map_vector_to_txq(adapter, i, txr_idx);
1182 txr_idx++;
1183 txr_remaining--;
9a799d71 1184 }
9a799d71
AK		 1185 }
1186
021230d4
AV		 1187out:
1188 return err;
1189}
1190
1191/**
1192 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1193 * @adapter: board private structure
1194 *
1195 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1196 * interrupts from the kernel.
1197 **/
1198static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1199{
1200 struct net_device *netdev = adapter->netdev;
1201 irqreturn_t (*handler)(int, void *);
1202 int i, vector, q_vectors, err;
1203
1204 /* Decrement for Other and TCP Timer vectors */
1205 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1206
1207 /* Map the Tx/Rx rings to the vectors we were allotted. */
1208 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1209 if (err)
1210 goto out;
1211
1212#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1213 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1214 &ixgbe_msix_clean_many)
021230d4
AV		 1215 for (vector = 0; vector < q_vectors; vector++) {
1216 handler = SET_HANDLER(&adapter->q_vector[vector]);
1217 sprintf(adapter->name[vector], "%s:v%d-%s",
b4617240
PW		 1218 netdev->name, vector,
1219 (handler == &ixgbe_msix_clean_rx) ? "Rx" :
1220 ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx"));
021230d4 1221 err = request_irq(adapter->msix_entries[vector].vector,
b4617240
PW		 1222 handler, 0, adapter->name[vector],
1223 &(adapter->q_vector[vector]));
9a799d71
AK		 1224 if (err) {
1225 DPRINTK(PROBE, ERR,
b4617240
PW		 1226 "request_irq failed for MSIX interrupt "
1227 "Error: %d\n", err);
021230d4 1228 goto free_queue_irqs;
9a799d71 1229 }
9a799d71
AK		 1230 }
1231
021230d4
AV		 1232 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1233 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1234 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1235 if (err) {
1236 DPRINTK(PROBE, ERR,
1237 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1238 goto free_queue_irqs;
9a799d71
AK		 1239 }
1240
9a799d71
AK		 1241 return 0;
1242
021230d4
AV		 1243free_queue_irqs:
1244 for (i = vector - 1; i >= 0; i--)
1245 free_irq(adapter->msix_entries[--vector].vector,
b4617240 1246 &(adapter->q_vector[i]));
021230d4
AV		 1247 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1248 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1249 kfree(adapter->msix_entries);
1250 adapter->msix_entries = NULL;
021230d4 1251out:
9a799d71
AK		 1252 return err;
1253}
1254
f494e8fa
AV		 1255static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1256{
1257 struct ixgbe_hw *hw = &adapter->hw;
1258 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1259 u8 current_itr;
1260 u32 new_itr = q_vector->eitr;
1261 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1262 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1263
30efa5a3 1264 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1265 q_vector->tx_itr,
1266 tx_ring->total_packets,
1267 tx_ring->total_bytes);
30efa5a3 1268 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1269 q_vector->rx_itr,
1270 rx_ring->total_packets,
1271 rx_ring->total_bytes);
f494e8fa 1272
30efa5a3 1273 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1274
1275 switch (current_itr) {
1276 /* counts and packets in update_itr are dependent on these numbers */
1277 case lowest_latency:
1278 new_itr = 100000;
1279 break;
1280 case low_latency:
1281 new_itr = 20000; /* aka hwitr = ~200 */
1282 break;
1283 case bulk_latency:
1284 new_itr = 8000;
1285 break;
1286 default:
1287 break;
1288 }
1289
1290 if (new_itr != q_vector->eitr) {
1291 u32 itr_reg;
1292 /* do an exponential smoothing */
1293 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1294 q_vector->eitr = new_itr;
1295 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1296 /* must write high and low 16 bits to reset counter */
1297 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1298 }
1299
1300 return;
1301}
1302
021230d4
AV		 1303static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter);
1304
9a799d71 1305/**
021230d4 1306 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1307 * @irq: interrupt number
1308 * @data: pointer to a network interface device structure
1309 * @pt_regs: CPU registers structure
1310 **/
1311static irqreturn_t ixgbe_intr(int irq, void *data)
1312{
1313 struct net_device *netdev = data;
1314 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1315 struct ixgbe_hw *hw = &adapter->hw;
1316 u32 eicr;
1317
9a799d71 1318
021230d4
AV		 1319 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1320 * therefore no explict interrupt disable is necessary */
1321 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1322 if (!eicr) {
1323 /* shared interrupt alert!
1324 * make sure interrupts are enabled because the read will
1325 * have disabled interrupts due to EIAM */
1326 ixgbe_irq_enable(adapter);
9a799d71 1327 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1328 }
9a799d71 1329
cf8280ee
JB		 1330 if (eicr & IXGBE_EICR_LSC)
1331 ixgbe_check_lsc(adapter);
021230d4
AV		 1332
1333 if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) {
f494e8fa
AV		 1334 adapter->tx_ring[0].total_packets = 0;
1335 adapter->tx_ring[0].total_bytes = 0;
1336 adapter->rx_ring[0].total_packets = 0;
1337 adapter->rx_ring[0].total_bytes = 0;
021230d4
AV		 1338 /* would disable interrupts here but EIAM disabled it */
1339 __netif_rx_schedule(netdev, &adapter->q_vector[0].napi);
9a799d71
AK		 1340 }
1341
1342 return IRQ_HANDLED;
1343}
1344
021230d4
AV		 1345static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1346{
1347 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1348
1349 for (i = 0; i < q_vectors; i++) {
1350 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1351 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1352 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1353 q_vector->rxr_count = 0;
1354 q_vector->txr_count = 0;
1355 }
1356}
1357
9a799d71
AK		 1358/**
1359 * ixgbe_request_irq - initialize interrupts
1360 * @adapter: board private structure
1361 *
1362 * Attempts to configure interrupts using the best available
1363 * capabilities of the hardware and kernel.
1364 **/
021230d4 1365static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1366{
1367 struct net_device *netdev = adapter->netdev;
021230d4 1368 int err;
9a799d71 1369
021230d4
AV		 1370 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1371 err = ixgbe_request_msix_irqs(adapter);
1372 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1373 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1374 netdev->name, netdev);
021230d4
AV		 1375 } else {
1376 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1377 netdev->name, netdev);
9a799d71
AK		 1378 }
1379
9a799d71
AK		 1380 if (err)
1381 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1382
9a799d71
AK		 1383 return err;
1384}
1385
1386static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1387{
1388 struct net_device *netdev = adapter->netdev;
1389
1390 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1391 int i, q_vectors;
9a799d71 1392
021230d4
AV		 1393 q_vectors = adapter->num_msix_vectors;
1394
1395 i = q_vectors - 1;
9a799d71 1396 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1397
021230d4
AV		 1398 i--;
1399 for (; i >= 0; i--) {
1400 free_irq(adapter->msix_entries[i].vector,
b4617240 1401 &(adapter->q_vector[i]));
021230d4
AV		 1402 }
1403
1404 ixgbe_reset_q_vectors(adapter);
1405 } else {
1406 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1407 }
1408}
1409
1410/**
1411 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1412 * @adapter: board private structure
1413 **/
1414static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1415{
9a799d71
AK		 1416 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1417 IXGBE_WRITE_FLUSH(&adapter->hw);
021230d4
AV		 1418 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1419 int i;
1420 for (i = 0; i < adapter->num_msix_vectors; i++)
1421 synchronize_irq(adapter->msix_entries[i].vector);
1422 } else {
1423 synchronize_irq(adapter->pdev->irq);
1424 }
9a799d71
AK		 1425}
1426
1427/**
1428 * ixgbe_irq_enable - Enable default interrupt generation settings
1429 * @adapter: board private structure
1430 **/
1431static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1432{
021230d4
AV		 1433 u32 mask;
1434 mask = IXGBE_EIMS_ENABLE_MASK;
1435 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
d4f80882 1436 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1437}
1438
1439/**
1440 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1441 *
1442 **/
1443static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1444{
9a799d71
AK		 1445 struct ixgbe_hw *hw = &adapter->hw;
1446
021230d4 1447 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1448 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71
AK		 1449
1450 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
021230d4
AV		 1451 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1452
1453 map_vector_to_rxq(adapter, 0, 0);
1454 map_vector_to_txq(adapter, 0, 0);
1455
1456 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1457}
1458
1459/**
3a581073 1460 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1461 * @adapter: board private structure
1462 *
1463 * Configure the Tx unit of the MAC after a reset.
1464 **/
1465static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1466{
e01c31a5 1467 u64 tdba, tdwba;
9a799d71 1468 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1469 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1470
1471 /* Setup the HW Tx Head and Tail descriptor pointers */
1472 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1473 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1474 j = ring->reg_idx;
1475 tdba = ring->dma;
1476 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1477 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
e01c31a5 1478 (tdba & DMA_32BIT_MASK));
021230d4 1479 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
e01c31a5
JB		 1480 tdwba = ring->dma +
1481 (ring->count * sizeof(union ixgbe_adv_tx_desc));
1482 tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE;
1483 IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK);
1484 IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32));
021230d4
AV		 1485 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1486 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1487 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1488 adapter->tx_ring[i].head = IXGBE_TDH(j);
1489 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1490 /* Disable Tx Head Writeback RO bit, since this hoses
1491 * bookkeeping if things aren't delivered in order.
1492 */
e01c31a5 1493 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1494 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1495 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1496 }
9a799d71
AK		 1497}
1498
cc41ac7c
JB		 1499#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1500
1501static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1502{
1503 struct ixgbe_ring *rx_ring;
1504 u32 srrctl;
1505 int queue0;
3be1adfb
AD		 1506 unsigned long mask;
1507
1508 /* program one srrctl register per VMDq index */
1509 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
1510 long shift, len;
1511 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1512 len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8;
1513 shift = find_first_bit(&mask, len);
1514 queue0 = index & mask;
1515 index = (index & mask) >> shift;
1516 /* program one srrctl per RSS queue since RDRXCTL.MVMEN is enabled */
cc41ac7c 1517 } else {
3be1adfb
AD		 1518 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1519 queue0 = index & mask;
1520 index = index & mask;
cc41ac7c 1521 }
3be1adfb 1522
cc41ac7c
JB		 1523 rx_ring = &adapter->rx_ring[queue0];
1524
1525 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1526
1527 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1528 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1529
1530 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1531 srrctl |= IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1532 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1533 srrctl |= ((IXGBE_RX_HDR_SIZE <<
b4617240
PW		 1534 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1535 IXGBE_SRRCTL_BSIZEHDR_MASK);
cc41ac7c
JB		 1536 } else {
1537 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1538
1539 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1540 srrctl |= IXGBE_RXBUFFER_2048 >>
1541 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1542 else
1543 srrctl |= rx_ring->rx_buf_len >>
1544 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1545 }
1546 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1547}
9a799d71 1548
177db6ff
MC		 1549/**
1550 * ixgbe_get_skb_hdr - helper function for LRO header processing
1551 * @skb: pointer to sk_buff to be added to LRO packet
b4617240 1552 * @iphdr: pointer to ip header structure
177db6ff
MC		 1553 * @tcph: pointer to tcp header structure
1554 * @hdr_flags: pointer to header flags
1555 * @priv: private data
1556 **/
1557static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
1558 u64 *hdr_flags, void *priv)
1559{
1560 union ixgbe_adv_rx_desc *rx_desc = priv;
1561
1562 /* Verify that this is a valid IPv4 TCP packet */
e9990a9c
JB		 1563 if (!((ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_IPV4) &&
1564 (ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_TCP)))
177db6ff
MC		 1565 return -1;
1566
1567 /* Set network headers */
1568 skb_reset_network_header(skb);
1569 skb_set_transport_header(skb, ip_hdrlen(skb));
1570 *iphdr = ip_hdr(skb);
1571 *tcph = tcp_hdr(skb);
1572 *hdr_flags = LRO_IPV4 | LRO_TCP;
1573 return 0;
1574}
1575
cc41ac7c 1576#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
b4617240 1577 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
cc41ac7c 1578
9a799d71 1579/**
3a581073 1580 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1581 * @adapter: board private structure
1582 *
1583 * Configure the Rx unit of the MAC after a reset.
1584 **/
1585static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1586{
1587 u64 rdba;
1588 struct ixgbe_hw *hw = &adapter->hw;
1589 struct net_device *netdev = adapter->netdev;
1590 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1591 int i, j;
9a799d71 1592 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1593 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1594 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1595 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1596 u32 fctrl, hlreg0;
9a799d71 1597 u32 pages;
cc41ac7c
JB		 1598 u32 reta = 0, mrqc;
1599 u32 rdrxctl;
7c6e0a43 1600 int rx_buf_len;
9a799d71
AK		 1601
1602 /* Decide whether to use packet split mode or not */
762f4c57 1603 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1604
1605 /* Set the RX buffer length according to the mode */
1606 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1607 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71
AK		 1608 } else {
1609 if (netdev->mtu <= ETH_DATA_LEN)
7c6e0a43 1610 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1611 else
7c6e0a43 1612 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1613 }
1614
1615 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1616 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1617 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
9a799d71
AK		 1618 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1619
1620 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1621 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1622 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1623 else
1624 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1625 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1626
1627 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1628
9a799d71
AK		 1629 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1630 /* disable receives while setting up the descriptors */
1631 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1632 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1633
1634 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1635 * the Base and Length of the Rx Descriptor Ring */
1636 for (i = 0; i < adapter->num_rx_queues; i++) {
1637 rdba = adapter->rx_ring[i].dma;
7c6e0a43
JB		 1638 j = adapter->rx_ring[i].reg_idx;
1639 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1640 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1641 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1642 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1643 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1644 adapter->rx_ring[i].head = IXGBE_RDH(j);
1645 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1646 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
e9990a9c
JB		 1647 /* Intitial LRO Settings */
1648 adapter->rx_ring[i].lro_mgr.max_aggr = IXGBE_MAX_LRO_AGGREGATE;
1649 adapter->rx_ring[i].lro_mgr.max_desc = IXGBE_MAX_LRO_DESCRIPTORS;
1650 adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr;
1651 adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID;
1652 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1653 adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI;
1654 adapter->rx_ring[i].lro_mgr.dev = adapter->netdev;
1655 adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1656 adapter->rx_ring[i].lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
cc41ac7c
JB		 1657
1658 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1659 }
1660
cc41ac7c
JB		 1661 /*
1662 * For VMDq support of different descriptor types or
1663 * buffer sizes through the use of multiple SRRCTL
1664 * registers, RDRXCTL.MVMEN must be set to 1
1665 *
1666 * also, the manual doesn't mention it clearly but DCA hints
1667 * will only use queue 0's tags unless this bit is set. Side
1668 * effects of setting this bit are only that SRRCTL must be
1669 * fully programmed [0..15]
1670 */
1671 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1672 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1673 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1674
177db6ff 1675
021230d4 1676 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1677 /* Fill out redirection table */
021230d4
AV		 1678 for (i = 0, j = 0; i < 128; i++, j++) {
1679 if (j == adapter->ring_feature[RING_F_RSS].indices)
1680 j = 0;
1681 /* reta = 4-byte sliding window of
1682 * 0x00..(indices-1)(indices-1)00..etc. */
1683 reta = (reta << 8) | (j * 0x11);
1684 if ((i & 3) == 3)
1685 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1686 }
1687
1688 /* Fill out hash function seeds */
1689 for (i = 0; i < 10; i++)
7c6e0a43 1690 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71
AK		 1691
1692 mrqc = IXGBE_MRQC_RSSEN
1693 /* Perform hash on these packet types */
7c6e0a43
JB		 1694 | IXGBE_MRQC_RSS_FIELD_IPV4
1695 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1696 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1697 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1698 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1699 | IXGBE_MRQC_RSS_FIELD_IPV6
1700 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1701 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1702 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
9a799d71 1703 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
021230d4 1704 }
9a799d71 1705
021230d4
AV		 1706 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1707
1708 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1709 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1710 /* Disable indicating checksum in descriptor, enables
1711 * RSS hash */
9a799d71 1712 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1713 }
021230d4
AV		 1714 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1715 /* Enable IPv4 payload checksum for UDP fragments
1716 * if PCSD is not set */
1717 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1718 }
1719
1720 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
9a799d71
AK		 1721}
1722
1723static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 1724 struct vlan_group *grp)
9a799d71
AK		 1725{
1726 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1727 u32 ctrl;
1728
d4f80882
AV		 1729 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1730 ixgbe_irq_disable(adapter);
9a799d71
AK		 1731 adapter->vlgrp = grp;
1732
1733 if (grp) {
1734 /* enable VLAN tag insert/strip */
1735 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
746b9f02 1736 ctrl |= IXGBE_VLNCTRL_VME;
9a799d71
AK		 1737 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1738 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1739 }
1740
d4f80882
AV		 1741 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1742 ixgbe_irq_enable(adapter);
9a799d71
AK		 1743}
1744
1745static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1746{
1747 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1748 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 1749
1750 /* add VID to filter table */
c44ade9e 1751 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
9a799d71
AK		 1752}
1753
1754static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1755{
1756 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1757 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 1758
d4f80882
AV		 1759 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1760 ixgbe_irq_disable(adapter);
1761
9a799d71 1762 vlan_group_set_device(adapter->vlgrp, vid, NULL);
d4f80882
AV		 1763
1764 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1765 ixgbe_irq_enable(adapter);
9a799d71
AK		 1766
1767 /* remove VID from filter table */
c44ade9e 1768 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
9a799d71
AK		 1769}
1770
1771static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1772{
1773 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1774
1775 if (adapter->vlgrp) {
1776 u16 vid;
1777 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1778 if (!vlan_group_get_device(adapter->vlgrp, vid))
1779 continue;
1780 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1781 }
1782 }
1783}
1784
2c5645cf
CL		 1785static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1786{
1787 struct dev_mc_list *mc_ptr;
1788 u8 *addr = *mc_addr_ptr;
1789 *vmdq = 0;
1790
1791 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1792 if (mc_ptr->next)
1793 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1794 else
1795 *mc_addr_ptr = NULL;
1796
1797 return addr;
1798}
1799
9a799d71 1800/**
2c5645cf 1801 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 1802 * @netdev: network interface device structure
1803 *
2c5645cf
CL		 1804 * The set_rx_method entry point is called whenever the unicast/multicast
1805 * address list or the network interface flags are updated. This routine is
1806 * responsible for configuring the hardware for proper unicast, multicast and
1807 * promiscuous mode.
9a799d71 1808 **/
2c5645cf 1809static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 1810{
1811 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1812 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 1813 u32 fctrl, vlnctrl;
2c5645cf
CL		 1814 u8 *addr_list = NULL;
1815 int addr_count = 0;
9a799d71
AK		 1816
1817 /* Check for Promiscuous and All Multicast modes */
1818
1819 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 1820 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 1821
1822 if (netdev->flags & IFF_PROMISC) {
2c5645cf 1823 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 1824 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 1825 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 1826 } else {
746b9f02
PM		 1827 if (netdev->flags & IFF_ALLMULTI) {
1828 fctrl |= IXGBE_FCTRL_MPE;
1829 fctrl &= ~IXGBE_FCTRL_UPE;
1830 } else {
1831 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1832 }
3d01625a 1833 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 1834 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 1835 }
1836
1837 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 1838 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 1839
2c5645cf
CL		 1840 /* reprogram secondary unicast list */
1841 addr_count = netdev->uc_count;
1842 if (addr_count)
1843 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 1844 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
1845 ixgbe_addr_list_itr);
9a799d71 1846
2c5645cf
CL		 1847 /* reprogram multicast list */
1848 addr_count = netdev->mc_count;
1849 if (addr_count)
1850 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 1851 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
1852 ixgbe_addr_list_itr);
9a799d71
AK		 1853}
1854
021230d4
AV		 1855static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1856{
1857 int q_idx;
1858 struct ixgbe_q_vector *q_vector;
1859 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1860
1861 /* legacy and MSI only use one vector */
1862 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1863 q_vectors = 1;
1864
1865 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 1866 struct napi_struct *napi;
021230d4
AV		 1867 q_vector = &adapter->q_vector[q_idx];
1868 if (!q_vector->rxr_count)
1869 continue;
f0848276
JB		 1870 napi = &q_vector->napi;
1871 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
1872 (q_vector->rxr_count > 1))
1873 napi->poll = &ixgbe_clean_rxonly_many;
1874
1875 napi_enable(napi);
021230d4
AV		 1876 }
1877}
1878
1879static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1880{
1881 int q_idx;
1882 struct ixgbe_q_vector *q_vector;
1883 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1884
1885 /* legacy and MSI only use one vector */
1886 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1887 q_vectors = 1;
1888
1889 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1890 q_vector = &adapter->q_vector[q_idx];
1891 if (!q_vector->rxr_count)
1892 continue;
1893 napi_disable(&q_vector->napi);
1894 }
1895}
1896
9a799d71
AK		 1897static void ixgbe_configure(struct ixgbe_adapter *adapter)
1898{
1899 struct net_device *netdev = adapter->netdev;
1900 int i;
1901
2c5645cf 1902 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 1903
1904 ixgbe_restore_vlan(adapter);
1905
1906 ixgbe_configure_tx(adapter);
1907 ixgbe_configure_rx(adapter);
1908 for (i = 0; i < adapter->num_rx_queues; i++)
1909 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 1910 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 1911}
1912
1913static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1914{
1915 struct net_device *netdev = adapter->netdev;
9a799d71 1916 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1917 int i, j = 0;
9a799d71 1918 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4
AV		 1919 u32 txdctl, rxdctl, mhadd;
1920 u32 gpie;
9a799d71 1921
5eba3699
AV		 1922 ixgbe_get_hw_control(adapter);
1923
021230d4
AV		 1924 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1925 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 1926 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1927 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 1928 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 1929 } else {
1930 /* MSI only */
021230d4 1931 gpie = 0;
9a799d71 1932 }
021230d4
AV		 1933 /* XXX: to interrupt immediately for EICS writes, enable this */
1934 /* gpie |= IXGBE_GPIE_EIMEN; */
1935 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 1936 }
1937
021230d4
AV		 1938 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1939 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1940 * specifically only auto mask tx and rx interrupts */
1941 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1942 }
9a799d71 1943
021230d4 1944 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 1945 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1946 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1947 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
1948
1949 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
1950 }
1951
1952 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 1953 j = adapter->tx_ring[i].reg_idx;
1954 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 1955 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
1956 txdctl |= (8 << 16);
9a799d71 1957 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 1958 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 1959 }
1960
1961 for (i = 0; i < adapter->num_rx_queues; i++) {
021230d4
AV		 1962 j = adapter->rx_ring[i].reg_idx;
1963 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
1964 /* enable PTHRESH=32 descriptors (half the internal cache)
1965 * and HTHRESH=0 descriptors (to minimize latency on fetch),
1966 * this also removes a pesky rx_no_buffer_count increment */
1967 rxdctl |= 0x0020;
9a799d71 1968 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 1969 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
9a799d71
AK		 1970 }
1971 /* enable all receives */
1972 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1973 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
1974 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
1975
1976 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1977 ixgbe_configure_msix(adapter);
1978 else
1979 ixgbe_configure_msi_and_legacy(adapter);
1980
1981 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 1982 ixgbe_napi_enable_all(adapter);
1983
1984 /* clear any pending interrupts, may auto mask */
1985 IXGBE_READ_REG(hw, IXGBE_EICR);
1986
9a799d71
AK		 1987 ixgbe_irq_enable(adapter);
1988
1989 /* bring the link up in the watchdog, this could race with our first
1990 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 1991 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1992 adapter->link_check_timeout = jiffies;
9a799d71
AK		 1993 mod_timer(&adapter->watchdog_timer, jiffies);
1994 return 0;
1995}
1996
d4f80882
AV		 1997void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
1998{
1999 WARN_ON(in_interrupt());
2000 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2001 msleep(1);
2002 ixgbe_down(adapter);
2003 ixgbe_up(adapter);
2004 clear_bit(__IXGBE_RESETTING, &adapter->state);
2005}
2006
9a799d71
AK		 2007int ixgbe_up(struct ixgbe_adapter *adapter)
2008{
2009 /* hardware has been reset, we need to reload some things */
2010 ixgbe_configure(adapter);
2011
2012 return ixgbe_up_complete(adapter);
2013}
2014
2015void ixgbe_reset(struct ixgbe_adapter *adapter)
2016{
c44ade9e
JB		 2017 struct ixgbe_hw *hw = &adapter->hw;
2018 if (hw->mac.ops.init_hw(hw))
2019 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2020
2021 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2022 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2023
2024}
2025
9a799d71
AK		 2026/**
2027 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2028 * @adapter: board private structure
2029 * @rx_ring: ring to free buffers from
2030 **/
2031static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2032 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2033{
2034 struct pci_dev *pdev = adapter->pdev;
2035 unsigned long size;
2036 unsigned int i;
2037
2038 /* Free all the Rx ring sk_buffs */
2039
2040 for (i = 0; i < rx_ring->count; i++) {
2041 struct ixgbe_rx_buffer *rx_buffer_info;
2042
2043 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2044 if (rx_buffer_info->dma) {
2045 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2046 rx_ring->rx_buf_len,
2047 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2048 rx_buffer_info->dma = 0;
2049 }
2050 if (rx_buffer_info->skb) {
2051 dev_kfree_skb(rx_buffer_info->skb);
2052 rx_buffer_info->skb = NULL;
2053 }
2054 if (!rx_buffer_info->page)
2055 continue;
762f4c57
JB		 2056 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2057 PCI_DMA_FROMDEVICE);
9a799d71 2058 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2059 put_page(rx_buffer_info->page);
2060 rx_buffer_info->page = NULL;
762f4c57 2061 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2062 }
2063
2064 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2065 memset(rx_ring->rx_buffer_info, 0, size);
2066
2067 /* Zero out the descriptor ring */
2068 memset(rx_ring->desc, 0, rx_ring->size);
2069
2070 rx_ring->next_to_clean = 0;
2071 rx_ring->next_to_use = 0;
2072
2073 writel(0, adapter->hw.hw_addr + rx_ring->head);
2074 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2075}
2076
2077/**
2078 * ixgbe_clean_tx_ring - Free Tx Buffers
2079 * @adapter: board private structure
2080 * @tx_ring: ring to be cleaned
2081 **/
2082static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2083 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2084{
2085 struct ixgbe_tx_buffer *tx_buffer_info;
2086 unsigned long size;
2087 unsigned int i;
2088
2089 /* Free all the Tx ring sk_buffs */
2090
2091 for (i = 0; i < tx_ring->count; i++) {
2092 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2093 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2094 }
2095
2096 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2097 memset(tx_ring->tx_buffer_info, 0, size);
2098
2099 /* Zero out the descriptor ring */
2100 memset(tx_ring->desc, 0, tx_ring->size);
2101
2102 tx_ring->next_to_use = 0;
2103 tx_ring->next_to_clean = 0;
2104
2105 writel(0, adapter->hw.hw_addr + tx_ring->head);
2106 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2107}
2108
2109/**
021230d4 2110 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2111 * @adapter: board private structure
2112 **/
021230d4 2113static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2114{
2115 int i;
2116
021230d4
AV		 2117 for (i = 0; i < adapter->num_rx_queues; i++)
2118 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2119}
2120
2121/**
021230d4 2122 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2123 * @adapter: board private structure
2124 **/
021230d4 2125static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2126{
2127 int i;
2128
021230d4
AV		 2129 for (i = 0; i < adapter->num_tx_queues; i++)
2130 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2131}
2132
2133void ixgbe_down(struct ixgbe_adapter *adapter)
2134{
2135 struct net_device *netdev = adapter->netdev;
7f821875 2136 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2137 u32 rxctrl;
7f821875
JB		 2138 u32 txdctl;
2139 int i, j;
9a799d71
AK		 2140
2141 /* signal that we are down to the interrupt handler */
2142 set_bit(__IXGBE_DOWN, &adapter->state);
2143
2144 /* disable receives */
7f821875
JB		 2145 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2146 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2147
2148 netif_tx_disable(netdev);
2149
7f821875 2150 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2151 msleep(10);
2152
7f821875
JB		 2153 netif_tx_stop_all_queues(netdev);
2154
9a799d71
AK		 2155 ixgbe_irq_disable(adapter);
2156
021230d4 2157 ixgbe_napi_disable_all(adapter);
7f821875 2158
9a799d71 2159 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2160 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2161
7f821875
JB		 2162 /* disable transmits in the hardware now that interrupts are off */
2163 for (i = 0; i < adapter->num_tx_queues; i++) {
2164 j = adapter->tx_ring[i].reg_idx;
2165 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2166 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2167 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2168 }
2169
9a799d71 2170 netif_carrier_off(netdev);
9a799d71 2171
a1f96ee7 2172#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
96b0e0f6
JB		 2173 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2174 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2175 dca_remove_requester(&adapter->pdev->dev);
2176 }
2177
2178#endif
6f4a0e45
PL		 2179 if (!pci_channel_offline(adapter->pdev))
2180 ixgbe_reset(adapter);
9a799d71
AK		 2181 ixgbe_clean_all_tx_rings(adapter);
2182 ixgbe_clean_all_rx_rings(adapter);
2183
a1f96ee7 2184#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
96b0e0f6
JB		 2185 /* since we reset the hardware DCA settings were cleared */
2186 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2187 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2188 /* always use CB2 mode, difference is masked
2189 * in the CB driver */
b4617240 2190 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
96b0e0f6
JB		 2191 ixgbe_setup_dca(adapter);
2192 }
2193#endif
9a799d71
AK		 2194}
2195
9a799d71 2196/**
021230d4
AV		 2197 * ixgbe_poll - NAPI Rx polling callback
2198 * @napi: structure for representing this polling device
2199 * @budget: how many packets driver is allowed to clean
2200 *
2201 * This function is used for legacy and MSI, NAPI mode
9a799d71 2202 **/
021230d4 2203static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2204{
021230d4 2205 struct ixgbe_q_vector *q_vector = container_of(napi,
b4617240 2206 struct ixgbe_q_vector, napi);
021230d4 2207 struct ixgbe_adapter *adapter = q_vector->adapter;
74ce8dd2 2208 int tx_cleaned, work_done = 0;
9a799d71 2209
a1f96ee7 2210#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd
JC		 2211 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2212 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2213 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2214 }
2215#endif
2216
d2c7ddd6 2217 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
021230d4 2218 ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget);
9a799d71 2219
d2c7ddd6
DM		 2220 if (tx_cleaned)
2221 work_done = budget;
2222
53e52c72
DM		 2223 /* If budget not fully consumed, exit the polling mode */
2224 if (work_done < budget) {
021230d4 2225 netif_rx_complete(adapter->netdev, napi);
30efa5a3 2226 if (adapter->itr_setting & 3)
f494e8fa 2227 ixgbe_set_itr(adapter);
d4f80882
AV		 2228 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2229 ixgbe_irq_enable(adapter);
9a799d71 2230 }
9a799d71
AK		 2231 return work_done;
2232}
2233
2234/**
2235 * ixgbe_tx_timeout - Respond to a Tx Hang
2236 * @netdev: network interface device structure
2237 **/
2238static void ixgbe_tx_timeout(struct net_device *netdev)
2239{
2240 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2241
2242 /* Do the reset outside of interrupt context */
2243 schedule_work(&adapter->reset_task);
2244}
2245
2246static void ixgbe_reset_task(struct work_struct *work)
2247{
2248 struct ixgbe_adapter *adapter;
2249 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2250
2251 adapter->tx_timeout_count++;
2252
d4f80882 2253 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2254}
2255
b9804972
JB		 2256static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2257{
2258 int nrq = 1, ntq = 1;
2259 int feature_mask = 0, rss_i, rss_m;
2260
2261 /* Number of supported queues */
2262 switch (adapter->hw.mac.type) {
2263 case ixgbe_mac_82598EB:
2264 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2265 rss_m = 0;
2266 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2267
2268 switch (adapter->flags & feature_mask) {
2269 case (IXGBE_FLAG_RSS_ENABLED):
2270 rss_m = 0xF;
2271 nrq = rss_i;
2272 ntq = rss_i;
2273 break;
2274 case 0:
2275 default:
2276 rss_i = 0;
2277 rss_m = 0;
2278 nrq = 1;
2279 ntq = 1;
2280 break;
2281 }
2282
2283 adapter->ring_feature[RING_F_RSS].indices = rss_i;
2284 adapter->ring_feature[RING_F_RSS].mask = rss_m;
2285 break;
2286 default:
2287 nrq = 1;
2288 ntq = 1;
2289 break;
2290 }
2291
2292 adapter->num_rx_queues = nrq;
2293 adapter->num_tx_queues = ntq;
2294}
2295
021230d4 2296static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2297 int vectors)
021230d4
AV		 2298{
2299 int err, vector_threshold;
2300
2301 /* We'll want at least 3 (vector_threshold):
2302 * 1) TxQ[0] Cleanup
2303 * 2) RxQ[0] Cleanup
2304 * 3) Other (Link Status Change, etc.)
2305 * 4) TCP Timer (optional)
2306 */
2307 vector_threshold = MIN_MSIX_COUNT;
2308
2309 /* The more we get, the more we will assign to Tx/Rx Cleanup
2310 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2311 * Right now, we simply care about how many we'll get; we'll
2312 * set them up later while requesting irq's.
2313 */
2314 while (vectors >= vector_threshold) {
2315 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2316 vectors);
021230d4
AV		 2317 if (!err) /* Success in acquiring all requested vectors. */
2318 break;
2319 else if (err < 0)
2320 vectors = 0; /* Nasty failure, quit now */
2321 else /* err == number of vectors we should try again with */
2322 vectors = err;
2323 }
2324
2325 if (vectors < vector_threshold) {
2326 /* Can't allocate enough MSI-X interrupts? Oh well.
2327 * This just means we'll go with either a single MSI
2328 * vector or fall back to legacy interrupts.
2329 */
2330 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2331 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2332 kfree(adapter->msix_entries);
2333 adapter->msix_entries = NULL;
2334 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
b9804972 2335 ixgbe_set_num_queues(adapter);
021230d4
AV		 2336 } else {
2337 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2338 adapter->num_msix_vectors = vectors;
2339 }
2340}
2341
021230d4
AV		 2342/**
2343 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2344 * @adapter: board private structure to initialize
2345 *
2346 * Once we know the feature-set enabled for the device, we'll cache
2347 * the register offset the descriptor ring is assigned to.
2348 **/
2349static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2350{
021230d4
AV		 2351 int feature_mask = 0, rss_i;
2352 int i, txr_idx, rxr_idx;
2353
2354 /* Number of supported queues */
2355 switch (adapter->hw.mac.type) {
2356 case ixgbe_mac_82598EB:
2357 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2358 txr_idx = 0;
2359 rxr_idx = 0;
2360 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2361 switch (adapter->flags & feature_mask) {
2362 case (IXGBE_FLAG_RSS_ENABLED):
2363 for (i = 0; i < adapter->num_rx_queues; i++)
2364 adapter->rx_ring[i].reg_idx = i;
2365 for (i = 0; i < adapter->num_tx_queues; i++)
2366 adapter->tx_ring[i].reg_idx = i;
2367 break;
2368 case 0:
2369 default:
2370 break;
2371 }
2372 break;
2373 default:
2374 break;
2375 }
2376}
2377
9a799d71
AK		 2378/**
2379 * ixgbe_alloc_queues - Allocate memory for all rings
2380 * @adapter: board private structure to initialize
2381 *
2382 * We allocate one ring per queue at run-time since we don't know the
2383 * number of queues at compile-time. The polling_netdev array is
2384 * intended for Multiqueue, but should work fine with a single queue.
2385 **/
2386static int __devinit ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2387{
2388 int i;
2389
2390 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 2391 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 2392 if (!adapter->tx_ring)
021230d4 2393 goto err_tx_ring_allocation;
9a799d71
AK		 2394
2395 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 2396 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 2397 if (!adapter->rx_ring)
2398 goto err_rx_ring_allocation;
9a799d71 2399
021230d4 2400 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 2401 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 2402 adapter->tx_ring[i].queue_index = i;
2403 }
b9804972 2404
9a799d71 2405 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 2406 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 2407 adapter->rx_ring[i].queue_index = i;
2408 }
2409
2410 ixgbe_cache_ring_register(adapter);
2411
2412 return 0;
2413
2414err_rx_ring_allocation:
2415 kfree(adapter->tx_ring);
2416err_tx_ring_allocation:
2417 return -ENOMEM;
2418}
2419
2420/**
2421 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2422 * @adapter: board private structure to initialize
2423 *
2424 * Attempt to configure the interrupts using the best available
2425 * capabilities of the hardware and the kernel.
2426 **/
2427static int __devinit ixgbe_set_interrupt_capability(struct ixgbe_adapter
b4617240 2428 *adapter)
021230d4
AV		 2429{
2430 int err = 0;
2431 int vector, v_budget;
2432
2433 /*
2434 * It's easy to be greedy for MSI-X vectors, but it really
2435 * doesn't do us much good if we have a lot more vectors
2436 * than CPU's. So let's be conservative and only ask for
2437 * (roughly) twice the number of vectors as there are CPU's.
2438 */
2439 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 2440 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 2441
2442 /*
2443 * At the same time, hardware can only support a maximum of
2444 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2445 * we can easily reach upwards of 64 Rx descriptor queues and
2446 * 32 Tx queues. Thus, we cap it off in those rare cases where
2447 * the cpu count also exceeds our vector limit.
2448 */
2449 v_budget = min(v_budget, MAX_MSIX_COUNT);
2450
2451 /* A failure in MSI-X entry allocation isn't fatal, but it does
2452 * mean we disable MSI-X capabilities of the adapter. */
2453 adapter->msix_entries = kcalloc(v_budget,
b4617240 2454 sizeof(struct msix_entry), GFP_KERNEL);
021230d4
AV		 2455 if (!adapter->msix_entries) {
2456 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2457 ixgbe_set_num_queues(adapter);
2458 kfree(adapter->tx_ring);
2459 kfree(adapter->rx_ring);
2460 err = ixgbe_alloc_queues(adapter);
2461 if (err) {
2462 DPRINTK(PROBE, ERR, "Unable to allocate memory "
b4617240 2463 "for queues\n");
021230d4
AV		 2464 goto out;
2465 }
2466
2467 goto try_msi;
2468 }
2469
2470 for (vector = 0; vector < v_budget; vector++)
2471 adapter->msix_entries[vector].entry = vector;
2472
2473 ixgbe_acquire_msix_vectors(adapter, v_budget);
2474
2475 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2476 goto out;
2477
2478try_msi:
2479 err = pci_enable_msi(adapter->pdev);
2480 if (!err) {
2481 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2482 } else {
2483 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 2484 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 2485 /* reset err */
2486 err = 0;
2487 }
2488
2489out:
30eba97a 2490 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 2491 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
021230d4
AV		 2492
2493 return err;
2494}
2495
2496static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2497{
2498 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2499 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2500 pci_disable_msix(adapter->pdev);
2501 kfree(adapter->msix_entries);
2502 adapter->msix_entries = NULL;
2503 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2504 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2505 pci_disable_msi(adapter->pdev);
2506 }
2507 return;
2508}
2509
2510/**
2511 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2512 * @adapter: board private structure to initialize
2513 *
2514 * We determine which interrupt scheme to use based on...
2515 * - Kernel support (MSI, MSI-X)
2516 * - which can be user-defined (via MODULE_PARAM)
2517 * - Hardware queue count (num_*_queues)
2518 * - defined by miscellaneous hardware support/features (RSS, etc.)
2519 **/
2520static int __devinit ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2521{
2522 int err;
2523
2524 /* Number of supported queues */
2525 ixgbe_set_num_queues(adapter);
2526
2527 err = ixgbe_alloc_queues(adapter);
2528 if (err) {
2529 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2530 goto err_alloc_queues;
2531 }
2532
2533 err = ixgbe_set_interrupt_capability(adapter);
2534 if (err) {
2535 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2536 goto err_set_interrupt;
9a799d71
AK		 2537 }
2538
021230d4 2539 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 2540 "Tx Queue count = %u\n",
2541 (adapter->num_rx_queues > 1) ? "Enabled" :
2542 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 2543
2544 set_bit(__IXGBE_DOWN, &adapter->state);
2545
9a799d71 2546 return 0;
021230d4
AV		 2547
2548err_set_interrupt:
2549 kfree(adapter->tx_ring);
2550 kfree(adapter->rx_ring);
2551err_alloc_queues:
2552 return err;
9a799d71
AK		 2553}
2554
2555/**
2556 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2557 * @adapter: board private structure to initialize
2558 *
2559 * ixgbe_sw_init initializes the Adapter private data structure.
2560 * Fields are initialized based on PCI device information and
2561 * OS network device settings (MTU size).
2562 **/
2563static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2564{
2565 struct ixgbe_hw *hw = &adapter->hw;
2566 struct pci_dev *pdev = adapter->pdev;
021230d4
AV		 2567 unsigned int rss;
2568
c44ade9e
JB		 2569 /* PCI config space info */
2570
2571 hw->vendor_id = pdev->vendor;
2572 hw->device_id = pdev->device;
2573 hw->revision_id = pdev->revision;
2574 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2575 hw->subsystem_device_id = pdev->subsystem_device;
2576
021230d4
AV		 2577 /* Set capability flags */
2578 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2579 adapter->ring_feature[RING_F_RSS].indices = rss;
2580 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
9a799d71
AK		 2581
2582 /* default flow control settings */
2b9ade93
JB		 2583 hw->fc.original_type = ixgbe_fc_none;
2584 hw->fc.type = ixgbe_fc_none;
2585 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2586 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2587 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2588 hw->fc.send_xon = true;
9a799d71 2589
021230d4 2590 /* select 10G link by default */
9a799d71 2591 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
9a799d71 2592
30efa5a3
JB		 2593 /* enable itr by default in dynamic mode */
2594 adapter->itr_setting = 1;
2595 adapter->eitr_param = 20000;
2596
2597 /* set defaults for eitr in MegaBytes */
2598 adapter->eitr_low = 10;
2599 adapter->eitr_high = 20;
2600
2601 /* set default ring sizes */
2602 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
2603 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
2604
9a799d71 2605 /* initialize eeprom parameters */
c44ade9e 2606 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 2607 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2608 return -EIO;
2609 }
2610
021230d4 2611 /* enable rx csum by default */
9a799d71
AK		 2612 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2613
9a799d71
AK		 2614 set_bit(__IXGBE_DOWN, &adapter->state);
2615
2616 return 0;
2617}
2618
2619/**
2620 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2621 * @adapter: board private structure
3a581073 2622 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2623 *
2624 * Return 0 on success, negative on failure
2625 **/
2626int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 2627 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2628{
2629 struct pci_dev *pdev = adapter->pdev;
2630 int size;
2631
3a581073
JB		 2632 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2633 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 2634 if (!tx_ring->tx_buffer_info)
2635 goto err;
3a581073 2636 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 2637
2638 /* round up to nearest 4K */
e01c31a5
JB		 2639 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) +
2640 sizeof(u32);
3a581073 2641 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 2642
3a581073
JB		 2643 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2644 &tx_ring->dma);
e01c31a5
JB		 2645 if (!tx_ring->desc)
2646 goto err;
9a799d71 2647
3a581073
JB		 2648 tx_ring->next_to_use = 0;
2649 tx_ring->next_to_clean = 0;
2650 tx_ring->work_limit = tx_ring->count;
9a799d71 2651 return 0;
e01c31a5
JB		 2652
2653err:
2654 vfree(tx_ring->tx_buffer_info);
2655 tx_ring->tx_buffer_info = NULL;
2656 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
2657 "descriptor ring\n");
2658 return -ENOMEM;
9a799d71
AK		 2659}
2660
2661/**
2662 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2663 * @adapter: board private structure
3a581073 2664 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2665 *
2666 * Returns 0 on success, negative on failure
2667 **/
2668int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 2669 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2670{
2671 struct pci_dev *pdev = adapter->pdev;
021230d4 2672 int size;
9a799d71 2673
177db6ff 2674 size = sizeof(struct net_lro_desc) * IXGBE_MAX_LRO_DESCRIPTORS;
3a581073
JB		 2675 rx_ring->lro_mgr.lro_arr = vmalloc(size);
2676 if (!rx_ring->lro_mgr.lro_arr)
177db6ff 2677 return -ENOMEM;
3a581073 2678 memset(rx_ring->lro_mgr.lro_arr, 0, size);
177db6ff 2679
3a581073
JB		 2680 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2681 rx_ring->rx_buffer_info = vmalloc(size);
2682 if (!rx_ring->rx_buffer_info) {
9a799d71 2683 DPRINTK(PROBE, ERR,
b4617240 2684 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 2685 goto alloc_failed;
9a799d71 2686 }
3a581073 2687 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 2688
9a799d71 2689 /* Round up to nearest 4K */
3a581073
JB		 2690 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2691 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 2692
3a581073 2693 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 2694
3a581073 2695 if (!rx_ring->desc) {
9a799d71 2696 DPRINTK(PROBE, ERR,
b4617240 2697 "Memory allocation failed for the rx desc ring\n");
3a581073 2698 vfree(rx_ring->rx_buffer_info);
177db6ff 2699 goto alloc_failed;
9a799d71
AK		 2700 }
2701
3a581073
JB		 2702 rx_ring->next_to_clean = 0;
2703 rx_ring->next_to_use = 0;
9a799d71
AK		 2704
2705 return 0;
177db6ff
MC		 2706
2707alloc_failed:
3a581073
JB		 2708 vfree(rx_ring->lro_mgr.lro_arr);
2709 rx_ring->lro_mgr.lro_arr = NULL;
177db6ff 2710 return -ENOMEM;
9a799d71
AK		 2711}
2712
2713/**
2714 * ixgbe_free_tx_resources - Free Tx Resources per Queue
2715 * @adapter: board private structure
2716 * @tx_ring: Tx descriptor ring for a specific queue
2717 *
2718 * Free all transmit software resources
2719 **/
c431f97e
JB		 2720void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
2721 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2722{
2723 struct pci_dev *pdev = adapter->pdev;
2724
2725 ixgbe_clean_tx_ring(adapter, tx_ring);
2726
2727 vfree(tx_ring->tx_buffer_info);
2728 tx_ring->tx_buffer_info = NULL;
2729
2730 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2731
2732 tx_ring->desc = NULL;
2733}
2734
2735/**
2736 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2737 * @adapter: board private structure
2738 *
2739 * Free all transmit software resources
2740 **/
2741static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
2742{
2743 int i;
2744
2745 for (i = 0; i < adapter->num_tx_queues; i++)
2746 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
2747}
2748
2749/**
b4617240 2750 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 2751 * @adapter: board private structure
2752 * @rx_ring: ring to clean the resources from
2753 *
2754 * Free all receive software resources
2755 **/
c431f97e
JB		 2756void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2757 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2758{
2759 struct pci_dev *pdev = adapter->pdev;
2760
177db6ff
MC		 2761 vfree(rx_ring->lro_mgr.lro_arr);
2762 rx_ring->lro_mgr.lro_arr = NULL;
2763
9a799d71
AK		 2764 ixgbe_clean_rx_ring(adapter, rx_ring);
2765
2766 vfree(rx_ring->rx_buffer_info);
2767 rx_ring->rx_buffer_info = NULL;
2768
2769 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2770
2771 rx_ring->desc = NULL;
2772}
2773
2774/**
2775 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
2776 * @adapter: board private structure
2777 *
2778 * Free all receive software resources
2779 **/
2780static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
2781{
2782 int i;
2783
2784 for (i = 0; i < adapter->num_rx_queues; i++)
2785 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
2786}
2787
2788/**
021230d4 2789 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
9a799d71
AK		 2790 * @adapter: board private structure
2791 *
2792 * If this function returns with an error, then it's possible one or
2793 * more of the rings is populated (while the rest are not). It is the
2794 * callers duty to clean those orphaned rings.
2795 *
2796 * Return 0 on success, negative on failure
2797 **/
2798static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2799{
2800 int i, err = 0;
2801
2802 for (i = 0; i < adapter->num_tx_queues; i++) {
2803 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
b4617240
PW		 2804 if (!err)
2805 continue;
2806 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
2807 break;
9a799d71
AK		 2808 }
2809
2810 return err;
2811}
2812
2813/**
021230d4 2814 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
9a799d71
AK		 2815 * @adapter: board private structure
2816 *
2817 * If this function returns with an error, then it's possible one or
2818 * more of the rings is populated (while the rest are not). It is the
2819 * callers duty to clean those orphaned rings.
2820 *
2821 * Return 0 on success, negative on failure
2822 **/
2823
2824static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2825{
2826 int i, err = 0;
2827
2828 for (i = 0; i < adapter->num_rx_queues; i++) {
2829 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
b4617240
PW		 2830 if (!err)
2831 continue;
2832 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
2833 break;
9a799d71
AK		 2834 }
2835
2836 return err;
2837}
2838
2839/**
2840 * ixgbe_change_mtu - Change the Maximum Transfer Unit
2841 * @netdev: network interface device structure
2842 * @new_mtu: new value for maximum frame size
2843 *
2844 * Returns 0 on success, negative on failure
2845 **/
2846static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
2847{
2848 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2849 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2850
42c783c5
JB		 2851 /* MTU < 68 is an error and causes problems on some kernels */
2852 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 2853 return -EINVAL;
2854
021230d4 2855 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 2856 netdev->mtu, new_mtu);
021230d4 2857 /* must set new MTU before calling down or up */
9a799d71
AK		 2858 netdev->mtu = new_mtu;
2859
d4f80882
AV		 2860 if (netif_running(netdev))
2861 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2862
2863 return 0;
2864}
2865
2866/**
2867 * ixgbe_open - Called when a network interface is made active
2868 * @netdev: network interface device structure
2869 *
2870 * Returns 0 on success, negative value on failure
2871 *
2872 * The open entry point is called when a network interface is made
2873 * active by the system (IFF_UP). At this point all resources needed
2874 * for transmit and receive operations are allocated, the interrupt
2875 * handler is registered with the OS, the watchdog timer is started,
2876 * and the stack is notified that the interface is ready.
2877 **/
2878static int ixgbe_open(struct net_device *netdev)
2879{
2880 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2881 int err;
4bebfaa5
AK		 2882
2883 /* disallow open during test */
2884 if (test_bit(__IXGBE_TESTING, &adapter->state))
2885 return -EBUSY;
9a799d71 2886
9a799d71
AK		 2887 /* allocate transmit descriptors */
2888 err = ixgbe_setup_all_tx_resources(adapter);
2889 if (err)
2890 goto err_setup_tx;
2891
9a799d71
AK		 2892 /* allocate receive descriptors */
2893 err = ixgbe_setup_all_rx_resources(adapter);
2894 if (err)
2895 goto err_setup_rx;
2896
2897 ixgbe_configure(adapter);
2898
021230d4 2899 err = ixgbe_request_irq(adapter);
9a799d71
AK		 2900 if (err)
2901 goto err_req_irq;
2902
9a799d71
AK		 2903 err = ixgbe_up_complete(adapter);
2904 if (err)
2905 goto err_up;
2906
d55b53ff
JK		 2907 netif_tx_start_all_queues(netdev);
2908
9a799d71
AK		 2909 return 0;
2910
2911err_up:
5eba3699 2912 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2913 ixgbe_free_irq(adapter);
2914err_req_irq:
2915 ixgbe_free_all_rx_resources(adapter);
2916err_setup_rx:
2917 ixgbe_free_all_tx_resources(adapter);
2918err_setup_tx:
2919 ixgbe_reset(adapter);
2920
2921 return err;
2922}
2923
2924/**
2925 * ixgbe_close - Disables a network interface
2926 * @netdev: network interface device structure
2927 *
2928 * Returns 0, this is not allowed to fail
2929 *
2930 * The close entry point is called when an interface is de-activated
2931 * by the OS. The hardware is still under the drivers control, but
2932 * needs to be disabled. A global MAC reset is issued to stop the
2933 * hardware, and all transmit and receive resources are freed.
2934 **/
2935static int ixgbe_close(struct net_device *netdev)
2936{
2937 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 2938
2939 ixgbe_down(adapter);
2940 ixgbe_free_irq(adapter);
2941
2942 ixgbe_free_all_tx_resources(adapter);
2943 ixgbe_free_all_rx_resources(adapter);
2944
5eba3699 2945 ixgbe_release_hw_control(adapter);
9a799d71
AK		 2946
2947 return 0;
2948}
2949
b3c8b4ba
AD		 2950/**
2951 * ixgbe_napi_add_all - prep napi structs for use
2952 * @adapter: private struct
2953 * helper function to napi_add each possible q_vector->napi
2954 */
2955static void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
2956{
2957 int q_idx, q_vectors;
2958 int (*poll)(struct napi_struct *, int);
2959
2960 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2961 poll = &ixgbe_clean_rxonly;
2962 /* Only enable as many vectors as we have rx queues. */
2963 q_vectors = adapter->num_rx_queues;
2964 } else {
2965 poll = &ixgbe_poll;
2966 /* only one q_vector for legacy modes */
2967 q_vectors = 1;
2968 }
2969
2970 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2971 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
2972 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
2973 }
2974}
2975
2976static void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
2977{
2978 int q_idx;
2979 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2980
2981 /* legacy and MSI only use one vector */
2982 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2983 q_vectors = 1;
2984
2985 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2986 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
2987 if (!q_vector->rxr_count)
2988 continue;
2989 netif_napi_del(&q_vector->napi);
2990 }
2991}
2992
2993#ifdef CONFIG_PM
2994static int ixgbe_resume(struct pci_dev *pdev)
2995{
2996 struct net_device *netdev = pci_get_drvdata(pdev);
2997 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2998 u32 err;
2999
3000 pci_set_power_state(pdev, PCI_D0);
3001 pci_restore_state(pdev);
3002 err = pci_enable_device(pdev);
3003 if (err) {
3004 printk(KERN_ERR "ixgbe: Cannot enable PCI device from " \
3005 "suspend\n");
3006 return err;
3007 }
3008 pci_set_master(pdev);
3009
3010 pci_enable_wake(pdev, PCI_D3hot, 0);
3011 pci_enable_wake(pdev, PCI_D3cold, 0);
3012
3013 err = ixgbe_init_interrupt_scheme(adapter);
3014 if (err) {
3015 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3016 "device\n");
3017 return err;
3018 }
3019
3020 ixgbe_napi_add_all(adapter);
3021 ixgbe_reset(adapter);
3022
3023 if (netif_running(netdev)) {
3024 err = ixgbe_open(adapter->netdev);
3025 if (err)
3026 return err;
3027 }
3028
3029 netif_device_attach(netdev);
3030
3031 return 0;
3032}
3033
3034#endif /* CONFIG_PM */
3035static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3036{
3037 struct net_device *netdev = pci_get_drvdata(pdev);
3038 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3039#ifdef CONFIG_PM
3040 int retval = 0;
3041#endif
3042
3043 netif_device_detach(netdev);
3044
3045 if (netif_running(netdev)) {
3046 ixgbe_down(adapter);
3047 ixgbe_free_irq(adapter);
3048 ixgbe_free_all_tx_resources(adapter);
3049 ixgbe_free_all_rx_resources(adapter);
3050 }
3051 ixgbe_reset_interrupt_capability(adapter);
3052 ixgbe_napi_del_all(adapter);
3053 kfree(adapter->tx_ring);
3054 kfree(adapter->rx_ring);
3055
3056#ifdef CONFIG_PM
3057 retval = pci_save_state(pdev);
3058 if (retval)
3059 return retval;
3060#endif
3061
3062 pci_enable_wake(pdev, PCI_D3hot, 0);
3063 pci_enable_wake(pdev, PCI_D3cold, 0);
3064
3065 ixgbe_release_hw_control(adapter);
3066
3067 pci_disable_device(pdev);
3068
3069 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3070
3071 return 0;
3072}
3073
3074static void ixgbe_shutdown(struct pci_dev *pdev)
3075{
3076 ixgbe_suspend(pdev, PMSG_SUSPEND);
3077}
3078
9a799d71
AK		 3079/**
3080 * ixgbe_update_stats - Update the board statistics counters.
3081 * @adapter: board private structure
3082 **/
3083void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3084{
3085 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 3086 u64 total_mpc = 0;
3087 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71
AK		 3088
3089 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 3090 for (i = 0; i < 8; i++) {
3091 /* for packet buffers not used, the register should read 0 */
3092 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3093 missed_rx += mpc;
3094 adapter->stats.mpc[i] += mpc;
3095 total_mpc += adapter->stats.mpc[i];
3096 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3097 }
3098 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3099 /* work around hardware counting issue */
3100 adapter->stats.gprc -= missed_rx;
3101
3102 /* 82598 hardware only has a 32 bit counter in the high register */
9a799d71 3103 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6f11eef7
AV		 3104 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3105 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
9a799d71
AK		 3106 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3107 adapter->stats.bprc += bprc;
3108 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3109 adapter->stats.mprc -= bprc;
3110 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3111 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3112 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3113 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3114 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3115 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3116 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71
AK		 3117 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3118 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
9a799d71 3119 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6f11eef7
AV		 3120 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3121 adapter->stats.lxontxc += lxon;
3122 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3123 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 3124 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3125 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 3126 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3127 /*
3128 * 82598 errata - tx of flow control packets is included in tx counters
3129 */
3130 xon_off_tot = lxon + lxoff;
3131 adapter->stats.gptc -= xon_off_tot;
3132 adapter->stats.mptc -= xon_off_tot;
3133 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 3134 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3135 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3136 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 3137 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3138 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 3139 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 3140 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3141 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3142 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3143 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3144 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 3145 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3146
3147 /* Fill out the OS statistics structure */
9a799d71
AK		 3148 adapter->net_stats.multicast = adapter->stats.mprc;
3149
3150 /* Rx Errors */
3151 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 3152 adapter->stats.rlec;
9a799d71
AK		 3153 adapter->net_stats.rx_dropped = 0;
3154 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3155 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 3156 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 3157}
3158
3159/**
3160 * ixgbe_watchdog - Timer Call-back
3161 * @data: pointer to adapter cast into an unsigned long
3162 **/
3163static void ixgbe_watchdog(unsigned long data)
3164{
3165 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 3166 struct ixgbe_hw *hw = &adapter->hw;
3167
3168 /* Do the watchdog outside of interrupt context due to the lovely
3169 * delays that some of the newer hardware requires */
3170 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3171 /* Cause software interrupt to ensure rx rings are cleaned */
3172 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3173 u32 eics =
3174 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3175 IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3176 } else {
3177 /* For legacy and MSI interrupts don't set any bits that
3178 * are enabled for EIAM, because this operation would
3179 * set *both* EIMS and EICS for any bit in EIAM */
3180 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3181 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3182 }
3183 /* Reset the timer */
3184 mod_timer(&adapter->watchdog_timer,
3185 round_jiffies(jiffies + 2 * HZ));
3186 }
9a799d71 3187
cf8280ee
JB		 3188 schedule_work(&adapter->watchdog_task);
3189}
3190
3191/**
3192 * ixgbe_watchdog_task - worker thread to bring link up
3193 * @work: pointer to work_struct containing our data
3194 **/
3195static void ixgbe_watchdog_task(struct work_struct *work)
3196{
3197 struct ixgbe_adapter *adapter = container_of(work,
3198 struct ixgbe_adapter,
3199 watchdog_task);
3200 struct net_device *netdev = adapter->netdev;
3201 struct ixgbe_hw *hw = &adapter->hw;
3202 u32 link_speed = adapter->link_speed;
3203 bool link_up = adapter->link_up;
3204
3205 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3206
3207 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3208 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3209 if (link_up ||
3210 time_after(jiffies, (adapter->link_check_timeout +
3211 IXGBE_TRY_LINK_TIMEOUT))) {
3212 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3213 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3214 }
3215 adapter->link_up = link_up;
3216 adapter->link_speed = link_speed;
3217 }
9a799d71
AK		 3218
3219 if (link_up) {
3220 if (!netif_carrier_ok(netdev)) {
cf8280ee
JB		 3221 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3222 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
9a799d71
AK		 3223#define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
3224#define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
3225 DPRINTK(LINK, INFO, "NIC Link is Up %s, "
cf8280ee
JB		 3226 "Flow Control: %s\n",
3227 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3228 "10 Gbps" :
3229 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3230 "1 Gbps" : "unknown speed")),
3231 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
3232 (FLOW_RX ? "RX" :
3233 (FLOW_TX ? "TX" : "None"))));
9a799d71
AK		 3234
3235 netif_carrier_on(netdev);
fd2ea0a7 3236 netif_tx_wake_all_queues(netdev);
9a799d71
AK		 3237 } else {
3238 /* Force detection of hung controller */
3239 adapter->detect_tx_hung = true;
3240 }
3241 } else {
cf8280ee
JB		 3242 adapter->link_up = false;
3243 adapter->link_speed = 0;
9a799d71
AK		 3244 if (netif_carrier_ok(netdev)) {
3245 DPRINTK(LINK, INFO, "NIC Link is Down\n");
3246 netif_carrier_off(netdev);
fd2ea0a7 3247 netif_tx_stop_all_queues(netdev);
9a799d71
AK		 3248 }
3249 }
3250
3251 ixgbe_update_stats(adapter);
cf8280ee 3252 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 3253}
3254
9a799d71 3255static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 3256 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3257 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 3258{
3259 struct ixgbe_adv_tx_context_desc *context_desc;
3260 unsigned int i;
3261 int err;
3262 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 3263 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
3264 u32 mss_l4len_idx, l4len;
9a799d71
AK		 3265
3266 if (skb_is_gso(skb)) {
3267 if (skb_header_cloned(skb)) {
3268 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3269 if (err)
3270 return err;
3271 }
3272 l4len = tcp_hdrlen(skb);
3273 *hdr_len += l4len;
3274
8327d000 3275 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 3276 struct iphdr *iph = ip_hdr(skb);
3277 iph->tot_len = 0;
3278 iph->check = 0;
3279 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 3280 iph->daddr, 0,
3281 IPPROTO_TCP,
3282 0);
9a799d71
AK		 3283 adapter->hw_tso_ctxt++;
3284 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3285 ipv6_hdr(skb)->payload_len = 0;
3286 tcp_hdr(skb)->check =
3287 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 3288 &ipv6_hdr(skb)->daddr,
3289 0, IPPROTO_TCP, 0);
9a799d71
AK		 3290 adapter->hw_tso6_ctxt++;
3291 }
3292
3293 i = tx_ring->next_to_use;
3294
3295 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3296 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3297
3298 /* VLAN MACLEN IPLEN */
3299 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3300 vlan_macip_lens |=
3301 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3302 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 3303 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 3304 *hdr_len += skb_network_offset(skb);
3305 vlan_macip_lens |=
3306 (skb_transport_header(skb) - skb_network_header(skb));
3307 *hdr_len +=
3308 (skb_transport_header(skb) - skb_network_header(skb));
3309 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3310 context_desc->seqnum_seed = 0;
3311
3312 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 3313 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 3314 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 3315
8327d000 3316 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3317 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3318 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3319 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3320
3321 /* MSS L4LEN IDX */
9f8cdf4f 3322 mss_l4len_idx =
9a799d71
AK		 3323 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3324 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 3325 /* use index 1 for TSO */
3326 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 3327 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3328
3329 tx_buffer_info->time_stamp = jiffies;
3330 tx_buffer_info->next_to_watch = i;
3331
3332 i++;
3333 if (i == tx_ring->count)
3334 i = 0;
3335 tx_ring->next_to_use = i;
3336
3337 return true;
3338 }
3339 return false;
3340}
3341
3342static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 3343 struct ixgbe_ring *tx_ring,
3344 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 3345{
3346 struct ixgbe_adv_tx_context_desc *context_desc;
3347 unsigned int i;
3348 struct ixgbe_tx_buffer *tx_buffer_info;
3349 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3350
3351 if (skb->ip_summed == CHECKSUM_PARTIAL ||
3352 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3353 i = tx_ring->next_to_use;
3354 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3355 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3356
3357 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3358 vlan_macip_lens |=
3359 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3360 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 3361 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 3362 if (skb->ip_summed == CHECKSUM_PARTIAL)
3363 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 3364 skb_network_header(skb));
9a799d71
AK		 3365
3366 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3367 context_desc->seqnum_seed = 0;
3368
3369 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 3370 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 3371
3372 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71
AK		 3373 switch (skb->protocol) {
3374 case __constant_htons(ETH_P_IP):
9a799d71 3375 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 3376 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3377 type_tucmd_mlhl |=
b4617240 3378 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 3379 break;
41825d71
AK		 3380 case __constant_htons(ETH_P_IPV6):
3381 /* XXX what about other V6 headers?? */
3382 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3383 type_tucmd_mlhl |=
b4617240 3384 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 3385 break;
41825d71
AK		 3386 default:
3387 if (unlikely(net_ratelimit())) {
3388 DPRINTK(PROBE, WARNING,
3389 "partial checksum but proto=%x!\n",
3390 skb->protocol);
3391 }
3392 break;
3393 }
9a799d71
AK		 3394 }
3395
3396 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 3397 /* use index zero for tx checksum offload */
9a799d71
AK		 3398 context_desc->mss_l4len_idx = 0;
3399
3400 tx_buffer_info->time_stamp = jiffies;
3401 tx_buffer_info->next_to_watch = i;
9f8cdf4f 3402
9a799d71
AK		 3403 adapter->hw_csum_tx_good++;
3404 i++;
3405 if (i == tx_ring->count)
3406 i = 0;
3407 tx_ring->next_to_use = i;
3408
3409 return true;
3410 }
9f8cdf4f 3411
9a799d71
AK		 3412 return false;
3413}
3414
3415static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240
PW		 3416 struct ixgbe_ring *tx_ring,
3417 struct sk_buff *skb, unsigned int first)
9a799d71
AK		 3418{
3419 struct ixgbe_tx_buffer *tx_buffer_info;
3420 unsigned int len = skb->len;
3421 unsigned int offset = 0, size, count = 0, i;
3422 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3423 unsigned int f;
3424
3425 len -= skb->data_len;
3426
3427 i = tx_ring->next_to_use;
3428
3429 while (len) {
3430 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3431 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3432
3433 tx_buffer_info->length = size;
3434 tx_buffer_info->dma = pci_map_single(adapter->pdev,
b4617240
PW		 3435 skb->data + offset,
3436 size, PCI_DMA_TODEVICE);
9a799d71
AK		 3437 tx_buffer_info->time_stamp = jiffies;
3438 tx_buffer_info->next_to_watch = i;
3439
3440 len -= size;
3441 offset += size;
3442 count++;
3443 i++;
3444 if (i == tx_ring->count)
3445 i = 0;
3446 }
3447
3448 for (f = 0; f < nr_frags; f++) {
3449 struct skb_frag_struct *frag;
3450
3451 frag = &skb_shinfo(skb)->frags[f];
3452 len = frag->size;
3453 offset = frag->page_offset;
3454
3455 while (len) {
3456 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3457 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3458
3459 tx_buffer_info->length = size;
3460 tx_buffer_info->dma = pci_map_page(adapter->pdev,
b4617240
PW		 3461 frag->page,
3462 offset,
3463 size,
3464 PCI_DMA_TODEVICE);
9a799d71
AK		 3465 tx_buffer_info->time_stamp = jiffies;
3466 tx_buffer_info->next_to_watch = i;
3467
3468 len -= size;
3469 offset += size;
3470 count++;
3471 i++;
3472 if (i == tx_ring->count)
3473 i = 0;
3474 }
3475 }
3476 if (i == 0)
3477 i = tx_ring->count - 1;
3478 else
3479 i = i - 1;
3480 tx_ring->tx_buffer_info[i].skb = skb;
3481 tx_ring->tx_buffer_info[first].next_to_watch = i;
3482
3483 return count;
3484}
3485
3486static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 3487 struct ixgbe_ring *tx_ring,
3488 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 3489{
3490 union ixgbe_adv_tx_desc *tx_desc = NULL;
3491 struct ixgbe_tx_buffer *tx_buffer_info;
3492 u32 olinfo_status = 0, cmd_type_len = 0;
3493 unsigned int i;
3494 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3495
3496 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3497
3498 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3499
3500 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3501 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3502
3503 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3504 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3505
3506 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 3507 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 3508
4eeae6fd
PW		 3509 /* use index 1 context for tso */
3510 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 3511 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3512 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 3513 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 3514
3515 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3516 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 3517 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 3518
3519 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3520
3521 i = tx_ring->next_to_use;
3522 while (count--) {
3523 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3524 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3525 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3526 tx_desc->read.cmd_type_len =
b4617240 3527 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71
AK		 3528 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3529
3530 i++;
3531 if (i == tx_ring->count)
3532 i = 0;
3533 }
3534
3535 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3536
3537 /*
3538 * Force memory writes to complete before letting h/w
3539 * know there are new descriptors to fetch. (Only
3540 * applicable for weak-ordered memory model archs,
3541 * such as IA-64).
3542 */
3543 wmb();
3544
3545 tx_ring->next_to_use = i;
3546 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3547}
3548
e092be60 3549static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 3550 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 3551{
3552 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3553
30eba97a 3554 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3555 /* Herbert's original patch had:
3556 * smp_mb__after_netif_stop_queue();
3557 * but since that doesn't exist yet, just open code it. */
3558 smp_mb();
3559
3560 /* We need to check again in a case another CPU has just
3561 * made room available. */
3562 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3563 return -EBUSY;
3564
3565 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 3566 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3567 ++adapter->restart_queue;
3568 return 0;
3569}
3570
3571static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 3572 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 3573{
3574 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3575 return 0;
3576 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3577}
3578
3579
9a799d71
AK		 3580static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3581{
3582 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3583 struct ixgbe_ring *tx_ring;
9a799d71
AK		 3584 unsigned int first;
3585 unsigned int tx_flags = 0;
30eba97a
AV		 3586 u8 hdr_len = 0;
3587 int r_idx = 0, tso;
9a799d71
AK		 3588 int count = 0;
3589 unsigned int f;
9f8cdf4f 3590
30eba97a 3591 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
30eba97a 3592 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 3593
9f8cdf4f
JB		 3594 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3595 tx_flags |= vlan_tx_tag_get(skb);
3596 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3597 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 3598 }
9f8cdf4f
JB		 3599 /* three things can cause us to need a context descriptor */
3600 if (skb_is_gso(skb) ||
3601 (skb->ip_summed == CHECKSUM_PARTIAL) ||
3602 (tx_flags & IXGBE_TX_FLAGS_VLAN))
9a799d71
AK		 3603 count++;
3604
9f8cdf4f
JB		 3605 count += TXD_USE_COUNT(skb_headlen(skb));
3606 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 3607 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3608
e092be60 3609 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 3610 adapter->tx_busy++;
9a799d71
AK		 3611 return NETDEV_TX_BUSY;
3612 }
9a799d71 3613
8327d000 3614 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3615 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3616 first = tx_ring->next_to_use;
3617 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3618 if (tso < 0) {
3619 dev_kfree_skb_any(skb);
3620 return NETDEV_TX_OK;
3621 }
3622
3623 if (tso)
3624 tx_flags |= IXGBE_TX_FLAGS_TSO;
3625 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
b4617240 3626 (skb->ip_summed == CHECKSUM_PARTIAL))
9a799d71
AK		 3627 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3628
3629 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
b4617240
PW		 3630 ixgbe_tx_map(adapter, tx_ring, skb, first),
3631 skb->len, hdr_len);
9a799d71
AK		 3632
3633 netdev->trans_start = jiffies;
3634
e092be60 3635 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71
AK		 3636
3637 return NETDEV_TX_OK;
3638}
3639
3640/**
3641 * ixgbe_get_stats - Get System Network Statistics
3642 * @netdev: network interface device structure
3643 *
3644 * Returns the address of the device statistics structure.
3645 * The statistics are actually updated from the timer callback.
3646 **/
3647static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3648{
3649 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3650
3651 /* only return the current stats */
3652 return &adapter->net_stats;
3653}
3654
3655/**
3656 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3657 * @netdev: network interface device structure
3658 * @p: pointer to an address structure
3659 *
3660 * Returns 0 on success, negative on failure
3661 **/
3662static int ixgbe_set_mac(struct net_device *netdev, void *p)
3663{
3664 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 3665 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3666 struct sockaddr *addr = p;
3667
3668 if (!is_valid_ether_addr(addr->sa_data))
3669 return -EADDRNOTAVAIL;
3670
3671 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 3672 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 3673
b4617240 3674 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 3675
3676 return 0;
3677}
3678
3679#ifdef CONFIG_NET_POLL_CONTROLLER
3680/*
3681 * Polling 'interrupt' - used by things like netconsole to send skbs
3682 * without having to re-enable interrupts. It's not called while
3683 * the interrupt routine is executing.
3684 */
3685static void ixgbe_netpoll(struct net_device *netdev)
3686{
3687 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3688
3689 disable_irq(adapter->pdev->irq);
3690 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3691 ixgbe_intr(adapter->pdev->irq, netdev);
3692 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3693 enable_irq(adapter->pdev->irq);
3694}
3695#endif
3696
c44ade9e
JB		 3697/**
3698 * ixgbe_link_config - set up initial link with default speed and duplex
3699 * @hw: pointer to private hardware struct
3700 *
3701 * Returns 0 on success, negative on failure
3702 **/
3703static int ixgbe_link_config(struct ixgbe_hw *hw)
3704{
3705 u32 autoneg = IXGBE_LINK_SPEED_10GB_FULL;
3706
3707 /* must always autoneg for both 1G and 10G link */
3708 hw->mac.autoneg = true;
3709
3710 return hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3711}
3712
9a799d71
AK		 3713/**
3714 * ixgbe_probe - Device Initialization Routine
3715 * @pdev: PCI device information struct
3716 * @ent: entry in ixgbe_pci_tbl
3717 *
3718 * Returns 0 on success, negative on failure
3719 *
3720 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3721 * The OS initialization, configuring of the adapter private structure,
3722 * and a hardware reset occur.
3723 **/
3724static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 3725 const struct pci_device_id *ent)
9a799d71
AK		 3726{
3727 struct net_device *netdev;
3728 struct ixgbe_adapter *adapter = NULL;
3729 struct ixgbe_hw *hw;
3730 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 3731 static int cards_found;
3732 int i, err, pci_using_dac;
3733 u16 link_status, link_speed, link_width;
c44ade9e 3734 u32 part_num, eec;
9a799d71
AK		 3735
3736 err = pci_enable_device(pdev);
3737 if (err)
3738 return err;
3739
3740 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3741 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3742 pci_using_dac = 1;
3743 } else {
3744 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3745 if (err) {
3746 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3747 if (err) {
b4617240
PW		 3748 dev_err(&pdev->dev, "No usable DMA "
3749 "configuration, aborting\n");
9a799d71
AK		 3750 goto err_dma;
3751 }
3752 }
3753 pci_using_dac = 0;
3754 }
3755
3756 err = pci_request_regions(pdev, ixgbe_driver_name);
3757 if (err) {
3758 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3759 goto err_pci_reg;
3760 }
3761
3762 pci_set_master(pdev);
fb3b27bc 3763 pci_save_state(pdev);
9a799d71 3764
30eba97a 3765 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 3766 if (!netdev) {
3767 err = -ENOMEM;
3768 goto err_alloc_etherdev;
3769 }
3770
9a799d71
AK		 3771 SET_NETDEV_DEV(netdev, &pdev->dev);
3772
3773 pci_set_drvdata(pdev, netdev);
3774 adapter = netdev_priv(netdev);
3775
3776 adapter->netdev = netdev;
3777 adapter->pdev = pdev;
3778 hw = &adapter->hw;
3779 hw->back = adapter;
3780 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
3781
05857980
JK		 3782 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
3783 pci_resource_len(pdev, 0));
9a799d71
AK		 3784 if (!hw->hw_addr) {
3785 err = -EIO;
3786 goto err_ioremap;
3787 }
3788
3789 for (i = 1; i <= 5; i++) {
3790 if (pci_resource_len(pdev, i) == 0)
3791 continue;
3792 }
3793
3794 netdev->open = &ixgbe_open;
3795 netdev->stop = &ixgbe_close;
3796 netdev->hard_start_xmit = &ixgbe_xmit_frame;
3797 netdev->get_stats = &ixgbe_get_stats;
2c5645cf
CL		 3798 netdev->set_rx_mode = &ixgbe_set_rx_mode;
3799 netdev->set_multicast_list = &ixgbe_set_rx_mode;
9a799d71
AK		 3800 netdev->set_mac_address = &ixgbe_set_mac;
3801 netdev->change_mtu = &ixgbe_change_mtu;
3802 ixgbe_set_ethtool_ops(netdev);
3803 netdev->tx_timeout = &ixgbe_tx_timeout;
3804 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 3805 netdev->vlan_rx_register = ixgbe_vlan_rx_register;
3806 netdev->vlan_rx_add_vid = ixgbe_vlan_rx_add_vid;
3807 netdev->vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid;
3808#ifdef CONFIG_NET_POLL_CONTROLLER
3809 netdev->poll_controller = ixgbe_netpoll;
3810#endif
3811 strcpy(netdev->name, pci_name(pdev));
3812
9a799d71
AK		 3813 adapter->bd_number = cards_found;
3814
9a799d71
AK		 3815 /* Setup hw api */
3816 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 3817 hw->mac.type = ii->mac;
9a799d71 3818
c44ade9e
JB		 3819 /* EEPROM */
3820 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
3821 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
3822 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
3823 if (!(eec & (1 << 8)))
3824 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
3825
3826 /* PHY */
3827 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
3828 /* phy->sfp_type = ixgbe_sfp_type_unknown; */
3829
9a799d71
AK		 3830 err = ii->get_invariants(hw);
3831 if (err)
3832 goto err_hw_init;
3833
3834 /* setup the private structure */
3835 err = ixgbe_sw_init(adapter);
3836 if (err)
3837 goto err_sw_init;
3838
c44ade9e
JB		 3839 /* reset_hw fills in the perm_addr as well */
3840 err = hw->mac.ops.reset_hw(hw);
3841 if (err) {
3842 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
3843 goto err_sw_init;
3844 }
3845
9a799d71 3846 netdev->features = NETIF_F_SG |
b4617240
PW		 3847 NETIF_F_IP_CSUM |
3848 NETIF_F_HW_VLAN_TX |
3849 NETIF_F_HW_VLAN_RX |
3850 NETIF_F_HW_VLAN_FILTER;
9a799d71 3851
e9990a9c 3852 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 3853 netdev->features |= NETIF_F_TSO;
9a799d71 3854 netdev->features |= NETIF_F_TSO6;
e9990a9c 3855 netdev->features |= NETIF_F_LRO;
ad31c402
JK		 3856
3857 netdev->vlan_features |= NETIF_F_TSO;
3858 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 3859 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 3860 netdev->vlan_features |= NETIF_F_SG;
3861
9a799d71
AK		 3862 if (pci_using_dac)
3863 netdev->features |= NETIF_F_HIGHDMA;
3864
9a799d71 3865 /* make sure the EEPROM is good */
c44ade9e 3866 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 3867 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
3868 err = -EIO;
3869 goto err_eeprom;
3870 }
3871
3872 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
3873 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
3874
c44ade9e
JB		 3875 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
3876 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 3877 err = -EIO;
3878 goto err_eeprom;
3879 }
3880
3881 init_timer(&adapter->watchdog_timer);
3882 adapter->watchdog_timer.function = &ixgbe_watchdog;
3883 adapter->watchdog_timer.data = (unsigned long)adapter;
3884
3885 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 3886 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 3887
021230d4
AV		 3888 err = ixgbe_init_interrupt_scheme(adapter);
3889 if (err)
3890 goto err_sw_init;
9a799d71
AK		 3891
3892 /* print bus type/speed/width info */
3893 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
3894 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
3895 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
3896 dev_info(&pdev->dev, "(PCI Express:%s:%s) "
b4617240
PW		 3897 "%02x:%02x:%02x:%02x:%02x:%02x\n",
3898 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
3899 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
3900 "Unknown"),
3901 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
3902 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
3903 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
3904 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
3905 "Unknown"),
3906 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
3907 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
c44ade9e 3908 ixgbe_read_pba_num_generic(hw, &part_num);
9a799d71 3909 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
b4617240
PW		 3910 hw->mac.type, hw->phy.type,
3911 (part_num >> 8), (part_num & 0xff));
9a799d71 3912
0c254d86
AK		 3913 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
3914 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 3915 "this card is not sufficient for optimal "
3916 "performance.\n");
0c254d86 3917 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 3918 "PCI-Express slot is required.\n");
0c254d86
AK		 3919 }
3920
9a799d71 3921 /* reset the hardware with the new settings */
c44ade9e
JB		 3922 hw->mac.ops.start_hw(hw);
3923
3924 /* link_config depends on start_hw being called at least once */
3925 err = ixgbe_link_config(hw);
3926 if (err) {
3927 dev_err(&pdev->dev, "setup_link_speed FAILED %d\n", err);
3928 goto err_register;
3929 }
9a799d71
AK		 3930
3931 netif_carrier_off(netdev);
fd2ea0a7 3932 netif_tx_stop_all_queues(netdev);
9a799d71 3933
021230d4
AV		 3934 ixgbe_napi_add_all(adapter);
3935
9a799d71
AK		 3936 strcpy(netdev->name, "eth%d");
3937 err = register_netdev(netdev);
3938 if (err)
3939 goto err_register;
3940
a1f96ee7 3941#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
652f093f 3942 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 3943 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
3944 /* always use CB2 mode, difference is masked
3945 * in the CB driver */
3946 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
3947 ixgbe_setup_dca(adapter);
3948 }
3949#endif
9a799d71
AK		 3950
3951 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
3952 cards_found++;
3953 return 0;
3954
3955err_register:
5eba3699 3956 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3957err_hw_init:
3958err_sw_init:
021230d4 3959 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3960err_eeprom:
3961 iounmap(hw->hw_addr);
3962err_ioremap:
3963 free_netdev(netdev);
3964err_alloc_etherdev:
3965 pci_release_regions(pdev);
3966err_pci_reg:
3967err_dma:
3968 pci_disable_device(pdev);
3969 return err;
3970}
3971
3972/**
3973 * ixgbe_remove - Device Removal Routine
3974 * @pdev: PCI device information struct
3975 *
3976 * ixgbe_remove is called by the PCI subsystem to alert the driver
3977 * that it should release a PCI device. The could be caused by a
3978 * Hot-Plug event, or because the driver is going to be removed from
3979 * memory.
3980 **/
3981static void __devexit ixgbe_remove(struct pci_dev *pdev)
3982{
3983 struct net_device *netdev = pci_get_drvdata(pdev);
3984 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3985
3986 set_bit(__IXGBE_DOWN, &adapter->state);
3987 del_timer_sync(&adapter->watchdog_timer);
3988
3989 flush_scheduled_work();
3990
a1f96ee7 3991#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd
JC		 3992 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3993 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
3994 dca_remove_requester(&pdev->dev);
3995 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
3996 }
3997
3998#endif
9a799d71
AK		 3999 unregister_netdev(netdev);
4000
021230d4 4001 ixgbe_reset_interrupt_capability(adapter);
5eba3699 4002
021230d4 4003 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4004
4005 iounmap(adapter->hw.hw_addr);
4006 pci_release_regions(pdev);
4007
021230d4 4008 DPRINTK(PROBE, INFO, "complete\n");
b3c8b4ba 4009 ixgbe_napi_del_all(adapter);
021230d4
AV		 4010 kfree(adapter->tx_ring);
4011 kfree(adapter->rx_ring);
4012
9a799d71
AK		 4013 free_netdev(netdev);
4014
4015 pci_disable_device(pdev);
4016}
4017
4018/**
4019 * ixgbe_io_error_detected - called when PCI error is detected
4020 * @pdev: Pointer to PCI device
4021 * @state: The current pci connection state
4022 *
4023 * This function is called after a PCI bus error affecting
4024 * this device has been detected.
4025 */
4026static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 4027 pci_channel_state_t state)
9a799d71
AK		 4028{
4029 struct net_device *netdev = pci_get_drvdata(pdev);
4030 struct ixgbe_adapter *adapter = netdev->priv;
4031
4032 netif_device_detach(netdev);
4033
4034 if (netif_running(netdev))
4035 ixgbe_down(adapter);
4036 pci_disable_device(pdev);
4037
b4617240 4038 /* Request a slot reset. */
9a799d71
AK		 4039 return PCI_ERS_RESULT_NEED_RESET;
4040}
4041
4042/**
4043 * ixgbe_io_slot_reset - called after the pci bus has been reset.
4044 * @pdev: Pointer to PCI device
4045 *
4046 * Restart the card from scratch, as if from a cold-boot.
4047 */
4048static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4049{
4050 struct net_device *netdev = pci_get_drvdata(pdev);
4051 struct ixgbe_adapter *adapter = netdev->priv;
4052
4053 if (pci_enable_device(pdev)) {
4054 DPRINTK(PROBE, ERR,
b4617240 4055 "Cannot re-enable PCI device after reset.\n");
9a799d71
AK		 4056 return PCI_ERS_RESULT_DISCONNECT;
4057 }
4058 pci_set_master(pdev);
fb3b27bc 4059 pci_restore_state(pdev);
9a799d71
AK		 4060
4061 pci_enable_wake(pdev, PCI_D3hot, 0);
4062 pci_enable_wake(pdev, PCI_D3cold, 0);
4063
4064 ixgbe_reset(adapter);
4065
4066 return PCI_ERS_RESULT_RECOVERED;
4067}
4068
4069/**
4070 * ixgbe_io_resume - called when traffic can start flowing again.
4071 * @pdev: Pointer to PCI device
4072 *
4073 * This callback is called when the error recovery driver tells us that
4074 * its OK to resume normal operation.
4075 */
4076static void ixgbe_io_resume(struct pci_dev *pdev)
4077{
4078 struct net_device *netdev = pci_get_drvdata(pdev);
4079 struct ixgbe_adapter *adapter = netdev->priv;
4080
4081 if (netif_running(netdev)) {
4082 if (ixgbe_up(adapter)) {
4083 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4084 return;
4085 }
4086 }
4087
4088 netif_device_attach(netdev);
4089
4090}
4091
4092static struct pci_error_handlers ixgbe_err_handler = {
4093 .error_detected = ixgbe_io_error_detected,
4094 .slot_reset = ixgbe_io_slot_reset,
4095 .resume = ixgbe_io_resume,
4096};
4097
4098static struct pci_driver ixgbe_driver = {
4099 .name = ixgbe_driver_name,
4100 .id_table = ixgbe_pci_tbl,
4101 .probe = ixgbe_probe,
4102 .remove = __devexit_p(ixgbe_remove),
4103#ifdef CONFIG_PM
4104 .suspend = ixgbe_suspend,
4105 .resume = ixgbe_resume,
4106#endif
4107 .shutdown = ixgbe_shutdown,
4108 .err_handler = &ixgbe_err_handler
4109};
4110
4111/**
4112 * ixgbe_init_module - Driver Registration Routine
4113 *
4114 * ixgbe_init_module is the first routine called when the driver is
4115 * loaded. All it does is register with the PCI subsystem.
4116 **/
4117static int __init ixgbe_init_module(void)
4118{
4119 int ret;
4120 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4121 ixgbe_driver_string, ixgbe_driver_version);
4122
4123 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4124
a1f96ee7 4125#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd
JC		 4126 dca_register_notify(&dca_notifier);
4127
4128#endif
9a799d71
AK		 4129 ret = pci_register_driver(&ixgbe_driver);
4130 return ret;
4131}
b4617240 4132
9a799d71
AK		 4133module_init(ixgbe_init_module);
4134
4135/**
4136 * ixgbe_exit_module - Driver Exit Cleanup Routine
4137 *
4138 * ixgbe_exit_module is called just before the driver is removed
4139 * from memory.
4140 **/
4141static void __exit ixgbe_exit_module(void)
4142{
a1f96ee7 4143#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd
JC		 4144 dca_unregister_notify(&dca_notifier);
4145#endif
9a799d71
AK		 4146 pci_unregister_driver(&ixgbe_driver);
4147}
bd0362dd 4148
a1f96ee7 4149#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
bd0362dd 4150static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 4151 void *p)
bd0362dd
JC		 4152{
4153 int ret_val;
4154
4155 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 4156 __ixgbe_notify_dca);
bd0362dd
JC		 4157
4158 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4159}
96b0e0f6 4160#endif /* CONFIG_DCA or CONFIG_DCA_MODULE */
bd0362dd 4161
9a799d71
AK		 4162module_exit(ixgbe_exit_module);
4163
4164/* ixgbe_main.c */
Linux kernel - Deliverables
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