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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
8c47eaa7 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
60127865 | 37 | #include <linux/pkt_sched.h> |
9a799d71 | 38 | #include <linux/ipv6.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
9a799d71 AK |
40 | #include <net/checksum.h> |
41 | #include <net/ip6_checksum.h> | |
42 | #include <linux/ethtool.h> | |
43 | #include <linux/if_vlan.h> | |
eacd73f7 | 44 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
45 | |
46 | #include "ixgbe.h" | |
47 | #include "ixgbe_common.h" | |
ee5f784a | 48 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 49 | #include "ixgbe_sriov.h" |
9a799d71 AK |
50 | |
51 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 52 | static const char ixgbe_driver_string[] = |
e8e9f696 | 53 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
9a799d71 | 54 | |
310e5ca8 | 55 | #define DRV_VERSION "3.2.9-k2" |
9c8eb720 | 56 | const char ixgbe_driver_version[] = DRV_VERSION; |
8c47eaa7 | 57 | static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation."; |
9a799d71 AK |
58 | |
59 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 60 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 61 | [board_82599] = &ixgbe_82599_info, |
fe15e8e1 | 62 | [board_X540] = &ixgbe_X540_info, |
9a799d71 AK |
63 | }; |
64 | ||
65 | /* ixgbe_pci_tbl - PCI Device ID Table | |
66 | * | |
67 | * Wildcard entries (PCI_ANY_ID) should come last | |
68 | * Last entry must be all 0s | |
69 | * | |
70 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
71 | * Class, Class Mask, private data (not used) } | |
72 | */ | |
a3aa1884 | 73 | static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { |
1e336d0f DS |
74 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), |
75 | board_82598 }, | |
9a799d71 | 76 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), |
3957d63d | 77 | board_82598 }, |
9a799d71 | 78 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 79 | board_82598 }, |
0befdb3e JB |
80 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
81 | board_82598 }, | |
3845bec0 PWJ |
82 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), |
83 | board_82598 }, | |
9a799d71 | 84 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 85 | board_82598 }, |
8d792cd9 JB |
86 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
87 | board_82598 }, | |
c4900be0 DS |
88 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
89 | board_82598 }, | |
90 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
91 | board_82598 }, | |
b95f5fcb JB |
92 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
93 | board_82598 }, | |
c4900be0 DS |
94 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
95 | board_82598 }, | |
2f21bdd3 DS |
96 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), |
97 | board_82598 }, | |
e8e26350 PW |
98 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), |
99 | board_82599 }, | |
1fcf03e6 PWJ |
100 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), |
101 | board_82599 }, | |
74757d49 DS |
102 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), |
103 | board_82599 }, | |
e8e26350 PW |
104 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), |
105 | board_82599 }, | |
38ad1c8e DS |
106 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), |
107 | board_82599 }, | |
dbfec662 DS |
108 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), |
109 | board_82599 }, | |
8911184f PWJ |
110 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), |
111 | board_82599 }, | |
dbffcb21 DS |
112 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), |
113 | board_82599 }, | |
114 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), | |
115 | board_82599 }, | |
119fc60a MC |
116 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), |
117 | board_82599 }, | |
312eb931 DS |
118 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), |
119 | board_82599 }, | |
b93a2226 | 120 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), |
d994653d | 121 | board_X540 }, |
9a799d71 AK |
122 | |
123 | /* required last entry */ | |
124 | {0, } | |
125 | }; | |
126 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
127 | ||
5dd2d332 | 128 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 129 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
e8e9f696 | 130 | void *p); |
bd0362dd JC |
131 | static struct notifier_block dca_notifier = { |
132 | .notifier_call = ixgbe_notify_dca, | |
133 | .next = NULL, | |
134 | .priority = 0 | |
135 | }; | |
136 | #endif | |
137 | ||
1cdd1ec8 GR |
138 | #ifdef CONFIG_PCI_IOV |
139 | static unsigned int max_vfs; | |
140 | module_param(max_vfs, uint, 0); | |
e8e9f696 JP |
141 | MODULE_PARM_DESC(max_vfs, |
142 | "Maximum number of virtual functions to allocate per physical function"); | |
1cdd1ec8 GR |
143 | #endif /* CONFIG_PCI_IOV */ |
144 | ||
9a799d71 AK |
145 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
146 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
147 | MODULE_LICENSE("GPL"); | |
148 | MODULE_VERSION(DRV_VERSION); | |
149 | ||
150 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
151 | ||
1cdd1ec8 GR |
152 | static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter) |
153 | { | |
154 | struct ixgbe_hw *hw = &adapter->hw; | |
155 | u32 gcr; | |
156 | u32 gpie; | |
157 | u32 vmdctl; | |
158 | ||
159 | #ifdef CONFIG_PCI_IOV | |
160 | /* disable iov and allow time for transactions to clear */ | |
161 | pci_disable_sriov(adapter->pdev); | |
162 | #endif | |
163 | ||
164 | /* turn off device IOV mode */ | |
165 | gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
166 | gcr &= ~(IXGBE_GCR_EXT_SRIOV); | |
167 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr); | |
168 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
169 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
170 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
171 | ||
172 | /* set default pool back to 0 */ | |
173 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
174 | vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; | |
175 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); | |
176 | ||
177 | /* take a breather then clean up driver data */ | |
178 | msleep(100); | |
e8e9f696 JP |
179 | |
180 | kfree(adapter->vfinfo); | |
1cdd1ec8 GR |
181 | adapter->vfinfo = NULL; |
182 | ||
183 | adapter->num_vfs = 0; | |
184 | adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; | |
185 | } | |
186 | ||
dcd79aeb TI |
187 | struct ixgbe_reg_info { |
188 | u32 ofs; | |
189 | char *name; | |
190 | }; | |
191 | ||
192 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
193 | ||
194 | /* General Registers */ | |
195 | {IXGBE_CTRL, "CTRL"}, | |
196 | {IXGBE_STATUS, "STATUS"}, | |
197 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
198 | ||
199 | /* Interrupt Registers */ | |
200 | {IXGBE_EICR, "EICR"}, | |
201 | ||
202 | /* RX Registers */ | |
203 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
204 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
205 | {IXGBE_RDLEN(0), "RDLEN"}, | |
206 | {IXGBE_RDH(0), "RDH"}, | |
207 | {IXGBE_RDT(0), "RDT"}, | |
208 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
209 | {IXGBE_RDBAL(0), "RDBAL"}, | |
210 | {IXGBE_RDBAH(0), "RDBAH"}, | |
211 | ||
212 | /* TX Registers */ | |
213 | {IXGBE_TDBAL(0), "TDBAL"}, | |
214 | {IXGBE_TDBAH(0), "TDBAH"}, | |
215 | {IXGBE_TDLEN(0), "TDLEN"}, | |
216 | {IXGBE_TDH(0), "TDH"}, | |
217 | {IXGBE_TDT(0), "TDT"}, | |
218 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
219 | ||
220 | /* List Terminator */ | |
221 | {} | |
222 | }; | |
223 | ||
224 | ||
225 | /* | |
226 | * ixgbe_regdump - register printout routine | |
227 | */ | |
228 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
229 | { | |
230 | int i = 0, j = 0; | |
231 | char rname[16]; | |
232 | u32 regs[64]; | |
233 | ||
234 | switch (reginfo->ofs) { | |
235 | case IXGBE_SRRCTL(0): | |
236 | for (i = 0; i < 64; i++) | |
237 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
238 | break; | |
239 | case IXGBE_DCA_RXCTRL(0): | |
240 | for (i = 0; i < 64; i++) | |
241 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
242 | break; | |
243 | case IXGBE_RDLEN(0): | |
244 | for (i = 0; i < 64; i++) | |
245 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
246 | break; | |
247 | case IXGBE_RDH(0): | |
248 | for (i = 0; i < 64; i++) | |
249 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
250 | break; | |
251 | case IXGBE_RDT(0): | |
252 | for (i = 0; i < 64; i++) | |
253 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
254 | break; | |
255 | case IXGBE_RXDCTL(0): | |
256 | for (i = 0; i < 64; i++) | |
257 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
258 | break; | |
259 | case IXGBE_RDBAL(0): | |
260 | for (i = 0; i < 64; i++) | |
261 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
262 | break; | |
263 | case IXGBE_RDBAH(0): | |
264 | for (i = 0; i < 64; i++) | |
265 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
266 | break; | |
267 | case IXGBE_TDBAL(0): | |
268 | for (i = 0; i < 64; i++) | |
269 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
270 | break; | |
271 | case IXGBE_TDBAH(0): | |
272 | for (i = 0; i < 64; i++) | |
273 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
274 | break; | |
275 | case IXGBE_TDLEN(0): | |
276 | for (i = 0; i < 64; i++) | |
277 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
278 | break; | |
279 | case IXGBE_TDH(0): | |
280 | for (i = 0; i < 64; i++) | |
281 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
282 | break; | |
283 | case IXGBE_TDT(0): | |
284 | for (i = 0; i < 64; i++) | |
285 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
286 | break; | |
287 | case IXGBE_TXDCTL(0): | |
288 | for (i = 0; i < 64; i++) | |
289 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
290 | break; | |
291 | default: | |
c7689578 | 292 | pr_info("%-15s %08x\n", reginfo->name, |
dcd79aeb TI |
293 | IXGBE_READ_REG(hw, reginfo->ofs)); |
294 | return; | |
295 | } | |
296 | ||
297 | for (i = 0; i < 8; i++) { | |
298 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); | |
c7689578 | 299 | pr_err("%-15s", rname); |
dcd79aeb | 300 | for (j = 0; j < 8; j++) |
c7689578 JP |
301 | pr_cont(" %08x", regs[i*8+j]); |
302 | pr_cont("\n"); | |
dcd79aeb TI |
303 | } |
304 | ||
305 | } | |
306 | ||
307 | /* | |
308 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
309 | */ | |
310 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
311 | { | |
312 | struct net_device *netdev = adapter->netdev; | |
313 | struct ixgbe_hw *hw = &adapter->hw; | |
314 | struct ixgbe_reg_info *reginfo; | |
315 | int n = 0; | |
316 | struct ixgbe_ring *tx_ring; | |
317 | struct ixgbe_tx_buffer *tx_buffer_info; | |
318 | union ixgbe_adv_tx_desc *tx_desc; | |
319 | struct my_u0 { u64 a; u64 b; } *u0; | |
320 | struct ixgbe_ring *rx_ring; | |
321 | union ixgbe_adv_rx_desc *rx_desc; | |
322 | struct ixgbe_rx_buffer *rx_buffer_info; | |
323 | u32 staterr; | |
324 | int i = 0; | |
325 | ||
326 | if (!netif_msg_hw(adapter)) | |
327 | return; | |
328 | ||
329 | /* Print netdevice Info */ | |
330 | if (netdev) { | |
331 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
c7689578 | 332 | pr_info("Device Name state " |
dcd79aeb | 333 | "trans_start last_rx\n"); |
c7689578 JP |
334 | pr_info("%-15s %016lX %016lX %016lX\n", |
335 | netdev->name, | |
336 | netdev->state, | |
337 | netdev->trans_start, | |
338 | netdev->last_rx); | |
dcd79aeb TI |
339 | } |
340 | ||
341 | /* Print Registers */ | |
342 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
c7689578 | 343 | pr_info(" Register Name Value\n"); |
dcd79aeb TI |
344 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; |
345 | reginfo->name; reginfo++) { | |
346 | ixgbe_regdump(hw, reginfo); | |
347 | } | |
348 | ||
349 | /* Print TX Ring Summary */ | |
350 | if (!netdev || !netif_running(netdev)) | |
351 | goto exit; | |
352 | ||
353 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
c7689578 | 354 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
dcd79aeb TI |
355 | for (n = 0; n < adapter->num_tx_queues; n++) { |
356 | tx_ring = adapter->tx_ring[n]; | |
357 | tx_buffer_info = | |
358 | &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; | |
c7689578 | 359 | pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", |
dcd79aeb TI |
360 | n, tx_ring->next_to_use, tx_ring->next_to_clean, |
361 | (u64)tx_buffer_info->dma, | |
362 | tx_buffer_info->length, | |
363 | tx_buffer_info->next_to_watch, | |
364 | (u64)tx_buffer_info->time_stamp); | |
365 | } | |
366 | ||
367 | /* Print TX Rings */ | |
368 | if (!netif_msg_tx_done(adapter)) | |
369 | goto rx_ring_summary; | |
370 | ||
371 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
372 | ||
373 | /* Transmit Descriptor Formats | |
374 | * | |
375 | * Advanced Transmit Descriptor | |
376 | * +--------------------------------------------------------------+ | |
377 | * 0 | Buffer Address [63:0] | | |
378 | * +--------------------------------------------------------------+ | |
379 | * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | | |
380 | * +--------------------------------------------------------------+ | |
381 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
382 | */ | |
383 | ||
384 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
385 | tx_ring = adapter->tx_ring[n]; | |
c7689578 JP |
386 | pr_info("------------------------------------\n"); |
387 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
388 | pr_info("------------------------------------\n"); | |
389 | pr_info("T [desc] [address 63:0 ] " | |
dcd79aeb TI |
390 | "[PlPOIdStDDt Ln] [bi->dma ] " |
391 | "leng ntw timestamp bi->skb\n"); | |
392 | ||
393 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
31f05a2d | 394 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i); |
dcd79aeb TI |
395 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
396 | u0 = (struct my_u0 *)tx_desc; | |
c7689578 | 397 | pr_info("T [0x%03X] %016llX %016llX %016llX" |
dcd79aeb TI |
398 | " %04X %3X %016llX %p", i, |
399 | le64_to_cpu(u0->a), | |
400 | le64_to_cpu(u0->b), | |
401 | (u64)tx_buffer_info->dma, | |
402 | tx_buffer_info->length, | |
403 | tx_buffer_info->next_to_watch, | |
404 | (u64)tx_buffer_info->time_stamp, | |
405 | tx_buffer_info->skb); | |
406 | if (i == tx_ring->next_to_use && | |
407 | i == tx_ring->next_to_clean) | |
c7689578 | 408 | pr_cont(" NTC/U\n"); |
dcd79aeb | 409 | else if (i == tx_ring->next_to_use) |
c7689578 | 410 | pr_cont(" NTU\n"); |
dcd79aeb | 411 | else if (i == tx_ring->next_to_clean) |
c7689578 | 412 | pr_cont(" NTC\n"); |
dcd79aeb | 413 | else |
c7689578 | 414 | pr_cont("\n"); |
dcd79aeb TI |
415 | |
416 | if (netif_msg_pktdata(adapter) && | |
417 | tx_buffer_info->dma != 0) | |
418 | print_hex_dump(KERN_INFO, "", | |
419 | DUMP_PREFIX_ADDRESS, 16, 1, | |
420 | phys_to_virt(tx_buffer_info->dma), | |
421 | tx_buffer_info->length, true); | |
422 | } | |
423 | } | |
424 | ||
425 | /* Print RX Rings Summary */ | |
426 | rx_ring_summary: | |
427 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
c7689578 | 428 | pr_info("Queue [NTU] [NTC]\n"); |
dcd79aeb TI |
429 | for (n = 0; n < adapter->num_rx_queues; n++) { |
430 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
431 | pr_info("%5d %5X %5X\n", |
432 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
dcd79aeb TI |
433 | } |
434 | ||
435 | /* Print RX Rings */ | |
436 | if (!netif_msg_rx_status(adapter)) | |
437 | goto exit; | |
438 | ||
439 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
440 | ||
441 | /* Advanced Receive Descriptor (Read) Format | |
442 | * 63 1 0 | |
443 | * +-----------------------------------------------------+ | |
444 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
445 | * +----------------------------------------------+------+ | |
446 | * 8 | Header Buffer Address [63:1] | DD | | |
447 | * +-----------------------------------------------------+ | |
448 | * | |
449 | * | |
450 | * Advanced Receive Descriptor (Write-Back) Format | |
451 | * | |
452 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
453 | * +------------------------------------------------------+ | |
454 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
455 | * | Checksum Ident | | | | Type | Type | | |
456 | * +------------------------------------------------------+ | |
457 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
458 | * +------------------------------------------------------+ | |
459 | * 63 48 47 32 31 20 19 0 | |
460 | */ | |
461 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
462 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
463 | pr_info("------------------------------------\n"); |
464 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
465 | pr_info("------------------------------------\n"); | |
466 | pr_info("R [desc] [ PktBuf A0] " | |
dcd79aeb TI |
467 | "[ HeadBuf DD] [bi->dma ] [bi->skb] " |
468 | "<-- Adv Rx Read format\n"); | |
c7689578 | 469 | pr_info("RWB[desc] [PcsmIpSHl PtRs] " |
dcd79aeb TI |
470 | "[vl er S cks ln] ---------------- [bi->skb] " |
471 | "<-- Adv Rx Write-Back format\n"); | |
472 | ||
473 | for (i = 0; i < rx_ring->count; i++) { | |
474 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
31f05a2d | 475 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i); |
dcd79aeb TI |
476 | u0 = (struct my_u0 *)rx_desc; |
477 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
478 | if (staterr & IXGBE_RXD_STAT_DD) { | |
479 | /* Descriptor Done */ | |
c7689578 | 480 | pr_info("RWB[0x%03X] %016llX " |
dcd79aeb TI |
481 | "%016llX ---------------- %p", i, |
482 | le64_to_cpu(u0->a), | |
483 | le64_to_cpu(u0->b), | |
484 | rx_buffer_info->skb); | |
485 | } else { | |
c7689578 | 486 | pr_info("R [0x%03X] %016llX " |
dcd79aeb TI |
487 | "%016llX %016llX %p", i, |
488 | le64_to_cpu(u0->a), | |
489 | le64_to_cpu(u0->b), | |
490 | (u64)rx_buffer_info->dma, | |
491 | rx_buffer_info->skb); | |
492 | ||
493 | if (netif_msg_pktdata(adapter)) { | |
494 | print_hex_dump(KERN_INFO, "", | |
495 | DUMP_PREFIX_ADDRESS, 16, 1, | |
496 | phys_to_virt(rx_buffer_info->dma), | |
497 | rx_ring->rx_buf_len, true); | |
498 | ||
499 | if (rx_ring->rx_buf_len | |
500 | < IXGBE_RXBUFFER_2048) | |
501 | print_hex_dump(KERN_INFO, "", | |
502 | DUMP_PREFIX_ADDRESS, 16, 1, | |
503 | phys_to_virt( | |
504 | rx_buffer_info->page_dma + | |
505 | rx_buffer_info->page_offset | |
506 | ), | |
507 | PAGE_SIZE/2, true); | |
508 | } | |
509 | } | |
510 | ||
511 | if (i == rx_ring->next_to_use) | |
c7689578 | 512 | pr_cont(" NTU\n"); |
dcd79aeb | 513 | else if (i == rx_ring->next_to_clean) |
c7689578 | 514 | pr_cont(" NTC\n"); |
dcd79aeb | 515 | else |
c7689578 | 516 | pr_cont("\n"); |
dcd79aeb TI |
517 | |
518 | } | |
519 | } | |
520 | ||
521 | exit: | |
522 | return; | |
523 | } | |
524 | ||
5eba3699 AV |
525 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
526 | { | |
527 | u32 ctrl_ext; | |
528 | ||
529 | /* Let firmware take over control of h/w */ | |
530 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
531 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 532 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
533 | } |
534 | ||
535 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
536 | { | |
537 | u32 ctrl_ext; | |
538 | ||
539 | /* Let firmware know the driver has taken over */ | |
540 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
541 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 542 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 543 | } |
9a799d71 | 544 | |
e8e26350 PW |
545 | /* |
546 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
547 | * @adapter: pointer to adapter struct | |
548 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
549 | * @queue: queue to map the corresponding interrupt to | |
550 | * @msix_vector: the vector to map to the corresponding queue | |
551 | * | |
552 | */ | |
553 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
e8e9f696 | 554 | u8 queue, u8 msix_vector) |
9a799d71 AK |
555 | { |
556 | u32 ivar, index; | |
e8e26350 PW |
557 | struct ixgbe_hw *hw = &adapter->hw; |
558 | switch (hw->mac.type) { | |
559 | case ixgbe_mac_82598EB: | |
560 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
561 | if (direction == -1) | |
562 | direction = 0; | |
563 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
564 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
565 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
566 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
567 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
568 | break; | |
569 | case ixgbe_mac_82599EB: | |
b93a2226 | 570 | case ixgbe_mac_X540: |
e8e26350 PW |
571 | if (direction == -1) { |
572 | /* other causes */ | |
573 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
574 | index = ((queue & 1) * 8); | |
575 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
576 | ivar &= ~(0xFF << index); | |
577 | ivar |= (msix_vector << index); | |
578 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
579 | break; | |
580 | } else { | |
581 | /* tx or rx causes */ | |
582 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
583 | index = ((16 * (queue & 1)) + (8 * direction)); | |
584 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
585 | ivar &= ~(0xFF << index); | |
586 | ivar |= (msix_vector << index); | |
587 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
588 | break; | |
589 | } | |
590 | default: | |
591 | break; | |
592 | } | |
9a799d71 AK |
593 | } |
594 | ||
fe49f04a | 595 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
e8e9f696 | 596 | u64 qmask) |
fe49f04a AD |
597 | { |
598 | u32 mask; | |
599 | ||
bd508178 AD |
600 | switch (adapter->hw.mac.type) { |
601 | case ixgbe_mac_82598EB: | |
fe49f04a AD |
602 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
603 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
bd508178 AD |
604 | break; |
605 | case ixgbe_mac_82599EB: | |
b93a2226 | 606 | case ixgbe_mac_X540: |
fe49f04a AD |
607 | mask = (qmask & 0xFFFFFFFF); |
608 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
609 | mask = (qmask >> 32); | |
610 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
bd508178 AD |
611 | break; |
612 | default: | |
613 | break; | |
fe49f04a AD |
614 | } |
615 | } | |
616 | ||
b6ec895e AD |
617 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring, |
618 | struct ixgbe_tx_buffer *tx_buffer_info) | |
9a799d71 | 619 | { |
e5a43549 AD |
620 | if (tx_buffer_info->dma) { |
621 | if (tx_buffer_info->mapped_as_page) | |
b6ec895e | 622 | dma_unmap_page(tx_ring->dev, |
e5a43549 AD |
623 | tx_buffer_info->dma, |
624 | tx_buffer_info->length, | |
1b507730 | 625 | DMA_TO_DEVICE); |
e5a43549 | 626 | else |
b6ec895e | 627 | dma_unmap_single(tx_ring->dev, |
e5a43549 AD |
628 | tx_buffer_info->dma, |
629 | tx_buffer_info->length, | |
1b507730 | 630 | DMA_TO_DEVICE); |
e5a43549 AD |
631 | tx_buffer_info->dma = 0; |
632 | } | |
9a799d71 AK |
633 | if (tx_buffer_info->skb) { |
634 | dev_kfree_skb_any(tx_buffer_info->skb); | |
635 | tx_buffer_info->skb = NULL; | |
636 | } | |
44df32c5 | 637 | tx_buffer_info->time_stamp = 0; |
9a799d71 AK |
638 | /* tx_buffer_info must be completely set up in the transmit path */ |
639 | } | |
640 | ||
26f23d82 | 641 | /** |
c84d324c JF |
642 | * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class |
643 | * @adapter: driver private struct | |
644 | * @index: reg idx of queue to query (0-127) | |
26f23d82 | 645 | * |
c84d324c JF |
646 | * Helper function to determine the traffic index for a paticular |
647 | * register index. | |
26f23d82 | 648 | * |
c84d324c | 649 | * Returns : a tc index for use in range 0-7, or 0-3 |
26f23d82 | 650 | */ |
c84d324c | 651 | u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx) |
26f23d82 | 652 | { |
c84d324c JF |
653 | int tc = -1; |
654 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
26f23d82 | 655 | |
c84d324c JF |
656 | /* if DCB is not enabled the queues have no TC */ |
657 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) | |
658 | return tc; | |
26f23d82 | 659 | |
c84d324c JF |
660 | /* check valid range */ |
661 | if (reg_idx >= adapter->hw.mac.max_tx_queues) | |
662 | return tc; | |
663 | ||
664 | switch (adapter->hw.mac.type) { | |
665 | case ixgbe_mac_82598EB: | |
666 | tc = reg_idx >> 2; | |
667 | break; | |
668 | default: | |
669 | if (dcb_i != 4 && dcb_i != 8) | |
6837e895 | 670 | break; |
c84d324c JF |
671 | |
672 | /* if VMDq is enabled the lowest order bits determine TC */ | |
673 | if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED | | |
674 | IXGBE_FLAG_VMDQ_ENABLED)) { | |
675 | tc = reg_idx & (dcb_i - 1); | |
676 | break; | |
677 | } | |
678 | ||
679 | /* | |
680 | * Convert the reg_idx into the correct TC. This bitmask | |
681 | * targets the last full 32 ring traffic class and assigns | |
682 | * it a value of 1. From there the rest of the rings are | |
683 | * based on shifting the mask further up to include the | |
684 | * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i | |
685 | * will only ever be 8 or 4 and that reg_idx will never | |
686 | * be greater then 128. The code without the power of 2 | |
687 | * optimizations would be: | |
688 | * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32) | |
689 | */ | |
690 | tc = ((reg_idx & 0X1F) + 0x20) * dcb_i; | |
691 | tc >>= 9 - (reg_idx >> 5); | |
692 | } | |
693 | ||
694 | return tc; | |
695 | } | |
696 | ||
697 | static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) | |
698 | { | |
699 | struct ixgbe_hw *hw = &adapter->hw; | |
700 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
701 | u32 data = 0; | |
702 | u32 xoff[8] = {0}; | |
703 | int i; | |
704 | ||
705 | if ((hw->fc.current_mode == ixgbe_fc_full) || | |
706 | (hw->fc.current_mode == ixgbe_fc_rx_pause)) { | |
707 | switch (hw->mac.type) { | |
708 | case ixgbe_mac_82598EB: | |
709 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
6837e895 PW |
710 | break; |
711 | default: | |
c84d324c JF |
712 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); |
713 | } | |
714 | hwstats->lxoffrxc += data; | |
715 | ||
716 | /* refill credits (no tx hang) if we received xoff */ | |
717 | if (!data) | |
718 | return; | |
719 | ||
720 | for (i = 0; i < adapter->num_tx_queues; i++) | |
721 | clear_bit(__IXGBE_HANG_CHECK_ARMED, | |
722 | &adapter->tx_ring[i]->state); | |
723 | return; | |
724 | } else if (!(adapter->dcb_cfg.pfc_mode_enable)) | |
725 | return; | |
726 | ||
727 | /* update stats for each tc, only valid with PFC enabled */ | |
728 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
729 | switch (hw->mac.type) { | |
730 | case ixgbe_mac_82598EB: | |
731 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); | |
bd508178 | 732 | break; |
c84d324c JF |
733 | default: |
734 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); | |
26f23d82 | 735 | } |
c84d324c JF |
736 | hwstats->pxoffrxc[i] += xoff[i]; |
737 | } | |
738 | ||
739 | /* disarm tx queues that have received xoff frames */ | |
740 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
741 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
742 | u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx); | |
743 | ||
744 | if (xoff[tc]) | |
745 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
26f23d82 | 746 | } |
26f23d82 YZ |
747 | } |
748 | ||
c84d324c | 749 | static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) |
9a799d71 | 750 | { |
c84d324c JF |
751 | return ring->tx_stats.completed; |
752 | } | |
753 | ||
754 | static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) | |
755 | { | |
756 | struct ixgbe_adapter *adapter = netdev_priv(ring->netdev); | |
e01c31a5 | 757 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 758 | |
c84d324c JF |
759 | u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); |
760 | u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); | |
761 | ||
762 | if (head != tail) | |
763 | return (head < tail) ? | |
764 | tail - head : (tail + ring->count - head); | |
765 | ||
766 | return 0; | |
767 | } | |
768 | ||
769 | static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) | |
770 | { | |
771 | u32 tx_done = ixgbe_get_tx_completed(tx_ring); | |
772 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
773 | u32 tx_pending = ixgbe_get_tx_pending(tx_ring); | |
774 | bool ret = false; | |
775 | ||
7d637bcc | 776 | clear_check_for_tx_hang(tx_ring); |
c84d324c JF |
777 | |
778 | /* | |
779 | * Check for a hung queue, but be thorough. This verifies | |
780 | * that a transmit has been completed since the previous | |
781 | * check AND there is at least one packet pending. The | |
782 | * ARMED bit is set to indicate a potential hang. The | |
783 | * bit is cleared if a pause frame is received to remove | |
784 | * false hang detection due to PFC or 802.3x frames. By | |
785 | * requiring this to fail twice we avoid races with | |
786 | * pfc clearing the ARMED bit and conditions where we | |
787 | * run the check_tx_hang logic with a transmit completion | |
788 | * pending but without time to complete it yet. | |
789 | */ | |
790 | if ((tx_done_old == tx_done) && tx_pending) { | |
791 | /* make sure it is true for two checks in a row */ | |
792 | ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, | |
793 | &tx_ring->state); | |
794 | } else { | |
795 | /* update completed stats and continue */ | |
796 | tx_ring->tx_stats.tx_done_old = tx_done; | |
797 | /* reset the countdown */ | |
798 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
9a799d71 AK |
799 | } |
800 | ||
c84d324c | 801 | return ret; |
9a799d71 AK |
802 | } |
803 | ||
b4617240 PW |
804 | #define IXGBE_MAX_TXD_PWR 14 |
805 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
806 | |
807 | /* Tx Descriptors needed, worst case */ | |
808 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
809 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
810 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 811 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 812 | |
e01c31a5 JB |
813 | static void ixgbe_tx_timeout(struct net_device *netdev); |
814 | ||
9a799d71 AK |
815 | /** |
816 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 817 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 818 | * @tx_ring: tx ring to clean |
9a799d71 | 819 | **/ |
fe49f04a | 820 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 821 | struct ixgbe_ring *tx_ring) |
9a799d71 | 822 | { |
fe49f04a | 823 | struct ixgbe_adapter *adapter = q_vector->adapter; |
12207e49 PWJ |
824 | union ixgbe_adv_tx_desc *tx_desc, *eop_desc; |
825 | struct ixgbe_tx_buffer *tx_buffer_info; | |
e01c31a5 | 826 | unsigned int total_bytes = 0, total_packets = 0; |
b953799e | 827 | u16 i, eop, count = 0; |
9a799d71 AK |
828 | |
829 | i = tx_ring->next_to_clean; | |
12207e49 | 830 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
31f05a2d | 831 | eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop); |
12207e49 PWJ |
832 | |
833 | while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && | |
9a1a69ad | 834 | (count < tx_ring->work_limit)) { |
12207e49 | 835 | bool cleaned = false; |
2d0bb1c1 | 836 | rmb(); /* read buffer_info after eop_desc */ |
12207e49 | 837 | for ( ; !cleaned; count++) { |
31f05a2d | 838 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i); |
9a799d71 | 839 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
8ad494b0 AD |
840 | |
841 | tx_desc->wb.status = 0; | |
12207e49 | 842 | cleaned = (i == eop); |
9a799d71 | 843 | |
8ad494b0 AD |
844 | i++; |
845 | if (i == tx_ring->count) | |
846 | i = 0; | |
e01c31a5 | 847 | |
8ad494b0 AD |
848 | if (cleaned && tx_buffer_info->skb) { |
849 | total_bytes += tx_buffer_info->bytecount; | |
850 | total_packets += tx_buffer_info->gso_segs; | |
e092be60 | 851 | } |
e01c31a5 | 852 | |
b6ec895e | 853 | ixgbe_unmap_and_free_tx_resource(tx_ring, |
e8e9f696 | 854 | tx_buffer_info); |
e01c31a5 | 855 | } |
12207e49 | 856 | |
c84d324c | 857 | tx_ring->tx_stats.completed++; |
12207e49 | 858 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
31f05a2d | 859 | eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop); |
12207e49 PWJ |
860 | } |
861 | ||
9a799d71 | 862 | tx_ring->next_to_clean = i; |
b953799e AD |
863 | tx_ring->total_bytes += total_bytes; |
864 | tx_ring->total_packets += total_packets; | |
865 | u64_stats_update_begin(&tx_ring->syncp); | |
866 | tx_ring->stats.packets += total_packets; | |
867 | tx_ring->stats.bytes += total_bytes; | |
868 | u64_stats_update_end(&tx_ring->syncp); | |
869 | ||
c84d324c JF |
870 | if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { |
871 | /* schedule immediate reset if we believe we hung */ | |
872 | struct ixgbe_hw *hw = &adapter->hw; | |
873 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop); | |
874 | e_err(drv, "Detected Tx Unit Hang\n" | |
875 | " Tx Queue <%d>\n" | |
876 | " TDH, TDT <%x>, <%x>\n" | |
877 | " next_to_use <%x>\n" | |
878 | " next_to_clean <%x>\n" | |
879 | "tx_buffer_info[next_to_clean]\n" | |
880 | " time_stamp <%lx>\n" | |
881 | " jiffies <%lx>\n", | |
882 | tx_ring->queue_index, | |
883 | IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), | |
884 | IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), | |
885 | tx_ring->next_to_use, eop, | |
886 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
887 | ||
888 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
889 | ||
890 | e_info(probe, | |
891 | "tx hang %d detected on queue %d, resetting adapter\n", | |
892 | adapter->tx_timeout_count + 1, tx_ring->queue_index); | |
893 | ||
b953799e | 894 | /* schedule immediate reset if we believe we hung */ |
b953799e AD |
895 | ixgbe_tx_timeout(adapter->netdev); |
896 | ||
897 | /* the adapter is about to reset, no point in enabling stuff */ | |
898 | return true; | |
899 | } | |
9a799d71 | 900 | |
e092be60 | 901 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
fc77dc3c | 902 | if (unlikely(count && netif_carrier_ok(tx_ring->netdev) && |
e8e9f696 | 903 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { |
e092be60 AV |
904 | /* Make sure that anybody stopping the queue after this |
905 | * sees the new next_to_clean. | |
906 | */ | |
907 | smp_mb(); | |
fc77dc3c | 908 | if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) && |
30eba97a | 909 | !test_bit(__IXGBE_DOWN, &adapter->state)) { |
fc77dc3c | 910 | netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 911 | ++tx_ring->tx_stats.restart_queue; |
30eba97a | 912 | } |
e092be60 | 913 | } |
9a799d71 | 914 | |
807540ba | 915 | return count < tx_ring->work_limit; |
9a799d71 AK |
916 | } |
917 | ||
5dd2d332 | 918 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 919 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
33cf09c9 AD |
920 | struct ixgbe_ring *rx_ring, |
921 | int cpu) | |
bd0362dd | 922 | { |
33cf09c9 | 923 | struct ixgbe_hw *hw = &adapter->hw; |
bd0362dd | 924 | u32 rxctrl; |
33cf09c9 AD |
925 | u8 reg_idx = rx_ring->reg_idx; |
926 | ||
927 | rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx)); | |
928 | switch (hw->mac.type) { | |
929 | case ixgbe_mac_82598EB: | |
930 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
931 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
932 | break; | |
933 | case ixgbe_mac_82599EB: | |
b93a2226 | 934 | case ixgbe_mac_X540: |
33cf09c9 AD |
935 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; |
936 | rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
937 | IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); | |
938 | break; | |
939 | default: | |
940 | break; | |
bd0362dd | 941 | } |
33cf09c9 AD |
942 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
943 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
944 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); | |
945 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | | |
946 | IXGBE_DCA_RXCTRL_DESC_HSRO_EN); | |
947 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); | |
bd0362dd JC |
948 | } |
949 | ||
950 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
33cf09c9 AD |
951 | struct ixgbe_ring *tx_ring, |
952 | int cpu) | |
bd0362dd | 953 | { |
33cf09c9 | 954 | struct ixgbe_hw *hw = &adapter->hw; |
bd0362dd | 955 | u32 txctrl; |
33cf09c9 AD |
956 | u8 reg_idx = tx_ring->reg_idx; |
957 | ||
958 | switch (hw->mac.type) { | |
959 | case ixgbe_mac_82598EB: | |
960 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx)); | |
961 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; | |
962 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
963 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
964 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; | |
965 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl); | |
966 | break; | |
967 | case ixgbe_mac_82599EB: | |
b93a2226 | 968 | case ixgbe_mac_X540: |
33cf09c9 AD |
969 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx)); |
970 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; | |
971 | txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
972 | IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); | |
973 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
974 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; | |
975 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl); | |
976 | break; | |
977 | default: | |
978 | break; | |
979 | } | |
980 | } | |
981 | ||
982 | static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) | |
983 | { | |
984 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
bd0362dd | 985 | int cpu = get_cpu(); |
33cf09c9 AD |
986 | long r_idx; |
987 | int i; | |
bd0362dd | 988 | |
33cf09c9 AD |
989 | if (q_vector->cpu == cpu) |
990 | goto out_no_update; | |
991 | ||
992 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
993 | for (i = 0; i < q_vector->txr_count; i++) { | |
994 | ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu); | |
995 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
996 | r_idx + 1); | |
bd0362dd | 997 | } |
33cf09c9 AD |
998 | |
999 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1000 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1001 | ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu); | |
1002 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1003 | r_idx + 1); | |
1004 | } | |
1005 | ||
1006 | q_vector->cpu = cpu; | |
1007 | out_no_update: | |
bd0362dd JC |
1008 | put_cpu(); |
1009 | } | |
1010 | ||
1011 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
1012 | { | |
33cf09c9 | 1013 | int num_q_vectors; |
bd0362dd JC |
1014 | int i; |
1015 | ||
1016 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
1017 | return; | |
1018 | ||
e35ec126 AD |
1019 | /* always use CB2 mode, difference is masked in the CB driver */ |
1020 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
1021 | ||
33cf09c9 AD |
1022 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
1023 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1024 | else | |
1025 | num_q_vectors = 1; | |
1026 | ||
1027 | for (i = 0; i < num_q_vectors; i++) { | |
1028 | adapter->q_vector[i]->cpu = -1; | |
1029 | ixgbe_update_dca(adapter->q_vector[i]); | |
bd0362dd JC |
1030 | } |
1031 | } | |
1032 | ||
1033 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
1034 | { | |
c60fbb00 | 1035 | struct ixgbe_adapter *adapter = dev_get_drvdata(dev); |
bd0362dd JC |
1036 | unsigned long event = *(unsigned long *)data; |
1037 | ||
33cf09c9 AD |
1038 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) |
1039 | return 0; | |
1040 | ||
bd0362dd JC |
1041 | switch (event) { |
1042 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
1043 | /* if we're already enabled, don't do it again */ |
1044 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1045 | break; | |
652f093f | 1046 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 1047 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
1048 | ixgbe_setup_dca(adapter); |
1049 | break; | |
1050 | } | |
1051 | /* Fall Through since DCA is disabled. */ | |
1052 | case DCA_PROVIDER_REMOVE: | |
1053 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
1054 | dca_remove_requester(dev); | |
1055 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
1056 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
1057 | } | |
1058 | break; | |
1059 | } | |
1060 | ||
652f093f | 1061 | return 0; |
bd0362dd JC |
1062 | } |
1063 | ||
5dd2d332 | 1064 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
1065 | /** |
1066 | * ixgbe_receive_skb - Send a completed packet up the stack | |
1067 | * @adapter: board private structure | |
1068 | * @skb: packet to send up | |
177db6ff MC |
1069 | * @status: hardware indication of status of receive |
1070 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
1071 | * @rx_desc: rx descriptor | |
9a799d71 | 1072 | **/ |
78b6f4ce | 1073 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
e8e9f696 JP |
1074 | struct sk_buff *skb, u8 status, |
1075 | struct ixgbe_ring *ring, | |
1076 | union ixgbe_adv_rx_desc *rx_desc) | |
9a799d71 | 1077 | { |
78b6f4ce HX |
1078 | struct ixgbe_adapter *adapter = q_vector->adapter; |
1079 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
1080 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
1081 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 1082 | |
f62bbb5e JG |
1083 | if (is_vlan && (tag & VLAN_VID_MASK)) |
1084 | __vlan_hwaccel_put_tag(skb, tag); | |
1085 | ||
1086 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) | |
1087 | napi_gro_receive(napi, skb); | |
1088 | else | |
1089 | netif_rx(skb); | |
9a799d71 AK |
1090 | } |
1091 | ||
e59bd25d AV |
1092 | /** |
1093 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
1094 | * @adapter: address of board private structure | |
1095 | * @status_err: hardware indication of status of receive | |
1096 | * @skb: skb currently being received and modified | |
1097 | **/ | |
9a799d71 | 1098 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
8bae1b2b DS |
1099 | union ixgbe_adv_rx_desc *rx_desc, |
1100 | struct sk_buff *skb) | |
9a799d71 | 1101 | { |
8bae1b2b DS |
1102 | u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error); |
1103 | ||
bc8acf2c | 1104 | skb_checksum_none_assert(skb); |
9a799d71 | 1105 | |
712744be JB |
1106 | /* Rx csum disabled */ |
1107 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 1108 | return; |
e59bd25d AV |
1109 | |
1110 | /* if IP and error */ | |
1111 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
1112 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
1113 | adapter->hw_csum_rx_error++; |
1114 | return; | |
1115 | } | |
e59bd25d AV |
1116 | |
1117 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
1118 | return; | |
1119 | ||
1120 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
8bae1b2b DS |
1121 | u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
1122 | ||
1123 | /* | |
1124 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
1125 | * checksum errors. | |
1126 | */ | |
1127 | if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) && | |
1128 | (adapter->hw.mac.type == ixgbe_mac_82599EB)) | |
1129 | return; | |
1130 | ||
e59bd25d AV |
1131 | adapter->hw_csum_rx_error++; |
1132 | return; | |
1133 | } | |
1134 | ||
9a799d71 | 1135 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 1136 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
1137 | } |
1138 | ||
84ea2591 | 1139 | static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val) |
e8e26350 PW |
1140 | { |
1141 | /* | |
1142 | * Force memory writes to complete before letting h/w | |
1143 | * know there are new descriptors to fetch. (Only | |
1144 | * applicable for weak-ordered memory model archs, | |
1145 | * such as IA-64). | |
1146 | */ | |
1147 | wmb(); | |
84ea2591 | 1148 | writel(val, rx_ring->tail); |
e8e26350 PW |
1149 | } |
1150 | ||
9a799d71 AK |
1151 | /** |
1152 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
fc77dc3c AD |
1153 | * @rx_ring: ring to place buffers on |
1154 | * @cleaned_count: number of buffers to replace | |
9a799d71 | 1155 | **/ |
fc77dc3c | 1156 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) |
9a799d71 | 1157 | { |
9a799d71 | 1158 | union ixgbe_adv_rx_desc *rx_desc; |
3a581073 | 1159 | struct ixgbe_rx_buffer *bi; |
d5f398ed AD |
1160 | struct sk_buff *skb; |
1161 | u16 i = rx_ring->next_to_use; | |
9a799d71 | 1162 | |
fc77dc3c AD |
1163 | /* do nothing if no valid netdev defined */ |
1164 | if (!rx_ring->netdev) | |
1165 | return; | |
1166 | ||
9a799d71 | 1167 | while (cleaned_count--) { |
31f05a2d | 1168 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i); |
d5f398ed AD |
1169 | bi = &rx_ring->rx_buffer_info[i]; |
1170 | skb = bi->skb; | |
9a799d71 | 1171 | |
d5f398ed | 1172 | if (!skb) { |
fc77dc3c | 1173 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, |
d5f398ed | 1174 | rx_ring->rx_buf_len); |
9a799d71 | 1175 | if (!skb) { |
5b7da515 | 1176 | rx_ring->rx_stats.alloc_rx_buff_failed++; |
9a799d71 AK |
1177 | goto no_buffers; |
1178 | } | |
d716a7d8 AD |
1179 | /* initialize queue mapping */ |
1180 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
d5f398ed | 1181 | bi->skb = skb; |
d716a7d8 | 1182 | } |
9a799d71 | 1183 | |
d716a7d8 | 1184 | if (!bi->dma) { |
b6ec895e | 1185 | bi->dma = dma_map_single(rx_ring->dev, |
d5f398ed | 1186 | skb->data, |
e8e9f696 | 1187 | rx_ring->rx_buf_len, |
1b507730 | 1188 | DMA_FROM_DEVICE); |
b6ec895e | 1189 | if (dma_mapping_error(rx_ring->dev, bi->dma)) { |
5b7da515 | 1190 | rx_ring->rx_stats.alloc_rx_buff_failed++; |
d5f398ed AD |
1191 | bi->dma = 0; |
1192 | goto no_buffers; | |
1193 | } | |
9a799d71 | 1194 | } |
d5f398ed | 1195 | |
7d637bcc | 1196 | if (ring_is_ps_enabled(rx_ring)) { |
d5f398ed | 1197 | if (!bi->page) { |
fc77dc3c | 1198 | bi->page = netdev_alloc_page(rx_ring->netdev); |
d5f398ed | 1199 | if (!bi->page) { |
5b7da515 | 1200 | rx_ring->rx_stats.alloc_rx_page_failed++; |
d5f398ed AD |
1201 | goto no_buffers; |
1202 | } | |
1203 | } | |
1204 | ||
1205 | if (!bi->page_dma) { | |
1206 | /* use a half page if we're re-using */ | |
1207 | bi->page_offset ^= PAGE_SIZE / 2; | |
b6ec895e | 1208 | bi->page_dma = dma_map_page(rx_ring->dev, |
d5f398ed AD |
1209 | bi->page, |
1210 | bi->page_offset, | |
1211 | PAGE_SIZE / 2, | |
1212 | DMA_FROM_DEVICE); | |
b6ec895e | 1213 | if (dma_mapping_error(rx_ring->dev, |
d5f398ed | 1214 | bi->page_dma)) { |
5b7da515 | 1215 | rx_ring->rx_stats.alloc_rx_page_failed++; |
d5f398ed AD |
1216 | bi->page_dma = 0; |
1217 | goto no_buffers; | |
1218 | } | |
1219 | } | |
1220 | ||
1221 | /* Refresh the desc even if buffer_addrs didn't change | |
1222 | * because each write-back erases this info. */ | |
3a581073 JB |
1223 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
1224 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 1225 | } else { |
3a581073 | 1226 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
84418e3b | 1227 | rx_desc->read.hdr_addr = 0; |
9a799d71 AK |
1228 | } |
1229 | ||
1230 | i++; | |
1231 | if (i == rx_ring->count) | |
1232 | i = 0; | |
9a799d71 | 1233 | } |
7c6e0a43 | 1234 | |
9a799d71 AK |
1235 | no_buffers: |
1236 | if (rx_ring->next_to_use != i) { | |
1237 | rx_ring->next_to_use = i; | |
84ea2591 | 1238 | ixgbe_release_rx_desc(rx_ring, i); |
9a799d71 AK |
1239 | } |
1240 | } | |
1241 | ||
c267fc16 | 1242 | static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc) |
7c6e0a43 | 1243 | { |
c267fc16 AD |
1244 | /* HW will not DMA in data larger than the given buffer, even if it |
1245 | * parses the (NFS, of course) header to be larger. In that case, it | |
1246 | * fills the header buffer and spills the rest into the page. | |
1247 | */ | |
1248 | u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info); | |
1249 | u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
1250 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; | |
1251 | if (hlen > IXGBE_RX_HDR_SIZE) | |
1252 | hlen = IXGBE_RX_HDR_SIZE; | |
1253 | return hlen; | |
7c6e0a43 JB |
1254 | } |
1255 | ||
f8212f97 AD |
1256 | /** |
1257 | * ixgbe_transform_rsc_queue - change rsc queue into a full packet | |
1258 | * @skb: pointer to the last skb in the rsc queue | |
1259 | * | |
1260 | * This function changes a queue full of hw rsc buffers into a completed | |
1261 | * packet. It uses the ->prev pointers to find the first packet and then | |
1262 | * turns it into the frag list owner. | |
1263 | **/ | |
aa80175a | 1264 | static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb) |
f8212f97 AD |
1265 | { |
1266 | unsigned int frag_list_size = 0; | |
aa80175a | 1267 | unsigned int skb_cnt = 1; |
f8212f97 AD |
1268 | |
1269 | while (skb->prev) { | |
1270 | struct sk_buff *prev = skb->prev; | |
1271 | frag_list_size += skb->len; | |
1272 | skb->prev = NULL; | |
1273 | skb = prev; | |
aa80175a | 1274 | skb_cnt++; |
f8212f97 AD |
1275 | } |
1276 | ||
1277 | skb_shinfo(skb)->frag_list = skb->next; | |
1278 | skb->next = NULL; | |
1279 | skb->len += frag_list_size; | |
1280 | skb->data_len += frag_list_size; | |
1281 | skb->truesize += frag_list_size; | |
aa80175a AD |
1282 | IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt; |
1283 | ||
f8212f97 AD |
1284 | return skb; |
1285 | } | |
1286 | ||
aa80175a AD |
1287 | static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc) |
1288 | { | |
1289 | return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) & | |
1290 | IXGBE_RXDADV_RSCCNT_MASK); | |
1291 | } | |
43634e82 | 1292 | |
c267fc16 | 1293 | static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 JP |
1294 | struct ixgbe_ring *rx_ring, |
1295 | int *work_done, int work_to_do) | |
9a799d71 | 1296 | { |
78b6f4ce | 1297 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a799d71 AK |
1298 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; |
1299 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
1300 | struct sk_buff *skb; | |
d2f4fbe2 | 1301 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
c267fc16 | 1302 | const int current_node = numa_node_id(); |
3d8fd385 YZ |
1303 | #ifdef IXGBE_FCOE |
1304 | int ddp_bytes = 0; | |
1305 | #endif /* IXGBE_FCOE */ | |
c267fc16 AD |
1306 | u32 staterr; |
1307 | u16 i; | |
1308 | u16 cleaned_count = 0; | |
aa80175a | 1309 | bool pkt_is_rsc = false; |
9a799d71 AK |
1310 | |
1311 | i = rx_ring->next_to_clean; | |
31f05a2d | 1312 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i); |
9a799d71 | 1313 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
9a799d71 AK |
1314 | |
1315 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 1316 | u32 upper_len = 0; |
9a799d71 | 1317 | |
3c945e5b | 1318 | rmb(); /* read descriptor and rx_buffer_info after status DD */ |
9a799d71 | 1319 | |
c267fc16 AD |
1320 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; |
1321 | ||
9a799d71 | 1322 | skb = rx_buffer_info->skb; |
9a799d71 | 1323 | rx_buffer_info->skb = NULL; |
c267fc16 | 1324 | prefetch(skb->data); |
9a799d71 | 1325 | |
c267fc16 | 1326 | if (ring_is_rsc_enabled(rx_ring)) |
aa80175a | 1327 | pkt_is_rsc = ixgbe_get_rsc_state(rx_desc); |
c267fc16 AD |
1328 | |
1329 | /* if this is a skb from previous receive DMA will be 0 */ | |
21fa4e66 | 1330 | if (rx_buffer_info->dma) { |
c267fc16 | 1331 | u16 hlen; |
aa80175a | 1332 | if (pkt_is_rsc && |
c267fc16 AD |
1333 | !(staterr & IXGBE_RXD_STAT_EOP) && |
1334 | !skb->prev) { | |
43634e82 MC |
1335 | /* |
1336 | * When HWRSC is enabled, delay unmapping | |
1337 | * of the first packet. It carries the | |
1338 | * header information, HW may still | |
1339 | * access the header after the writeback. | |
1340 | * Only unmap it when EOP is reached | |
1341 | */ | |
e8171aaa | 1342 | IXGBE_RSC_CB(skb)->delay_unmap = true; |
43634e82 | 1343 | IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma; |
e8171aaa | 1344 | } else { |
b6ec895e | 1345 | dma_unmap_single(rx_ring->dev, |
e8e9f696 JP |
1346 | rx_buffer_info->dma, |
1347 | rx_ring->rx_buf_len, | |
1348 | DMA_FROM_DEVICE); | |
e8171aaa | 1349 | } |
4f57ca6e | 1350 | rx_buffer_info->dma = 0; |
c267fc16 AD |
1351 | |
1352 | if (ring_is_ps_enabled(rx_ring)) { | |
1353 | hlen = ixgbe_get_hlen(rx_desc); | |
1354 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
1355 | } else { | |
1356 | hlen = le16_to_cpu(rx_desc->wb.upper.length); | |
1357 | } | |
1358 | ||
1359 | skb_put(skb, hlen); | |
1360 | } else { | |
1361 | /* assume packet split since header is unmapped */ | |
1362 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
9a799d71 AK |
1363 | } |
1364 | ||
1365 | if (upper_len) { | |
b6ec895e AD |
1366 | dma_unmap_page(rx_ring->dev, |
1367 | rx_buffer_info->page_dma, | |
1368 | PAGE_SIZE / 2, | |
1369 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1370 | rx_buffer_info->page_dma = 0; |
1371 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
e8e9f696 JP |
1372 | rx_buffer_info->page, |
1373 | rx_buffer_info->page_offset, | |
1374 | upper_len); | |
762f4c57 | 1375 | |
c267fc16 AD |
1376 | if ((page_count(rx_buffer_info->page) == 1) && |
1377 | (page_to_nid(rx_buffer_info->page) == current_node)) | |
762f4c57 | 1378 | get_page(rx_buffer_info->page); |
c267fc16 AD |
1379 | else |
1380 | rx_buffer_info->page = NULL; | |
9a799d71 AK |
1381 | |
1382 | skb->len += upper_len; | |
1383 | skb->data_len += upper_len; | |
1384 | skb->truesize += upper_len; | |
1385 | } | |
1386 | ||
1387 | i++; | |
1388 | if (i == rx_ring->count) | |
1389 | i = 0; | |
9a799d71 | 1390 | |
31f05a2d | 1391 | next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i); |
9a799d71 | 1392 | prefetch(next_rxd); |
9a799d71 | 1393 | cleaned_count++; |
f8212f97 | 1394 | |
aa80175a | 1395 | if (pkt_is_rsc) { |
f8212f97 AD |
1396 | u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >> |
1397 | IXGBE_RXDADV_NEXTP_SHIFT; | |
1398 | next_buffer = &rx_ring->rx_buffer_info[nextp]; | |
f8212f97 AD |
1399 | } else { |
1400 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
1401 | } | |
1402 | ||
c267fc16 | 1403 | if (!(staterr & IXGBE_RXD_STAT_EOP)) { |
7d637bcc | 1404 | if (ring_is_ps_enabled(rx_ring)) { |
f8212f97 AD |
1405 | rx_buffer_info->skb = next_buffer->skb; |
1406 | rx_buffer_info->dma = next_buffer->dma; | |
1407 | next_buffer->skb = skb; | |
1408 | next_buffer->dma = 0; | |
1409 | } else { | |
1410 | skb->next = next_buffer->skb; | |
1411 | skb->next->prev = skb; | |
1412 | } | |
5b7da515 | 1413 | rx_ring->rx_stats.non_eop_descs++; |
9a799d71 AK |
1414 | goto next_desc; |
1415 | } | |
1416 | ||
aa80175a AD |
1417 | if (skb->prev) { |
1418 | skb = ixgbe_transform_rsc_queue(skb); | |
1419 | /* if we got here without RSC the packet is invalid */ | |
1420 | if (!pkt_is_rsc) { | |
1421 | __pskb_trim(skb, 0); | |
1422 | rx_buffer_info->skb = skb; | |
1423 | goto next_desc; | |
1424 | } | |
1425 | } | |
c267fc16 AD |
1426 | |
1427 | if (ring_is_rsc_enabled(rx_ring)) { | |
1428 | if (IXGBE_RSC_CB(skb)->delay_unmap) { | |
1429 | dma_unmap_single(rx_ring->dev, | |
1430 | IXGBE_RSC_CB(skb)->dma, | |
1431 | rx_ring->rx_buf_len, | |
1432 | DMA_FROM_DEVICE); | |
1433 | IXGBE_RSC_CB(skb)->dma = 0; | |
1434 | IXGBE_RSC_CB(skb)->delay_unmap = false; | |
1435 | } | |
aa80175a AD |
1436 | } |
1437 | if (pkt_is_rsc) { | |
c267fc16 AD |
1438 | if (ring_is_ps_enabled(rx_ring)) |
1439 | rx_ring->rx_stats.rsc_count += | |
aa80175a | 1440 | skb_shinfo(skb)->nr_frags; |
c267fc16 | 1441 | else |
aa80175a AD |
1442 | rx_ring->rx_stats.rsc_count += |
1443 | IXGBE_RSC_CB(skb)->skb_cnt; | |
c267fc16 AD |
1444 | rx_ring->rx_stats.rsc_flush++; |
1445 | } | |
1446 | ||
1447 | /* ERR_MASK will only have valid bits if EOP set */ | |
9a799d71 | 1448 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { |
c267fc16 AD |
1449 | /* trim packet back to size 0 and recycle it */ |
1450 | __pskb_trim(skb, 0); | |
1451 | rx_buffer_info->skb = skb; | |
9a799d71 AK |
1452 | goto next_desc; |
1453 | } | |
1454 | ||
8bae1b2b | 1455 | ixgbe_rx_checksum(adapter, rx_desc, skb); |
d2f4fbe2 AV |
1456 | |
1457 | /* probably a little skewed due to removing CRC */ | |
1458 | total_rx_bytes += skb->len; | |
1459 | total_rx_packets++; | |
1460 | ||
fc77dc3c | 1461 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); |
332d4a7d YZ |
1462 | #ifdef IXGBE_FCOE |
1463 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
3d8fd385 YZ |
1464 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { |
1465 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); | |
1466 | if (!ddp_bytes) | |
332d4a7d | 1467 | goto next_desc; |
3d8fd385 | 1468 | } |
332d4a7d | 1469 | #endif /* IXGBE_FCOE */ |
fdaff1ce | 1470 | ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc); |
9a799d71 AK |
1471 | |
1472 | next_desc: | |
1473 | rx_desc->wb.upper.status_error = 0; | |
1474 | ||
c267fc16 AD |
1475 | (*work_done)++; |
1476 | if (*work_done >= work_to_do) | |
1477 | break; | |
1478 | ||
9a799d71 AK |
1479 | /* return some buffers to hardware, one at a time is too slow */ |
1480 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
fc77dc3c | 1481 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); |
9a799d71 AK |
1482 | cleaned_count = 0; |
1483 | } | |
1484 | ||
1485 | /* use prefetched values */ | |
1486 | rx_desc = next_rxd; | |
9a799d71 | 1487 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
177db6ff MC |
1488 | } |
1489 | ||
9a799d71 AK |
1490 | rx_ring->next_to_clean = i; |
1491 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
1492 | ||
1493 | if (cleaned_count) | |
fc77dc3c | 1494 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); |
9a799d71 | 1495 | |
3d8fd385 YZ |
1496 | #ifdef IXGBE_FCOE |
1497 | /* include DDPed FCoE data */ | |
1498 | if (ddp_bytes > 0) { | |
1499 | unsigned int mss; | |
1500 | ||
fc77dc3c | 1501 | mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) - |
3d8fd385 YZ |
1502 | sizeof(struct fc_frame_header) - |
1503 | sizeof(struct fcoe_crc_eof); | |
1504 | if (mss > 512) | |
1505 | mss &= ~511; | |
1506 | total_rx_bytes += ddp_bytes; | |
1507 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
1508 | } | |
1509 | #endif /* IXGBE_FCOE */ | |
1510 | ||
f494e8fa AV |
1511 | rx_ring->total_packets += total_rx_packets; |
1512 | rx_ring->total_bytes += total_rx_bytes; | |
c267fc16 AD |
1513 | u64_stats_update_begin(&rx_ring->syncp); |
1514 | rx_ring->stats.packets += total_rx_packets; | |
1515 | rx_ring->stats.bytes += total_rx_bytes; | |
1516 | u64_stats_update_end(&rx_ring->syncp); | |
9a799d71 AK |
1517 | } |
1518 | ||
021230d4 | 1519 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
1520 | /** |
1521 | * ixgbe_configure_msix - Configure MSI-X hardware | |
1522 | * @adapter: board private structure | |
1523 | * | |
1524 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
1525 | * interrupts. | |
1526 | **/ | |
1527 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
1528 | { | |
021230d4 | 1529 | struct ixgbe_q_vector *q_vector; |
bf29ee6c | 1530 | int i, q_vectors, v_idx, r_idx; |
021230d4 | 1531 | u32 mask; |
9a799d71 | 1532 | |
021230d4 | 1533 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 1534 | |
4df10466 JB |
1535 | /* |
1536 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
1537 | * corresponding register. |
1538 | */ | |
1539 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
7a921c93 | 1540 | q_vector = adapter->q_vector[v_idx]; |
984b3f57 | 1541 | /* XXX for_each_set_bit(...) */ |
021230d4 | 1542 | r_idx = find_first_bit(q_vector->rxr_idx, |
e8e9f696 | 1543 | adapter->num_rx_queues); |
021230d4 AV |
1544 | |
1545 | for (i = 0; i < q_vector->rxr_count; i++) { | |
bf29ee6c AD |
1546 | u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx; |
1547 | ixgbe_set_ivar(adapter, 0, reg_idx, v_idx); | |
021230d4 | 1548 | r_idx = find_next_bit(q_vector->rxr_idx, |
e8e9f696 JP |
1549 | adapter->num_rx_queues, |
1550 | r_idx + 1); | |
021230d4 AV |
1551 | } |
1552 | r_idx = find_first_bit(q_vector->txr_idx, | |
e8e9f696 | 1553 | adapter->num_tx_queues); |
021230d4 AV |
1554 | |
1555 | for (i = 0; i < q_vector->txr_count; i++) { | |
bf29ee6c AD |
1556 | u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx; |
1557 | ixgbe_set_ivar(adapter, 1, reg_idx, v_idx); | |
021230d4 | 1558 | r_idx = find_next_bit(q_vector->txr_idx, |
e8e9f696 JP |
1559 | adapter->num_tx_queues, |
1560 | r_idx + 1); | |
021230d4 AV |
1561 | } |
1562 | ||
021230d4 | 1563 | if (q_vector->txr_count && !q_vector->rxr_count) |
f7554a2b NS |
1564 | /* tx only */ |
1565 | q_vector->eitr = adapter->tx_eitr_param; | |
509ee935 | 1566 | else if (q_vector->rxr_count) |
f7554a2b NS |
1567 | /* rx or mixed */ |
1568 | q_vector->eitr = adapter->rx_eitr_param; | |
021230d4 | 1569 | |
fe49f04a | 1570 | ixgbe_write_eitr(q_vector); |
b25ebfd2 PW |
1571 | /* If Flow Director is enabled, set interrupt affinity */ |
1572 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
1573 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) { | |
1574 | /* | |
1575 | * Allocate the affinity_hint cpumask, assign the mask | |
1576 | * for this vector, and set our affinity_hint for | |
1577 | * this irq. | |
1578 | */ | |
1579 | if (!alloc_cpumask_var(&q_vector->affinity_mask, | |
1580 | GFP_KERNEL)) | |
1581 | return; | |
1582 | cpumask_set_cpu(v_idx, q_vector->affinity_mask); | |
1583 | irq_set_affinity_hint(adapter->msix_entries[v_idx].vector, | |
1584 | q_vector->affinity_mask); | |
1585 | } | |
9a799d71 AK |
1586 | } |
1587 | ||
bd508178 AD |
1588 | switch (adapter->hw.mac.type) { |
1589 | case ixgbe_mac_82598EB: | |
e8e26350 | 1590 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, |
e8e9f696 | 1591 | v_idx); |
bd508178 AD |
1592 | break; |
1593 | case ixgbe_mac_82599EB: | |
b93a2226 | 1594 | case ixgbe_mac_X540: |
e8e26350 | 1595 | ixgbe_set_ivar(adapter, -1, 1, v_idx); |
bd508178 AD |
1596 | break; |
1597 | ||
1598 | default: | |
1599 | break; | |
1600 | } | |
021230d4 AV |
1601 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1602 | ||
41fb9248 | 1603 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 1604 | mask = IXGBE_EIMS_ENABLE_MASK; |
1cdd1ec8 GR |
1605 | if (adapter->num_vfs) |
1606 | mask &= ~(IXGBE_EIMS_OTHER | | |
1607 | IXGBE_EIMS_MAILBOX | | |
1608 | IXGBE_EIMS_LSC); | |
1609 | else | |
1610 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); | |
021230d4 | 1611 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
1612 | } |
1613 | ||
f494e8fa AV |
1614 | enum latency_range { |
1615 | lowest_latency = 0, | |
1616 | low_latency = 1, | |
1617 | bulk_latency = 2, | |
1618 | latency_invalid = 255 | |
1619 | }; | |
1620 | ||
1621 | /** | |
1622 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
1623 | * @adapter: pointer to adapter | |
1624 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
1625 | * @itr_setting: current throttle rate in ints/second | |
1626 | * @packets: the number of packets during this measurement interval | |
1627 | * @bytes: the number of bytes during this measurement interval | |
1628 | * | |
1629 | * Stores a new ITR value based on packets and byte | |
1630 | * counts during the last interrupt. The advantage of per interrupt | |
1631 | * computation is faster updates and more accurate ITR for the current | |
1632 | * traffic pattern. Constants in this function were computed | |
1633 | * based on theoretical maximum wire speed and thresholds were set based | |
1634 | * on testing data as well as attempting to minimize response time | |
1635 | * while increasing bulk throughput. | |
1636 | * this functionality is controlled by the InterruptThrottleRate module | |
1637 | * parameter (see ixgbe_param.c) | |
1638 | **/ | |
1639 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
e8e9f696 JP |
1640 | u32 eitr, u8 itr_setting, |
1641 | int packets, int bytes) | |
f494e8fa AV |
1642 | { |
1643 | unsigned int retval = itr_setting; | |
1644 | u32 timepassed_us; | |
1645 | u64 bytes_perint; | |
1646 | ||
1647 | if (packets == 0) | |
1648 | goto update_itr_done; | |
1649 | ||
1650 | ||
1651 | /* simple throttlerate management | |
1652 | * 0-20MB/s lowest (100000 ints/s) | |
1653 | * 20-100MB/s low (20000 ints/s) | |
1654 | * 100-1249MB/s bulk (8000 ints/s) | |
1655 | */ | |
1656 | /* what was last interrupt timeslice? */ | |
1657 | timepassed_us = 1000000/eitr; | |
1658 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
1659 | ||
1660 | switch (itr_setting) { | |
1661 | case lowest_latency: | |
1662 | if (bytes_perint > adapter->eitr_low) | |
1663 | retval = low_latency; | |
1664 | break; | |
1665 | case low_latency: | |
1666 | if (bytes_perint > adapter->eitr_high) | |
1667 | retval = bulk_latency; | |
1668 | else if (bytes_perint <= adapter->eitr_low) | |
1669 | retval = lowest_latency; | |
1670 | break; | |
1671 | case bulk_latency: | |
1672 | if (bytes_perint <= adapter->eitr_high) | |
1673 | retval = low_latency; | |
1674 | break; | |
1675 | } | |
1676 | ||
1677 | update_itr_done: | |
1678 | return retval; | |
1679 | } | |
1680 | ||
509ee935 JB |
1681 | /** |
1682 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1683 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1684 | * |
1685 | * This function is made to be called by ethtool and by the driver | |
1686 | * when it needs to update EITR registers at runtime. Hardware | |
1687 | * specific quirks/differences are taken care of here. | |
1688 | */ | |
fe49f04a | 1689 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1690 | { |
fe49f04a | 1691 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1692 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
1693 | int v_idx = q_vector->v_idx; |
1694 | u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr); | |
1695 | ||
bd508178 AD |
1696 | switch (adapter->hw.mac.type) { |
1697 | case ixgbe_mac_82598EB: | |
509ee935 JB |
1698 | /* must write high and low 16 bits to reset counter */ |
1699 | itr_reg |= (itr_reg << 16); | |
bd508178 AD |
1700 | break; |
1701 | case ixgbe_mac_82599EB: | |
b93a2226 | 1702 | case ixgbe_mac_X540: |
f8d1dcaf | 1703 | /* |
b93a2226 | 1704 | * 82599 and X540 can support a value of zero, so allow it for |
f8d1dcaf JB |
1705 | * max interrupt rate, but there is an errata where it can |
1706 | * not be zero with RSC | |
1707 | */ | |
1708 | if (itr_reg == 8 && | |
1709 | !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) | |
1710 | itr_reg = 0; | |
1711 | ||
509ee935 JB |
1712 | /* |
1713 | * set the WDIS bit to not clear the timer bits and cause an | |
1714 | * immediate assertion of the interrupt | |
1715 | */ | |
1716 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
bd508178 AD |
1717 | break; |
1718 | default: | |
1719 | break; | |
509ee935 JB |
1720 | } |
1721 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1722 | } | |
1723 | ||
f494e8fa AV |
1724 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) |
1725 | { | |
1726 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
125601bf | 1727 | int i, r_idx; |
f494e8fa AV |
1728 | u32 new_itr; |
1729 | u8 current_itr, ret_itr; | |
f494e8fa AV |
1730 | |
1731 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1732 | for (i = 0; i < q_vector->txr_count; i++) { | |
125601bf | 1733 | struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx]; |
f494e8fa | 1734 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, |
e8e9f696 JP |
1735 | q_vector->tx_itr, |
1736 | tx_ring->total_packets, | |
1737 | tx_ring->total_bytes); | |
f494e8fa AV |
1738 | /* if the result for this queue would decrease interrupt |
1739 | * rate for this vector then use that result */ | |
30efa5a3 | 1740 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
e8e9f696 | 1741 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 1742 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
e8e9f696 | 1743 | r_idx + 1); |
f494e8fa AV |
1744 | } |
1745 | ||
1746 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1747 | for (i = 0; i < q_vector->rxr_count; i++) { | |
125601bf | 1748 | struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx]; |
f494e8fa | 1749 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, |
e8e9f696 JP |
1750 | q_vector->rx_itr, |
1751 | rx_ring->total_packets, | |
1752 | rx_ring->total_bytes); | |
f494e8fa AV |
1753 | /* if the result for this queue would decrease interrupt |
1754 | * rate for this vector then use that result */ | |
30efa5a3 | 1755 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
e8e9f696 | 1756 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 1757 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
e8e9f696 | 1758 | r_idx + 1); |
f494e8fa AV |
1759 | } |
1760 | ||
30efa5a3 | 1761 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1762 | |
1763 | switch (current_itr) { | |
1764 | /* counts and packets in update_itr are dependent on these numbers */ | |
1765 | case lowest_latency: | |
1766 | new_itr = 100000; | |
1767 | break; | |
1768 | case low_latency: | |
1769 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1770 | break; | |
1771 | case bulk_latency: | |
1772 | default: | |
1773 | new_itr = 8000; | |
1774 | break; | |
1775 | } | |
1776 | ||
1777 | if (new_itr != q_vector->eitr) { | |
fe49f04a | 1778 | /* do an exponential smoothing */ |
125601bf | 1779 | new_itr = ((q_vector->eitr * 9) + new_itr)/10; |
509ee935 JB |
1780 | |
1781 | /* save the algorithm value here, not the smoothed one */ | |
1782 | q_vector->eitr = new_itr; | |
fe49f04a AD |
1783 | |
1784 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 1785 | } |
f494e8fa AV |
1786 | } |
1787 | ||
119fc60a MC |
1788 | /** |
1789 | * ixgbe_check_overtemp_task - worker thread to check over tempurature | |
1790 | * @work: pointer to work_struct containing our data | |
1791 | **/ | |
1792 | static void ixgbe_check_overtemp_task(struct work_struct *work) | |
1793 | { | |
1794 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
1795 | struct ixgbe_adapter, |
1796 | check_overtemp_task); | |
119fc60a MC |
1797 | struct ixgbe_hw *hw = &adapter->hw; |
1798 | u32 eicr = adapter->interrupt_event; | |
1799 | ||
7ca647bd JP |
1800 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) |
1801 | return; | |
1802 | ||
1803 | switch (hw->device_id) { | |
1804 | case IXGBE_DEV_ID_82599_T3_LOM: { | |
1805 | u32 autoneg; | |
1806 | bool link_up = false; | |
1807 | ||
1808 | if (hw->mac.ops.check_link) | |
1809 | hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
1810 | ||
1811 | if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) || | |
1812 | (eicr & IXGBE_EICR_LSC)) | |
1813 | /* Check if this is due to overtemp */ | |
1814 | if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP) | |
1815 | break; | |
1816 | return; | |
1817 | } | |
1818 | default: | |
1819 | if (!(eicr & IXGBE_EICR_GPI_SDP0)) | |
119fc60a | 1820 | return; |
7ca647bd | 1821 | break; |
119fc60a | 1822 | } |
7ca647bd JP |
1823 | e_crit(drv, |
1824 | "Network adapter has been stopped because it has over heated. " | |
1825 | "Restart the computer. If the problem persists, " | |
1826 | "power off the system and replace the adapter\n"); | |
1827 | /* write to clear the interrupt */ | |
1828 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0); | |
119fc60a MC |
1829 | } |
1830 | ||
0befdb3e JB |
1831 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
1832 | { | |
1833 | struct ixgbe_hw *hw = &adapter->hw; | |
1834 | ||
1835 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
1836 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
396e799c | 1837 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
0befdb3e JB |
1838 | /* write to clear the interrupt */ |
1839 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1840 | } | |
1841 | } | |
cf8280ee | 1842 | |
e8e26350 PW |
1843 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
1844 | { | |
1845 | struct ixgbe_hw *hw = &adapter->hw; | |
1846 | ||
73c4b7cd AD |
1847 | if (eicr & IXGBE_EICR_GPI_SDP2) { |
1848 | /* Clear the interrupt */ | |
1849 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
1850 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1851 | schedule_work(&adapter->sfp_config_module_task); | |
1852 | } | |
1853 | ||
e8e26350 PW |
1854 | if (eicr & IXGBE_EICR_GPI_SDP1) { |
1855 | /* Clear the interrupt */ | |
1856 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
73c4b7cd AD |
1857 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1858 | schedule_work(&adapter->multispeed_fiber_task); | |
e8e26350 PW |
1859 | } |
1860 | } | |
1861 | ||
cf8280ee JB |
1862 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
1863 | { | |
1864 | struct ixgbe_hw *hw = &adapter->hw; | |
1865 | ||
1866 | adapter->lsc_int++; | |
1867 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
1868 | adapter->link_check_timeout = jiffies; | |
1869 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1870 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 1871 | IXGBE_WRITE_FLUSH(hw); |
cf8280ee JB |
1872 | schedule_work(&adapter->watchdog_task); |
1873 | } | |
1874 | } | |
1875 | ||
9a799d71 AK |
1876 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
1877 | { | |
1878 | struct net_device *netdev = data; | |
1879 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1880 | struct ixgbe_hw *hw = &adapter->hw; | |
54037505 DS |
1881 | u32 eicr; |
1882 | ||
1883 | /* | |
1884 | * Workaround for Silicon errata. Use clear-by-write instead | |
1885 | * of clear-by-read. Reading with EICS will return the | |
1886 | * interrupt causes without clearing, which later be done | |
1887 | * with the write to EICR. | |
1888 | */ | |
1889 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
1890 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
9a799d71 | 1891 | |
cf8280ee JB |
1892 | if (eicr & IXGBE_EICR_LSC) |
1893 | ixgbe_check_lsc(adapter); | |
d4f80882 | 1894 | |
1cdd1ec8 GR |
1895 | if (eicr & IXGBE_EICR_MAILBOX) |
1896 | ixgbe_msg_task(adapter); | |
1897 | ||
bd508178 AD |
1898 | switch (hw->mac.type) { |
1899 | case ixgbe_mac_82599EB: | |
d994653d DS |
1900 | ixgbe_check_sfp_event(adapter, eicr); |
1901 | if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && | |
1902 | ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) { | |
1903 | adapter->interrupt_event = eicr; | |
1904 | schedule_work(&adapter->check_overtemp_task); | |
1905 | } | |
1906 | /* now fallthrough to handle Flow Director */ | |
b93a2226 | 1907 | case ixgbe_mac_X540: |
c4cf55e5 PWJ |
1908 | /* Handle Flow Director Full threshold interrupt */ |
1909 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
1910 | int i; | |
1911 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR); | |
1912 | /* Disable transmits before FDIR Re-initialization */ | |
1913 | netif_tx_stop_all_queues(netdev); | |
1914 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1915 | struct ixgbe_ring *tx_ring = | |
e8e9f696 | 1916 | adapter->tx_ring[i]; |
7d637bcc AD |
1917 | if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, |
1918 | &tx_ring->state)) | |
c4cf55e5 PWJ |
1919 | schedule_work(&adapter->fdir_reinit_task); |
1920 | } | |
1921 | } | |
bd508178 AD |
1922 | break; |
1923 | default: | |
1924 | break; | |
c4cf55e5 | 1925 | } |
bd508178 AD |
1926 | |
1927 | ixgbe_check_fan_failure(adapter, eicr); | |
1928 | ||
d4f80882 AV |
1929 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1930 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
1931 | |
1932 | return IRQ_HANDLED; | |
1933 | } | |
1934 | ||
fe49f04a AD |
1935 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
1936 | u64 qmask) | |
1937 | { | |
1938 | u32 mask; | |
bd508178 | 1939 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 1940 | |
bd508178 AD |
1941 | switch (hw->mac.type) { |
1942 | case ixgbe_mac_82598EB: | |
fe49f04a | 1943 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
1944 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); |
1945 | break; | |
1946 | case ixgbe_mac_82599EB: | |
b93a2226 | 1947 | case ixgbe_mac_X540: |
fe49f04a | 1948 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
1949 | if (mask) |
1950 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | |
fe49f04a | 1951 | mask = (qmask >> 32); |
bd508178 AD |
1952 | if (mask) |
1953 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | |
1954 | break; | |
1955 | default: | |
1956 | break; | |
fe49f04a AD |
1957 | } |
1958 | /* skip the flush */ | |
1959 | } | |
1960 | ||
1961 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
e8e9f696 | 1962 | u64 qmask) |
fe49f04a AD |
1963 | { |
1964 | u32 mask; | |
bd508178 | 1965 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 1966 | |
bd508178 AD |
1967 | switch (hw->mac.type) { |
1968 | case ixgbe_mac_82598EB: | |
fe49f04a | 1969 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
1970 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); |
1971 | break; | |
1972 | case ixgbe_mac_82599EB: | |
b93a2226 | 1973 | case ixgbe_mac_X540: |
fe49f04a | 1974 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
1975 | if (mask) |
1976 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); | |
fe49f04a | 1977 | mask = (qmask >> 32); |
bd508178 AD |
1978 | if (mask) |
1979 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); | |
1980 | break; | |
1981 | default: | |
1982 | break; | |
fe49f04a AD |
1983 | } |
1984 | /* skip the flush */ | |
1985 | } | |
1986 | ||
9a799d71 AK |
1987 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) |
1988 | { | |
021230d4 AV |
1989 | struct ixgbe_q_vector *q_vector = data; |
1990 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1991 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
1992 | int i, r_idx; |
1993 | ||
1994 | if (!q_vector->txr_count) | |
1995 | return IRQ_HANDLED; | |
1996 | ||
1997 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1998 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 1999 | tx_ring = adapter->tx_ring[r_idx]; |
3a581073 JB |
2000 | tx_ring->total_bytes = 0; |
2001 | tx_ring->total_packets = 0; | |
021230d4 | 2002 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
e8e9f696 | 2003 | r_idx + 1); |
021230d4 | 2004 | } |
9a799d71 | 2005 | |
9b471446 | 2006 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 AD |
2007 | napi_schedule(&q_vector->napi); |
2008 | ||
9a799d71 AK |
2009 | return IRQ_HANDLED; |
2010 | } | |
2011 | ||
021230d4 AV |
2012 | /** |
2013 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
2014 | * @irq: unused | |
2015 | * @data: pointer to our q_vector struct for this interrupt vector | |
2016 | **/ | |
9a799d71 AK |
2017 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
2018 | { | |
021230d4 AV |
2019 | struct ixgbe_q_vector *q_vector = data; |
2020 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 2021 | struct ixgbe_ring *rx_ring; |
021230d4 | 2022 | int r_idx; |
30efa5a3 | 2023 | int i; |
021230d4 | 2024 | |
33cf09c9 AD |
2025 | #ifdef CONFIG_IXGBE_DCA |
2026 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2027 | ixgbe_update_dca(q_vector); | |
2028 | #endif | |
2029 | ||
021230d4 | 2030 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
33cf09c9 | 2031 | for (i = 0; i < q_vector->rxr_count; i++) { |
4a0b9ca0 | 2032 | rx_ring = adapter->rx_ring[r_idx]; |
30efa5a3 JB |
2033 | rx_ring->total_bytes = 0; |
2034 | rx_ring->total_packets = 0; | |
2035 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
e8e9f696 | 2036 | r_idx + 1); |
30efa5a3 JB |
2037 | } |
2038 | ||
021230d4 AV |
2039 | if (!q_vector->rxr_count) |
2040 | return IRQ_HANDLED; | |
2041 | ||
9b471446 | 2042 | /* EIAM disabled interrupts (on this vector) for us */ |
288379f0 | 2043 | napi_schedule(&q_vector->napi); |
021230d4 AV |
2044 | |
2045 | return IRQ_HANDLED; | |
2046 | } | |
2047 | ||
2048 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
2049 | { | |
91281fd3 AD |
2050 | struct ixgbe_q_vector *q_vector = data; |
2051 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
2052 | struct ixgbe_ring *ring; | |
2053 | int r_idx; | |
2054 | int i; | |
2055 | ||
2056 | if (!q_vector->txr_count && !q_vector->rxr_count) | |
2057 | return IRQ_HANDLED; | |
2058 | ||
2059 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
2060 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 2061 | ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
2062 | ring->total_bytes = 0; |
2063 | ring->total_packets = 0; | |
2064 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
e8e9f696 | 2065 | r_idx + 1); |
91281fd3 AD |
2066 | } |
2067 | ||
2068 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
2069 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 2070 | ring = adapter->rx_ring[r_idx]; |
91281fd3 AD |
2071 | ring->total_bytes = 0; |
2072 | ring->total_packets = 0; | |
2073 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
e8e9f696 | 2074 | r_idx + 1); |
91281fd3 AD |
2075 | } |
2076 | ||
9b471446 | 2077 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 2078 | napi_schedule(&q_vector->napi); |
9a799d71 | 2079 | |
9a799d71 AK |
2080 | return IRQ_HANDLED; |
2081 | } | |
2082 | ||
021230d4 AV |
2083 | /** |
2084 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
2085 | * @napi: napi struct with our devices info in it | |
2086 | * @budget: amount of work driver is allowed to do this pass, in packets | |
2087 | * | |
f0848276 JB |
2088 | * This function is optimized for cleaning one queue only on a single |
2089 | * q_vector!!! | |
021230d4 | 2090 | **/ |
9a799d71 AK |
2091 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
2092 | { | |
021230d4 | 2093 | struct ixgbe_q_vector *q_vector = |
e8e9f696 | 2094 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 2095 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 2096 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 2097 | int work_done = 0; |
021230d4 | 2098 | long r_idx; |
9a799d71 | 2099 | |
5dd2d332 | 2100 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 2101 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
33cf09c9 | 2102 | ixgbe_update_dca(q_vector); |
bd0362dd | 2103 | #endif |
9a799d71 | 2104 | |
33cf09c9 AD |
2105 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
2106 | rx_ring = adapter->rx_ring[r_idx]; | |
2107 | ||
78b6f4ce | 2108 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
9a799d71 | 2109 | |
021230d4 AV |
2110 | /* If all Rx work done, exit the polling mode */ |
2111 | if (work_done < budget) { | |
288379f0 | 2112 | napi_complete(napi); |
f7554a2b | 2113 | if (adapter->rx_itr_setting & 1) |
f494e8fa | 2114 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 2115 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
fe49f04a | 2116 | ixgbe_irq_enable_queues(adapter, |
e8e9f696 | 2117 | ((u64)1 << q_vector->v_idx)); |
9a799d71 AK |
2118 | } |
2119 | ||
2120 | return work_done; | |
2121 | } | |
2122 | ||
f0848276 | 2123 | /** |
91281fd3 | 2124 | * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine |
f0848276 JB |
2125 | * @napi: napi struct with our devices info in it |
2126 | * @budget: amount of work driver is allowed to do this pass, in packets | |
2127 | * | |
2128 | * This function will clean more than one rx queue associated with a | |
2129 | * q_vector. | |
2130 | **/ | |
91281fd3 | 2131 | static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget) |
f0848276 JB |
2132 | { |
2133 | struct ixgbe_q_vector *q_vector = | |
e8e9f696 | 2134 | container_of(napi, struct ixgbe_q_vector, napi); |
f0848276 | 2135 | struct ixgbe_adapter *adapter = q_vector->adapter; |
91281fd3 | 2136 | struct ixgbe_ring *ring = NULL; |
f0848276 JB |
2137 | int work_done = 0, i; |
2138 | long r_idx; | |
91281fd3 AD |
2139 | bool tx_clean_complete = true; |
2140 | ||
33cf09c9 AD |
2141 | #ifdef CONFIG_IXGBE_DCA |
2142 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2143 | ixgbe_update_dca(q_vector); | |
2144 | #endif | |
2145 | ||
91281fd3 AD |
2146 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); |
2147 | for (i = 0; i < q_vector->txr_count; i++) { | |
4a0b9ca0 | 2148 | ring = adapter->tx_ring[r_idx]; |
91281fd3 AD |
2149 | tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring); |
2150 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
e8e9f696 | 2151 | r_idx + 1); |
91281fd3 | 2152 | } |
f0848276 JB |
2153 | |
2154 | /* attempt to distribute budget to each queue fairly, but don't allow | |
2155 | * the budget to go below 1 because we'll exit polling */ | |
2156 | budget /= (q_vector->rxr_count ?: 1); | |
2157 | budget = max(budget, 1); | |
2158 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
2159 | for (i = 0; i < q_vector->rxr_count; i++) { | |
4a0b9ca0 | 2160 | ring = adapter->rx_ring[r_idx]; |
91281fd3 | 2161 | ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget); |
f0848276 | 2162 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
e8e9f696 | 2163 | r_idx + 1); |
f0848276 JB |
2164 | } |
2165 | ||
2166 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
4a0b9ca0 | 2167 | ring = adapter->rx_ring[r_idx]; |
f0848276 | 2168 | /* If all Rx work done, exit the polling mode */ |
7f821875 | 2169 | if (work_done < budget) { |
288379f0 | 2170 | napi_complete(napi); |
f7554a2b | 2171 | if (adapter->rx_itr_setting & 1) |
f0848276 JB |
2172 | ixgbe_set_itr_msix(q_vector); |
2173 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
fe49f04a | 2174 | ixgbe_irq_enable_queues(adapter, |
e8e9f696 | 2175 | ((u64)1 << q_vector->v_idx)); |
f0848276 JB |
2176 | return 0; |
2177 | } | |
2178 | ||
2179 | return work_done; | |
2180 | } | |
91281fd3 AD |
2181 | |
2182 | /** | |
2183 | * ixgbe_clean_txonly - msix (aka one shot) tx clean routine | |
2184 | * @napi: napi struct with our devices info in it | |
2185 | * @budget: amount of work driver is allowed to do this pass, in packets | |
2186 | * | |
2187 | * This function is optimized for cleaning one queue only on a single | |
2188 | * q_vector!!! | |
2189 | **/ | |
2190 | static int ixgbe_clean_txonly(struct napi_struct *napi, int budget) | |
2191 | { | |
2192 | struct ixgbe_q_vector *q_vector = | |
e8e9f696 | 2193 | container_of(napi, struct ixgbe_q_vector, napi); |
91281fd3 AD |
2194 | struct ixgbe_adapter *adapter = q_vector->adapter; |
2195 | struct ixgbe_ring *tx_ring = NULL; | |
2196 | int work_done = 0; | |
2197 | long r_idx; | |
2198 | ||
91281fd3 AD |
2199 | #ifdef CONFIG_IXGBE_DCA |
2200 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
33cf09c9 | 2201 | ixgbe_update_dca(q_vector); |
91281fd3 AD |
2202 | #endif |
2203 | ||
33cf09c9 AD |
2204 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); |
2205 | tx_ring = adapter->tx_ring[r_idx]; | |
2206 | ||
91281fd3 AD |
2207 | if (!ixgbe_clean_tx_irq(q_vector, tx_ring)) |
2208 | work_done = budget; | |
2209 | ||
f7554a2b | 2210 | /* If all Tx work done, exit the polling mode */ |
91281fd3 AD |
2211 | if (work_done < budget) { |
2212 | napi_complete(napi); | |
f7554a2b | 2213 | if (adapter->tx_itr_setting & 1) |
91281fd3 AD |
2214 | ixgbe_set_itr_msix(q_vector); |
2215 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
e8e9f696 JP |
2216 | ixgbe_irq_enable_queues(adapter, |
2217 | ((u64)1 << q_vector->v_idx)); | |
91281fd3 AD |
2218 | } |
2219 | ||
2220 | return work_done; | |
2221 | } | |
2222 | ||
021230d4 | 2223 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
e8e9f696 | 2224 | int r_idx) |
021230d4 | 2225 | { |
7a921c93 | 2226 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
2274543f | 2227 | struct ixgbe_ring *rx_ring = a->rx_ring[r_idx]; |
7a921c93 AD |
2228 | |
2229 | set_bit(r_idx, q_vector->rxr_idx); | |
2230 | q_vector->rxr_count++; | |
2274543f | 2231 | rx_ring->q_vector = q_vector; |
021230d4 AV |
2232 | } |
2233 | ||
2234 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
e8e9f696 | 2235 | int t_idx) |
021230d4 | 2236 | { |
7a921c93 | 2237 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
2274543f | 2238 | struct ixgbe_ring *tx_ring = a->tx_ring[t_idx]; |
7a921c93 AD |
2239 | |
2240 | set_bit(t_idx, q_vector->txr_idx); | |
2241 | q_vector->txr_count++; | |
2274543f | 2242 | tx_ring->q_vector = q_vector; |
021230d4 AV |
2243 | } |
2244 | ||
9a799d71 | 2245 | /** |
021230d4 AV |
2246 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
2247 | * @adapter: board private structure to initialize | |
9a799d71 | 2248 | * |
021230d4 AV |
2249 | * This function maps descriptor rings to the queue-specific vectors |
2250 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
2251 | * one vector per ring/queue, but on a constrained vector budget, we | |
2252 | * group the rings as "efficiently" as possible. You would add new | |
2253 | * mapping configurations in here. | |
9a799d71 | 2254 | **/ |
d0759ebb | 2255 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter) |
021230d4 | 2256 | { |
d0759ebb | 2257 | int q_vectors; |
021230d4 AV |
2258 | int v_start = 0; |
2259 | int rxr_idx = 0, txr_idx = 0; | |
2260 | int rxr_remaining = adapter->num_rx_queues; | |
2261 | int txr_remaining = adapter->num_tx_queues; | |
2262 | int i, j; | |
2263 | int rqpv, tqpv; | |
2264 | int err = 0; | |
2265 | ||
2266 | /* No mapping required if MSI-X is disabled. */ | |
2267 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2268 | goto out; | |
9a799d71 | 2269 | |
d0759ebb AD |
2270 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
2271 | ||
021230d4 AV |
2272 | /* |
2273 | * The ideal configuration... | |
2274 | * We have enough vectors to map one per queue. | |
2275 | */ | |
d0759ebb | 2276 | if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) { |
021230d4 AV |
2277 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) |
2278 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 2279 | |
021230d4 AV |
2280 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
2281 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 2282 | |
9a799d71 | 2283 | goto out; |
021230d4 | 2284 | } |
9a799d71 | 2285 | |
021230d4 AV |
2286 | /* |
2287 | * If we don't have enough vectors for a 1-to-1 | |
2288 | * mapping, we'll have to group them so there are | |
2289 | * multiple queues per vector. | |
2290 | */ | |
2291 | /* Re-adjusting *qpv takes care of the remainder. */ | |
d0759ebb AD |
2292 | for (i = v_start; i < q_vectors; i++) { |
2293 | rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i); | |
021230d4 AV |
2294 | for (j = 0; j < rqpv; j++) { |
2295 | map_vector_to_rxq(adapter, i, rxr_idx); | |
2296 | rxr_idx++; | |
2297 | rxr_remaining--; | |
2298 | } | |
d0759ebb | 2299 | tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i); |
021230d4 AV |
2300 | for (j = 0; j < tqpv; j++) { |
2301 | map_vector_to_txq(adapter, i, txr_idx); | |
2302 | txr_idx++; | |
2303 | txr_remaining--; | |
9a799d71 | 2304 | } |
9a799d71 | 2305 | } |
021230d4 AV |
2306 | out: |
2307 | return err; | |
2308 | } | |
2309 | ||
2310 | /** | |
2311 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
2312 | * @adapter: board private structure | |
2313 | * | |
2314 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
2315 | * interrupts from the kernel. | |
2316 | **/ | |
2317 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
2318 | { | |
2319 | struct net_device *netdev = adapter->netdev; | |
2320 | irqreturn_t (*handler)(int, void *); | |
2321 | int i, vector, q_vectors, err; | |
e8e9f696 | 2322 | int ri = 0, ti = 0; |
021230d4 AV |
2323 | |
2324 | /* Decrement for Other and TCP Timer vectors */ | |
2325 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2326 | ||
d0759ebb | 2327 | err = ixgbe_map_rings_to_vectors(adapter); |
021230d4 | 2328 | if (err) |
d0759ebb | 2329 | return err; |
021230d4 | 2330 | |
d0759ebb AD |
2331 | #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \ |
2332 | ? &ixgbe_msix_clean_many : \ | |
2333 | (_v)->rxr_count ? &ixgbe_msix_clean_rx : \ | |
2334 | (_v)->txr_count ? &ixgbe_msix_clean_tx : \ | |
2335 | NULL) | |
021230d4 | 2336 | for (vector = 0; vector < q_vectors; vector++) { |
d0759ebb AD |
2337 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; |
2338 | handler = SET_HANDLER(q_vector); | |
cb13fc20 | 2339 | |
e8e9f696 | 2340 | if (handler == &ixgbe_msix_clean_rx) { |
9fe93afd DS |
2341 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
2342 | "%s-%s-%d", netdev->name, "rx", ri++); | |
e8e9f696 | 2343 | } else if (handler == &ixgbe_msix_clean_tx) { |
9fe93afd DS |
2344 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
2345 | "%s-%s-%d", netdev->name, "tx", ti++); | |
d0759ebb | 2346 | } else if (handler == &ixgbe_msix_clean_many) { |
9fe93afd DS |
2347 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
2348 | "%s-%s-%d", netdev->name, "TxRx", ri++); | |
32aa77a4 | 2349 | ti++; |
d0759ebb AD |
2350 | } else { |
2351 | /* skip this unused q_vector */ | |
2352 | continue; | |
32aa77a4 | 2353 | } |
021230d4 | 2354 | err = request_irq(adapter->msix_entries[vector].vector, |
d0759ebb AD |
2355 | handler, 0, q_vector->name, |
2356 | q_vector); | |
9a799d71 | 2357 | if (err) { |
396e799c | 2358 | e_err(probe, "request_irq failed for MSIX interrupt " |
849c4542 | 2359 | "Error: %d\n", err); |
021230d4 | 2360 | goto free_queue_irqs; |
9a799d71 | 2361 | } |
9a799d71 AK |
2362 | } |
2363 | ||
d0759ebb | 2364 | sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name); |
021230d4 | 2365 | err = request_irq(adapter->msix_entries[vector].vector, |
d0759ebb | 2366 | ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev); |
9a799d71 | 2367 | if (err) { |
396e799c | 2368 | e_err(probe, "request_irq for msix_lsc failed: %d\n", err); |
021230d4 | 2369 | goto free_queue_irqs; |
9a799d71 AK |
2370 | } |
2371 | ||
9a799d71 AK |
2372 | return 0; |
2373 | ||
021230d4 AV |
2374 | free_queue_irqs: |
2375 | for (i = vector - 1; i >= 0; i--) | |
2376 | free_irq(adapter->msix_entries[--vector].vector, | |
e8e9f696 | 2377 | adapter->q_vector[i]); |
021230d4 AV |
2378 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
2379 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
2380 | kfree(adapter->msix_entries); |
2381 | adapter->msix_entries = NULL; | |
9a799d71 AK |
2382 | return err; |
2383 | } | |
2384 | ||
f494e8fa AV |
2385 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
2386 | { | |
7a921c93 | 2387 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
4a0b9ca0 PW |
2388 | struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; |
2389 | struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; | |
125601bf AD |
2390 | u32 new_itr = q_vector->eitr; |
2391 | u8 current_itr; | |
f494e8fa | 2392 | |
30efa5a3 | 2393 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
e8e9f696 JP |
2394 | q_vector->tx_itr, |
2395 | tx_ring->total_packets, | |
2396 | tx_ring->total_bytes); | |
30efa5a3 | 2397 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
e8e9f696 JP |
2398 | q_vector->rx_itr, |
2399 | rx_ring->total_packets, | |
2400 | rx_ring->total_bytes); | |
f494e8fa | 2401 | |
30efa5a3 | 2402 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
2403 | |
2404 | switch (current_itr) { | |
2405 | /* counts and packets in update_itr are dependent on these numbers */ | |
2406 | case lowest_latency: | |
2407 | new_itr = 100000; | |
2408 | break; | |
2409 | case low_latency: | |
2410 | new_itr = 20000; /* aka hwitr = ~200 */ | |
2411 | break; | |
2412 | case bulk_latency: | |
2413 | new_itr = 8000; | |
2414 | break; | |
2415 | default: | |
2416 | break; | |
2417 | } | |
2418 | ||
2419 | if (new_itr != q_vector->eitr) { | |
fe49f04a | 2420 | /* do an exponential smoothing */ |
125601bf | 2421 | new_itr = ((q_vector->eitr * 9) + new_itr)/10; |
509ee935 | 2422 | |
125601bf | 2423 | /* save the algorithm value here */ |
509ee935 | 2424 | q_vector->eitr = new_itr; |
fe49f04a AD |
2425 | |
2426 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 2427 | } |
f494e8fa AV |
2428 | } |
2429 | ||
79aefa45 AD |
2430 | /** |
2431 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
2432 | * @adapter: board private structure | |
2433 | **/ | |
6af3b9eb ET |
2434 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, |
2435 | bool flush) | |
79aefa45 AD |
2436 | { |
2437 | u32 mask; | |
835462fc NS |
2438 | |
2439 | mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); | |
119fc60a MC |
2440 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
2441 | mask |= IXGBE_EIMS_GPI_SDP0; | |
6ab33d51 DM |
2442 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
2443 | mask |= IXGBE_EIMS_GPI_SDP1; | |
bd508178 AD |
2444 | switch (adapter->hw.mac.type) { |
2445 | case ixgbe_mac_82599EB: | |
b93a2226 | 2446 | case ixgbe_mac_X540: |
2a41ff81 | 2447 | mask |= IXGBE_EIMS_ECC; |
e8e26350 PW |
2448 | mask |= IXGBE_EIMS_GPI_SDP1; |
2449 | mask |= IXGBE_EIMS_GPI_SDP2; | |
1cdd1ec8 GR |
2450 | if (adapter->num_vfs) |
2451 | mask |= IXGBE_EIMS_MAILBOX; | |
bd508178 AD |
2452 | break; |
2453 | default: | |
2454 | break; | |
e8e26350 | 2455 | } |
c4cf55e5 PWJ |
2456 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
2457 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
2458 | mask |= IXGBE_EIMS_FLOW_DIR; | |
e8e26350 | 2459 | |
79aefa45 | 2460 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
6af3b9eb ET |
2461 | if (queues) |
2462 | ixgbe_irq_enable_queues(adapter, ~0); | |
2463 | if (flush) | |
2464 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1cdd1ec8 GR |
2465 | |
2466 | if (adapter->num_vfs > 32) { | |
2467 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
2468 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
2469 | } | |
79aefa45 | 2470 | } |
021230d4 | 2471 | |
9a799d71 | 2472 | /** |
021230d4 | 2473 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
2474 | * @irq: interrupt number |
2475 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
2476 | **/ |
2477 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
2478 | { | |
2479 | struct net_device *netdev = data; | |
2480 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2481 | struct ixgbe_hw *hw = &adapter->hw; | |
7a921c93 | 2482 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
2483 | u32 eicr; |
2484 | ||
54037505 | 2485 | /* |
6af3b9eb | 2486 | * Workaround for silicon errata on 82598. Mask the interrupts |
54037505 DS |
2487 | * before the read of EICR. |
2488 | */ | |
2489 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
2490 | ||
021230d4 AV |
2491 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
2492 | * therefore no explict interrupt disable is necessary */ | |
2493 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e | 2494 | if (!eicr) { |
6af3b9eb ET |
2495 | /* |
2496 | * shared interrupt alert! | |
f47cf66e | 2497 | * make sure interrupts are enabled because the read will |
6af3b9eb ET |
2498 | * have disabled interrupts due to EIAM |
2499 | * finish the workaround of silicon errata on 82598. Unmask | |
2500 | * the interrupt that we masked before the EICR read. | |
2501 | */ | |
2502 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2503 | ixgbe_irq_enable(adapter, true, true); | |
9a799d71 | 2504 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 2505 | } |
9a799d71 | 2506 | |
cf8280ee JB |
2507 | if (eicr & IXGBE_EICR_LSC) |
2508 | ixgbe_check_lsc(adapter); | |
021230d4 | 2509 | |
bd508178 AD |
2510 | switch (hw->mac.type) { |
2511 | case ixgbe_mac_82599EB: | |
e8e26350 | 2512 | ixgbe_check_sfp_event(adapter, eicr); |
bd508178 AD |
2513 | if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
2514 | ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) { | |
2515 | adapter->interrupt_event = eicr; | |
2516 | schedule_work(&adapter->check_overtemp_task); | |
2517 | } | |
2518 | break; | |
2519 | default: | |
2520 | break; | |
2521 | } | |
e8e26350 | 2522 | |
0befdb3e JB |
2523 | ixgbe_check_fan_failure(adapter, eicr); |
2524 | ||
7a921c93 | 2525 | if (napi_schedule_prep(&(q_vector->napi))) { |
4a0b9ca0 PW |
2526 | adapter->tx_ring[0]->total_packets = 0; |
2527 | adapter->tx_ring[0]->total_bytes = 0; | |
2528 | adapter->rx_ring[0]->total_packets = 0; | |
2529 | adapter->rx_ring[0]->total_bytes = 0; | |
021230d4 | 2530 | /* would disable interrupts here but EIAM disabled it */ |
7a921c93 | 2531 | __napi_schedule(&(q_vector->napi)); |
9a799d71 AK |
2532 | } |
2533 | ||
6af3b9eb ET |
2534 | /* |
2535 | * re-enable link(maybe) and non-queue interrupts, no flush. | |
2536 | * ixgbe_poll will re-enable the queue interrupts | |
2537 | */ | |
2538 | ||
2539 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2540 | ixgbe_irq_enable(adapter, false, false); | |
2541 | ||
9a799d71 AK |
2542 | return IRQ_HANDLED; |
2543 | } | |
2544 | ||
021230d4 AV |
2545 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
2546 | { | |
2547 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2548 | ||
2549 | for (i = 0; i < q_vectors; i++) { | |
7a921c93 | 2550 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; |
021230d4 AV |
2551 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); |
2552 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
2553 | q_vector->rxr_count = 0; | |
2554 | q_vector->txr_count = 0; | |
2555 | } | |
2556 | } | |
2557 | ||
9a799d71 AK |
2558 | /** |
2559 | * ixgbe_request_irq - initialize interrupts | |
2560 | * @adapter: board private structure | |
2561 | * | |
2562 | * Attempts to configure interrupts using the best available | |
2563 | * capabilities of the hardware and kernel. | |
2564 | **/ | |
021230d4 | 2565 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2566 | { |
2567 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 2568 | int err; |
9a799d71 | 2569 | |
021230d4 AV |
2570 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2571 | err = ixgbe_request_msix_irqs(adapter); | |
2572 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
a0607fd3 | 2573 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
e8e9f696 | 2574 | netdev->name, netdev); |
021230d4 | 2575 | } else { |
a0607fd3 | 2576 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
e8e9f696 | 2577 | netdev->name, netdev); |
9a799d71 AK |
2578 | } |
2579 | ||
9a799d71 | 2580 | if (err) |
396e799c | 2581 | e_err(probe, "request_irq failed, Error %d\n", err); |
9a799d71 | 2582 | |
9a799d71 AK |
2583 | return err; |
2584 | } | |
2585 | ||
2586 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
2587 | { | |
2588 | struct net_device *netdev = adapter->netdev; | |
2589 | ||
2590 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 2591 | int i, q_vectors; |
9a799d71 | 2592 | |
021230d4 AV |
2593 | q_vectors = adapter->num_msix_vectors; |
2594 | ||
2595 | i = q_vectors - 1; | |
9a799d71 | 2596 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 2597 | |
021230d4 AV |
2598 | i--; |
2599 | for (; i >= 0; i--) { | |
2600 | free_irq(adapter->msix_entries[i].vector, | |
e8e9f696 | 2601 | adapter->q_vector[i]); |
021230d4 AV |
2602 | } |
2603 | ||
2604 | ixgbe_reset_q_vectors(adapter); | |
2605 | } else { | |
2606 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
2607 | } |
2608 | } | |
2609 | ||
22d5a71b JB |
2610 | /** |
2611 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
2612 | * @adapter: board private structure | |
2613 | **/ | |
2614 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
2615 | { | |
bd508178 AD |
2616 | switch (adapter->hw.mac.type) { |
2617 | case ixgbe_mac_82598EB: | |
835462fc | 2618 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); |
bd508178 AD |
2619 | break; |
2620 | case ixgbe_mac_82599EB: | |
b93a2226 | 2621 | case ixgbe_mac_X540: |
835462fc NS |
2622 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); |
2623 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 2624 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
1cdd1ec8 GR |
2625 | if (adapter->num_vfs > 32) |
2626 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
bd508178 AD |
2627 | break; |
2628 | default: | |
2629 | break; | |
22d5a71b JB |
2630 | } |
2631 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
2632 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
2633 | int i; | |
2634 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
2635 | synchronize_irq(adapter->msix_entries[i].vector); | |
2636 | } else { | |
2637 | synchronize_irq(adapter->pdev->irq); | |
2638 | } | |
2639 | } | |
2640 | ||
9a799d71 AK |
2641 | /** |
2642 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
2643 | * | |
2644 | **/ | |
2645 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
2646 | { | |
9a799d71 AK |
2647 | struct ixgbe_hw *hw = &adapter->hw; |
2648 | ||
021230d4 | 2649 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
e8e9f696 | 2650 | EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param)); |
9a799d71 | 2651 | |
e8e26350 PW |
2652 | ixgbe_set_ivar(adapter, 0, 0, 0); |
2653 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 AV |
2654 | |
2655 | map_vector_to_rxq(adapter, 0, 0); | |
2656 | map_vector_to_txq(adapter, 0, 0); | |
2657 | ||
396e799c | 2658 | e_info(hw, "Legacy interrupt IVAR setup done\n"); |
9a799d71 AK |
2659 | } |
2660 | ||
43e69bf0 AD |
2661 | /** |
2662 | * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset | |
2663 | * @adapter: board private structure | |
2664 | * @ring: structure containing ring specific data | |
2665 | * | |
2666 | * Configure the Tx descriptor ring after a reset. | |
2667 | **/ | |
84418e3b AD |
2668 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, |
2669 | struct ixgbe_ring *ring) | |
43e69bf0 AD |
2670 | { |
2671 | struct ixgbe_hw *hw = &adapter->hw; | |
2672 | u64 tdba = ring->dma; | |
2f1860b8 AD |
2673 | int wait_loop = 10; |
2674 | u32 txdctl; | |
bf29ee6c | 2675 | u8 reg_idx = ring->reg_idx; |
43e69bf0 | 2676 | |
2f1860b8 AD |
2677 | /* disable queue to avoid issues while updating state */ |
2678 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); | |
2679 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), | |
2680 | txdctl & ~IXGBE_TXDCTL_ENABLE); | |
2681 | IXGBE_WRITE_FLUSH(hw); | |
2682 | ||
43e69bf0 | 2683 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), |
e8e9f696 | 2684 | (tdba & DMA_BIT_MASK(32))); |
43e69bf0 AD |
2685 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); |
2686 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), | |
2687 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
2688 | IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); | |
2689 | IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); | |
84ea2591 | 2690 | ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx); |
43e69bf0 | 2691 | |
2f1860b8 AD |
2692 | /* configure fetching thresholds */ |
2693 | if (adapter->rx_itr_setting == 0) { | |
2694 | /* cannot set wthresh when itr==0 */ | |
2695 | txdctl &= ~0x007F0000; | |
2696 | } else { | |
2697 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ | |
2698 | txdctl |= (8 << 16); | |
2699 | } | |
2700 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
2701 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
2702 | txdctl |= 32; | |
2703 | } | |
2704 | ||
2705 | /* reinitialize flowdirector state */ | |
ee9e0f0b AD |
2706 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2707 | adapter->atr_sample_rate) { | |
2708 | ring->atr_sample_rate = adapter->atr_sample_rate; | |
2709 | ring->atr_count = 0; | |
2710 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); | |
2711 | } else { | |
2712 | ring->atr_sample_rate = 0; | |
2713 | } | |
2f1860b8 | 2714 | |
c84d324c JF |
2715 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); |
2716 | ||
2f1860b8 AD |
2717 | /* enable queue */ |
2718 | txdctl |= IXGBE_TXDCTL_ENABLE; | |
2719 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); | |
2720 | ||
2721 | /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2722 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2723 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2724 | return; | |
2725 | ||
2726 | /* poll to verify queue is enabled */ | |
2727 | do { | |
2728 | msleep(1); | |
2729 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); | |
2730 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
2731 | if (!wait_loop) | |
2732 | e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); | |
43e69bf0 AD |
2733 | } |
2734 | ||
120ff942 AD |
2735 | static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) |
2736 | { | |
2737 | struct ixgbe_hw *hw = &adapter->hw; | |
2738 | u32 rttdcs; | |
2739 | u32 mask; | |
2740 | ||
2741 | if (hw->mac.type == ixgbe_mac_82598EB) | |
2742 | return; | |
2743 | ||
2744 | /* disable the arbiter while setting MTQC */ | |
2745 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
2746 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
2747 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2748 | ||
2749 | /* set transmit pool layout */ | |
2750 | mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED); | |
2751 | switch (adapter->flags & mask) { | |
2752 | ||
2753 | case (IXGBE_FLAG_SRIOV_ENABLED): | |
2754 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2755 | (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF)); | |
2756 | break; | |
2757 | ||
2758 | case (IXGBE_FLAG_DCB_ENABLED): | |
2759 | /* We enable 8 traffic classes, DCB only */ | |
2760 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2761 | (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ)); | |
2762 | break; | |
2763 | ||
2764 | default: | |
2765 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB); | |
2766 | break; | |
2767 | } | |
2768 | ||
2769 | /* re-enable the arbiter */ | |
2770 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2771 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2772 | } | |
2773 | ||
9a799d71 | 2774 | /** |
3a581073 | 2775 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
2776 | * @adapter: board private structure |
2777 | * | |
2778 | * Configure the Tx unit of the MAC after a reset. | |
2779 | **/ | |
2780 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
2781 | { | |
2f1860b8 AD |
2782 | struct ixgbe_hw *hw = &adapter->hw; |
2783 | u32 dmatxctl; | |
43e69bf0 | 2784 | u32 i; |
9a799d71 | 2785 | |
2f1860b8 AD |
2786 | ixgbe_setup_mtqc(adapter); |
2787 | ||
2788 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
2789 | /* DMATXCTL.EN must be before Tx queues are enabled */ | |
2790 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2791 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2792 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2793 | } | |
2794 | ||
9a799d71 | 2795 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
43e69bf0 AD |
2796 | for (i = 0; i < adapter->num_tx_queues; i++) |
2797 | ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
2798 | } |
2799 | ||
e8e26350 | 2800 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2801 | |
a6616b42 | 2802 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
e8e9f696 | 2803 | struct ixgbe_ring *rx_ring) |
cc41ac7c | 2804 | { |
cc41ac7c | 2805 | u32 srrctl; |
bf29ee6c | 2806 | u8 reg_idx = rx_ring->reg_idx; |
3be1adfb | 2807 | |
bd508178 AD |
2808 | switch (adapter->hw.mac.type) { |
2809 | case ixgbe_mac_82598EB: { | |
2810 | struct ixgbe_ring_feature *feature = adapter->ring_feature; | |
2811 | const int mask = feature[RING_F_RSS].mask; | |
bf29ee6c | 2812 | reg_idx = reg_idx & mask; |
cc41ac7c | 2813 | } |
bd508178 AD |
2814 | break; |
2815 | case ixgbe_mac_82599EB: | |
b93a2226 | 2816 | case ixgbe_mac_X540: |
bd508178 AD |
2817 | default: |
2818 | break; | |
2819 | } | |
2820 | ||
bf29ee6c | 2821 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx)); |
cc41ac7c JB |
2822 | |
2823 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2824 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
9e10e045 AD |
2825 | if (adapter->num_vfs) |
2826 | srrctl |= IXGBE_SRRCTL_DROP_EN; | |
cc41ac7c | 2827 | |
afafd5b0 AD |
2828 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
2829 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2830 | ||
7d637bcc | 2831 | if (ring_is_ps_enabled(rx_ring)) { |
afafd5b0 AD |
2832 | #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER |
2833 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2834 | #else | |
2835 | srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2836 | #endif | |
cc41ac7c | 2837 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
cc41ac7c | 2838 | } else { |
afafd5b0 AD |
2839 | srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >> |
2840 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
cc41ac7c | 2841 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
cc41ac7c | 2842 | } |
e8e26350 | 2843 | |
bf29ee6c | 2844 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl); |
cc41ac7c | 2845 | } |
9a799d71 | 2846 | |
05abb126 | 2847 | static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
0cefafad | 2848 | { |
05abb126 AD |
2849 | struct ixgbe_hw *hw = &adapter->hw; |
2850 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, | |
e8e9f696 JP |
2851 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, |
2852 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
05abb126 AD |
2853 | u32 mrqc = 0, reta = 0; |
2854 | u32 rxcsum; | |
2855 | int i, j; | |
0cefafad JB |
2856 | int mask; |
2857 | ||
05abb126 AD |
2858 | /* Fill out hash function seeds */ |
2859 | for (i = 0; i < 10; i++) | |
2860 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); | |
2861 | ||
2862 | /* Fill out redirection table */ | |
2863 | for (i = 0, j = 0; i < 128; i++, j++) { | |
2864 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
2865 | j = 0; | |
2866 | /* reta = 4-byte sliding window of | |
2867 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2868 | reta = (reta << 8) | (j * 0x11); | |
2869 | if ((i & 3) == 3) | |
2870 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
2871 | } | |
0cefafad | 2872 | |
05abb126 AD |
2873 | /* Disable indicating checksum in descriptor, enables RSS hash */ |
2874 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
2875 | rxcsum |= IXGBE_RXCSUM_PCSD; | |
2876 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
2877 | ||
2878 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
2879 | mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED; | |
2880 | else | |
2881 | mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
0cefafad | 2882 | #ifdef CONFIG_IXGBE_DCB |
05abb126 | 2883 | | IXGBE_FLAG_DCB_ENABLED |
0cefafad | 2884 | #endif |
05abb126 AD |
2885 | | IXGBE_FLAG_SRIOV_ENABLED |
2886 | ); | |
0cefafad JB |
2887 | |
2888 | switch (mask) { | |
2889 | case (IXGBE_FLAG_RSS_ENABLED): | |
2890 | mrqc = IXGBE_MRQC_RSSEN; | |
2891 | break; | |
1cdd1ec8 GR |
2892 | case (IXGBE_FLAG_SRIOV_ENABLED): |
2893 | mrqc = IXGBE_MRQC_VMDQEN; | |
2894 | break; | |
0cefafad JB |
2895 | #ifdef CONFIG_IXGBE_DCB |
2896 | case (IXGBE_FLAG_DCB_ENABLED): | |
2897 | mrqc = IXGBE_MRQC_RT8TCEN; | |
2898 | break; | |
2899 | #endif /* CONFIG_IXGBE_DCB */ | |
2900 | default: | |
2901 | break; | |
2902 | } | |
2903 | ||
05abb126 AD |
2904 | /* Perform hash on these packet types */ |
2905 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 | |
2906 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
2907 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
2908 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; | |
2909 | ||
2910 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); | |
0cefafad JB |
2911 | } |
2912 | ||
b93a2226 DS |
2913 | /** |
2914 | * ixgbe_clear_rscctl - disable RSC for the indicated ring | |
2915 | * @adapter: address of board private structure | |
2916 | * @ring: structure containing ring specific data | |
2917 | **/ | |
2918 | void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter, | |
2919 | struct ixgbe_ring *ring) | |
2920 | { | |
2921 | struct ixgbe_hw *hw = &adapter->hw; | |
2922 | u32 rscctrl; | |
2923 | u8 reg_idx = ring->reg_idx; | |
2924 | ||
2925 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); | |
2926 | rscctrl &= ~IXGBE_RSCCTL_RSCEN; | |
2927 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); | |
2928 | } | |
2929 | ||
bb5a9ad2 NS |
2930 | /** |
2931 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
2932 | * @adapter: address of board private structure | |
2933 | * @index: index of ring to set | |
bb5a9ad2 | 2934 | **/ |
b93a2226 | 2935 | void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
7367096a | 2936 | struct ixgbe_ring *ring) |
bb5a9ad2 | 2937 | { |
bb5a9ad2 | 2938 | struct ixgbe_hw *hw = &adapter->hw; |
bb5a9ad2 | 2939 | u32 rscctrl; |
edd2ea55 | 2940 | int rx_buf_len; |
bf29ee6c | 2941 | u8 reg_idx = ring->reg_idx; |
7367096a | 2942 | |
7d637bcc | 2943 | if (!ring_is_rsc_enabled(ring)) |
7367096a | 2944 | return; |
bb5a9ad2 | 2945 | |
7367096a AD |
2946 | rx_buf_len = ring->rx_buf_len; |
2947 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); | |
bb5a9ad2 NS |
2948 | rscctrl |= IXGBE_RSCCTL_RSCEN; |
2949 | /* | |
2950 | * we must limit the number of descriptors so that the | |
2951 | * total size of max desc * buf_len is not greater | |
2952 | * than 65535 | |
2953 | */ | |
7d637bcc | 2954 | if (ring_is_ps_enabled(ring)) { |
bb5a9ad2 NS |
2955 | #if (MAX_SKB_FRAGS > 16) |
2956 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2957 | #elif (MAX_SKB_FRAGS > 8) | |
2958 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2959 | #elif (MAX_SKB_FRAGS > 4) | |
2960 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2961 | #else | |
2962 | rscctrl |= IXGBE_RSCCTL_MAXDESC_1; | |
2963 | #endif | |
2964 | } else { | |
2965 | if (rx_buf_len < IXGBE_RXBUFFER_4096) | |
2966 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2967 | else if (rx_buf_len < IXGBE_RXBUFFER_8192) | |
2968 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2969 | else | |
2970 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2971 | } | |
7367096a | 2972 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); |
bb5a9ad2 NS |
2973 | } |
2974 | ||
9e10e045 AD |
2975 | /** |
2976 | * ixgbe_set_uta - Set unicast filter table address | |
2977 | * @adapter: board private structure | |
2978 | * | |
2979 | * The unicast table address is a register array of 32-bit registers. | |
2980 | * The table is meant to be used in a way similar to how the MTA is used | |
2981 | * however due to certain limitations in the hardware it is necessary to | |
2982 | * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous | |
2983 | * enable bit to allow vlan tag stripping when promiscuous mode is enabled | |
2984 | **/ | |
2985 | static void ixgbe_set_uta(struct ixgbe_adapter *adapter) | |
2986 | { | |
2987 | struct ixgbe_hw *hw = &adapter->hw; | |
2988 | int i; | |
2989 | ||
2990 | /* The UTA table only exists on 82599 hardware and newer */ | |
2991 | if (hw->mac.type < ixgbe_mac_82599EB) | |
2992 | return; | |
2993 | ||
2994 | /* we only need to do this if VMDq is enabled */ | |
2995 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
2996 | return; | |
2997 | ||
2998 | for (i = 0; i < 128; i++) | |
2999 | IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); | |
3000 | } | |
3001 | ||
3002 | #define IXGBE_MAX_RX_DESC_POLL 10 | |
3003 | static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
3004 | struct ixgbe_ring *ring) | |
3005 | { | |
3006 | struct ixgbe_hw *hw = &adapter->hw; | |
9e10e045 AD |
3007 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; |
3008 | u32 rxdctl; | |
bf29ee6c | 3009 | u8 reg_idx = ring->reg_idx; |
9e10e045 AD |
3010 | |
3011 | /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
3012 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3013 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3014 | return; | |
3015 | ||
3016 | do { | |
3017 | msleep(1); | |
3018 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3019 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3020 | ||
3021 | if (!wait_loop) { | |
3022 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " | |
3023 | "the polling period\n", reg_idx); | |
3024 | } | |
3025 | } | |
3026 | ||
2d39d576 YZ |
3027 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
3028 | struct ixgbe_ring *ring) | |
3029 | { | |
3030 | struct ixgbe_hw *hw = &adapter->hw; | |
3031 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; | |
3032 | u32 rxdctl; | |
3033 | u8 reg_idx = ring->reg_idx; | |
3034 | ||
3035 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3036 | rxdctl &= ~IXGBE_RXDCTL_ENABLE; | |
3037 | ||
3038 | /* write value back with RXDCTL.ENABLE bit cleared */ | |
3039 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3040 | ||
3041 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3042 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3043 | return; | |
3044 | ||
3045 | /* the hardware may take up to 100us to really disable the rx queue */ | |
3046 | do { | |
3047 | udelay(10); | |
3048 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3049 | } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3050 | ||
3051 | if (!wait_loop) { | |
3052 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " | |
3053 | "the polling period\n", reg_idx); | |
3054 | } | |
3055 | } | |
3056 | ||
84418e3b AD |
3057 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, |
3058 | struct ixgbe_ring *ring) | |
acd37177 AD |
3059 | { |
3060 | struct ixgbe_hw *hw = &adapter->hw; | |
3061 | u64 rdba = ring->dma; | |
9e10e045 | 3062 | u32 rxdctl; |
bf29ee6c | 3063 | u8 reg_idx = ring->reg_idx; |
acd37177 | 3064 | |
9e10e045 AD |
3065 | /* disable queue to avoid issues while updating state */ |
3066 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2d39d576 | 3067 | ixgbe_disable_rx_queue(adapter, ring); |
9e10e045 | 3068 | |
acd37177 AD |
3069 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); |
3070 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); | |
3071 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), | |
3072 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
3073 | IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); | |
3074 | IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); | |
84ea2591 | 3075 | ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx); |
9e10e045 AD |
3076 | |
3077 | ixgbe_configure_srrctl(adapter, ring); | |
3078 | ixgbe_configure_rscctl(adapter, ring); | |
3079 | ||
3080 | if (hw->mac.type == ixgbe_mac_82598EB) { | |
3081 | /* | |
3082 | * enable cache line friendly hardware writes: | |
3083 | * PTHRESH=32 descriptors (half the internal cache), | |
3084 | * this also removes ugly rx_no_buffer_count increment | |
3085 | * HTHRESH=4 descriptors (to minimize latency on fetch) | |
3086 | * WTHRESH=8 burst writeback up to two cache lines | |
3087 | */ | |
3088 | rxdctl &= ~0x3FFFFF; | |
3089 | rxdctl |= 0x080420; | |
3090 | } | |
3091 | ||
3092 | /* enable receive descriptor ring */ | |
3093 | rxdctl |= IXGBE_RXDCTL_ENABLE; | |
3094 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3095 | ||
3096 | ixgbe_rx_desc_queue_enable(adapter, ring); | |
fc77dc3c | 3097 | ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring)); |
acd37177 AD |
3098 | } |
3099 | ||
48654521 AD |
3100 | static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) |
3101 | { | |
3102 | struct ixgbe_hw *hw = &adapter->hw; | |
3103 | int p; | |
3104 | ||
3105 | /* PSRTYPE must be initialized in non 82598 adapters */ | |
3106 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
e8e9f696 JP |
3107 | IXGBE_PSRTYPE_UDPHDR | |
3108 | IXGBE_PSRTYPE_IPV4HDR | | |
48654521 | 3109 | IXGBE_PSRTYPE_L2HDR | |
e8e9f696 | 3110 | IXGBE_PSRTYPE_IPV6HDR; |
48654521 AD |
3111 | |
3112 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3113 | return; | |
3114 | ||
3115 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) | |
3116 | psrtype |= (adapter->num_rx_queues_per_pool << 29); | |
3117 | ||
3118 | for (p = 0; p < adapter->num_rx_pools; p++) | |
3119 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p), | |
3120 | psrtype); | |
3121 | } | |
3122 | ||
f5b4a52e AD |
3123 | static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) |
3124 | { | |
3125 | struct ixgbe_hw *hw = &adapter->hw; | |
3126 | u32 gcr_ext; | |
3127 | u32 vt_reg_bits; | |
3128 | u32 reg_offset, vf_shift; | |
3129 | u32 vmdctl; | |
3130 | ||
3131 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
3132 | return; | |
3133 | ||
3134 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
3135 | vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN; | |
3136 | vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT); | |
3137 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits); | |
3138 | ||
3139 | vf_shift = adapter->num_vfs % 32; | |
3140 | reg_offset = (adapter->num_vfs > 32) ? 1 : 0; | |
3141 | ||
3142 | /* Enable only the PF's pool for Tx/Rx */ | |
3143 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift)); | |
3144 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0); | |
3145 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift)); | |
3146 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0); | |
3147 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
3148 | ||
3149 | /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ | |
3150 | hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs); | |
3151 | ||
3152 | /* | |
3153 | * Set up VF register offsets for selected VT Mode, | |
3154 | * i.e. 32 or 64 VFs for SR-IOV | |
3155 | */ | |
3156 | gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
3157 | gcr_ext |= IXGBE_GCR_EXT_MSIX_EN; | |
3158 | gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64; | |
3159 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); | |
3160 | ||
3161 | /* enable Tx loopback for VF/PF communication */ | |
3162 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
a985b6c3 GR |
3163 | /* Enable MAC Anti-Spoofing */ |
3164 | hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0), | |
3165 | adapter->num_vfs); | |
f5b4a52e AD |
3166 | } |
3167 | ||
477de6ed | 3168 | static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) |
9a799d71 | 3169 | { |
9a799d71 AK |
3170 | struct ixgbe_hw *hw = &adapter->hw; |
3171 | struct net_device *netdev = adapter->netdev; | |
3172 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
7c6e0a43 | 3173 | int rx_buf_len; |
477de6ed AD |
3174 | struct ixgbe_ring *rx_ring; |
3175 | int i; | |
3176 | u32 mhadd, hlreg0; | |
48654521 | 3177 | |
9a799d71 | 3178 | /* Decide whether to use packet split mode or not */ |
a124339a DS |
3179 | /* On by default */ |
3180 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; | |
3181 | ||
1cdd1ec8 | 3182 | /* Do not use packet split if we're in SR-IOV Mode */ |
a124339a DS |
3183 | if (adapter->num_vfs) |
3184 | adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED; | |
3185 | ||
3186 | /* Disable packet split due to 82599 erratum #45 */ | |
3187 | if (hw->mac.type == ixgbe_mac_82599EB) | |
3188 | adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED; | |
9a799d71 AK |
3189 | |
3190 | /* Set the RX buffer length according to the mode */ | |
3191 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 3192 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
9a799d71 | 3193 | } else { |
0c19d6af | 3194 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && |
f8212f97 | 3195 | (netdev->mtu <= ETH_DATA_LEN)) |
7c6e0a43 | 3196 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 3197 | else |
477de6ed | 3198 | rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024); |
9a799d71 AK |
3199 | } |
3200 | ||
63f39bd1 | 3201 | #ifdef IXGBE_FCOE |
477de6ed AD |
3202 | /* adjust max frame to be able to do baby jumbo for FCoE */ |
3203 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
3204 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
3205 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9a799d71 | 3206 | |
477de6ed AD |
3207 | #endif /* IXGBE_FCOE */ |
3208 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); | |
3209 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { | |
3210 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
3211 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
3212 | ||
3213 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
3214 | } | |
3215 | ||
3216 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
3217 | /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ | |
3218 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
3219 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
9a799d71 | 3220 | |
0cefafad JB |
3221 | /* |
3222 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3223 | * the Base and Length of the Rx Descriptor Ring | |
3224 | */ | |
9a799d71 | 3225 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 3226 | rx_ring = adapter->rx_ring[i]; |
a6616b42 | 3227 | rx_ring->rx_buf_len = rx_buf_len; |
cc41ac7c | 3228 | |
6e455b89 | 3229 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) |
7d637bcc AD |
3230 | set_ring_ps_enabled(rx_ring); |
3231 | else | |
3232 | clear_ring_ps_enabled(rx_ring); | |
3233 | ||
3234 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) | |
3235 | set_ring_rsc_enabled(rx_ring); | |
1b3ff02e | 3236 | else |
7d637bcc | 3237 | clear_ring_rsc_enabled(rx_ring); |
cc41ac7c | 3238 | |
63f39bd1 | 3239 | #ifdef IXGBE_FCOE |
e8e9f696 | 3240 | if (netdev->features & NETIF_F_FCOE_MTU) { |
63f39bd1 YZ |
3241 | struct ixgbe_ring_feature *f; |
3242 | f = &adapter->ring_feature[RING_F_FCOE]; | |
6e455b89 | 3243 | if ((i >= f->mask) && (i < f->mask + f->indices)) { |
7d637bcc | 3244 | clear_ring_ps_enabled(rx_ring); |
6e455b89 YZ |
3245 | if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) |
3246 | rx_ring->rx_buf_len = | |
e8e9f696 | 3247 | IXGBE_FCOE_JUMBO_FRAME_SIZE; |
7d637bcc AD |
3248 | } else if (!ring_is_rsc_enabled(rx_ring) && |
3249 | !ring_is_ps_enabled(rx_ring)) { | |
3250 | rx_ring->rx_buf_len = | |
3251 | IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
6e455b89 | 3252 | } |
63f39bd1 | 3253 | } |
63f39bd1 | 3254 | #endif /* IXGBE_FCOE */ |
477de6ed | 3255 | } |
477de6ed AD |
3256 | } |
3257 | ||
7367096a AD |
3258 | static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) |
3259 | { | |
3260 | struct ixgbe_hw *hw = &adapter->hw; | |
3261 | u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
3262 | ||
3263 | switch (hw->mac.type) { | |
3264 | case ixgbe_mac_82598EB: | |
3265 | /* | |
3266 | * For VMDq support of different descriptor types or | |
3267 | * buffer sizes through the use of multiple SRRCTL | |
3268 | * registers, RDRXCTL.MVMEN must be set to 1 | |
3269 | * | |
3270 | * also, the manual doesn't mention it clearly but DCA hints | |
3271 | * will only use queue 0's tags unless this bit is set. Side | |
3272 | * effects of setting this bit are only that SRRCTL must be | |
3273 | * fully programmed [0..15] | |
3274 | */ | |
3275 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
3276 | break; | |
3277 | case ixgbe_mac_82599EB: | |
b93a2226 | 3278 | case ixgbe_mac_X540: |
7367096a AD |
3279 | /* Disable RSC for ACK packets */ |
3280 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
3281 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
3282 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; | |
3283 | /* hardware requires some bits to be set by default */ | |
3284 | rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); | |
3285 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
3286 | break; | |
3287 | default: | |
3288 | /* We should do nothing since we don't know this hardware */ | |
3289 | return; | |
3290 | } | |
3291 | ||
3292 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
3293 | } | |
3294 | ||
477de6ed AD |
3295 | /** |
3296 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset | |
3297 | * @adapter: board private structure | |
3298 | * | |
3299 | * Configure the Rx unit of the MAC after a reset. | |
3300 | **/ | |
3301 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
3302 | { | |
3303 | struct ixgbe_hw *hw = &adapter->hw; | |
477de6ed AD |
3304 | int i; |
3305 | u32 rxctrl; | |
477de6ed AD |
3306 | |
3307 | /* disable receives while setting up the descriptors */ | |
3308 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
3309 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
3310 | ||
3311 | ixgbe_setup_psrtype(adapter); | |
7367096a | 3312 | ixgbe_setup_rdrxctl(adapter); |
477de6ed | 3313 | |
9e10e045 | 3314 | /* Program registers for the distribution of queues */ |
f5b4a52e | 3315 | ixgbe_setup_mrqc(adapter); |
f5b4a52e | 3316 | |
9e10e045 AD |
3317 | ixgbe_set_uta(adapter); |
3318 | ||
477de6ed AD |
3319 | /* set_rx_buffer_len must be called before ring initialization */ |
3320 | ixgbe_set_rx_buffer_len(adapter); | |
3321 | ||
3322 | /* | |
3323 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3324 | * the Base and Length of the Rx Descriptor Ring | |
3325 | */ | |
9e10e045 AD |
3326 | for (i = 0; i < adapter->num_rx_queues; i++) |
3327 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
177db6ff | 3328 | |
9e10e045 AD |
3329 | /* disable drop enable for 82598 parts */ |
3330 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3331 | rxctrl |= IXGBE_RXCTRL_DMBYPS; | |
3332 | ||
3333 | /* enable all receives */ | |
3334 | rxctrl |= IXGBE_RXCTRL_RXEN; | |
3335 | hw->mac.ops.enable_rx_dma(hw, rxctrl); | |
9a799d71 AK |
3336 | } |
3337 | ||
068c89b0 DS |
3338 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
3339 | { | |
3340 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3341 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3342 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
3343 | |
3344 | /* add VID to filter table */ | |
1ada1b1b | 3345 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true); |
f62bbb5e | 3346 | set_bit(vid, adapter->active_vlans); |
068c89b0 DS |
3347 | } |
3348 | ||
3349 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
3350 | { | |
3351 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3352 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3353 | int pool_ndx = adapter->num_vfs; |
068c89b0 | 3354 | |
068c89b0 | 3355 | /* remove VID from filter table */ |
1ada1b1b | 3356 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false); |
f62bbb5e | 3357 | clear_bit(vid, adapter->active_vlans); |
068c89b0 DS |
3358 | } |
3359 | ||
5f6c0181 JB |
3360 | /** |
3361 | * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering | |
3362 | * @adapter: driver data | |
3363 | */ | |
3364 | static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter) | |
3365 | { | |
3366 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e JG |
3367 | u32 vlnctrl; |
3368 | ||
3369 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3370 | vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); | |
3371 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3372 | } | |
3373 | ||
3374 | /** | |
3375 | * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering | |
3376 | * @adapter: driver data | |
3377 | */ | |
3378 | static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter) | |
3379 | { | |
3380 | struct ixgbe_hw *hw = &adapter->hw; | |
3381 | u32 vlnctrl; | |
3382 | ||
3383 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3384 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
3385 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
3386 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3387 | } | |
3388 | ||
3389 | /** | |
3390 | * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping | |
3391 | * @adapter: driver data | |
3392 | */ | |
3393 | static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) | |
3394 | { | |
3395 | struct ixgbe_hw *hw = &adapter->hw; | |
3396 | u32 vlnctrl; | |
5f6c0181 JB |
3397 | int i, j; |
3398 | ||
3399 | switch (hw->mac.type) { | |
3400 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3401 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3402 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3403 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3404 | break; | |
3405 | case ixgbe_mac_82599EB: | |
b93a2226 | 3406 | case ixgbe_mac_X540: |
5f6c0181 JB |
3407 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3408 | j = adapter->rx_ring[i]->reg_idx; | |
3409 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3410 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
3411 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3412 | } | |
3413 | break; | |
3414 | default: | |
3415 | break; | |
3416 | } | |
3417 | } | |
3418 | ||
3419 | /** | |
f62bbb5e | 3420 | * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping |
5f6c0181 JB |
3421 | * @adapter: driver data |
3422 | */ | |
f62bbb5e | 3423 | static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) |
5f6c0181 JB |
3424 | { |
3425 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e | 3426 | u32 vlnctrl; |
5f6c0181 JB |
3427 | int i, j; |
3428 | ||
3429 | switch (hw->mac.type) { | |
3430 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3431 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3432 | vlnctrl |= IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3433 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3434 | break; | |
3435 | case ixgbe_mac_82599EB: | |
b93a2226 | 3436 | case ixgbe_mac_X540: |
5f6c0181 JB |
3437 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3438 | j = adapter->rx_ring[i]->reg_idx; | |
3439 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3440 | vlnctrl |= IXGBE_RXDCTL_VME; | |
3441 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3442 | } | |
3443 | break; | |
3444 | default: | |
3445 | break; | |
3446 | } | |
3447 | } | |
3448 | ||
9a799d71 AK |
3449 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
3450 | { | |
f62bbb5e | 3451 | u16 vid; |
9a799d71 | 3452 | |
f62bbb5e JG |
3453 | ixgbe_vlan_rx_add_vid(adapter->netdev, 0); |
3454 | ||
3455 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) | |
3456 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
9a799d71 AK |
3457 | } |
3458 | ||
2850062a AD |
3459 | /** |
3460 | * ixgbe_write_uc_addr_list - write unicast addresses to RAR table | |
3461 | * @netdev: network interface device structure | |
3462 | * | |
3463 | * Writes unicast address list to the RAR table. | |
3464 | * Returns: -ENOMEM on failure/insufficient address space | |
3465 | * 0 on no addresses written | |
3466 | * X on writing X addresses to the RAR table | |
3467 | **/ | |
3468 | static int ixgbe_write_uc_addr_list(struct net_device *netdev) | |
3469 | { | |
3470 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3471 | struct ixgbe_hw *hw = &adapter->hw; | |
3472 | unsigned int vfn = adapter->num_vfs; | |
3473 | unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1); | |
3474 | int count = 0; | |
3475 | ||
3476 | /* return ENOMEM indicating insufficient memory for addresses */ | |
3477 | if (netdev_uc_count(netdev) > rar_entries) | |
3478 | return -ENOMEM; | |
3479 | ||
3480 | if (!netdev_uc_empty(netdev) && rar_entries) { | |
3481 | struct netdev_hw_addr *ha; | |
3482 | /* return error if we do not support writing to RAR table */ | |
3483 | if (!hw->mac.ops.set_rar) | |
3484 | return -ENOMEM; | |
3485 | ||
3486 | netdev_for_each_uc_addr(ha, netdev) { | |
3487 | if (!rar_entries) | |
3488 | break; | |
3489 | hw->mac.ops.set_rar(hw, rar_entries--, ha->addr, | |
3490 | vfn, IXGBE_RAH_AV); | |
3491 | count++; | |
3492 | } | |
3493 | } | |
3494 | /* write the addresses in reverse order to avoid write combining */ | |
3495 | for (; rar_entries > 0 ; rar_entries--) | |
3496 | hw->mac.ops.clear_rar(hw, rar_entries); | |
3497 | ||
3498 | return count; | |
3499 | } | |
3500 | ||
9a799d71 | 3501 | /** |
2c5645cf | 3502 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
3503 | * @netdev: network interface device structure |
3504 | * | |
2c5645cf CL |
3505 | * The set_rx_method entry point is called whenever the unicast/multicast |
3506 | * address list or the network interface flags are updated. This routine is | |
3507 | * responsible for configuring the hardware for proper unicast, multicast and | |
3508 | * promiscuous mode. | |
9a799d71 | 3509 | **/ |
7f870475 | 3510 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
3511 | { |
3512 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3513 | struct ixgbe_hw *hw = &adapter->hw; | |
2850062a AD |
3514 | u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; |
3515 | int count; | |
9a799d71 AK |
3516 | |
3517 | /* Check for Promiscuous and All Multicast modes */ | |
3518 | ||
3519 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3520 | ||
f5dc442b AD |
3521 | /* set all bits that we expect to always be set */ |
3522 | fctrl |= IXGBE_FCTRL_BAM; | |
3523 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ | |
3524 | fctrl |= IXGBE_FCTRL_PMCF; | |
3525 | ||
2850062a AD |
3526 | /* clear the bits we are changing the status of */ |
3527 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
3528 | ||
9a799d71 | 3529 | if (netdev->flags & IFF_PROMISC) { |
e433ea1f | 3530 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 3531 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
2850062a | 3532 | vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE); |
5f6c0181 JB |
3533 | /* don't hardware filter vlans in promisc mode */ |
3534 | ixgbe_vlan_filter_disable(adapter); | |
9a799d71 | 3535 | } else { |
746b9f02 PM |
3536 | if (netdev->flags & IFF_ALLMULTI) { |
3537 | fctrl |= IXGBE_FCTRL_MPE; | |
2850062a AD |
3538 | vmolr |= IXGBE_VMOLR_MPE; |
3539 | } else { | |
3540 | /* | |
3541 | * Write addresses to the MTA, if the attempt fails | |
3542 | * then we should just turn on promiscous mode so | |
3543 | * that we can at least receive multicast traffic | |
3544 | */ | |
3545 | hw->mac.ops.update_mc_addr_list(hw, netdev); | |
3546 | vmolr |= IXGBE_VMOLR_ROMPE; | |
746b9f02 | 3547 | } |
5f6c0181 | 3548 | ixgbe_vlan_filter_enable(adapter); |
e433ea1f | 3549 | hw->addr_ctrl.user_set_promisc = false; |
2850062a AD |
3550 | /* |
3551 | * Write addresses to available RAR registers, if there is not | |
3552 | * sufficient space to store all the addresses then enable | |
3553 | * unicast promiscous mode | |
3554 | */ | |
3555 | count = ixgbe_write_uc_addr_list(netdev); | |
3556 | if (count < 0) { | |
3557 | fctrl |= IXGBE_FCTRL_UPE; | |
3558 | vmolr |= IXGBE_VMOLR_ROPE; | |
3559 | } | |
9a799d71 AK |
3560 | } |
3561 | ||
2850062a | 3562 | if (adapter->num_vfs) { |
1cdd1ec8 | 3563 | ixgbe_restore_vf_multicasts(adapter); |
2850062a AD |
3564 | vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) & |
3565 | ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | | |
3566 | IXGBE_VMOLR_ROPE); | |
3567 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr); | |
3568 | } | |
3569 | ||
3570 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
f62bbb5e JG |
3571 | |
3572 | if (netdev->features & NETIF_F_HW_VLAN_RX) | |
3573 | ixgbe_vlan_strip_enable(adapter); | |
3574 | else | |
3575 | ixgbe_vlan_strip_disable(adapter); | |
9a799d71 AK |
3576 | } |
3577 | ||
021230d4 AV |
3578 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
3579 | { | |
3580 | int q_idx; | |
3581 | struct ixgbe_q_vector *q_vector; | |
3582 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3583 | ||
3584 | /* legacy and MSI only use one vector */ | |
3585 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3586 | q_vectors = 1; | |
3587 | ||
3588 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 3589 | struct napi_struct *napi; |
7a921c93 | 3590 | q_vector = adapter->q_vector[q_idx]; |
f0848276 | 3591 | napi = &q_vector->napi; |
91281fd3 AD |
3592 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
3593 | if (!q_vector->rxr_count || !q_vector->txr_count) { | |
3594 | if (q_vector->txr_count == 1) | |
3595 | napi->poll = &ixgbe_clean_txonly; | |
3596 | else if (q_vector->rxr_count == 1) | |
3597 | napi->poll = &ixgbe_clean_rxonly; | |
3598 | } | |
3599 | } | |
f0848276 JB |
3600 | |
3601 | napi_enable(napi); | |
021230d4 AV |
3602 | } |
3603 | } | |
3604 | ||
3605 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
3606 | { | |
3607 | int q_idx; | |
3608 | struct ixgbe_q_vector *q_vector; | |
3609 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3610 | ||
3611 | /* legacy and MSI only use one vector */ | |
3612 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3613 | q_vectors = 1; | |
3614 | ||
3615 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 3616 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
3617 | napi_disable(&q_vector->napi); |
3618 | } | |
3619 | } | |
3620 | ||
7a6b6f51 | 3621 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3622 | /* |
3623 | * ixgbe_configure_dcb - Configure DCB hardware | |
3624 | * @adapter: ixgbe adapter struct | |
3625 | * | |
3626 | * This is called by the driver on open to configure the DCB hardware. | |
3627 | * This is also called by the gennetlink interface when reconfiguring | |
3628 | * the DCB state. | |
3629 | */ | |
3630 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
3631 | { | |
3632 | struct ixgbe_hw *hw = &adapter->hw; | |
9806307a | 3633 | int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
2f90b865 | 3634 | |
67ebd791 AD |
3635 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { |
3636 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3637 | netif_set_gso_max_size(adapter->netdev, 65536); | |
3638 | return; | |
3639 | } | |
3640 | ||
3641 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3642 | netif_set_gso_max_size(adapter->netdev, 32768); | |
3643 | ||
9806307a JF |
3644 | #ifdef CONFIG_FCOE |
3645 | if (adapter->netdev->features & NETIF_F_FCOE_MTU) | |
3646 | max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); | |
3647 | #endif | |
3648 | ||
80ab193d | 3649 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, |
9806307a | 3650 | DCB_TX_CONFIG); |
80ab193d | 3651 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, |
9806307a | 3652 | DCB_RX_CONFIG); |
2f90b865 | 3653 | |
2f90b865 | 3654 | /* Enable VLAN tag insert/strip */ |
f62bbb5e | 3655 | adapter->netdev->features |= NETIF_F_HW_VLAN_RX; |
5f6c0181 | 3656 | |
2f90b865 | 3657 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
01fa7d90 AD |
3658 | |
3659 | /* reconfigure the hardware */ | |
3660 | ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); | |
2f90b865 AD |
3661 | } |
3662 | ||
3663 | #endif | |
9a799d71 AK |
3664 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
3665 | { | |
3666 | struct net_device *netdev = adapter->netdev; | |
c4cf55e5 | 3667 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
3668 | int i; |
3669 | ||
7a6b6f51 | 3670 | #ifdef CONFIG_IXGBE_DCB |
67ebd791 | 3671 | ixgbe_configure_dcb(adapter); |
2f90b865 | 3672 | #endif |
9a799d71 | 3673 | |
f62bbb5e JG |
3674 | ixgbe_set_rx_mode(netdev); |
3675 | ixgbe_restore_vlan(adapter); | |
3676 | ||
eacd73f7 YZ |
3677 | #ifdef IXGBE_FCOE |
3678 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
3679 | ixgbe_configure_fcoe(adapter); | |
3680 | ||
3681 | #endif /* IXGBE_FCOE */ | |
c4cf55e5 PWJ |
3682 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
3683 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 3684 | adapter->tx_ring[i]->atr_sample_rate = |
e8e9f696 | 3685 | adapter->atr_sample_rate; |
c4cf55e5 PWJ |
3686 | ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc); |
3687 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { | |
3688 | ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc); | |
3689 | } | |
933d41f1 | 3690 | ixgbe_configure_virtualization(adapter); |
c4cf55e5 | 3691 | |
9a799d71 AK |
3692 | ixgbe_configure_tx(adapter); |
3693 | ixgbe_configure_rx(adapter); | |
9a799d71 AK |
3694 | } |
3695 | ||
e8e26350 PW |
3696 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
3697 | { | |
3698 | switch (hw->phy.type) { | |
3699 | case ixgbe_phy_sfp_avago: | |
3700 | case ixgbe_phy_sfp_ftl: | |
3701 | case ixgbe_phy_sfp_intel: | |
3702 | case ixgbe_phy_sfp_unknown: | |
ea0a04df DS |
3703 | case ixgbe_phy_sfp_passive_tyco: |
3704 | case ixgbe_phy_sfp_passive_unknown: | |
3705 | case ixgbe_phy_sfp_active_unknown: | |
3706 | case ixgbe_phy_sfp_ftl_active: | |
e8e26350 PW |
3707 | return true; |
3708 | default: | |
3709 | return false; | |
3710 | } | |
3711 | } | |
3712 | ||
0ecc061d | 3713 | /** |
e8e26350 PW |
3714 | * ixgbe_sfp_link_config - set up SFP+ link |
3715 | * @adapter: pointer to private adapter struct | |
3716 | **/ | |
3717 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
3718 | { | |
3719 | struct ixgbe_hw *hw = &adapter->hw; | |
3720 | ||
3721 | if (hw->phy.multispeed_fiber) { | |
3722 | /* | |
3723 | * In multispeed fiber setups, the device may not have | |
3724 | * had a physical connection when the driver loaded. | |
3725 | * If that's the case, the initial link configuration | |
3726 | * couldn't get the MAC into 10G or 1G mode, so we'll | |
3727 | * never have a link status change interrupt fire. | |
3728 | * We need to try and force an autonegotiation | |
3729 | * session, then bring up link. | |
3730 | */ | |
4c7e604b AG |
3731 | if (hw->mac.ops.setup_sfp) |
3732 | hw->mac.ops.setup_sfp(hw); | |
e8e26350 PW |
3733 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) |
3734 | schedule_work(&adapter->multispeed_fiber_task); | |
3735 | } else { | |
3736 | /* | |
3737 | * Direct Attach Cu and non-multispeed fiber modules | |
3738 | * still need to be configured properly prior to | |
3739 | * attempting link. | |
3740 | */ | |
3741 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK)) | |
3742 | schedule_work(&adapter->sfp_config_module_task); | |
3743 | } | |
3744 | } | |
3745 | ||
3746 | /** | |
3747 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
3748 | * @hw: pointer to private hardware struct |
3749 | * | |
3750 | * Returns 0 on success, negative on failure | |
3751 | **/ | |
e8e26350 | 3752 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
3753 | { |
3754 | u32 autoneg; | |
8620a103 | 3755 | bool negotiation, link_up = false; |
0ecc061d PWJ |
3756 | u32 ret = IXGBE_ERR_LINK_SETUP; |
3757 | ||
3758 | if (hw->mac.ops.check_link) | |
3759 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
3760 | ||
3761 | if (ret) | |
3762 | goto link_cfg_out; | |
3763 | ||
3764 | if (hw->mac.ops.get_link_capabilities) | |
e8e9f696 JP |
3765 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, |
3766 | &negotiation); | |
0ecc061d PWJ |
3767 | if (ret) |
3768 | goto link_cfg_out; | |
3769 | ||
8620a103 MC |
3770 | if (hw->mac.ops.setup_link) |
3771 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
3772 | link_cfg_out: |
3773 | return ret; | |
3774 | } | |
3775 | ||
a34bcfff | 3776 | static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) |
9a799d71 | 3777 | { |
9a799d71 | 3778 | struct ixgbe_hw *hw = &adapter->hw; |
a34bcfff | 3779 | u32 gpie = 0; |
9a799d71 | 3780 | |
9b471446 | 3781 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
a34bcfff AD |
3782 | gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
3783 | IXGBE_GPIE_OCD; | |
3784 | gpie |= IXGBE_GPIE_EIAME; | |
9b471446 JB |
3785 | /* |
3786 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
3787 | * this saves a register write for every interrupt | |
3788 | */ | |
3789 | switch (hw->mac.type) { | |
3790 | case ixgbe_mac_82598EB: | |
3791 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3792 | break; | |
9b471446 | 3793 | case ixgbe_mac_82599EB: |
b93a2226 DS |
3794 | case ixgbe_mac_X540: |
3795 | default: | |
9b471446 JB |
3796 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); |
3797 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
3798 | break; | |
3799 | } | |
3800 | } else { | |
021230d4 AV |
3801 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
3802 | * specifically only auto mask tx and rx interrupts */ | |
3803 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3804 | } | |
9a799d71 | 3805 | |
a34bcfff AD |
3806 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
3807 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
3808 | ||
3809 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
3810 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
3811 | gpie |= IXGBE_GPIE_VTMODE_64; | |
119fc60a MC |
3812 | } |
3813 | ||
a34bcfff AD |
3814 | /* Enable fan failure interrupt */ |
3815 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
0befdb3e | 3816 | gpie |= IXGBE_SDP1_GPIEN; |
0befdb3e | 3817 | |
a34bcfff | 3818 | if (hw->mac.type == ixgbe_mac_82599EB) |
e8e26350 PW |
3819 | gpie |= IXGBE_SDP1_GPIEN; |
3820 | gpie |= IXGBE_SDP2_GPIEN; | |
a34bcfff AD |
3821 | |
3822 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
3823 | } | |
3824 | ||
3825 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) | |
3826 | { | |
3827 | struct ixgbe_hw *hw = &adapter->hw; | |
a34bcfff | 3828 | int err; |
a34bcfff AD |
3829 | u32 ctrl_ext; |
3830 | ||
3831 | ixgbe_get_hw_control(adapter); | |
3832 | ixgbe_setup_gpie(adapter); | |
e8e26350 | 3833 | |
9a799d71 AK |
3834 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3835 | ixgbe_configure_msix(adapter); | |
3836 | else | |
3837 | ixgbe_configure_msi_and_legacy(adapter); | |
3838 | ||
c6ecf39a DS |
3839 | /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */ |
3840 | if (hw->mac.ops.enable_tx_laser && | |
3841 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 3842 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a | 3843 | (hw->mac.type == ixgbe_mac_82599EB)))) |
61fac744 PW |
3844 | hw->mac.ops.enable_tx_laser(hw); |
3845 | ||
9a799d71 | 3846 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
3847 | ixgbe_napi_enable_all(adapter); |
3848 | ||
73c4b7cd AD |
3849 | if (ixgbe_is_sfp(hw)) { |
3850 | ixgbe_sfp_link_config(adapter); | |
3851 | } else { | |
3852 | err = ixgbe_non_sfp_link_config(hw); | |
3853 | if (err) | |
3854 | e_err(probe, "link_config FAILED %d\n", err); | |
3855 | } | |
3856 | ||
021230d4 AV |
3857 | /* clear any pending interrupts, may auto mask */ |
3858 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
6af3b9eb | 3859 | ixgbe_irq_enable(adapter, true, true); |
9a799d71 | 3860 | |
bf069c97 DS |
3861 | /* |
3862 | * If this adapter has a fan, check to see if we had a failure | |
3863 | * before we enabled the interrupt. | |
3864 | */ | |
3865 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
3866 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
3867 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 3868 | e_crit(drv, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
3869 | } |
3870 | ||
e8e26350 PW |
3871 | /* |
3872 | * For hot-pluggable SFP+ devices, a new SFP+ module may have | |
19343de2 DS |
3873 | * arrived before interrupts were enabled but after probe. Such |
3874 | * devices wouldn't have their type identified yet. We need to | |
3875 | * kick off the SFP+ module setup first, then try to bring up link. | |
e8e26350 PW |
3876 | * If we're not hot-pluggable SFP+, we just need to configure link |
3877 | * and bring it up. | |
3878 | */ | |
73c4b7cd AD |
3879 | if (hw->phy.type == ixgbe_phy_unknown) |
3880 | schedule_work(&adapter->sfp_config_module_task); | |
0ecc061d | 3881 | |
1da100bb | 3882 | /* enable transmits */ |
477de6ed | 3883 | netif_tx_start_all_queues(adapter->netdev); |
1da100bb | 3884 | |
9a799d71 AK |
3885 | /* bring the link up in the watchdog, this could race with our first |
3886 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
3887 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
3888 | adapter->link_check_timeout = jiffies; | |
9a799d71 | 3889 | mod_timer(&adapter->watchdog_timer, jiffies); |
c9205697 GR |
3890 | |
3891 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
3892 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
3893 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
3894 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
3895 | ||
9a799d71 AK |
3896 | return 0; |
3897 | } | |
3898 | ||
d4f80882 AV |
3899 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
3900 | { | |
3901 | WARN_ON(in_interrupt()); | |
3902 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
3903 | msleep(1); | |
3904 | ixgbe_down(adapter); | |
5809a1ae GR |
3905 | /* |
3906 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
3907 | * back up to give the VFs time to respond to the reset. The | |
3908 | * two second wait is based upon the watchdog timer cycle in | |
3909 | * the VF driver. | |
3910 | */ | |
3911 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3912 | msleep(2000); | |
d4f80882 AV |
3913 | ixgbe_up(adapter); |
3914 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
3915 | } | |
3916 | ||
9a799d71 AK |
3917 | int ixgbe_up(struct ixgbe_adapter *adapter) |
3918 | { | |
3919 | /* hardware has been reset, we need to reload some things */ | |
3920 | ixgbe_configure(adapter); | |
3921 | ||
3922 | return ixgbe_up_complete(adapter); | |
3923 | } | |
3924 | ||
3925 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
3926 | { | |
c44ade9e | 3927 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
3928 | int err; |
3929 | ||
3930 | err = hw->mac.ops.init_hw(hw); | |
da4dd0f7 PWJ |
3931 | switch (err) { |
3932 | case 0: | |
3933 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
3934 | break; | |
3935 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
849c4542 | 3936 | e_dev_err("master disable timed out\n"); |
da4dd0f7 | 3937 | break; |
794caeb2 PWJ |
3938 | case IXGBE_ERR_EEPROM_VERSION: |
3939 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
3940 | e_dev_warn("This device is a pre-production adapter/LOM. " |
3941 | "Please be aware there may be issuesassociated with " | |
3942 | "your hardware. If you are experiencing problems " | |
3943 | "please contact your Intel or hardware " | |
3944 | "representative who provided you with this " | |
3945 | "hardware.\n"); | |
794caeb2 | 3946 | break; |
da4dd0f7 | 3947 | default: |
849c4542 | 3948 | e_dev_err("Hardware Error: %d\n", err); |
da4dd0f7 | 3949 | } |
9a799d71 AK |
3950 | |
3951 | /* reprogram the RAR[0] in case user changed it. */ | |
1cdd1ec8 GR |
3952 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
3953 | IXGBE_RAH_AV); | |
9a799d71 AK |
3954 | } |
3955 | ||
9a799d71 AK |
3956 | /** |
3957 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
9a799d71 AK |
3958 | * @rx_ring: ring to free buffers from |
3959 | **/ | |
b6ec895e | 3960 | static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) |
9a799d71 | 3961 | { |
b6ec895e | 3962 | struct device *dev = rx_ring->dev; |
9a799d71 | 3963 | unsigned long size; |
b6ec895e | 3964 | u16 i; |
9a799d71 | 3965 | |
84418e3b AD |
3966 | /* ring already cleared, nothing to do */ |
3967 | if (!rx_ring->rx_buffer_info) | |
3968 | return; | |
9a799d71 | 3969 | |
84418e3b | 3970 | /* Free all the Rx ring sk_buffs */ |
9a799d71 AK |
3971 | for (i = 0; i < rx_ring->count; i++) { |
3972 | struct ixgbe_rx_buffer *rx_buffer_info; | |
3973 | ||
3974 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
3975 | if (rx_buffer_info->dma) { | |
b6ec895e | 3976 | dma_unmap_single(rx_ring->dev, rx_buffer_info->dma, |
e8e9f696 | 3977 | rx_ring->rx_buf_len, |
1b507730 | 3978 | DMA_FROM_DEVICE); |
9a799d71 AK |
3979 | rx_buffer_info->dma = 0; |
3980 | } | |
3981 | if (rx_buffer_info->skb) { | |
f8212f97 | 3982 | struct sk_buff *skb = rx_buffer_info->skb; |
9a799d71 | 3983 | rx_buffer_info->skb = NULL; |
f8212f97 AD |
3984 | do { |
3985 | struct sk_buff *this = skb; | |
e8171aaa | 3986 | if (IXGBE_RSC_CB(this)->delay_unmap) { |
b6ec895e | 3987 | dma_unmap_single(dev, |
1b507730 | 3988 | IXGBE_RSC_CB(this)->dma, |
e8e9f696 | 3989 | rx_ring->rx_buf_len, |
1b507730 | 3990 | DMA_FROM_DEVICE); |
fd3686a8 | 3991 | IXGBE_RSC_CB(this)->dma = 0; |
e8171aaa | 3992 | IXGBE_RSC_CB(skb)->delay_unmap = false; |
fd3686a8 | 3993 | } |
f8212f97 AD |
3994 | skb = skb->prev; |
3995 | dev_kfree_skb(this); | |
3996 | } while (skb); | |
9a799d71 AK |
3997 | } |
3998 | if (!rx_buffer_info->page) | |
3999 | continue; | |
4f57ca6e | 4000 | if (rx_buffer_info->page_dma) { |
b6ec895e | 4001 | dma_unmap_page(dev, rx_buffer_info->page_dma, |
1b507730 | 4002 | PAGE_SIZE / 2, DMA_FROM_DEVICE); |
4f57ca6e JB |
4003 | rx_buffer_info->page_dma = 0; |
4004 | } | |
9a799d71 AK |
4005 | put_page(rx_buffer_info->page); |
4006 | rx_buffer_info->page = NULL; | |
762f4c57 | 4007 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
4008 | } |
4009 | ||
4010 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
4011 | memset(rx_ring->rx_buffer_info, 0, size); | |
4012 | ||
4013 | /* Zero out the descriptor ring */ | |
4014 | memset(rx_ring->desc, 0, rx_ring->size); | |
4015 | ||
4016 | rx_ring->next_to_clean = 0; | |
4017 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
4018 | } |
4019 | ||
4020 | /** | |
4021 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
9a799d71 AK |
4022 | * @tx_ring: ring to be cleaned |
4023 | **/ | |
b6ec895e | 4024 | static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) |
9a799d71 AK |
4025 | { |
4026 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4027 | unsigned long size; | |
b6ec895e | 4028 | u16 i; |
9a799d71 | 4029 | |
84418e3b AD |
4030 | /* ring already cleared, nothing to do */ |
4031 | if (!tx_ring->tx_buffer_info) | |
4032 | return; | |
9a799d71 | 4033 | |
84418e3b | 4034 | /* Free all the Tx ring sk_buffs */ |
9a799d71 AK |
4035 | for (i = 0; i < tx_ring->count; i++) { |
4036 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
b6ec895e | 4037 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
9a799d71 AK |
4038 | } |
4039 | ||
4040 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
4041 | memset(tx_ring->tx_buffer_info, 0, size); | |
4042 | ||
4043 | /* Zero out the descriptor ring */ | |
4044 | memset(tx_ring->desc, 0, tx_ring->size); | |
4045 | ||
4046 | tx_ring->next_to_use = 0; | |
4047 | tx_ring->next_to_clean = 0; | |
9a799d71 AK |
4048 | } |
4049 | ||
4050 | /** | |
021230d4 | 4051 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
4052 | * @adapter: board private structure |
4053 | **/ | |
021230d4 | 4054 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4055 | { |
4056 | int i; | |
4057 | ||
021230d4 | 4058 | for (i = 0; i < adapter->num_rx_queues; i++) |
b6ec895e | 4059 | ixgbe_clean_rx_ring(adapter->rx_ring[i]); |
9a799d71 AK |
4060 | } |
4061 | ||
4062 | /** | |
021230d4 | 4063 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
4064 | * @adapter: board private structure |
4065 | **/ | |
021230d4 | 4066 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4067 | { |
4068 | int i; | |
4069 | ||
021230d4 | 4070 | for (i = 0; i < adapter->num_tx_queues; i++) |
b6ec895e | 4071 | ixgbe_clean_tx_ring(adapter->tx_ring[i]); |
9a799d71 AK |
4072 | } |
4073 | ||
4074 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
4075 | { | |
4076 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 4077 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 4078 | u32 rxctrl; |
7f821875 | 4079 | u32 txdctl; |
bf29ee6c | 4080 | int i; |
b25ebfd2 | 4081 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 AK |
4082 | |
4083 | /* signal that we are down to the interrupt handler */ | |
4084 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4085 | ||
767081ad GR |
4086 | /* disable receive for all VFs and wait one second */ |
4087 | if (adapter->num_vfs) { | |
767081ad GR |
4088 | /* ping all the active vfs to let them know we are going down */ |
4089 | ixgbe_ping_all_vfs(adapter); | |
581d1aa7 | 4090 | |
767081ad GR |
4091 | /* Disable all VFTE/VFRE TX/RX */ |
4092 | ixgbe_disable_tx_rx(adapter); | |
581d1aa7 GR |
4093 | |
4094 | /* Mark all the VFs as inactive */ | |
4095 | for (i = 0 ; i < adapter->num_vfs; i++) | |
4096 | adapter->vfinfo[i].clear_to_send = 0; | |
767081ad GR |
4097 | } |
4098 | ||
9a799d71 | 4099 | /* disable receives */ |
7f821875 JB |
4100 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
4101 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 | 4102 | |
2d39d576 YZ |
4103 | /* disable all enabled rx queues */ |
4104 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4105 | /* this call also flushes the previous write */ | |
4106 | ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); | |
4107 | ||
9a799d71 AK |
4108 | msleep(10); |
4109 | ||
7f821875 JB |
4110 | netif_tx_stop_all_queues(netdev); |
4111 | ||
0a1f87cb DS |
4112 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
4113 | del_timer_sync(&adapter->sfp_timer); | |
9a799d71 | 4114 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 4115 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 4116 | |
c0dfb90e JF |
4117 | netif_carrier_off(netdev); |
4118 | netif_tx_disable(netdev); | |
4119 | ||
4120 | ixgbe_irq_disable(adapter); | |
4121 | ||
4122 | ixgbe_napi_disable_all(adapter); | |
4123 | ||
b25ebfd2 PW |
4124 | /* Cleanup the affinity_hint CPU mask memory and callback */ |
4125 | for (i = 0; i < num_q_vectors; i++) { | |
4126 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
4127 | /* clear the affinity_mask in the IRQ descriptor */ | |
4128 | irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL); | |
4129 | /* release the CPU mask memory */ | |
4130 | free_cpumask_var(q_vector->affinity_mask); | |
4131 | } | |
4132 | ||
c4cf55e5 PWJ |
4133 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
4134 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
4135 | cancel_work_sync(&adapter->fdir_reinit_task); | |
4136 | ||
119fc60a MC |
4137 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
4138 | cancel_work_sync(&adapter->check_overtemp_task); | |
4139 | ||
7f821875 JB |
4140 | /* disable transmits in the hardware now that interrupts are off */ |
4141 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
bf29ee6c AD |
4142 | u8 reg_idx = adapter->tx_ring[i]->reg_idx; |
4143 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); | |
4144 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), | |
e8e9f696 | 4145 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); |
7f821875 | 4146 | } |
88512539 | 4147 | /* Disable the Tx DMA engine on 82599 */ |
bd508178 AD |
4148 | switch (hw->mac.type) { |
4149 | case ixgbe_mac_82599EB: | |
b93a2226 | 4150 | case ixgbe_mac_X540: |
88512539 | 4151 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, |
e8e9f696 JP |
4152 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & |
4153 | ~IXGBE_DMATXCTL_TE)); | |
bd508178 AD |
4154 | break; |
4155 | default: | |
4156 | break; | |
4157 | } | |
7f821875 | 4158 | |
9a713e7c PW |
4159 | /* clear n-tuple filters that are cached */ |
4160 | ethtool_ntuple_flush(netdev); | |
4161 | ||
6f4a0e45 PL |
4162 | if (!pci_channel_offline(adapter->pdev)) |
4163 | ixgbe_reset(adapter); | |
c6ecf39a DS |
4164 | |
4165 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ | |
4166 | if (hw->mac.ops.disable_tx_laser && | |
4167 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 4168 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a DS |
4169 | (hw->mac.type == ixgbe_mac_82599EB)))) |
4170 | hw->mac.ops.disable_tx_laser(hw); | |
4171 | ||
9a799d71 AK |
4172 | ixgbe_clean_all_tx_rings(adapter); |
4173 | ixgbe_clean_all_rx_rings(adapter); | |
4174 | ||
5dd2d332 | 4175 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 4176 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 4177 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 4178 | #endif |
9a799d71 AK |
4179 | } |
4180 | ||
9a799d71 | 4181 | /** |
021230d4 AV |
4182 | * ixgbe_poll - NAPI Rx polling callback |
4183 | * @napi: structure for representing this polling device | |
4184 | * @budget: how many packets driver is allowed to clean | |
4185 | * | |
4186 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 4187 | **/ |
021230d4 | 4188 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 4189 | { |
9a1a69ad | 4190 | struct ixgbe_q_vector *q_vector = |
e8e9f696 | 4191 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 4192 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a1a69ad | 4193 | int tx_clean_complete, work_done = 0; |
9a799d71 | 4194 | |
5dd2d332 | 4195 | #ifdef CONFIG_IXGBE_DCA |
33cf09c9 AD |
4196 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
4197 | ixgbe_update_dca(q_vector); | |
bd0362dd JC |
4198 | #endif |
4199 | ||
4a0b9ca0 PW |
4200 | tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]); |
4201 | ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget); | |
9a799d71 | 4202 | |
9a1a69ad | 4203 | if (!tx_clean_complete) |
d2c7ddd6 DM |
4204 | work_done = budget; |
4205 | ||
53e52c72 DM |
4206 | /* If budget not fully consumed, exit the polling mode */ |
4207 | if (work_done < budget) { | |
288379f0 | 4208 | napi_complete(napi); |
f7554a2b | 4209 | if (adapter->rx_itr_setting & 1) |
f494e8fa | 4210 | ixgbe_set_itr(adapter); |
d4f80882 | 4211 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 4212 | ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 4213 | } |
9a799d71 AK |
4214 | return work_done; |
4215 | } | |
4216 | ||
4217 | /** | |
4218 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
4219 | * @netdev: network interface device structure | |
4220 | **/ | |
4221 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
4222 | { | |
4223 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4224 | ||
c84d324c JF |
4225 | adapter->tx_timeout_count++; |
4226 | ||
9a799d71 AK |
4227 | /* Do the reset outside of interrupt context */ |
4228 | schedule_work(&adapter->reset_task); | |
4229 | } | |
4230 | ||
4231 | static void ixgbe_reset_task(struct work_struct *work) | |
4232 | { | |
4233 | struct ixgbe_adapter *adapter; | |
4234 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
4235 | ||
2f90b865 AD |
4236 | /* If we're already down or resetting, just bail */ |
4237 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
4238 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
4239 | return; | |
4240 | ||
dcd79aeb TI |
4241 | ixgbe_dump(adapter); |
4242 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
d4f80882 | 4243 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
4244 | } |
4245 | ||
bc97114d PWJ |
4246 | #ifdef CONFIG_IXGBE_DCB |
4247 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
b9804972 | 4248 | { |
bc97114d | 4249 | bool ret = false; |
0cefafad | 4250 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB]; |
b9804972 | 4251 | |
0cefafad JB |
4252 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) |
4253 | return ret; | |
4254 | ||
4255 | f->mask = 0x7 << 3; | |
4256 | adapter->num_rx_queues = f->indices; | |
4257 | adapter->num_tx_queues = f->indices; | |
4258 | ret = true; | |
2f90b865 | 4259 | |
bc97114d PWJ |
4260 | return ret; |
4261 | } | |
4262 | #endif | |
4263 | ||
4df10466 JB |
4264 | /** |
4265 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
4266 | * @adapter: board private structure to initialize | |
4267 | * | |
4268 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
4269 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
4270 | * | |
4271 | **/ | |
bc97114d PWJ |
4272 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
4273 | { | |
4274 | bool ret = false; | |
0cefafad | 4275 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS]; |
bc97114d PWJ |
4276 | |
4277 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
0cefafad JB |
4278 | f->mask = 0xF; |
4279 | adapter->num_rx_queues = f->indices; | |
4280 | adapter->num_tx_queues = f->indices; | |
bc97114d PWJ |
4281 | ret = true; |
4282 | } else { | |
bc97114d | 4283 | ret = false; |
b9804972 JB |
4284 | } |
4285 | ||
bc97114d PWJ |
4286 | return ret; |
4287 | } | |
4288 | ||
c4cf55e5 PWJ |
4289 | /** |
4290 | * ixgbe_set_fdir_queues: Allocate queues for Flow Director | |
4291 | * @adapter: board private structure to initialize | |
4292 | * | |
4293 | * Flow Director is an advanced Rx filter, attempting to get Rx flows back | |
4294 | * to the original CPU that initiated the Tx session. This runs in addition | |
4295 | * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the | |
4296 | * Rx load across CPUs using RSS. | |
4297 | * | |
4298 | **/ | |
e8e9f696 | 4299 | static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter) |
c4cf55e5 PWJ |
4300 | { |
4301 | bool ret = false; | |
4302 | struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR]; | |
4303 | ||
4304 | f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices); | |
4305 | f_fdir->mask = 0; | |
4306 | ||
4307 | /* Flow Director must have RSS enabled */ | |
4308 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
4309 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
4310 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) { | |
4311 | adapter->num_tx_queues = f_fdir->indices; | |
4312 | adapter->num_rx_queues = f_fdir->indices; | |
4313 | ret = true; | |
4314 | } else { | |
4315 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
4316 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
4317 | } | |
4318 | return ret; | |
4319 | } | |
4320 | ||
0331a832 YZ |
4321 | #ifdef IXGBE_FCOE |
4322 | /** | |
4323 | * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE) | |
4324 | * @adapter: board private structure to initialize | |
4325 | * | |
4326 | * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges. | |
4327 | * The ring feature mask is not used as a mask for FCoE, as it can take any 8 | |
4328 | * rx queues out of the max number of rx queues, instead, it is used as the | |
4329 | * index of the first rx queue used by FCoE. | |
4330 | * | |
4331 | **/ | |
4332 | static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter) | |
4333 | { | |
4334 | bool ret = false; | |
4335 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
4336 | ||
4337 | f->indices = min((int)num_online_cpus(), f->indices); | |
4338 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
8de8b2e6 YZ |
4339 | adapter->num_rx_queues = 1; |
4340 | adapter->num_tx_queues = 1; | |
0331a832 YZ |
4341 | #ifdef CONFIG_IXGBE_DCB |
4342 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
396e799c | 4343 | e_info(probe, "FCoE enabled with DCB\n"); |
0331a832 YZ |
4344 | ixgbe_set_dcb_queues(adapter); |
4345 | } | |
4346 | #endif | |
4347 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
396e799c | 4348 | e_info(probe, "FCoE enabled with RSS\n"); |
8faa2a78 YZ |
4349 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || |
4350 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) | |
4351 | ixgbe_set_fdir_queues(adapter); | |
4352 | else | |
4353 | ixgbe_set_rss_queues(adapter); | |
0331a832 YZ |
4354 | } |
4355 | /* adding FCoE rx rings to the end */ | |
4356 | f->mask = adapter->num_rx_queues; | |
4357 | adapter->num_rx_queues += f->indices; | |
8de8b2e6 | 4358 | adapter->num_tx_queues += f->indices; |
0331a832 YZ |
4359 | |
4360 | ret = true; | |
4361 | } | |
4362 | ||
4363 | return ret; | |
4364 | } | |
4365 | ||
4366 | #endif /* IXGBE_FCOE */ | |
1cdd1ec8 GR |
4367 | /** |
4368 | * ixgbe_set_sriov_queues: Allocate queues for IOV use | |
4369 | * @adapter: board private structure to initialize | |
4370 | * | |
4371 | * IOV doesn't actually use anything, so just NAK the | |
4372 | * request for now and let the other queue routines | |
4373 | * figure out what to do. | |
4374 | */ | |
4375 | static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter) | |
4376 | { | |
4377 | return false; | |
4378 | } | |
4379 | ||
4df10466 JB |
4380 | /* |
4381 | * ixgbe_set_num_queues: Allocate queues for device, feature dependant | |
4382 | * @adapter: board private structure to initialize | |
4383 | * | |
4384 | * This is the top level queue allocation routine. The order here is very | |
4385 | * important, starting with the "most" number of features turned on at once, | |
4386 | * and ending with the smallest set of features. This way large combinations | |
4387 | * can be allocated if they're turned on, and smaller combinations are the | |
4388 | * fallthrough conditions. | |
4389 | * | |
4390 | **/ | |
847f53ff | 4391 | static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
bc97114d | 4392 | { |
1cdd1ec8 GR |
4393 | /* Start with base case */ |
4394 | adapter->num_rx_queues = 1; | |
4395 | adapter->num_tx_queues = 1; | |
4396 | adapter->num_rx_pools = adapter->num_rx_queues; | |
4397 | adapter->num_rx_queues_per_pool = 1; | |
4398 | ||
4399 | if (ixgbe_set_sriov_queues(adapter)) | |
847f53ff | 4400 | goto done; |
1cdd1ec8 | 4401 | |
0331a832 YZ |
4402 | #ifdef IXGBE_FCOE |
4403 | if (ixgbe_set_fcoe_queues(adapter)) | |
4404 | goto done; | |
4405 | ||
4406 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
4407 | #ifdef CONFIG_IXGBE_DCB |
4408 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 4409 | goto done; |
bc97114d PWJ |
4410 | |
4411 | #endif | |
c4cf55e5 PWJ |
4412 | if (ixgbe_set_fdir_queues(adapter)) |
4413 | goto done; | |
4414 | ||
bc97114d | 4415 | if (ixgbe_set_rss_queues(adapter)) |
af22ab1b WF |
4416 | goto done; |
4417 | ||
4418 | /* fallback to base case */ | |
4419 | adapter->num_rx_queues = 1; | |
4420 | adapter->num_tx_queues = 1; | |
4421 | ||
4422 | done: | |
847f53ff | 4423 | /* Notify the stack of the (possibly) reduced queue counts. */ |
f0796d5c | 4424 | netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); |
847f53ff BH |
4425 | return netif_set_real_num_rx_queues(adapter->netdev, |
4426 | adapter->num_rx_queues); | |
b9804972 JB |
4427 | } |
4428 | ||
021230d4 | 4429 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
e8e9f696 | 4430 | int vectors) |
021230d4 AV |
4431 | { |
4432 | int err, vector_threshold; | |
4433 | ||
4434 | /* We'll want at least 3 (vector_threshold): | |
4435 | * 1) TxQ[0] Cleanup | |
4436 | * 2) RxQ[0] Cleanup | |
4437 | * 3) Other (Link Status Change, etc.) | |
4438 | * 4) TCP Timer (optional) | |
4439 | */ | |
4440 | vector_threshold = MIN_MSIX_COUNT; | |
4441 | ||
4442 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
4443 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
4444 | * Right now, we simply care about how many we'll get; we'll | |
4445 | * set them up later while requesting irq's. | |
4446 | */ | |
4447 | while (vectors >= vector_threshold) { | |
4448 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
e8e9f696 | 4449 | vectors); |
021230d4 AV |
4450 | if (!err) /* Success in acquiring all requested vectors. */ |
4451 | break; | |
4452 | else if (err < 0) | |
4453 | vectors = 0; /* Nasty failure, quit now */ | |
4454 | else /* err == number of vectors we should try again with */ | |
4455 | vectors = err; | |
4456 | } | |
4457 | ||
4458 | if (vectors < vector_threshold) { | |
4459 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
4460 | * This just means we'll go with either a single MSI | |
4461 | * vector or fall back to legacy interrupts. | |
4462 | */ | |
849c4542 ET |
4463 | netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, |
4464 | "Unable to allocate MSI-X interrupts\n"); | |
021230d4 AV |
4465 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
4466 | kfree(adapter->msix_entries); | |
4467 | adapter->msix_entries = NULL; | |
021230d4 AV |
4468 | } else { |
4469 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
4470 | /* |
4471 | * Adjust for only the vectors we'll use, which is minimum | |
4472 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
4473 | * vectors we were allocated. | |
4474 | */ | |
4475 | adapter->num_msix_vectors = min(vectors, | |
e8e9f696 | 4476 | adapter->max_msix_q_vectors + NON_Q_VECTORS); |
021230d4 AV |
4477 | } |
4478 | } | |
4479 | ||
021230d4 | 4480 | /** |
bc97114d | 4481 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
4482 | * @adapter: board private structure to initialize |
4483 | * | |
bc97114d PWJ |
4484 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
4485 | * | |
021230d4 | 4486 | **/ |
bc97114d | 4487 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 4488 | { |
bc97114d | 4489 | int i; |
bc97114d | 4490 | |
9d6b758f AD |
4491 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) |
4492 | return false; | |
bc97114d | 4493 | |
9d6b758f AD |
4494 | for (i = 0; i < adapter->num_rx_queues; i++) |
4495 | adapter->rx_ring[i]->reg_idx = i; | |
4496 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4497 | adapter->tx_ring[i]->reg_idx = i; | |
4498 | ||
4499 | return true; | |
bc97114d PWJ |
4500 | } |
4501 | ||
4502 | #ifdef CONFIG_IXGBE_DCB | |
4503 | /** | |
4504 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
4505 | * @adapter: board private structure to initialize | |
4506 | * | |
4507 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
4508 | * | |
4509 | **/ | |
4510 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
4511 | { | |
4512 | int i; | |
4513 | bool ret = false; | |
4514 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
4515 | ||
bd508178 AD |
4516 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) |
4517 | return false; | |
f92ef202 | 4518 | |
bd508178 AD |
4519 | /* the number of queues is assumed to be symmetric */ |
4520 | switch (adapter->hw.mac.type) { | |
4521 | case ixgbe_mac_82598EB: | |
4522 | for (i = 0; i < dcb_i; i++) { | |
4523 | adapter->rx_ring[i]->reg_idx = i << 3; | |
4524 | adapter->tx_ring[i]->reg_idx = i << 2; | |
4525 | } | |
4526 | ret = true; | |
4527 | break; | |
4528 | case ixgbe_mac_82599EB: | |
b93a2226 | 4529 | case ixgbe_mac_X540: |
bd508178 AD |
4530 | if (dcb_i == 8) { |
4531 | /* | |
4532 | * Tx TC0 starts at: descriptor queue 0 | |
4533 | * Tx TC1 starts at: descriptor queue 32 | |
4534 | * Tx TC2 starts at: descriptor queue 64 | |
4535 | * Tx TC3 starts at: descriptor queue 80 | |
4536 | * Tx TC4 starts at: descriptor queue 96 | |
4537 | * Tx TC5 starts at: descriptor queue 104 | |
4538 | * Tx TC6 starts at: descriptor queue 112 | |
4539 | * Tx TC7 starts at: descriptor queue 120 | |
4540 | * | |
4541 | * Rx TC0-TC7 are offset by 16 queues each | |
4542 | */ | |
4543 | for (i = 0; i < 3; i++) { | |
4544 | adapter->tx_ring[i]->reg_idx = i << 5; | |
4545 | adapter->rx_ring[i]->reg_idx = i << 4; | |
e8e26350 | 4546 | } |
bd508178 AD |
4547 | for ( ; i < 5; i++) { |
4548 | adapter->tx_ring[i]->reg_idx = ((i + 2) << 4); | |
4549 | adapter->rx_ring[i]->reg_idx = i << 4; | |
4550 | } | |
4551 | for ( ; i < dcb_i; i++) { | |
4552 | adapter->tx_ring[i]->reg_idx = ((i + 8) << 3); | |
4553 | adapter->rx_ring[i]->reg_idx = i << 4; | |
4554 | } | |
4555 | ret = true; | |
4556 | } else if (dcb_i == 4) { | |
4557 | /* | |
4558 | * Tx TC0 starts at: descriptor queue 0 | |
4559 | * Tx TC1 starts at: descriptor queue 64 | |
4560 | * Tx TC2 starts at: descriptor queue 96 | |
4561 | * Tx TC3 starts at: descriptor queue 112 | |
4562 | * | |
4563 | * Rx TC0-TC3 are offset by 32 queues each | |
4564 | */ | |
4565 | adapter->tx_ring[0]->reg_idx = 0; | |
4566 | adapter->tx_ring[1]->reg_idx = 64; | |
4567 | adapter->tx_ring[2]->reg_idx = 96; | |
4568 | adapter->tx_ring[3]->reg_idx = 112; | |
4569 | for (i = 0 ; i < dcb_i; i++) | |
4570 | adapter->rx_ring[i]->reg_idx = i << 5; | |
4571 | ret = true; | |
021230d4 | 4572 | } |
bd508178 AD |
4573 | break; |
4574 | default: | |
4575 | break; | |
021230d4 | 4576 | } |
bc97114d PWJ |
4577 | return ret; |
4578 | } | |
4579 | #endif | |
4580 | ||
c4cf55e5 PWJ |
4581 | /** |
4582 | * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director | |
4583 | * @adapter: board private structure to initialize | |
4584 | * | |
4585 | * Cache the descriptor ring offsets for Flow Director to the assigned rings. | |
4586 | * | |
4587 | **/ | |
e8e9f696 | 4588 | static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter) |
c4cf55e5 PWJ |
4589 | { |
4590 | int i; | |
4591 | bool ret = false; | |
4592 | ||
4593 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
4594 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
4595 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) { | |
4596 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 4597 | adapter->rx_ring[i]->reg_idx = i; |
c4cf55e5 | 4598 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 4599 | adapter->tx_ring[i]->reg_idx = i; |
c4cf55e5 PWJ |
4600 | ret = true; |
4601 | } | |
4602 | ||
4603 | return ret; | |
4604 | } | |
4605 | ||
0331a832 YZ |
4606 | #ifdef IXGBE_FCOE |
4607 | /** | |
4608 | * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE | |
4609 | * @adapter: board private structure to initialize | |
4610 | * | |
4611 | * Cache the descriptor ring offsets for FCoE mode to the assigned rings. | |
4612 | * | |
4613 | */ | |
4614 | static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter) | |
4615 | { | |
0331a832 | 4616 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; |
bf29ee6c AD |
4617 | int i; |
4618 | u8 fcoe_rx_i = 0, fcoe_tx_i = 0; | |
4619 | ||
4620 | if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) | |
4621 | return false; | |
0331a832 | 4622 | |
0331a832 | 4623 | #ifdef CONFIG_IXGBE_DCB |
bf29ee6c AD |
4624 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
4625 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; | |
8de8b2e6 | 4626 | |
bf29ee6c AD |
4627 | ixgbe_cache_ring_dcb(adapter); |
4628 | /* find out queues in TC for FCoE */ | |
4629 | fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1; | |
4630 | fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1; | |
4631 | /* | |
4632 | * In 82599, the number of Tx queues for each traffic | |
4633 | * class for both 8-TC and 4-TC modes are: | |
4634 | * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 | |
4635 | * 8 TCs: 32 32 16 16 8 8 8 8 | |
4636 | * 4 TCs: 64 64 32 32 | |
4637 | * We have max 8 queues for FCoE, where 8 the is | |
4638 | * FCoE redirection table size. If TC for FCoE is | |
4639 | * less than or equal to TC3, we have enough queues | |
4640 | * to add max of 8 queues for FCoE, so we start FCoE | |
4641 | * Tx queue from the next one, i.e., reg_idx + 1. | |
4642 | * If TC for FCoE is above TC3, implying 8 TC mode, | |
4643 | * and we need 8 for FCoE, we have to take all queues | |
4644 | * in that traffic class for FCoE. | |
4645 | */ | |
4646 | if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3)) | |
4647 | fcoe_tx_i--; | |
4648 | } | |
0331a832 | 4649 | #endif /* CONFIG_IXGBE_DCB */ |
bf29ee6c AD |
4650 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
4651 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
4652 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) | |
4653 | ixgbe_cache_ring_fdir(adapter); | |
4654 | else | |
4655 | ixgbe_cache_ring_rss(adapter); | |
8faa2a78 | 4656 | |
bf29ee6c AD |
4657 | fcoe_rx_i = f->mask; |
4658 | fcoe_tx_i = f->mask; | |
0331a832 | 4659 | } |
bf29ee6c AD |
4660 | for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) { |
4661 | adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i; | |
4662 | adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i; | |
4663 | } | |
4664 | return true; | |
0331a832 YZ |
4665 | } |
4666 | ||
4667 | #endif /* IXGBE_FCOE */ | |
1cdd1ec8 GR |
4668 | /** |
4669 | * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov | |
4670 | * @adapter: board private structure to initialize | |
4671 | * | |
4672 | * SR-IOV doesn't use any descriptor rings but changes the default if | |
4673 | * no other mapping is used. | |
4674 | * | |
4675 | */ | |
4676 | static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter) | |
4677 | { | |
4a0b9ca0 PW |
4678 | adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2; |
4679 | adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2; | |
1cdd1ec8 GR |
4680 | if (adapter->num_vfs) |
4681 | return true; | |
4682 | else | |
4683 | return false; | |
4684 | } | |
4685 | ||
bc97114d PWJ |
4686 | /** |
4687 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
4688 | * @adapter: board private structure to initialize | |
4689 | * | |
4690 | * Once we know the feature-set enabled for the device, we'll cache | |
4691 | * the register offset the descriptor ring is assigned to. | |
4692 | * | |
4693 | * Note, the order the various feature calls is important. It must start with | |
4694 | * the "most" features enabled at the same time, then trickle down to the | |
4695 | * least amount of features turned on at once. | |
4696 | **/ | |
4697 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
4698 | { | |
4699 | /* start with default case */ | |
4a0b9ca0 PW |
4700 | adapter->rx_ring[0]->reg_idx = 0; |
4701 | adapter->tx_ring[0]->reg_idx = 0; | |
bc97114d | 4702 | |
1cdd1ec8 GR |
4703 | if (ixgbe_cache_ring_sriov(adapter)) |
4704 | return; | |
4705 | ||
0331a832 YZ |
4706 | #ifdef IXGBE_FCOE |
4707 | if (ixgbe_cache_ring_fcoe(adapter)) | |
4708 | return; | |
4709 | ||
4710 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
4711 | #ifdef CONFIG_IXGBE_DCB |
4712 | if (ixgbe_cache_ring_dcb(adapter)) | |
4713 | return; | |
4714 | ||
4715 | #endif | |
c4cf55e5 PWJ |
4716 | if (ixgbe_cache_ring_fdir(adapter)) |
4717 | return; | |
4718 | ||
bc97114d PWJ |
4719 | if (ixgbe_cache_ring_rss(adapter)) |
4720 | return; | |
021230d4 AV |
4721 | } |
4722 | ||
9a799d71 AK |
4723 | /** |
4724 | * ixgbe_alloc_queues - Allocate memory for all rings | |
4725 | * @adapter: board private structure to initialize | |
4726 | * | |
4727 | * We allocate one ring per queue at run-time since we don't know the | |
4df10466 JB |
4728 | * number of queues at compile-time. The polling_netdev array is |
4729 | * intended for Multiqueue, but should work fine with a single queue. | |
9a799d71 | 4730 | **/ |
2f90b865 | 4731 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 | 4732 | { |
e2ddeba9 | 4733 | int rx = 0, tx = 0, nid = adapter->node; |
9a799d71 | 4734 | |
e2ddeba9 ED |
4735 | if (nid < 0 || !node_online(nid)) |
4736 | nid = first_online_node; | |
4737 | ||
4738 | for (; tx < adapter->num_tx_queues; tx++) { | |
4739 | struct ixgbe_ring *ring; | |
4740 | ||
4741 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid); | |
4a0b9ca0 | 4742 | if (!ring) |
e2ddeba9 | 4743 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
4a0b9ca0 | 4744 | if (!ring) |
e2ddeba9 | 4745 | goto err_allocation; |
4a0b9ca0 | 4746 | ring->count = adapter->tx_ring_count; |
e2ddeba9 ED |
4747 | ring->queue_index = tx; |
4748 | ring->numa_node = nid; | |
b6ec895e | 4749 | ring->dev = &adapter->pdev->dev; |
fc77dc3c | 4750 | ring->netdev = adapter->netdev; |
4a0b9ca0 | 4751 | |
e2ddeba9 | 4752 | adapter->tx_ring[tx] = ring; |
021230d4 | 4753 | } |
b9804972 | 4754 | |
e2ddeba9 ED |
4755 | for (; rx < adapter->num_rx_queues; rx++) { |
4756 | struct ixgbe_ring *ring; | |
4a0b9ca0 | 4757 | |
e2ddeba9 | 4758 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid); |
4a0b9ca0 | 4759 | if (!ring) |
e2ddeba9 | 4760 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
4a0b9ca0 | 4761 | if (!ring) |
e2ddeba9 ED |
4762 | goto err_allocation; |
4763 | ring->count = adapter->rx_ring_count; | |
4764 | ring->queue_index = rx; | |
4765 | ring->numa_node = nid; | |
b6ec895e | 4766 | ring->dev = &adapter->pdev->dev; |
fc77dc3c | 4767 | ring->netdev = adapter->netdev; |
4a0b9ca0 | 4768 | |
e2ddeba9 | 4769 | adapter->rx_ring[rx] = ring; |
021230d4 AV |
4770 | } |
4771 | ||
4772 | ixgbe_cache_ring_register(adapter); | |
4773 | ||
4774 | return 0; | |
4775 | ||
e2ddeba9 ED |
4776 | err_allocation: |
4777 | while (tx) | |
4778 | kfree(adapter->tx_ring[--tx]); | |
4779 | ||
4780 | while (rx) | |
4781 | kfree(adapter->rx_ring[--rx]); | |
021230d4 AV |
4782 | return -ENOMEM; |
4783 | } | |
4784 | ||
4785 | /** | |
4786 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
4787 | * @adapter: board private structure to initialize | |
4788 | * | |
4789 | * Attempt to configure the interrupts using the best available | |
4790 | * capabilities of the hardware and the kernel. | |
4791 | **/ | |
feea6a57 | 4792 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 4793 | { |
8be0e467 | 4794 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
4795 | int err = 0; |
4796 | int vector, v_budget; | |
4797 | ||
4798 | /* | |
4799 | * It's easy to be greedy for MSI-X vectors, but it really | |
4800 | * doesn't do us much good if we have a lot more vectors | |
4801 | * than CPU's. So let's be conservative and only ask for | |
342bde1b | 4802 | * (roughly) the same number of vectors as there are CPU's. |
021230d4 AV |
4803 | */ |
4804 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
e8e9f696 | 4805 | (int)num_online_cpus()) + NON_Q_VECTORS; |
021230d4 AV |
4806 | |
4807 | /* | |
4808 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
4809 | * hw.mac->max_msix_vectors vectors. With features |
4810 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
4811 | * descriptor queues supported by our device. Thus, we cap it off in | |
4812 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 4813 | */ |
8be0e467 | 4814 | v_budget = min(v_budget, (int)hw->mac.max_msix_vectors); |
021230d4 AV |
4815 | |
4816 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
4817 | * mean we disable MSI-X capabilities of the adapter. */ | |
4818 | adapter->msix_entries = kcalloc(v_budget, | |
e8e9f696 | 4819 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
4820 | if (adapter->msix_entries) { |
4821 | for (vector = 0; vector < v_budget; vector++) | |
4822 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 4823 | |
7a921c93 | 4824 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 4825 | |
7a921c93 AD |
4826 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
4827 | goto out; | |
4828 | } | |
26d27844 | 4829 | |
7a921c93 AD |
4830 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
4831 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
45b9f509 AD |
4832 | if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE | |
4833 | IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) { | |
4834 | e_err(probe, | |
4835 | "Flow Director is not supported while multiple " | |
4836 | "queues are disabled. Disabling Flow Director\n"); | |
4837 | } | |
c4cf55e5 PWJ |
4838 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
4839 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
4840 | adapter->atr_sample_rate = 0; | |
1cdd1ec8 GR |
4841 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
4842 | ixgbe_disable_sriov(adapter); | |
4843 | ||
847f53ff BH |
4844 | err = ixgbe_set_num_queues(adapter); |
4845 | if (err) | |
4846 | return err; | |
021230d4 | 4847 | |
021230d4 AV |
4848 | err = pci_enable_msi(adapter->pdev); |
4849 | if (!err) { | |
4850 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
4851 | } else { | |
849c4542 ET |
4852 | netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, |
4853 | "Unable to allocate MSI interrupt, " | |
4854 | "falling back to legacy. Error: %d\n", err); | |
021230d4 AV |
4855 | /* reset err */ |
4856 | err = 0; | |
4857 | } | |
4858 | ||
4859 | out: | |
021230d4 AV |
4860 | return err; |
4861 | } | |
4862 | ||
7a921c93 AD |
4863 | /** |
4864 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
4865 | * @adapter: board private structure to initialize | |
4866 | * | |
4867 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
4868 | * return -ENOMEM. | |
4869 | **/ | |
4870 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
4871 | { | |
4872 | int q_idx, num_q_vectors; | |
4873 | struct ixgbe_q_vector *q_vector; | |
7a921c93 AD |
4874 | int (*poll)(struct napi_struct *, int); |
4875 | ||
4876 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
4877 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
91281fd3 | 4878 | poll = &ixgbe_clean_rxtx_many; |
7a921c93 AD |
4879 | } else { |
4880 | num_q_vectors = 1; | |
7a921c93 AD |
4881 | poll = &ixgbe_poll; |
4882 | } | |
4883 | ||
4884 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
1a6c14a2 | 4885 | q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector), |
e8e9f696 | 4886 | GFP_KERNEL, adapter->node); |
1a6c14a2 JB |
4887 | if (!q_vector) |
4888 | q_vector = kzalloc(sizeof(struct ixgbe_q_vector), | |
e8e9f696 | 4889 | GFP_KERNEL); |
7a921c93 AD |
4890 | if (!q_vector) |
4891 | goto err_out; | |
4892 | q_vector->adapter = adapter; | |
f7554a2b NS |
4893 | if (q_vector->txr_count && !q_vector->rxr_count) |
4894 | q_vector->eitr = adapter->tx_eitr_param; | |
4895 | else | |
4896 | q_vector->eitr = adapter->rx_eitr_param; | |
fe49f04a | 4897 | q_vector->v_idx = q_idx; |
91281fd3 | 4898 | netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64); |
7a921c93 AD |
4899 | adapter->q_vector[q_idx] = q_vector; |
4900 | } | |
4901 | ||
4902 | return 0; | |
4903 | ||
4904 | err_out: | |
4905 | while (q_idx) { | |
4906 | q_idx--; | |
4907 | q_vector = adapter->q_vector[q_idx]; | |
4908 | netif_napi_del(&q_vector->napi); | |
4909 | kfree(q_vector); | |
4910 | adapter->q_vector[q_idx] = NULL; | |
4911 | } | |
4912 | return -ENOMEM; | |
4913 | } | |
4914 | ||
4915 | /** | |
4916 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
4917 | * @adapter: board private structure to initialize | |
4918 | * | |
4919 | * This function frees the memory allocated to the q_vectors. In addition if | |
4920 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
4921 | * to freeing the q_vector. | |
4922 | **/ | |
4923 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
4924 | { | |
4925 | int q_idx, num_q_vectors; | |
7a921c93 | 4926 | |
91281fd3 | 4927 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
7a921c93 | 4928 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
91281fd3 | 4929 | else |
7a921c93 | 4930 | num_q_vectors = 1; |
7a921c93 AD |
4931 | |
4932 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
4933 | struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx]; | |
7a921c93 | 4934 | adapter->q_vector[q_idx] = NULL; |
91281fd3 | 4935 | netif_napi_del(&q_vector->napi); |
7a921c93 AD |
4936 | kfree(q_vector); |
4937 | } | |
4938 | } | |
4939 | ||
7b25cdba | 4940 | static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
4941 | { |
4942 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
4943 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
4944 | pci_disable_msix(adapter->pdev); | |
4945 | kfree(adapter->msix_entries); | |
4946 | adapter->msix_entries = NULL; | |
4947 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
4948 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
4949 | pci_disable_msi(adapter->pdev); | |
4950 | } | |
021230d4 AV |
4951 | } |
4952 | ||
4953 | /** | |
4954 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
4955 | * @adapter: board private structure to initialize | |
4956 | * | |
4957 | * We determine which interrupt scheme to use based on... | |
4958 | * - Kernel support (MSI, MSI-X) | |
4959 | * - which can be user-defined (via MODULE_PARAM) | |
4960 | * - Hardware queue count (num_*_queues) | |
4961 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
4962 | **/ | |
2f90b865 | 4963 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
4964 | { |
4965 | int err; | |
4966 | ||
4967 | /* Number of supported queues */ | |
847f53ff BH |
4968 | err = ixgbe_set_num_queues(adapter); |
4969 | if (err) | |
4970 | return err; | |
021230d4 | 4971 | |
021230d4 AV |
4972 | err = ixgbe_set_interrupt_capability(adapter); |
4973 | if (err) { | |
849c4542 | 4974 | e_dev_err("Unable to setup interrupt capabilities\n"); |
021230d4 | 4975 | goto err_set_interrupt; |
9a799d71 AK |
4976 | } |
4977 | ||
7a921c93 AD |
4978 | err = ixgbe_alloc_q_vectors(adapter); |
4979 | if (err) { | |
849c4542 | 4980 | e_dev_err("Unable to allocate memory for queue vectors\n"); |
7a921c93 AD |
4981 | goto err_alloc_q_vectors; |
4982 | } | |
4983 | ||
4984 | err = ixgbe_alloc_queues(adapter); | |
4985 | if (err) { | |
849c4542 | 4986 | e_dev_err("Unable to allocate memory for queues\n"); |
7a921c93 AD |
4987 | goto err_alloc_queues; |
4988 | } | |
4989 | ||
849c4542 | 4990 | e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n", |
396e799c ET |
4991 | (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled", |
4992 | adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
4993 | |
4994 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4995 | ||
9a799d71 | 4996 | return 0; |
021230d4 | 4997 | |
7a921c93 AD |
4998 | err_alloc_queues: |
4999 | ixgbe_free_q_vectors(adapter); | |
5000 | err_alloc_q_vectors: | |
5001 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 5002 | err_set_interrupt: |
7a921c93 AD |
5003 | return err; |
5004 | } | |
5005 | ||
1a51502b ED |
5006 | static void ring_free_rcu(struct rcu_head *head) |
5007 | { | |
5008 | kfree(container_of(head, struct ixgbe_ring, rcu)); | |
5009 | } | |
5010 | ||
7a921c93 AD |
5011 | /** |
5012 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
5013 | * @adapter: board private structure to clear interrupt scheme on | |
5014 | * | |
5015 | * We go through and clear interrupt specific resources and reset the structure | |
5016 | * to pre-load conditions | |
5017 | **/ | |
5018 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
5019 | { | |
4a0b9ca0 PW |
5020 | int i; |
5021 | ||
5022 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
5023 | kfree(adapter->tx_ring[i]); | |
5024 | adapter->tx_ring[i] = NULL; | |
5025 | } | |
5026 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1a51502b ED |
5027 | struct ixgbe_ring *ring = adapter->rx_ring[i]; |
5028 | ||
5029 | /* ixgbe_get_stats64() might access this ring, we must wait | |
5030 | * a grace period before freeing it. | |
5031 | */ | |
5032 | call_rcu(&ring->rcu, ring_free_rcu); | |
4a0b9ca0 PW |
5033 | adapter->rx_ring[i] = NULL; |
5034 | } | |
7a921c93 | 5035 | |
b8eb3a10 DS |
5036 | adapter->num_tx_queues = 0; |
5037 | adapter->num_rx_queues = 0; | |
5038 | ||
7a921c93 AD |
5039 | ixgbe_free_q_vectors(adapter); |
5040 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
5041 | } |
5042 | ||
c4900be0 DS |
5043 | /** |
5044 | * ixgbe_sfp_timer - worker thread to find a missing module | |
5045 | * @data: pointer to our adapter struct | |
5046 | **/ | |
5047 | static void ixgbe_sfp_timer(unsigned long data) | |
5048 | { | |
5049 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
5050 | ||
4df10466 JB |
5051 | /* |
5052 | * Do the sfp_timer outside of interrupt context due to the | |
c4900be0 DS |
5053 | * delays that sfp+ detection requires |
5054 | */ | |
5055 | schedule_work(&adapter->sfp_task); | |
5056 | } | |
5057 | ||
5058 | /** | |
5059 | * ixgbe_sfp_task - worker thread to find a missing module | |
5060 | * @work: pointer to work_struct containing our data | |
5061 | **/ | |
5062 | static void ixgbe_sfp_task(struct work_struct *work) | |
5063 | { | |
5064 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
5065 | struct ixgbe_adapter, |
5066 | sfp_task); | |
c4900be0 DS |
5067 | struct ixgbe_hw *hw = &adapter->hw; |
5068 | ||
5069 | if ((hw->phy.type == ixgbe_phy_nl) && | |
5070 | (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { | |
5071 | s32 ret = hw->phy.ops.identify_sfp(hw); | |
63d6e1d8 | 5072 | if (ret == IXGBE_ERR_SFP_NOT_PRESENT) |
c4900be0 DS |
5073 | goto reschedule; |
5074 | ret = hw->phy.ops.reset(hw); | |
5075 | if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
849c4542 ET |
5076 | e_dev_err("failed to initialize because an unsupported " |
5077 | "SFP+ module type was detected.\n"); | |
5078 | e_dev_err("Reload the driver after installing a " | |
5079 | "supported module.\n"); | |
c4900be0 DS |
5080 | unregister_netdev(adapter->netdev); |
5081 | } else { | |
396e799c | 5082 | e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); |
c4900be0 DS |
5083 | } |
5084 | /* don't need this routine any more */ | |
5085 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
5086 | } | |
5087 | return; | |
5088 | reschedule: | |
5089 | if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) | |
5090 | mod_timer(&adapter->sfp_timer, | |
e8e9f696 | 5091 | round_jiffies(jiffies + (2 * HZ))); |
c4900be0 DS |
5092 | } |
5093 | ||
9a799d71 AK |
5094 | /** |
5095 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
5096 | * @adapter: board private structure to initialize | |
5097 | * | |
5098 | * ixgbe_sw_init initializes the Adapter private data structure. | |
5099 | * Fields are initialized based on PCI device information and | |
5100 | * OS network device settings (MTU size). | |
5101 | **/ | |
5102 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
5103 | { | |
5104 | struct ixgbe_hw *hw = &adapter->hw; | |
5105 | struct pci_dev *pdev = adapter->pdev; | |
9a713e7c | 5106 | struct net_device *dev = adapter->netdev; |
021230d4 | 5107 | unsigned int rss; |
7a6b6f51 | 5108 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
5109 | int j; |
5110 | struct tc_configuration *tc; | |
5111 | #endif | |
16b61beb | 5112 | int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 | 5113 | |
c44ade9e JB |
5114 | /* PCI config space info */ |
5115 | ||
5116 | hw->vendor_id = pdev->vendor; | |
5117 | hw->device_id = pdev->device; | |
5118 | hw->revision_id = pdev->revision; | |
5119 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
5120 | hw->subsystem_device_id = pdev->subsystem_device; | |
5121 | ||
021230d4 AV |
5122 | /* Set capability flags */ |
5123 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
5124 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
5125 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 5126 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
bd508178 AD |
5127 | switch (hw->mac.type) { |
5128 | case ixgbe_mac_82598EB: | |
bf069c97 DS |
5129 | if (hw->device_id == IXGBE_DEV_ID_82598AT) |
5130 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 5131 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bd508178 AD |
5132 | break; |
5133 | case ixgbe_mac_82599EB: | |
b93a2226 | 5134 | case ixgbe_mac_X540: |
e8e26350 | 5135 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
0c19d6af PWJ |
5136 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
5137 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
119fc60a MC |
5138 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) |
5139 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
45b9f509 AD |
5140 | /* n-tuple support exists, always init our spinlock */ |
5141 | spin_lock_init(&adapter->fdir_perfect_lock); | |
5142 | /* Flow Director hash filters enabled */ | |
5143 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
5144 | adapter->atr_sample_rate = 20; | |
c4cf55e5 | 5145 | adapter->ring_feature[RING_F_FDIR].indices = |
e8e9f696 | 5146 | IXGBE_MAX_FDIR_INDICES; |
c4cf55e5 | 5147 | adapter->fdir_pballoc = 0; |
eacd73f7 | 5148 | #ifdef IXGBE_FCOE |
0d551589 YZ |
5149 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
5150 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
5151 | adapter->ring_feature[RING_F_FCOE].indices = 0; | |
61a0f421 | 5152 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 YZ |
5153 | /* Default traffic class to use for FCoE */ |
5154 | adapter->fcoe.tc = IXGBE_FCOE_DEFTC; | |
56075a98 | 5155 | adapter->fcoe.up = IXGBE_FCOE_DEFTC; |
61a0f421 | 5156 | #endif |
eacd73f7 | 5157 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5158 | break; |
5159 | default: | |
5160 | break; | |
f8212f97 | 5161 | } |
2f90b865 | 5162 | |
7a6b6f51 | 5163 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
5164 | /* Configure DCB traffic classes */ |
5165 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
5166 | tc = &adapter->dcb_cfg.tc_config[j]; | |
5167 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
5168 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
5169 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
5170 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
5171 | tc->dcb_pfc = pfc_disabled; | |
5172 | } | |
5173 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
5174 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
5175 | adapter->dcb_cfg.rx_pba_cfg = pba_equal; | |
264857b8 | 5176 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 AD |
5177 | adapter->dcb_cfg.round_robin_enable = false; |
5178 | adapter->dcb_set_bitmap = 0x00; | |
5179 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, | |
e8e9f696 | 5180 | adapter->ring_feature[RING_F_DCB].indices); |
2f90b865 AD |
5181 | |
5182 | #endif | |
9a799d71 AK |
5183 | |
5184 | /* default flow control settings */ | |
cd7664f6 | 5185 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 5186 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
264857b8 PWJ |
5187 | #ifdef CONFIG_DCB |
5188 | adapter->last_lfc_mode = hw->fc.current_mode; | |
5189 | #endif | |
16b61beb JF |
5190 | hw->fc.high_water = FC_HIGH_WATER(max_frame); |
5191 | hw->fc.low_water = FC_LOW_WATER(max_frame); | |
2b9ade93 JB |
5192 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; |
5193 | hw->fc.send_xon = true; | |
71fd570b | 5194 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 5195 | |
30efa5a3 | 5196 | /* enable itr by default in dynamic mode */ |
f7554a2b NS |
5197 | adapter->rx_itr_setting = 1; |
5198 | adapter->rx_eitr_param = 20000; | |
5199 | adapter->tx_itr_setting = 1; | |
5200 | adapter->tx_eitr_param = 10000; | |
30efa5a3 JB |
5201 | |
5202 | /* set defaults for eitr in MegaBytes */ | |
5203 | adapter->eitr_low = 10; | |
5204 | adapter->eitr_high = 20; | |
5205 | ||
5206 | /* set default ring sizes */ | |
5207 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
5208 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
5209 | ||
9a799d71 | 5210 | /* initialize eeprom parameters */ |
c44ade9e | 5211 | if (ixgbe_init_eeprom_params_generic(hw)) { |
849c4542 | 5212 | e_dev_err("EEPROM initialization failed\n"); |
9a799d71 AK |
5213 | return -EIO; |
5214 | } | |
5215 | ||
021230d4 | 5216 | /* enable rx csum by default */ |
9a799d71 AK |
5217 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
5218 | ||
1a6c14a2 JB |
5219 | /* get assigned NUMA node */ |
5220 | adapter->node = dev_to_node(&pdev->dev); | |
5221 | ||
9a799d71 AK |
5222 | set_bit(__IXGBE_DOWN, &adapter->state); |
5223 | ||
5224 | return 0; | |
5225 | } | |
5226 | ||
5227 | /** | |
5228 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3a581073 | 5229 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
5230 | * |
5231 | * Return 0 on success, negative on failure | |
5232 | **/ | |
b6ec895e | 5233 | int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 5234 | { |
b6ec895e | 5235 | struct device *dev = tx_ring->dev; |
9a799d71 AK |
5236 | int size; |
5237 | ||
3a581073 | 5238 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
89bf67f1 | 5239 | tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node); |
1a6c14a2 | 5240 | if (!tx_ring->tx_buffer_info) |
89bf67f1 | 5241 | tx_ring->tx_buffer_info = vzalloc(size); |
e01c31a5 JB |
5242 | if (!tx_ring->tx_buffer_info) |
5243 | goto err; | |
9a799d71 AK |
5244 | |
5245 | /* round up to nearest 4K */ | |
12207e49 | 5246 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 5247 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 5248 | |
b6ec895e | 5249 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, |
1b507730 | 5250 | &tx_ring->dma, GFP_KERNEL); |
e01c31a5 JB |
5251 | if (!tx_ring->desc) |
5252 | goto err; | |
9a799d71 | 5253 | |
3a581073 JB |
5254 | tx_ring->next_to_use = 0; |
5255 | tx_ring->next_to_clean = 0; | |
5256 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 5257 | return 0; |
e01c31a5 JB |
5258 | |
5259 | err: | |
5260 | vfree(tx_ring->tx_buffer_info); | |
5261 | tx_ring->tx_buffer_info = NULL; | |
b6ec895e | 5262 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); |
e01c31a5 | 5263 | return -ENOMEM; |
9a799d71 AK |
5264 | } |
5265 | ||
69888674 AD |
5266 | /** |
5267 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
5268 | * @adapter: board private structure | |
5269 | * | |
5270 | * If this function returns with an error, then it's possible one or | |
5271 | * more of the rings is populated (while the rest are not). It is the | |
5272 | * callers duty to clean those orphaned rings. | |
5273 | * | |
5274 | * Return 0 on success, negative on failure | |
5275 | **/ | |
5276 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
5277 | { | |
5278 | int i, err = 0; | |
5279 | ||
5280 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
b6ec895e | 5281 | err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); |
69888674 AD |
5282 | if (!err) |
5283 | continue; | |
396e799c | 5284 | e_err(probe, "Allocation for Tx Queue %u failed\n", i); |
69888674 AD |
5285 | break; |
5286 | } | |
5287 | ||
5288 | return err; | |
5289 | } | |
5290 | ||
9a799d71 AK |
5291 | /** |
5292 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3a581073 | 5293 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
5294 | * |
5295 | * Returns 0 on success, negative on failure | |
5296 | **/ | |
b6ec895e | 5297 | int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 5298 | { |
b6ec895e | 5299 | struct device *dev = rx_ring->dev; |
021230d4 | 5300 | int size; |
9a799d71 | 5301 | |
3a581073 | 5302 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
89bf67f1 | 5303 | rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node); |
1a6c14a2 | 5304 | if (!rx_ring->rx_buffer_info) |
89bf67f1 | 5305 | rx_ring->rx_buffer_info = vzalloc(size); |
b6ec895e AD |
5306 | if (!rx_ring->rx_buffer_info) |
5307 | goto err; | |
9a799d71 | 5308 | |
9a799d71 | 5309 | /* Round up to nearest 4K */ |
3a581073 JB |
5310 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
5311 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 5312 | |
b6ec895e | 5313 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, |
1b507730 | 5314 | &rx_ring->dma, GFP_KERNEL); |
9a799d71 | 5315 | |
b6ec895e AD |
5316 | if (!rx_ring->desc) |
5317 | goto err; | |
9a799d71 | 5318 | |
3a581073 JB |
5319 | rx_ring->next_to_clean = 0; |
5320 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
5321 | |
5322 | return 0; | |
b6ec895e AD |
5323 | err: |
5324 | vfree(rx_ring->rx_buffer_info); | |
5325 | rx_ring->rx_buffer_info = NULL; | |
5326 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); | |
177db6ff | 5327 | return -ENOMEM; |
9a799d71 AK |
5328 | } |
5329 | ||
69888674 AD |
5330 | /** |
5331 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
5332 | * @adapter: board private structure | |
5333 | * | |
5334 | * If this function returns with an error, then it's possible one or | |
5335 | * more of the rings is populated (while the rest are not). It is the | |
5336 | * callers duty to clean those orphaned rings. | |
5337 | * | |
5338 | * Return 0 on success, negative on failure | |
5339 | **/ | |
69888674 AD |
5340 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) |
5341 | { | |
5342 | int i, err = 0; | |
5343 | ||
5344 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
b6ec895e | 5345 | err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); |
69888674 AD |
5346 | if (!err) |
5347 | continue; | |
396e799c | 5348 | e_err(probe, "Allocation for Rx Queue %u failed\n", i); |
69888674 AD |
5349 | break; |
5350 | } | |
5351 | ||
5352 | return err; | |
5353 | } | |
5354 | ||
9a799d71 AK |
5355 | /** |
5356 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
9a799d71 AK |
5357 | * @tx_ring: Tx descriptor ring for a specific queue |
5358 | * | |
5359 | * Free all transmit software resources | |
5360 | **/ | |
b6ec895e | 5361 | void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 5362 | { |
b6ec895e | 5363 | ixgbe_clean_tx_ring(tx_ring); |
9a799d71 AK |
5364 | |
5365 | vfree(tx_ring->tx_buffer_info); | |
5366 | tx_ring->tx_buffer_info = NULL; | |
5367 | ||
b6ec895e AD |
5368 | /* if not set, then don't free */ |
5369 | if (!tx_ring->desc) | |
5370 | return; | |
5371 | ||
5372 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
5373 | tx_ring->desc, tx_ring->dma); | |
9a799d71 AK |
5374 | |
5375 | tx_ring->desc = NULL; | |
5376 | } | |
5377 | ||
5378 | /** | |
5379 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
5380 | * @adapter: board private structure | |
5381 | * | |
5382 | * Free all transmit software resources | |
5383 | **/ | |
5384 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
5385 | { | |
5386 | int i; | |
5387 | ||
5388 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 5389 | if (adapter->tx_ring[i]->desc) |
b6ec895e | 5390 | ixgbe_free_tx_resources(adapter->tx_ring[i]); |
9a799d71 AK |
5391 | } |
5392 | ||
5393 | /** | |
b4617240 | 5394 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
5395 | * @rx_ring: ring to clean the resources from |
5396 | * | |
5397 | * Free all receive software resources | |
5398 | **/ | |
b6ec895e | 5399 | void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 5400 | { |
b6ec895e | 5401 | ixgbe_clean_rx_ring(rx_ring); |
9a799d71 AK |
5402 | |
5403 | vfree(rx_ring->rx_buffer_info); | |
5404 | rx_ring->rx_buffer_info = NULL; | |
5405 | ||
b6ec895e AD |
5406 | /* if not set, then don't free */ |
5407 | if (!rx_ring->desc) | |
5408 | return; | |
5409 | ||
5410 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
5411 | rx_ring->desc, rx_ring->dma); | |
9a799d71 AK |
5412 | |
5413 | rx_ring->desc = NULL; | |
5414 | } | |
5415 | ||
5416 | /** | |
5417 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
5418 | * @adapter: board private structure | |
5419 | * | |
5420 | * Free all receive software resources | |
5421 | **/ | |
5422 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
5423 | { | |
5424 | int i; | |
5425 | ||
5426 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 5427 | if (adapter->rx_ring[i]->desc) |
b6ec895e | 5428 | ixgbe_free_rx_resources(adapter->rx_ring[i]); |
9a799d71 AK |
5429 | } |
5430 | ||
9a799d71 AK |
5431 | /** |
5432 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
5433 | * @netdev: network interface device structure | |
5434 | * @new_mtu: new value for maximum frame size | |
5435 | * | |
5436 | * Returns 0 on success, negative on failure | |
5437 | **/ | |
5438 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
5439 | { | |
5440 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
16b61beb | 5441 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
5442 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; |
5443 | ||
42c783c5 JB |
5444 | /* MTU < 68 is an error and causes problems on some kernels */ |
5445 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
9a799d71 AK |
5446 | return -EINVAL; |
5447 | ||
396e799c | 5448 | e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
021230d4 | 5449 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
5450 | netdev->mtu = new_mtu; |
5451 | ||
16b61beb JF |
5452 | hw->fc.high_water = FC_HIGH_WATER(max_frame); |
5453 | hw->fc.low_water = FC_LOW_WATER(max_frame); | |
5454 | ||
d4f80882 AV |
5455 | if (netif_running(netdev)) |
5456 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
5457 | |
5458 | return 0; | |
5459 | } | |
5460 | ||
5461 | /** | |
5462 | * ixgbe_open - Called when a network interface is made active | |
5463 | * @netdev: network interface device structure | |
5464 | * | |
5465 | * Returns 0 on success, negative value on failure | |
5466 | * | |
5467 | * The open entry point is called when a network interface is made | |
5468 | * active by the system (IFF_UP). At this point all resources needed | |
5469 | * for transmit and receive operations are allocated, the interrupt | |
5470 | * handler is registered with the OS, the watchdog timer is started, | |
5471 | * and the stack is notified that the interface is ready. | |
5472 | **/ | |
5473 | static int ixgbe_open(struct net_device *netdev) | |
5474 | { | |
5475 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5476 | int err; | |
4bebfaa5 AK |
5477 | |
5478 | /* disallow open during test */ | |
5479 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
5480 | return -EBUSY; | |
9a799d71 | 5481 | |
54386467 JB |
5482 | netif_carrier_off(netdev); |
5483 | ||
9a799d71 AK |
5484 | /* allocate transmit descriptors */ |
5485 | err = ixgbe_setup_all_tx_resources(adapter); | |
5486 | if (err) | |
5487 | goto err_setup_tx; | |
5488 | ||
9a799d71 AK |
5489 | /* allocate receive descriptors */ |
5490 | err = ixgbe_setup_all_rx_resources(adapter); | |
5491 | if (err) | |
5492 | goto err_setup_rx; | |
5493 | ||
5494 | ixgbe_configure(adapter); | |
5495 | ||
021230d4 | 5496 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
5497 | if (err) |
5498 | goto err_req_irq; | |
5499 | ||
9a799d71 AK |
5500 | err = ixgbe_up_complete(adapter); |
5501 | if (err) | |
5502 | goto err_up; | |
5503 | ||
d55b53ff JK |
5504 | netif_tx_start_all_queues(netdev); |
5505 | ||
9a799d71 AK |
5506 | return 0; |
5507 | ||
5508 | err_up: | |
5eba3699 | 5509 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5510 | ixgbe_free_irq(adapter); |
5511 | err_req_irq: | |
9a799d71 | 5512 | err_setup_rx: |
a20a1199 | 5513 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 5514 | err_setup_tx: |
a20a1199 | 5515 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
5516 | ixgbe_reset(adapter); |
5517 | ||
5518 | return err; | |
5519 | } | |
5520 | ||
5521 | /** | |
5522 | * ixgbe_close - Disables a network interface | |
5523 | * @netdev: network interface device structure | |
5524 | * | |
5525 | * Returns 0, this is not allowed to fail | |
5526 | * | |
5527 | * The close entry point is called when an interface is de-activated | |
5528 | * by the OS. The hardware is still under the drivers control, but | |
5529 | * needs to be disabled. A global MAC reset is issued to stop the | |
5530 | * hardware, and all transmit and receive resources are freed. | |
5531 | **/ | |
5532 | static int ixgbe_close(struct net_device *netdev) | |
5533 | { | |
5534 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
5535 | |
5536 | ixgbe_down(adapter); | |
5537 | ixgbe_free_irq(adapter); | |
5538 | ||
5539 | ixgbe_free_all_tx_resources(adapter); | |
5540 | ixgbe_free_all_rx_resources(adapter); | |
5541 | ||
5eba3699 | 5542 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5543 | |
5544 | return 0; | |
5545 | } | |
5546 | ||
b3c8b4ba AD |
5547 | #ifdef CONFIG_PM |
5548 | static int ixgbe_resume(struct pci_dev *pdev) | |
5549 | { | |
c60fbb00 AD |
5550 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
5551 | struct net_device *netdev = adapter->netdev; | |
b3c8b4ba AD |
5552 | u32 err; |
5553 | ||
5554 | pci_set_power_state(pdev, PCI_D0); | |
5555 | pci_restore_state(pdev); | |
656ab817 DS |
5556 | /* |
5557 | * pci_restore_state clears dev->state_saved so call | |
5558 | * pci_save_state to restore it. | |
5559 | */ | |
5560 | pci_save_state(pdev); | |
9ce77666 | 5561 | |
5562 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 5563 | if (err) { |
849c4542 | 5564 | e_dev_err("Cannot enable PCI device from suspend\n"); |
b3c8b4ba AD |
5565 | return err; |
5566 | } | |
5567 | pci_set_master(pdev); | |
5568 | ||
dd4d8ca6 | 5569 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
5570 | |
5571 | err = ixgbe_init_interrupt_scheme(adapter); | |
5572 | if (err) { | |
849c4542 | 5573 | e_dev_err("Cannot initialize interrupts for device\n"); |
b3c8b4ba AD |
5574 | return err; |
5575 | } | |
5576 | ||
b3c8b4ba AD |
5577 | ixgbe_reset(adapter); |
5578 | ||
495dce12 WJP |
5579 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
5580 | ||
b3c8b4ba | 5581 | if (netif_running(netdev)) { |
c60fbb00 | 5582 | err = ixgbe_open(netdev); |
b3c8b4ba AD |
5583 | if (err) |
5584 | return err; | |
5585 | } | |
5586 | ||
5587 | netif_device_attach(netdev); | |
5588 | ||
5589 | return 0; | |
5590 | } | |
b3c8b4ba | 5591 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
5592 | |
5593 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba | 5594 | { |
c60fbb00 AD |
5595 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
5596 | struct net_device *netdev = adapter->netdev; | |
e8e26350 PW |
5597 | struct ixgbe_hw *hw = &adapter->hw; |
5598 | u32 ctrl, fctrl; | |
5599 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
5600 | #ifdef CONFIG_PM |
5601 | int retval = 0; | |
5602 | #endif | |
5603 | ||
5604 | netif_device_detach(netdev); | |
5605 | ||
5606 | if (netif_running(netdev)) { | |
5607 | ixgbe_down(adapter); | |
5608 | ixgbe_free_irq(adapter); | |
5609 | ixgbe_free_all_tx_resources(adapter); | |
5610 | ixgbe_free_all_rx_resources(adapter); | |
5611 | } | |
b3c8b4ba | 5612 | |
5f5ae6fc AD |
5613 | ixgbe_clear_interrupt_scheme(adapter); |
5614 | ||
b3c8b4ba AD |
5615 | #ifdef CONFIG_PM |
5616 | retval = pci_save_state(pdev); | |
5617 | if (retval) | |
5618 | return retval; | |
4df10466 | 5619 | |
b3c8b4ba | 5620 | #endif |
e8e26350 PW |
5621 | if (wufc) { |
5622 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 5623 | |
e8e26350 PW |
5624 | /* turn on all-multi mode if wake on multicast is enabled */ |
5625 | if (wufc & IXGBE_WUFC_MC) { | |
5626 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5627 | fctrl |= IXGBE_FCTRL_MPE; | |
5628 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
5629 | } | |
5630 | ||
5631 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
5632 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
5633 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
5634 | ||
5635 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
5636 | } else { | |
5637 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
5638 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
5639 | } | |
5640 | ||
bd508178 AD |
5641 | switch (hw->mac.type) { |
5642 | case ixgbe_mac_82598EB: | |
dd4d8ca6 | 5643 | pci_wake_from_d3(pdev, false); |
bd508178 AD |
5644 | break; |
5645 | case ixgbe_mac_82599EB: | |
b93a2226 | 5646 | case ixgbe_mac_X540: |
bd508178 AD |
5647 | pci_wake_from_d3(pdev, !!wufc); |
5648 | break; | |
5649 | default: | |
5650 | break; | |
5651 | } | |
b3c8b4ba | 5652 | |
9d8d05ae RW |
5653 | *enable_wake = !!wufc; |
5654 | ||
b3c8b4ba AD |
5655 | ixgbe_release_hw_control(adapter); |
5656 | ||
5657 | pci_disable_device(pdev); | |
5658 | ||
9d8d05ae RW |
5659 | return 0; |
5660 | } | |
5661 | ||
5662 | #ifdef CONFIG_PM | |
5663 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
5664 | { | |
5665 | int retval; | |
5666 | bool wake; | |
5667 | ||
5668 | retval = __ixgbe_shutdown(pdev, &wake); | |
5669 | if (retval) | |
5670 | return retval; | |
5671 | ||
5672 | if (wake) { | |
5673 | pci_prepare_to_sleep(pdev); | |
5674 | } else { | |
5675 | pci_wake_from_d3(pdev, false); | |
5676 | pci_set_power_state(pdev, PCI_D3hot); | |
5677 | } | |
b3c8b4ba AD |
5678 | |
5679 | return 0; | |
5680 | } | |
9d8d05ae | 5681 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
5682 | |
5683 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
5684 | { | |
9d8d05ae RW |
5685 | bool wake; |
5686 | ||
5687 | __ixgbe_shutdown(pdev, &wake); | |
5688 | ||
5689 | if (system_state == SYSTEM_POWER_OFF) { | |
5690 | pci_wake_from_d3(pdev, wake); | |
5691 | pci_set_power_state(pdev, PCI_D3hot); | |
5692 | } | |
b3c8b4ba AD |
5693 | } |
5694 | ||
9a799d71 AK |
5695 | /** |
5696 | * ixgbe_update_stats - Update the board statistics counters. | |
5697 | * @adapter: board private structure | |
5698 | **/ | |
5699 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
5700 | { | |
2d86f139 | 5701 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 5702 | struct ixgbe_hw *hw = &adapter->hw; |
5b7da515 | 5703 | struct ixgbe_hw_stats *hwstats = &adapter->stats; |
6f11eef7 AV |
5704 | u64 total_mpc = 0; |
5705 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
5b7da515 AD |
5706 | u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; |
5707 | u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; | |
5708 | u64 bytes = 0, packets = 0; | |
9a799d71 | 5709 | |
d08935c2 DS |
5710 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5711 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5712 | return; | |
5713 | ||
94b982b2 | 5714 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 5715 | u64 rsc_count = 0; |
94b982b2 | 5716 | u64 rsc_flush = 0; |
d51019a4 PW |
5717 | for (i = 0; i < 16; i++) |
5718 | adapter->hw_rx_no_dma_resources += | |
7ca647bd | 5719 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); |
94b982b2 | 5720 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5b7da515 AD |
5721 | rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; |
5722 | rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; | |
94b982b2 MC |
5723 | } |
5724 | adapter->rsc_total_count = rsc_count; | |
5725 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
5726 | } |
5727 | ||
5b7da515 AD |
5728 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5729 | struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; | |
5730 | non_eop_descs += rx_ring->rx_stats.non_eop_descs; | |
5731 | alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; | |
5732 | alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; | |
5733 | bytes += rx_ring->stats.bytes; | |
5734 | packets += rx_ring->stats.packets; | |
5735 | } | |
5736 | adapter->non_eop_descs = non_eop_descs; | |
5737 | adapter->alloc_rx_page_failed = alloc_rx_page_failed; | |
5738 | adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; | |
5739 | netdev->stats.rx_bytes = bytes; | |
5740 | netdev->stats.rx_packets = packets; | |
5741 | ||
5742 | bytes = 0; | |
5743 | packets = 0; | |
7ca3bc58 | 5744 | /* gather some stats to the adapter struct that are per queue */ |
5b7da515 AD |
5745 | for (i = 0; i < adapter->num_tx_queues; i++) { |
5746 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
5747 | restart_queue += tx_ring->tx_stats.restart_queue; | |
5748 | tx_busy += tx_ring->tx_stats.tx_busy; | |
5749 | bytes += tx_ring->stats.bytes; | |
5750 | packets += tx_ring->stats.packets; | |
5751 | } | |
eb985f09 | 5752 | adapter->restart_queue = restart_queue; |
5b7da515 AD |
5753 | adapter->tx_busy = tx_busy; |
5754 | netdev->stats.tx_bytes = bytes; | |
5755 | netdev->stats.tx_packets = packets; | |
7ca3bc58 | 5756 | |
7ca647bd | 5757 | hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
6f11eef7 AV |
5758 | for (i = 0; i < 8; i++) { |
5759 | /* for packet buffers not used, the register should read 0 */ | |
5760 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
5761 | missed_rx += mpc; | |
7ca647bd JP |
5762 | hwstats->mpc[i] += mpc; |
5763 | total_mpc += hwstats->mpc[i]; | |
e8e26350 | 5764 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
5765 | hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
5766 | hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
5767 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
5768 | hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
5769 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
bd508178 AD |
5770 | switch (hw->mac.type) { |
5771 | case ixgbe_mac_82598EB: | |
7ca647bd JP |
5772 | hwstats->pxonrxc[i] += |
5773 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
bd508178 AD |
5774 | break; |
5775 | case ixgbe_mac_82599EB: | |
b93a2226 | 5776 | case ixgbe_mac_X540: |
bd508178 AD |
5777 | hwstats->pxonrxc[i] += |
5778 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
bd508178 AD |
5779 | break; |
5780 | default: | |
5781 | break; | |
e8e26350 | 5782 | } |
7ca647bd JP |
5783 | hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
5784 | hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
6f11eef7 | 5785 | } |
7ca647bd | 5786 | hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); |
6f11eef7 | 5787 | /* work around hardware counting issue */ |
7ca647bd | 5788 | hwstats->gprc -= missed_rx; |
6f11eef7 | 5789 | |
c84d324c JF |
5790 | ixgbe_update_xoff_received(adapter); |
5791 | ||
6f11eef7 | 5792 | /* 82598 hardware only has a 32 bit counter in the high register */ |
bd508178 AD |
5793 | switch (hw->mac.type) { |
5794 | case ixgbe_mac_82598EB: | |
5795 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
bd508178 AD |
5796 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
5797 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
5798 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
5799 | break; | |
5800 | case ixgbe_mac_82599EB: | |
b93a2226 | 5801 | case ixgbe_mac_X540: |
7ca647bd | 5802 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
bd508178 | 5803 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ |
7ca647bd | 5804 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
bd508178 | 5805 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ |
7ca647bd | 5806 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
bd508178 | 5807 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
7ca647bd | 5808 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
7ca647bd JP |
5809 | hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
5810 | hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c | 5811 | #ifdef IXGBE_FCOE |
7ca647bd JP |
5812 | hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); |
5813 | hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
5814 | hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
5815 | hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
5816 | hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
5817 | hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
6d45522c | 5818 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5819 | break; |
5820 | default: | |
5821 | break; | |
e8e26350 | 5822 | } |
9a799d71 | 5823 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
7ca647bd JP |
5824 | hwstats->bprc += bprc; |
5825 | hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 | 5826 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
5827 | hwstats->mprc -= bprc; |
5828 | hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
5829 | hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
5830 | hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
5831 | hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
5832 | hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
5833 | hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
5834 | hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
5835 | hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); | |
6f11eef7 | 5836 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
7ca647bd | 5837 | hwstats->lxontxc += lxon; |
6f11eef7 | 5838 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
7ca647bd JP |
5839 | hwstats->lxofftxc += lxoff; |
5840 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
5841 | hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
5842 | hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); | |
6f11eef7 AV |
5843 | /* |
5844 | * 82598 errata - tx of flow control packets is included in tx counters | |
5845 | */ | |
5846 | xon_off_tot = lxon + lxoff; | |
7ca647bd JP |
5847 | hwstats->gptc -= xon_off_tot; |
5848 | hwstats->mptc -= xon_off_tot; | |
5849 | hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
5850 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
5851 | hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
5852 | hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
5853 | hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); | |
5854 | hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
5855 | hwstats->ptc64 -= xon_off_tot; | |
5856 | hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); | |
5857 | hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
5858 | hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
5859 | hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
5860 | hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
5861 | hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); | |
9a799d71 AK |
5862 | |
5863 | /* Fill out the OS statistics structure */ | |
7ca647bd | 5864 | netdev->stats.multicast = hwstats->mprc; |
9a799d71 AK |
5865 | |
5866 | /* Rx Errors */ | |
7ca647bd | 5867 | netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; |
2d86f139 | 5868 | netdev->stats.rx_dropped = 0; |
7ca647bd JP |
5869 | netdev->stats.rx_length_errors = hwstats->rlec; |
5870 | netdev->stats.rx_crc_errors = hwstats->crcerrs; | |
2d86f139 | 5871 | netdev->stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
5872 | } |
5873 | ||
5874 | /** | |
5875 | * ixgbe_watchdog - Timer Call-back | |
5876 | * @data: pointer to adapter cast into an unsigned long | |
5877 | **/ | |
5878 | static void ixgbe_watchdog(unsigned long data) | |
5879 | { | |
5880 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee | 5881 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
5882 | u64 eics = 0; |
5883 | int i; | |
cf8280ee | 5884 | |
fe49f04a AD |
5885 | /* |
5886 | * Do the watchdog outside of interrupt context due to the lovely | |
5887 | * delays that some of the newer hardware requires | |
5888 | */ | |
22d5a71b | 5889 | |
fe49f04a AD |
5890 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
5891 | goto watchdog_short_circuit; | |
22d5a71b | 5892 | |
fe49f04a AD |
5893 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
5894 | /* | |
5895 | * for legacy and MSI interrupts don't set any bits | |
5896 | * that are enabled for EIAM, because this operation | |
5897 | * would set *both* EIMS and EICS for any bit in EIAM | |
5898 | */ | |
5899 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
5900 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
5901 | goto watchdog_reschedule; | |
5902 | } | |
5903 | ||
5904 | /* get one bit for every active tx/rx interrupt vector */ | |
5905 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { | |
5906 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; | |
5907 | if (qv->rxr_count || qv->txr_count) | |
5908 | eics |= ((u64)1 << i); | |
cf8280ee | 5909 | } |
9a799d71 | 5910 | |
fe49f04a AD |
5911 | /* Cause software interrupt to ensure rx rings are cleaned */ |
5912 | ixgbe_irq_rearm_queues(adapter, eics); | |
5913 | ||
5914 | watchdog_reschedule: | |
5915 | /* Reset the timer */ | |
5916 | mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ)); | |
5917 | ||
5918 | watchdog_short_circuit: | |
cf8280ee JB |
5919 | schedule_work(&adapter->watchdog_task); |
5920 | } | |
5921 | ||
e8e26350 PW |
5922 | /** |
5923 | * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber | |
5924 | * @work: pointer to work_struct containing our data | |
5925 | **/ | |
5926 | static void ixgbe_multispeed_fiber_task(struct work_struct *work) | |
5927 | { | |
5928 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
5929 | struct ixgbe_adapter, |
5930 | multispeed_fiber_task); | |
e8e26350 PW |
5931 | struct ixgbe_hw *hw = &adapter->hw; |
5932 | u32 autoneg; | |
8620a103 | 5933 | bool negotiation; |
e8e26350 PW |
5934 | |
5935 | adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK; | |
a1f25324 MC |
5936 | autoneg = hw->phy.autoneg_advertised; |
5937 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
8620a103 | 5938 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); |
1097cd17 | 5939 | hw->mac.autotry_restart = false; |
8620a103 MC |
5940 | if (hw->mac.ops.setup_link) |
5941 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
e8e26350 PW |
5942 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
5943 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK; | |
5944 | } | |
5945 | ||
5946 | /** | |
5947 | * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module | |
5948 | * @work: pointer to work_struct containing our data | |
5949 | **/ | |
5950 | static void ixgbe_sfp_config_module_task(struct work_struct *work) | |
5951 | { | |
5952 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
5953 | struct ixgbe_adapter, |
5954 | sfp_config_module_task); | |
e8e26350 PW |
5955 | struct ixgbe_hw *hw = &adapter->hw; |
5956 | u32 err; | |
5957 | ||
5958 | adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK; | |
63d6e1d8 DS |
5959 | |
5960 | /* Time for electrical oscillations to settle down */ | |
5961 | msleep(100); | |
e8e26350 | 5962 | err = hw->phy.ops.identify_sfp(hw); |
63d6e1d8 | 5963 | |
e8e26350 | 5964 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { |
849c4542 ET |
5965 | e_dev_err("failed to initialize because an unsupported SFP+ " |
5966 | "module type was detected.\n"); | |
5967 | e_dev_err("Reload the driver after installing a supported " | |
5968 | "module.\n"); | |
63d6e1d8 | 5969 | unregister_netdev(adapter->netdev); |
e8e26350 PW |
5970 | return; |
5971 | } | |
4c7e604b AG |
5972 | if (hw->mac.ops.setup_sfp) |
5973 | hw->mac.ops.setup_sfp(hw); | |
e8e26350 | 5974 | |
8d1c3c07 | 5975 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) |
e8e26350 PW |
5976 | /* This will also work for DA Twinax connections */ |
5977 | schedule_work(&adapter->multispeed_fiber_task); | |
5978 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK; | |
5979 | } | |
5980 | ||
c4cf55e5 PWJ |
5981 | /** |
5982 | * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table | |
5983 | * @work: pointer to work_struct containing our data | |
5984 | **/ | |
5985 | static void ixgbe_fdir_reinit_task(struct work_struct *work) | |
5986 | { | |
5987 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
5988 | struct ixgbe_adapter, |
5989 | fdir_reinit_task); | |
c4cf55e5 PWJ |
5990 | struct ixgbe_hw *hw = &adapter->hw; |
5991 | int i; | |
5992 | ||
5993 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { | |
5994 | for (i = 0; i < adapter->num_tx_queues; i++) | |
7d637bcc AD |
5995 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, |
5996 | &(adapter->tx_ring[i]->state)); | |
c4cf55e5 | 5997 | } else { |
396e799c | 5998 | e_err(probe, "failed to finish FDIR re-initialization, " |
849c4542 | 5999 | "ignored adding FDIR ATR filters\n"); |
c4cf55e5 PWJ |
6000 | } |
6001 | /* Done FDIR Re-initialization, enable transmits */ | |
6002 | netif_tx_start_all_queues(adapter->netdev); | |
6003 | } | |
6004 | ||
a985b6c3 GR |
6005 | static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) |
6006 | { | |
6007 | u32 ssvpc; | |
6008 | ||
6009 | /* Do not perform spoof check for 82598 */ | |
6010 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
6011 | return; | |
6012 | ||
6013 | ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); | |
6014 | ||
6015 | /* | |
6016 | * ssvpc register is cleared on read, if zero then no | |
6017 | * spoofed packets in the last interval. | |
6018 | */ | |
6019 | if (!ssvpc) | |
6020 | return; | |
6021 | ||
6022 | e_warn(drv, "%d Spoofed packets detected\n", ssvpc); | |
6023 | } | |
6024 | ||
10eec955 JF |
6025 | static DEFINE_MUTEX(ixgbe_watchdog_lock); |
6026 | ||
cf8280ee | 6027 | /** |
69888674 AD |
6028 | * ixgbe_watchdog_task - worker thread to bring link up |
6029 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
6030 | **/ |
6031 | static void ixgbe_watchdog_task(struct work_struct *work) | |
6032 | { | |
6033 | struct ixgbe_adapter *adapter = container_of(work, | |
e8e9f696 JP |
6034 | struct ixgbe_adapter, |
6035 | watchdog_task); | |
cf8280ee JB |
6036 | struct net_device *netdev = adapter->netdev; |
6037 | struct ixgbe_hw *hw = &adapter->hw; | |
10eec955 JF |
6038 | u32 link_speed; |
6039 | bool link_up; | |
bc59fcda NS |
6040 | int i; |
6041 | struct ixgbe_ring *tx_ring; | |
6042 | int some_tx_pending = 0; | |
cf8280ee | 6043 | |
10eec955 JF |
6044 | mutex_lock(&ixgbe_watchdog_lock); |
6045 | ||
6046 | link_up = adapter->link_up; | |
6047 | link_speed = adapter->link_speed; | |
cf8280ee JB |
6048 | |
6049 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
6050 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
264857b8 PWJ |
6051 | if (link_up) { |
6052 | #ifdef CONFIG_DCB | |
6053 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
6054 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) | |
620fa036 | 6055 | hw->mac.ops.fc_enable(hw, i); |
264857b8 | 6056 | } else { |
620fa036 | 6057 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
6058 | } |
6059 | #else | |
620fa036 | 6060 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
6061 | #endif |
6062 | } | |
6063 | ||
cf8280ee JB |
6064 | if (link_up || |
6065 | time_after(jiffies, (adapter->link_check_timeout + | |
e8e9f696 | 6066 | IXGBE_TRY_LINK_TIMEOUT))) { |
cf8280ee | 6067 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
264857b8 | 6068 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); |
cf8280ee JB |
6069 | } |
6070 | adapter->link_up = link_up; | |
6071 | adapter->link_speed = link_speed; | |
6072 | } | |
9a799d71 AK |
6073 | |
6074 | if (link_up) { | |
6075 | if (!netif_carrier_ok(netdev)) { | |
e8e26350 PW |
6076 | bool flow_rx, flow_tx; |
6077 | ||
bd508178 AD |
6078 | switch (hw->mac.type) { |
6079 | case ixgbe_mac_82598EB: { | |
e8e26350 PW |
6080 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
6081 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
078788b6 PWJ |
6082 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); |
6083 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
e8e26350 | 6084 | } |
bd508178 | 6085 | break; |
b93a2226 DS |
6086 | case ixgbe_mac_82599EB: |
6087 | case ixgbe_mac_X540: { | |
bd508178 AD |
6088 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); |
6089 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
6090 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); | |
6091 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
6092 | } | |
6093 | break; | |
6094 | default: | |
6095 | flow_tx = false; | |
6096 | flow_rx = false; | |
6097 | break; | |
6098 | } | |
e8e26350 | 6099 | |
396e799c | 6100 | e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", |
a46e534b | 6101 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? |
849c4542 ET |
6102 | "10 Gbps" : |
6103 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
6104 | "1 Gbps" : "unknown speed")), | |
e8e26350 | 6105 | ((flow_rx && flow_tx) ? "RX/TX" : |
849c4542 ET |
6106 | (flow_rx ? "RX" : |
6107 | (flow_tx ? "TX" : "None")))); | |
9a799d71 AK |
6108 | |
6109 | netif_carrier_on(netdev); | |
9a799d71 AK |
6110 | } else { |
6111 | /* Force detection of hung controller */ | |
7d637bcc AD |
6112 | for (i = 0; i < adapter->num_tx_queues; i++) { |
6113 | tx_ring = adapter->tx_ring[i]; | |
6114 | set_check_for_tx_hang(tx_ring); | |
6115 | } | |
9a799d71 AK |
6116 | } |
6117 | } else { | |
cf8280ee JB |
6118 | adapter->link_up = false; |
6119 | adapter->link_speed = 0; | |
9a799d71 | 6120 | if (netif_carrier_ok(netdev)) { |
396e799c | 6121 | e_info(drv, "NIC Link is Down\n"); |
9a799d71 | 6122 | netif_carrier_off(netdev); |
9a799d71 AK |
6123 | } |
6124 | } | |
6125 | ||
bc59fcda NS |
6126 | if (!netif_carrier_ok(netdev)) { |
6127 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4a0b9ca0 | 6128 | tx_ring = adapter->tx_ring[i]; |
bc59fcda NS |
6129 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { |
6130 | some_tx_pending = 1; | |
6131 | break; | |
6132 | } | |
6133 | } | |
6134 | ||
6135 | if (some_tx_pending) { | |
6136 | /* We've lost link, so the controller stops DMA, | |
6137 | * but we've got queued Tx work that's never going | |
6138 | * to get done, so reset controller to flush Tx. | |
6139 | * (Do the reset outside of interrupt context). | |
6140 | */ | |
6141 | schedule_work(&adapter->reset_task); | |
6142 | } | |
6143 | } | |
6144 | ||
a985b6c3 | 6145 | ixgbe_spoof_check(adapter); |
9a799d71 | 6146 | ixgbe_update_stats(adapter); |
10eec955 | 6147 | mutex_unlock(&ixgbe_watchdog_lock); |
9a799d71 AK |
6148 | } |
6149 | ||
9a799d71 | 6150 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
e8e9f696 | 6151 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
5e09a105 | 6152 | u32 tx_flags, u8 *hdr_len, __be16 protocol) |
9a799d71 AK |
6153 | { |
6154 | struct ixgbe_adv_tx_context_desc *context_desc; | |
6155 | unsigned int i; | |
6156 | int err; | |
6157 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
6158 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
6159 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
6160 | |
6161 | if (skb_is_gso(skb)) { | |
6162 | if (skb_header_cloned(skb)) { | |
6163 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
6164 | if (err) | |
6165 | return err; | |
6166 | } | |
6167 | l4len = tcp_hdrlen(skb); | |
6168 | *hdr_len += l4len; | |
6169 | ||
5e09a105 | 6170 | if (protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
6171 | struct iphdr *iph = ip_hdr(skb); |
6172 | iph->tot_len = 0; | |
6173 | iph->check = 0; | |
6174 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
e8e9f696 JP |
6175 | iph->daddr, 0, |
6176 | IPPROTO_TCP, | |
6177 | 0); | |
8e1e8a47 | 6178 | } else if (skb_is_gso_v6(skb)) { |
9a799d71 AK |
6179 | ipv6_hdr(skb)->payload_len = 0; |
6180 | tcp_hdr(skb)->check = | |
6181 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
e8e9f696 JP |
6182 | &ipv6_hdr(skb)->daddr, |
6183 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
6184 | } |
6185 | ||
6186 | i = tx_ring->next_to_use; | |
6187 | ||
6188 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
31f05a2d | 6189 | context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i); |
9a799d71 AK |
6190 | |
6191 | /* VLAN MACLEN IPLEN */ | |
6192 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
6193 | vlan_macip_lens |= | |
6194 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
6195 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
e8e9f696 | 6196 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
6197 | *hdr_len += skb_network_offset(skb); |
6198 | vlan_macip_lens |= | |
6199 | (skb_transport_header(skb) - skb_network_header(skb)); | |
6200 | *hdr_len += | |
6201 | (skb_transport_header(skb) - skb_network_header(skb)); | |
6202 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
6203 | context_desc->seqnum_seed = 0; | |
6204 | ||
6205 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 6206 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
e8e9f696 | 6207 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 6208 | |
5e09a105 | 6209 | if (protocol == htons(ETH_P_IP)) |
9a799d71 AK |
6210 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
6211 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
6212 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
6213 | ||
6214 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 6215 | mss_l4len_idx = |
9a799d71 AK |
6216 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
6217 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
6218 | /* use index 1 for TSO */ |
6219 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
6220 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
6221 | ||
6222 | tx_buffer_info->time_stamp = jiffies; | |
6223 | tx_buffer_info->next_to_watch = i; | |
6224 | ||
6225 | i++; | |
6226 | if (i == tx_ring->count) | |
6227 | i = 0; | |
6228 | tx_ring->next_to_use = i; | |
6229 | ||
6230 | return true; | |
6231 | } | |
6232 | return false; | |
6233 | } | |
6234 | ||
5e09a105 HZ |
6235 | static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb, |
6236 | __be16 protocol) | |
7ca647bd JP |
6237 | { |
6238 | u32 rtn = 0; | |
7ca647bd JP |
6239 | |
6240 | switch (protocol) { | |
6241 | case cpu_to_be16(ETH_P_IP): | |
6242 | rtn |= IXGBE_ADVTXD_TUCMD_IPV4; | |
6243 | switch (ip_hdr(skb)->protocol) { | |
6244 | case IPPROTO_TCP: | |
6245 | rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
6246 | break; | |
6247 | case IPPROTO_SCTP: | |
6248 | rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
6249 | break; | |
6250 | } | |
6251 | break; | |
6252 | case cpu_to_be16(ETH_P_IPV6): | |
6253 | /* XXX what about other V6 headers?? */ | |
6254 | switch (ipv6_hdr(skb)->nexthdr) { | |
6255 | case IPPROTO_TCP: | |
6256 | rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
6257 | break; | |
6258 | case IPPROTO_SCTP: | |
6259 | rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
6260 | break; | |
6261 | } | |
6262 | break; | |
6263 | default: | |
6264 | if (unlikely(net_ratelimit())) | |
6265 | e_warn(probe, "partial checksum but proto=%x!\n", | |
5e09a105 | 6266 | protocol); |
7ca647bd JP |
6267 | break; |
6268 | } | |
6269 | ||
6270 | return rtn; | |
6271 | } | |
6272 | ||
9a799d71 | 6273 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, |
e8e9f696 | 6274 | struct ixgbe_ring *tx_ring, |
5e09a105 HZ |
6275 | struct sk_buff *skb, u32 tx_flags, |
6276 | __be16 protocol) | |
9a799d71 AK |
6277 | { |
6278 | struct ixgbe_adv_tx_context_desc *context_desc; | |
6279 | unsigned int i; | |
6280 | struct ixgbe_tx_buffer *tx_buffer_info; | |
6281 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
6282 | ||
6283 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
6284 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
6285 | i = tx_ring->next_to_use; | |
6286 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
31f05a2d | 6287 | context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i); |
9a799d71 AK |
6288 | |
6289 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
6290 | vlan_macip_lens |= | |
6291 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
6292 | vlan_macip_lens |= (skb_network_offset(skb) << | |
e8e9f696 | 6293 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
6294 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
6295 | vlan_macip_lens |= (skb_transport_header(skb) - | |
e8e9f696 | 6296 | skb_network_header(skb)); |
9a799d71 AK |
6297 | |
6298 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
6299 | context_desc->seqnum_seed = 0; | |
6300 | ||
6301 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
e8e9f696 | 6302 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 6303 | |
7ca647bd | 6304 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
5e09a105 | 6305 | type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol); |
9a799d71 AK |
6306 | |
6307 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 6308 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
6309 | context_desc->mss_l4len_idx = 0; |
6310 | ||
6311 | tx_buffer_info->time_stamp = jiffies; | |
6312 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 6313 | |
9a799d71 AK |
6314 | i++; |
6315 | if (i == tx_ring->count) | |
6316 | i = 0; | |
6317 | tx_ring->next_to_use = i; | |
6318 | ||
6319 | return true; | |
6320 | } | |
9f8cdf4f | 6321 | |
9a799d71 AK |
6322 | return false; |
6323 | } | |
6324 | ||
6325 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
e8e9f696 JP |
6326 | struct ixgbe_ring *tx_ring, |
6327 | struct sk_buff *skb, u32 tx_flags, | |
8ad494b0 | 6328 | unsigned int first, const u8 hdr_len) |
9a799d71 | 6329 | { |
b6ec895e | 6330 | struct device *dev = tx_ring->dev; |
9a799d71 | 6331 | struct ixgbe_tx_buffer *tx_buffer_info; |
eacd73f7 YZ |
6332 | unsigned int len; |
6333 | unsigned int total = skb->len; | |
9a799d71 AK |
6334 | unsigned int offset = 0, size, count = 0, i; |
6335 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
6336 | unsigned int f; | |
8ad494b0 AD |
6337 | unsigned int bytecount = skb->len; |
6338 | u16 gso_segs = 1; | |
9a799d71 AK |
6339 | |
6340 | i = tx_ring->next_to_use; | |
6341 | ||
eacd73f7 YZ |
6342 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) |
6343 | /* excluding fcoe_crc_eof for FCoE */ | |
6344 | total -= sizeof(struct fcoe_crc_eof); | |
6345 | ||
6346 | len = min(skb_headlen(skb), total); | |
9a799d71 AK |
6347 | while (len) { |
6348 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
6349 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
6350 | ||
6351 | tx_buffer_info->length = size; | |
e5a43549 | 6352 | tx_buffer_info->mapped_as_page = false; |
b6ec895e | 6353 | tx_buffer_info->dma = dma_map_single(dev, |
e5a43549 | 6354 | skb->data + offset, |
1b507730 | 6355 | size, DMA_TO_DEVICE); |
b6ec895e | 6356 | if (dma_mapping_error(dev, tx_buffer_info->dma)) |
e5a43549 | 6357 | goto dma_error; |
9a799d71 AK |
6358 | tx_buffer_info->time_stamp = jiffies; |
6359 | tx_buffer_info->next_to_watch = i; | |
6360 | ||
6361 | len -= size; | |
eacd73f7 | 6362 | total -= size; |
9a799d71 AK |
6363 | offset += size; |
6364 | count++; | |
44df32c5 AD |
6365 | |
6366 | if (len) { | |
6367 | i++; | |
6368 | if (i == tx_ring->count) | |
6369 | i = 0; | |
6370 | } | |
9a799d71 AK |
6371 | } |
6372 | ||
6373 | for (f = 0; f < nr_frags; f++) { | |
6374 | struct skb_frag_struct *frag; | |
6375 | ||
6376 | frag = &skb_shinfo(skb)->frags[f]; | |
eacd73f7 | 6377 | len = min((unsigned int)frag->size, total); |
e5a43549 | 6378 | offset = frag->page_offset; |
9a799d71 AK |
6379 | |
6380 | while (len) { | |
44df32c5 AD |
6381 | i++; |
6382 | if (i == tx_ring->count) | |
6383 | i = 0; | |
6384 | ||
9a799d71 AK |
6385 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
6386 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
6387 | ||
6388 | tx_buffer_info->length = size; | |
b6ec895e | 6389 | tx_buffer_info->dma = dma_map_page(dev, |
e5a43549 AD |
6390 | frag->page, |
6391 | offset, size, | |
1b507730 | 6392 | DMA_TO_DEVICE); |
e5a43549 | 6393 | tx_buffer_info->mapped_as_page = true; |
b6ec895e | 6394 | if (dma_mapping_error(dev, tx_buffer_info->dma)) |
e5a43549 | 6395 | goto dma_error; |
9a799d71 AK |
6396 | tx_buffer_info->time_stamp = jiffies; |
6397 | tx_buffer_info->next_to_watch = i; | |
6398 | ||
6399 | len -= size; | |
eacd73f7 | 6400 | total -= size; |
9a799d71 AK |
6401 | offset += size; |
6402 | count++; | |
9a799d71 | 6403 | } |
eacd73f7 YZ |
6404 | if (total == 0) |
6405 | break; | |
9a799d71 | 6406 | } |
44df32c5 | 6407 | |
8ad494b0 AD |
6408 | if (tx_flags & IXGBE_TX_FLAGS_TSO) |
6409 | gso_segs = skb_shinfo(skb)->gso_segs; | |
6410 | #ifdef IXGBE_FCOE | |
6411 | /* adjust for FCoE Sequence Offload */ | |
6412 | else if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
6413 | gso_segs = DIV_ROUND_UP(skb->len - hdr_len, | |
6414 | skb_shinfo(skb)->gso_size); | |
6415 | #endif /* IXGBE_FCOE */ | |
6416 | bytecount += (gso_segs - 1) * hdr_len; | |
6417 | ||
6418 | /* multiply data chunks by size of headers */ | |
6419 | tx_ring->tx_buffer_info[i].bytecount = bytecount; | |
6420 | tx_ring->tx_buffer_info[i].gso_segs = gso_segs; | |
9a799d71 AK |
6421 | tx_ring->tx_buffer_info[i].skb = skb; |
6422 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
6423 | ||
e5a43549 AD |
6424 | return count; |
6425 | ||
6426 | dma_error: | |
849c4542 | 6427 | e_dev_err("TX DMA map failed\n"); |
e5a43549 AD |
6428 | |
6429 | /* clear timestamp and dma mappings for failed tx_buffer_info map */ | |
6430 | tx_buffer_info->dma = 0; | |
6431 | tx_buffer_info->time_stamp = 0; | |
6432 | tx_buffer_info->next_to_watch = 0; | |
c1fa347f RK |
6433 | if (count) |
6434 | count--; | |
e5a43549 AD |
6435 | |
6436 | /* clear timestamp and dma mappings for remaining portion of packet */ | |
c1fa347f | 6437 | while (count--) { |
e8e9f696 | 6438 | if (i == 0) |
e5a43549 | 6439 | i += tx_ring->count; |
c1fa347f | 6440 | i--; |
e5a43549 | 6441 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
b6ec895e | 6442 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
e5a43549 AD |
6443 | } |
6444 | ||
e44d38e1 | 6445 | return 0; |
9a799d71 AK |
6446 | } |
6447 | ||
84ea2591 | 6448 | static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring, |
e8e9f696 | 6449 | int tx_flags, int count, u32 paylen, u8 hdr_len) |
9a799d71 AK |
6450 | { |
6451 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
6452 | struct ixgbe_tx_buffer *tx_buffer_info; | |
6453 | u32 olinfo_status = 0, cmd_type_len = 0; | |
6454 | unsigned int i; | |
6455 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
6456 | ||
6457 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
6458 | ||
6459 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
6460 | ||
6461 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
6462 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
6463 | ||
6464 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
6465 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
6466 | ||
6467 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
e8e9f696 | 6468 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 6469 | |
4eeae6fd PW |
6470 | /* use index 1 context for tso */ |
6471 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
6472 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
6473 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
e8e9f696 | 6474 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
6475 | |
6476 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
6477 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
e8e9f696 | 6478 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 6479 | |
eacd73f7 YZ |
6480 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
6481 | olinfo_status |= IXGBE_ADVTXD_CC; | |
6482 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
6483 | if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
6484 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
6485 | } | |
6486 | ||
9a799d71 AK |
6487 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); |
6488 | ||
6489 | i = tx_ring->next_to_use; | |
6490 | while (count--) { | |
6491 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
31f05a2d | 6492 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i); |
9a799d71 AK |
6493 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); |
6494 | tx_desc->read.cmd_type_len = | |
e8e9f696 | 6495 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 6496 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
6497 | i++; |
6498 | if (i == tx_ring->count) | |
6499 | i = 0; | |
6500 | } | |
6501 | ||
6502 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
6503 | ||
6504 | /* | |
6505 | * Force memory writes to complete before letting h/w | |
6506 | * know there are new descriptors to fetch. (Only | |
6507 | * applicable for weak-ordered memory model archs, | |
6508 | * such as IA-64). | |
6509 | */ | |
6510 | wmb(); | |
6511 | ||
6512 | tx_ring->next_to_use = i; | |
84ea2591 | 6513 | writel(i, tx_ring->tail); |
9a799d71 AK |
6514 | } |
6515 | ||
69830529 AD |
6516 | static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb, |
6517 | u32 tx_flags, __be16 protocol) | |
6518 | { | |
6519 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
6520 | union ixgbe_atr_hash_dword input = { .dword = 0 }; | |
6521 | union ixgbe_atr_hash_dword common = { .dword = 0 }; | |
6522 | union { | |
6523 | unsigned char *network; | |
6524 | struct iphdr *ipv4; | |
6525 | struct ipv6hdr *ipv6; | |
6526 | } hdr; | |
ee9e0f0b | 6527 | struct tcphdr *th; |
905e4a41 | 6528 | __be16 vlan_id; |
c4cf55e5 | 6529 | |
69830529 AD |
6530 | /* if ring doesn't have a interrupt vector, cannot perform ATR */ |
6531 | if (!q_vector) | |
6532 | return; | |
6533 | ||
6534 | /* do nothing if sampling is disabled */ | |
6535 | if (!ring->atr_sample_rate) | |
d3ead241 | 6536 | return; |
c4cf55e5 | 6537 | |
69830529 | 6538 | ring->atr_count++; |
c4cf55e5 | 6539 | |
69830529 AD |
6540 | /* snag network header to get L4 type and address */ |
6541 | hdr.network = skb_network_header(skb); | |
6542 | ||
6543 | /* Currently only IPv4/IPv6 with TCP is supported */ | |
6544 | if ((protocol != __constant_htons(ETH_P_IPV6) || | |
6545 | hdr.ipv6->nexthdr != IPPROTO_TCP) && | |
6546 | (protocol != __constant_htons(ETH_P_IP) || | |
6547 | hdr.ipv4->protocol != IPPROTO_TCP)) | |
6548 | return; | |
ee9e0f0b AD |
6549 | |
6550 | th = tcp_hdr(skb); | |
c4cf55e5 | 6551 | |
69830529 AD |
6552 | /* skip this packet since the socket is closing */ |
6553 | if (th->fin) | |
6554 | return; | |
6555 | ||
6556 | /* sample on all syn packets or once every atr sample count */ | |
6557 | if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) | |
6558 | return; | |
6559 | ||
6560 | /* reset sample count */ | |
6561 | ring->atr_count = 0; | |
6562 | ||
6563 | vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6564 | ||
6565 | /* | |
6566 | * src and dst are inverted, think how the receiver sees them | |
6567 | * | |
6568 | * The input is broken into two sections, a non-compressed section | |
6569 | * containing vm_pool, vlan_id, and flow_type. The rest of the data | |
6570 | * is XORed together and stored in the compressed dword. | |
6571 | */ | |
6572 | input.formatted.vlan_id = vlan_id; | |
6573 | ||
6574 | /* | |
6575 | * since src port and flex bytes occupy the same word XOR them together | |
6576 | * and write the value to source port portion of compressed dword | |
6577 | */ | |
6578 | if (vlan_id) | |
6579 | common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q); | |
6580 | else | |
6581 | common.port.src ^= th->dest ^ protocol; | |
6582 | common.port.dst ^= th->source; | |
6583 | ||
6584 | if (protocol == __constant_htons(ETH_P_IP)) { | |
6585 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; | |
6586 | common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; | |
6587 | } else { | |
6588 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; | |
6589 | common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ | |
6590 | hdr.ipv6->saddr.s6_addr32[1] ^ | |
6591 | hdr.ipv6->saddr.s6_addr32[2] ^ | |
6592 | hdr.ipv6->saddr.s6_addr32[3] ^ | |
6593 | hdr.ipv6->daddr.s6_addr32[0] ^ | |
6594 | hdr.ipv6->daddr.s6_addr32[1] ^ | |
6595 | hdr.ipv6->daddr.s6_addr32[2] ^ | |
6596 | hdr.ipv6->daddr.s6_addr32[3]; | |
6597 | } | |
c4cf55e5 PWJ |
6598 | |
6599 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
69830529 AD |
6600 | ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, |
6601 | input, common, ring->queue_index); | |
c4cf55e5 PWJ |
6602 | } |
6603 | ||
fc77dc3c | 6604 | static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size) |
e092be60 | 6605 | { |
fc77dc3c | 6606 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); |
e092be60 AV |
6607 | /* Herbert's original patch had: |
6608 | * smp_mb__after_netif_stop_queue(); | |
6609 | * but since that doesn't exist yet, just open code it. */ | |
6610 | smp_mb(); | |
6611 | ||
6612 | /* We need to check again in a case another CPU has just | |
6613 | * made room available. */ | |
6614 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
6615 | return -EBUSY; | |
6616 | ||
6617 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
fc77dc3c | 6618 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 6619 | ++tx_ring->tx_stats.restart_queue; |
e092be60 AV |
6620 | return 0; |
6621 | } | |
6622 | ||
fc77dc3c | 6623 | static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
6624 | { |
6625 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
6626 | return 0; | |
fc77dc3c | 6627 | return __ixgbe_maybe_stop_tx(tx_ring, size); |
e092be60 AV |
6628 | } |
6629 | ||
09a3b1f8 SH |
6630 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
6631 | { | |
6632 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5f715823 | 6633 | int txq = smp_processor_id(); |
56075a98 | 6634 | #ifdef IXGBE_FCOE |
5e09a105 HZ |
6635 | __be16 protocol; |
6636 | ||
6637 | protocol = vlan_get_protocol(skb); | |
6638 | ||
6639 | if ((protocol == htons(ETH_P_FCOE)) || | |
6640 | (protocol == htons(ETH_P_FIP))) { | |
56075a98 JF |
6641 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { |
6642 | txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1); | |
6643 | txq += adapter->ring_feature[RING_F_FCOE].mask; | |
6644 | return txq; | |
4bc091d8 | 6645 | #ifdef CONFIG_IXGBE_DCB |
56075a98 JF |
6646 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
6647 | txq = adapter->fcoe.up; | |
6648 | return txq; | |
4bc091d8 | 6649 | #endif |
56075a98 JF |
6650 | } |
6651 | } | |
6652 | #endif | |
6653 | ||
fdd3d631 KK |
6654 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
6655 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
6656 | txq -= dev->real_num_tx_queues; | |
5f715823 | 6657 | return txq; |
fdd3d631 | 6658 | } |
c4cf55e5 | 6659 | |
2ea186ae JF |
6660 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
6661 | if (skb->priority == TC_PRIO_CONTROL) | |
6662 | txq = adapter->ring_feature[RING_F_DCB].indices-1; | |
6663 | else | |
6664 | txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) | |
6665 | >> 13; | |
6666 | return txq; | |
6667 | } | |
09a3b1f8 SH |
6668 | |
6669 | return skb_tx_hash(dev, skb); | |
6670 | } | |
6671 | ||
fc77dc3c | 6672 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
84418e3b AD |
6673 | struct ixgbe_adapter *adapter, |
6674 | struct ixgbe_ring *tx_ring) | |
9a799d71 | 6675 | { |
9a799d71 AK |
6676 | unsigned int first; |
6677 | unsigned int tx_flags = 0; | |
30eba97a | 6678 | u8 hdr_len = 0; |
5f715823 | 6679 | int tso; |
9a799d71 AK |
6680 | int count = 0; |
6681 | unsigned int f; | |
5e09a105 HZ |
6682 | __be16 protocol; |
6683 | ||
6684 | protocol = vlan_get_protocol(skb); | |
9f8cdf4f | 6685 | |
eab6d18d | 6686 | if (vlan_tx_tag_present(skb)) { |
9f8cdf4f | 6687 | tx_flags |= vlan_tx_tag_get(skb); |
2f90b865 AD |
6688 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
6689 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
5f715823 | 6690 | tx_flags |= ((skb->queue_mapping & 0x7) << 13); |
2f90b865 AD |
6691 | } |
6692 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
6693 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
33c66bd1 JF |
6694 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED && |
6695 | skb->priority != TC_PRIO_CONTROL) { | |
2ea186ae JF |
6696 | tx_flags |= ((skb->queue_mapping & 0x7) << 13); |
6697 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
6698 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 6699 | } |
eacd73f7 | 6700 | |
09ad1cc0 | 6701 | #ifdef IXGBE_FCOE |
56075a98 JF |
6702 | /* for FCoE with DCB, we force the priority to what |
6703 | * was specified by the switch */ | |
6704 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED && | |
5e09a105 HZ |
6705 | (protocol == htons(ETH_P_FCOE) || |
6706 | protocol == htons(ETH_P_FIP))) { | |
4bc091d8 JF |
6707 | #ifdef CONFIG_IXGBE_DCB |
6708 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
6709 | tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK | |
6710 | << IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6711 | tx_flags |= ((adapter->fcoe.up << 13) | |
6712 | << IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6713 | } | |
6714 | #endif | |
ca77cd59 | 6715 | /* flag for FCoE offloads */ |
5e09a105 | 6716 | if (protocol == htons(ETH_P_FCOE)) |
ca77cd59 | 6717 | tx_flags |= IXGBE_TX_FLAGS_FCOE; |
09ad1cc0 | 6718 | } |
ca77cd59 RL |
6719 | #endif |
6720 | ||
eacd73f7 | 6721 | /* four things can cause us to need a context descriptor */ |
9f8cdf4f JB |
6722 | if (skb_is_gso(skb) || |
6723 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
eacd73f7 YZ |
6724 | (tx_flags & IXGBE_TX_FLAGS_VLAN) || |
6725 | (tx_flags & IXGBE_TX_FLAGS_FCOE)) | |
9a799d71 AK |
6726 | count++; |
6727 | ||
9f8cdf4f JB |
6728 | count += TXD_USE_COUNT(skb_headlen(skb)); |
6729 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
6730 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
6731 | ||
fc77dc3c | 6732 | if (ixgbe_maybe_stop_tx(tx_ring, count)) { |
5b7da515 | 6733 | tx_ring->tx_stats.tx_busy++; |
9a799d71 AK |
6734 | return NETDEV_TX_BUSY; |
6735 | } | |
9a799d71 | 6736 | |
9a799d71 | 6737 | first = tx_ring->next_to_use; |
eacd73f7 YZ |
6738 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
6739 | #ifdef IXGBE_FCOE | |
6740 | /* setup tx offload for FCoE */ | |
6741 | tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
6742 | if (tso < 0) { | |
6743 | dev_kfree_skb_any(skb); | |
6744 | return NETDEV_TX_OK; | |
6745 | } | |
6746 | if (tso) | |
6747 | tx_flags |= IXGBE_TX_FLAGS_FSO; | |
6748 | #endif /* IXGBE_FCOE */ | |
6749 | } else { | |
5e09a105 | 6750 | if (protocol == htons(ETH_P_IP)) |
eacd73f7 | 6751 | tx_flags |= IXGBE_TX_FLAGS_IPV4; |
5e09a105 HZ |
6752 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len, |
6753 | protocol); | |
eacd73f7 YZ |
6754 | if (tso < 0) { |
6755 | dev_kfree_skb_any(skb); | |
6756 | return NETDEV_TX_OK; | |
6757 | } | |
9a799d71 | 6758 | |
eacd73f7 YZ |
6759 | if (tso) |
6760 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
5e09a105 HZ |
6761 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags, |
6762 | protocol) && | |
eacd73f7 YZ |
6763 | (skb->ip_summed == CHECKSUM_PARTIAL)) |
6764 | tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
6765 | } | |
9a799d71 | 6766 | |
8ad494b0 | 6767 | count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len); |
44df32c5 | 6768 | if (count) { |
c4cf55e5 | 6769 | /* add the ATR filter if ATR is on */ |
69830529 AD |
6770 | if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) |
6771 | ixgbe_atr(tx_ring, skb, tx_flags, protocol); | |
84ea2591 | 6772 | ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len); |
fc77dc3c | 6773 | ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); |
9a799d71 | 6774 | |
44df32c5 AD |
6775 | } else { |
6776 | dev_kfree_skb_any(skb); | |
6777 | tx_ring->tx_buffer_info[first].time_stamp = 0; | |
6778 | tx_ring->next_to_use = first; | |
6779 | } | |
9a799d71 AK |
6780 | |
6781 | return NETDEV_TX_OK; | |
6782 | } | |
6783 | ||
84418e3b AD |
6784 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
6785 | { | |
6786 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6787 | struct ixgbe_ring *tx_ring; | |
6788 | ||
6789 | tx_ring = adapter->tx_ring[skb->queue_mapping]; | |
fc77dc3c | 6790 | return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); |
84418e3b AD |
6791 | } |
6792 | ||
9a799d71 AK |
6793 | /** |
6794 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
6795 | * @netdev: network interface device structure | |
6796 | * @p: pointer to an address structure | |
6797 | * | |
6798 | * Returns 0 on success, negative on failure | |
6799 | **/ | |
6800 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
6801 | { | |
6802 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 6803 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
6804 | struct sockaddr *addr = p; |
6805 | ||
6806 | if (!is_valid_ether_addr(addr->sa_data)) | |
6807 | return -EADDRNOTAVAIL; | |
6808 | ||
6809 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 6810 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 6811 | |
1cdd1ec8 GR |
6812 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
6813 | IXGBE_RAH_AV); | |
9a799d71 AK |
6814 | |
6815 | return 0; | |
6816 | } | |
6817 | ||
6b73e10d BH |
6818 | static int |
6819 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
6820 | { | |
6821 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6822 | struct ixgbe_hw *hw = &adapter->hw; | |
6823 | u16 value; | |
6824 | int rc; | |
6825 | ||
6826 | if (prtad != hw->phy.mdio.prtad) | |
6827 | return -EINVAL; | |
6828 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
6829 | if (!rc) | |
6830 | rc = value; | |
6831 | return rc; | |
6832 | } | |
6833 | ||
6834 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
6835 | u16 addr, u16 value) | |
6836 | { | |
6837 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6838 | struct ixgbe_hw *hw = &adapter->hw; | |
6839 | ||
6840 | if (prtad != hw->phy.mdio.prtad) | |
6841 | return -EINVAL; | |
6842 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
6843 | } | |
6844 | ||
6845 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
6846 | { | |
6847 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6848 | ||
6849 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
6850 | } | |
6851 | ||
0365e6e4 PW |
6852 | /** |
6853 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 6854 | * netdev->dev_addrs |
0365e6e4 PW |
6855 | * @netdev: network interface device structure |
6856 | * | |
6857 | * Returns non-zero on failure | |
6858 | **/ | |
6859 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
6860 | { | |
6861 | int err = 0; | |
6862 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6863 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6864 | ||
6865 | if (is_valid_ether_addr(mac->san_addr)) { | |
6866 | rtnl_lock(); | |
6867 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6868 | rtnl_unlock(); | |
6869 | } | |
6870 | return err; | |
6871 | } | |
6872 | ||
6873 | /** | |
6874 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 6875 | * netdev->dev_addrs |
0365e6e4 PW |
6876 | * @netdev: network interface device structure |
6877 | * | |
6878 | * Returns non-zero on failure | |
6879 | **/ | |
6880 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
6881 | { | |
6882 | int err = 0; | |
6883 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6884 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6885 | ||
6886 | if (is_valid_ether_addr(mac->san_addr)) { | |
6887 | rtnl_lock(); | |
6888 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6889 | rtnl_unlock(); | |
6890 | } | |
6891 | return err; | |
6892 | } | |
6893 | ||
9a799d71 AK |
6894 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6895 | /* | |
6896 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
6897 | * without having to re-enable interrupts. It's not called while | |
6898 | * the interrupt routine is executing. | |
6899 | */ | |
6900 | static void ixgbe_netpoll(struct net_device *netdev) | |
6901 | { | |
6902 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 6903 | int i; |
9a799d71 | 6904 | |
1a647bd2 AD |
6905 | /* if interface is down do nothing */ |
6906 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
6907 | return; | |
6908 | ||
9a799d71 | 6909 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 PWJ |
6910 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
6911 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
6912 | for (i = 0; i < num_q_vectors; i++) { | |
6913 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
6914 | ixgbe_msix_clean_many(0, q_vector); | |
6915 | } | |
6916 | } else { | |
6917 | ixgbe_intr(adapter->pdev->irq, netdev); | |
6918 | } | |
9a799d71 | 6919 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 AK |
6920 | } |
6921 | #endif | |
6922 | ||
de1036b1 ED |
6923 | static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, |
6924 | struct rtnl_link_stats64 *stats) | |
6925 | { | |
6926 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6927 | int i; | |
6928 | ||
1a51502b | 6929 | rcu_read_lock(); |
de1036b1 | 6930 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1a51502b | 6931 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); |
de1036b1 ED |
6932 | u64 bytes, packets; |
6933 | unsigned int start; | |
6934 | ||
1a51502b ED |
6935 | if (ring) { |
6936 | do { | |
6937 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6938 | packets = ring->stats.packets; | |
6939 | bytes = ring->stats.bytes; | |
6940 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6941 | stats->rx_packets += packets; | |
6942 | stats->rx_bytes += bytes; | |
6943 | } | |
de1036b1 | 6944 | } |
1ac9ad13 ED |
6945 | |
6946 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
6947 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); | |
6948 | u64 bytes, packets; | |
6949 | unsigned int start; | |
6950 | ||
6951 | if (ring) { | |
6952 | do { | |
6953 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6954 | packets = ring->stats.packets; | |
6955 | bytes = ring->stats.bytes; | |
6956 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6957 | stats->tx_packets += packets; | |
6958 | stats->tx_bytes += bytes; | |
6959 | } | |
6960 | } | |
1a51502b | 6961 | rcu_read_unlock(); |
de1036b1 ED |
6962 | /* following stats updated by ixgbe_watchdog_task() */ |
6963 | stats->multicast = netdev->stats.multicast; | |
6964 | stats->rx_errors = netdev->stats.rx_errors; | |
6965 | stats->rx_length_errors = netdev->stats.rx_length_errors; | |
6966 | stats->rx_crc_errors = netdev->stats.rx_crc_errors; | |
6967 | stats->rx_missed_errors = netdev->stats.rx_missed_errors; | |
6968 | return stats; | |
6969 | } | |
6970 | ||
6971 | ||
0edc3527 | 6972 | static const struct net_device_ops ixgbe_netdev_ops = { |
e8e9f696 | 6973 | .ndo_open = ixgbe_open, |
0edc3527 | 6974 | .ndo_stop = ixgbe_close, |
00829823 | 6975 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 6976 | .ndo_select_queue = ixgbe_select_queue, |
e90d400c | 6977 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
6978 | .ndo_set_multicast_list = ixgbe_set_rx_mode, |
6979 | .ndo_validate_addr = eth_validate_addr, | |
6980 | .ndo_set_mac_address = ixgbe_set_mac, | |
6981 | .ndo_change_mtu = ixgbe_change_mtu, | |
6982 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
0edc3527 SH |
6983 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, |
6984 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 6985 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
6986 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
6987 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
6988 | .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw, | |
6989 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, | |
de1036b1 | 6990 | .ndo_get_stats64 = ixgbe_get_stats64, |
0edc3527 SH |
6991 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6992 | .ndo_poll_controller = ixgbe_netpoll, | |
6993 | #endif | |
332d4a7d YZ |
6994 | #ifdef IXGBE_FCOE |
6995 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
6996 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, | |
8450ff8c YZ |
6997 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
6998 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 6999 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
332d4a7d | 7000 | #endif /* IXGBE_FCOE */ |
0edc3527 SH |
7001 | }; |
7002 | ||
1cdd1ec8 GR |
7003 | static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter, |
7004 | const struct ixgbe_info *ii) | |
7005 | { | |
7006 | #ifdef CONFIG_PCI_IOV | |
7007 | struct ixgbe_hw *hw = &adapter->hw; | |
7008 | int err; | |
7009 | ||
3377eba7 | 7010 | if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs) |
1cdd1ec8 GR |
7011 | return; |
7012 | ||
7013 | /* The 82599 supports up to 64 VFs per physical function | |
7014 | * but this implementation limits allocation to 63 so that | |
7015 | * basic networking resources are still available to the | |
7016 | * physical function | |
7017 | */ | |
7018 | adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs; | |
7019 | adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED; | |
7020 | err = pci_enable_sriov(adapter->pdev, adapter->num_vfs); | |
7021 | if (err) { | |
396e799c | 7022 | e_err(probe, "Failed to enable PCI sriov: %d\n", err); |
1cdd1ec8 GR |
7023 | goto err_novfs; |
7024 | } | |
7025 | /* If call to enable VFs succeeded then allocate memory | |
7026 | * for per VF control structures. | |
7027 | */ | |
7028 | adapter->vfinfo = | |
7029 | kcalloc(adapter->num_vfs, | |
7030 | sizeof(struct vf_data_storage), GFP_KERNEL); | |
7031 | if (adapter->vfinfo) { | |
7032 | /* Now that we're sure SR-IOV is enabled | |
7033 | * and memory allocated set up the mailbox parameters | |
7034 | */ | |
7035 | ixgbe_init_mbx_params_pf(hw); | |
7036 | memcpy(&hw->mbx.ops, ii->mbx_ops, | |
7037 | sizeof(hw->mbx.ops)); | |
7038 | ||
7039 | /* Disable RSC when in SR-IOV mode */ | |
7040 | adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE | | |
7041 | IXGBE_FLAG2_RSC_ENABLED); | |
7042 | return; | |
7043 | } | |
7044 | ||
7045 | /* Oh oh */ | |
396e799c ET |
7046 | e_err(probe, "Unable to allocate memory for VF Data Storage - " |
7047 | "SRIOV disabled\n"); | |
1cdd1ec8 GR |
7048 | pci_disable_sriov(adapter->pdev); |
7049 | ||
7050 | err_novfs: | |
7051 | adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; | |
7052 | adapter->num_vfs = 0; | |
7053 | #endif /* CONFIG_PCI_IOV */ | |
7054 | } | |
7055 | ||
9a799d71 AK |
7056 | /** |
7057 | * ixgbe_probe - Device Initialization Routine | |
7058 | * @pdev: PCI device information struct | |
7059 | * @ent: entry in ixgbe_pci_tbl | |
7060 | * | |
7061 | * Returns 0 on success, negative on failure | |
7062 | * | |
7063 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
7064 | * The OS initialization, configuring of the adapter private structure, | |
7065 | * and a hardware reset occur. | |
7066 | **/ | |
7067 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
e8e9f696 | 7068 | const struct pci_device_id *ent) |
9a799d71 AK |
7069 | { |
7070 | struct net_device *netdev; | |
7071 | struct ixgbe_adapter *adapter = NULL; | |
7072 | struct ixgbe_hw *hw; | |
7073 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
7074 | static int cards_found; |
7075 | int i, err, pci_using_dac; | |
289700db | 7076 | u8 part_str[IXGBE_PBANUM_LENGTH]; |
c85a2618 | 7077 | unsigned int indices = num_possible_cpus(); |
eacd73f7 YZ |
7078 | #ifdef IXGBE_FCOE |
7079 | u16 device_caps; | |
7080 | #endif | |
289700db | 7081 | u32 eec; |
9a799d71 | 7082 | |
bded64a7 AG |
7083 | /* Catch broken hardware that put the wrong VF device ID in |
7084 | * the PCIe SR-IOV capability. | |
7085 | */ | |
7086 | if (pdev->is_virtfn) { | |
7087 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
7088 | pci_name(pdev), pdev->vendor, pdev->device); | |
7089 | return -EINVAL; | |
7090 | } | |
7091 | ||
9ce77666 | 7092 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
7093 | if (err) |
7094 | return err; | |
7095 | ||
1b507730 NN |
7096 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && |
7097 | !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
7098 | pci_using_dac = 1; |
7099 | } else { | |
1b507730 | 7100 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 7101 | if (err) { |
1b507730 NN |
7102 | err = dma_set_coherent_mask(&pdev->dev, |
7103 | DMA_BIT_MASK(32)); | |
9a799d71 | 7104 | if (err) { |
b8bc0421 DC |
7105 | dev_err(&pdev->dev, |
7106 | "No usable DMA configuration, aborting\n"); | |
9a799d71 AK |
7107 | goto err_dma; |
7108 | } | |
7109 | } | |
7110 | pci_using_dac = 0; | |
7111 | } | |
7112 | ||
9ce77666 | 7113 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7114 | IORESOURCE_MEM), ixgbe_driver_name); |
9a799d71 | 7115 | if (err) { |
b8bc0421 DC |
7116 | dev_err(&pdev->dev, |
7117 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
7118 | goto err_pci_reg; |
7119 | } | |
7120 | ||
19d5afd4 | 7121 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 7122 | |
9a799d71 | 7123 | pci_set_master(pdev); |
fb3b27bc | 7124 | pci_save_state(pdev); |
9a799d71 | 7125 | |
c85a2618 JF |
7126 | if (ii->mac == ixgbe_mac_82598EB) |
7127 | indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); | |
7128 | else | |
7129 | indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); | |
7130 | ||
7131 | indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES); | |
7132 | #ifdef IXGBE_FCOE | |
7133 | indices += min_t(unsigned int, num_possible_cpus(), | |
7134 | IXGBE_MAX_FCOE_INDICES); | |
7135 | #endif | |
c85a2618 | 7136 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
7137 | if (!netdev) { |
7138 | err = -ENOMEM; | |
7139 | goto err_alloc_etherdev; | |
7140 | } | |
7141 | ||
9a799d71 AK |
7142 | SET_NETDEV_DEV(netdev, &pdev->dev); |
7143 | ||
9a799d71 | 7144 | adapter = netdev_priv(netdev); |
c60fbb00 | 7145 | pci_set_drvdata(pdev, adapter); |
9a799d71 AK |
7146 | |
7147 | adapter->netdev = netdev; | |
7148 | adapter->pdev = pdev; | |
7149 | hw = &adapter->hw; | |
7150 | hw->back = adapter; | |
7151 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
7152 | ||
05857980 | 7153 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
e8e9f696 | 7154 | pci_resource_len(pdev, 0)); |
9a799d71 AK |
7155 | if (!hw->hw_addr) { |
7156 | err = -EIO; | |
7157 | goto err_ioremap; | |
7158 | } | |
7159 | ||
7160 | for (i = 1; i <= 5; i++) { | |
7161 | if (pci_resource_len(pdev, i) == 0) | |
7162 | continue; | |
7163 | } | |
7164 | ||
0edc3527 | 7165 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 7166 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 7167 | netdev->watchdog_timeo = 5 * HZ; |
9fe93afd | 7168 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); |
9a799d71 | 7169 | |
9a799d71 AK |
7170 | adapter->bd_number = cards_found; |
7171 | ||
9a799d71 AK |
7172 | /* Setup hw api */ |
7173 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 7174 | hw->mac.type = ii->mac; |
9a799d71 | 7175 | |
c44ade9e JB |
7176 | /* EEPROM */ |
7177 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
7178 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
7179 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
7180 | if (!(eec & (1 << 8))) | |
7181 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
7182 | ||
7183 | /* PHY */ | |
7184 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 7185 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
7186 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
7187 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
7188 | hw->phy.mdio.mmds = 0; | |
7189 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
7190 | hw->phy.mdio.dev = netdev; | |
7191 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
7192 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 DS |
7193 | |
7194 | /* set up this timer and work struct before calling get_invariants | |
7195 | * which might start the timer | |
7196 | */ | |
7197 | init_timer(&adapter->sfp_timer); | |
c061b18d | 7198 | adapter->sfp_timer.function = ixgbe_sfp_timer; |
c4900be0 DS |
7199 | adapter->sfp_timer.data = (unsigned long) adapter; |
7200 | ||
7201 | INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); | |
c44ade9e | 7202 | |
e8e26350 PW |
7203 | /* multispeed fiber has its own tasklet, called from GPI SDP1 context */ |
7204 | INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task); | |
7205 | ||
7206 | /* a new SFP+ module arrival, called from GPI SDP2 context */ | |
7207 | INIT_WORK(&adapter->sfp_config_module_task, | |
e8e9f696 | 7208 | ixgbe_sfp_config_module_task); |
e8e26350 | 7209 | |
8ca783ab | 7210 | ii->get_invariants(hw); |
9a799d71 AK |
7211 | |
7212 | /* setup the private structure */ | |
7213 | err = ixgbe_sw_init(adapter); | |
7214 | if (err) | |
7215 | goto err_sw_init; | |
7216 | ||
e86bff0e | 7217 | /* Make it possible the adapter to be woken up via WOL */ |
b93a2226 DS |
7218 | switch (adapter->hw.mac.type) { |
7219 | case ixgbe_mac_82599EB: | |
7220 | case ixgbe_mac_X540: | |
e86bff0e | 7221 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
b93a2226 DS |
7222 | break; |
7223 | default: | |
7224 | break; | |
7225 | } | |
e86bff0e | 7226 | |
bf069c97 DS |
7227 | /* |
7228 | * If there is a fan on this device and it has failed log the | |
7229 | * failure. | |
7230 | */ | |
7231 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
7232 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
7233 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 7234 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
7235 | } |
7236 | ||
c44ade9e | 7237 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 7238 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 7239 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 7240 | hw->phy.reset_if_overtemp = false; |
8ca783ab DS |
7241 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
7242 | hw->mac.type == ixgbe_mac_82598EB) { | |
7243 | /* | |
7244 | * Start a kernel thread to watch for a module to arrive. | |
7245 | * Only do this for 82598, since 82599 will generate | |
7246 | * interrupts on module arrival. | |
7247 | */ | |
7248 | set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
7249 | mod_timer(&adapter->sfp_timer, | |
7250 | round_jiffies(jiffies + (2 * HZ))); | |
7251 | err = 0; | |
7252 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
849c4542 ET |
7253 | e_dev_err("failed to initialize because an unsupported SFP+ " |
7254 | "module type was detected.\n"); | |
7255 | e_dev_err("Reload the driver after installing a supported " | |
7256 | "module.\n"); | |
04f165ef PW |
7257 | goto err_sw_init; |
7258 | } else if (err) { | |
849c4542 | 7259 | e_dev_err("HW Init failed: %d\n", err); |
c44ade9e JB |
7260 | goto err_sw_init; |
7261 | } | |
7262 | ||
1cdd1ec8 GR |
7263 | ixgbe_probe_vf(adapter, ii); |
7264 | ||
396e799c | 7265 | netdev->features = NETIF_F_SG | |
e8e9f696 JP |
7266 | NETIF_F_IP_CSUM | |
7267 | NETIF_F_HW_VLAN_TX | | |
7268 | NETIF_F_HW_VLAN_RX | | |
7269 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 7270 | |
e9990a9c | 7271 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 7272 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 7273 | netdev->features |= NETIF_F_TSO6; |
78b6f4ce | 7274 | netdev->features |= NETIF_F_GRO; |
ad31c402 | 7275 | |
45a5ead0 JB |
7276 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
7277 | netdev->features |= NETIF_F_SCTP_CSUM; | |
7278 | ||
ad31c402 JK |
7279 | netdev->vlan_features |= NETIF_F_TSO; |
7280 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 7281 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 7282 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
7283 | netdev->vlan_features |= NETIF_F_SG; |
7284 | ||
1cdd1ec8 GR |
7285 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7286 | adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED | | |
7287 | IXGBE_FLAG_DCB_ENABLED); | |
2f90b865 AD |
7288 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
7289 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
7290 | ||
7a6b6f51 | 7291 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
7292 | netdev->dcbnl_ops = &dcbnl_ops; |
7293 | #endif | |
7294 | ||
eacd73f7 | 7295 | #ifdef IXGBE_FCOE |
0d551589 | 7296 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
7297 | if (hw->mac.ops.get_device_caps) { |
7298 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
7299 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
7300 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 YZ |
7301 | } |
7302 | } | |
5e09d7f6 YZ |
7303 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
7304 | netdev->vlan_features |= NETIF_F_FCOE_CRC; | |
7305 | netdev->vlan_features |= NETIF_F_FSO; | |
7306 | netdev->vlan_features |= NETIF_F_FCOE_MTU; | |
7307 | } | |
eacd73f7 | 7308 | #endif /* IXGBE_FCOE */ |
7b872a55 | 7309 | if (pci_using_dac) { |
9a799d71 | 7310 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
7311 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
7312 | } | |
9a799d71 | 7313 | |
0c19d6af | 7314 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
7315 | netdev->features |= NETIF_F_LRO; |
7316 | ||
9a799d71 | 7317 | /* make sure the EEPROM is good */ |
c44ade9e | 7318 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
849c4542 | 7319 | e_dev_err("The EEPROM Checksum Is Not Valid\n"); |
9a799d71 AK |
7320 | err = -EIO; |
7321 | goto err_eeprom; | |
7322 | } | |
7323 | ||
7324 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
7325 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
7326 | ||
c44ade9e | 7327 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
849c4542 | 7328 | e_dev_err("invalid MAC address\n"); |
9a799d71 AK |
7329 | err = -EIO; |
7330 | goto err_eeprom; | |
7331 | } | |
7332 | ||
c6ecf39a DS |
7333 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ |
7334 | if (hw->mac.ops.disable_tx_laser && | |
7335 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 7336 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a | 7337 | (hw->mac.type == ixgbe_mac_82599EB)))) |
61fac744 PW |
7338 | hw->mac.ops.disable_tx_laser(hw); |
7339 | ||
9a799d71 | 7340 | init_timer(&adapter->watchdog_timer); |
c061b18d | 7341 | adapter->watchdog_timer.function = ixgbe_watchdog; |
9a799d71 AK |
7342 | adapter->watchdog_timer.data = (unsigned long)adapter; |
7343 | ||
7344 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 7345 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 7346 | |
021230d4 AV |
7347 | err = ixgbe_init_interrupt_scheme(adapter); |
7348 | if (err) | |
7349 | goto err_sw_init; | |
9a799d71 | 7350 | |
e8e26350 | 7351 | switch (pdev->device) { |
0b077fea DS |
7352 | case IXGBE_DEV_ID_82599_SFP: |
7353 | /* Only this subdevice supports WOL */ | |
7354 | if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP) | |
7355 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | | |
7356 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); | |
7357 | break; | |
50d6c681 AD |
7358 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: |
7359 | /* All except this subdevice support WOL */ | |
0b077fea DS |
7360 | if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) |
7361 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | | |
7362 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); | |
7363 | break; | |
e8e26350 | 7364 | case IXGBE_DEV_ID_82599_KX4: |
495dce12 | 7365 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | |
e8e9f696 | 7366 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); |
e8e26350 PW |
7367 | break; |
7368 | default: | |
7369 | adapter->wol = 0; | |
7370 | break; | |
7371 | } | |
e8e26350 PW |
7372 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
7373 | ||
04f165ef PW |
7374 | /* pick up the PCI bus settings for reporting later */ |
7375 | hw->mac.ops.get_bus_info(hw); | |
7376 | ||
9a799d71 | 7377 | /* print bus type/speed/width info */ |
849c4542 | 7378 | e_dev_info("(PCI Express:%s:%s) %pM\n", |
e8e9f696 JP |
7379 | (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" : |
7380 | hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" : | |
7381 | "Unknown"), | |
7382 | (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" : | |
7383 | hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" : | |
7384 | hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" : | |
7385 | "Unknown"), | |
7386 | netdev->dev_addr); | |
289700db DS |
7387 | |
7388 | err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH); | |
7389 | if (err) | |
9fe93afd | 7390 | strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH); |
e8e26350 | 7391 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
289700db | 7392 | e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", |
849c4542 | 7393 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, |
289700db | 7394 | part_str); |
e8e26350 | 7395 | else |
289700db DS |
7396 | e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", |
7397 | hw->mac.type, hw->phy.type, part_str); | |
9a799d71 | 7398 | |
e8e26350 | 7399 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
849c4542 ET |
7400 | e_dev_warn("PCI-Express bandwidth available for this card is " |
7401 | "not sufficient for optimal performance.\n"); | |
7402 | e_dev_warn("For optimal performance a x8 PCI-Express slot " | |
7403 | "is required.\n"); | |
0c254d86 AK |
7404 | } |
7405 | ||
34b0368c PWJ |
7406 | /* save off EEPROM version number */ |
7407 | hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version); | |
7408 | ||
9a799d71 | 7409 | /* reset the hardware with the new settings */ |
794caeb2 | 7410 | err = hw->mac.ops.start_hw(hw); |
c44ade9e | 7411 | |
794caeb2 PWJ |
7412 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
7413 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
7414 | e_dev_warn("This device is a pre-production adapter/LOM. " |
7415 | "Please be aware there may be issues associated " | |
7416 | "with your hardware. If you are experiencing " | |
7417 | "problems please contact your Intel or hardware " | |
7418 | "representative who provided you with this " | |
7419 | "hardware.\n"); | |
794caeb2 | 7420 | } |
9a799d71 AK |
7421 | strcpy(netdev->name, "eth%d"); |
7422 | err = register_netdev(netdev); | |
7423 | if (err) | |
7424 | goto err_register; | |
7425 | ||
54386467 JB |
7426 | /* carrier off reporting is important to ethtool even BEFORE open */ |
7427 | netif_carrier_off(netdev); | |
7428 | ||
c4cf55e5 PWJ |
7429 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
7430 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
7431 | INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task); | |
7432 | ||
119fc60a | 7433 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
e8e9f696 JP |
7434 | INIT_WORK(&adapter->check_overtemp_task, |
7435 | ixgbe_check_overtemp_task); | |
5dd2d332 | 7436 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 7437 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 7438 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
7439 | ixgbe_setup_dca(adapter); |
7440 | } | |
7441 | #endif | |
1cdd1ec8 | 7442 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
396e799c | 7443 | e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); |
1cdd1ec8 GR |
7444 | for (i = 0; i < adapter->num_vfs; i++) |
7445 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
7446 | } | |
7447 | ||
0365e6e4 PW |
7448 | /* add san mac addr to netdev */ |
7449 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 | 7450 | |
849c4542 | 7451 | e_dev_info("Intel(R) 10 Gigabit Network Connection\n"); |
9a799d71 AK |
7452 | cards_found++; |
7453 | return 0; | |
7454 | ||
7455 | err_register: | |
5eba3699 | 7456 | ixgbe_release_hw_control(adapter); |
7a921c93 | 7457 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 AK |
7458 | err_sw_init: |
7459 | err_eeprom: | |
1cdd1ec8 GR |
7460 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7461 | ixgbe_disable_sriov(adapter); | |
c4900be0 DS |
7462 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
7463 | del_timer_sync(&adapter->sfp_timer); | |
7464 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
7465 | cancel_work_sync(&adapter->multispeed_fiber_task); |
7466 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
7467 | iounmap(hw->hw_addr); |
7468 | err_ioremap: | |
7469 | free_netdev(netdev); | |
7470 | err_alloc_etherdev: | |
e8e9f696 JP |
7471 | pci_release_selected_regions(pdev, |
7472 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9a799d71 AK |
7473 | err_pci_reg: |
7474 | err_dma: | |
7475 | pci_disable_device(pdev); | |
7476 | return err; | |
7477 | } | |
7478 | ||
7479 | /** | |
7480 | * ixgbe_remove - Device Removal Routine | |
7481 | * @pdev: PCI device information struct | |
7482 | * | |
7483 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
7484 | * that it should release a PCI device. The could be caused by a | |
7485 | * Hot-Plug event, or because the driver is going to be removed from | |
7486 | * memory. | |
7487 | **/ | |
7488 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
7489 | { | |
c60fbb00 AD |
7490 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7491 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
7492 | |
7493 | set_bit(__IXGBE_DOWN, &adapter->state); | |
760141a5 TH |
7494 | |
7495 | /* | |
7496 | * The timers may be rescheduled, so explicitly disable them | |
7497 | * from being rescheduled. | |
c4900be0 DS |
7498 | */ |
7499 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
9a799d71 | 7500 | del_timer_sync(&adapter->watchdog_timer); |
c4900be0 | 7501 | del_timer_sync(&adapter->sfp_timer); |
760141a5 | 7502 | |
c4900be0 DS |
7503 | cancel_work_sync(&adapter->watchdog_task); |
7504 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
7505 | cancel_work_sync(&adapter->multispeed_fiber_task); |
7506 | cancel_work_sync(&adapter->sfp_config_module_task); | |
c4cf55e5 PWJ |
7507 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
7508 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
7509 | cancel_work_sync(&adapter->fdir_reinit_task); | |
760141a5 TH |
7510 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
7511 | cancel_work_sync(&adapter->check_overtemp_task); | |
9a799d71 | 7512 | |
5dd2d332 | 7513 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7514 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
7515 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
7516 | dca_remove_requester(&pdev->dev); | |
7517 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
7518 | } | |
7519 | ||
7520 | #endif | |
332d4a7d YZ |
7521 | #ifdef IXGBE_FCOE |
7522 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
7523 | ixgbe_cleanup_fcoe(adapter); | |
7524 | ||
7525 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
7526 | |
7527 | /* remove the added san mac */ | |
7528 | ixgbe_del_sanmac_netdev(netdev); | |
7529 | ||
c4900be0 DS |
7530 | if (netdev->reg_state == NETREG_REGISTERED) |
7531 | unregister_netdev(netdev); | |
9a799d71 | 7532 | |
1cdd1ec8 GR |
7533 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7534 | ixgbe_disable_sriov(adapter); | |
7535 | ||
7a921c93 | 7536 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 7537 | |
021230d4 | 7538 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
7539 | |
7540 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 7541 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7542 | IORESOURCE_MEM)); |
9a799d71 | 7543 | |
849c4542 | 7544 | e_dev_info("complete\n"); |
021230d4 | 7545 | |
9a799d71 AK |
7546 | free_netdev(netdev); |
7547 | ||
19d5afd4 | 7548 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 7549 | |
9a799d71 AK |
7550 | pci_disable_device(pdev); |
7551 | } | |
7552 | ||
7553 | /** | |
7554 | * ixgbe_io_error_detected - called when PCI error is detected | |
7555 | * @pdev: Pointer to PCI device | |
7556 | * @state: The current pci connection state | |
7557 | * | |
7558 | * This function is called after a PCI bus error affecting | |
7559 | * this device has been detected. | |
7560 | */ | |
7561 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
e8e9f696 | 7562 | pci_channel_state_t state) |
9a799d71 | 7563 | { |
c60fbb00 AD |
7564 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7565 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
7566 | |
7567 | netif_device_detach(netdev); | |
7568 | ||
3044b8d1 BL |
7569 | if (state == pci_channel_io_perm_failure) |
7570 | return PCI_ERS_RESULT_DISCONNECT; | |
7571 | ||
9a799d71 AK |
7572 | if (netif_running(netdev)) |
7573 | ixgbe_down(adapter); | |
7574 | pci_disable_device(pdev); | |
7575 | ||
b4617240 | 7576 | /* Request a slot reset. */ |
9a799d71 AK |
7577 | return PCI_ERS_RESULT_NEED_RESET; |
7578 | } | |
7579 | ||
7580 | /** | |
7581 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
7582 | * @pdev: Pointer to PCI device | |
7583 | * | |
7584 | * Restart the card from scratch, as if from a cold-boot. | |
7585 | */ | |
7586 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
7587 | { | |
c60fbb00 | 7588 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6fabd715 PWJ |
7589 | pci_ers_result_t result; |
7590 | int err; | |
9a799d71 | 7591 | |
9ce77666 | 7592 | if (pci_enable_device_mem(pdev)) { |
396e799c | 7593 | e_err(probe, "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
7594 | result = PCI_ERS_RESULT_DISCONNECT; |
7595 | } else { | |
7596 | pci_set_master(pdev); | |
7597 | pci_restore_state(pdev); | |
c0e1f68b | 7598 | pci_save_state(pdev); |
9a799d71 | 7599 | |
dd4d8ca6 | 7600 | pci_wake_from_d3(pdev, false); |
9a799d71 | 7601 | |
6fabd715 | 7602 | ixgbe_reset(adapter); |
88512539 | 7603 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
7604 | result = PCI_ERS_RESULT_RECOVERED; |
7605 | } | |
7606 | ||
7607 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
7608 | if (err) { | |
849c4542 ET |
7609 | e_dev_err("pci_cleanup_aer_uncorrect_error_status " |
7610 | "failed 0x%0x\n", err); | |
6fabd715 PWJ |
7611 | /* non-fatal, continue */ |
7612 | } | |
9a799d71 | 7613 | |
6fabd715 | 7614 | return result; |
9a799d71 AK |
7615 | } |
7616 | ||
7617 | /** | |
7618 | * ixgbe_io_resume - called when traffic can start flowing again. | |
7619 | * @pdev: Pointer to PCI device | |
7620 | * | |
7621 | * This callback is called when the error recovery driver tells us that | |
7622 | * its OK to resume normal operation. | |
7623 | */ | |
7624 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
7625 | { | |
c60fbb00 AD |
7626 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7627 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
7628 | |
7629 | if (netif_running(netdev)) { | |
7630 | if (ixgbe_up(adapter)) { | |
396e799c | 7631 | e_info(probe, "ixgbe_up failed after reset\n"); |
9a799d71 AK |
7632 | return; |
7633 | } | |
7634 | } | |
7635 | ||
7636 | netif_device_attach(netdev); | |
9a799d71 AK |
7637 | } |
7638 | ||
7639 | static struct pci_error_handlers ixgbe_err_handler = { | |
7640 | .error_detected = ixgbe_io_error_detected, | |
7641 | .slot_reset = ixgbe_io_slot_reset, | |
7642 | .resume = ixgbe_io_resume, | |
7643 | }; | |
7644 | ||
7645 | static struct pci_driver ixgbe_driver = { | |
7646 | .name = ixgbe_driver_name, | |
7647 | .id_table = ixgbe_pci_tbl, | |
7648 | .probe = ixgbe_probe, | |
7649 | .remove = __devexit_p(ixgbe_remove), | |
7650 | #ifdef CONFIG_PM | |
7651 | .suspend = ixgbe_suspend, | |
7652 | .resume = ixgbe_resume, | |
7653 | #endif | |
7654 | .shutdown = ixgbe_shutdown, | |
7655 | .err_handler = &ixgbe_err_handler | |
7656 | }; | |
7657 | ||
7658 | /** | |
7659 | * ixgbe_init_module - Driver Registration Routine | |
7660 | * | |
7661 | * ixgbe_init_module is the first routine called when the driver is | |
7662 | * loaded. All it does is register with the PCI subsystem. | |
7663 | **/ | |
7664 | static int __init ixgbe_init_module(void) | |
7665 | { | |
7666 | int ret; | |
c7689578 | 7667 | pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); |
849c4542 | 7668 | pr_info("%s\n", ixgbe_copyright); |
9a799d71 | 7669 | |
5dd2d332 | 7670 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7671 | dca_register_notify(&dca_notifier); |
bd0362dd | 7672 | #endif |
5dd2d332 | 7673 | |
9a799d71 AK |
7674 | ret = pci_register_driver(&ixgbe_driver); |
7675 | return ret; | |
7676 | } | |
b4617240 | 7677 | |
9a799d71 AK |
7678 | module_init(ixgbe_init_module); |
7679 | ||
7680 | /** | |
7681 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
7682 | * | |
7683 | * ixgbe_exit_module is called just before the driver is removed | |
7684 | * from memory. | |
7685 | **/ | |
7686 | static void __exit ixgbe_exit_module(void) | |
7687 | { | |
5dd2d332 | 7688 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7689 | dca_unregister_notify(&dca_notifier); |
7690 | #endif | |
9a799d71 | 7691 | pci_unregister_driver(&ixgbe_driver); |
1a51502b | 7692 | rcu_barrier(); /* Wait for completion of call_rcu()'s */ |
9a799d71 | 7693 | } |
bd0362dd | 7694 | |
5dd2d332 | 7695 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7696 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
e8e9f696 | 7697 | void *p) |
bd0362dd JC |
7698 | { |
7699 | int ret_val; | |
7700 | ||
7701 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
e8e9f696 | 7702 | __ixgbe_notify_dca); |
bd0362dd JC |
7703 | |
7704 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
7705 | } | |
b453368d | 7706 | |
5dd2d332 | 7707 | #endif /* CONFIG_IXGBE_DCA */ |
849c4542 | 7708 | |
b453368d | 7709 | /** |
849c4542 | 7710 | * ixgbe_get_hw_dev return device |
b453368d AD |
7711 | * used by hardware layer to print debugging information |
7712 | **/ | |
849c4542 | 7713 | struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw) |
b453368d AD |
7714 | { |
7715 | struct ixgbe_adapter *adapter = hw->back; | |
849c4542 | 7716 | return adapter->netdev; |
b453368d | 7717 | } |
bd0362dd | 7718 | |
9a799d71 AK |
7719 | module_exit(ixgbe_exit_module); |
7720 | ||
7721 | /* ixgbe_main.c */ |