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ixgbe: Merge ATR reinit into the service task
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
e8e9f696 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
75e3d3c6 54#define MAJ 3
c89c7112
DS		 55#define MIN 3
56#define BUILD 8
75e3d3c6
JK		 57#define KFIX 2
58#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
59 __stringify(BUILD) "-k" __stringify(KFIX)
9c8eb720 60const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 61static const char ixgbe_copyright[] =
62 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 63
64static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 65 [board_82598] = &ixgbe_82598_info,
e8e26350 66 [board_82599] = &ixgbe_82599_info,
fe15e8e1 67 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 68};
69
70/* ixgbe_pci_tbl - PCI Device ID Table
71 *
72 * Wildcard entries (PCI_ANY_ID) should come last
73 * Last entry must be all 0s
74 *
75 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
76 * Class, Class Mask, private data (not used) }
77 */
a3aa1884 78static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
80 board_82598 },
9a799d71 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 84 board_82598 },
0befdb3e
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
86 board_82598 },
3845bec0
PWJ		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
88 board_82598 },
9a799d71 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 90 board_82598 },
8d792cd9
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
94 board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
96 board_82598 },
b95f5fcb
JB		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
98 board_82598 },
c4900be0
DS		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
100 board_82598 },
2f21bdd3
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
102 board_82598 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
104 board_82599 },
1fcf03e6
PWJ		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
106 board_82599 },
74757d49
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
108 board_82599 },
e8e26350
PW		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
110 board_82599 },
38ad1c8e
DS		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
112 board_82599 },
dbfec662
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
114 board_82599 },
8911184f
PWJ		 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
116 board_82599 },
dbffcb21
DS		 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
118 board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
120 board_82599 },
119fc60a
MC		 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
122 board_82599 },
312eb931
DS		 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
124 board_82599 },
b93a2226 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
d994653d 126 board_X540 },
4c40ef02
ET		 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
128 board_82599 },
9a799d71
AK		 129
130 /* required last entry */
131 {0, }
132};
133MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
134
5dd2d332 135#ifdef CONFIG_IXGBE_DCA
bd0362dd 136static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 137 void *p);
bd0362dd
JC		 138static struct notifier_block dca_notifier = {
139 .notifier_call = ixgbe_notify_dca,
140 .next = NULL,
141 .priority = 0
142};
143#endif
144
1cdd1ec8
GR		 145#ifdef CONFIG_PCI_IOV
146static unsigned int max_vfs;
147module_param(max_vfs, uint, 0);
e8e9f696
JP		 148MODULE_PARM_DESC(max_vfs,
149 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 150#endif /* CONFIG_PCI_IOV */
151
9a799d71
AK		 152MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
153MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
154MODULE_LICENSE("GPL");
155MODULE_VERSION(DRV_VERSION);
156
157#define DEFAULT_DEBUG_LEVEL_SHIFT 3
158
1cdd1ec8
GR		 159static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
160{
161 struct ixgbe_hw *hw = &adapter->hw;
162 u32 gcr;
163 u32 gpie;
164 u32 vmdctl;
165
166#ifdef CONFIG_PCI_IOV
167 /* disable iov and allow time for transactions to clear */
168 pci_disable_sriov(adapter->pdev);
169#endif
170
171 /* turn off device IOV mode */
172 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
173 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
174 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
175 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
176 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
177 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
178
179 /* set default pool back to 0 */
180 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
181 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
182 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
183
184 /* take a breather then clean up driver data */
185 msleep(100);
e8e9f696
JP		 186
187 kfree(adapter->vfinfo);
1cdd1ec8
GR		 188 adapter->vfinfo = NULL;
189
190 adapter->num_vfs = 0;
191 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
192}
193
7086400d
AD		 194static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
195{
196 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
197 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
198 schedule_work(&adapter->service_task);
199}
200
201static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
202{
203 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
204
205 /* flush memory to make sure state is correct before next watchog */
206 smp_mb__before_clear_bit();
207 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
208}
209
dcd79aeb
TI		 210struct ixgbe_reg_info {
211 u32 ofs;
212 char *name;
213};
214
215static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
216
217 /* General Registers */
218 {IXGBE_CTRL, "CTRL"},
219 {IXGBE_STATUS, "STATUS"},
220 {IXGBE_CTRL_EXT, "CTRL_EXT"},
221
222 /* Interrupt Registers */
223 {IXGBE_EICR, "EICR"},
224
225 /* RX Registers */
226 {IXGBE_SRRCTL(0), "SRRCTL"},
227 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
228 {IXGBE_RDLEN(0), "RDLEN"},
229 {IXGBE_RDH(0), "RDH"},
230 {IXGBE_RDT(0), "RDT"},
231 {IXGBE_RXDCTL(0), "RXDCTL"},
232 {IXGBE_RDBAL(0), "RDBAL"},
233 {IXGBE_RDBAH(0), "RDBAH"},
234
235 /* TX Registers */
236 {IXGBE_TDBAL(0), "TDBAL"},
237 {IXGBE_TDBAH(0), "TDBAH"},
238 {IXGBE_TDLEN(0), "TDLEN"},
239 {IXGBE_TDH(0), "TDH"},
240 {IXGBE_TDT(0), "TDT"},
241 {IXGBE_TXDCTL(0), "TXDCTL"},
242
243 /* List Terminator */
244 {}
245};
246
247
248/*
249 * ixgbe_regdump - register printout routine
250 */
251static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
252{
253 int i = 0, j = 0;
254 char rname[16];
255 u32 regs[64];
256
257 switch (reginfo->ofs) {
258 case IXGBE_SRRCTL(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
261 break;
262 case IXGBE_DCA_RXCTRL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
265 break;
266 case IXGBE_RDLEN(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
269 break;
270 case IXGBE_RDH(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
273 break;
274 case IXGBE_RDT(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
277 break;
278 case IXGBE_RXDCTL(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
281 break;
282 case IXGBE_RDBAL(0):
283 for (i = 0; i < 64; i++)
284 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
285 break;
286 case IXGBE_RDBAH(0):
287 for (i = 0; i < 64; i++)
288 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
289 break;
290 case IXGBE_TDBAL(0):
291 for (i = 0; i < 64; i++)
292 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
293 break;
294 case IXGBE_TDBAH(0):
295 for (i = 0; i < 64; i++)
296 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
297 break;
298 case IXGBE_TDLEN(0):
299 for (i = 0; i < 64; i++)
300 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
301 break;
302 case IXGBE_TDH(0):
303 for (i = 0; i < 64; i++)
304 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
305 break;
306 case IXGBE_TDT(0):
307 for (i = 0; i < 64; i++)
308 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
309 break;
310 case IXGBE_TXDCTL(0):
311 for (i = 0; i < 64; i++)
312 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
313 break;
314 default:
c7689578 315 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 316 IXGBE_READ_REG(hw, reginfo->ofs));
317 return;
318 }
319
320 for (i = 0; i < 8; i++) {
321 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 322 pr_err("%-15s", rname);
dcd79aeb 323 for (j = 0; j < 8; j++)
c7689578
JP		 324 pr_cont(" %08x", regs[i*8+j]);
325 pr_cont("\n");
dcd79aeb
TI		 326 }
327
328}
329
330/*
331 * ixgbe_dump - Print registers, tx-rings and rx-rings
332 */
333static void ixgbe_dump(struct ixgbe_adapter *adapter)
334{
335 struct net_device *netdev = adapter->netdev;
336 struct ixgbe_hw *hw = &adapter->hw;
337 struct ixgbe_reg_info *reginfo;
338 int n = 0;
339 struct ixgbe_ring *tx_ring;
340 struct ixgbe_tx_buffer *tx_buffer_info;
341 union ixgbe_adv_tx_desc *tx_desc;
342 struct my_u0 { u64 a; u64 b; } *u0;
343 struct ixgbe_ring *rx_ring;
344 union ixgbe_adv_rx_desc *rx_desc;
345 struct ixgbe_rx_buffer *rx_buffer_info;
346 u32 staterr;
347 int i = 0;
348
349 if (!netif_msg_hw(adapter))
350 return;
351
352 /* Print netdevice Info */
353 if (netdev) {
354 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 355 pr_info("Device Name state "
dcd79aeb 356 "trans_start last_rx\n");
c7689578
JP		 357 pr_info("%-15s %016lX %016lX %016lX\n",
358 netdev->name,
359 netdev->state,
360 netdev->trans_start,
361 netdev->last_rx);
dcd79aeb
TI		 362 }
363
364 /* Print Registers */
365 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 366 pr_info(" Register Name Value\n");
dcd79aeb
TI		 367 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
368 reginfo->name; reginfo++) {
369 ixgbe_regdump(hw, reginfo);
370 }
371
372 /* Print TX Ring Summary */
373 if (!netdev || !netif_running(netdev))
374 goto exit;
375
376 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 377 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 378 for (n = 0; n < adapter->num_tx_queues; n++) {
379 tx_ring = adapter->tx_ring[n];
380 tx_buffer_info =
381 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 382 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 383 n, tx_ring->next_to_use, tx_ring->next_to_clean,
384 (u64)tx_buffer_info->dma,
385 tx_buffer_info->length,
386 tx_buffer_info->next_to_watch,
387 (u64)tx_buffer_info->time_stamp);
388 }
389
390 /* Print TX Rings */
391 if (!netif_msg_tx_done(adapter))
392 goto rx_ring_summary;
393
394 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
395
396 /* Transmit Descriptor Formats
397 *
398 * Advanced Transmit Descriptor
399 * +--------------------------------------------------------------+
400 * 0 | Buffer Address [63:0] |
401 * +--------------------------------------------------------------+
402 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
403 * +--------------------------------------------------------------+
404 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
405 */
406
407 for (n = 0; n < adapter->num_tx_queues; n++) {
408 tx_ring = adapter->tx_ring[n];
c7689578
JP		 409 pr_info("------------------------------------\n");
410 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
411 pr_info("------------------------------------\n");
412 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 413 "[PlPOIdStDDt Ln] [bi->dma ] "
414 "leng ntw timestamp bi->skb\n");
415
416 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 417 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 418 tx_buffer_info = &tx_ring->tx_buffer_info[i];
419 u0 = (struct my_u0 *)tx_desc;
c7689578 420 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 421 " %04X %3X %016llX %p", i,
422 le64_to_cpu(u0->a),
423 le64_to_cpu(u0->b),
424 (u64)tx_buffer_info->dma,
425 tx_buffer_info->length,
426 tx_buffer_info->next_to_watch,
427 (u64)tx_buffer_info->time_stamp,
428 tx_buffer_info->skb);
429 if (i == tx_ring->next_to_use &&
430 i == tx_ring->next_to_clean)
c7689578 431 pr_cont(" NTC/U\n");
dcd79aeb 432 else if (i == tx_ring->next_to_use)
c7689578 433 pr_cont(" NTU\n");
dcd79aeb 434 else if (i == tx_ring->next_to_clean)
c7689578 435 pr_cont(" NTC\n");
dcd79aeb 436 else
c7689578 437 pr_cont("\n");
dcd79aeb
TI		 438
439 if (netif_msg_pktdata(adapter) &&
440 tx_buffer_info->dma != 0)
441 print_hex_dump(KERN_INFO, "",
442 DUMP_PREFIX_ADDRESS, 16, 1,
443 phys_to_virt(tx_buffer_info->dma),
444 tx_buffer_info->length, true);
445 }
446 }
447
448 /* Print RX Rings Summary */
449rx_ring_summary:
450 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 451 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 452 for (n = 0; n < adapter->num_rx_queues; n++) {
453 rx_ring = adapter->rx_ring[n];
c7689578
JP		 454 pr_info("%5d %5X %5X\n",
455 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 456 }
457
458 /* Print RX Rings */
459 if (!netif_msg_rx_status(adapter))
460 goto exit;
461
462 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
463
464 /* Advanced Receive Descriptor (Read) Format
465 * 63 1 0
466 * +-----------------------------------------------------+
467 * 0 | Packet Buffer Address [63:1] |A0/NSE|
468 * +----------------------------------------------+------+
469 * 8 | Header Buffer Address [63:1] | DD |
470 * +-----------------------------------------------------+
471 *
472 *
473 * Advanced Receive Descriptor (Write-Back) Format
474 *
475 * 63 48 47 32 31 30 21 20 16 15 4 3 0
476 * +------------------------------------------------------+
477 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
478 * | Checksum Ident | | | | Type | Type |
479 * +------------------------------------------------------+
480 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
481 * +------------------------------------------------------+
482 * 63 48 47 32 31 20 19 0
483 */
484 for (n = 0; n < adapter->num_rx_queues; n++) {
485 rx_ring = adapter->rx_ring[n];
c7689578
JP		 486 pr_info("------------------------------------\n");
487 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
488 pr_info("------------------------------------\n");
489 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 490 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
491 "<-- Adv Rx Read format\n");
c7689578 492 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 493 "[vl er S cks ln] ---------------- [bi->skb] "
494 "<-- Adv Rx Write-Back format\n");
495
496 for (i = 0; i < rx_ring->count; i++) {
497 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 498 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 499 u0 = (struct my_u0 *)rx_desc;
500 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
501 if (staterr & IXGBE_RXD_STAT_DD) {
502 /* Descriptor Done */
c7689578 503 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 504 "%016llX ---------------- %p", i,
505 le64_to_cpu(u0->a),
506 le64_to_cpu(u0->b),
507 rx_buffer_info->skb);
508 } else {
c7689578 509 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 510 "%016llX %016llX %p", i,
511 le64_to_cpu(u0->a),
512 le64_to_cpu(u0->b),
513 (u64)rx_buffer_info->dma,
514 rx_buffer_info->skb);
515
516 if (netif_msg_pktdata(adapter)) {
517 print_hex_dump(KERN_INFO, "",
518 DUMP_PREFIX_ADDRESS, 16, 1,
519 phys_to_virt(rx_buffer_info->dma),
520 rx_ring->rx_buf_len, true);
521
522 if (rx_ring->rx_buf_len
523 < IXGBE_RXBUFFER_2048)
524 print_hex_dump(KERN_INFO, "",
525 DUMP_PREFIX_ADDRESS, 16, 1,
526 phys_to_virt(
527 rx_buffer_info->page_dma +
528 rx_buffer_info->page_offset
529 ),
530 PAGE_SIZE/2, true);
531 }
532 }
533
534 if (i == rx_ring->next_to_use)
c7689578 535 pr_cont(" NTU\n");
dcd79aeb 536 else if (i == rx_ring->next_to_clean)
c7689578 537 pr_cont(" NTC\n");
dcd79aeb 538 else
c7689578 539 pr_cont("\n");
dcd79aeb
TI		 540
541 }
542 }
543
544exit:
545 return;
546}
547
5eba3699
AV		 548static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
549{
550 u32 ctrl_ext;
551
552 /* Let firmware take over control of h/w */
553 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
554 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 555 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 556}
557
558static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
559{
560 u32 ctrl_ext;
561
562 /* Let firmware know the driver has taken over */
563 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
564 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 565 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 566}
9a799d71 567
e8e26350
PW		 568/*
569 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
570 * @adapter: pointer to adapter struct
571 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
572 * @queue: queue to map the corresponding interrupt to
573 * @msix_vector: the vector to map to the corresponding queue
574 *
575 */
576static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 577 u8 queue, u8 msix_vector)
9a799d71
AK		 578{
579 u32 ivar, index;
e8e26350
PW		 580 struct ixgbe_hw *hw = &adapter->hw;
581 switch (hw->mac.type) {
582 case ixgbe_mac_82598EB:
583 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
584 if (direction == -1)
585 direction = 0;
586 index = (((direction * 64) + queue) >> 2) & 0x1F;
587 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
588 ivar &= ~(0xFF << (8 * (queue & 0x3)));
589 ivar |= (msix_vector << (8 * (queue & 0x3)));
590 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
591 break;
592 case ixgbe_mac_82599EB:
b93a2226 593 case ixgbe_mac_X540:
e8e26350
PW		 594 if (direction == -1) {
595 /* other causes */
596 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
597 index = ((queue & 1) * 8);
598 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
599 ivar &= ~(0xFF << index);
600 ivar |= (msix_vector << index);
601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
602 break;
603 } else {
604 /* tx or rx causes */
605 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
606 index = ((16 * (queue & 1)) + (8 * direction));
607 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
608 ivar &= ~(0xFF << index);
609 ivar |= (msix_vector << index);
610 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
611 break;
612 }
613 default:
614 break;
615 }
9a799d71
AK		 616}
617
fe49f04a 618static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 619 u64 qmask)
fe49f04a
AD		 620{
621 u32 mask;
622
bd508178
AD		 623 switch (adapter->hw.mac.type) {
624 case ixgbe_mac_82598EB:
fe49f04a
AD		 625 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
626 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 627 break;
628 case ixgbe_mac_82599EB:
b93a2226 629 case ixgbe_mac_X540:
fe49f04a
AD		 630 mask = (qmask & 0xFFFFFFFF);
631 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
632 mask = (qmask >> 32);
633 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 634 break;
635 default:
636 break;
fe49f04a
AD		 637 }
638}
639
b6ec895e
AD		 640void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
641 struct ixgbe_tx_buffer *tx_buffer_info)
9a799d71 642{
e5a43549
AD		 643 if (tx_buffer_info->dma) {
644 if (tx_buffer_info->mapped_as_page)
b6ec895e 645 dma_unmap_page(tx_ring->dev,
e5a43549
AD		 646 tx_buffer_info->dma,
647 tx_buffer_info->length,
1b507730 648 DMA_TO_DEVICE);
e5a43549 649 else
b6ec895e 650 dma_unmap_single(tx_ring->dev,
e5a43549
AD		 651 tx_buffer_info->dma,
652 tx_buffer_info->length,
1b507730 653 DMA_TO_DEVICE);
e5a43549
AD		 654 tx_buffer_info->dma = 0;
655 }
9a799d71
AK		 656 if (tx_buffer_info->skb) {
657 dev_kfree_skb_any(tx_buffer_info->skb);
658 tx_buffer_info->skb = NULL;
659 }
44df32c5 660 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 661 /* tx_buffer_info must be completely set up in the transmit path */
662}
663
26f23d82 664/**
c84d324c
JF		 665 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
666 * @adapter: driver private struct
667 * @index: reg idx of queue to query (0-127)
26f23d82 668 *
25985edc 669 * Helper function to determine the traffic index for a particular
c84d324c 670 * register index.
26f23d82 671 *
c84d324c 672 * Returns : a tc index for use in range 0-7, or 0-3
26f23d82 673 */
3b2ee943 674static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
26f23d82 675{
c84d324c 676 int tc = -1;
e5b64635 677 int dcb_i = netdev_get_num_tc(adapter->netdev);
26f23d82 678
c84d324c
JF		 679 /* if DCB is not enabled the queues have no TC */
680 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
681 return tc;
26f23d82 682
c84d324c
JF		 683 /* check valid range */
684 if (reg_idx >= adapter->hw.mac.max_tx_queues)
685 return tc;
686
687 switch (adapter->hw.mac.type) {
688 case ixgbe_mac_82598EB:
689 tc = reg_idx >> 2;
690 break;
691 default:
692 if (dcb_i != 4 && dcb_i != 8)
6837e895 693 break;
c84d324c
JF		 694
695 /* if VMDq is enabled the lowest order bits determine TC */
696 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
697 IXGBE_FLAG_VMDQ_ENABLED)) {
698 tc = reg_idx & (dcb_i - 1);
699 break;
700 }
701
702 /*
703 * Convert the reg_idx into the correct TC. This bitmask
704 * targets the last full 32 ring traffic class and assigns
705 * it a value of 1. From there the rest of the rings are
706 * based on shifting the mask further up to include the
707 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
708 * will only ever be 8 or 4 and that reg_idx will never
709 * be greater then 128. The code without the power of 2
710 * optimizations would be:
711 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
712 */
713 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
714 tc >>= 9 - (reg_idx >> 5);
715 }
716
717 return tc;
718}
719
720static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
721{
722 struct ixgbe_hw *hw = &adapter->hw;
723 struct ixgbe_hw_stats *hwstats = &adapter->stats;
724 u32 data = 0;
725 u32 xoff[8] = {0};
726 int i;
727
728 if ((hw->fc.current_mode == ixgbe_fc_full) ||
729 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
730 switch (hw->mac.type) {
731 case ixgbe_mac_82598EB:
732 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 733 break;
734 default:
c84d324c
JF		 735 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
736 }
737 hwstats->lxoffrxc += data;
738
739 /* refill credits (no tx hang) if we received xoff */
740 if (!data)
741 return;
742
743 for (i = 0; i < adapter->num_tx_queues; i++)
744 clear_bit(__IXGBE_HANG_CHECK_ARMED,
745 &adapter->tx_ring[i]->state);
746 return;
747 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
748 return;
749
750 /* update stats for each tc, only valid with PFC enabled */
751 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
752 switch (hw->mac.type) {
753 case ixgbe_mac_82598EB:
754 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 755 break;
c84d324c
JF		 756 default:
757 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 758 }
c84d324c
JF		 759 hwstats->pxoffrxc[i] += xoff[i];
760 }
761
762 /* disarm tx queues that have received xoff frames */
763 for (i = 0; i < adapter->num_tx_queues; i++) {
764 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
765 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
766
767 if (xoff[tc])
768 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 769 }
26f23d82
YZ		 770}
771
c84d324c 772static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 773{
c84d324c
JF		 774 return ring->tx_stats.completed;
775}
776
777static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
778{
779 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 780 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 781
c84d324c
JF		 782 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
783 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
784
785 if (head != tail)
786 return (head < tail) ?
787 tail - head : (tail + ring->count - head);
788
789 return 0;
790}
791
792static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
793{
794 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
795 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
796 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
797 bool ret = false;
798
7d637bcc 799 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 800
801 /*
802 * Check for a hung queue, but be thorough. This verifies
803 * that a transmit has been completed since the previous
804 * check AND there is at least one packet pending. The
805 * ARMED bit is set to indicate a potential hang. The
806 * bit is cleared if a pause frame is received to remove
807 * false hang detection due to PFC or 802.3x frames. By
808 * requiring this to fail twice we avoid races with
809 * pfc clearing the ARMED bit and conditions where we
810 * run the check_tx_hang logic with a transmit completion
811 * pending but without time to complete it yet.
812 */
813 if ((tx_done_old == tx_done) && tx_pending) {
814 /* make sure it is true for two checks in a row */
815 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
816 &tx_ring->state);
817 } else {
818 /* update completed stats and continue */
819 tx_ring->tx_stats.tx_done_old = tx_done;
820 /* reset the countdown */
821 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 822 }
823
c84d324c 824 return ret;
9a799d71
AK		 825}
826
b4617240
PW		 827#define IXGBE_MAX_TXD_PWR 14
828#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 829
830/* Tx Descriptors needed, worst case */
831#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
832 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
833#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 834 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 835
c83c6cbd
AD		 836/**
837 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
838 * @adapter: driver private struct
839 **/
840static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
841{
842
843 /* Do the reset outside of interrupt context */
844 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
845 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
846 ixgbe_service_event_schedule(adapter);
847 }
848}
e01c31a5 849
9a799d71
AK		 850/**
851 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 852 * @q_vector: structure containing interrupt and ring information
e01c31a5 853 * @tx_ring: tx ring to clean
9a799d71 854 **/
fe49f04a 855static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 856 struct ixgbe_ring *tx_ring)
9a799d71 857{
fe49f04a 858 struct ixgbe_adapter *adapter = q_vector->adapter;
12207e49
PWJ		 859 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
860 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5 861 unsigned int total_bytes = 0, total_packets = 0;
b953799e 862 u16 i, eop, count = 0;
9a799d71
AK		 863
864 i = tx_ring->next_to_clean;
12207e49 865 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 866 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 867
868 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 869 (count < tx_ring->work_limit)) {
12207e49 870 bool cleaned = false;
2d0bb1c1 871 rmb(); /* read buffer_info after eop_desc */
12207e49 872 for ( ; !cleaned; count++) {
31f05a2d 873 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 874 tx_buffer_info = &tx_ring->tx_buffer_info[i];
8ad494b0
AD		 875
876 tx_desc->wb.status = 0;
12207e49 877 cleaned = (i == eop);
9a799d71 878
8ad494b0
AD		 879 i++;
880 if (i == tx_ring->count)
881 i = 0;
e01c31a5 882
8ad494b0
AD		 883 if (cleaned && tx_buffer_info->skb) {
884 total_bytes += tx_buffer_info->bytecount;
885 total_packets += tx_buffer_info->gso_segs;
e092be60 886 }
e01c31a5 887
b6ec895e 888 ixgbe_unmap_and_free_tx_resource(tx_ring,
e8e9f696 889 tx_buffer_info);
e01c31a5 890 }
12207e49 891
c84d324c 892 tx_ring->tx_stats.completed++;
12207e49 893 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 894 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 895 }
896
9a799d71 897 tx_ring->next_to_clean = i;
b953799e
AD		 898 tx_ring->total_bytes += total_bytes;
899 tx_ring->total_packets += total_packets;
900 u64_stats_update_begin(&tx_ring->syncp);
901 tx_ring->stats.packets += total_packets;
902 tx_ring->stats.bytes += total_bytes;
903 u64_stats_update_end(&tx_ring->syncp);
904
c84d324c
JF		 905 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
906 /* schedule immediate reset if we believe we hung */
907 struct ixgbe_hw *hw = &adapter->hw;
908 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
909 e_err(drv, "Detected Tx Unit Hang\n"
910 " Tx Queue <%d>\n"
911 " TDH, TDT <%x>, <%x>\n"
912 " next_to_use <%x>\n"
913 " next_to_clean <%x>\n"
914 "tx_buffer_info[next_to_clean]\n"
915 " time_stamp <%lx>\n"
916 " jiffies <%lx>\n",
917 tx_ring->queue_index,
918 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
919 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
920 tx_ring->next_to_use, eop,
921 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
922
923 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
924
925 e_info(probe,
926 "tx hang %d detected on queue %d, resetting adapter\n",
927 adapter->tx_timeout_count + 1, tx_ring->queue_index);
928
b953799e 929 /* schedule immediate reset if we believe we hung */
c83c6cbd 930 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 931
932 /* the adapter is about to reset, no point in enabling stuff */
933 return true;
934 }
9a799d71 935
e092be60 936#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
fc77dc3c 937 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
e8e9f696 938 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 939 /* Make sure that anybody stopping the queue after this
940 * sees the new next_to_clean.
941 */
942 smp_mb();
fc77dc3c 943 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 944 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 945 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 946 ++tx_ring->tx_stats.restart_queue;
30eba97a 947 }
e092be60 948 }
9a799d71 949
807540ba 950 return count < tx_ring->work_limit;
9a799d71
AK		 951}
952
5dd2d332 953#ifdef CONFIG_IXGBE_DCA
bd0362dd 954static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 955 struct ixgbe_ring *rx_ring,
956 int cpu)
bd0362dd 957{
33cf09c9 958 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 959 u32 rxctrl;
33cf09c9
AD		 960 u8 reg_idx = rx_ring->reg_idx;
961
962 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
963 switch (hw->mac.type) {
964 case ixgbe_mac_82598EB:
965 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
966 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
967 break;
968 case ixgbe_mac_82599EB:
b93a2226 969 case ixgbe_mac_X540:
33cf09c9
AD		 970 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
971 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
972 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
973 break;
974 default:
975 break;
bd0362dd 976 }
33cf09c9
AD		 977 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
978 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
979 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 980 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 981}
982
983static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 984 struct ixgbe_ring *tx_ring,
985 int cpu)
bd0362dd 986{
33cf09c9 987 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 988 u32 txctrl;
33cf09c9
AD		 989 u8 reg_idx = tx_ring->reg_idx;
990
991 switch (hw->mac.type) {
992 case ixgbe_mac_82598EB:
993 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
994 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
995 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
996 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 997 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
998 break;
999 case ixgbe_mac_82599EB:
b93a2226 1000 case ixgbe_mac_X540:
33cf09c9
AD		 1001 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
1002 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
1003 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
1004 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
1005 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 1006 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
1007 break;
1008 default:
1009 break;
1010 }
1011}
1012
1013static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1014{
1015 struct ixgbe_adapter *adapter = q_vector->adapter;
bd0362dd 1016 int cpu = get_cpu();
33cf09c9
AD		 1017 long r_idx;
1018 int i;
bd0362dd 1019
33cf09c9
AD		 1020 if (q_vector->cpu == cpu)
1021 goto out_no_update;
1022
1023 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1024 for (i = 0; i < q_vector->txr_count; i++) {
1025 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
1026 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1027 r_idx + 1);
bd0362dd 1028 }
33cf09c9
AD		 1029
1030 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1031 for (i = 0; i < q_vector->rxr_count; i++) {
1032 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1033 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1034 r_idx + 1);
1035 }
1036
1037 q_vector->cpu = cpu;
1038out_no_update:
bd0362dd
JC		 1039 put_cpu();
1040}
1041
1042static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1043{
33cf09c9 1044 int num_q_vectors;
bd0362dd
JC		 1045 int i;
1046
1047 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1048 return;
1049
e35ec126
AD		 1050 /* always use CB2 mode, difference is masked in the CB driver */
1051 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1052
33cf09c9
AD		 1053 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1054 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1055 else
1056 num_q_vectors = 1;
1057
1058 for (i = 0; i < num_q_vectors; i++) {
1059 adapter->q_vector[i]->cpu = -1;
1060 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1061 }
1062}
1063
1064static int __ixgbe_notify_dca(struct device *dev, void *data)
1065{
c60fbb00 1066 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1067 unsigned long event = *(unsigned long *)data;
1068
33cf09c9
AD		 1069 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1070 return 0;
1071
bd0362dd
JC		 1072 switch (event) {
1073 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1074 /* if we're already enabled, don't do it again */
1075 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1076 break;
652f093f 1077 if (dca_add_requester(dev) == 0) {
96b0e0f6 1078 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1079 ixgbe_setup_dca(adapter);
1080 break;
1081 }
1082 /* Fall Through since DCA is disabled. */
1083 case DCA_PROVIDER_REMOVE:
1084 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1085 dca_remove_requester(dev);
1086 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1087 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1088 }
1089 break;
1090 }
1091
652f093f 1092 return 0;
bd0362dd 1093}
5dd2d332 1094#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 1095
1096static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1097 struct sk_buff *skb)
1098{
1099 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1100}
1101
9a799d71
AK		 1102/**
1103 * ixgbe_receive_skb - Send a completed packet up the stack
1104 * @adapter: board private structure
1105 * @skb: packet to send up
177db6ff
MC		 1106 * @status: hardware indication of status of receive
1107 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1108 * @rx_desc: rx descriptor
9a799d71 1109 **/
78b6f4ce 1110static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1111 struct sk_buff *skb, u8 status,
1112 struct ixgbe_ring *ring,
1113 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1114{
78b6f4ce
HX		 1115 struct ixgbe_adapter *adapter = q_vector->adapter;
1116 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1117 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1118 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1119
f62bbb5e
JG		 1120 if (is_vlan && (tag & VLAN_VID_MASK))
1121 __vlan_hwaccel_put_tag(skb, tag);
1122
1123 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1124 napi_gro_receive(napi, skb);
1125 else
1126 netif_rx(skb);
9a799d71
AK		 1127}
1128
e59bd25d
AV		 1129/**
1130 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1131 * @adapter: address of board private structure
1132 * @status_err: hardware indication of status of receive
1133 * @skb: skb currently being received and modified
1134 **/
9a799d71 1135static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 1136 union ixgbe_adv_rx_desc *rx_desc,
1137 struct sk_buff *skb)
9a799d71 1138{
8bae1b2b
DS		 1139 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1140
bc8acf2c 1141 skb_checksum_none_assert(skb);
9a799d71 1142
712744be
JB		 1143 /* Rx csum disabled */
1144 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1145 return;
e59bd25d
AV		 1146
1147 /* if IP and error */
1148 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1149 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1150 adapter->hw_csum_rx_error++;
1151 return;
1152 }
e59bd25d
AV		 1153
1154 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1155 return;
1156
1157 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1158 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1159
1160 /*
1161 * 82599 errata, UDP frames with a 0 checksum can be marked as
1162 * checksum errors.
1163 */
1164 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1165 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1166 return;
1167
e59bd25d
AV		 1168 adapter->hw_csum_rx_error++;
1169 return;
1170 }
1171
9a799d71 1172 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1173 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1174}
1175
84ea2591 1176static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1177{
1178 /*
1179 * Force memory writes to complete before letting h/w
1180 * know there are new descriptors to fetch. (Only
1181 * applicable for weak-ordered memory model archs,
1182 * such as IA-64).
1183 */
1184 wmb();
84ea2591 1185 writel(val, rx_ring->tail);
e8e26350
PW		 1186}
1187
9a799d71
AK		 1188/**
1189 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1190 * @rx_ring: ring to place buffers on
1191 * @cleaned_count: number of buffers to replace
9a799d71 1192 **/
fc77dc3c 1193void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1194{
9a799d71 1195 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1196 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1197 struct sk_buff *skb;
1198 u16 i = rx_ring->next_to_use;
9a799d71 1199
fc77dc3c
AD		 1200 /* do nothing if no valid netdev defined */
1201 if (!rx_ring->netdev)
1202 return;
1203
9a799d71 1204 while (cleaned_count--) {
31f05a2d 1205 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1206 bi = &rx_ring->rx_buffer_info[i];
1207 skb = bi->skb;
9a799d71 1208
d5f398ed 1209 if (!skb) {
fc77dc3c 1210 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1211 rx_ring->rx_buf_len);
9a799d71 1212 if (!skb) {
5b7da515 1213 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1214 goto no_buffers;
1215 }
d716a7d8
AD		 1216 /* initialize queue mapping */
1217 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1218 bi->skb = skb;
d716a7d8 1219 }
9a799d71 1220
d716a7d8 1221 if (!bi->dma) {
b6ec895e 1222 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1223 skb->data,
e8e9f696 1224 rx_ring->rx_buf_len,
1b507730 1225 DMA_FROM_DEVICE);
b6ec895e 1226 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1227 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1228 bi->dma = 0;
1229 goto no_buffers;
1230 }
9a799d71 1231 }
d5f398ed 1232
7d637bcc 1233 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1234 if (!bi->page) {
fc77dc3c 1235 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1236 if (!bi->page) {
5b7da515 1237 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1238 goto no_buffers;
1239 }
1240 }
1241
1242 if (!bi->page_dma) {
1243 /* use a half page if we're re-using */
1244 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1245 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1246 bi->page,
1247 bi->page_offset,
1248 PAGE_SIZE / 2,
1249 DMA_FROM_DEVICE);
b6ec895e 1250 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1251 bi->page_dma)) {
5b7da515 1252 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1253 bi->page_dma = 0;
1254 goto no_buffers;
1255 }
1256 }
1257
1258 /* Refresh the desc even if buffer_addrs didn't change
1259 * because each write-back erases this info. */
3a581073
JB		 1260 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1261 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1262 } else {
3a581073 1263 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1264 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1265 }
1266
1267 i++;
1268 if (i == rx_ring->count)
1269 i = 0;
9a799d71 1270 }
7c6e0a43 1271
9a799d71
AK		 1272no_buffers:
1273 if (rx_ring->next_to_use != i) {
1274 rx_ring->next_to_use = i;
84ea2591 1275 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1276 }
1277}
1278
c267fc16 1279static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1280{
c267fc16
AD		 1281 /* HW will not DMA in data larger than the given buffer, even if it
1282 * parses the (NFS, of course) header to be larger. In that case, it
1283 * fills the header buffer and spills the rest into the page.
1284 */
1285 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1286 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1287 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1288 if (hlen > IXGBE_RX_HDR_SIZE)
1289 hlen = IXGBE_RX_HDR_SIZE;
1290 return hlen;
7c6e0a43
JB		 1291}
1292
f8212f97
AD		 1293/**
1294 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1295 * @skb: pointer to the last skb in the rsc queue
1296 *
1297 * This function changes a queue full of hw rsc buffers into a completed
1298 * packet. It uses the ->prev pointers to find the first packet and then
1299 * turns it into the frag list owner.
1300 **/
aa80175a 1301static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1302{
1303 unsigned int frag_list_size = 0;
aa80175a 1304 unsigned int skb_cnt = 1;
f8212f97
AD		 1305
1306 while (skb->prev) {
1307 struct sk_buff *prev = skb->prev;
1308 frag_list_size += skb->len;
1309 skb->prev = NULL;
1310 skb = prev;
aa80175a 1311 skb_cnt++;
f8212f97
AD		 1312 }
1313
1314 skb_shinfo(skb)->frag_list = skb->next;
1315 skb->next = NULL;
1316 skb->len += frag_list_size;
1317 skb->data_len += frag_list_size;
1318 skb->truesize += frag_list_size;
aa80175a
AD		 1319 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1320
f8212f97
AD		 1321 return skb;
1322}
1323
aa80175a
AD		 1324static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1325{
1326 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1327 IXGBE_RXDADV_RSCCNT_MASK);
1328}
43634e82 1329
c267fc16 1330static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1331 struct ixgbe_ring *rx_ring,
1332 int *work_done, int work_to_do)
9a799d71 1333{
78b6f4ce 1334 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1335 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1336 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1337 struct sk_buff *skb;
d2f4fbe2 1338 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1339 const int current_node = numa_node_id();
3d8fd385
YZ		 1340#ifdef IXGBE_FCOE
1341 int ddp_bytes = 0;
1342#endif /* IXGBE_FCOE */
c267fc16
AD		 1343 u32 staterr;
1344 u16 i;
1345 u16 cleaned_count = 0;
aa80175a 1346 bool pkt_is_rsc = false;
9a799d71
AK		 1347
1348 i = rx_ring->next_to_clean;
31f05a2d 1349 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1350 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1351
1352 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1353 u32 upper_len = 0;
9a799d71 1354
3c945e5b 1355 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1356
c267fc16
AD		 1357 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1358
9a799d71 1359 skb = rx_buffer_info->skb;
9a799d71 1360 rx_buffer_info->skb = NULL;
c267fc16 1361 prefetch(skb->data);
9a799d71 1362
c267fc16 1363 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1364 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16
AD		 1365
1366 /* if this is a skb from previous receive DMA will be 0 */
21fa4e66 1367 if (rx_buffer_info->dma) {
c267fc16 1368 u16 hlen;
aa80175a 1369 if (pkt_is_rsc &&
c267fc16
AD		 1370 !(staterr & IXGBE_RXD_STAT_EOP) &&
1371 !skb->prev) {
43634e82
MC		 1372 /*
1373 * When HWRSC is enabled, delay unmapping
1374 * of the first packet. It carries the
1375 * header information, HW may still
1376 * access the header after the writeback.
1377 * Only unmap it when EOP is reached
1378 */
e8171aaa 1379 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1380 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1381 } else {
b6ec895e 1382 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1383 rx_buffer_info->dma,
1384 rx_ring->rx_buf_len,
1385 DMA_FROM_DEVICE);
e8171aaa 1386 }
4f57ca6e 1387 rx_buffer_info->dma = 0;
c267fc16
AD		 1388
1389 if (ring_is_ps_enabled(rx_ring)) {
1390 hlen = ixgbe_get_hlen(rx_desc);
1391 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1392 } else {
1393 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1394 }
1395
1396 skb_put(skb, hlen);
1397 } else {
1398 /* assume packet split since header is unmapped */
1399 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1400 }
1401
1402 if (upper_len) {
b6ec895e
AD		 1403 dma_unmap_page(rx_ring->dev,
1404 rx_buffer_info->page_dma,
1405 PAGE_SIZE / 2,
1406 DMA_FROM_DEVICE);
9a799d71
AK		 1407 rx_buffer_info->page_dma = 0;
1408 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1409 rx_buffer_info->page,
1410 rx_buffer_info->page_offset,
1411 upper_len);
762f4c57 1412
c267fc16
AD		 1413 if ((page_count(rx_buffer_info->page) == 1) &&
1414 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1415 get_page(rx_buffer_info->page);
c267fc16
AD		 1416 else
1417 rx_buffer_info->page = NULL;
9a799d71
AK		 1418
1419 skb->len += upper_len;
1420 skb->data_len += upper_len;
1421 skb->truesize += upper_len;
1422 }
1423
1424 i++;
1425 if (i == rx_ring->count)
1426 i = 0;
9a799d71 1427
31f05a2d 1428 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1429 prefetch(next_rxd);
9a799d71 1430 cleaned_count++;
f8212f97 1431
aa80175a 1432 if (pkt_is_rsc) {
f8212f97
AD		 1433 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1434 IXGBE_RXDADV_NEXTP_SHIFT;
1435 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1436 } else {
1437 next_buffer = &rx_ring->rx_buffer_info[i];
1438 }
1439
c267fc16 1440 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1441 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1442 rx_buffer_info->skb = next_buffer->skb;
1443 rx_buffer_info->dma = next_buffer->dma;
1444 next_buffer->skb = skb;
1445 next_buffer->dma = 0;
1446 } else {
1447 skb->next = next_buffer->skb;
1448 skb->next->prev = skb;
1449 }
5b7da515 1450 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1451 goto next_desc;
1452 }
1453
aa80175a
AD		 1454 if (skb->prev) {
1455 skb = ixgbe_transform_rsc_queue(skb);
1456 /* if we got here without RSC the packet is invalid */
1457 if (!pkt_is_rsc) {
1458 __pskb_trim(skb, 0);
1459 rx_buffer_info->skb = skb;
1460 goto next_desc;
1461 }
1462 }
c267fc16
AD		 1463
1464 if (ring_is_rsc_enabled(rx_ring)) {
1465 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1466 dma_unmap_single(rx_ring->dev,
1467 IXGBE_RSC_CB(skb)->dma,
1468 rx_ring->rx_buf_len,
1469 DMA_FROM_DEVICE);
1470 IXGBE_RSC_CB(skb)->dma = 0;
1471 IXGBE_RSC_CB(skb)->delay_unmap = false;
1472 }
aa80175a
AD		 1473 }
1474 if (pkt_is_rsc) {
c267fc16
AD		 1475 if (ring_is_ps_enabled(rx_ring))
1476 rx_ring->rx_stats.rsc_count +=
aa80175a 1477 skb_shinfo(skb)->nr_frags;
c267fc16 1478 else
aa80175a
AD		 1479 rx_ring->rx_stats.rsc_count +=
1480 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1481 rx_ring->rx_stats.rsc_flush++;
1482 }
1483
1484 /* ERR_MASK will only have valid bits if EOP set */
9a799d71 1485 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
c267fc16
AD		 1486 /* trim packet back to size 0 and recycle it */
1487 __pskb_trim(skb, 0);
1488 rx_buffer_info->skb = skb;
9a799d71
AK		 1489 goto next_desc;
1490 }
1491
8bae1b2b 1492 ixgbe_rx_checksum(adapter, rx_desc, skb);
67a74ee2
ET		 1493 if (adapter->netdev->features & NETIF_F_RXHASH)
1494 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1495
1496 /* probably a little skewed due to removing CRC */
1497 total_rx_bytes += skb->len;
1498 total_rx_packets++;
1499
fc77dc3c 1500 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1501#ifdef IXGBE_FCOE
1502 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1503 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1504 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1505 if (!ddp_bytes)
332d4a7d 1506 goto next_desc;
3d8fd385 1507 }
332d4a7d 1508#endif /* IXGBE_FCOE */
fdaff1ce 1509 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1510
1511next_desc:
1512 rx_desc->wb.upper.status_error = 0;
1513
c267fc16
AD		 1514 (*work_done)++;
1515 if (*work_done >= work_to_do)
1516 break;
1517
9a799d71
AK		 1518 /* return some buffers to hardware, one at a time is too slow */
1519 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1520 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1521 cleaned_count = 0;
1522 }
1523
1524 /* use prefetched values */
1525 rx_desc = next_rxd;
9a799d71 1526 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1527 }
1528
9a799d71
AK		 1529 rx_ring->next_to_clean = i;
1530 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1531
1532 if (cleaned_count)
fc77dc3c 1533 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1534
3d8fd385
YZ		 1535#ifdef IXGBE_FCOE
1536 /* include DDPed FCoE data */
1537 if (ddp_bytes > 0) {
1538 unsigned int mss;
1539
fc77dc3c 1540 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1541 sizeof(struct fc_frame_header) -
1542 sizeof(struct fcoe_crc_eof);
1543 if (mss > 512)
1544 mss &= ~511;
1545 total_rx_bytes += ddp_bytes;
1546 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1547 }
1548#endif /* IXGBE_FCOE */
1549
f494e8fa
AV		 1550 rx_ring->total_packets += total_rx_packets;
1551 rx_ring->total_bytes += total_rx_bytes;
c267fc16
AD		 1552 u64_stats_update_begin(&rx_ring->syncp);
1553 rx_ring->stats.packets += total_rx_packets;
1554 rx_ring->stats.bytes += total_rx_bytes;
1555 u64_stats_update_end(&rx_ring->syncp);
9a799d71
AK		 1556}
1557
021230d4 1558static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1559/**
1560 * ixgbe_configure_msix - Configure MSI-X hardware
1561 * @adapter: board private structure
1562 *
1563 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1564 * interrupts.
1565 **/
1566static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1567{
021230d4 1568 struct ixgbe_q_vector *q_vector;
bf29ee6c 1569 int i, q_vectors, v_idx, r_idx;
021230d4 1570 u32 mask;
9a799d71 1571
021230d4 1572 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1573
4df10466
JB		 1574 /*
1575 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1576 * corresponding register.
1577 */
1578 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1579 q_vector = adapter->q_vector[v_idx];
984b3f57 1580 /* XXX for_each_set_bit(...) */
021230d4 1581 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1582 adapter->num_rx_queues);
021230d4
AV		 1583
1584 for (i = 0; i < q_vector->rxr_count; i++) {
bf29ee6c
AD		 1585 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1586 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
021230d4 1587 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1588 adapter->num_rx_queues,
1589 r_idx + 1);
021230d4
AV		 1590 }
1591 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1592 adapter->num_tx_queues);
021230d4
AV		 1593
1594 for (i = 0; i < q_vector->txr_count; i++) {
bf29ee6c
AD		 1595 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1596 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
021230d4 1597 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1598 adapter->num_tx_queues,
1599 r_idx + 1);
021230d4
AV		 1600 }
1601
021230d4 1602 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1603 /* tx only */
1604 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1605 else if (q_vector->rxr_count)
f7554a2b
NS		 1606 /* rx or mixed */
1607 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1608
fe49f04a 1609 ixgbe_write_eitr(q_vector);
b25ebfd2
PW		 1610 /* If Flow Director is enabled, set interrupt affinity */
1611 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1612 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1613 /*
1614 * Allocate the affinity_hint cpumask, assign the mask
1615 * for this vector, and set our affinity_hint for
1616 * this irq.
1617 */
1618 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1619 GFP_KERNEL))
1620 return;
1621 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1622 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1623 q_vector->affinity_mask);
1624 }
9a799d71
AK		 1625 }
1626
bd508178
AD		 1627 switch (adapter->hw.mac.type) {
1628 case ixgbe_mac_82598EB:
e8e26350 1629 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1630 v_idx);
bd508178
AD		 1631 break;
1632 case ixgbe_mac_82599EB:
b93a2226 1633 case ixgbe_mac_X540:
e8e26350 1634 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178
AD		 1635 break;
1636
1637 default:
1638 break;
1639 }
021230d4
AV		 1640 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1641
41fb9248 1642 /* set up to autoclear timer, and the vectors */
021230d4 1643 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1644 if (adapter->num_vfs)
1645 mask &= ~(IXGBE_EIMS_OTHER |
1646 IXGBE_EIMS_MAILBOX |
1647 IXGBE_EIMS_LSC);
1648 else
1649 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1650 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1651}
1652
f494e8fa
AV		 1653enum latency_range {
1654 lowest_latency = 0,
1655 low_latency = 1,
1656 bulk_latency = 2,
1657 latency_invalid = 255
1658};
1659
1660/**
1661 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1662 * @adapter: pointer to adapter
1663 * @eitr: eitr setting (ints per sec) to give last timeslice
1664 * @itr_setting: current throttle rate in ints/second
1665 * @packets: the number of packets during this measurement interval
1666 * @bytes: the number of bytes during this measurement interval
1667 *
1668 * Stores a new ITR value based on packets and byte
1669 * counts during the last interrupt. The advantage of per interrupt
1670 * computation is faster updates and more accurate ITR for the current
1671 * traffic pattern. Constants in this function were computed
1672 * based on theoretical maximum wire speed and thresholds were set based
1673 * on testing data as well as attempting to minimize response time
1674 * while increasing bulk throughput.
1675 * this functionality is controlled by the InterruptThrottleRate module
1676 * parameter (see ixgbe_param.c)
1677 **/
1678static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1679 u32 eitr, u8 itr_setting,
1680 int packets, int bytes)
f494e8fa
AV		 1681{
1682 unsigned int retval = itr_setting;
1683 u32 timepassed_us;
1684 u64 bytes_perint;
1685
1686 if (packets == 0)
1687 goto update_itr_done;
1688
1689
1690 /* simple throttlerate management
1691 * 0-20MB/s lowest (100000 ints/s)
1692 * 20-100MB/s low (20000 ints/s)
1693 * 100-1249MB/s bulk (8000 ints/s)
1694 */
1695 /* what was last interrupt timeslice? */
1696 timepassed_us = 1000000/eitr;
1697 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1698
1699 switch (itr_setting) {
1700 case lowest_latency:
1701 if (bytes_perint > adapter->eitr_low)
1702 retval = low_latency;
1703 break;
1704 case low_latency:
1705 if (bytes_perint > adapter->eitr_high)
1706 retval = bulk_latency;
1707 else if (bytes_perint <= adapter->eitr_low)
1708 retval = lowest_latency;
1709 break;
1710 case bulk_latency:
1711 if (bytes_perint <= adapter->eitr_high)
1712 retval = low_latency;
1713 break;
1714 }
1715
1716update_itr_done:
1717 return retval;
1718}
1719
509ee935
JB		 1720/**
1721 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1722 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1723 *
1724 * This function is made to be called by ethtool and by the driver
1725 * when it needs to update EITR registers at runtime. Hardware
1726 * specific quirks/differences are taken care of here.
1727 */
fe49f04a 1728void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1729{
fe49f04a 1730 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1731 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1732 int v_idx = q_vector->v_idx;
1733 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1734
bd508178
AD		 1735 switch (adapter->hw.mac.type) {
1736 case ixgbe_mac_82598EB:
509ee935
JB		 1737 /* must write high and low 16 bits to reset counter */
1738 itr_reg |= (itr_reg << 16);
bd508178
AD		 1739 break;
1740 case ixgbe_mac_82599EB:
b93a2226 1741 case ixgbe_mac_X540:
f8d1dcaf 1742 /*
b93a2226 1743 * 82599 and X540 can support a value of zero, so allow it for
f8d1dcaf
JB		 1744 * max interrupt rate, but there is an errata where it can
1745 * not be zero with RSC
1746 */
1747 if (itr_reg == 8 &&
1748 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1749 itr_reg = 0;
1750
509ee935
JB		 1751 /*
1752 * set the WDIS bit to not clear the timer bits and cause an
1753 * immediate assertion of the interrupt
1754 */
1755 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1756 break;
1757 default:
1758 break;
509ee935
JB		 1759 }
1760 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1761}
1762
f494e8fa
AV		 1763static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1764{
1765 struct ixgbe_adapter *adapter = q_vector->adapter;
125601bf 1766 int i, r_idx;
f494e8fa
AV		 1767 u32 new_itr;
1768 u8 current_itr, ret_itr;
f494e8fa
AV		 1769
1770 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1771 for (i = 0; i < q_vector->txr_count; i++) {
125601bf 1772 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1773 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1774 q_vector->tx_itr,
1775 tx_ring->total_packets,
1776 tx_ring->total_bytes);
f494e8fa
AV		 1777 /* if the result for this queue would decrease interrupt
1778 * rate for this vector then use that result */
30efa5a3 1779 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1780 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1781 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1782 r_idx + 1);
f494e8fa
AV		 1783 }
1784
1785 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1786 for (i = 0; i < q_vector->rxr_count; i++) {
125601bf 1787 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1788 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1789 q_vector->rx_itr,
1790 rx_ring->total_packets,
1791 rx_ring->total_bytes);
f494e8fa
AV		 1792 /* if the result for this queue would decrease interrupt
1793 * rate for this vector then use that result */
30efa5a3 1794 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1795 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1796 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1797 r_idx + 1);
f494e8fa
AV		 1798 }
1799
30efa5a3 1800 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1801
1802 switch (current_itr) {
1803 /* counts and packets in update_itr are dependent on these numbers */
1804 case lowest_latency:
1805 new_itr = 100000;
1806 break;
1807 case low_latency:
1808 new_itr = 20000; /* aka hwitr = ~200 */
1809 break;
1810 case bulk_latency:
1811 default:
1812 new_itr = 8000;
1813 break;
1814 }
1815
1816 if (new_itr != q_vector->eitr) {
fe49f04a 1817 /* do an exponential smoothing */
125601bf 1818 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935
JB		 1819
1820 /* save the algorithm value here, not the smoothed one */
1821 q_vector->eitr = new_itr;
fe49f04a
AD		 1822
1823 ixgbe_write_eitr(q_vector);
f494e8fa 1824 }
f494e8fa
AV		 1825}
1826
119fc60a
MC		 1827/**
1828 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1829 * @work: pointer to work_struct containing our data
1830 **/
1831static void ixgbe_check_overtemp_task(struct work_struct *work)
1832{
1833 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 1834 struct ixgbe_adapter,
1835 check_overtemp_task);
119fc60a
MC		 1836 struct ixgbe_hw *hw = &adapter->hw;
1837 u32 eicr = adapter->interrupt_event;
1838
7ca647bd
JP		 1839 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1840 return;
1841
1842 switch (hw->device_id) {
1843 case IXGBE_DEV_ID_82599_T3_LOM: {
1844 u32 autoneg;
1845 bool link_up = false;
1846
1847 if (hw->mac.ops.check_link)
1848 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1849
1850 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1851 (eicr & IXGBE_EICR_LSC))
1852 /* Check if this is due to overtemp */
1853 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1854 break;
1855 return;
1856 }
1857 default:
1858 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1859 return;
7ca647bd 1860 break;
119fc60a 1861 }
7ca647bd
JP		 1862 e_crit(drv,
1863 "Network adapter has been stopped because it has over heated. "
1864 "Restart the computer. If the problem persists, "
1865 "power off the system and replace the adapter\n");
1866 /* write to clear the interrupt */
1867 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
119fc60a
MC		 1868}
1869
0befdb3e
JB		 1870static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1871{
1872 struct ixgbe_hw *hw = &adapter->hw;
1873
1874 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1875 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1876 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1877 /* write to clear the interrupt */
1878 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1879 }
1880}
cf8280ee 1881
e8e26350
PW		 1882static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1883{
1884 struct ixgbe_hw *hw = &adapter->hw;
1885
73c4b7cd
AD		 1886 if (eicr & IXGBE_EICR_GPI_SDP2) {
1887 /* Clear the interrupt */
1888 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 1889 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1890 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1891 ixgbe_service_event_schedule(adapter);
1892 }
73c4b7cd
AD		 1893 }
1894
e8e26350
PW		 1895 if (eicr & IXGBE_EICR_GPI_SDP1) {
1896 /* Clear the interrupt */
1897 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 1898 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1899 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1900 ixgbe_service_event_schedule(adapter);
1901 }
e8e26350
PW		 1902 }
1903}
1904
cf8280ee
JB		 1905static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1906{
1907 struct ixgbe_hw *hw = &adapter->hw;
1908
1909 adapter->lsc_int++;
1910 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1911 adapter->link_check_timeout = jiffies;
1912 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1913 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1914 IXGBE_WRITE_FLUSH(hw);
93c52dd0 1915 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 1916 }
1917}
1918
9a799d71
AK		 1919static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1920{
1921 struct net_device *netdev = data;
1922 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1923 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1924 u32 eicr;
1925
1926 /*
1927 * Workaround for Silicon errata. Use clear-by-write instead
1928 * of clear-by-read. Reading with EICS will return the
1929 * interrupt causes without clearing, which later be done
1930 * with the write to EICR.
1931 */
1932 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1933 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1934
cf8280ee
JB		 1935 if (eicr & IXGBE_EICR_LSC)
1936 ixgbe_check_lsc(adapter);
d4f80882 1937
1cdd1ec8
GR		 1938 if (eicr & IXGBE_EICR_MAILBOX)
1939 ixgbe_msg_task(adapter);
1940
bd508178
AD		 1941 switch (hw->mac.type) {
1942 case ixgbe_mac_82599EB:
d994653d
DS		 1943 ixgbe_check_sfp_event(adapter, eicr);
1944 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1945 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1946 adapter->interrupt_event = eicr;
1947 schedule_work(&adapter->check_overtemp_task);
1948 }
1949 /* now fallthrough to handle Flow Director */
b93a2226 1950 case ixgbe_mac_X540:
c4cf55e5
PWJ		 1951 /* Handle Flow Director Full threshold interrupt */
1952 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 1953 int reinit_count = 0;
c4cf55e5 1954 int i;
c4cf55e5 1955 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 1956 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 1957 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 1958 &ring->state))
1959 reinit_count++;
1960 }
1961 if (reinit_count) {
1962 /* no more flow director interrupts until after init */
1963 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1964 eicr &= ~IXGBE_EICR_FLOW_DIR;
1965 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1966 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1967 }
1968 }
bd508178
AD		 1969 break;
1970 default:
1971 break;
c4cf55e5 1972 }
bd508178
AD		 1973
1974 ixgbe_check_fan_failure(adapter, eicr);
1975
7086400d 1976 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 1977 if (!test_bit(__IXGBE_DOWN, &adapter->state))
7086400d
AD		 1978 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1979 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
9a799d71
AK		 1980
1981 return IRQ_HANDLED;
1982}
1983
fe49f04a
AD		 1984static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1985 u64 qmask)
1986{
1987 u32 mask;
bd508178 1988 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1989
bd508178
AD		 1990 switch (hw->mac.type) {
1991 case ixgbe_mac_82598EB:
fe49f04a 1992 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1993 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1994 break;
1995 case ixgbe_mac_82599EB:
b93a2226 1996 case ixgbe_mac_X540:
fe49f04a 1997 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1998 if (mask)
1999 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2000 mask = (qmask >> 32);
bd508178
AD		 2001 if (mask)
2002 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2003 break;
2004 default:
2005 break;
fe49f04a
AD		 2006 }
2007 /* skip the flush */
2008}
2009
2010static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2011 u64 qmask)
fe49f04a
AD		 2012{
2013 u32 mask;
bd508178 2014 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2015
bd508178
AD		 2016 switch (hw->mac.type) {
2017 case ixgbe_mac_82598EB:
fe49f04a 2018 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2019 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2020 break;
2021 case ixgbe_mac_82599EB:
b93a2226 2022 case ixgbe_mac_X540:
fe49f04a 2023 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2024 if (mask)
2025 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2026 mask = (qmask >> 32);
bd508178
AD		 2027 if (mask)
2028 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2029 break;
2030 default:
2031 break;
fe49f04a
AD		 2032 }
2033 /* skip the flush */
2034}
2035
9a799d71
AK		 2036static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
2037{
021230d4
AV		 2038 struct ixgbe_q_vector *q_vector = data;
2039 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2040 struct ixgbe_ring *tx_ring;
021230d4
AV		 2041 int i, r_idx;
2042
2043 if (!q_vector->txr_count)
2044 return IRQ_HANDLED;
2045
2046 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2047 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2048 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 2049 tx_ring->total_bytes = 0;
2050 tx_ring->total_packets = 0;
021230d4 2051 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2052 r_idx + 1);
021230d4 2053 }
9a799d71 2054
9b471446 2055 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 2056 napi_schedule(&q_vector->napi);
2057
9a799d71
AK		 2058 return IRQ_HANDLED;
2059}
2060
021230d4
AV		 2061/**
2062 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2063 * @irq: unused
2064 * @data: pointer to our q_vector struct for this interrupt vector
2065 **/
9a799d71
AK		 2066static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2067{
021230d4
AV		 2068 struct ixgbe_q_vector *q_vector = data;
2069 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2070 struct ixgbe_ring *rx_ring;
021230d4 2071 int r_idx;
30efa5a3 2072 int i;
021230d4 2073
33cf09c9
AD		 2074#ifdef CONFIG_IXGBE_DCA
2075 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2076 ixgbe_update_dca(q_vector);
2077#endif
2078
021230d4 2079 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
33cf09c9 2080 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2081 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 2082 rx_ring->total_bytes = 0;
2083 rx_ring->total_packets = 0;
2084 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2085 r_idx + 1);
30efa5a3
JB		 2086 }
2087
021230d4
AV		 2088 if (!q_vector->rxr_count)
2089 return IRQ_HANDLED;
2090
9b471446 2091 /* EIAM disabled interrupts (on this vector) for us */
288379f0 2092 napi_schedule(&q_vector->napi);
021230d4
AV		 2093
2094 return IRQ_HANDLED;
2095}
2096
2097static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2098{
91281fd3
AD		 2099 struct ixgbe_q_vector *q_vector = data;
2100 struct ixgbe_adapter *adapter = q_vector->adapter;
2101 struct ixgbe_ring *ring;
2102 int r_idx;
2103 int i;
2104
2105 if (!q_vector->txr_count && !q_vector->rxr_count)
2106 return IRQ_HANDLED;
2107
2108 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2109 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2110 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2111 ring->total_bytes = 0;
2112 ring->total_packets = 0;
2113 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2114 r_idx + 1);
91281fd3
AD		 2115 }
2116
2117 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2118 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2119 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 2120 ring->total_bytes = 0;
2121 ring->total_packets = 0;
2122 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2123 r_idx + 1);
91281fd3
AD		 2124 }
2125
9b471446 2126 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2127 napi_schedule(&q_vector->napi);
9a799d71 2128
9a799d71
AK		 2129 return IRQ_HANDLED;
2130}
2131
021230d4
AV		 2132/**
2133 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2134 * @napi: napi struct with our devices info in it
2135 * @budget: amount of work driver is allowed to do this pass, in packets
2136 *
f0848276
JB		 2137 * This function is optimized for cleaning one queue only on a single
2138 * q_vector!!!
021230d4 2139 **/
9a799d71
AK		 2140static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2141{
021230d4 2142 struct ixgbe_q_vector *q_vector =
e8e9f696 2143 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2144 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 2145 struct ixgbe_ring *rx_ring = NULL;
9a799d71 2146 int work_done = 0;
021230d4 2147 long r_idx;
9a799d71 2148
5dd2d332 2149#ifdef CONFIG_IXGBE_DCA
bd0362dd 2150 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2151 ixgbe_update_dca(q_vector);
bd0362dd 2152#endif
9a799d71 2153
33cf09c9
AD		 2154 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2155 rx_ring = adapter->rx_ring[r_idx];
2156
78b6f4ce 2157 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 2158
021230d4
AV		 2159 /* If all Rx work done, exit the polling mode */
2160 if (work_done < budget) {
288379f0 2161 napi_complete(napi);
f7554a2b 2162 if (adapter->rx_itr_setting & 1)
f494e8fa 2163 ixgbe_set_itr_msix(q_vector);
9a799d71 2164 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2165 ixgbe_irq_enable_queues(adapter,
e8e9f696 2166 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 2167 }
2168
2169 return work_done;
2170}
2171
f0848276 2172/**
91281fd3 2173 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 2174 * @napi: napi struct with our devices info in it
2175 * @budget: amount of work driver is allowed to do this pass, in packets
2176 *
2177 * This function will clean more than one rx queue associated with a
2178 * q_vector.
2179 **/
91281fd3 2180static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 2181{
2182 struct ixgbe_q_vector *q_vector =
e8e9f696 2183 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 2184 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 2185 struct ixgbe_ring *ring = NULL;
f0848276
JB		 2186 int work_done = 0, i;
2187 long r_idx;
91281fd3
AD		 2188 bool tx_clean_complete = true;
2189
33cf09c9
AD		 2190#ifdef CONFIG_IXGBE_DCA
2191 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2192 ixgbe_update_dca(q_vector);
2193#endif
2194
91281fd3
AD		 2195 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2196 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2197 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2198 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2199 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2200 r_idx + 1);
91281fd3 2201 }
f0848276
JB		 2202
2203 /* attempt to distribute budget to each queue fairly, but don't allow
2204 * the budget to go below 1 because we'll exit polling */
2205 budget /= (q_vector->rxr_count ?: 1);
2206 budget = max(budget, 1);
2207 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2208 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2209 ring = adapter->rx_ring[r_idx];
91281fd3 2210 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 2211 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2212 r_idx + 1);
f0848276
JB		 2213 }
2214
2215 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 2216 ring = adapter->rx_ring[r_idx];
f0848276 2217 /* If all Rx work done, exit the polling mode */
7f821875 2218 if (work_done < budget) {
288379f0 2219 napi_complete(napi);
f7554a2b 2220 if (adapter->rx_itr_setting & 1)
f0848276
JB		 2221 ixgbe_set_itr_msix(q_vector);
2222 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2223 ixgbe_irq_enable_queues(adapter,
e8e9f696 2224 ((u64)1 << q_vector->v_idx));
f0848276
JB		 2225 return 0;
2226 }
2227
2228 return work_done;
2229}
91281fd3
AD		 2230
2231/**
2232 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2233 * @napi: napi struct with our devices info in it
2234 * @budget: amount of work driver is allowed to do this pass, in packets
2235 *
2236 * This function is optimized for cleaning one queue only on a single
2237 * q_vector!!!
2238 **/
2239static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2240{
2241 struct ixgbe_q_vector *q_vector =
e8e9f696 2242 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2243 struct ixgbe_adapter *adapter = q_vector->adapter;
2244 struct ixgbe_ring *tx_ring = NULL;
2245 int work_done = 0;
2246 long r_idx;
2247
91281fd3
AD		 2248#ifdef CONFIG_IXGBE_DCA
2249 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2250 ixgbe_update_dca(q_vector);
91281fd3
AD		 2251#endif
2252
33cf09c9
AD		 2253 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2254 tx_ring = adapter->tx_ring[r_idx];
2255
91281fd3
AD		 2256 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2257 work_done = budget;
2258
f7554a2b 2259 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2260 if (work_done < budget) {
2261 napi_complete(napi);
f7554a2b 2262 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2263 ixgbe_set_itr_msix(q_vector);
2264 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2265 ixgbe_irq_enable_queues(adapter,
2266 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2267 }
2268
2269 return work_done;
2270}
2271
021230d4 2272static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2273 int r_idx)
021230d4 2274{
7a921c93 2275 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2276 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93
AD		 2277
2278 set_bit(r_idx, q_vector->rxr_idx);
2279 q_vector->rxr_count++;
2274543f 2280 rx_ring->q_vector = q_vector;
021230d4
AV		 2281}
2282
2283static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2284 int t_idx)
021230d4 2285{
7a921c93 2286 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2287 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93
AD		 2288
2289 set_bit(t_idx, q_vector->txr_idx);
2290 q_vector->txr_count++;
2274543f 2291 tx_ring->q_vector = q_vector;
021230d4
AV		 2292}
2293
9a799d71 2294/**
021230d4
AV		 2295 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2296 * @adapter: board private structure to initialize
9a799d71 2297 *
021230d4
AV		 2298 * This function maps descriptor rings to the queue-specific vectors
2299 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2300 * one vector per ring/queue, but on a constrained vector budget, we
2301 * group the rings as "efficiently" as possible. You would add new
2302 * mapping configurations in here.
9a799d71 2303 **/
d0759ebb 2304static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2305{
d0759ebb 2306 int q_vectors;
021230d4
AV		 2307 int v_start = 0;
2308 int rxr_idx = 0, txr_idx = 0;
2309 int rxr_remaining = adapter->num_rx_queues;
2310 int txr_remaining = adapter->num_tx_queues;
2311 int i, j;
2312 int rqpv, tqpv;
2313 int err = 0;
2314
2315 /* No mapping required if MSI-X is disabled. */
2316 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2317 goto out;
9a799d71 2318
d0759ebb
AD		 2319 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2320
021230d4
AV		 2321 /*
2322 * The ideal configuration...
2323 * We have enough vectors to map one per queue.
2324 */
d0759ebb 2325 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
021230d4
AV		 2326 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2327 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2328
021230d4
AV		 2329 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2330 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2331
9a799d71 2332 goto out;
021230d4 2333 }
9a799d71 2334
021230d4
AV		 2335 /*
2336 * If we don't have enough vectors for a 1-to-1
2337 * mapping, we'll have to group them so there are
2338 * multiple queues per vector.
2339 */
2340 /* Re-adjusting *qpv takes care of the remainder. */
d0759ebb
AD		 2341 for (i = v_start; i < q_vectors; i++) {
2342 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
021230d4
AV		 2343 for (j = 0; j < rqpv; j++) {
2344 map_vector_to_rxq(adapter, i, rxr_idx);
2345 rxr_idx++;
2346 rxr_remaining--;
2347 }
d0759ebb 2348 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
021230d4
AV		 2349 for (j = 0; j < tqpv; j++) {
2350 map_vector_to_txq(adapter, i, txr_idx);
2351 txr_idx++;
2352 txr_remaining--;
9a799d71 2353 }
9a799d71 2354 }
021230d4
AV		 2355out:
2356 return err;
2357}
2358
2359/**
2360 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2361 * @adapter: board private structure
2362 *
2363 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2364 * interrupts from the kernel.
2365 **/
2366static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2367{
2368 struct net_device *netdev = adapter->netdev;
2369 irqreturn_t (*handler)(int, void *);
2370 int i, vector, q_vectors, err;
e8e9f696 2371 int ri = 0, ti = 0;
021230d4
AV		 2372
2373 /* Decrement for Other and TCP Timer vectors */
2374 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2375
d0759ebb 2376 err = ixgbe_map_rings_to_vectors(adapter);
021230d4 2377 if (err)
d0759ebb 2378 return err;
021230d4 2379
d0759ebb
AD		 2380#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2381 ? &ixgbe_msix_clean_many : \
2382 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2383 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2384 NULL)
021230d4 2385 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb
AD		 2386 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2387 handler = SET_HANDLER(q_vector);
cb13fc20 2388
e8e9f696 2389 if (handler == &ixgbe_msix_clean_rx) {
9fe93afd
DS		 2390 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2391 "%s-%s-%d", netdev->name, "rx", ri++);
e8e9f696 2392 } else if (handler == &ixgbe_msix_clean_tx) {
9fe93afd
DS		 2393 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2394 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb 2395 } else if (handler == &ixgbe_msix_clean_many) {
9fe93afd
DS		 2396 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2397 "%s-%s-%d", netdev->name, "TxRx", ri++);
32aa77a4 2398 ti++;
d0759ebb
AD		 2399 } else {
2400 /* skip this unused q_vector */
2401 continue;
32aa77a4 2402 }
021230d4 2403 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb
AD		 2404 handler, 0, q_vector->name,
2405 q_vector);
9a799d71 2406 if (err) {
396e799c 2407 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2408 "Error: %d\n", err);
021230d4 2409 goto free_queue_irqs;
9a799d71 2410 }
9a799d71
AK		 2411 }
2412
d0759ebb 2413 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
021230d4 2414 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb 2415 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
9a799d71 2416 if (err) {
396e799c 2417 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2418 goto free_queue_irqs;
9a799d71
AK		 2419 }
2420
9a799d71
AK		 2421 return 0;
2422
021230d4
AV		 2423free_queue_irqs:
2424 for (i = vector - 1; i >= 0; i--)
2425 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2426 adapter->q_vector[i]);
021230d4
AV		 2427 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2428 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2429 kfree(adapter->msix_entries);
2430 adapter->msix_entries = NULL;
9a799d71
AK		 2431 return err;
2432}
2433
f494e8fa
AV		 2434static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2435{
7a921c93 2436 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
4a0b9ca0
PW		 2437 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2438 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
125601bf
AD		 2439 u32 new_itr = q_vector->eitr;
2440 u8 current_itr;
f494e8fa 2441
30efa5a3 2442 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2443 q_vector->tx_itr,
2444 tx_ring->total_packets,
2445 tx_ring->total_bytes);
30efa5a3 2446 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2447 q_vector->rx_itr,
2448 rx_ring->total_packets,
2449 rx_ring->total_bytes);
f494e8fa 2450
30efa5a3 2451 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2452
2453 switch (current_itr) {
2454 /* counts and packets in update_itr are dependent on these numbers */
2455 case lowest_latency:
2456 new_itr = 100000;
2457 break;
2458 case low_latency:
2459 new_itr = 20000; /* aka hwitr = ~200 */
2460 break;
2461 case bulk_latency:
2462 new_itr = 8000;
2463 break;
2464 default:
2465 break;
2466 }
2467
2468 if (new_itr != q_vector->eitr) {
fe49f04a 2469 /* do an exponential smoothing */
125601bf 2470 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935 2471
125601bf 2472 /* save the algorithm value here */
509ee935 2473 q_vector->eitr = new_itr;
fe49f04a
AD		 2474
2475 ixgbe_write_eitr(q_vector);
f494e8fa 2476 }
f494e8fa
AV		 2477}
2478
79aefa45
AD		 2479/**
2480 * ixgbe_irq_enable - Enable default interrupt generation settings
2481 * @adapter: board private structure
2482 **/
6af3b9eb
ET		 2483static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2484 bool flush)
79aefa45
AD		 2485{
2486 u32 mask;
835462fc
NS		 2487
2488 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2489 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2490 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2491 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2492 mask |= IXGBE_EIMS_GPI_SDP1;
bd508178
AD		 2493 switch (adapter->hw.mac.type) {
2494 case ixgbe_mac_82599EB:
b93a2226 2495 case ixgbe_mac_X540:
2a41ff81 2496 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2497 mask |= IXGBE_EIMS_GPI_SDP1;
2498 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2499 if (adapter->num_vfs)
2500 mask |= IXGBE_EIMS_MAILBOX;
bd508178
AD		 2501 break;
2502 default:
2503 break;
e8e26350 2504 }
c4cf55e5
PWJ		 2505 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2506 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2507 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2508
79aefa45 2509 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2510 if (queues)
2511 ixgbe_irq_enable_queues(adapter, ~0);
2512 if (flush)
2513 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2514
2515 if (adapter->num_vfs > 32) {
2516 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2517 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2518 }
79aefa45 2519}
021230d4 2520
9a799d71 2521/**
021230d4 2522 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2523 * @irq: interrupt number
2524 * @data: pointer to a network interface device structure
9a799d71
AK		 2525 **/
2526static irqreturn_t ixgbe_intr(int irq, void *data)
2527{
2528 struct net_device *netdev = data;
2529 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2530 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2531 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2532 u32 eicr;
2533
54037505 2534 /*
6af3b9eb 2535 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2536 * before the read of EICR.
2537 */
2538 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2539
021230d4
AV		 2540 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2541 * therefore no explict interrupt disable is necessary */
2542 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2543 if (!eicr) {
6af3b9eb
ET		 2544 /*
2545 * shared interrupt alert!
f47cf66e 2546 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2547 * have disabled interrupts due to EIAM
2548 * finish the workaround of silicon errata on 82598. Unmask
2549 * the interrupt that we masked before the EICR read.
2550 */
2551 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2552 ixgbe_irq_enable(adapter, true, true);
9a799d71 2553 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2554 }
9a799d71 2555
cf8280ee
JB		 2556 if (eicr & IXGBE_EICR_LSC)
2557 ixgbe_check_lsc(adapter);
021230d4 2558
bd508178
AD		 2559 switch (hw->mac.type) {
2560 case ixgbe_mac_82599EB:
e8e26350 2561 ixgbe_check_sfp_event(adapter, eicr);
bd508178
AD		 2562 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2563 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2564 adapter->interrupt_event = eicr;
2565 schedule_work(&adapter->check_overtemp_task);
2566 }
2567 break;
2568 default:
2569 break;
2570 }
e8e26350 2571
0befdb3e
JB		 2572 ixgbe_check_fan_failure(adapter, eicr);
2573
7a921c93 2574 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2575 adapter->tx_ring[0]->total_packets = 0;
2576 adapter->tx_ring[0]->total_bytes = 0;
2577 adapter->rx_ring[0]->total_packets = 0;
2578 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2579 /* would disable interrupts here but EIAM disabled it */
7a921c93 2580 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2581 }
2582
6af3b9eb
ET		 2583 /*
2584 * re-enable link(maybe) and non-queue interrupts, no flush.
2585 * ixgbe_poll will re-enable the queue interrupts
2586 */
2587
2588 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2589 ixgbe_irq_enable(adapter, false, false);
2590
9a799d71
AK		 2591 return IRQ_HANDLED;
2592}
2593
021230d4
AV		 2594static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2595{
2596 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2597
2598 for (i = 0; i < q_vectors; i++) {
7a921c93 2599 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2600 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2601 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2602 q_vector->rxr_count = 0;
2603 q_vector->txr_count = 0;
2604 }
2605}
2606
9a799d71
AK		 2607/**
2608 * ixgbe_request_irq - initialize interrupts
2609 * @adapter: board private structure
2610 *
2611 * Attempts to configure interrupts using the best available
2612 * capabilities of the hardware and kernel.
2613 **/
021230d4 2614static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2615{
2616 struct net_device *netdev = adapter->netdev;
021230d4 2617 int err;
9a799d71 2618
021230d4
AV		 2619 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2620 err = ixgbe_request_msix_irqs(adapter);
2621 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2622 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2623 netdev->name, netdev);
021230d4 2624 } else {
a0607fd3 2625 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2626 netdev->name, netdev);
9a799d71
AK		 2627 }
2628
9a799d71 2629 if (err)
396e799c 2630 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2631
9a799d71
AK		 2632 return err;
2633}
2634
2635static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2636{
2637 struct net_device *netdev = adapter->netdev;
2638
2639 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2640 int i, q_vectors;
9a799d71 2641
021230d4
AV		 2642 q_vectors = adapter->num_msix_vectors;
2643
2644 i = q_vectors - 1;
9a799d71 2645 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2646
021230d4
AV		 2647 i--;
2648 for (; i >= 0; i--) {
894ff7cf
AD		 2649 /* free only the irqs that were actually requested */
2650 if (!adapter->q_vector[i]->rxr_count &&
2651 !adapter->q_vector[i]->txr_count)
2652 continue;
2653
021230d4 2654 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2655 adapter->q_vector[i]);
021230d4
AV		 2656 }
2657
2658 ixgbe_reset_q_vectors(adapter);
2659 } else {
2660 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2661 }
2662}
2663
22d5a71b
JB		 2664/**
2665 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2666 * @adapter: board private structure
2667 **/
2668static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2669{
bd508178
AD		 2670 switch (adapter->hw.mac.type) {
2671 case ixgbe_mac_82598EB:
835462fc 2672 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2673 break;
2674 case ixgbe_mac_82599EB:
b93a2226 2675 case ixgbe_mac_X540:
835462fc
NS		 2676 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2677 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2678 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2679 if (adapter->num_vfs > 32)
2680 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
bd508178
AD		 2681 break;
2682 default:
2683 break;
22d5a71b
JB		 2684 }
2685 IXGBE_WRITE_FLUSH(&adapter->hw);
2686 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2687 int i;
2688 for (i = 0; i < adapter->num_msix_vectors; i++)
2689 synchronize_irq(adapter->msix_entries[i].vector);
2690 } else {
2691 synchronize_irq(adapter->pdev->irq);
2692 }
2693}
2694
9a799d71
AK		 2695/**
2696 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2697 *
2698 **/
2699static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2700{
9a799d71
AK		 2701 struct ixgbe_hw *hw = &adapter->hw;
2702
021230d4 2703 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2704 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2705
e8e26350
PW		 2706 ixgbe_set_ivar(adapter, 0, 0, 0);
2707 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2708
2709 map_vector_to_rxq(adapter, 0, 0);
2710 map_vector_to_txq(adapter, 0, 0);
2711
396e799c 2712 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2713}
2714
43e69bf0
AD		 2715/**
2716 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2717 * @adapter: board private structure
2718 * @ring: structure containing ring specific data
2719 *
2720 * Configure the Tx descriptor ring after a reset.
2721 **/
84418e3b
AD		 2722void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2723 struct ixgbe_ring *ring)
43e69bf0
AD		 2724{
2725 struct ixgbe_hw *hw = &adapter->hw;
2726 u64 tdba = ring->dma;
2f1860b8
AD		 2727 int wait_loop = 10;
2728 u32 txdctl;
bf29ee6c 2729 u8 reg_idx = ring->reg_idx;
43e69bf0 2730
2f1860b8
AD		 2731 /* disable queue to avoid issues while updating state */
2732 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2733 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2734 txdctl & ~IXGBE_TXDCTL_ENABLE);
2735 IXGBE_WRITE_FLUSH(hw);
2736
43e69bf0 2737 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2738 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2739 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2740 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2741 ring->count * sizeof(union ixgbe_adv_tx_desc));
2742 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2743 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2744 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2745
2f1860b8
AD		 2746 /* configure fetching thresholds */
2747 if (adapter->rx_itr_setting == 0) {
2748 /* cannot set wthresh when itr==0 */
2749 txdctl &= ~0x007F0000;
2750 } else {
2751 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2752 txdctl |= (8 << 16);
2753 }
2754 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2755 /* PThresh workaround for Tx hang with DFP enabled. */
2756 txdctl |= 32;
2757 }
2758
2759 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2760 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2761 adapter->atr_sample_rate) {
2762 ring->atr_sample_rate = adapter->atr_sample_rate;
2763 ring->atr_count = 0;
2764 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2765 } else {
2766 ring->atr_sample_rate = 0;
2767 }
2f1860b8 2768
c84d324c
JF		 2769 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2770
2f1860b8
AD		 2771 /* enable queue */
2772 txdctl |= IXGBE_TXDCTL_ENABLE;
2773 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2774
2775 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2776 if (hw->mac.type == ixgbe_mac_82598EB &&
2777 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2778 return;
2779
2780 /* poll to verify queue is enabled */
2781 do {
032b4325 2782 usleep_range(1000, 2000);
2f1860b8
AD		 2783 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2784 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2785 if (!wait_loop)
2786 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2787}
2788
120ff942
AD		 2789static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2790{
2791 struct ixgbe_hw *hw = &adapter->hw;
2792 u32 rttdcs;
2793 u32 mask;
2794
2795 if (hw->mac.type == ixgbe_mac_82598EB)
2796 return;
2797
2798 /* disable the arbiter while setting MTQC */
2799 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2800 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2801 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2802
2803 /* set transmit pool layout */
2804 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2805 switch (adapter->flags & mask) {
2806
2807 case (IXGBE_FLAG_SRIOV_ENABLED):
2808 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2809 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2810 break;
2811
2812 case (IXGBE_FLAG_DCB_ENABLED):
2813 /* We enable 8 traffic classes, DCB only */
2814 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2815 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2816 break;
2817
2818 default:
2819 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2820 break;
2821 }
2822
2823 /* re-enable the arbiter */
2824 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2825 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2826}
2827
9a799d71 2828/**
3a581073 2829 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2830 * @adapter: board private structure
2831 *
2832 * Configure the Tx unit of the MAC after a reset.
2833 **/
2834static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2835{
2f1860b8
AD		 2836 struct ixgbe_hw *hw = &adapter->hw;
2837 u32 dmatxctl;
43e69bf0 2838 u32 i;
9a799d71 2839
2f1860b8
AD		 2840 ixgbe_setup_mtqc(adapter);
2841
2842 if (hw->mac.type != ixgbe_mac_82598EB) {
2843 /* DMATXCTL.EN must be before Tx queues are enabled */
2844 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2845 dmatxctl |= IXGBE_DMATXCTL_TE;
2846 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2847 }
2848
9a799d71 2849 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2850 for (i = 0; i < adapter->num_tx_queues; i++)
2851 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2852}
2853
e8e26350 2854#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2855
a6616b42 2856static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2857 struct ixgbe_ring *rx_ring)
cc41ac7c 2858{
cc41ac7c 2859 u32 srrctl;
bf29ee6c 2860 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2861
bd508178
AD		 2862 switch (adapter->hw.mac.type) {
2863 case ixgbe_mac_82598EB: {
2864 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2865 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2866 reg_idx = reg_idx & mask;
cc41ac7c 2867 }
bd508178
AD		 2868 break;
2869 case ixgbe_mac_82599EB:
b93a2226 2870 case ixgbe_mac_X540:
bd508178
AD		 2871 default:
2872 break;
2873 }
2874
bf29ee6c 2875 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2876
2877 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2878 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2879 if (adapter->num_vfs)
2880 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2881
afafd5b0
AD		 2882 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2883 IXGBE_SRRCTL_BSIZEHDR_MASK;
2884
7d637bcc 2885 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2886#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2887 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2888#else
2889 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2890#endif
cc41ac7c 2891 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2892 } else {
afafd5b0
AD		 2893 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2894 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2895 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2896 }
e8e26350 2897
bf29ee6c 2898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2899}
9a799d71 2900
05abb126 2901static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2902{
05abb126
AD		 2903 struct ixgbe_hw *hw = &adapter->hw;
2904 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2905 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2906 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2907 u32 mrqc = 0, reta = 0;
2908 u32 rxcsum;
2909 int i, j;
0cefafad
JB		 2910 int mask;
2911
05abb126
AD		 2912 /* Fill out hash function seeds */
2913 for (i = 0; i < 10; i++)
2914 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2915
2916 /* Fill out redirection table */
2917 for (i = 0, j = 0; i < 128; i++, j++) {
2918 if (j == adapter->ring_feature[RING_F_RSS].indices)
2919 j = 0;
2920 /* reta = 4-byte sliding window of
2921 * 0x00..(indices-1)(indices-1)00..etc. */
2922 reta = (reta << 8) | (j * 0x11);
2923 if ((i & 3) == 3)
2924 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2925 }
0cefafad 2926
05abb126
AD		 2927 /* Disable indicating checksum in descriptor, enables RSS hash */
2928 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2929 rxcsum |= IXGBE_RXCSUM_PCSD;
2930 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2931
2932 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2933 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2934 else
2935 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2936#ifdef CONFIG_IXGBE_DCB
05abb126 2937 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2938#endif
05abb126
AD		 2939 | IXGBE_FLAG_SRIOV_ENABLED
2940 );
0cefafad
JB		 2941
2942 switch (mask) {
8187cd48
JF		 2943#ifdef CONFIG_IXGBE_DCB
2944 case (IXGBE_FLAG_DCB_ENABLED | IXGBE_FLAG_RSS_ENABLED):
2945 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2946 break;
2947 case (IXGBE_FLAG_DCB_ENABLED):
2948 mrqc = IXGBE_MRQC_RT8TCEN;
2949 break;
2950#endif /* CONFIG_IXGBE_DCB */
0cefafad
JB		 2951 case (IXGBE_FLAG_RSS_ENABLED):
2952 mrqc = IXGBE_MRQC_RSSEN;
2953 break;
1cdd1ec8
GR		 2954 case (IXGBE_FLAG_SRIOV_ENABLED):
2955 mrqc = IXGBE_MRQC_VMDQEN;
2956 break;
0cefafad
JB		 2957 default:
2958 break;
2959 }
2960
05abb126
AD		 2961 /* Perform hash on these packet types */
2962 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2963 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2964 | IXGBE_MRQC_RSS_FIELD_IPV6
2965 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2966
2967 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2968}
2969
b93a2226
DS		 2970/**
2971 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2972 * @adapter: address of board private structure
2973 * @ring: structure containing ring specific data
2974 **/
2975void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2976 struct ixgbe_ring *ring)
2977{
2978 struct ixgbe_hw *hw = &adapter->hw;
2979 u32 rscctrl;
2980 u8 reg_idx = ring->reg_idx;
2981
2982 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2983 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2984 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2985}
2986
bb5a9ad2
NS		 2987/**
2988 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2989 * @adapter: address of board private structure
2990 * @index: index of ring to set
bb5a9ad2 2991 **/
b93a2226 2992void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2993 struct ixgbe_ring *ring)
bb5a9ad2 2994{
bb5a9ad2 2995 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2996 u32 rscctrl;
edd2ea55 2997 int rx_buf_len;
bf29ee6c 2998 u8 reg_idx = ring->reg_idx;
7367096a 2999
7d637bcc 3000 if (!ring_is_rsc_enabled(ring))
7367096a 3001 return;
bb5a9ad2 3002
7367096a
AD		 3003 rx_buf_len = ring->rx_buf_len;
3004 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3005 rscctrl |= IXGBE_RSCCTL_RSCEN;
3006 /*
3007 * we must limit the number of descriptors so that the
3008 * total size of max desc * buf_len is not greater
3009 * than 65535
3010 */
7d637bcc 3011 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 3012#if (MAX_SKB_FRAGS > 16)
3013 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3014#elif (MAX_SKB_FRAGS > 8)
3015 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
3016#elif (MAX_SKB_FRAGS > 4)
3017 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
3018#else
3019 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
3020#endif
3021 } else {
3022 if (rx_buf_len < IXGBE_RXBUFFER_4096)
3023 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3024 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
3025 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
3026 else
3027 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
3028 }
7367096a 3029 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3030}
3031
9e10e045
AD		 3032/**
3033 * ixgbe_set_uta - Set unicast filter table address
3034 * @adapter: board private structure
3035 *
3036 * The unicast table address is a register array of 32-bit registers.
3037 * The table is meant to be used in a way similar to how the MTA is used
3038 * however due to certain limitations in the hardware it is necessary to
3039 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
3040 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
3041 **/
3042static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
3043{
3044 struct ixgbe_hw *hw = &adapter->hw;
3045 int i;
3046
3047 /* The UTA table only exists on 82599 hardware and newer */
3048 if (hw->mac.type < ixgbe_mac_82599EB)
3049 return;
3050
3051 /* we only need to do this if VMDq is enabled */
3052 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3053 return;
3054
3055 for (i = 0; i < 128; i++)
3056 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3057}
3058
3059#define IXGBE_MAX_RX_DESC_POLL 10
3060static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3061 struct ixgbe_ring *ring)
3062{
3063 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3064 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3065 u32 rxdctl;
bf29ee6c 3066 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3067
3068 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3069 if (hw->mac.type == ixgbe_mac_82598EB &&
3070 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3071 return;
3072
3073 do {
032b4325 3074 usleep_range(1000, 2000);
9e10e045
AD		 3075 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3076 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3077
3078 if (!wait_loop) {
3079 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3080 "the polling period\n", reg_idx);
3081 }
3082}
3083
2d39d576
YZ		 3084void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3085 struct ixgbe_ring *ring)
3086{
3087 struct ixgbe_hw *hw = &adapter->hw;
3088 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3089 u32 rxdctl;
3090 u8 reg_idx = ring->reg_idx;
3091
3092 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3093 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3094
3095 /* write value back with RXDCTL.ENABLE bit cleared */
3096 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3097
3098 if (hw->mac.type == ixgbe_mac_82598EB &&
3099 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3100 return;
3101
3102 /* the hardware may take up to 100us to really disable the rx queue */
3103 do {
3104 udelay(10);
3105 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3106 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3107
3108 if (!wait_loop) {
3109 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3110 "the polling period\n", reg_idx);
3111 }
3112}
3113
84418e3b
AD		 3114void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3115 struct ixgbe_ring *ring)
acd37177
AD		 3116{
3117 struct ixgbe_hw *hw = &adapter->hw;
3118 u64 rdba = ring->dma;
9e10e045 3119 u32 rxdctl;
bf29ee6c 3120 u8 reg_idx = ring->reg_idx;
acd37177 3121
9e10e045
AD		 3122 /* disable queue to avoid issues while updating state */
3123 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3124 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3125
acd37177
AD		 3126 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3127 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3128 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3129 ring->count * sizeof(union ixgbe_adv_rx_desc));
3130 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3131 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3132 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3133
3134 ixgbe_configure_srrctl(adapter, ring);
3135 ixgbe_configure_rscctl(adapter, ring);
3136
e9f98072
GR		 3137 /* If operating in IOV mode set RLPML for X540 */
3138 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3139 hw->mac.type == ixgbe_mac_X540) {
3140 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3141 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3142 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3143 }
3144
9e10e045
AD		 3145 if (hw->mac.type == ixgbe_mac_82598EB) {
3146 /*
3147 * enable cache line friendly hardware writes:
3148 * PTHRESH=32 descriptors (half the internal cache),
3149 * this also removes ugly rx_no_buffer_count increment
3150 * HTHRESH=4 descriptors (to minimize latency on fetch)
3151 * WTHRESH=8 burst writeback up to two cache lines
3152 */
3153 rxdctl &= ~0x3FFFFF;
3154 rxdctl |= 0x080420;
3155 }
3156
3157 /* enable receive descriptor ring */
3158 rxdctl |= IXGBE_RXDCTL_ENABLE;
3159 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3160
3161 ixgbe_rx_desc_queue_enable(adapter, ring);
fc77dc3c 3162 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 3163}
3164
48654521
AD		 3165static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3166{
3167 struct ixgbe_hw *hw = &adapter->hw;
3168 int p;
3169
3170 /* PSRTYPE must be initialized in non 82598 adapters */
3171 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3172 IXGBE_PSRTYPE_UDPHDR |
3173 IXGBE_PSRTYPE_IPV4HDR |
48654521 3174 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3175 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3176
3177 if (hw->mac.type == ixgbe_mac_82598EB)
3178 return;
3179
3180 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3181 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3182
3183 for (p = 0; p < adapter->num_rx_pools; p++)
3184 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3185 psrtype);
3186}
3187
f5b4a52e
AD		 3188static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3189{
3190 struct ixgbe_hw *hw = &adapter->hw;
3191 u32 gcr_ext;
3192 u32 vt_reg_bits;
3193 u32 reg_offset, vf_shift;
3194 u32 vmdctl;
3195
3196 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3197 return;
3198
3199 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3200 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3201 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3202 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3203
3204 vf_shift = adapter->num_vfs % 32;
3205 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3206
3207 /* Enable only the PF's pool for Tx/Rx */
3208 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3209 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3210 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3211 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3212 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3213
3214 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3215 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3216
3217 /*
3218 * Set up VF register offsets for selected VT Mode,
3219 * i.e. 32 or 64 VFs for SR-IOV
3220 */
3221 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3222 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3223 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3224 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3225
3226 /* enable Tx loopback for VF/PF communication */
3227 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 3228 /* Enable MAC Anti-Spoofing */
a1cbb15c
GR		 3229 hw->mac.ops.set_mac_anti_spoofing(hw,
3230 (adapter->antispoofing_enabled =
3231 (adapter->num_vfs != 0)),
a985b6c3 3232 adapter->num_vfs);
f5b4a52e
AD		 3233}
3234
477de6ed 3235static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3236{
9a799d71
AK		 3237 struct ixgbe_hw *hw = &adapter->hw;
3238 struct net_device *netdev = adapter->netdev;
3239 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3240 int rx_buf_len;
477de6ed
AD		 3241 struct ixgbe_ring *rx_ring;
3242 int i;
3243 u32 mhadd, hlreg0;
48654521 3244
9a799d71 3245 /* Decide whether to use packet split mode or not */
a124339a
DS		 3246 /* On by default */
3247 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3248
1cdd1ec8 3249 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 3250 if (adapter->num_vfs)
3251 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3252
3253 /* Disable packet split due to 82599 erratum #45 */
3254 if (hw->mac.type == ixgbe_mac_82599EB)
3255 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 3256
3257 /* Set the RX buffer length according to the mode */
3258 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 3259 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 3260 } else {
0c19d6af 3261 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 3262 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 3263 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 3264 else
477de6ed 3265 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 3266 }
3267
63f39bd1 3268#ifdef IXGBE_FCOE
477de6ed
AD		 3269 /* adjust max frame to be able to do baby jumbo for FCoE */
3270 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3271 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3272 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3273
477de6ed
AD		 3274#endif /* IXGBE_FCOE */
3275 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3276 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3277 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3278 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3279
3280 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3281 }
3282
3283 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3284 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3285 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3286 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3287
0cefafad
JB		 3288 /*
3289 * Setup the HW Rx Head and Tail Descriptor Pointers and
3290 * the Base and Length of the Rx Descriptor Ring
3291 */
9a799d71 3292 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3293 rx_ring = adapter->rx_ring[i];
a6616b42 3294 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3295
6e455b89 3296 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3297 set_ring_ps_enabled(rx_ring);
3298 else
3299 clear_ring_ps_enabled(rx_ring);
3300
3301 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3302 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3303 else
7d637bcc 3304 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3305
63f39bd1 3306#ifdef IXGBE_FCOE
e8e9f696 3307 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3308 struct ixgbe_ring_feature *f;
3309 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3310 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3311 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3312 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3313 rx_ring->rx_buf_len =
e8e9f696 3314 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3315 } else if (!ring_is_rsc_enabled(rx_ring) &&
3316 !ring_is_ps_enabled(rx_ring)) {
3317 rx_ring->rx_buf_len =
3318 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3319 }
63f39bd1 3320 }
63f39bd1 3321#endif /* IXGBE_FCOE */
477de6ed 3322 }
477de6ed
AD		 3323}
3324
7367096a
AD		 3325static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3326{
3327 struct ixgbe_hw *hw = &adapter->hw;
3328 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3329
3330 switch (hw->mac.type) {
3331 case ixgbe_mac_82598EB:
3332 /*
3333 * For VMDq support of different descriptor types or
3334 * buffer sizes through the use of multiple SRRCTL
3335 * registers, RDRXCTL.MVMEN must be set to 1
3336 *
3337 * also, the manual doesn't mention it clearly but DCA hints
3338 * will only use queue 0's tags unless this bit is set. Side
3339 * effects of setting this bit are only that SRRCTL must be
3340 * fully programmed [0..15]
3341 */
3342 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3343 break;
3344 case ixgbe_mac_82599EB:
b93a2226 3345 case ixgbe_mac_X540:
7367096a
AD		 3346 /* Disable RSC for ACK packets */
3347 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3348 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3349 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3350 /* hardware requires some bits to be set by default */
3351 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3352 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3353 break;
3354 default:
3355 /* We should do nothing since we don't know this hardware */
3356 return;
3357 }
3358
3359 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3360}
3361
477de6ed
AD		 3362/**
3363 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3364 * @adapter: board private structure
3365 *
3366 * Configure the Rx unit of the MAC after a reset.
3367 **/
3368static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3369{
3370 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3371 int i;
3372 u32 rxctrl;
477de6ed
AD		 3373
3374 /* disable receives while setting up the descriptors */
3375 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3376 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3377
3378 ixgbe_setup_psrtype(adapter);
7367096a 3379 ixgbe_setup_rdrxctl(adapter);
477de6ed 3380
9e10e045 3381 /* Program registers for the distribution of queues */
f5b4a52e 3382 ixgbe_setup_mrqc(adapter);
f5b4a52e 3383
9e10e045
AD		 3384 ixgbe_set_uta(adapter);
3385
477de6ed
AD		 3386 /* set_rx_buffer_len must be called before ring initialization */
3387 ixgbe_set_rx_buffer_len(adapter);
3388
3389 /*
3390 * Setup the HW Rx Head and Tail Descriptor Pointers and
3391 * the Base and Length of the Rx Descriptor Ring
3392 */
9e10e045
AD		 3393 for (i = 0; i < adapter->num_rx_queues; i++)
3394 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3395
9e10e045
AD		 3396 /* disable drop enable for 82598 parts */
3397 if (hw->mac.type == ixgbe_mac_82598EB)
3398 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3399
3400 /* enable all receives */
3401 rxctrl |= IXGBE_RXCTRL_RXEN;
3402 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3403}
3404
068c89b0
DS		 3405static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3406{
3407 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3408 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3409 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3410
3411 /* add VID to filter table */
1ada1b1b 3412 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3413 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3414}
3415
3416static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3417{
3418 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3419 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3420 int pool_ndx = adapter->num_vfs;
068c89b0 3421
068c89b0 3422 /* remove VID from filter table */
1ada1b1b 3423 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3424 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3425}
3426
5f6c0181
JB		 3427/**
3428 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3429 * @adapter: driver data
3430 */
3431static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3432{
3433 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3434 u32 vlnctrl;
3435
3436 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3437 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3438 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3439}
3440
3441/**
3442 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3443 * @adapter: driver data
3444 */
3445static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3446{
3447 struct ixgbe_hw *hw = &adapter->hw;
3448 u32 vlnctrl;
3449
3450 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3451 vlnctrl |= IXGBE_VLNCTRL_VFE;
3452 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3453 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3454}
3455
3456/**
3457 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3458 * @adapter: driver data
3459 */
3460static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3461{
3462 struct ixgbe_hw *hw = &adapter->hw;
3463 u32 vlnctrl;
5f6c0181
JB		 3464 int i, j;
3465
3466 switch (hw->mac.type) {
3467 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3468 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3469 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3470 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3471 break;
3472 case ixgbe_mac_82599EB:
b93a2226 3473 case ixgbe_mac_X540:
5f6c0181
JB		 3474 for (i = 0; i < adapter->num_rx_queues; i++) {
3475 j = adapter->rx_ring[i]->reg_idx;
3476 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3477 vlnctrl &= ~IXGBE_RXDCTL_VME;
3478 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3479 }
3480 break;
3481 default:
3482 break;
3483 }
3484}
3485
3486/**
f62bbb5e 3487 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3488 * @adapter: driver data
3489 */
f62bbb5e 3490static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3491{
3492 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3493 u32 vlnctrl;
5f6c0181
JB		 3494 int i, j;
3495
3496 switch (hw->mac.type) {
3497 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3498 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3499 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3500 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3501 break;
3502 case ixgbe_mac_82599EB:
b93a2226 3503 case ixgbe_mac_X540:
5f6c0181
JB		 3504 for (i = 0; i < adapter->num_rx_queues; i++) {
3505 j = adapter->rx_ring[i]->reg_idx;
3506 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3507 vlnctrl |= IXGBE_RXDCTL_VME;
3508 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3509 }
3510 break;
3511 default:
3512 break;
3513 }
3514}
3515
9a799d71
AK		 3516static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3517{
f62bbb5e 3518 u16 vid;
9a799d71 3519
f62bbb5e
JG		 3520 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3521
3522 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3523 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3524}
3525
2850062a
AD		 3526/**
3527 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3528 * @netdev: network interface device structure
3529 *
3530 * Writes unicast address list to the RAR table.
3531 * Returns: -ENOMEM on failure/insufficient address space
3532 * 0 on no addresses written
3533 * X on writing X addresses to the RAR table
3534 **/
3535static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3536{
3537 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3538 struct ixgbe_hw *hw = &adapter->hw;
3539 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3540 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3541 int count = 0;
3542
3543 /* return ENOMEM indicating insufficient memory for addresses */
3544 if (netdev_uc_count(netdev) > rar_entries)
3545 return -ENOMEM;
3546
3547 if (!netdev_uc_empty(netdev) && rar_entries) {
3548 struct netdev_hw_addr *ha;
3549 /* return error if we do not support writing to RAR table */
3550 if (!hw->mac.ops.set_rar)
3551 return -ENOMEM;
3552
3553 netdev_for_each_uc_addr(ha, netdev) {
3554 if (!rar_entries)
3555 break;
3556 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3557 vfn, IXGBE_RAH_AV);
3558 count++;
3559 }
3560 }
3561 /* write the addresses in reverse order to avoid write combining */
3562 for (; rar_entries > 0 ; rar_entries--)
3563 hw->mac.ops.clear_rar(hw, rar_entries);
3564
3565 return count;
3566}
3567
9a799d71 3568/**
2c5645cf 3569 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3570 * @netdev: network interface device structure
3571 *
2c5645cf
CL		 3572 * The set_rx_method entry point is called whenever the unicast/multicast
3573 * address list or the network interface flags are updated. This routine is
3574 * responsible for configuring the hardware for proper unicast, multicast and
3575 * promiscuous mode.
9a799d71 3576 **/
7f870475 3577void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3578{
3579 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3580 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3581 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3582 int count;
9a799d71
AK		 3583
3584 /* Check for Promiscuous and All Multicast modes */
3585
3586 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3587
f5dc442b
AD		 3588 /* set all bits that we expect to always be set */
3589 fctrl |= IXGBE_FCTRL_BAM;
3590 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3591 fctrl |= IXGBE_FCTRL_PMCF;
3592
2850062a
AD		 3593 /* clear the bits we are changing the status of */
3594 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3595
9a799d71 3596 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3597 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3598 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3599 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3600 /* don't hardware filter vlans in promisc mode */
3601 ixgbe_vlan_filter_disable(adapter);
9a799d71 3602 } else {
746b9f02
PM		 3603 if (netdev->flags & IFF_ALLMULTI) {
3604 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3605 vmolr |= IXGBE_VMOLR_MPE;
3606 } else {
3607 /*
3608 * Write addresses to the MTA, if the attempt fails
25985edc 3609 * then we should just turn on promiscuous mode so
2850062a
AD		 3610 * that we can at least receive multicast traffic
3611 */
3612 hw->mac.ops.update_mc_addr_list(hw, netdev);
3613 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3614 }
5f6c0181 3615 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3616 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3617 /*
3618 * Write addresses to available RAR registers, if there is not
3619 * sufficient space to store all the addresses then enable
25985edc 3620 * unicast promiscuous mode
2850062a
AD		 3621 */
3622 count = ixgbe_write_uc_addr_list(netdev);
3623 if (count < 0) {
3624 fctrl |= IXGBE_FCTRL_UPE;
3625 vmolr |= IXGBE_VMOLR_ROPE;
3626 }
9a799d71
AK		 3627 }
3628
2850062a 3629 if (adapter->num_vfs) {
1cdd1ec8 3630 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3631 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3632 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3633 IXGBE_VMOLR_ROPE);
3634 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3635 }
3636
3637 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3638
3639 if (netdev->features & NETIF_F_HW_VLAN_RX)
3640 ixgbe_vlan_strip_enable(adapter);
3641 else
3642 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3643}
3644
021230d4
AV		 3645static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3646{
3647 int q_idx;
3648 struct ixgbe_q_vector *q_vector;
3649 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3650
3651 /* legacy and MSI only use one vector */
3652 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3653 q_vectors = 1;
3654
3655 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3656 struct napi_struct *napi;
7a921c93 3657 q_vector = adapter->q_vector[q_idx];
f0848276 3658 napi = &q_vector->napi;
91281fd3
AD		 3659 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3660 if (!q_vector->rxr_count || !q_vector->txr_count) {
3661 if (q_vector->txr_count == 1)
3662 napi->poll = &ixgbe_clean_txonly;
3663 else if (q_vector->rxr_count == 1)
3664 napi->poll = &ixgbe_clean_rxonly;
3665 }
3666 }
f0848276
JB		 3667
3668 napi_enable(napi);
021230d4
AV		 3669 }
3670}
3671
3672static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3673{
3674 int q_idx;
3675 struct ixgbe_q_vector *q_vector;
3676 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3677
3678 /* legacy and MSI only use one vector */
3679 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3680 q_vectors = 1;
3681
3682 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3683 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3684 napi_disable(&q_vector->napi);
3685 }
3686}
3687
7a6b6f51 3688#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3689/*
3690 * ixgbe_configure_dcb - Configure DCB hardware
3691 * @adapter: ixgbe adapter struct
3692 *
3693 * This is called by the driver on open to configure the DCB hardware.
3694 * This is also called by the gennetlink interface when reconfiguring
3695 * the DCB state.
3696 */
3697static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3698{
3699 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3700 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3701
67ebd791
AD		 3702 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3703 if (hw->mac.type == ixgbe_mac_82598EB)
3704 netif_set_gso_max_size(adapter->netdev, 65536);
3705 return;
3706 }
3707
3708 if (hw->mac.type == ixgbe_mac_82598EB)
3709 netif_set_gso_max_size(adapter->netdev, 32768);
3710
2f90b865 3711
2f90b865 3712 /* Enable VLAN tag insert/strip */
f62bbb5e 3713 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3714
2f90b865 3715 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3716
3717 /* reconfigure the hardware */
c27931da
JF		 3718 if (adapter->dcbx_cap & (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE)) {
3719#ifdef CONFIG_FCOE
3720 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3721 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3722#endif
3723 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3724 DCB_TX_CONFIG);
3725 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3726 DCB_RX_CONFIG);
3727 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3728 } else {
3729 struct net_device *dev = adapter->netdev;
3730
3731 if (adapter->ixgbe_ieee_ets)
3732 dev->dcbnl_ops->ieee_setets(dev,
3733 adapter->ixgbe_ieee_ets);
3734 if (adapter->ixgbe_ieee_pfc)
3735 dev->dcbnl_ops->ieee_setpfc(dev,
3736 adapter->ixgbe_ieee_pfc);
3737 }
8187cd48
JF		 3738
3739 /* Enable RSS Hash per TC */
3740 if (hw->mac.type != ixgbe_mac_82598EB) {
3741 int i;
3742 u32 reg = 0;
3743
3744 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3745 u8 msb = 0;
3746 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3747
3748 while (cnt >>= 1)
3749 msb++;
3750
3751 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3752 }
3753 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3754 }
2f90b865
AD		 3755}
3756
3757#endif
9a799d71
AK		 3758static void ixgbe_configure(struct ixgbe_adapter *adapter)
3759{
3760 struct net_device *netdev = adapter->netdev;
c4cf55e5 3761 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3762 int i;
3763
7a6b6f51 3764#ifdef CONFIG_IXGBE_DCB
67ebd791 3765 ixgbe_configure_dcb(adapter);
2f90b865 3766#endif
9a799d71 3767
f62bbb5e
JG		 3768 ixgbe_set_rx_mode(netdev);
3769 ixgbe_restore_vlan(adapter);
3770
eacd73f7
YZ		 3771#ifdef IXGBE_FCOE
3772 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3773 ixgbe_configure_fcoe(adapter);
3774
3775#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3776 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3777 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3778 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3779 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3780 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3781 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3782 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3783 }
933d41f1 3784 ixgbe_configure_virtualization(adapter);
c4cf55e5 3785
9a799d71
AK		 3786 ixgbe_configure_tx(adapter);
3787 ixgbe_configure_rx(adapter);
9a799d71
AK		 3788}
3789
e8e26350
PW		 3790static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3791{
3792 switch (hw->phy.type) {
3793 case ixgbe_phy_sfp_avago:
3794 case ixgbe_phy_sfp_ftl:
3795 case ixgbe_phy_sfp_intel:
3796 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3797 case ixgbe_phy_sfp_passive_tyco:
3798 case ixgbe_phy_sfp_passive_unknown:
3799 case ixgbe_phy_sfp_active_unknown:
3800 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3801 return true;
3802 default:
3803 return false;
3804 }
3805}
3806
0ecc061d 3807/**
e8e26350
PW		 3808 * ixgbe_sfp_link_config - set up SFP+ link
3809 * @adapter: pointer to private adapter struct
3810 **/
3811static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3812{
7086400d
AD		 3813 /*
3814 * We are assuming the worst case scenerio here, and that
3815 * is that an SFP was inserted/removed after the reset
3816 * but before SFP detection was enabled. As such the best
3817 * solution is to just start searching as soon as we start
3818 */
3819 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3820 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3821
7086400d 3822 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3823}
3824
3825/**
3826 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3827 * @hw: pointer to private hardware struct
3828 *
3829 * Returns 0 on success, negative on failure
3830 **/
e8e26350 3831static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3832{
3833 u32 autoneg;
8620a103 3834 bool negotiation, link_up = false;
0ecc061d
PWJ		 3835 u32 ret = IXGBE_ERR_LINK_SETUP;
3836
3837 if (hw->mac.ops.check_link)
3838 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3839
3840 if (ret)
3841 goto link_cfg_out;
3842
0b0c2b31
ET		 3843 autoneg = hw->phy.autoneg_advertised;
3844 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3845 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3846 &negotiation);
0ecc061d
PWJ		 3847 if (ret)
3848 goto link_cfg_out;
3849
8620a103
MC		 3850 if (hw->mac.ops.setup_link)
3851 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3852link_cfg_out:
3853 return ret;
3854}
3855
a34bcfff 3856static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3857{
9a799d71 3858 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3859 u32 gpie = 0;
9a799d71 3860
9b471446 3861 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3862 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3863 IXGBE_GPIE_OCD;
3864 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3865 /*
3866 * use EIAM to auto-mask when MSI-X interrupt is asserted
3867 * this saves a register write for every interrupt
3868 */
3869 switch (hw->mac.type) {
3870 case ixgbe_mac_82598EB:
3871 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3872 break;
9b471446 3873 case ixgbe_mac_82599EB:
b93a2226
DS		 3874 case ixgbe_mac_X540:
3875 default:
9b471446
JB		 3876 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3877 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3878 break;
3879 }
3880 } else {
021230d4
AV		 3881 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3882 * specifically only auto mask tx and rx interrupts */
3883 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3884 }
9a799d71 3885
a34bcfff
AD		 3886 /* XXX: to interrupt immediately for EICS writes, enable this */
3887 /* gpie |= IXGBE_GPIE_EIMEN; */
3888
3889 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3890 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3891 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3892 }
3893
a34bcfff
AD		 3894 /* Enable fan failure interrupt */
3895 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3896 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3897
2698b208 3898 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3899 gpie |= IXGBE_SDP1_GPIEN;
3900 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3901 }
a34bcfff
AD		 3902
3903 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3904}
3905
3906static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3907{
3908 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3909 int err;
a34bcfff
AD		 3910 u32 ctrl_ext;
3911
3912 ixgbe_get_hw_control(adapter);
3913 ixgbe_setup_gpie(adapter);
e8e26350 3914
9a799d71
AK		 3915 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3916 ixgbe_configure_msix(adapter);
3917 else
3918 ixgbe_configure_msi_and_legacy(adapter);
3919
c6ecf39a
DS		 3920 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3921 if (hw->mac.ops.enable_tx_laser &&
3922 ((hw->phy.multispeed_fiber) ||
9f911707 3923 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3924 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3925 hw->mac.ops.enable_tx_laser(hw);
3926
9a799d71 3927 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3928 ixgbe_napi_enable_all(adapter);
3929
73c4b7cd
AD		 3930 if (ixgbe_is_sfp(hw)) {
3931 ixgbe_sfp_link_config(adapter);
3932 } else {
3933 err = ixgbe_non_sfp_link_config(hw);
3934 if (err)
3935 e_err(probe, "link_config FAILED %d\n", err);
3936 }
3937
021230d4
AV		 3938 /* clear any pending interrupts, may auto mask */
3939 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3940 ixgbe_irq_enable(adapter, true, true);
9a799d71 3941
bf069c97
DS		 3942 /*
3943 * If this adapter has a fan, check to see if we had a failure
3944 * before we enabled the interrupt.
3945 */
3946 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3947 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3948 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3949 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3950 }
3951
1da100bb 3952 /* enable transmits */
477de6ed 3953 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3954
9a799d71
AK		 3955 /* bring the link up in the watchdog, this could race with our first
3956 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3957 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3958 adapter->link_check_timeout = jiffies;
7086400d 3959 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3960
3961 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3962 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3963 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3964 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3965
9a799d71
AK		 3966 return 0;
3967}
3968
d4f80882
AV		 3969void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3970{
3971 WARN_ON(in_interrupt());
7086400d
AD		 3972 /* put off any impending NetWatchDogTimeout */
3973 adapter->netdev->trans_start = jiffies;
3974
d4f80882 3975 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3976 usleep_range(1000, 2000);
d4f80882 3977 ixgbe_down(adapter);
5809a1ae
GR		 3978 /*
3979 * If SR-IOV enabled then wait a bit before bringing the adapter
3980 * back up to give the VFs time to respond to the reset. The
3981 * two second wait is based upon the watchdog timer cycle in
3982 * the VF driver.
3983 */
3984 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3985 msleep(2000);
d4f80882
AV		 3986 ixgbe_up(adapter);
3987 clear_bit(__IXGBE_RESETTING, &adapter->state);
3988}
3989
9a799d71
AK		 3990int ixgbe_up(struct ixgbe_adapter *adapter)
3991{
3992 /* hardware has been reset, we need to reload some things */
3993 ixgbe_configure(adapter);
3994
3995 return ixgbe_up_complete(adapter);
3996}
3997
3998void ixgbe_reset(struct ixgbe_adapter *adapter)
3999{
c44ade9e 4000 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4001 int err;
4002
7086400d
AD		 4003 /* lock SFP init bit to prevent race conditions with the watchdog */
4004 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4005 usleep_range(1000, 2000);
4006
4007 /* clear all SFP and link config related flags while holding SFP_INIT */
4008 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4009 IXGBE_FLAG2_SFP_NEEDS_RESET);
4010 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4011
8ca783ab 4012 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4013 switch (err) {
4014 case 0:
4015 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4016 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4017 break;
4018 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4019 e_dev_err("master disable timed out\n");
da4dd0f7 4020 break;
794caeb2
PWJ		 4021 case IXGBE_ERR_EEPROM_VERSION:
4022 /* We are running on a pre-production device, log a warning */
849c4542
ET		 4023 e_dev_warn("This device is a pre-production adapter/LOM. "
4024 "Please be aware there may be issuesassociated with "
4025 "your hardware. If you are experiencing problems "
4026 "please contact your Intel or hardware "
4027 "representative who provided you with this "
4028 "hardware.\n");
794caeb2 4029 break;
da4dd0f7 4030 default:
849c4542 4031 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4032 }
9a799d71 4033
7086400d
AD		 4034 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4035
9a799d71 4036 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 4037 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4038 IXGBE_RAH_AV);
9a799d71
AK		 4039}
4040
9a799d71
AK		 4041/**
4042 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4043 * @rx_ring: ring to free buffers from
4044 **/
b6ec895e 4045static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4046{
b6ec895e 4047 struct device *dev = rx_ring->dev;
9a799d71 4048 unsigned long size;
b6ec895e 4049 u16 i;
9a799d71 4050
84418e3b
AD		 4051 /* ring already cleared, nothing to do */
4052 if (!rx_ring->rx_buffer_info)
4053 return;
9a799d71 4054
84418e3b 4055 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 4056 for (i = 0; i < rx_ring->count; i++) {
4057 struct ixgbe_rx_buffer *rx_buffer_info;
4058
4059 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4060 if (rx_buffer_info->dma) {
b6ec895e 4061 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 4062 rx_ring->rx_buf_len,
1b507730 4063 DMA_FROM_DEVICE);
9a799d71
AK		 4064 rx_buffer_info->dma = 0;
4065 }
4066 if (rx_buffer_info->skb) {
f8212f97 4067 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 4068 rx_buffer_info->skb = NULL;
f8212f97
AD		 4069 do {
4070 struct sk_buff *this = skb;
e8171aaa 4071 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 4072 dma_unmap_single(dev,
1b507730 4073 IXGBE_RSC_CB(this)->dma,
e8e9f696 4074 rx_ring->rx_buf_len,
1b507730 4075 DMA_FROM_DEVICE);
fd3686a8 4076 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 4077 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 4078 }
f8212f97
AD		 4079 skb = skb->prev;
4080 dev_kfree_skb(this);
4081 } while (skb);
9a799d71
AK		 4082 }
4083 if (!rx_buffer_info->page)
4084 continue;
4f57ca6e 4085 if (rx_buffer_info->page_dma) {
b6ec895e 4086 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 4087 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 4088 rx_buffer_info->page_dma = 0;
4089 }
9a799d71
AK		 4090 put_page(rx_buffer_info->page);
4091 rx_buffer_info->page = NULL;
762f4c57 4092 rx_buffer_info->page_offset = 0;
9a799d71
AK		 4093 }
4094
4095 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4096 memset(rx_ring->rx_buffer_info, 0, size);
4097
4098 /* Zero out the descriptor ring */
4099 memset(rx_ring->desc, 0, rx_ring->size);
4100
4101 rx_ring->next_to_clean = 0;
4102 rx_ring->next_to_use = 0;
9a799d71
AK		 4103}
4104
4105/**
4106 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4107 * @tx_ring: ring to be cleaned
4108 **/
b6ec895e 4109static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4110{
4111 struct ixgbe_tx_buffer *tx_buffer_info;
4112 unsigned long size;
b6ec895e 4113 u16 i;
9a799d71 4114
84418e3b
AD		 4115 /* ring already cleared, nothing to do */
4116 if (!tx_ring->tx_buffer_info)
4117 return;
9a799d71 4118
84418e3b 4119 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4120 for (i = 0; i < tx_ring->count; i++) {
4121 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4122 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4123 }
4124
4125 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4126 memset(tx_ring->tx_buffer_info, 0, size);
4127
4128 /* Zero out the descriptor ring */
4129 memset(tx_ring->desc, 0, tx_ring->size);
4130
4131 tx_ring->next_to_use = 0;
4132 tx_ring->next_to_clean = 0;
9a799d71
AK		 4133}
4134
4135/**
021230d4 4136 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4137 * @adapter: board private structure
4138 **/
021230d4 4139static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4140{
4141 int i;
4142
021230d4 4143 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4144 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4145}
4146
4147/**
021230d4 4148 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4149 * @adapter: board private structure
4150 **/
021230d4 4151static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4152{
4153 int i;
4154
021230d4 4155 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4156 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4157}
4158
4159void ixgbe_down(struct ixgbe_adapter *adapter)
4160{
4161 struct net_device *netdev = adapter->netdev;
7f821875 4162 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4163 u32 rxctrl;
7f821875 4164 u32 txdctl;
bf29ee6c 4165 int i;
b25ebfd2 4166 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 4167
4168 /* signal that we are down to the interrupt handler */
4169 set_bit(__IXGBE_DOWN, &adapter->state);
4170
767081ad
GR		 4171 /* disable receive for all VFs and wait one second */
4172 if (adapter->num_vfs) {
767081ad
GR		 4173 /* ping all the active vfs to let them know we are going down */
4174 ixgbe_ping_all_vfs(adapter);
581d1aa7 4175
767081ad
GR		 4176 /* Disable all VFTE/VFRE TX/RX */
4177 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 4178
4179 /* Mark all the VFs as inactive */
4180 for (i = 0 ; i < adapter->num_vfs; i++)
4181 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 4182 }
4183
9a799d71 4184 /* disable receives */
7f821875
JB		 4185 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4186 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4187
2d39d576
YZ		 4188 /* disable all enabled rx queues */
4189 for (i = 0; i < adapter->num_rx_queues; i++)
4190 /* this call also flushes the previous write */
4191 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4192
032b4325 4193 usleep_range(10000, 20000);
9a799d71 4194
7f821875
JB		 4195 netif_tx_stop_all_queues(netdev);
4196
7086400d 4197 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4198 netif_carrier_off(netdev);
4199 netif_tx_disable(netdev);
4200
4201 ixgbe_irq_disable(adapter);
4202
4203 ixgbe_napi_disable_all(adapter);
4204
d034acf1
AD		 4205 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4206 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4207 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4208
4209 del_timer_sync(&adapter->service_timer);
4210
b25ebfd2
PW		 4211 /* Cleanup the affinity_hint CPU mask memory and callback */
4212 for (i = 0; i < num_q_vectors; i++) {
4213 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4214 /* clear the affinity_mask in the IRQ descriptor */
4215 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4216 /* release the CPU mask memory */
4217 free_cpumask_var(q_vector->affinity_mask);
4218 }
4219
7f821875
JB		 4220 /* disable transmits in the hardware now that interrupts are off */
4221 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c
AD		 4222 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4223 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4224 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
e8e9f696 4225 (txdctl & ~IXGBE_TXDCTL_ENABLE));
7f821875 4226 }
88512539 4227 /* Disable the Tx DMA engine on 82599 */
bd508178
AD		 4228 switch (hw->mac.type) {
4229 case ixgbe_mac_82599EB:
b93a2226 4230 case ixgbe_mac_X540:
88512539 4231 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4232 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4233 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4234 break;
4235 default:
4236 break;
4237 }
7f821875 4238
6f4a0e45
PL		 4239 if (!pci_channel_offline(adapter->pdev))
4240 ixgbe_reset(adapter);
c6ecf39a
DS		 4241
4242 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4243 if (hw->mac.ops.disable_tx_laser &&
4244 ((hw->phy.multispeed_fiber) ||
9f911707 4245 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4246 (hw->mac.type == ixgbe_mac_82599EB))))
4247 hw->mac.ops.disable_tx_laser(hw);
4248
9a799d71
AK		 4249 ixgbe_clean_all_tx_rings(adapter);
4250 ixgbe_clean_all_rx_rings(adapter);
4251
5dd2d332 4252#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4253 /* since we reset the hardware DCA settings were cleared */
e35ec126 4254 ixgbe_setup_dca(adapter);
96b0e0f6 4255#endif
9a799d71
AK		 4256}
4257
9a799d71 4258/**
021230d4
AV		 4259 * ixgbe_poll - NAPI Rx polling callback
4260 * @napi: structure for representing this polling device
4261 * @budget: how many packets driver is allowed to clean
4262 *
4263 * This function is used for legacy and MSI, NAPI mode
9a799d71 4264 **/
021230d4 4265static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4266{
9a1a69ad 4267 struct ixgbe_q_vector *q_vector =
e8e9f696 4268 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4269 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 4270 int tx_clean_complete, work_done = 0;
9a799d71 4271
5dd2d332 4272#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4273 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4274 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4275#endif
4276
4a0b9ca0
PW		 4277 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4278 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 4279
9a1a69ad 4280 if (!tx_clean_complete)
d2c7ddd6
DM		 4281 work_done = budget;
4282
53e52c72
DM		 4283 /* If budget not fully consumed, exit the polling mode */
4284 if (work_done < budget) {
288379f0 4285 napi_complete(napi);
f7554a2b 4286 if (adapter->rx_itr_setting & 1)
f494e8fa 4287 ixgbe_set_itr(adapter);
d4f80882 4288 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 4289 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 4290 }
9a799d71
AK		 4291 return work_done;
4292}
4293
4294/**
4295 * ixgbe_tx_timeout - Respond to a Tx Hang
4296 * @netdev: network interface device structure
4297 **/
4298static void ixgbe_tx_timeout(struct net_device *netdev)
4299{
4300 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4301
4302 /* Do the reset outside of interrupt context */
c83c6cbd 4303 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4304}
4305
4df10466
JB		 4306/**
4307 * ixgbe_set_rss_queues: Allocate queues for RSS
4308 * @adapter: board private structure to initialize
4309 *
4310 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4311 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4312 *
4313 **/
bc97114d
PWJ		 4314static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4315{
4316 bool ret = false;
0cefafad 4317 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4318
4319 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4320 f->mask = 0xF;
4321 adapter->num_rx_queues = f->indices;
4322 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4323 ret = true;
4324 } else {
bc97114d 4325 ret = false;
b9804972
JB		 4326 }
4327
bc97114d
PWJ		 4328 return ret;
4329}
4330
c4cf55e5
PWJ		 4331/**
4332 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4333 * @adapter: board private structure to initialize
4334 *
4335 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4336 * to the original CPU that initiated the Tx session. This runs in addition
4337 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4338 * Rx load across CPUs using RSS.
4339 *
4340 **/
e8e9f696 4341static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4342{
4343 bool ret = false;
4344 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4345
4346 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4347 f_fdir->mask = 0;
4348
4349 /* Flow Director must have RSS enabled */
4350 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4351 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4352 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4353 adapter->num_tx_queues = f_fdir->indices;
4354 adapter->num_rx_queues = f_fdir->indices;
4355 ret = true;
4356 } else {
4357 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4358 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4359 }
4360 return ret;
4361}
4362
0331a832
YZ		 4363#ifdef IXGBE_FCOE
4364/**
4365 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4366 * @adapter: board private structure to initialize
4367 *
4368 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4369 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4370 * rx queues out of the max number of rx queues, instead, it is used as the
4371 * index of the first rx queue used by FCoE.
4372 *
4373 **/
4374static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4375{
0331a832
YZ		 4376 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4377
e5b64635
JF		 4378 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4379 return false;
4380
4381 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
0331a832 4382#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4383 int tc;
4384 struct net_device *dev = adapter->netdev;
4385
4386 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4387 f->indices = dev->tc_to_txq[tc].count;
4388 f->mask = dev->tc_to_txq[tc].offset;
0331a832 4389#endif
e5b64635
JF		 4390 } else {
4391 f->indices = min((int)num_online_cpus(), f->indices);
4392
4393 adapter->num_rx_queues = 1;
4394 adapter->num_tx_queues = 1;
4395
0331a832 4396 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 4397 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 4398 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4399 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4400 ixgbe_set_fdir_queues(adapter);
4401 else
4402 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 4403 }
4404 /* adding FCoE rx rings to the end */
4405 f->mask = adapter->num_rx_queues;
4406 adapter->num_rx_queues += f->indices;
8de8b2e6 4407 adapter->num_tx_queues += f->indices;
e5b64635 4408 }
0331a832 4409
e5b64635
JF		 4410 return true;
4411}
4412#endif /* IXGBE_FCOE */
4413
4414#ifdef CONFIG_IXGBE_DCB
4415static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4416{
4417 bool ret = false;
4418 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4419 int i, q;
4420
4421 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4422 return ret;
4423
4424 f->indices = 0;
4425 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
4426 q = min((int)num_online_cpus(), MAX_TRAFFIC_CLASS);
4427 f->indices += q;
0331a832
YZ		 4428 }
4429
e5b64635
JF		 4430 f->mask = 0x7 << 3;
4431 adapter->num_rx_queues = f->indices;
4432 adapter->num_tx_queues = f->indices;
4433 ret = true;
4434
4435#ifdef IXGBE_FCOE
4436 /* FCoE enabled queues require special configuration done through
4437 * configure_fcoe() and others. Here we map FCoE indices onto the
4438 * DCB queue pairs allowing FCoE to own configuration later.
4439 */
4440 ixgbe_set_fcoe_queues(adapter);
4441#endif
4442
0331a832
YZ		 4443 return ret;
4444}
e5b64635 4445#endif
0331a832 4446
1cdd1ec8
GR		 4447/**
4448 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4449 * @adapter: board private structure to initialize
4450 *
4451 * IOV doesn't actually use anything, so just NAK the
4452 * request for now and let the other queue routines
4453 * figure out what to do.
4454 */
4455static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4456{
4457 return false;
4458}
4459
4df10466 4460/*
25985edc 4461 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4462 * @adapter: board private structure to initialize
4463 *
4464 * This is the top level queue allocation routine. The order here is very
4465 * important, starting with the "most" number of features turned on at once,
4466 * and ending with the smallest set of features. This way large combinations
4467 * can be allocated if they're turned on, and smaller combinations are the
4468 * fallthrough conditions.
4469 *
4470 **/
847f53ff 4471static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4472{
1cdd1ec8
GR		 4473 /* Start with base case */
4474 adapter->num_rx_queues = 1;
4475 adapter->num_tx_queues = 1;
4476 adapter->num_rx_pools = adapter->num_rx_queues;
4477 adapter->num_rx_queues_per_pool = 1;
4478
4479 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4480 goto done;
1cdd1ec8 4481
bc97114d
PWJ		 4482#ifdef CONFIG_IXGBE_DCB
4483 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4484 goto done;
bc97114d
PWJ		 4485
4486#endif
e5b64635
JF		 4487#ifdef IXGBE_FCOE
4488 if (ixgbe_set_fcoe_queues(adapter))
4489 goto done;
4490
4491#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4492 if (ixgbe_set_fdir_queues(adapter))
4493 goto done;
4494
bc97114d 4495 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4496 goto done;
4497
4498 /* fallback to base case */
4499 adapter->num_rx_queues = 1;
4500 adapter->num_tx_queues = 1;
4501
4502done:
847f53ff 4503 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4504 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4505 return netif_set_real_num_rx_queues(adapter->netdev,
4506 adapter->num_rx_queues);
b9804972
JB		 4507}
4508
021230d4 4509static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4510 int vectors)
021230d4
AV		 4511{
4512 int err, vector_threshold;
4513
4514 /* We'll want at least 3 (vector_threshold):
4515 * 1) TxQ[0] Cleanup
4516 * 2) RxQ[0] Cleanup
4517 * 3) Other (Link Status Change, etc.)
4518 * 4) TCP Timer (optional)
4519 */
4520 vector_threshold = MIN_MSIX_COUNT;
4521
4522 /* The more we get, the more we will assign to Tx/Rx Cleanup
4523 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4524 * Right now, we simply care about how many we'll get; we'll
4525 * set them up later while requesting irq's.
4526 */
4527 while (vectors >= vector_threshold) {
4528 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4529 vectors);
021230d4
AV		 4530 if (!err) /* Success in acquiring all requested vectors. */
4531 break;
4532 else if (err < 0)
4533 vectors = 0; /* Nasty failure, quit now */
4534 else /* err == number of vectors we should try again with */
4535 vectors = err;
4536 }
4537
4538 if (vectors < vector_threshold) {
4539 /* Can't allocate enough MSI-X interrupts? Oh well.
4540 * This just means we'll go with either a single MSI
4541 * vector or fall back to legacy interrupts.
4542 */
849c4542
ET		 4543 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4544 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4545 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4546 kfree(adapter->msix_entries);
4547 adapter->msix_entries = NULL;
021230d4
AV		 4548 } else {
4549 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4550 /*
4551 * Adjust for only the vectors we'll use, which is minimum
4552 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4553 * vectors we were allocated.
4554 */
4555 adapter->num_msix_vectors = min(vectors,
e8e9f696 4556 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4557 }
4558}
4559
021230d4 4560/**
bc97114d 4561 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4562 * @adapter: board private structure to initialize
4563 *
bc97114d
PWJ		 4564 * Cache the descriptor ring offsets for RSS to the assigned rings.
4565 *
021230d4 4566 **/
bc97114d 4567static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4568{
bc97114d 4569 int i;
bc97114d 4570
9d6b758f
AD		 4571 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4572 return false;
bc97114d 4573
9d6b758f
AD		 4574 for (i = 0; i < adapter->num_rx_queues; i++)
4575 adapter->rx_ring[i]->reg_idx = i;
4576 for (i = 0; i < adapter->num_tx_queues; i++)
4577 adapter->tx_ring[i]->reg_idx = i;
4578
4579 return true;
bc97114d
PWJ		 4580}
4581
4582#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4583
4584/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4585static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4586 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4587{
4588 struct net_device *dev = adapter->netdev;
4589 struct ixgbe_hw *hw = &adapter->hw;
4590 u8 num_tcs = netdev_get_num_tc(dev);
4591
4592 *tx = 0;
4593 *rx = 0;
4594
4595 switch (hw->mac.type) {
4596 case ixgbe_mac_82598EB:
4597 *tx = tc << 3;
4598 *rx = tc << 2;
4599 break;
4600 case ixgbe_mac_82599EB:
4601 case ixgbe_mac_X540:
4602 if (num_tcs == 8) {
4603 if (tc < 3) {
4604 *tx = tc << 5;
4605 *rx = tc << 4;
4606 } else if (tc < 5) {
4607 *tx = ((tc + 2) << 4);
4608 *rx = tc << 4;
4609 } else if (tc < num_tcs) {
4610 *tx = ((tc + 8) << 3);
4611 *rx = tc << 4;
4612 }
4613 } else if (num_tcs == 4) {
4614 *rx = tc << 5;
4615 switch (tc) {
4616 case 0:
4617 *tx = 0;
4618 break;
4619 case 1:
4620 *tx = 64;
4621 break;
4622 case 2:
4623 *tx = 96;
4624 break;
4625 case 3:
4626 *tx = 112;
4627 break;
4628 default:
4629 break;
4630 }
4631 }
4632 break;
4633 default:
4634 break;
4635 }
4636}
4637
4638#define IXGBE_MAX_Q_PER_TC (IXGBE_MAX_DCB_INDICES / MAX_TRAFFIC_CLASS)
4639
4640/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
4641 * classes.
4642 *
4643 * @netdev: net device to configure
4644 * @tc: number of traffic classes to enable
4645 */
4646int ixgbe_setup_tc(struct net_device *dev, u8 tc)
4647{
4648 int i;
4649 unsigned int q, offset = 0;
4650
4651 if (!tc) {
4652 netdev_reset_tc(dev);
4653 } else {
24095aa3
JF		 4654 struct ixgbe_adapter *adapter = netdev_priv(dev);
4655
4656 /* Hardware supports up to 8 traffic classes */
4657 if (tc > MAX_TRAFFIC_CLASS || netdev_set_num_tc(dev, tc))
e5b64635
JF		 4658 return -EINVAL;
4659
4660 /* Partition Tx queues evenly amongst traffic classes */
4661 for (i = 0; i < tc; i++) {
4662 q = min((int)num_online_cpus(), IXGBE_MAX_Q_PER_TC);
4663 netdev_set_prio_tc_map(dev, i, i);
4664 netdev_set_tc_queue(dev, i, q, offset);
4665 offset += q;
4666 }
24095aa3
JF		 4667
4668 /* This enables multiple traffic class support in the hardware
4669 * which defaults to strict priority transmission by default.
4670 * If traffic classes are already enabled perhaps through DCB
4671 * code path then existing configuration will be used.
4672 */
4673 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
4674 dev->dcbnl_ops && dev->dcbnl_ops->setdcbx) {
4675 struct ieee_ets ets = {
4676 .prio_tc = {0, 1, 2, 3, 4, 5, 6, 7},
4677 };
4678 u8 mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
4679
4680 dev->dcbnl_ops->setdcbx(dev, mode);
4681 dev->dcbnl_ops->ieee_setets(dev, &ets);
4682 }
e5b64635
JF		 4683 }
4684 return 0;
4685}
4686
bc97114d
PWJ		 4687/**
4688 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4689 * @adapter: board private structure to initialize
4690 *
4691 * Cache the descriptor ring offsets for DCB to the assigned rings.
4692 *
4693 **/
4694static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4695{
e5b64635
JF		 4696 struct net_device *dev = adapter->netdev;
4697 int i, j, k;
4698 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4699
bd508178
AD		 4700 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4701 return false;
f92ef202 4702
e5b64635
JF		 4703 for (i = 0, k = 0; i < num_tcs; i++) {
4704 unsigned int tx_s, rx_s;
4705 u16 count = dev->tc_to_txq[i].count;
4706
4707 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4708 for (j = 0; j < count; j++, k++) {
4709 adapter->tx_ring[k]->reg_idx = tx_s + j;
4710 adapter->rx_ring[k]->reg_idx = rx_s + j;
4711 adapter->tx_ring[k]->dcb_tc = i;
4712 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4713 }
021230d4 4714 }
e5b64635
JF		 4715
4716 return true;
bc97114d
PWJ		 4717}
4718#endif
4719
c4cf55e5
PWJ		 4720/**
4721 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4722 * @adapter: board private structure to initialize
4723 *
4724 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4725 *
4726 **/
e8e9f696 4727static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4728{
4729 int i;
4730 bool ret = false;
4731
4732 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4733 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4734 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4735 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4736 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4737 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4738 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4739 ret = true;
4740 }
4741
4742 return ret;
4743}
4744
0331a832
YZ		 4745#ifdef IXGBE_FCOE
4746/**
4747 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4748 * @adapter: board private structure to initialize
4749 *
4750 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4751 *
4752 */
4753static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4754{
0331a832 4755 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4756 int i;
4757 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4758
4759 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4760 return false;
0331a832 4761
bf29ee6c
AD		 4762 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4763 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4764 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4765 ixgbe_cache_ring_fdir(adapter);
4766 else
4767 ixgbe_cache_ring_rss(adapter);
8faa2a78 4768
bf29ee6c
AD		 4769 fcoe_rx_i = f->mask;
4770 fcoe_tx_i = f->mask;
0331a832 4771 }
bf29ee6c
AD		 4772 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4773 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4774 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4775 }
4776 return true;
0331a832
YZ		 4777}
4778
4779#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4780/**
4781 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4782 * @adapter: board private structure to initialize
4783 *
4784 * SR-IOV doesn't use any descriptor rings but changes the default if
4785 * no other mapping is used.
4786 *
4787 */
4788static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4789{
4a0b9ca0
PW		 4790 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4791 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4792 if (adapter->num_vfs)
4793 return true;
4794 else
4795 return false;
4796}
4797
bc97114d
PWJ		 4798/**
4799 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4800 * @adapter: board private structure to initialize
4801 *
4802 * Once we know the feature-set enabled for the device, we'll cache
4803 * the register offset the descriptor ring is assigned to.
4804 *
4805 * Note, the order the various feature calls is important. It must start with
4806 * the "most" features enabled at the same time, then trickle down to the
4807 * least amount of features turned on at once.
4808 **/
4809static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4810{
4811 /* start with default case */
4a0b9ca0
PW		 4812 adapter->rx_ring[0]->reg_idx = 0;
4813 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4814
1cdd1ec8
GR		 4815 if (ixgbe_cache_ring_sriov(adapter))
4816 return;
4817
e5b64635
JF		 4818#ifdef CONFIG_IXGBE_DCB
4819 if (ixgbe_cache_ring_dcb(adapter))
4820 return;
4821#endif
4822
0331a832
YZ		 4823#ifdef IXGBE_FCOE
4824 if (ixgbe_cache_ring_fcoe(adapter))
4825 return;
0331a832 4826#endif /* IXGBE_FCOE */
bc97114d 4827
c4cf55e5
PWJ		 4828 if (ixgbe_cache_ring_fdir(adapter))
4829 return;
4830
bc97114d
PWJ		 4831 if (ixgbe_cache_ring_rss(adapter))
4832 return;
021230d4
AV		 4833}
4834
9a799d71
AK		 4835/**
4836 * ixgbe_alloc_queues - Allocate memory for all rings
4837 * @adapter: board private structure to initialize
4838 *
4839 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4840 * number of queues at compile-time. The polling_netdev array is
4841 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4842 **/
2f90b865 4843static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4844{
e2ddeba9 4845 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4846
e2ddeba9
ED		 4847 if (nid < 0 || !node_online(nid))
4848 nid = first_online_node;
4849
4850 for (; tx < adapter->num_tx_queues; tx++) {
4851 struct ixgbe_ring *ring;
4852
4853 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4854 if (!ring)
e2ddeba9 4855 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4856 if (!ring)
e2ddeba9 4857 goto err_allocation;
4a0b9ca0 4858 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4859 ring->queue_index = tx;
4860 ring->numa_node = nid;
b6ec895e 4861 ring->dev = &adapter->pdev->dev;
fc77dc3c 4862 ring->netdev = adapter->netdev;
4a0b9ca0 4863
e2ddeba9 4864 adapter->tx_ring[tx] = ring;
021230d4 4865 }
b9804972 4866
e2ddeba9
ED		 4867 for (; rx < adapter->num_rx_queues; rx++) {
4868 struct ixgbe_ring *ring;
4a0b9ca0 4869
e2ddeba9 4870 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4871 if (!ring)
e2ddeba9 4872 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4873 if (!ring)
e2ddeba9
ED		 4874 goto err_allocation;
4875 ring->count = adapter->rx_ring_count;
4876 ring->queue_index = rx;
4877 ring->numa_node = nid;
b6ec895e 4878 ring->dev = &adapter->pdev->dev;
fc77dc3c 4879 ring->netdev = adapter->netdev;
4a0b9ca0 4880
e2ddeba9 4881 adapter->rx_ring[rx] = ring;
021230d4
AV		 4882 }
4883
4884 ixgbe_cache_ring_register(adapter);
4885
4886 return 0;
4887
e2ddeba9
ED		 4888err_allocation:
4889 while (tx)
4890 kfree(adapter->tx_ring[--tx]);
4891
4892 while (rx)
4893 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4894 return -ENOMEM;
4895}
4896
4897/**
4898 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4899 * @adapter: board private structure to initialize
4900 *
4901 * Attempt to configure the interrupts using the best available
4902 * capabilities of the hardware and the kernel.
4903 **/
feea6a57 4904static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4905{
8be0e467 4906 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4907 int err = 0;
4908 int vector, v_budget;
4909
4910 /*
4911 * It's easy to be greedy for MSI-X vectors, but it really
4912 * doesn't do us much good if we have a lot more vectors
4913 * than CPU's. So let's be conservative and only ask for
342bde1b 4914 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4915 */
4916 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4917 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4918
4919 /*
4920 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4921 * hw.mac->max_msix_vectors vectors. With features
4922 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4923 * descriptor queues supported by our device. Thus, we cap it off in
4924 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4925 */
8be0e467 4926 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4927
4928 /* A failure in MSI-X entry allocation isn't fatal, but it does
4929 * mean we disable MSI-X capabilities of the adapter. */
4930 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4931 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4932 if (adapter->msix_entries) {
4933 for (vector = 0; vector < v_budget; vector++)
4934 adapter->msix_entries[vector].entry = vector;
021230d4 4935
7a921c93 4936 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4937
7a921c93
AD		 4938 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4939 goto out;
4940 }
26d27844 4941
7a921c93
AD		 4942 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4943 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
45b9f509
AD		 4944 if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4945 IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4946 e_err(probe,
4947 "Flow Director is not supported while multiple "
4948 "queues are disabled. Disabling Flow Director\n");
4949 }
c4cf55e5
PWJ		 4950 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4951 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4952 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4953 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4954 ixgbe_disable_sriov(adapter);
4955
847f53ff
BH		 4956 err = ixgbe_set_num_queues(adapter);
4957 if (err)
4958 return err;
021230d4 4959
021230d4
AV		 4960 err = pci_enable_msi(adapter->pdev);
4961 if (!err) {
4962 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4963 } else {
849c4542
ET		 4964 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4965 "Unable to allocate MSI interrupt, "
4966 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4967 /* reset err */
4968 err = 0;
4969 }
4970
4971out:
021230d4
AV		 4972 return err;
4973}
4974
7a921c93
AD		 4975/**
4976 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4977 * @adapter: board private structure to initialize
4978 *
4979 * We allocate one q_vector per queue interrupt. If allocation fails we
4980 * return -ENOMEM.
4981 **/
4982static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4983{
4984 int q_idx, num_q_vectors;
4985 struct ixgbe_q_vector *q_vector;
7a921c93
AD		 4986 int (*poll)(struct napi_struct *, int);
4987
4988 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4989 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4990 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4991 } else {
4992 num_q_vectors = 1;
7a921c93
AD		 4993 poll = &ixgbe_poll;
4994 }
4995
4996 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4997 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4998 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4999 if (!q_vector)
5000 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 5001 GFP_KERNEL);
7a921c93
AD		 5002 if (!q_vector)
5003 goto err_out;
5004 q_vector->adapter = adapter;
f7554a2b
NS		 5005 if (q_vector->txr_count && !q_vector->rxr_count)
5006 q_vector->eitr = adapter->tx_eitr_param;
5007 else
5008 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 5009 q_vector->v_idx = q_idx;
91281fd3 5010 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 5011 adapter->q_vector[q_idx] = q_vector;
5012 }
5013
5014 return 0;
5015
5016err_out:
5017 while (q_idx) {
5018 q_idx--;
5019 q_vector = adapter->q_vector[q_idx];
5020 netif_napi_del(&q_vector->napi);
5021 kfree(q_vector);
5022 adapter->q_vector[q_idx] = NULL;
5023 }
5024 return -ENOMEM;
5025}
5026
5027/**
5028 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5029 * @adapter: board private structure to initialize
5030 *
5031 * This function frees the memory allocated to the q_vectors. In addition if
5032 * NAPI is enabled it will delete any references to the NAPI struct prior
5033 * to freeing the q_vector.
5034 **/
5035static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5036{
5037 int q_idx, num_q_vectors;
7a921c93 5038
91281fd3 5039 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 5040 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 5041 else
7a921c93 5042 num_q_vectors = 1;
7a921c93
AD		 5043
5044 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5045 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 5046 adapter->q_vector[q_idx] = NULL;
91281fd3 5047 netif_napi_del(&q_vector->napi);
7a921c93
AD		 5048 kfree(q_vector);
5049 }
5050}
5051
7b25cdba 5052static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 5053{
5054 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5055 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5056 pci_disable_msix(adapter->pdev);
5057 kfree(adapter->msix_entries);
5058 adapter->msix_entries = NULL;
5059 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5060 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5061 pci_disable_msi(adapter->pdev);
5062 }
021230d4
AV		 5063}
5064
5065/**
5066 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5067 * @adapter: board private structure to initialize
5068 *
5069 * We determine which interrupt scheme to use based on...
5070 * - Kernel support (MSI, MSI-X)
5071 * - which can be user-defined (via MODULE_PARAM)
5072 * - Hardware queue count (num_*_queues)
5073 * - defined by miscellaneous hardware support/features (RSS, etc.)
5074 **/
2f90b865 5075int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 5076{
5077 int err;
5078
5079 /* Number of supported queues */
847f53ff
BH		 5080 err = ixgbe_set_num_queues(adapter);
5081 if (err)
5082 return err;
021230d4 5083
021230d4
AV		 5084 err = ixgbe_set_interrupt_capability(adapter);
5085 if (err) {
849c4542 5086 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 5087 goto err_set_interrupt;
9a799d71
AK		 5088 }
5089
7a921c93
AD		 5090 err = ixgbe_alloc_q_vectors(adapter);
5091 if (err) {
849c4542 5092 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 5093 goto err_alloc_q_vectors;
5094 }
5095
5096 err = ixgbe_alloc_queues(adapter);
5097 if (err) {
849c4542 5098 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 5099 goto err_alloc_queues;
5100 }
5101
849c4542 5102 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 5103 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5104 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 5105
5106 set_bit(__IXGBE_DOWN, &adapter->state);
5107
9a799d71 5108 return 0;
021230d4 5109
7a921c93
AD		 5110err_alloc_queues:
5111 ixgbe_free_q_vectors(adapter);
5112err_alloc_q_vectors:
5113 ixgbe_reset_interrupt_capability(adapter);
021230d4 5114err_set_interrupt:
7a921c93
AD		 5115 return err;
5116}
5117
1a51502b
ED		 5118static void ring_free_rcu(struct rcu_head *head)
5119{
5120 kfree(container_of(head, struct ixgbe_ring, rcu));
5121}
5122
7a921c93
AD		 5123/**
5124 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5125 * @adapter: board private structure to clear interrupt scheme on
5126 *
5127 * We go through and clear interrupt specific resources and reset the structure
5128 * to pre-load conditions
5129 **/
5130void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5131{
4a0b9ca0
PW		 5132 int i;
5133
5134 for (i = 0; i < adapter->num_tx_queues; i++) {
5135 kfree(adapter->tx_ring[i]);
5136 adapter->tx_ring[i] = NULL;
5137 }
5138 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 5139 struct ixgbe_ring *ring = adapter->rx_ring[i];
5140
5141 /* ixgbe_get_stats64() might access this ring, we must wait
5142 * a grace period before freeing it.
5143 */
5144 call_rcu(&ring->rcu, ring_free_rcu);
4a0b9ca0
PW		 5145 adapter->rx_ring[i] = NULL;
5146 }
7a921c93 5147
b8eb3a10
DS		 5148 adapter->num_tx_queues = 0;
5149 adapter->num_rx_queues = 0;
5150
7a921c93
AD		 5151 ixgbe_free_q_vectors(adapter);
5152 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5153}
5154
5155/**
5156 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5157 * @adapter: board private structure to initialize
5158 *
5159 * ixgbe_sw_init initializes the Adapter private data structure.
5160 * Fields are initialized based on PCI device information and
5161 * OS network device settings (MTU size).
5162 **/
5163static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5164{
5165 struct ixgbe_hw *hw = &adapter->hw;
5166 struct pci_dev *pdev = adapter->pdev;
9a713e7c 5167 struct net_device *dev = adapter->netdev;
021230d4 5168 unsigned int rss;
7a6b6f51 5169#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5170 int j;
5171 struct tc_configuration *tc;
5172#endif
16b61beb 5173 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 5174
c44ade9e
JB		 5175 /* PCI config space info */
5176
5177 hw->vendor_id = pdev->vendor;
5178 hw->device_id = pdev->device;
5179 hw->revision_id = pdev->revision;
5180 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5181 hw->subsystem_device_id = pdev->subsystem_device;
5182
021230d4
AV		 5183 /* Set capability flags */
5184 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5185 adapter->ring_feature[RING_F_RSS].indices = rss;
5186 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 5187 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bd508178
AD		 5188 switch (hw->mac.type) {
5189 case ixgbe_mac_82598EB:
bf069c97
DS		 5190 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5191 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5192 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178
AD		 5193 break;
5194 case ixgbe_mac_82599EB:
b93a2226 5195 case ixgbe_mac_X540:
e8e26350 5196 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5197 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5198 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5199 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5200 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5201 /* n-tuple support exists, always init our spinlock */
5202 spin_lock_init(&adapter->fdir_perfect_lock);
5203 /* Flow Director hash filters enabled */
5204 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5205 adapter->atr_sample_rate = 20;
c4cf55e5 5206 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5207 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 5208 adapter->fdir_pballoc = 0;
eacd73f7 5209#ifdef IXGBE_FCOE
0d551589
YZ		 5210 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5211 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5212 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5213#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 5214 /* Default traffic class to use for FCoE */
5215 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 5216 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5217#endif
eacd73f7 5218#endif /* IXGBE_FCOE */
bd508178
AD		 5219 break;
5220 default:
5221 break;
f8212f97 5222 }
2f90b865 5223
7a6b6f51 5224#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5225 /* Configure DCB traffic classes */
5226 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5227 tc = &adapter->dcb_cfg.tc_config[j];
5228 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5229 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5230 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5231 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5232 tc->dcb_pfc = pfc_disabled;
5233 }
5234 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5235 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5236 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 5237 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5238 adapter->dcb_set_bitmap = 0x00;
3032309b 5239 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5240 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5241 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5242
5243#endif
9a799d71
AK		 5244
5245 /* default flow control settings */
cd7664f6 5246 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5247 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5248#ifdef CONFIG_DCB
5249 adapter->last_lfc_mode = hw->fc.current_mode;
5250#endif
16b61beb
JF		 5251 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5252 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 5253 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5254 hw->fc.send_xon = true;
71fd570b 5255 hw->fc.disable_fc_autoneg = false;
9a799d71 5256
30efa5a3 5257 /* enable itr by default in dynamic mode */
f7554a2b
NS		 5258 adapter->rx_itr_setting = 1;
5259 adapter->rx_eitr_param = 20000;
5260 adapter->tx_itr_setting = 1;
5261 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 5262
5263 /* set defaults for eitr in MegaBytes */
5264 adapter->eitr_low = 10;
5265 adapter->eitr_high = 20;
5266
5267 /* set default ring sizes */
5268 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5269 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5270
9a799d71 5271 /* initialize eeprom parameters */
c44ade9e 5272 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5273 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5274 return -EIO;
5275 }
5276
021230d4 5277 /* enable rx csum by default */
9a799d71
AK		 5278 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5279
1a6c14a2
JB		 5280 /* get assigned NUMA node */
5281 adapter->node = dev_to_node(&pdev->dev);
5282
9a799d71
AK		 5283 set_bit(__IXGBE_DOWN, &adapter->state);
5284
5285 return 0;
5286}
5287
5288/**
5289 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5290 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5291 *
5292 * Return 0 on success, negative on failure
5293 **/
b6ec895e 5294int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5295{
b6ec895e 5296 struct device *dev = tx_ring->dev;
9a799d71
AK		 5297 int size;
5298
3a581073 5299 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5300 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5301 if (!tx_ring->tx_buffer_info)
89bf67f1 5302 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5303 if (!tx_ring->tx_buffer_info)
5304 goto err;
9a799d71
AK		 5305
5306 /* round up to nearest 4K */
12207e49 5307 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5308 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5309
b6ec895e 5310 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5311 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5312 if (!tx_ring->desc)
5313 goto err;
9a799d71 5314
3a581073
JB		 5315 tx_ring->next_to_use = 0;
5316 tx_ring->next_to_clean = 0;
5317 tx_ring->work_limit = tx_ring->count;
9a799d71 5318 return 0;
e01c31a5
JB		 5319
5320err:
5321 vfree(tx_ring->tx_buffer_info);
5322 tx_ring->tx_buffer_info = NULL;
b6ec895e 5323 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5324 return -ENOMEM;
9a799d71
AK		 5325}
5326
69888674
AD		 5327/**
5328 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5329 * @adapter: board private structure
5330 *
5331 * If this function returns with an error, then it's possible one or
5332 * more of the rings is populated (while the rest are not). It is the
5333 * callers duty to clean those orphaned rings.
5334 *
5335 * Return 0 on success, negative on failure
5336 **/
5337static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5338{
5339 int i, err = 0;
5340
5341 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5342 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5343 if (!err)
5344 continue;
396e799c 5345 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5346 break;
5347 }
5348
5349 return err;
5350}
5351
9a799d71
AK		 5352/**
5353 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5354 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5355 *
5356 * Returns 0 on success, negative on failure
5357 **/
b6ec895e 5358int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5359{
b6ec895e 5360 struct device *dev = rx_ring->dev;
021230d4 5361 int size;
9a799d71 5362
3a581073 5363 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5364 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5365 if (!rx_ring->rx_buffer_info)
89bf67f1 5366 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5367 if (!rx_ring->rx_buffer_info)
5368 goto err;
9a799d71 5369
9a799d71 5370 /* Round up to nearest 4K */
3a581073
JB		 5371 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5372 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5373
b6ec895e 5374 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5375 &rx_ring->dma, GFP_KERNEL);
9a799d71 5376
b6ec895e
AD		 5377 if (!rx_ring->desc)
5378 goto err;
9a799d71 5379
3a581073
JB		 5380 rx_ring->next_to_clean = 0;
5381 rx_ring->next_to_use = 0;
9a799d71
AK		 5382
5383 return 0;
b6ec895e
AD		 5384err:
5385 vfree(rx_ring->rx_buffer_info);
5386 rx_ring->rx_buffer_info = NULL;
5387 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5388 return -ENOMEM;
9a799d71
AK		 5389}
5390
69888674
AD		 5391/**
5392 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5393 * @adapter: board private structure
5394 *
5395 * If this function returns with an error, then it's possible one or
5396 * more of the rings is populated (while the rest are not). It is the
5397 * callers duty to clean those orphaned rings.
5398 *
5399 * Return 0 on success, negative on failure
5400 **/
69888674
AD		 5401static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5402{
5403 int i, err = 0;
5404
5405 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5406 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5407 if (!err)
5408 continue;
396e799c 5409 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5410 break;
5411 }
5412
5413 return err;
5414}
5415
9a799d71
AK		 5416/**
5417 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5418 * @tx_ring: Tx descriptor ring for a specific queue
5419 *
5420 * Free all transmit software resources
5421 **/
b6ec895e 5422void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5423{
b6ec895e 5424 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5425
5426 vfree(tx_ring->tx_buffer_info);
5427 tx_ring->tx_buffer_info = NULL;
5428
b6ec895e
AD		 5429 /* if not set, then don't free */
5430 if (!tx_ring->desc)
5431 return;
5432
5433 dma_free_coherent(tx_ring->dev, tx_ring->size,
5434 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5435
5436 tx_ring->desc = NULL;
5437}
5438
5439/**
5440 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5441 * @adapter: board private structure
5442 *
5443 * Free all transmit software resources
5444 **/
5445static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5446{
5447 int i;
5448
5449 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5450 if (adapter->tx_ring[i]->desc)
b6ec895e 5451 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5452}
5453
5454/**
b4617240 5455 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5456 * @rx_ring: ring to clean the resources from
5457 *
5458 * Free all receive software resources
5459 **/
b6ec895e 5460void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5461{
b6ec895e 5462 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5463
5464 vfree(rx_ring->rx_buffer_info);
5465 rx_ring->rx_buffer_info = NULL;
5466
b6ec895e
AD		 5467 /* if not set, then don't free */
5468 if (!rx_ring->desc)
5469 return;
5470
5471 dma_free_coherent(rx_ring->dev, rx_ring->size,
5472 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5473
5474 rx_ring->desc = NULL;
5475}
5476
5477/**
5478 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5479 * @adapter: board private structure
5480 *
5481 * Free all receive software resources
5482 **/
5483static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5484{
5485 int i;
5486
5487 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5488 if (adapter->rx_ring[i]->desc)
b6ec895e 5489 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5490}
5491
9a799d71
AK		 5492/**
5493 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5494 * @netdev: network interface device structure
5495 * @new_mtu: new value for maximum frame size
5496 *
5497 * Returns 0 on success, negative on failure
5498 **/
5499static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5500{
5501 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5502 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5503 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5504
42c783c5 5505 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5506 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5507 hw->mac.type != ixgbe_mac_X540) {
5508 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5509 return -EINVAL;
5510 } else {
5511 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5512 return -EINVAL;
5513 }
9a799d71 5514
396e799c 5515 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5516 /* must set new MTU before calling down or up */
9a799d71
AK		 5517 netdev->mtu = new_mtu;
5518
16b61beb
JF		 5519 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5520 hw->fc.low_water = FC_LOW_WATER(max_frame);
5521
d4f80882
AV		 5522 if (netif_running(netdev))
5523 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5524
5525 return 0;
5526}
5527
5528/**
5529 * ixgbe_open - Called when a network interface is made active
5530 * @netdev: network interface device structure
5531 *
5532 * Returns 0 on success, negative value on failure
5533 *
5534 * The open entry point is called when a network interface is made
5535 * active by the system (IFF_UP). At this point all resources needed
5536 * for transmit and receive operations are allocated, the interrupt
5537 * handler is registered with the OS, the watchdog timer is started,
5538 * and the stack is notified that the interface is ready.
5539 **/
5540static int ixgbe_open(struct net_device *netdev)
5541{
5542 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5543 int err;
4bebfaa5
AK		 5544
5545 /* disallow open during test */
5546 if (test_bit(__IXGBE_TESTING, &adapter->state))
5547 return -EBUSY;
9a799d71 5548
54386467
JB		 5549 netif_carrier_off(netdev);
5550
9a799d71
AK		 5551 /* allocate transmit descriptors */
5552 err = ixgbe_setup_all_tx_resources(adapter);
5553 if (err)
5554 goto err_setup_tx;
5555
9a799d71
AK		 5556 /* allocate receive descriptors */
5557 err = ixgbe_setup_all_rx_resources(adapter);
5558 if (err)
5559 goto err_setup_rx;
5560
5561 ixgbe_configure(adapter);
5562
021230d4 5563 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5564 if (err)
5565 goto err_req_irq;
5566
9a799d71
AK		 5567 err = ixgbe_up_complete(adapter);
5568 if (err)
5569 goto err_up;
5570
d55b53ff
JK		 5571 netif_tx_start_all_queues(netdev);
5572
9a799d71
AK		 5573 return 0;
5574
5575err_up:
5eba3699 5576 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5577 ixgbe_free_irq(adapter);
5578err_req_irq:
9a799d71 5579err_setup_rx:
a20a1199 5580 ixgbe_free_all_rx_resources(adapter);
9a799d71 5581err_setup_tx:
a20a1199 5582 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5583 ixgbe_reset(adapter);
5584
5585 return err;
5586}
5587
5588/**
5589 * ixgbe_close - Disables a network interface
5590 * @netdev: network interface device structure
5591 *
5592 * Returns 0, this is not allowed to fail
5593 *
5594 * The close entry point is called when an interface is de-activated
5595 * by the OS. The hardware is still under the drivers control, but
5596 * needs to be disabled. A global MAC reset is issued to stop the
5597 * hardware, and all transmit and receive resources are freed.
5598 **/
5599static int ixgbe_close(struct net_device *netdev)
5600{
5601 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5602
5603 ixgbe_down(adapter);
5604 ixgbe_free_irq(adapter);
5605
5606 ixgbe_free_all_tx_resources(adapter);
5607 ixgbe_free_all_rx_resources(adapter);
5608
5eba3699 5609 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5610
5611 return 0;
5612}
5613
b3c8b4ba
AD		 5614#ifdef CONFIG_PM
5615static int ixgbe_resume(struct pci_dev *pdev)
5616{
c60fbb00
AD		 5617 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5618 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5619 u32 err;
5620
5621 pci_set_power_state(pdev, PCI_D0);
5622 pci_restore_state(pdev);
656ab817
DS		 5623 /*
5624 * pci_restore_state clears dev->state_saved so call
5625 * pci_save_state to restore it.
5626 */
5627 pci_save_state(pdev);
9ce77666 5628
5629 err = pci_enable_device_mem(pdev);
b3c8b4ba 5630 if (err) {
849c4542 5631 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5632 return err;
5633 }
5634 pci_set_master(pdev);
5635
dd4d8ca6 5636 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5637
5638 err = ixgbe_init_interrupt_scheme(adapter);
5639 if (err) {
849c4542 5640 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5641 return err;
5642 }
5643
b3c8b4ba
AD		 5644 ixgbe_reset(adapter);
5645
495dce12
WJP		 5646 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5647
b3c8b4ba 5648 if (netif_running(netdev)) {
c60fbb00 5649 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5650 if (err)
5651 return err;
5652 }
5653
5654 netif_device_attach(netdev);
5655
5656 return 0;
5657}
b3c8b4ba 5658#endif /* CONFIG_PM */
9d8d05ae
RW		 5659
5660static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5661{
c60fbb00
AD		 5662 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5663 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5664 struct ixgbe_hw *hw = &adapter->hw;
5665 u32 ctrl, fctrl;
5666 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5667#ifdef CONFIG_PM
5668 int retval = 0;
5669#endif
5670
5671 netif_device_detach(netdev);
5672
5673 if (netif_running(netdev)) {
5674 ixgbe_down(adapter);
5675 ixgbe_free_irq(adapter);
5676 ixgbe_free_all_tx_resources(adapter);
5677 ixgbe_free_all_rx_resources(adapter);
5678 }
b3c8b4ba 5679
5f5ae6fc 5680 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5681#ifdef CONFIG_DCB
5682 kfree(adapter->ixgbe_ieee_pfc);
5683 kfree(adapter->ixgbe_ieee_ets);
5684#endif
5f5ae6fc 5685
b3c8b4ba
AD		 5686#ifdef CONFIG_PM
5687 retval = pci_save_state(pdev);
5688 if (retval)
5689 return retval;
4df10466 5690
b3c8b4ba 5691#endif
e8e26350
PW		 5692 if (wufc) {
5693 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5694
e8e26350
PW		 5695 /* turn on all-multi mode if wake on multicast is enabled */
5696 if (wufc & IXGBE_WUFC_MC) {
5697 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5698 fctrl |= IXGBE_FCTRL_MPE;
5699 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5700 }
5701
5702 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5703 ctrl |= IXGBE_CTRL_GIO_DIS;
5704 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5705
5706 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5707 } else {
5708 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5709 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5710 }
5711
bd508178
AD		 5712 switch (hw->mac.type) {
5713 case ixgbe_mac_82598EB:
dd4d8ca6 5714 pci_wake_from_d3(pdev, false);
bd508178
AD		 5715 break;
5716 case ixgbe_mac_82599EB:
b93a2226 5717 case ixgbe_mac_X540:
bd508178
AD		 5718 pci_wake_from_d3(pdev, !!wufc);
5719 break;
5720 default:
5721 break;
5722 }
b3c8b4ba 5723
9d8d05ae
RW		 5724 *enable_wake = !!wufc;
5725
b3c8b4ba
AD		 5726 ixgbe_release_hw_control(adapter);
5727
5728 pci_disable_device(pdev);
5729
9d8d05ae
RW		 5730 return 0;
5731}
5732
5733#ifdef CONFIG_PM
5734static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5735{
5736 int retval;
5737 bool wake;
5738
5739 retval = __ixgbe_shutdown(pdev, &wake);
5740 if (retval)
5741 return retval;
5742
5743 if (wake) {
5744 pci_prepare_to_sleep(pdev);
5745 } else {
5746 pci_wake_from_d3(pdev, false);
5747 pci_set_power_state(pdev, PCI_D3hot);
5748 }
b3c8b4ba
AD		 5749
5750 return 0;
5751}
9d8d05ae 5752#endif /* CONFIG_PM */
b3c8b4ba
AD		 5753
5754static void ixgbe_shutdown(struct pci_dev *pdev)
5755{
9d8d05ae
RW		 5756 bool wake;
5757
5758 __ixgbe_shutdown(pdev, &wake);
5759
5760 if (system_state == SYSTEM_POWER_OFF) {
5761 pci_wake_from_d3(pdev, wake);
5762 pci_set_power_state(pdev, PCI_D3hot);
5763 }
b3c8b4ba
AD		 5764}
5765
9a799d71
AK		 5766/**
5767 * ixgbe_update_stats - Update the board statistics counters.
5768 * @adapter: board private structure
5769 **/
5770void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5771{
2d86f139 5772 struct net_device *netdev = adapter->netdev;
9a799d71 5773 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5774 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5775 u64 total_mpc = 0;
5776 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5777 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5778 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5779 u64 bytes = 0, packets = 0;
9a799d71 5780
d08935c2
DS		 5781 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5782 test_bit(__IXGBE_RESETTING, &adapter->state))
5783 return;
5784
94b982b2 5785 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5786 u64 rsc_count = 0;
94b982b2 5787 u64 rsc_flush = 0;
d51019a4
PW		 5788 for (i = 0; i < 16; i++)
5789 adapter->hw_rx_no_dma_resources +=
7ca647bd 5790 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5791 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5792 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5793 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5794 }
5795 adapter->rsc_total_count = rsc_count;
5796 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5797 }
5798
5b7da515
AD		 5799 for (i = 0; i < adapter->num_rx_queues; i++) {
5800 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5801 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5802 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5803 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5804 bytes += rx_ring->stats.bytes;
5805 packets += rx_ring->stats.packets;
5806 }
5807 adapter->non_eop_descs = non_eop_descs;
5808 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5809 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5810 netdev->stats.rx_bytes = bytes;
5811 netdev->stats.rx_packets = packets;
5812
5813 bytes = 0;
5814 packets = 0;
7ca3bc58 5815 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5816 for (i = 0; i < adapter->num_tx_queues; i++) {
5817 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5818 restart_queue += tx_ring->tx_stats.restart_queue;
5819 tx_busy += tx_ring->tx_stats.tx_busy;
5820 bytes += tx_ring->stats.bytes;
5821 packets += tx_ring->stats.packets;
5822 }
eb985f09 5823 adapter->restart_queue = restart_queue;
5b7da515
AD		 5824 adapter->tx_busy = tx_busy;
5825 netdev->stats.tx_bytes = bytes;
5826 netdev->stats.tx_packets = packets;
7ca3bc58 5827
7ca647bd 5828 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5829 for (i = 0; i < 8; i++) {
5830 /* for packet buffers not used, the register should read 0 */
5831 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5832 missed_rx += mpc;
7ca647bd
JP		 5833 hwstats->mpc[i] += mpc;
5834 total_mpc += hwstats->mpc[i];
e8e26350 5835 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5836 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5837 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5838 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5839 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5840 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
bd508178
AD		 5841 switch (hw->mac.type) {
5842 case ixgbe_mac_82598EB:
7ca647bd
JP		 5843 hwstats->pxonrxc[i] +=
5844 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5845 break;
5846 case ixgbe_mac_82599EB:
b93a2226 5847 case ixgbe_mac_X540:
bd508178
AD		 5848 hwstats->pxonrxc[i] +=
5849 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5850 break;
5851 default:
5852 break;
e8e26350 5853 }
7ca647bd
JP		 5854 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5855 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5856 }
7ca647bd 5857 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5858 /* work around hardware counting issue */
7ca647bd 5859 hwstats->gprc -= missed_rx;
6f11eef7 5860
c84d324c
JF		 5861 ixgbe_update_xoff_received(adapter);
5862
6f11eef7 5863 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5864 switch (hw->mac.type) {
5865 case ixgbe_mac_82598EB:
5866 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5867 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5868 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5869 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5870 break;
b93a2226 5871 case ixgbe_mac_X540:
58f6bcf9
ET		 5872 /* OS2BMC stats are X540 only*/
5873 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5874 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5875 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5876 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5877 case ixgbe_mac_82599EB:
7ca647bd 5878 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5879 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5880 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5881 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5882 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5883 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5884 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5885 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5886 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5887#ifdef IXGBE_FCOE
7ca647bd
JP		 5888 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5889 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5890 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5891 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5892 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5893 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5894#endif /* IXGBE_FCOE */
bd508178
AD		 5895 break;
5896 default:
5897 break;
e8e26350 5898 }
9a799d71 5899 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5900 hwstats->bprc += bprc;
5901 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5902 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5903 hwstats->mprc -= bprc;
5904 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5905 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5906 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5907 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5908 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5909 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5910 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5911 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5912 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5913 hwstats->lxontxc += lxon;
6f11eef7 5914 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5915 hwstats->lxofftxc += lxoff;
5916 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5917 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5918 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5919 /*
5920 * 82598 errata - tx of flow control packets is included in tx counters
5921 */
5922 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5923 hwstats->gptc -= xon_off_tot;
5924 hwstats->mptc -= xon_off_tot;
5925 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5926 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5927 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5928 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5929 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5930 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5931 hwstats->ptc64 -= xon_off_tot;
5932 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5933 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5934 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5935 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5936 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5937 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5938
5939 /* Fill out the OS statistics structure */
7ca647bd 5940 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5941
5942 /* Rx Errors */
7ca647bd 5943 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5944 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5945 netdev->stats.rx_length_errors = hwstats->rlec;
5946 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5947 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5948}
5949
5950/**
d034acf1
AD		 5951 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5952 * @adapter - pointer to the device adapter structure
9a799d71 5953 **/
d034acf1 5954static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
93c52dd0 5955{
93c52dd0
AD		 5956 struct ixgbe_hw *hw = &adapter->hw;
5957 int i;
5958
d034acf1
AD		 5959 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5960 return;
5961
5962 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5963
5964 /* if interface is down do nothing */
5965 if (test_bit(__IXGBE_DOWN, &adapter->state))
5966 return;
5967
5968 /* do nothing if we are not using signature filters */
5969 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5970 return;
5971
5972 adapter->fdir_overflow++;
5973
93c52dd0
AD		 5974 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5975 for (i = 0; i < adapter->num_tx_queues; i++)
5976 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5977 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5978 /* re-enable flow director interrupts */
5979 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5980 } else {
5981 e_err(probe, "failed to finish FDIR re-initialization, "
5982 "ignored adding FDIR ATR filters\n");
5983 }
93c52dd0
AD		 5984}
5985
5986/**
5987 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5988 * @adapter - pointer to the device adapter structure
5989 *
5990 * This function serves two purposes. First it strobes the interrupt lines
5991 * in order to make certain interrupts are occuring. Secondly it sets the
5992 * bits needed to check for TX hangs. As a result we should immediately
5993 * determine if a hang has occured.
5994 */
5995static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5996{
cf8280ee 5997 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5998 u64 eics = 0;
5999 int i;
cf8280ee 6000
93c52dd0
AD		 6001 /* If we're down or resetting, just bail */
6002 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6003 test_bit(__IXGBE_RESETTING, &adapter->state))
6004 return;
22d5a71b 6005
93c52dd0
AD		 6006 /* Force detection of hung controller */
6007 if (netif_carrier_ok(adapter->netdev)) {
6008 for (i = 0; i < adapter->num_tx_queues; i++)
6009 set_check_for_tx_hang(adapter->tx_ring[i]);
6010 }
22d5a71b 6011
fe49f04a
AD		 6012 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6013 /*
6014 * for legacy and MSI interrupts don't set any bits
6015 * that are enabled for EIAM, because this operation
6016 * would set *both* EIMS and EICS for any bit in EIAM
6017 */
6018 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6019 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6020 } else {
6021 /* get one bit for every active tx/rx interrupt vector */
6022 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6023 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6024 if (qv->rxr_count || qv->txr_count)
6025 eics |= ((u64)1 << i);
6026 }
cf8280ee 6027 }
9a799d71 6028
93c52dd0 6029 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6030 ixgbe_irq_rearm_queues(adapter, eics);
6031
cf8280ee
JB		 6032}
6033
c4cf55e5 6034/**
93c52dd0
AD		 6035 * ixgbe_watchdog_update_link - update the link status
6036 * @adapter - pointer to the device adapter structure
6037 * @link_speed - pointer to a u32 to store the link_speed
c4cf55e5 6038 **/
93c52dd0 6039static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
c4cf55e5 6040{
c4cf55e5 6041 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6042 u32 link_speed = adapter->link_speed;
6043 bool link_up = adapter->link_up;
c4cf55e5
PWJ		 6044 int i;
6045
93c52dd0
AD		 6046 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6047 return;
6048
6049 if (hw->mac.ops.check_link) {
6050 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6051 } else {
93c52dd0
AD		 6052 /* always assume link is up, if no check link function */
6053 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6054 link_up = true;
c4cf55e5 6055 }
93c52dd0
AD		 6056 if (link_up) {
6057 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6058 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6059 hw->mac.ops.fc_enable(hw, i);
6060 } else {
6061 hw->mac.ops.fc_enable(hw, 0);
6062 }
6063 }
6064
6065 if (link_up ||
6066 time_after(jiffies, (adapter->link_check_timeout +
6067 IXGBE_TRY_LINK_TIMEOUT))) {
6068 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6069 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6070 IXGBE_WRITE_FLUSH(hw);
6071 }
6072
6073 adapter->link_up = link_up;
6074 adapter->link_speed = link_speed;
c4cf55e5
PWJ		 6075}
6076
93c52dd0
AD		 6077/**
6078 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6079 * print link up message
6080 * @adapter - pointer to the device adapter structure
6081 **/
6082static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
a985b6c3 6083{
93c52dd0
AD		 6084 struct net_device *netdev = adapter->netdev;
6085 struct ixgbe_hw *hw = &adapter->hw;
6086 u32 link_speed = adapter->link_speed;
6087 bool flow_rx, flow_tx;
a985b6c3 6088
93c52dd0
AD		 6089 /* only continue if link was previously down */
6090 if (netif_carrier_ok(netdev))
a985b6c3
GR		 6091 return;
6092
93c52dd0 6093 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
a985b6c3 6094
93c52dd0
AD		 6095 switch (hw->mac.type) {
6096 case ixgbe_mac_82598EB: {
6097 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6098 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6099 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6100 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6101 }
6102 break;
6103 case ixgbe_mac_X540:
6104 case ixgbe_mac_82599EB: {
6105 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6106 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6107 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6108 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6109 }
6110 break;
6111 default:
6112 flow_tx = false;
6113 flow_rx = false;
6114 break;
6115 }
6116 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6117 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6118 "10 Gbps" :
6119 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6120 "1 Gbps" :
6121 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6122 "100 Mbps" :
6123 "unknown speed"))),
6124 ((flow_rx && flow_tx) ? "RX/TX" :
6125 (flow_rx ? "RX" :
6126 (flow_tx ? "TX" : "None"))));
a985b6c3 6127
93c52dd0
AD		 6128 netif_carrier_on(netdev);
6129#ifdef HAVE_IPLINK_VF_CONFIG
6130 ixgbe_check_vf_rate_limit(adapter);
6131#endif /* HAVE_IPLINK_VF_CONFIG */
a985b6c3
GR		 6132}
6133
cf8280ee 6134/**
93c52dd0
AD		 6135 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6136 * print link down message
6137 * @adapter - pointer to the adapter structure
cf8280ee 6138 **/
93c52dd0 6139static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
cf8280ee 6140{
cf8280ee
JB		 6141 struct net_device *netdev = adapter->netdev;
6142 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6143
93c52dd0
AD		 6144 adapter->link_up = false;
6145 adapter->link_speed = 0;
cf8280ee 6146
93c52dd0
AD		 6147 /* only continue if link was up previously */
6148 if (!netif_carrier_ok(netdev))
6149 return;
264857b8 6150
93c52dd0
AD		 6151 /* poll for SFP+ cable when link is down */
6152 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6153 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6154
93c52dd0
AD		 6155 e_info(drv, "NIC Link is Down\n");
6156 netif_carrier_off(netdev);
6157}
e8e26350 6158
93c52dd0
AD		 6159/**
6160 * ixgbe_watchdog_flush_tx - flush queues on link down
6161 * @adapter - pointer to the device adapter structure
6162 **/
6163static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6164{
6165 int i;
6166 int some_tx_pending = 0;
9a799d71 6167
93c52dd0 6168 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6169 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6170 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6171 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6172 some_tx_pending = 1;
6173 break;
6174 }
6175 }
6176
6177 if (some_tx_pending) {
6178 /* We've lost link, so the controller stops DMA,
6179 * but we've got queued Tx work that's never going
6180 * to get done, so reset controller to flush Tx.
6181 * (Do the reset outside of interrupt context).
6182 */
c83c6cbd 6183 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda
NS		 6184 }
6185 }
93c52dd0
AD		 6186}
6187
6188static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6189{
6190 u32 ssvpc;
6191
6192 /* Do not perform spoof check for 82598 */
6193 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6194 return;
6195
6196 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6197
6198 /*
6199 * ssvpc register is cleared on read, if zero then no
6200 * spoofed packets in the last interval.
6201 */
6202 if (!ssvpc)
6203 return;
6204
6205 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6206}
6207
6208/**
6209 * ixgbe_watchdog_subtask - check and bring link up
6210 * @adapter - pointer to the device adapter structure
6211 **/
6212static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6213{
6214 /* if interface is down do nothing */
6215 if (test_bit(__IXGBE_DOWN, &adapter->state))
6216 return;
6217
6218 ixgbe_watchdog_update_link(adapter);
6219
6220 if (adapter->link_up)
6221 ixgbe_watchdog_link_is_up(adapter);
6222 else
6223 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6224
a985b6c3 6225 ixgbe_spoof_check(adapter);
9a799d71 6226 ixgbe_update_stats(adapter);
93c52dd0
AD		 6227
6228 ixgbe_watchdog_flush_tx(adapter);
9a799d71
AK		 6229}
6230
7086400d
AD		 6231/**
6232 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6233 * @adapter - the ixgbe adapter structure
6234 **/
6235static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6236{
6237 struct ixgbe_hw *hw = &adapter->hw;
6238 s32 err;
6239
6240 /* not searching for SFP so there is nothing to do here */
6241 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6242 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6243 return;
6244
6245 /* someone else is in init, wait until next service event */
6246 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6247 return;
6248
6249 err = hw->phy.ops.identify_sfp(hw);
6250 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6251 goto sfp_out;
6252
6253 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6254 /* If no cable is present, then we need to reset
6255 * the next time we find a good cable. */
6256 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6257 }
6258
6259 /* exit on error */
6260 if (err)
6261 goto sfp_out;
6262
6263 /* exit if reset not needed */
6264 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6265 goto sfp_out;
6266
6267 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6268
6269 /*
6270 * A module may be identified correctly, but the EEPROM may not have
6271 * support for that module. setup_sfp() will fail in that case, so
6272 * we should not allow that module to load.
6273 */
6274 if (hw->mac.type == ixgbe_mac_82598EB)
6275 err = hw->phy.ops.reset(hw);
6276 else
6277 err = hw->mac.ops.setup_sfp(hw);
6278
6279 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6280 goto sfp_out;
6281
6282 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6283 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6284
6285sfp_out:
6286 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6287
6288 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6289 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6290 e_dev_err("failed to initialize because an unsupported "
6291 "SFP+ module type was detected.\n");
6292 e_dev_err("Reload the driver after installing a "
6293 "supported module.\n");
6294 unregister_netdev(adapter->netdev);
6295 }
6296}
6297
6298/**
6299 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6300 * @adapter - the ixgbe adapter structure
6301 **/
6302static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6303{
6304 struct ixgbe_hw *hw = &adapter->hw;
6305 u32 autoneg;
6306 bool negotiation;
6307
6308 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6309 return;
6310
6311 /* someone else is in init, wait until next service event */
6312 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6313 return;
6314
6315 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6316
6317 autoneg = hw->phy.autoneg_advertised;
6318 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6319 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6320 hw->mac.autotry_restart = false;
6321 if (hw->mac.ops.setup_link)
6322 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6323
6324 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6325 adapter->link_check_timeout = jiffies;
6326 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6327}
6328
6329/**
6330 * ixgbe_service_timer - Timer Call-back
6331 * @data: pointer to adapter cast into an unsigned long
6332 **/
6333static void ixgbe_service_timer(unsigned long data)
6334{
6335 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6336 unsigned long next_event_offset;
6337
6338 /* poll faster when waiting for link */
6339 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6340 next_event_offset = HZ / 10;
6341 else
6342 next_event_offset = HZ * 2;
6343
6344 /* Reset the timer */
6345 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6346
6347 ixgbe_service_event_schedule(adapter);
6348}
6349
c83c6cbd
AD		 6350static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6351{
6352 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6353 return;
6354
6355 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6356
6357 /* If we're already down or resetting, just bail */
6358 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6359 test_bit(__IXGBE_RESETTING, &adapter->state))
6360 return;
6361
6362 ixgbe_dump(adapter);
6363 netdev_err(adapter->netdev, "Reset adapter\n");
6364 adapter->tx_timeout_count++;
6365
6366 ixgbe_reinit_locked(adapter);
6367}
6368
7086400d
AD		 6369/**
6370 * ixgbe_service_task - manages and runs subtasks
6371 * @work: pointer to work_struct containing our data
6372 **/
6373static void ixgbe_service_task(struct work_struct *work)
6374{
6375 struct ixgbe_adapter *adapter = container_of(work,
6376 struct ixgbe_adapter,
6377 service_task);
6378
c83c6cbd 6379 ixgbe_reset_subtask(adapter);
7086400d
AD		 6380 ixgbe_sfp_detection_subtask(adapter);
6381 ixgbe_sfp_link_config_subtask(adapter);
93c52dd0 6382 ixgbe_watchdog_subtask(adapter);
d034acf1 6383 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6384 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6385
6386 ixgbe_service_event_complete(adapter);
6387}
6388
9a799d71 6389static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696 6390 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5e09a105 6391 u32 tx_flags, u8 *hdr_len, __be16 protocol)
9a799d71
AK		 6392{
6393 struct ixgbe_adv_tx_context_desc *context_desc;
6394 unsigned int i;
6395 int err;
6396 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 6397 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6398 u32 mss_l4len_idx, l4len;
9a799d71
AK		 6399
6400 if (skb_is_gso(skb)) {
6401 if (skb_header_cloned(skb)) {
6402 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6403 if (err)
6404 return err;
6405 }
6406 l4len = tcp_hdrlen(skb);
6407 *hdr_len += l4len;
6408
5e09a105 6409 if (protocol == htons(ETH_P_IP)) {
9a799d71
AK		 6410 struct iphdr *iph = ip_hdr(skb);
6411 iph->tot_len = 0;
6412 iph->check = 0;
6413 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 6414 iph->daddr, 0,
6415 IPPROTO_TCP,
6416 0);
8e1e8a47 6417 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 6418 ipv6_hdr(skb)->payload_len = 0;
6419 tcp_hdr(skb)->check =
6420 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 6421 &ipv6_hdr(skb)->daddr,
6422 0, IPPROTO_TCP, 0);
9a799d71
AK		 6423 }
6424
6425 i = tx_ring->next_to_use;
6426
6427 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6428 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6429
6430 /* VLAN MACLEN IPLEN */
6431 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6432 vlan_macip_lens |=
6433 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6434 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 6435 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6436 *hdr_len += skb_network_offset(skb);
6437 vlan_macip_lens |=
6438 (skb_transport_header(skb) - skb_network_header(skb));
6439 *hdr_len +=
6440 (skb_transport_header(skb) - skb_network_header(skb));
6441 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6442 context_desc->seqnum_seed = 0;
6443
6444 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 6445 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 6446 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6447
5e09a105 6448 if (protocol == htons(ETH_P_IP))
9a799d71
AK		 6449 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6450 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6451 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6452
6453 /* MSS L4LEN IDX */
9f8cdf4f 6454 mss_l4len_idx =
9a799d71
AK		 6455 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6456 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 6457 /* use index 1 for TSO */
6458 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6459 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6460
6461 tx_buffer_info->time_stamp = jiffies;
6462 tx_buffer_info->next_to_watch = i;
6463
6464 i++;
6465 if (i == tx_ring->count)
6466 i = 0;
6467 tx_ring->next_to_use = i;
6468
6469 return true;
6470 }
6471 return false;
6472}
6473
5e09a105
HZ		 6474static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6475 __be16 protocol)
7ca647bd
JP		 6476{
6477 u32 rtn = 0;
7ca647bd
JP		 6478
6479 switch (protocol) {
6480 case cpu_to_be16(ETH_P_IP):
6481 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6482 switch (ip_hdr(skb)->protocol) {
6483 case IPPROTO_TCP:
6484 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6485 break;
6486 case IPPROTO_SCTP:
6487 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6488 break;
6489 }
6490 break;
6491 case cpu_to_be16(ETH_P_IPV6):
6492 /* XXX what about other V6 headers?? */
6493 switch (ipv6_hdr(skb)->nexthdr) {
6494 case IPPROTO_TCP:
6495 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6496 break;
6497 case IPPROTO_SCTP:
6498 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6499 break;
6500 }
6501 break;
6502 default:
6503 if (unlikely(net_ratelimit()))
6504 e_warn(probe, "partial checksum but proto=%x!\n",
5e09a105 6505 protocol);
7ca647bd
JP		 6506 break;
6507 }
6508
6509 return rtn;
6510}
6511
9a799d71 6512static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696 6513 struct ixgbe_ring *tx_ring,
5e09a105
HZ		 6514 struct sk_buff *skb, u32 tx_flags,
6515 __be16 protocol)
9a799d71
AK		 6516{
6517 struct ixgbe_adv_tx_context_desc *context_desc;
6518 unsigned int i;
6519 struct ixgbe_tx_buffer *tx_buffer_info;
6520 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6521
6522 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6523 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6524 i = tx_ring->next_to_use;
6525 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6526 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6527
6528 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6529 vlan_macip_lens |=
6530 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6531 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 6532 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6533 if (skb->ip_summed == CHECKSUM_PARTIAL)
6534 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 6535 skb_network_header(skb));
9a799d71
AK		 6536
6537 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6538 context_desc->seqnum_seed = 0;
6539
6540 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 6541 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6542
7ca647bd 6543 if (skb->ip_summed == CHECKSUM_PARTIAL)
5e09a105 6544 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
9a799d71
AK		 6545
6546 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 6547 /* use index zero for tx checksum offload */
9a799d71
AK		 6548 context_desc->mss_l4len_idx = 0;
6549
6550 tx_buffer_info->time_stamp = jiffies;
6551 tx_buffer_info->next_to_watch = i;
9f8cdf4f 6552
9a799d71
AK		 6553 i++;
6554 if (i == tx_ring->count)
6555 i = 0;
6556 tx_ring->next_to_use = i;
6557
6558 return true;
6559 }
9f8cdf4f 6560
9a799d71
AK		 6561 return false;
6562}
6563
6564static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6565 struct ixgbe_ring *tx_ring,
6566 struct sk_buff *skb, u32 tx_flags,
8ad494b0 6567 unsigned int first, const u8 hdr_len)
9a799d71 6568{
b6ec895e 6569 struct device *dev = tx_ring->dev;
9a799d71 6570 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6571 unsigned int len;
6572 unsigned int total = skb->len;
9a799d71
AK		 6573 unsigned int offset = 0, size, count = 0, i;
6574 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6575 unsigned int f;
8ad494b0
AD		 6576 unsigned int bytecount = skb->len;
6577 u16 gso_segs = 1;
9a799d71
AK		 6578
6579 i = tx_ring->next_to_use;
6580
eacd73f7
YZ		 6581 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6582 /* excluding fcoe_crc_eof for FCoE */
6583 total -= sizeof(struct fcoe_crc_eof);
6584
6585 len = min(skb_headlen(skb), total);
9a799d71
AK		 6586 while (len) {
6587 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6588 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6589
6590 tx_buffer_info->length = size;
e5a43549 6591 tx_buffer_info->mapped_as_page = false;
b6ec895e 6592 tx_buffer_info->dma = dma_map_single(dev,
e5a43549 6593 skb->data + offset,
1b507730 6594 size, DMA_TO_DEVICE);
b6ec895e 6595 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6596 goto dma_error;
9a799d71
AK		 6597 tx_buffer_info->time_stamp = jiffies;
6598 tx_buffer_info->next_to_watch = i;
6599
6600 len -= size;
eacd73f7 6601 total -= size;
9a799d71
AK		 6602 offset += size;
6603 count++;
44df32c5
AD		 6604
6605 if (len) {
6606 i++;
6607 if (i == tx_ring->count)
6608 i = 0;
6609 }
9a799d71
AK		 6610 }
6611
6612 for (f = 0; f < nr_frags; f++) {
6613 struct skb_frag_struct *frag;
6614
6615 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6616 len = min((unsigned int)frag->size, total);
e5a43549 6617 offset = frag->page_offset;
9a799d71
AK		 6618
6619 while (len) {
44df32c5
AD		 6620 i++;
6621 if (i == tx_ring->count)
6622 i = 0;
6623
9a799d71
AK		 6624 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6625 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6626
6627 tx_buffer_info->length = size;
b6ec895e 6628 tx_buffer_info->dma = dma_map_page(dev,
e5a43549
AD		 6629 frag->page,
6630 offset, size,
1b507730 6631 DMA_TO_DEVICE);
e5a43549 6632 tx_buffer_info->mapped_as_page = true;
b6ec895e 6633 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6634 goto dma_error;
9a799d71
AK		 6635 tx_buffer_info->time_stamp = jiffies;
6636 tx_buffer_info->next_to_watch = i;
6637
6638 len -= size;
eacd73f7 6639 total -= size;
9a799d71
AK		 6640 offset += size;
6641 count++;
9a799d71 6642 }
eacd73f7
YZ		 6643 if (total == 0)
6644 break;
9a799d71 6645 }
44df32c5 6646
8ad494b0
AD		 6647 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6648 gso_segs = skb_shinfo(skb)->gso_segs;
6649#ifdef IXGBE_FCOE
6650 /* adjust for FCoE Sequence Offload */
6651 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6652 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6653 skb_shinfo(skb)->gso_size);
6654#endif /* IXGBE_FCOE */
6655 bytecount += (gso_segs - 1) * hdr_len;
6656
6657 /* multiply data chunks by size of headers */
6658 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6659 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
9a799d71
AK		 6660 tx_ring->tx_buffer_info[i].skb = skb;
6661 tx_ring->tx_buffer_info[first].next_to_watch = i;
6662
e5a43549
AD		 6663 return count;
6664
6665dma_error:
849c4542 6666 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6667
6668 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6669 tx_buffer_info->dma = 0;
6670 tx_buffer_info->time_stamp = 0;
6671 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6672 if (count)
6673 count--;
e5a43549
AD		 6674
6675 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6676 while (count--) {
e8e9f696 6677 if (i == 0)
e5a43549 6678 i += tx_ring->count;
c1fa347f 6679 i--;
e5a43549 6680 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 6681 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
e5a43549
AD		 6682 }
6683
e44d38e1 6684 return 0;
9a799d71
AK		 6685}
6686
84ea2591 6687static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
e8e9f696 6688 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6689{
6690 union ixgbe_adv_tx_desc *tx_desc = NULL;
6691 struct ixgbe_tx_buffer *tx_buffer_info;
6692 u32 olinfo_status = 0, cmd_type_len = 0;
6693 unsigned int i;
6694 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6695
6696 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6697
6698 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6699
6700 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6701 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6702
6703 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6704 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6705
6706 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6707 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6708
4eeae6fd
PW		 6709 /* use index 1 context for tso */
6710 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6711 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6712 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6713 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6714
6715 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6716 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6717 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6718
eacd73f7
YZ		 6719 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6720 olinfo_status |= IXGBE_ADVTXD_CC;
6721 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6722 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6723 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6724 }
6725
9a799d71
AK		 6726 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6727
6728 i = tx_ring->next_to_use;
6729 while (count--) {
6730 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6731 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6732 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6733 tx_desc->read.cmd_type_len =
e8e9f696 6734 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6735 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6736 i++;
6737 if (i == tx_ring->count)
6738 i = 0;
6739 }
6740
6741 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6742
6743 /*
6744 * Force memory writes to complete before letting h/w
6745 * know there are new descriptors to fetch. (Only
6746 * applicable for weak-ordered memory model archs,
6747 * such as IA-64).
6748 */
6749 wmb();
6750
6751 tx_ring->next_to_use = i;
84ea2591 6752 writel(i, tx_ring->tail);
9a799d71
AK		 6753}
6754
69830529
AD		 6755static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6756 u32 tx_flags, __be16 protocol)
6757{
6758 struct ixgbe_q_vector *q_vector = ring->q_vector;
6759 union ixgbe_atr_hash_dword input = { .dword = 0 };
6760 union ixgbe_atr_hash_dword common = { .dword = 0 };
6761 union {
6762 unsigned char *network;
6763 struct iphdr *ipv4;
6764 struct ipv6hdr *ipv6;
6765 } hdr;
ee9e0f0b 6766 struct tcphdr *th;
905e4a41 6767 __be16 vlan_id;
c4cf55e5 6768
69830529
AD		 6769 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6770 if (!q_vector)
6771 return;
6772
6773 /* do nothing if sampling is disabled */
6774 if (!ring->atr_sample_rate)
d3ead241 6775 return;
c4cf55e5 6776
69830529 6777 ring->atr_count++;
c4cf55e5 6778
69830529
AD		 6779 /* snag network header to get L4 type and address */
6780 hdr.network = skb_network_header(skb);
6781
6782 /* Currently only IPv4/IPv6 with TCP is supported */
6783 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6784 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6785 (protocol != __constant_htons(ETH_P_IP) ||
6786 hdr.ipv4->protocol != IPPROTO_TCP))
6787 return;
ee9e0f0b
AD		 6788
6789 th = tcp_hdr(skb);
c4cf55e5 6790
69830529
AD		 6791 /* skip this packet since the socket is closing */
6792 if (th->fin)
6793 return;
6794
6795 /* sample on all syn packets or once every atr sample count */
6796 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6797 return;
6798
6799 /* reset sample count */
6800 ring->atr_count = 0;
6801
6802 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6803
6804 /*
6805 * src and dst are inverted, think how the receiver sees them
6806 *
6807 * The input is broken into two sections, a non-compressed section
6808 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6809 * is XORed together and stored in the compressed dword.
6810 */
6811 input.formatted.vlan_id = vlan_id;
6812
6813 /*
6814 * since src port and flex bytes occupy the same word XOR them together
6815 * and write the value to source port portion of compressed dword
6816 */
6817 if (vlan_id)
6818 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6819 else
6820 common.port.src ^= th->dest ^ protocol;
6821 common.port.dst ^= th->source;
6822
6823 if (protocol == __constant_htons(ETH_P_IP)) {
6824 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6825 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6826 } else {
6827 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6828 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6829 hdr.ipv6->saddr.s6_addr32[1] ^
6830 hdr.ipv6->saddr.s6_addr32[2] ^
6831 hdr.ipv6->saddr.s6_addr32[3] ^
6832 hdr.ipv6->daddr.s6_addr32[0] ^
6833 hdr.ipv6->daddr.s6_addr32[1] ^
6834 hdr.ipv6->daddr.s6_addr32[2] ^
6835 hdr.ipv6->daddr.s6_addr32[3];
6836 }
c4cf55e5
PWJ		 6837
6838 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6839 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6840 input, common, ring->queue_index);
c4cf55e5
PWJ		 6841}
6842
fc77dc3c 6843static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60 6844{
fc77dc3c 6845 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6846 /* Herbert's original patch had:
6847 * smp_mb__after_netif_stop_queue();
6848 * but since that doesn't exist yet, just open code it. */
6849 smp_mb();
6850
6851 /* We need to check again in a case another CPU has just
6852 * made room available. */
6853 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6854 return -EBUSY;
6855
6856 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6857 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6858 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6859 return 0;
6860}
6861
fc77dc3c 6862static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6863{
6864 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6865 return 0;
fc77dc3c 6866 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6867}
6868
09a3b1f8
SH		 6869static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6870{
6871 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6872 int txq = smp_processor_id();
56075a98 6873#ifdef IXGBE_FCOE
5e09a105
HZ		 6874 __be16 protocol;
6875
6876 protocol = vlan_get_protocol(skb);
6877
e5b64635
JF		 6878 if (((protocol == htons(ETH_P_FCOE)) ||
6879 (protocol == htons(ETH_P_FIP))) &&
6880 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6881 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6882 txq += adapter->ring_feature[RING_F_FCOE].mask;
6883 return txq;
56075a98
JF		 6884 }
6885#endif
6886
fdd3d631
KK		 6887 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6888 while (unlikely(txq >= dev->real_num_tx_queues))
6889 txq -= dev->real_num_tx_queues;
5f715823 6890 return txq;
fdd3d631 6891 }
c4cf55e5 6892
09a3b1f8
SH		 6893 return skb_tx_hash(dev, skb);
6894}
6895
fc77dc3c 6896netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6897 struct ixgbe_adapter *adapter,
6898 struct ixgbe_ring *tx_ring)
9a799d71 6899{
9a799d71
AK		 6900 unsigned int first;
6901 unsigned int tx_flags = 0;
30eba97a 6902 u8 hdr_len = 0;
5f715823 6903 int tso;
9a799d71
AK		 6904 int count = 0;
6905 unsigned int f;
5e09a105
HZ		 6906 __be16 protocol;
6907
6908 protocol = vlan_get_protocol(skb);
9f8cdf4f 6909
eab6d18d 6910 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6911 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6912 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6913 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
e5b64635 6914 tx_flags |= tx_ring->dcb_tc << 13;
2f90b865
AD		 6915 }
6916 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6917 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6918 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6919 skb->priority != TC_PRIO_CONTROL) {
e5b64635 6920 tx_flags |= tx_ring->dcb_tc << 13;
2ea186ae
JF		 6921 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6922 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6923 }
eacd73f7 6924
09ad1cc0 6925#ifdef IXGBE_FCOE
56075a98
JF		 6926 /* for FCoE with DCB, we force the priority to what
6927 * was specified by the switch */
6928 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
e5b64635
JF		 6929 (protocol == htons(ETH_P_FCOE)))
6930 tx_flags |= IXGBE_TX_FLAGS_FCOE;
ca77cd59
RL		 6931#endif
6932
eacd73f7 6933 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6934 if (skb_is_gso(skb) ||
6935 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6936 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6937 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6938 count++;
6939
9f8cdf4f
JB		 6940 count += TXD_USE_COUNT(skb_headlen(skb));
6941 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6942 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6943
fc77dc3c 6944 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
5b7da515 6945 tx_ring->tx_stats.tx_busy++;
9a799d71
AK		 6946 return NETDEV_TX_BUSY;
6947 }
9a799d71 6948
9a799d71 6949 first = tx_ring->next_to_use;
eacd73f7
YZ		 6950 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6951#ifdef IXGBE_FCOE
6952 /* setup tx offload for FCoE */
6953 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6954 if (tso < 0) {
6955 dev_kfree_skb_any(skb);
6956 return NETDEV_TX_OK;
6957 }
6958 if (tso)
6959 tx_flags |= IXGBE_TX_FLAGS_FSO;
6960#endif /* IXGBE_FCOE */
6961 } else {
5e09a105 6962 if (protocol == htons(ETH_P_IP))
eacd73f7 6963 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5e09a105
HZ		 6964 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6965 protocol);
eacd73f7
YZ		 6966 if (tso < 0) {
6967 dev_kfree_skb_any(skb);
6968 return NETDEV_TX_OK;
6969 }
9a799d71 6970
eacd73f7
YZ		 6971 if (tso)
6972 tx_flags |= IXGBE_TX_FLAGS_TSO;
5e09a105
HZ		 6973 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6974 protocol) &&
eacd73f7
YZ		 6975 (skb->ip_summed == CHECKSUM_PARTIAL))
6976 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6977 }
9a799d71 6978
8ad494b0 6979 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
44df32c5 6980 if (count) {
c4cf55e5 6981 /* add the ATR filter if ATR is on */
69830529
AD		 6982 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6983 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
84ea2591 6984 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
fc77dc3c 6985 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71 6986
44df32c5
AD		 6987 } else {
6988 dev_kfree_skb_any(skb);
6989 tx_ring->tx_buffer_info[first].time_stamp = 0;
6990 tx_ring->next_to_use = first;
6991 }
9a799d71
AK		 6992
6993 return NETDEV_TX_OK;
6994}
6995
84418e3b
AD		 6996static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6997{
6998 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6999 struct ixgbe_ring *tx_ring;
7000
7001 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 7002 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7003}
7004
9a799d71
AK		 7005/**
7006 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7007 * @netdev: network interface device structure
7008 * @p: pointer to an address structure
7009 *
7010 * Returns 0 on success, negative on failure
7011 **/
7012static int ixgbe_set_mac(struct net_device *netdev, void *p)
7013{
7014 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7015 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7016 struct sockaddr *addr = p;
7017
7018 if (!is_valid_ether_addr(addr->sa_data))
7019 return -EADDRNOTAVAIL;
7020
7021 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7022 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7023
1cdd1ec8
GR		 7024 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
7025 IXGBE_RAH_AV);
9a799d71
AK		 7026
7027 return 0;
7028}
7029
6b73e10d
BH		 7030static int
7031ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7032{
7033 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7034 struct ixgbe_hw *hw = &adapter->hw;
7035 u16 value;
7036 int rc;
7037
7038 if (prtad != hw->phy.mdio.prtad)
7039 return -EINVAL;
7040 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7041 if (!rc)
7042 rc = value;
7043 return rc;
7044}
7045
7046static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7047 u16 addr, u16 value)
7048{
7049 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7050 struct ixgbe_hw *hw = &adapter->hw;
7051
7052 if (prtad != hw->phy.mdio.prtad)
7053 return -EINVAL;
7054 return hw->phy.ops.write_reg(hw, addr, devad, value);
7055}
7056
7057static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7058{
7059 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7060
7061 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7062}
7063
0365e6e4
PW		 7064/**
7065 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7066 * netdev->dev_addrs
0365e6e4
PW		 7067 * @netdev: network interface device structure
7068 *
7069 * Returns non-zero on failure
7070 **/
7071static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7072{
7073 int err = 0;
7074 struct ixgbe_adapter *adapter = netdev_priv(dev);
7075 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7076
7077 if (is_valid_ether_addr(mac->san_addr)) {
7078 rtnl_lock();
7079 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7080 rtnl_unlock();
7081 }
7082 return err;
7083}
7084
7085/**
7086 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7087 * netdev->dev_addrs
0365e6e4
PW		 7088 * @netdev: network interface device structure
7089 *
7090 * Returns non-zero on failure
7091 **/
7092static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7093{
7094 int err = 0;
7095 struct ixgbe_adapter *adapter = netdev_priv(dev);
7096 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7097
7098 if (is_valid_ether_addr(mac->san_addr)) {
7099 rtnl_lock();
7100 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7101 rtnl_unlock();
7102 }
7103 return err;
7104}
7105
9a799d71
AK		 7106#ifdef CONFIG_NET_POLL_CONTROLLER
7107/*
7108 * Polling 'interrupt' - used by things like netconsole to send skbs
7109 * without having to re-enable interrupts. It's not called while
7110 * the interrupt routine is executing.
7111 */
7112static void ixgbe_netpoll(struct net_device *netdev)
7113{
7114 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7115 int i;
9a799d71 7116
1a647bd2
AD		 7117 /* if interface is down do nothing */
7118 if (test_bit(__IXGBE_DOWN, &adapter->state))
7119 return;
7120
9a799d71 7121 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7122 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7123 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7124 for (i = 0; i < num_q_vectors; i++) {
7125 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7126 ixgbe_msix_clean_many(0, q_vector);
7127 }
7128 } else {
7129 ixgbe_intr(adapter->pdev->irq, netdev);
7130 }
9a799d71 7131 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7132}
7133#endif
7134
de1036b1
ED		 7135static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7136 struct rtnl_link_stats64 *stats)
7137{
7138 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7139 int i;
7140
1a51502b 7141 rcu_read_lock();
de1036b1 7142 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7143 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7144 u64 bytes, packets;
7145 unsigned int start;
7146
1a51502b
ED		 7147 if (ring) {
7148 do {
7149 start = u64_stats_fetch_begin_bh(&ring->syncp);
7150 packets = ring->stats.packets;
7151 bytes = ring->stats.bytes;
7152 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7153 stats->rx_packets += packets;
7154 stats->rx_bytes += bytes;
7155 }
de1036b1 7156 }
1ac9ad13
ED		 7157
7158 for (i = 0; i < adapter->num_tx_queues; i++) {
7159 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7160 u64 bytes, packets;
7161 unsigned int start;
7162
7163 if (ring) {
7164 do {
7165 start = u64_stats_fetch_begin_bh(&ring->syncp);
7166 packets = ring->stats.packets;
7167 bytes = ring->stats.bytes;
7168 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7169 stats->tx_packets += packets;
7170 stats->tx_bytes += bytes;
7171 }
7172 }
1a51502b 7173 rcu_read_unlock();
de1036b1
ED		 7174 /* following stats updated by ixgbe_watchdog_task() */
7175 stats->multicast = netdev->stats.multicast;
7176 stats->rx_errors = netdev->stats.rx_errors;
7177 stats->rx_length_errors = netdev->stats.rx_length_errors;
7178 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7179 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7180 return stats;
7181}
7182
7183
0edc3527 7184static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7185 .ndo_open = ixgbe_open,
0edc3527 7186 .ndo_stop = ixgbe_close,
00829823 7187 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7188 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7189 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7190 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7191 .ndo_validate_addr = eth_validate_addr,
7192 .ndo_set_mac_address = ixgbe_set_mac,
7193 .ndo_change_mtu = ixgbe_change_mtu,
7194 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7195 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7196 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7197 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7198 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7199 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7200 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7201 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7202 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3
JF		 7203#ifdef CONFIG_IXGBE_DCB
7204 .ndo_setup_tc = ixgbe_setup_tc,
7205#endif
0edc3527
SH		 7206#ifdef CONFIG_NET_POLL_CONTROLLER
7207 .ndo_poll_controller = ixgbe_netpoll,
7208#endif
332d4a7d
YZ		 7209#ifdef IXGBE_FCOE
7210 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7211 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7212 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7213 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7214 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7215 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7216#endif /* IXGBE_FCOE */
0edc3527
SH		 7217};
7218
1cdd1ec8
GR		 7219static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7220 const struct ixgbe_info *ii)
7221{
7222#ifdef CONFIG_PCI_IOV
7223 struct ixgbe_hw *hw = &adapter->hw;
7224 int err;
a1cbb15c
GR		 7225 int num_vf_macvlans, i;
7226 struct vf_macvlans *mv_list;
1cdd1ec8 7227
3377eba7 7228 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
1cdd1ec8
GR		 7229 return;
7230
7231 /* The 82599 supports up to 64 VFs per physical function
7232 * but this implementation limits allocation to 63 so that
7233 * basic networking resources are still available to the
7234 * physical function
7235 */
7236 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7237 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7238 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7239 if (err) {
396e799c 7240 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 7241 goto err_novfs;
7242 }
a1cbb15c
GR		 7243
7244 num_vf_macvlans = hw->mac.num_rar_entries -
7245 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7246
7247 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7248 sizeof(struct vf_macvlans),
7249 GFP_KERNEL);
7250 if (mv_list) {
7251 /* Initialize list of VF macvlans */
7252 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7253 for (i = 0; i < num_vf_macvlans; i++) {
7254 mv_list->vf = -1;
7255 mv_list->free = true;
7256 mv_list->rar_entry = hw->mac.num_rar_entries -
7257 (i + adapter->num_vfs + 1);
7258 list_add(&mv_list->l, &adapter->vf_mvs.l);
7259 mv_list++;
7260 }
7261 }
7262
1cdd1ec8
GR		 7263 /* If call to enable VFs succeeded then allocate memory
7264 * for per VF control structures.
7265 */
7266 adapter->vfinfo =
7267 kcalloc(adapter->num_vfs,
7268 sizeof(struct vf_data_storage), GFP_KERNEL);
7269 if (adapter->vfinfo) {
7270 /* Now that we're sure SR-IOV is enabled
7271 * and memory allocated set up the mailbox parameters
7272 */
7273 ixgbe_init_mbx_params_pf(hw);
7274 memcpy(&hw->mbx.ops, ii->mbx_ops,
7275 sizeof(hw->mbx.ops));
7276
7277 /* Disable RSC when in SR-IOV mode */
7278 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7279 IXGBE_FLAG2_RSC_ENABLED);
7280 return;
7281 }
7282
7283 /* Oh oh */
396e799c
ET		 7284 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7285 "SRIOV disabled\n");
1cdd1ec8
GR		 7286 pci_disable_sriov(adapter->pdev);
7287
7288err_novfs:
7289 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7290 adapter->num_vfs = 0;
7291#endif /* CONFIG_PCI_IOV */
7292}
7293
9a799d71
AK		 7294/**
7295 * ixgbe_probe - Device Initialization Routine
7296 * @pdev: PCI device information struct
7297 * @ent: entry in ixgbe_pci_tbl
7298 *
7299 * Returns 0 on success, negative on failure
7300 *
7301 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7302 * The OS initialization, configuring of the adapter private structure,
7303 * and a hardware reset occur.
7304 **/
7305static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7306 const struct pci_device_id *ent)
9a799d71
AK		 7307{
7308 struct net_device *netdev;
7309 struct ixgbe_adapter *adapter = NULL;
7310 struct ixgbe_hw *hw;
7311 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7312 static int cards_found;
7313 int i, err, pci_using_dac;
289700db 7314 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7315 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7316#ifdef IXGBE_FCOE
7317 u16 device_caps;
7318#endif
289700db 7319 u32 eec;
9a799d71 7320
bded64a7
AG		 7321 /* Catch broken hardware that put the wrong VF device ID in
7322 * the PCIe SR-IOV capability.
7323 */
7324 if (pdev->is_virtfn) {
7325 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7326 pci_name(pdev), pdev->vendor, pdev->device);
7327 return -EINVAL;
7328 }
7329
9ce77666 7330 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7331 if (err)
7332 return err;
7333
1b507730
NN		 7334 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7335 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7336 pci_using_dac = 1;
7337 } else {
1b507730 7338 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7339 if (err) {
1b507730
NN		 7340 err = dma_set_coherent_mask(&pdev->dev,
7341 DMA_BIT_MASK(32));
9a799d71 7342 if (err) {
b8bc0421
DC		 7343 dev_err(&pdev->dev,
7344 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7345 goto err_dma;
7346 }
7347 }
7348 pci_using_dac = 0;
7349 }
7350
9ce77666 7351 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7352 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7353 if (err) {
b8bc0421
DC		 7354 dev_err(&pdev->dev,
7355 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7356 goto err_pci_reg;
7357 }
7358
19d5afd4 7359 pci_enable_pcie_error_reporting(pdev);
6fabd715 7360
9a799d71 7361 pci_set_master(pdev);
fb3b27bc 7362 pci_save_state(pdev);
9a799d71 7363
c85a2618
JF		 7364 if (ii->mac == ixgbe_mac_82598EB)
7365 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7366 else
7367 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7368
e5b64635 7369#if defined(CONFIG_DCB)
c85a2618 7370 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
e5b64635 7371#elif defined(IXGBE_FCOE)
c85a2618
JF		 7372 indices += min_t(unsigned int, num_possible_cpus(),
7373 IXGBE_MAX_FCOE_INDICES);
7374#endif
c85a2618 7375 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7376 if (!netdev) {
7377 err = -ENOMEM;
7378 goto err_alloc_etherdev;
7379 }
7380
9a799d71
AK		 7381 SET_NETDEV_DEV(netdev, &pdev->dev);
7382
9a799d71 7383 adapter = netdev_priv(netdev);
c60fbb00 7384 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7385
7386 adapter->netdev = netdev;
7387 adapter->pdev = pdev;
7388 hw = &adapter->hw;
7389 hw->back = adapter;
7390 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7391
05857980 7392 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7393 pci_resource_len(pdev, 0));
9a799d71
AK		 7394 if (!hw->hw_addr) {
7395 err = -EIO;
7396 goto err_ioremap;
7397 }
7398
7399 for (i = 1; i <= 5; i++) {
7400 if (pci_resource_len(pdev, i) == 0)
7401 continue;
7402 }
7403
0edc3527 7404 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7405 ixgbe_set_ethtool_ops(netdev);
9a799d71 7406 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7407 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7408
9a799d71
AK		 7409 adapter->bd_number = cards_found;
7410
9a799d71
AK		 7411 /* Setup hw api */
7412 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7413 hw->mac.type = ii->mac;
9a799d71 7414
c44ade9e
JB		 7415 /* EEPROM */
7416 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7417 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7418 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7419 if (!(eec & (1 << 8)))
7420 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7421
7422 /* PHY */
7423 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7424 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7425 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7426 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7427 hw->phy.mdio.mmds = 0;
7428 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7429 hw->phy.mdio.dev = netdev;
7430 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7431 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7432
8ca783ab 7433 ii->get_invariants(hw);
9a799d71
AK		 7434
7435 /* setup the private structure */
7436 err = ixgbe_sw_init(adapter);
7437 if (err)
7438 goto err_sw_init;
7439
e86bff0e 7440 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7441 switch (adapter->hw.mac.type) {
7442 case ixgbe_mac_82599EB:
7443 case ixgbe_mac_X540:
e86bff0e 7444 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7445 break;
7446 default:
7447 break;
7448 }
e86bff0e 7449
bf069c97
DS		 7450 /*
7451 * If there is a fan on this device and it has failed log the
7452 * failure.
7453 */
7454 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7455 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7456 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7457 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7458 }
7459
c44ade9e 7460 /* reset_hw fills in the perm_addr as well */
119fc60a 7461 hw->phy.reset_if_overtemp = true;
c44ade9e 7462 err = hw->mac.ops.reset_hw(hw);
119fc60a 7463 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7464 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7465 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7466 err = 0;
7467 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7468 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7469 "module type was detected.\n");
7470 e_dev_err("Reload the driver after installing a supported "
7471 "module.\n");
04f165ef
PW		 7472 goto err_sw_init;
7473 } else if (err) {
849c4542 7474 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7475 goto err_sw_init;
7476 }
7477
1cdd1ec8
GR		 7478 ixgbe_probe_vf(adapter, ii);
7479
396e799c 7480 netdev->features = NETIF_F_SG |
e8e9f696
JP		 7481 NETIF_F_IP_CSUM |
7482 NETIF_F_HW_VLAN_TX |
7483 NETIF_F_HW_VLAN_RX |
7484 NETIF_F_HW_VLAN_FILTER;
9a799d71 7485
e9990a9c 7486 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 7487 netdev->features |= NETIF_F_TSO;
9a799d71 7488 netdev->features |= NETIF_F_TSO6;
78b6f4ce 7489 netdev->features |= NETIF_F_GRO;
67a74ee2 7490 netdev->features |= NETIF_F_RXHASH;
ad31c402 7491
58be7666
DS		 7492 switch (adapter->hw.mac.type) {
7493 case ixgbe_mac_82599EB:
7494 case ixgbe_mac_X540:
45a5ead0 7495 netdev->features |= NETIF_F_SCTP_CSUM;
58be7666
DS		 7496 break;
7497 default:
7498 break;
7499 }
45a5ead0 7500
ad31c402
JK		 7501 netdev->vlan_features |= NETIF_F_TSO;
7502 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7503 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7504 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7505 netdev->vlan_features |= NETIF_F_SG;
7506
1cdd1ec8
GR		 7507 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7508 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7509 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7510
7a6b6f51 7511#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7512 netdev->dcbnl_ops = &dcbnl_ops;
7513#endif
7514
eacd73f7 7515#ifdef IXGBE_FCOE
0d551589 7516 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7517 if (hw->mac.ops.get_device_caps) {
7518 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7519 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7520 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7521 }
7522 }
5e09d7f6
YZ		 7523 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7524 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7525 netdev->vlan_features |= NETIF_F_FSO;
7526 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7527 }
eacd73f7 7528#endif /* IXGBE_FCOE */
7b872a55 7529 if (pci_using_dac) {
9a799d71 7530 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7531 netdev->vlan_features |= NETIF_F_HIGHDMA;
7532 }
9a799d71 7533
0c19d6af 7534 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7535 netdev->features |= NETIF_F_LRO;
7536
9a799d71 7537 /* make sure the EEPROM is good */
c44ade9e 7538 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7539 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7540 err = -EIO;
7541 goto err_eeprom;
7542 }
7543
7544 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7545 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7546
c44ade9e 7547 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7548 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7549 err = -EIO;
7550 goto err_eeprom;
7551 }
7552
c6ecf39a
DS		 7553 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7554 if (hw->mac.ops.disable_tx_laser &&
7555 ((hw->phy.multispeed_fiber) ||
9f911707 7556 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 7557 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 7558 hw->mac.ops.disable_tx_laser(hw);
7559
7086400d
AD		 7560 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7561 (unsigned long) adapter);
9a799d71 7562
7086400d
AD		 7563 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7564 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7565
021230d4
AV		 7566 err = ixgbe_init_interrupt_scheme(adapter);
7567 if (err)
7568 goto err_sw_init;
9a799d71 7569
67a74ee2
ET		 7570 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7571 netdev->features &= ~NETIF_F_RXHASH;
7572
e8e26350 7573 switch (pdev->device) {
0b077fea
DS		 7574 case IXGBE_DEV_ID_82599_SFP:
7575 /* Only this subdevice supports WOL */
7576 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7577 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7578 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7579 break;
50d6c681
AD		 7580 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7581 /* All except this subdevice support WOL */
0b077fea
DS		 7582 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7583 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7584 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7585 break;
e8e26350 7586 case IXGBE_DEV_ID_82599_KX4:
495dce12 7587 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 7588 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 7589 break;
7590 default:
7591 adapter->wol = 0;
7592 break;
7593 }
e8e26350
PW		 7594 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7595
04f165ef
PW		 7596 /* pick up the PCI bus settings for reporting later */
7597 hw->mac.ops.get_bus_info(hw);
7598
9a799d71 7599 /* print bus type/speed/width info */
849c4542 7600 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7601 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7602 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7603 "Unknown"),
7604 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7605 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7606 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7607 "Unknown"),
7608 netdev->dev_addr);
289700db
DS		 7609
7610 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7611 if (err)
9fe93afd 7612 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7613 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7614 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7615 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7616 part_str);
e8e26350 7617 else
289700db
DS		 7618 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7619 hw->mac.type, hw->phy.type, part_str);
9a799d71 7620
e8e26350 7621 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7622 e_dev_warn("PCI-Express bandwidth available for this card is "
7623 "not sufficient for optimal performance.\n");
7624 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7625 "is required.\n");
0c254d86
AK		 7626 }
7627
34b0368c
PWJ		 7628 /* save off EEPROM version number */
7629 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7630
9a799d71 7631 /* reset the hardware with the new settings */
794caeb2 7632 err = hw->mac.ops.start_hw(hw);
c44ade9e 7633
794caeb2
PWJ		 7634 if (err == IXGBE_ERR_EEPROM_VERSION) {
7635 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7636 e_dev_warn("This device is a pre-production adapter/LOM. "
7637 "Please be aware there may be issues associated "
7638 "with your hardware. If you are experiencing "
7639 "problems please contact your Intel or hardware "
7640 "representative who provided you with this "
7641 "hardware.\n");
794caeb2 7642 }
9a799d71
AK		 7643 strcpy(netdev->name, "eth%d");
7644 err = register_netdev(netdev);
7645 if (err)
7646 goto err_register;
7647
54386467
JB		 7648 /* carrier off reporting is important to ethtool even BEFORE open */
7649 netif_carrier_off(netdev);
7650
119fc60a 7651 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
e8e9f696
JP		 7652 INIT_WORK(&adapter->check_overtemp_task,
7653 ixgbe_check_overtemp_task);
5dd2d332 7654#ifdef CONFIG_IXGBE_DCA
652f093f 7655 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7656 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7657 ixgbe_setup_dca(adapter);
7658 }
7659#endif
1cdd1ec8 7660 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7661 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7662 for (i = 0; i < adapter->num_vfs; i++)
7663 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7664 }
7665
0365e6e4
PW		 7666 /* add san mac addr to netdev */
7667 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7668
849c4542 7669 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7670 cards_found++;
7671 return 0;
7672
7673err_register:
5eba3699 7674 ixgbe_release_hw_control(adapter);
7a921c93 7675 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7676err_sw_init:
7677err_eeprom:
1cdd1ec8
GR		 7678 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7679 ixgbe_disable_sriov(adapter);
7086400d 7680 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7681 iounmap(hw->hw_addr);
7682err_ioremap:
7683 free_netdev(netdev);
7684err_alloc_etherdev:
e8e9f696
JP		 7685 pci_release_selected_regions(pdev,
7686 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7687err_pci_reg:
7688err_dma:
7689 pci_disable_device(pdev);
7690 return err;
7691}
7692
7693/**
7694 * ixgbe_remove - Device Removal Routine
7695 * @pdev: PCI device information struct
7696 *
7697 * ixgbe_remove is called by the PCI subsystem to alert the driver
7698 * that it should release a PCI device. The could be caused by a
7699 * Hot-Plug event, or because the driver is going to be removed from
7700 * memory.
7701 **/
7702static void __devexit ixgbe_remove(struct pci_dev *pdev)
7703{
c60fbb00
AD		 7704 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7705 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7706
7707 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7708 cancel_work_sync(&adapter->service_task);
760141a5 7709
760141a5
TH		 7710 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7711 cancel_work_sync(&adapter->check_overtemp_task);
5dd2d332 7712#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7713 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7714 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7715 dca_remove_requester(&pdev->dev);
7716 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7717 }
7718
7719#endif
332d4a7d
YZ		 7720#ifdef IXGBE_FCOE
7721 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7722 ixgbe_cleanup_fcoe(adapter);
7723
7724#endif /* IXGBE_FCOE */
0365e6e4
PW		 7725
7726 /* remove the added san mac */
7727 ixgbe_del_sanmac_netdev(netdev);
7728
c4900be0
DS		 7729 if (netdev->reg_state == NETREG_REGISTERED)
7730 unregister_netdev(netdev);
9a799d71 7731
1cdd1ec8
GR		 7732 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7733 ixgbe_disable_sriov(adapter);
7734
7a921c93 7735 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7736
021230d4 7737 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7738
7739 iounmap(adapter->hw.hw_addr);
9ce77666 7740 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7741 IORESOURCE_MEM));
9a799d71 7742
849c4542 7743 e_dev_info("complete\n");
021230d4 7744
9a799d71
AK		 7745 free_netdev(netdev);
7746
19d5afd4 7747 pci_disable_pcie_error_reporting(pdev);
6fabd715 7748
9a799d71
AK		 7749 pci_disable_device(pdev);
7750}
7751
7752/**
7753 * ixgbe_io_error_detected - called when PCI error is detected
7754 * @pdev: Pointer to PCI device
7755 * @state: The current pci connection state
7756 *
7757 * This function is called after a PCI bus error affecting
7758 * this device has been detected.
7759 */
7760static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7761 pci_channel_state_t state)
9a799d71 7762{
c60fbb00
AD		 7763 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7764 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7765
7766 netif_device_detach(netdev);
7767
3044b8d1
BL		 7768 if (state == pci_channel_io_perm_failure)
7769 return PCI_ERS_RESULT_DISCONNECT;
7770
9a799d71
AK		 7771 if (netif_running(netdev))
7772 ixgbe_down(adapter);
7773 pci_disable_device(pdev);
7774
b4617240 7775 /* Request a slot reset. */
9a799d71
AK		 7776 return PCI_ERS_RESULT_NEED_RESET;
7777}
7778
7779/**
7780 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7781 * @pdev: Pointer to PCI device
7782 *
7783 * Restart the card from scratch, as if from a cold-boot.
7784 */
7785static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7786{
c60fbb00 7787 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7788 pci_ers_result_t result;
7789 int err;
9a799d71 7790
9ce77666 7791 if (pci_enable_device_mem(pdev)) {
396e799c 7792 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7793 result = PCI_ERS_RESULT_DISCONNECT;
7794 } else {
7795 pci_set_master(pdev);
7796 pci_restore_state(pdev);
c0e1f68b 7797 pci_save_state(pdev);
9a799d71 7798
dd4d8ca6 7799 pci_wake_from_d3(pdev, false);
9a799d71 7800
6fabd715 7801 ixgbe_reset(adapter);
88512539 7802 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7803 result = PCI_ERS_RESULT_RECOVERED;
7804 }
7805
7806 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7807 if (err) {
849c4542
ET		 7808 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7809 "failed 0x%0x\n", err);
6fabd715
PWJ		 7810 /* non-fatal, continue */
7811 }
9a799d71 7812
6fabd715 7813 return result;
9a799d71
AK		 7814}
7815
7816/**
7817 * ixgbe_io_resume - called when traffic can start flowing again.
7818 * @pdev: Pointer to PCI device
7819 *
7820 * This callback is called when the error recovery driver tells us that
7821 * its OK to resume normal operation.
7822 */
7823static void ixgbe_io_resume(struct pci_dev *pdev)
7824{
c60fbb00
AD		 7825 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7826 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7827
7828 if (netif_running(netdev)) {
7829 if (ixgbe_up(adapter)) {
396e799c 7830 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7831 return;
7832 }
7833 }
7834
7835 netif_device_attach(netdev);
9a799d71
AK		 7836}
7837
7838static struct pci_error_handlers ixgbe_err_handler = {
7839 .error_detected = ixgbe_io_error_detected,
7840 .slot_reset = ixgbe_io_slot_reset,
7841 .resume = ixgbe_io_resume,
7842};
7843
7844static struct pci_driver ixgbe_driver = {
7845 .name = ixgbe_driver_name,
7846 .id_table = ixgbe_pci_tbl,
7847 .probe = ixgbe_probe,
7848 .remove = __devexit_p(ixgbe_remove),
7849#ifdef CONFIG_PM
7850 .suspend = ixgbe_suspend,
7851 .resume = ixgbe_resume,
7852#endif
7853 .shutdown = ixgbe_shutdown,
7854 .err_handler = &ixgbe_err_handler
7855};
7856
7857/**
7858 * ixgbe_init_module - Driver Registration Routine
7859 *
7860 * ixgbe_init_module is the first routine called when the driver is
7861 * loaded. All it does is register with the PCI subsystem.
7862 **/
7863static int __init ixgbe_init_module(void)
7864{
7865 int ret;
c7689578 7866 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7867 pr_info("%s\n", ixgbe_copyright);
9a799d71 7868
5dd2d332 7869#ifdef CONFIG_IXGBE_DCA
bd0362dd 7870 dca_register_notify(&dca_notifier);
bd0362dd 7871#endif
5dd2d332 7872
9a799d71
AK		 7873 ret = pci_register_driver(&ixgbe_driver);
7874 return ret;
7875}
b4617240 7876
9a799d71
AK		 7877module_init(ixgbe_init_module);
7878
7879/**
7880 * ixgbe_exit_module - Driver Exit Cleanup Routine
7881 *
7882 * ixgbe_exit_module is called just before the driver is removed
7883 * from memory.
7884 **/
7885static void __exit ixgbe_exit_module(void)
7886{
5dd2d332 7887#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7888 dca_unregister_notify(&dca_notifier);
7889#endif
9a799d71 7890 pci_unregister_driver(&ixgbe_driver);
1a51502b 7891 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7892}
bd0362dd 7893
5dd2d332 7894#ifdef CONFIG_IXGBE_DCA
bd0362dd 7895static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7896 void *p)
bd0362dd
JC		 7897{
7898 int ret_val;
7899
7900 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7901 __ixgbe_notify_dca);
bd0362dd
JC		 7902
7903 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7904}
b453368d 7905
5dd2d332 7906#endif /* CONFIG_IXGBE_DCA */
849c4542 7907
9a799d71
AK		 7908module_exit(ixgbe_exit_module);
7909
7910/* ixgbe_main.c */
Linux kernel - Deliverables
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