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ixgbe: DCB, use multiple Tx rings per traffic class
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
e8e9f696 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
310e5ca8 55#define DRV_VERSION "3.2.9-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 57static const char ixgbe_copyright[] =
58 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 59
60static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 61 [board_82598] = &ixgbe_82598_info,
e8e26350 62 [board_82599] = &ixgbe_82599_info,
fe15e8e1 63 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 64};
65
66/* ixgbe_pci_tbl - PCI Device ID Table
67 *
68 * Wildcard entries (PCI_ANY_ID) should come last
69 * Last entry must be all 0s
70 *
71 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
72 * Class, Class Mask, private data (not used) }
73 */
a3aa1884 74static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 78 board_82598 },
9a799d71 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 80 board_82598 },
0befdb3e
JB		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
82 board_82598 },
3845bec0
PWJ		 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
84 board_82598 },
9a799d71 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 86 board_82598 },
8d792cd9
JB		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
88 board_82598 },
c4900be0
DS		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
90 board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
92 board_82598 },
b95f5fcb
JB		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
94 board_82598 },
c4900be0
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
96 board_82598 },
2f21bdd3
DS		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
98 board_82598 },
e8e26350
PW		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
100 board_82599 },
1fcf03e6
PWJ		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
102 board_82599 },
74757d49
DS		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
104 board_82599 },
e8e26350
PW		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
106 board_82599 },
38ad1c8e
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
108 board_82599 },
dbfec662
DS		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
110 board_82599 },
8911184f
PWJ		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
112 board_82599 },
dbffcb21
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
114 board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
116 board_82599 },
119fc60a
MC		 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
118 board_82599 },
312eb931
DS		 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
120 board_82599 },
b93a2226 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
d994653d 122 board_X540 },
9a799d71
AK		 123
124 /* required last entry */
125 {0, }
126};
127MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
128
5dd2d332 129#ifdef CONFIG_IXGBE_DCA
bd0362dd 130static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 131 void *p);
bd0362dd
JC		 132static struct notifier_block dca_notifier = {
133 .notifier_call = ixgbe_notify_dca,
134 .next = NULL,
135 .priority = 0
136};
137#endif
138
1cdd1ec8
GR		 139#ifdef CONFIG_PCI_IOV
140static unsigned int max_vfs;
141module_param(max_vfs, uint, 0);
e8e9f696
JP		 142MODULE_PARM_DESC(max_vfs,
143 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 144#endif /* CONFIG_PCI_IOV */
145
9a799d71
AK		 146MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
147MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
148MODULE_LICENSE("GPL");
149MODULE_VERSION(DRV_VERSION);
150
151#define DEFAULT_DEBUG_LEVEL_SHIFT 3
152
1cdd1ec8
GR		 153static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
154{
155 struct ixgbe_hw *hw = &adapter->hw;
156 u32 gcr;
157 u32 gpie;
158 u32 vmdctl;
159
160#ifdef CONFIG_PCI_IOV
161 /* disable iov and allow time for transactions to clear */
162 pci_disable_sriov(adapter->pdev);
163#endif
164
165 /* turn off device IOV mode */
166 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
167 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
168 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
169 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
170 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
171 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
172
173 /* set default pool back to 0 */
174 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
175 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
176 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
177
178 /* take a breather then clean up driver data */
179 msleep(100);
e8e9f696
JP		 180
181 kfree(adapter->vfinfo);
1cdd1ec8
GR		 182 adapter->vfinfo = NULL;
183
184 adapter->num_vfs = 0;
185 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
186}
187
dcd79aeb
TI		 188struct ixgbe_reg_info {
189 u32 ofs;
190 char *name;
191};
192
193static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
194
195 /* General Registers */
196 {IXGBE_CTRL, "CTRL"},
197 {IXGBE_STATUS, "STATUS"},
198 {IXGBE_CTRL_EXT, "CTRL_EXT"},
199
200 /* Interrupt Registers */
201 {IXGBE_EICR, "EICR"},
202
203 /* RX Registers */
204 {IXGBE_SRRCTL(0), "SRRCTL"},
205 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
206 {IXGBE_RDLEN(0), "RDLEN"},
207 {IXGBE_RDH(0), "RDH"},
208 {IXGBE_RDT(0), "RDT"},
209 {IXGBE_RXDCTL(0), "RXDCTL"},
210 {IXGBE_RDBAL(0), "RDBAL"},
211 {IXGBE_RDBAH(0), "RDBAH"},
212
213 /* TX Registers */
214 {IXGBE_TDBAL(0), "TDBAL"},
215 {IXGBE_TDBAH(0), "TDBAH"},
216 {IXGBE_TDLEN(0), "TDLEN"},
217 {IXGBE_TDH(0), "TDH"},
218 {IXGBE_TDT(0), "TDT"},
219 {IXGBE_TXDCTL(0), "TXDCTL"},
220
221 /* List Terminator */
222 {}
223};
224
225
226/*
227 * ixgbe_regdump - register printout routine
228 */
229static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
230{
231 int i = 0, j = 0;
232 char rname[16];
233 u32 regs[64];
234
235 switch (reginfo->ofs) {
236 case IXGBE_SRRCTL(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
239 break;
240 case IXGBE_DCA_RXCTRL(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
243 break;
244 case IXGBE_RDLEN(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
247 break;
248 case IXGBE_RDH(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
251 break;
252 case IXGBE_RDT(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
255 break;
256 case IXGBE_RXDCTL(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
259 break;
260 case IXGBE_RDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
263 break;
264 case IXGBE_RDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
267 break;
268 case IXGBE_TDBAL(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
271 break;
272 case IXGBE_TDBAH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
275 break;
276 case IXGBE_TDLEN(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
279 break;
280 case IXGBE_TDH(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
283 break;
284 case IXGBE_TDT(0):
285 for (i = 0; i < 64; i++)
286 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
287 break;
288 case IXGBE_TXDCTL(0):
289 for (i = 0; i < 64; i++)
290 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
291 break;
292 default:
c7689578 293 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 294 IXGBE_READ_REG(hw, reginfo->ofs));
295 return;
296 }
297
298 for (i = 0; i < 8; i++) {
299 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 300 pr_err("%-15s", rname);
dcd79aeb 301 for (j = 0; j < 8; j++)
c7689578
JP		 302 pr_cont(" %08x", regs[i*8+j]);
303 pr_cont("\n");
dcd79aeb
TI		 304 }
305
306}
307
308/*
309 * ixgbe_dump - Print registers, tx-rings and rx-rings
310 */
311static void ixgbe_dump(struct ixgbe_adapter *adapter)
312{
313 struct net_device *netdev = adapter->netdev;
314 struct ixgbe_hw *hw = &adapter->hw;
315 struct ixgbe_reg_info *reginfo;
316 int n = 0;
317 struct ixgbe_ring *tx_ring;
318 struct ixgbe_tx_buffer *tx_buffer_info;
319 union ixgbe_adv_tx_desc *tx_desc;
320 struct my_u0 { u64 a; u64 b; } *u0;
321 struct ixgbe_ring *rx_ring;
322 union ixgbe_adv_rx_desc *rx_desc;
323 struct ixgbe_rx_buffer *rx_buffer_info;
324 u32 staterr;
325 int i = 0;
326
327 if (!netif_msg_hw(adapter))
328 return;
329
330 /* Print netdevice Info */
331 if (netdev) {
332 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 333 pr_info("Device Name state "
dcd79aeb 334 "trans_start last_rx\n");
c7689578
JP		 335 pr_info("%-15s %016lX %016lX %016lX\n",
336 netdev->name,
337 netdev->state,
338 netdev->trans_start,
339 netdev->last_rx);
dcd79aeb
TI		 340 }
341
342 /* Print Registers */
343 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 344 pr_info(" Register Name Value\n");
dcd79aeb
TI		 345 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
346 reginfo->name; reginfo++) {
347 ixgbe_regdump(hw, reginfo);
348 }
349
350 /* Print TX Ring Summary */
351 if (!netdev || !netif_running(netdev))
352 goto exit;
353
354 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 355 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 356 for (n = 0; n < adapter->num_tx_queues; n++) {
357 tx_ring = adapter->tx_ring[n];
358 tx_buffer_info =
359 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 360 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 361 n, tx_ring->next_to_use, tx_ring->next_to_clean,
362 (u64)tx_buffer_info->dma,
363 tx_buffer_info->length,
364 tx_buffer_info->next_to_watch,
365 (u64)tx_buffer_info->time_stamp);
366 }
367
368 /* Print TX Rings */
369 if (!netif_msg_tx_done(adapter))
370 goto rx_ring_summary;
371
372 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
373
374 /* Transmit Descriptor Formats
375 *
376 * Advanced Transmit Descriptor
377 * +--------------------------------------------------------------+
378 * 0 | Buffer Address [63:0] |
379 * +--------------------------------------------------------------+
380 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
381 * +--------------------------------------------------------------+
382 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
383 */
384
385 for (n = 0; n < adapter->num_tx_queues; n++) {
386 tx_ring = adapter->tx_ring[n];
c7689578
JP		 387 pr_info("------------------------------------\n");
388 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
389 pr_info("------------------------------------\n");
390 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 391 "[PlPOIdStDDt Ln] [bi->dma ] "
392 "leng ntw timestamp bi->skb\n");
393
394 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 395 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 396 tx_buffer_info = &tx_ring->tx_buffer_info[i];
397 u0 = (struct my_u0 *)tx_desc;
c7689578 398 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 399 " %04X %3X %016llX %p", i,
400 le64_to_cpu(u0->a),
401 le64_to_cpu(u0->b),
402 (u64)tx_buffer_info->dma,
403 tx_buffer_info->length,
404 tx_buffer_info->next_to_watch,
405 (u64)tx_buffer_info->time_stamp,
406 tx_buffer_info->skb);
407 if (i == tx_ring->next_to_use &&
408 i == tx_ring->next_to_clean)
c7689578 409 pr_cont(" NTC/U\n");
dcd79aeb 410 else if (i == tx_ring->next_to_use)
c7689578 411 pr_cont(" NTU\n");
dcd79aeb 412 else if (i == tx_ring->next_to_clean)
c7689578 413 pr_cont(" NTC\n");
dcd79aeb 414 else
c7689578 415 pr_cont("\n");
dcd79aeb
TI		 416
417 if (netif_msg_pktdata(adapter) &&
418 tx_buffer_info->dma != 0)
419 print_hex_dump(KERN_INFO, "",
420 DUMP_PREFIX_ADDRESS, 16, 1,
421 phys_to_virt(tx_buffer_info->dma),
422 tx_buffer_info->length, true);
423 }
424 }
425
426 /* Print RX Rings Summary */
427rx_ring_summary:
428 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 429 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 430 for (n = 0; n < adapter->num_rx_queues; n++) {
431 rx_ring = adapter->rx_ring[n];
c7689578
JP		 432 pr_info("%5d %5X %5X\n",
433 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 434 }
435
436 /* Print RX Rings */
437 if (!netif_msg_rx_status(adapter))
438 goto exit;
439
440 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
441
442 /* Advanced Receive Descriptor (Read) Format
443 * 63 1 0
444 * +-----------------------------------------------------+
445 * 0 | Packet Buffer Address [63:1] |A0/NSE|
446 * +----------------------------------------------+------+
447 * 8 | Header Buffer Address [63:1] | DD |
448 * +-----------------------------------------------------+
449 *
450 *
451 * Advanced Receive Descriptor (Write-Back) Format
452 *
453 * 63 48 47 32 31 30 21 20 16 15 4 3 0
454 * +------------------------------------------------------+
455 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
456 * | Checksum Ident | | | | Type | Type |
457 * +------------------------------------------------------+
458 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
459 * +------------------------------------------------------+
460 * 63 48 47 32 31 20 19 0
461 */
462 for (n = 0; n < adapter->num_rx_queues; n++) {
463 rx_ring = adapter->rx_ring[n];
c7689578
JP		 464 pr_info("------------------------------------\n");
465 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
466 pr_info("------------------------------------\n");
467 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 468 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
469 "<-- Adv Rx Read format\n");
c7689578 470 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 471 "[vl er S cks ln] ---------------- [bi->skb] "
472 "<-- Adv Rx Write-Back format\n");
473
474 for (i = 0; i < rx_ring->count; i++) {
475 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 476 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 477 u0 = (struct my_u0 *)rx_desc;
478 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
479 if (staterr & IXGBE_RXD_STAT_DD) {
480 /* Descriptor Done */
c7689578 481 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 482 "%016llX ---------------- %p", i,
483 le64_to_cpu(u0->a),
484 le64_to_cpu(u0->b),
485 rx_buffer_info->skb);
486 } else {
c7689578 487 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 488 "%016llX %016llX %p", i,
489 le64_to_cpu(u0->a),
490 le64_to_cpu(u0->b),
491 (u64)rx_buffer_info->dma,
492 rx_buffer_info->skb);
493
494 if (netif_msg_pktdata(adapter)) {
495 print_hex_dump(KERN_INFO, "",
496 DUMP_PREFIX_ADDRESS, 16, 1,
497 phys_to_virt(rx_buffer_info->dma),
498 rx_ring->rx_buf_len, true);
499
500 if (rx_ring->rx_buf_len
501 < IXGBE_RXBUFFER_2048)
502 print_hex_dump(KERN_INFO, "",
503 DUMP_PREFIX_ADDRESS, 16, 1,
504 phys_to_virt(
505 rx_buffer_info->page_dma +
506 rx_buffer_info->page_offset
507 ),
508 PAGE_SIZE/2, true);
509 }
510 }
511
512 if (i == rx_ring->next_to_use)
c7689578 513 pr_cont(" NTU\n");
dcd79aeb 514 else if (i == rx_ring->next_to_clean)
c7689578 515 pr_cont(" NTC\n");
dcd79aeb 516 else
c7689578 517 pr_cont("\n");
dcd79aeb
TI		 518
519 }
520 }
521
522exit:
523 return;
524}
525
5eba3699
AV		 526static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
527{
528 u32 ctrl_ext;
529
530 /* Let firmware take over control of h/w */
531 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
532 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 533 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 534}
535
536static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
537{
538 u32 ctrl_ext;
539
540 /* Let firmware know the driver has taken over */
541 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
542 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 543 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 544}
9a799d71 545
e8e26350
PW		 546/*
547 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
548 * @adapter: pointer to adapter struct
549 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
550 * @queue: queue to map the corresponding interrupt to
551 * @msix_vector: the vector to map to the corresponding queue
552 *
553 */
554static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 555 u8 queue, u8 msix_vector)
9a799d71
AK		 556{
557 u32 ivar, index;
e8e26350
PW		 558 struct ixgbe_hw *hw = &adapter->hw;
559 switch (hw->mac.type) {
560 case ixgbe_mac_82598EB:
561 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
562 if (direction == -1)
563 direction = 0;
564 index = (((direction * 64) + queue) >> 2) & 0x1F;
565 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
566 ivar &= ~(0xFF << (8 * (queue & 0x3)));
567 ivar |= (msix_vector << (8 * (queue & 0x3)));
568 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
569 break;
570 case ixgbe_mac_82599EB:
b93a2226 571 case ixgbe_mac_X540:
e8e26350
PW		 572 if (direction == -1) {
573 /* other causes */
574 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
575 index = ((queue & 1) * 8);
576 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
577 ivar &= ~(0xFF << index);
578 ivar |= (msix_vector << index);
579 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
580 break;
581 } else {
582 /* tx or rx causes */
583 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
584 index = ((16 * (queue & 1)) + (8 * direction));
585 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
586 ivar &= ~(0xFF << index);
587 ivar |= (msix_vector << index);
588 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
589 break;
590 }
591 default:
592 break;
593 }
9a799d71
AK		 594}
595
fe49f04a 596static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 597 u64 qmask)
fe49f04a
AD		 598{
599 u32 mask;
600
bd508178
AD		 601 switch (adapter->hw.mac.type) {
602 case ixgbe_mac_82598EB:
fe49f04a
AD		 603 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 605 break;
606 case ixgbe_mac_82599EB:
b93a2226 607 case ixgbe_mac_X540:
fe49f04a
AD		 608 mask = (qmask & 0xFFFFFFFF);
609 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
610 mask = (qmask >> 32);
611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 612 break;
613 default:
614 break;
fe49f04a
AD		 615 }
616}
617
b6ec895e
AD		 618void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
619 struct ixgbe_tx_buffer *tx_buffer_info)
9a799d71 620{
e5a43549
AD		 621 if (tx_buffer_info->dma) {
622 if (tx_buffer_info->mapped_as_page)
b6ec895e 623 dma_unmap_page(tx_ring->dev,
e5a43549
AD		 624 tx_buffer_info->dma,
625 tx_buffer_info->length,
1b507730 626 DMA_TO_DEVICE);
e5a43549 627 else
b6ec895e 628 dma_unmap_single(tx_ring->dev,
e5a43549
AD		 629 tx_buffer_info->dma,
630 tx_buffer_info->length,
1b507730 631 DMA_TO_DEVICE);
e5a43549
AD		 632 tx_buffer_info->dma = 0;
633 }
9a799d71
AK		 634 if (tx_buffer_info->skb) {
635 dev_kfree_skb_any(tx_buffer_info->skb);
636 tx_buffer_info->skb = NULL;
637 }
44df32c5 638 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 639 /* tx_buffer_info must be completely set up in the transmit path */
640}
641
26f23d82 642/**
c84d324c
JF		 643 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
644 * @adapter: driver private struct
645 * @index: reg idx of queue to query (0-127)
26f23d82 646 *
c84d324c
JF		 647 * Helper function to determine the traffic index for a paticular
648 * register index.
26f23d82 649 *
c84d324c 650 * Returns : a tc index for use in range 0-7, or 0-3
26f23d82 651 */
3b2ee943 652static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
26f23d82 653{
c84d324c 654 int tc = -1;
e5b64635 655 int dcb_i = netdev_get_num_tc(adapter->netdev);
26f23d82 656
c84d324c
JF		 657 /* if DCB is not enabled the queues have no TC */
658 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
659 return tc;
26f23d82 660
c84d324c
JF		 661 /* check valid range */
662 if (reg_idx >= adapter->hw.mac.max_tx_queues)
663 return tc;
664
665 switch (adapter->hw.mac.type) {
666 case ixgbe_mac_82598EB:
667 tc = reg_idx >> 2;
668 break;
669 default:
670 if (dcb_i != 4 && dcb_i != 8)
6837e895 671 break;
c84d324c
JF		 672
673 /* if VMDq is enabled the lowest order bits determine TC */
674 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
675 IXGBE_FLAG_VMDQ_ENABLED)) {
676 tc = reg_idx & (dcb_i - 1);
677 break;
678 }
679
680 /*
681 * Convert the reg_idx into the correct TC. This bitmask
682 * targets the last full 32 ring traffic class and assigns
683 * it a value of 1. From there the rest of the rings are
684 * based on shifting the mask further up to include the
685 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
686 * will only ever be 8 or 4 and that reg_idx will never
687 * be greater then 128. The code without the power of 2
688 * optimizations would be:
689 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
690 */
691 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
692 tc >>= 9 - (reg_idx >> 5);
693 }
694
695 return tc;
696}
697
698static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
699{
700 struct ixgbe_hw *hw = &adapter->hw;
701 struct ixgbe_hw_stats *hwstats = &adapter->stats;
702 u32 data = 0;
703 u32 xoff[8] = {0};
704 int i;
705
706 if ((hw->fc.current_mode == ixgbe_fc_full) ||
707 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
708 switch (hw->mac.type) {
709 case ixgbe_mac_82598EB:
710 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 711 break;
712 default:
c84d324c
JF		 713 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
714 }
715 hwstats->lxoffrxc += data;
716
717 /* refill credits (no tx hang) if we received xoff */
718 if (!data)
719 return;
720
721 for (i = 0; i < adapter->num_tx_queues; i++)
722 clear_bit(__IXGBE_HANG_CHECK_ARMED,
723 &adapter->tx_ring[i]->state);
724 return;
725 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
726 return;
727
728 /* update stats for each tc, only valid with PFC enabled */
729 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
730 switch (hw->mac.type) {
731 case ixgbe_mac_82598EB:
732 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 733 break;
c84d324c
JF		 734 default:
735 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 736 }
c84d324c
JF		 737 hwstats->pxoffrxc[i] += xoff[i];
738 }
739
740 /* disarm tx queues that have received xoff frames */
741 for (i = 0; i < adapter->num_tx_queues; i++) {
742 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
743 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
744
745 if (xoff[tc])
746 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 747 }
26f23d82
YZ		 748}
749
c84d324c 750static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 751{
c84d324c
JF		 752 return ring->tx_stats.completed;
753}
754
755static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
756{
757 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 758 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 759
c84d324c
JF		 760 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
761 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
762
763 if (head != tail)
764 return (head < tail) ?
765 tail - head : (tail + ring->count - head);
766
767 return 0;
768}
769
770static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
771{
772 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
773 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
774 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
775 bool ret = false;
776
7d637bcc 777 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 778
779 /*
780 * Check for a hung queue, but be thorough. This verifies
781 * that a transmit has been completed since the previous
782 * check AND there is at least one packet pending. The
783 * ARMED bit is set to indicate a potential hang. The
784 * bit is cleared if a pause frame is received to remove
785 * false hang detection due to PFC or 802.3x frames. By
786 * requiring this to fail twice we avoid races with
787 * pfc clearing the ARMED bit and conditions where we
788 * run the check_tx_hang logic with a transmit completion
789 * pending but without time to complete it yet.
790 */
791 if ((tx_done_old == tx_done) && tx_pending) {
792 /* make sure it is true for two checks in a row */
793 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
794 &tx_ring->state);
795 } else {
796 /* update completed stats and continue */
797 tx_ring->tx_stats.tx_done_old = tx_done;
798 /* reset the countdown */
799 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 800 }
801
c84d324c 802 return ret;
9a799d71
AK		 803}
804
b4617240
PW		 805#define IXGBE_MAX_TXD_PWR 14
806#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 807
808/* Tx Descriptors needed, worst case */
809#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
810 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
811#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 812 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 813
e01c31a5
JB		 814static void ixgbe_tx_timeout(struct net_device *netdev);
815
9a799d71
AK		 816/**
817 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 818 * @q_vector: structure containing interrupt and ring information
e01c31a5 819 * @tx_ring: tx ring to clean
9a799d71 820 **/
fe49f04a 821static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 822 struct ixgbe_ring *tx_ring)
9a799d71 823{
fe49f04a 824 struct ixgbe_adapter *adapter = q_vector->adapter;
12207e49
PWJ		 825 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
826 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5 827 unsigned int total_bytes = 0, total_packets = 0;
b953799e 828 u16 i, eop, count = 0;
9a799d71
AK		 829
830 i = tx_ring->next_to_clean;
12207e49 831 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 832 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 833
834 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 835 (count < tx_ring->work_limit)) {
12207e49 836 bool cleaned = false;
2d0bb1c1 837 rmb(); /* read buffer_info after eop_desc */
12207e49 838 for ( ; !cleaned; count++) {
31f05a2d 839 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 840 tx_buffer_info = &tx_ring->tx_buffer_info[i];
8ad494b0
AD		 841
842 tx_desc->wb.status = 0;
12207e49 843 cleaned = (i == eop);
9a799d71 844
8ad494b0
AD		 845 i++;
846 if (i == tx_ring->count)
847 i = 0;
e01c31a5 848
8ad494b0
AD		 849 if (cleaned && tx_buffer_info->skb) {
850 total_bytes += tx_buffer_info->bytecount;
851 total_packets += tx_buffer_info->gso_segs;
e092be60 852 }
e01c31a5 853
b6ec895e 854 ixgbe_unmap_and_free_tx_resource(tx_ring,
e8e9f696 855 tx_buffer_info);
e01c31a5 856 }
12207e49 857
c84d324c 858 tx_ring->tx_stats.completed++;
12207e49 859 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 860 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 861 }
862
9a799d71 863 tx_ring->next_to_clean = i;
b953799e
AD		 864 tx_ring->total_bytes += total_bytes;
865 tx_ring->total_packets += total_packets;
866 u64_stats_update_begin(&tx_ring->syncp);
867 tx_ring->stats.packets += total_packets;
868 tx_ring->stats.bytes += total_bytes;
869 u64_stats_update_end(&tx_ring->syncp);
870
c84d324c
JF		 871 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
872 /* schedule immediate reset if we believe we hung */
873 struct ixgbe_hw *hw = &adapter->hw;
874 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
875 e_err(drv, "Detected Tx Unit Hang\n"
876 " Tx Queue <%d>\n"
877 " TDH, TDT <%x>, <%x>\n"
878 " next_to_use <%x>\n"
879 " next_to_clean <%x>\n"
880 "tx_buffer_info[next_to_clean]\n"
881 " time_stamp <%lx>\n"
882 " jiffies <%lx>\n",
883 tx_ring->queue_index,
884 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
885 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
886 tx_ring->next_to_use, eop,
887 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
888
889 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
890
891 e_info(probe,
892 "tx hang %d detected on queue %d, resetting adapter\n",
893 adapter->tx_timeout_count + 1, tx_ring->queue_index);
894
b953799e 895 /* schedule immediate reset if we believe we hung */
b953799e
AD		 896 ixgbe_tx_timeout(adapter->netdev);
897
898 /* the adapter is about to reset, no point in enabling stuff */
899 return true;
900 }
9a799d71 901
e092be60 902#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
fc77dc3c 903 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
e8e9f696 904 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 905 /* Make sure that anybody stopping the queue after this
906 * sees the new next_to_clean.
907 */
908 smp_mb();
fc77dc3c 909 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 910 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 911 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 912 ++tx_ring->tx_stats.restart_queue;
30eba97a 913 }
e092be60 914 }
9a799d71 915
807540ba 916 return count < tx_ring->work_limit;
9a799d71
AK		 917}
918
5dd2d332 919#ifdef CONFIG_IXGBE_DCA
bd0362dd 920static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 921 struct ixgbe_ring *rx_ring,
922 int cpu)
bd0362dd 923{
33cf09c9 924 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 925 u32 rxctrl;
33cf09c9
AD		 926 u8 reg_idx = rx_ring->reg_idx;
927
928 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
929 switch (hw->mac.type) {
930 case ixgbe_mac_82598EB:
931 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
932 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
933 break;
934 case ixgbe_mac_82599EB:
b93a2226 935 case ixgbe_mac_X540:
33cf09c9
AD		 936 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
937 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
938 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
939 break;
940 default:
941 break;
bd0362dd 942 }
33cf09c9
AD		 943 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
944 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
945 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
946 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
947 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
948 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 949}
950
951static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 952 struct ixgbe_ring *tx_ring,
953 int cpu)
bd0362dd 954{
33cf09c9 955 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 956 u32 txctrl;
33cf09c9
AD		 957 u8 reg_idx = tx_ring->reg_idx;
958
959 switch (hw->mac.type) {
960 case ixgbe_mac_82598EB:
961 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
962 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
963 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
964 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
965 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
966 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
967 break;
968 case ixgbe_mac_82599EB:
b93a2226 969 case ixgbe_mac_X540:
33cf09c9
AD		 970 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
971 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
972 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
973 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
974 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
975 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
976 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
977 break;
978 default:
979 break;
980 }
981}
982
983static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
984{
985 struct ixgbe_adapter *adapter = q_vector->adapter;
bd0362dd 986 int cpu = get_cpu();
33cf09c9
AD		 987 long r_idx;
988 int i;
bd0362dd 989
33cf09c9
AD		 990 if (q_vector->cpu == cpu)
991 goto out_no_update;
992
993 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
994 for (i = 0; i < q_vector->txr_count; i++) {
995 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
996 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
997 r_idx + 1);
bd0362dd 998 }
33cf09c9
AD		 999
1000 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1001 for (i = 0; i < q_vector->rxr_count; i++) {
1002 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1003 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1004 r_idx + 1);
1005 }
1006
1007 q_vector->cpu = cpu;
1008out_no_update:
bd0362dd
JC		 1009 put_cpu();
1010}
1011
1012static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1013{
33cf09c9 1014 int num_q_vectors;
bd0362dd
JC		 1015 int i;
1016
1017 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1018 return;
1019
e35ec126
AD		 1020 /* always use CB2 mode, difference is masked in the CB driver */
1021 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1022
33cf09c9
AD		 1023 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1024 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1025 else
1026 num_q_vectors = 1;
1027
1028 for (i = 0; i < num_q_vectors; i++) {
1029 adapter->q_vector[i]->cpu = -1;
1030 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1031 }
1032}
1033
1034static int __ixgbe_notify_dca(struct device *dev, void *data)
1035{
c60fbb00 1036 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1037 unsigned long event = *(unsigned long *)data;
1038
33cf09c9
AD		 1039 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1040 return 0;
1041
bd0362dd
JC		 1042 switch (event) {
1043 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1044 /* if we're already enabled, don't do it again */
1045 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1046 break;
652f093f 1047 if (dca_add_requester(dev) == 0) {
96b0e0f6 1048 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1049 ixgbe_setup_dca(adapter);
1050 break;
1051 }
1052 /* Fall Through since DCA is disabled. */
1053 case DCA_PROVIDER_REMOVE:
1054 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1055 dca_remove_requester(dev);
1056 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1057 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1058 }
1059 break;
1060 }
1061
652f093f 1062 return 0;
bd0362dd
JC		 1063}
1064
5dd2d332 1065#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 1066/**
1067 * ixgbe_receive_skb - Send a completed packet up the stack
1068 * @adapter: board private structure
1069 * @skb: packet to send up
177db6ff
MC		 1070 * @status: hardware indication of status of receive
1071 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1072 * @rx_desc: rx descriptor
9a799d71 1073 **/
78b6f4ce 1074static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1075 struct sk_buff *skb, u8 status,
1076 struct ixgbe_ring *ring,
1077 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1078{
78b6f4ce
HX		 1079 struct ixgbe_adapter *adapter = q_vector->adapter;
1080 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1081 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1082 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1083
f62bbb5e
JG		 1084 if (is_vlan && (tag & VLAN_VID_MASK))
1085 __vlan_hwaccel_put_tag(skb, tag);
1086
1087 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1088 napi_gro_receive(napi, skb);
1089 else
1090 netif_rx(skb);
9a799d71
AK		 1091}
1092
e59bd25d
AV		 1093/**
1094 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1095 * @adapter: address of board private structure
1096 * @status_err: hardware indication of status of receive
1097 * @skb: skb currently being received and modified
1098 **/
9a799d71 1099static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 1100 union ixgbe_adv_rx_desc *rx_desc,
1101 struct sk_buff *skb)
9a799d71 1102{
8bae1b2b
DS		 1103 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1104
bc8acf2c 1105 skb_checksum_none_assert(skb);
9a799d71 1106
712744be
JB		 1107 /* Rx csum disabled */
1108 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1109 return;
e59bd25d
AV		 1110
1111 /* if IP and error */
1112 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1113 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1114 adapter->hw_csum_rx_error++;
1115 return;
1116 }
e59bd25d
AV		 1117
1118 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1119 return;
1120
1121 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1122 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1123
1124 /*
1125 * 82599 errata, UDP frames with a 0 checksum can be marked as
1126 * checksum errors.
1127 */
1128 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1129 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1130 return;
1131
e59bd25d
AV		 1132 adapter->hw_csum_rx_error++;
1133 return;
1134 }
1135
9a799d71 1136 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1137 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1138}
1139
84ea2591 1140static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1141{
1142 /*
1143 * Force memory writes to complete before letting h/w
1144 * know there are new descriptors to fetch. (Only
1145 * applicable for weak-ordered memory model archs,
1146 * such as IA-64).
1147 */
1148 wmb();
84ea2591 1149 writel(val, rx_ring->tail);
e8e26350
PW		 1150}
1151
9a799d71
AK		 1152/**
1153 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1154 * @rx_ring: ring to place buffers on
1155 * @cleaned_count: number of buffers to replace
9a799d71 1156 **/
fc77dc3c 1157void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1158{
9a799d71 1159 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1160 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1161 struct sk_buff *skb;
1162 u16 i = rx_ring->next_to_use;
9a799d71 1163
fc77dc3c
AD		 1164 /* do nothing if no valid netdev defined */
1165 if (!rx_ring->netdev)
1166 return;
1167
9a799d71 1168 while (cleaned_count--) {
31f05a2d 1169 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1170 bi = &rx_ring->rx_buffer_info[i];
1171 skb = bi->skb;
9a799d71 1172
d5f398ed 1173 if (!skb) {
fc77dc3c 1174 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1175 rx_ring->rx_buf_len);
9a799d71 1176 if (!skb) {
5b7da515 1177 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1178 goto no_buffers;
1179 }
d716a7d8
AD		 1180 /* initialize queue mapping */
1181 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1182 bi->skb = skb;
d716a7d8 1183 }
9a799d71 1184
d716a7d8 1185 if (!bi->dma) {
b6ec895e 1186 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1187 skb->data,
e8e9f696 1188 rx_ring->rx_buf_len,
1b507730 1189 DMA_FROM_DEVICE);
b6ec895e 1190 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1191 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1192 bi->dma = 0;
1193 goto no_buffers;
1194 }
9a799d71 1195 }
d5f398ed 1196
7d637bcc 1197 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1198 if (!bi->page) {
fc77dc3c 1199 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1200 if (!bi->page) {
5b7da515 1201 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1202 goto no_buffers;
1203 }
1204 }
1205
1206 if (!bi->page_dma) {
1207 /* use a half page if we're re-using */
1208 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1209 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1210 bi->page,
1211 bi->page_offset,
1212 PAGE_SIZE / 2,
1213 DMA_FROM_DEVICE);
b6ec895e 1214 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1215 bi->page_dma)) {
5b7da515 1216 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1217 bi->page_dma = 0;
1218 goto no_buffers;
1219 }
1220 }
1221
1222 /* Refresh the desc even if buffer_addrs didn't change
1223 * because each write-back erases this info. */
3a581073
JB		 1224 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1225 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1226 } else {
3a581073 1227 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1228 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1229 }
1230
1231 i++;
1232 if (i == rx_ring->count)
1233 i = 0;
9a799d71 1234 }
7c6e0a43 1235
9a799d71
AK		 1236no_buffers:
1237 if (rx_ring->next_to_use != i) {
1238 rx_ring->next_to_use = i;
84ea2591 1239 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1240 }
1241}
1242
c267fc16 1243static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1244{
c267fc16
AD		 1245 /* HW will not DMA in data larger than the given buffer, even if it
1246 * parses the (NFS, of course) header to be larger. In that case, it
1247 * fills the header buffer and spills the rest into the page.
1248 */
1249 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1250 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1251 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1252 if (hlen > IXGBE_RX_HDR_SIZE)
1253 hlen = IXGBE_RX_HDR_SIZE;
1254 return hlen;
7c6e0a43
JB		 1255}
1256
f8212f97
AD		 1257/**
1258 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1259 * @skb: pointer to the last skb in the rsc queue
1260 *
1261 * This function changes a queue full of hw rsc buffers into a completed
1262 * packet. It uses the ->prev pointers to find the first packet and then
1263 * turns it into the frag list owner.
1264 **/
aa80175a 1265static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1266{
1267 unsigned int frag_list_size = 0;
aa80175a 1268 unsigned int skb_cnt = 1;
f8212f97
AD		 1269
1270 while (skb->prev) {
1271 struct sk_buff *prev = skb->prev;
1272 frag_list_size += skb->len;
1273 skb->prev = NULL;
1274 skb = prev;
aa80175a 1275 skb_cnt++;
f8212f97
AD		 1276 }
1277
1278 skb_shinfo(skb)->frag_list = skb->next;
1279 skb->next = NULL;
1280 skb->len += frag_list_size;
1281 skb->data_len += frag_list_size;
1282 skb->truesize += frag_list_size;
aa80175a
AD		 1283 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1284
f8212f97
AD		 1285 return skb;
1286}
1287
aa80175a
AD		 1288static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1289{
1290 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1291 IXGBE_RXDADV_RSCCNT_MASK);
1292}
43634e82 1293
c267fc16 1294static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1295 struct ixgbe_ring *rx_ring,
1296 int *work_done, int work_to_do)
9a799d71 1297{
78b6f4ce 1298 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1299 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1300 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1301 struct sk_buff *skb;
d2f4fbe2 1302 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1303 const int current_node = numa_node_id();
3d8fd385
YZ		 1304#ifdef IXGBE_FCOE
1305 int ddp_bytes = 0;
1306#endif /* IXGBE_FCOE */
c267fc16
AD		 1307 u32 staterr;
1308 u16 i;
1309 u16 cleaned_count = 0;
aa80175a 1310 bool pkt_is_rsc = false;
9a799d71
AK		 1311
1312 i = rx_ring->next_to_clean;
31f05a2d 1313 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1314 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1315
1316 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1317 u32 upper_len = 0;
9a799d71 1318
3c945e5b 1319 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1320
c267fc16
AD		 1321 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1322
9a799d71 1323 skb = rx_buffer_info->skb;
9a799d71 1324 rx_buffer_info->skb = NULL;
c267fc16 1325 prefetch(skb->data);
9a799d71 1326
c267fc16 1327 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1328 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16
AD		 1329
1330 /* if this is a skb from previous receive DMA will be 0 */
21fa4e66 1331 if (rx_buffer_info->dma) {
c267fc16 1332 u16 hlen;
aa80175a 1333 if (pkt_is_rsc &&
c267fc16
AD		 1334 !(staterr & IXGBE_RXD_STAT_EOP) &&
1335 !skb->prev) {
43634e82
MC		 1336 /*
1337 * When HWRSC is enabled, delay unmapping
1338 * of the first packet. It carries the
1339 * header information, HW may still
1340 * access the header after the writeback.
1341 * Only unmap it when EOP is reached
1342 */
e8171aaa 1343 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1344 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1345 } else {
b6ec895e 1346 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1347 rx_buffer_info->dma,
1348 rx_ring->rx_buf_len,
1349 DMA_FROM_DEVICE);
e8171aaa 1350 }
4f57ca6e 1351 rx_buffer_info->dma = 0;
c267fc16
AD		 1352
1353 if (ring_is_ps_enabled(rx_ring)) {
1354 hlen = ixgbe_get_hlen(rx_desc);
1355 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1356 } else {
1357 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1358 }
1359
1360 skb_put(skb, hlen);
1361 } else {
1362 /* assume packet split since header is unmapped */
1363 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1364 }
1365
1366 if (upper_len) {
b6ec895e
AD		 1367 dma_unmap_page(rx_ring->dev,
1368 rx_buffer_info->page_dma,
1369 PAGE_SIZE / 2,
1370 DMA_FROM_DEVICE);
9a799d71
AK		 1371 rx_buffer_info->page_dma = 0;
1372 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1373 rx_buffer_info->page,
1374 rx_buffer_info->page_offset,
1375 upper_len);
762f4c57 1376
c267fc16
AD		 1377 if ((page_count(rx_buffer_info->page) == 1) &&
1378 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1379 get_page(rx_buffer_info->page);
c267fc16
AD		 1380 else
1381 rx_buffer_info->page = NULL;
9a799d71
AK		 1382
1383 skb->len += upper_len;
1384 skb->data_len += upper_len;
1385 skb->truesize += upper_len;
1386 }
1387
1388 i++;
1389 if (i == rx_ring->count)
1390 i = 0;
9a799d71 1391
31f05a2d 1392 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1393 prefetch(next_rxd);
9a799d71 1394 cleaned_count++;
f8212f97 1395
aa80175a 1396 if (pkt_is_rsc) {
f8212f97
AD		 1397 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1398 IXGBE_RXDADV_NEXTP_SHIFT;
1399 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1400 } else {
1401 next_buffer = &rx_ring->rx_buffer_info[i];
1402 }
1403
c267fc16 1404 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1405 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1406 rx_buffer_info->skb = next_buffer->skb;
1407 rx_buffer_info->dma = next_buffer->dma;
1408 next_buffer->skb = skb;
1409 next_buffer->dma = 0;
1410 } else {
1411 skb->next = next_buffer->skb;
1412 skb->next->prev = skb;
1413 }
5b7da515 1414 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1415 goto next_desc;
1416 }
1417
aa80175a
AD		 1418 if (skb->prev) {
1419 skb = ixgbe_transform_rsc_queue(skb);
1420 /* if we got here without RSC the packet is invalid */
1421 if (!pkt_is_rsc) {
1422 __pskb_trim(skb, 0);
1423 rx_buffer_info->skb = skb;
1424 goto next_desc;
1425 }
1426 }
c267fc16
AD		 1427
1428 if (ring_is_rsc_enabled(rx_ring)) {
1429 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1430 dma_unmap_single(rx_ring->dev,
1431 IXGBE_RSC_CB(skb)->dma,
1432 rx_ring->rx_buf_len,
1433 DMA_FROM_DEVICE);
1434 IXGBE_RSC_CB(skb)->dma = 0;
1435 IXGBE_RSC_CB(skb)->delay_unmap = false;
1436 }
aa80175a
AD		 1437 }
1438 if (pkt_is_rsc) {
c267fc16
AD		 1439 if (ring_is_ps_enabled(rx_ring))
1440 rx_ring->rx_stats.rsc_count +=
aa80175a 1441 skb_shinfo(skb)->nr_frags;
c267fc16 1442 else
aa80175a
AD		 1443 rx_ring->rx_stats.rsc_count +=
1444 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1445 rx_ring->rx_stats.rsc_flush++;
1446 }
1447
1448 /* ERR_MASK will only have valid bits if EOP set */
9a799d71 1449 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
c267fc16
AD		 1450 /* trim packet back to size 0 and recycle it */
1451 __pskb_trim(skb, 0);
1452 rx_buffer_info->skb = skb;
9a799d71
AK		 1453 goto next_desc;
1454 }
1455
8bae1b2b 1456 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1457
1458 /* probably a little skewed due to removing CRC */
1459 total_rx_bytes += skb->len;
1460 total_rx_packets++;
1461
fc77dc3c 1462 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1463#ifdef IXGBE_FCOE
1464 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1465 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1466 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1467 if (!ddp_bytes)
332d4a7d 1468 goto next_desc;
3d8fd385 1469 }
332d4a7d 1470#endif /* IXGBE_FCOE */
fdaff1ce 1471 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1472
1473next_desc:
1474 rx_desc->wb.upper.status_error = 0;
1475
c267fc16
AD		 1476 (*work_done)++;
1477 if (*work_done >= work_to_do)
1478 break;
1479
9a799d71
AK		 1480 /* return some buffers to hardware, one at a time is too slow */
1481 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1482 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1483 cleaned_count = 0;
1484 }
1485
1486 /* use prefetched values */
1487 rx_desc = next_rxd;
9a799d71 1488 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1489 }
1490
9a799d71
AK		 1491 rx_ring->next_to_clean = i;
1492 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1493
1494 if (cleaned_count)
fc77dc3c 1495 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1496
3d8fd385
YZ		 1497#ifdef IXGBE_FCOE
1498 /* include DDPed FCoE data */
1499 if (ddp_bytes > 0) {
1500 unsigned int mss;
1501
fc77dc3c 1502 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1503 sizeof(struct fc_frame_header) -
1504 sizeof(struct fcoe_crc_eof);
1505 if (mss > 512)
1506 mss &= ~511;
1507 total_rx_bytes += ddp_bytes;
1508 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1509 }
1510#endif /* IXGBE_FCOE */
1511
f494e8fa
AV		 1512 rx_ring->total_packets += total_rx_packets;
1513 rx_ring->total_bytes += total_rx_bytes;
c267fc16
AD		 1514 u64_stats_update_begin(&rx_ring->syncp);
1515 rx_ring->stats.packets += total_rx_packets;
1516 rx_ring->stats.bytes += total_rx_bytes;
1517 u64_stats_update_end(&rx_ring->syncp);
9a799d71
AK		 1518}
1519
021230d4 1520static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1521/**
1522 * ixgbe_configure_msix - Configure MSI-X hardware
1523 * @adapter: board private structure
1524 *
1525 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1526 * interrupts.
1527 **/
1528static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1529{
021230d4 1530 struct ixgbe_q_vector *q_vector;
bf29ee6c 1531 int i, q_vectors, v_idx, r_idx;
021230d4 1532 u32 mask;
9a799d71 1533
021230d4 1534 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1535
4df10466
JB		 1536 /*
1537 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1538 * corresponding register.
1539 */
1540 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1541 q_vector = adapter->q_vector[v_idx];
984b3f57 1542 /* XXX for_each_set_bit(...) */
021230d4 1543 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1544 adapter->num_rx_queues);
021230d4
AV		 1545
1546 for (i = 0; i < q_vector->rxr_count; i++) {
bf29ee6c
AD		 1547 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1548 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
021230d4 1549 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1550 adapter->num_rx_queues,
1551 r_idx + 1);
021230d4
AV		 1552 }
1553 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1554 adapter->num_tx_queues);
021230d4
AV		 1555
1556 for (i = 0; i < q_vector->txr_count; i++) {
bf29ee6c
AD		 1557 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1558 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
021230d4 1559 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1560 adapter->num_tx_queues,
1561 r_idx + 1);
021230d4
AV		 1562 }
1563
021230d4 1564 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1565 /* tx only */
1566 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1567 else if (q_vector->rxr_count)
f7554a2b
NS		 1568 /* rx or mixed */
1569 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1570
fe49f04a 1571 ixgbe_write_eitr(q_vector);
b25ebfd2
PW		 1572 /* If Flow Director is enabled, set interrupt affinity */
1573 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1574 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1575 /*
1576 * Allocate the affinity_hint cpumask, assign the mask
1577 * for this vector, and set our affinity_hint for
1578 * this irq.
1579 */
1580 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1581 GFP_KERNEL))
1582 return;
1583 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1584 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1585 q_vector->affinity_mask);
1586 }
9a799d71
AK		 1587 }
1588
bd508178
AD		 1589 switch (adapter->hw.mac.type) {
1590 case ixgbe_mac_82598EB:
e8e26350 1591 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1592 v_idx);
bd508178
AD		 1593 break;
1594 case ixgbe_mac_82599EB:
b93a2226 1595 case ixgbe_mac_X540:
e8e26350 1596 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178
AD		 1597 break;
1598
1599 default:
1600 break;
1601 }
021230d4
AV		 1602 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1603
41fb9248 1604 /* set up to autoclear timer, and the vectors */
021230d4 1605 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1606 if (adapter->num_vfs)
1607 mask &= ~(IXGBE_EIMS_OTHER |
1608 IXGBE_EIMS_MAILBOX |
1609 IXGBE_EIMS_LSC);
1610 else
1611 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1612 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1613}
1614
f494e8fa
AV		 1615enum latency_range {
1616 lowest_latency = 0,
1617 low_latency = 1,
1618 bulk_latency = 2,
1619 latency_invalid = 255
1620};
1621
1622/**
1623 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1624 * @adapter: pointer to adapter
1625 * @eitr: eitr setting (ints per sec) to give last timeslice
1626 * @itr_setting: current throttle rate in ints/second
1627 * @packets: the number of packets during this measurement interval
1628 * @bytes: the number of bytes during this measurement interval
1629 *
1630 * Stores a new ITR value based on packets and byte
1631 * counts during the last interrupt. The advantage of per interrupt
1632 * computation is faster updates and more accurate ITR for the current
1633 * traffic pattern. Constants in this function were computed
1634 * based on theoretical maximum wire speed and thresholds were set based
1635 * on testing data as well as attempting to minimize response time
1636 * while increasing bulk throughput.
1637 * this functionality is controlled by the InterruptThrottleRate module
1638 * parameter (see ixgbe_param.c)
1639 **/
1640static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1641 u32 eitr, u8 itr_setting,
1642 int packets, int bytes)
f494e8fa
AV		 1643{
1644 unsigned int retval = itr_setting;
1645 u32 timepassed_us;
1646 u64 bytes_perint;
1647
1648 if (packets == 0)
1649 goto update_itr_done;
1650
1651
1652 /* simple throttlerate management
1653 * 0-20MB/s lowest (100000 ints/s)
1654 * 20-100MB/s low (20000 ints/s)
1655 * 100-1249MB/s bulk (8000 ints/s)
1656 */
1657 /* what was last interrupt timeslice? */
1658 timepassed_us = 1000000/eitr;
1659 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1660
1661 switch (itr_setting) {
1662 case lowest_latency:
1663 if (bytes_perint > adapter->eitr_low)
1664 retval = low_latency;
1665 break;
1666 case low_latency:
1667 if (bytes_perint > adapter->eitr_high)
1668 retval = bulk_latency;
1669 else if (bytes_perint <= adapter->eitr_low)
1670 retval = lowest_latency;
1671 break;
1672 case bulk_latency:
1673 if (bytes_perint <= adapter->eitr_high)
1674 retval = low_latency;
1675 break;
1676 }
1677
1678update_itr_done:
1679 return retval;
1680}
1681
509ee935
JB		 1682/**
1683 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1684 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1685 *
1686 * This function is made to be called by ethtool and by the driver
1687 * when it needs to update EITR registers at runtime. Hardware
1688 * specific quirks/differences are taken care of here.
1689 */
fe49f04a 1690void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1691{
fe49f04a 1692 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1693 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1694 int v_idx = q_vector->v_idx;
1695 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1696
bd508178
AD		 1697 switch (adapter->hw.mac.type) {
1698 case ixgbe_mac_82598EB:
509ee935
JB		 1699 /* must write high and low 16 bits to reset counter */
1700 itr_reg |= (itr_reg << 16);
bd508178
AD		 1701 break;
1702 case ixgbe_mac_82599EB:
b93a2226 1703 case ixgbe_mac_X540:
f8d1dcaf 1704 /*
b93a2226 1705 * 82599 and X540 can support a value of zero, so allow it for
f8d1dcaf
JB		 1706 * max interrupt rate, but there is an errata where it can
1707 * not be zero with RSC
1708 */
1709 if (itr_reg == 8 &&
1710 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1711 itr_reg = 0;
1712
509ee935
JB		 1713 /*
1714 * set the WDIS bit to not clear the timer bits and cause an
1715 * immediate assertion of the interrupt
1716 */
1717 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1718 break;
1719 default:
1720 break;
509ee935
JB		 1721 }
1722 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1723}
1724
f494e8fa
AV		 1725static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1726{
1727 struct ixgbe_adapter *adapter = q_vector->adapter;
125601bf 1728 int i, r_idx;
f494e8fa
AV		 1729 u32 new_itr;
1730 u8 current_itr, ret_itr;
f494e8fa
AV		 1731
1732 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1733 for (i = 0; i < q_vector->txr_count; i++) {
125601bf 1734 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1735 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1736 q_vector->tx_itr,
1737 tx_ring->total_packets,
1738 tx_ring->total_bytes);
f494e8fa
AV		 1739 /* if the result for this queue would decrease interrupt
1740 * rate for this vector then use that result */
30efa5a3 1741 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1742 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1743 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1744 r_idx + 1);
f494e8fa
AV		 1745 }
1746
1747 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1748 for (i = 0; i < q_vector->rxr_count; i++) {
125601bf 1749 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1750 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1751 q_vector->rx_itr,
1752 rx_ring->total_packets,
1753 rx_ring->total_bytes);
f494e8fa
AV		 1754 /* if the result for this queue would decrease interrupt
1755 * rate for this vector then use that result */
30efa5a3 1756 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1757 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1758 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1759 r_idx + 1);
f494e8fa
AV		 1760 }
1761
30efa5a3 1762 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1763
1764 switch (current_itr) {
1765 /* counts and packets in update_itr are dependent on these numbers */
1766 case lowest_latency:
1767 new_itr = 100000;
1768 break;
1769 case low_latency:
1770 new_itr = 20000; /* aka hwitr = ~200 */
1771 break;
1772 case bulk_latency:
1773 default:
1774 new_itr = 8000;
1775 break;
1776 }
1777
1778 if (new_itr != q_vector->eitr) {
fe49f04a 1779 /* do an exponential smoothing */
125601bf 1780 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935
JB		 1781
1782 /* save the algorithm value here, not the smoothed one */
1783 q_vector->eitr = new_itr;
fe49f04a
AD		 1784
1785 ixgbe_write_eitr(q_vector);
f494e8fa 1786 }
f494e8fa
AV		 1787}
1788
119fc60a
MC		 1789/**
1790 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1791 * @work: pointer to work_struct containing our data
1792 **/
1793static void ixgbe_check_overtemp_task(struct work_struct *work)
1794{
1795 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 1796 struct ixgbe_adapter,
1797 check_overtemp_task);
119fc60a
MC		 1798 struct ixgbe_hw *hw = &adapter->hw;
1799 u32 eicr = adapter->interrupt_event;
1800
7ca647bd
JP		 1801 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1802 return;
1803
1804 switch (hw->device_id) {
1805 case IXGBE_DEV_ID_82599_T3_LOM: {
1806 u32 autoneg;
1807 bool link_up = false;
1808
1809 if (hw->mac.ops.check_link)
1810 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1811
1812 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1813 (eicr & IXGBE_EICR_LSC))
1814 /* Check if this is due to overtemp */
1815 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1816 break;
1817 return;
1818 }
1819 default:
1820 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1821 return;
7ca647bd 1822 break;
119fc60a 1823 }
7ca647bd
JP		 1824 e_crit(drv,
1825 "Network adapter has been stopped because it has over heated. "
1826 "Restart the computer. If the problem persists, "
1827 "power off the system and replace the adapter\n");
1828 /* write to clear the interrupt */
1829 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
119fc60a
MC		 1830}
1831
0befdb3e
JB		 1832static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1833{
1834 struct ixgbe_hw *hw = &adapter->hw;
1835
1836 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1837 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1838 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1839 /* write to clear the interrupt */
1840 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1841 }
1842}
cf8280ee 1843
e8e26350
PW		 1844static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1845{
1846 struct ixgbe_hw *hw = &adapter->hw;
1847
73c4b7cd
AD		 1848 if (eicr & IXGBE_EICR_GPI_SDP2) {
1849 /* Clear the interrupt */
1850 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1851 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1852 schedule_work(&adapter->sfp_config_module_task);
1853 }
1854
e8e26350
PW		 1855 if (eicr & IXGBE_EICR_GPI_SDP1) {
1856 /* Clear the interrupt */
1857 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
73c4b7cd
AD		 1858 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1859 schedule_work(&adapter->multispeed_fiber_task);
e8e26350
PW		 1860 }
1861}
1862
cf8280ee
JB		 1863static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1864{
1865 struct ixgbe_hw *hw = &adapter->hw;
1866
1867 adapter->lsc_int++;
1868 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1869 adapter->link_check_timeout = jiffies;
1870 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1871 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1872 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1873 schedule_work(&adapter->watchdog_task);
1874 }
1875}
1876
9a799d71
AK		 1877static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1878{
1879 struct net_device *netdev = data;
1880 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1881 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1882 u32 eicr;
1883
1884 /*
1885 * Workaround for Silicon errata. Use clear-by-write instead
1886 * of clear-by-read. Reading with EICS will return the
1887 * interrupt causes without clearing, which later be done
1888 * with the write to EICR.
1889 */
1890 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1891 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1892
cf8280ee
JB		 1893 if (eicr & IXGBE_EICR_LSC)
1894 ixgbe_check_lsc(adapter);
d4f80882 1895
1cdd1ec8
GR		 1896 if (eicr & IXGBE_EICR_MAILBOX)
1897 ixgbe_msg_task(adapter);
1898
bd508178
AD		 1899 switch (hw->mac.type) {
1900 case ixgbe_mac_82599EB:
d994653d
DS		 1901 ixgbe_check_sfp_event(adapter, eicr);
1902 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1903 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1904 adapter->interrupt_event = eicr;
1905 schedule_work(&adapter->check_overtemp_task);
1906 }
1907 /* now fallthrough to handle Flow Director */
b93a2226 1908 case ixgbe_mac_X540:
c4cf55e5
PWJ		 1909 /* Handle Flow Director Full threshold interrupt */
1910 if (eicr & IXGBE_EICR_FLOW_DIR) {
1911 int i;
1912 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1913 /* Disable transmits before FDIR Re-initialization */
1914 netif_tx_stop_all_queues(netdev);
1915 for (i = 0; i < adapter->num_tx_queues; i++) {
1916 struct ixgbe_ring *tx_ring =
e8e9f696 1917 adapter->tx_ring[i];
7d637bcc
AD		 1918 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1919 &tx_ring->state))
c4cf55e5
PWJ		 1920 schedule_work(&adapter->fdir_reinit_task);
1921 }
1922 }
bd508178
AD		 1923 break;
1924 default:
1925 break;
c4cf55e5 1926 }
bd508178
AD		 1927
1928 ixgbe_check_fan_failure(adapter, eicr);
1929
d4f80882
AV		 1930 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1931 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1932
1933 return IRQ_HANDLED;
1934}
1935
fe49f04a
AD		 1936static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1937 u64 qmask)
1938{
1939 u32 mask;
bd508178 1940 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1941
bd508178
AD		 1942 switch (hw->mac.type) {
1943 case ixgbe_mac_82598EB:
fe49f04a 1944 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1945 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1946 break;
1947 case ixgbe_mac_82599EB:
b93a2226 1948 case ixgbe_mac_X540:
fe49f04a 1949 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1950 if (mask)
1951 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1952 mask = (qmask >> 32);
bd508178
AD		 1953 if (mask)
1954 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1955 break;
1956 default:
1957 break;
fe49f04a
AD		 1958 }
1959 /* skip the flush */
1960}
1961
1962static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1963 u64 qmask)
fe49f04a
AD		 1964{
1965 u32 mask;
bd508178 1966 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1967
bd508178
AD		 1968 switch (hw->mac.type) {
1969 case ixgbe_mac_82598EB:
fe49f04a 1970 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1971 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1972 break;
1973 case ixgbe_mac_82599EB:
b93a2226 1974 case ixgbe_mac_X540:
fe49f04a 1975 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1976 if (mask)
1977 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1978 mask = (qmask >> 32);
bd508178
AD		 1979 if (mask)
1980 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1981 break;
1982 default:
1983 break;
fe49f04a
AD		 1984 }
1985 /* skip the flush */
1986}
1987
9a799d71
AK		 1988static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1989{
021230d4
AV		 1990 struct ixgbe_q_vector *q_vector = data;
1991 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1992 struct ixgbe_ring *tx_ring;
021230d4
AV		 1993 int i, r_idx;
1994
1995 if (!q_vector->txr_count)
1996 return IRQ_HANDLED;
1997
1998 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1999 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2000 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 2001 tx_ring->total_bytes = 0;
2002 tx_ring->total_packets = 0;
021230d4 2003 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2004 r_idx + 1);
021230d4 2005 }
9a799d71 2006
9b471446 2007 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 2008 napi_schedule(&q_vector->napi);
2009
9a799d71
AK		 2010 return IRQ_HANDLED;
2011}
2012
021230d4
AV		 2013/**
2014 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2015 * @irq: unused
2016 * @data: pointer to our q_vector struct for this interrupt vector
2017 **/
9a799d71
AK		 2018static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2019{
021230d4
AV		 2020 struct ixgbe_q_vector *q_vector = data;
2021 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2022 struct ixgbe_ring *rx_ring;
021230d4 2023 int r_idx;
30efa5a3 2024 int i;
021230d4 2025
33cf09c9
AD		 2026#ifdef CONFIG_IXGBE_DCA
2027 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2028 ixgbe_update_dca(q_vector);
2029#endif
2030
021230d4 2031 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
33cf09c9 2032 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2033 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 2034 rx_ring->total_bytes = 0;
2035 rx_ring->total_packets = 0;
2036 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2037 r_idx + 1);
30efa5a3
JB		 2038 }
2039
021230d4
AV		 2040 if (!q_vector->rxr_count)
2041 return IRQ_HANDLED;
2042
9b471446 2043 /* EIAM disabled interrupts (on this vector) for us */
288379f0 2044 napi_schedule(&q_vector->napi);
021230d4
AV		 2045
2046 return IRQ_HANDLED;
2047}
2048
2049static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2050{
91281fd3
AD		 2051 struct ixgbe_q_vector *q_vector = data;
2052 struct ixgbe_adapter *adapter = q_vector->adapter;
2053 struct ixgbe_ring *ring;
2054 int r_idx;
2055 int i;
2056
2057 if (!q_vector->txr_count && !q_vector->rxr_count)
2058 return IRQ_HANDLED;
2059
2060 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2061 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2062 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2063 ring->total_bytes = 0;
2064 ring->total_packets = 0;
2065 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2066 r_idx + 1);
91281fd3
AD		 2067 }
2068
2069 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2070 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2071 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 2072 ring->total_bytes = 0;
2073 ring->total_packets = 0;
2074 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2075 r_idx + 1);
91281fd3
AD		 2076 }
2077
9b471446 2078 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2079 napi_schedule(&q_vector->napi);
9a799d71 2080
9a799d71
AK		 2081 return IRQ_HANDLED;
2082}
2083
021230d4
AV		 2084/**
2085 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2086 * @napi: napi struct with our devices info in it
2087 * @budget: amount of work driver is allowed to do this pass, in packets
2088 *
f0848276
JB		 2089 * This function is optimized for cleaning one queue only on a single
2090 * q_vector!!!
021230d4 2091 **/
9a799d71
AK		 2092static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2093{
021230d4 2094 struct ixgbe_q_vector *q_vector =
e8e9f696 2095 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2096 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 2097 struct ixgbe_ring *rx_ring = NULL;
9a799d71 2098 int work_done = 0;
021230d4 2099 long r_idx;
9a799d71 2100
5dd2d332 2101#ifdef CONFIG_IXGBE_DCA
bd0362dd 2102 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2103 ixgbe_update_dca(q_vector);
bd0362dd 2104#endif
9a799d71 2105
33cf09c9
AD		 2106 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2107 rx_ring = adapter->rx_ring[r_idx];
2108
78b6f4ce 2109 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 2110
021230d4
AV		 2111 /* If all Rx work done, exit the polling mode */
2112 if (work_done < budget) {
288379f0 2113 napi_complete(napi);
f7554a2b 2114 if (adapter->rx_itr_setting & 1)
f494e8fa 2115 ixgbe_set_itr_msix(q_vector);
9a799d71 2116 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2117 ixgbe_irq_enable_queues(adapter,
e8e9f696 2118 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 2119 }
2120
2121 return work_done;
2122}
2123
f0848276 2124/**
91281fd3 2125 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 2126 * @napi: napi struct with our devices info in it
2127 * @budget: amount of work driver is allowed to do this pass, in packets
2128 *
2129 * This function will clean more than one rx queue associated with a
2130 * q_vector.
2131 **/
91281fd3 2132static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 2133{
2134 struct ixgbe_q_vector *q_vector =
e8e9f696 2135 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 2136 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 2137 struct ixgbe_ring *ring = NULL;
f0848276
JB		 2138 int work_done = 0, i;
2139 long r_idx;
91281fd3
AD		 2140 bool tx_clean_complete = true;
2141
33cf09c9
AD		 2142#ifdef CONFIG_IXGBE_DCA
2143 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2144 ixgbe_update_dca(q_vector);
2145#endif
2146
91281fd3
AD		 2147 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2148 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2149 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2150 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2151 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2152 r_idx + 1);
91281fd3 2153 }
f0848276
JB		 2154
2155 /* attempt to distribute budget to each queue fairly, but don't allow
2156 * the budget to go below 1 because we'll exit polling */
2157 budget /= (q_vector->rxr_count ?: 1);
2158 budget = max(budget, 1);
2159 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2160 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2161 ring = adapter->rx_ring[r_idx];
91281fd3 2162 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 2163 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2164 r_idx + 1);
f0848276
JB		 2165 }
2166
2167 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 2168 ring = adapter->rx_ring[r_idx];
f0848276 2169 /* If all Rx work done, exit the polling mode */
7f821875 2170 if (work_done < budget) {
288379f0 2171 napi_complete(napi);
f7554a2b 2172 if (adapter->rx_itr_setting & 1)
f0848276
JB		 2173 ixgbe_set_itr_msix(q_vector);
2174 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2175 ixgbe_irq_enable_queues(adapter,
e8e9f696 2176 ((u64)1 << q_vector->v_idx));
f0848276
JB		 2177 return 0;
2178 }
2179
2180 return work_done;
2181}
91281fd3
AD		 2182
2183/**
2184 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2185 * @napi: napi struct with our devices info in it
2186 * @budget: amount of work driver is allowed to do this pass, in packets
2187 *
2188 * This function is optimized for cleaning one queue only on a single
2189 * q_vector!!!
2190 **/
2191static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2192{
2193 struct ixgbe_q_vector *q_vector =
e8e9f696 2194 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2195 struct ixgbe_adapter *adapter = q_vector->adapter;
2196 struct ixgbe_ring *tx_ring = NULL;
2197 int work_done = 0;
2198 long r_idx;
2199
91281fd3
AD		 2200#ifdef CONFIG_IXGBE_DCA
2201 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2202 ixgbe_update_dca(q_vector);
91281fd3
AD		 2203#endif
2204
33cf09c9
AD		 2205 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2206 tx_ring = adapter->tx_ring[r_idx];
2207
91281fd3
AD		 2208 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2209 work_done = budget;
2210
f7554a2b 2211 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2212 if (work_done < budget) {
2213 napi_complete(napi);
f7554a2b 2214 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2215 ixgbe_set_itr_msix(q_vector);
2216 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2217 ixgbe_irq_enable_queues(adapter,
2218 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2219 }
2220
2221 return work_done;
2222}
2223
021230d4 2224static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2225 int r_idx)
021230d4 2226{
7a921c93 2227 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2228 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93
AD		 2229
2230 set_bit(r_idx, q_vector->rxr_idx);
2231 q_vector->rxr_count++;
2274543f 2232 rx_ring->q_vector = q_vector;
021230d4
AV		 2233}
2234
2235static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2236 int t_idx)
021230d4 2237{
7a921c93 2238 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2239 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93
AD		 2240
2241 set_bit(t_idx, q_vector->txr_idx);
2242 q_vector->txr_count++;
2274543f 2243 tx_ring->q_vector = q_vector;
021230d4
AV		 2244}
2245
9a799d71 2246/**
021230d4
AV		 2247 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2248 * @adapter: board private structure to initialize
9a799d71 2249 *
021230d4
AV		 2250 * This function maps descriptor rings to the queue-specific vectors
2251 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2252 * one vector per ring/queue, but on a constrained vector budget, we
2253 * group the rings as "efficiently" as possible. You would add new
2254 * mapping configurations in here.
9a799d71 2255 **/
d0759ebb 2256static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2257{
d0759ebb 2258 int q_vectors;
021230d4
AV		 2259 int v_start = 0;
2260 int rxr_idx = 0, txr_idx = 0;
2261 int rxr_remaining = adapter->num_rx_queues;
2262 int txr_remaining = adapter->num_tx_queues;
2263 int i, j;
2264 int rqpv, tqpv;
2265 int err = 0;
2266
2267 /* No mapping required if MSI-X is disabled. */
2268 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2269 goto out;
9a799d71 2270
d0759ebb
AD		 2271 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2272
021230d4
AV		 2273 /*
2274 * The ideal configuration...
2275 * We have enough vectors to map one per queue.
2276 */
d0759ebb 2277 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
021230d4
AV		 2278 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2279 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2280
021230d4
AV		 2281 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2282 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2283
9a799d71 2284 goto out;
021230d4 2285 }
9a799d71 2286
021230d4
AV		 2287 /*
2288 * If we don't have enough vectors for a 1-to-1
2289 * mapping, we'll have to group them so there are
2290 * multiple queues per vector.
2291 */
2292 /* Re-adjusting *qpv takes care of the remainder. */
d0759ebb
AD		 2293 for (i = v_start; i < q_vectors; i++) {
2294 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
021230d4
AV		 2295 for (j = 0; j < rqpv; j++) {
2296 map_vector_to_rxq(adapter, i, rxr_idx);
2297 rxr_idx++;
2298 rxr_remaining--;
2299 }
d0759ebb 2300 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
021230d4
AV		 2301 for (j = 0; j < tqpv; j++) {
2302 map_vector_to_txq(adapter, i, txr_idx);
2303 txr_idx++;
2304 txr_remaining--;
9a799d71 2305 }
9a799d71 2306 }
021230d4
AV		 2307out:
2308 return err;
2309}
2310
2311/**
2312 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2313 * @adapter: board private structure
2314 *
2315 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2316 * interrupts from the kernel.
2317 **/
2318static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2319{
2320 struct net_device *netdev = adapter->netdev;
2321 irqreturn_t (*handler)(int, void *);
2322 int i, vector, q_vectors, err;
e8e9f696 2323 int ri = 0, ti = 0;
021230d4
AV		 2324
2325 /* Decrement for Other and TCP Timer vectors */
2326 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2327
d0759ebb 2328 err = ixgbe_map_rings_to_vectors(adapter);
021230d4 2329 if (err)
d0759ebb 2330 return err;
021230d4 2331
d0759ebb
AD		 2332#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2333 ? &ixgbe_msix_clean_many : \
2334 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2335 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2336 NULL)
021230d4 2337 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb
AD		 2338 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2339 handler = SET_HANDLER(q_vector);
cb13fc20 2340
e8e9f696 2341 if (handler == &ixgbe_msix_clean_rx) {
9fe93afd
DS		 2342 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2343 "%s-%s-%d", netdev->name, "rx", ri++);
e8e9f696 2344 } else if (handler == &ixgbe_msix_clean_tx) {
9fe93afd
DS		 2345 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2346 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb 2347 } else if (handler == &ixgbe_msix_clean_many) {
9fe93afd
DS		 2348 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2349 "%s-%s-%d", netdev->name, "TxRx", ri++);
32aa77a4 2350 ti++;
d0759ebb
AD		 2351 } else {
2352 /* skip this unused q_vector */
2353 continue;
32aa77a4 2354 }
021230d4 2355 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb
AD		 2356 handler, 0, q_vector->name,
2357 q_vector);
9a799d71 2358 if (err) {
396e799c 2359 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2360 "Error: %d\n", err);
021230d4 2361 goto free_queue_irqs;
9a799d71 2362 }
9a799d71
AK		 2363 }
2364
d0759ebb 2365 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
021230d4 2366 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb 2367 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
9a799d71 2368 if (err) {
396e799c 2369 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2370 goto free_queue_irqs;
9a799d71
AK		 2371 }
2372
9a799d71
AK		 2373 return 0;
2374
021230d4
AV		 2375free_queue_irqs:
2376 for (i = vector - 1; i >= 0; i--)
2377 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2378 adapter->q_vector[i]);
021230d4
AV		 2379 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2380 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2381 kfree(adapter->msix_entries);
2382 adapter->msix_entries = NULL;
9a799d71
AK		 2383 return err;
2384}
2385
f494e8fa
AV		 2386static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2387{
7a921c93 2388 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
4a0b9ca0
PW		 2389 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2390 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
125601bf
AD		 2391 u32 new_itr = q_vector->eitr;
2392 u8 current_itr;
f494e8fa 2393
30efa5a3 2394 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2395 q_vector->tx_itr,
2396 tx_ring->total_packets,
2397 tx_ring->total_bytes);
30efa5a3 2398 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2399 q_vector->rx_itr,
2400 rx_ring->total_packets,
2401 rx_ring->total_bytes);
f494e8fa 2402
30efa5a3 2403 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2404
2405 switch (current_itr) {
2406 /* counts and packets in update_itr are dependent on these numbers */
2407 case lowest_latency:
2408 new_itr = 100000;
2409 break;
2410 case low_latency:
2411 new_itr = 20000; /* aka hwitr = ~200 */
2412 break;
2413 case bulk_latency:
2414 new_itr = 8000;
2415 break;
2416 default:
2417 break;
2418 }
2419
2420 if (new_itr != q_vector->eitr) {
fe49f04a 2421 /* do an exponential smoothing */
125601bf 2422 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935 2423
125601bf 2424 /* save the algorithm value here */
509ee935 2425 q_vector->eitr = new_itr;
fe49f04a
AD		 2426
2427 ixgbe_write_eitr(q_vector);
f494e8fa 2428 }
f494e8fa
AV		 2429}
2430
79aefa45
AD		 2431/**
2432 * ixgbe_irq_enable - Enable default interrupt generation settings
2433 * @adapter: board private structure
2434 **/
6af3b9eb
ET		 2435static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2436 bool flush)
79aefa45
AD		 2437{
2438 u32 mask;
835462fc
NS		 2439
2440 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2441 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2442 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2443 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2444 mask |= IXGBE_EIMS_GPI_SDP1;
bd508178
AD		 2445 switch (adapter->hw.mac.type) {
2446 case ixgbe_mac_82599EB:
b93a2226 2447 case ixgbe_mac_X540:
2a41ff81 2448 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2449 mask |= IXGBE_EIMS_GPI_SDP1;
2450 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2451 if (adapter->num_vfs)
2452 mask |= IXGBE_EIMS_MAILBOX;
bd508178
AD		 2453 break;
2454 default:
2455 break;
e8e26350 2456 }
c4cf55e5
PWJ		 2457 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2458 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2459 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2460
79aefa45 2461 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2462 if (queues)
2463 ixgbe_irq_enable_queues(adapter, ~0);
2464 if (flush)
2465 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2466
2467 if (adapter->num_vfs > 32) {
2468 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2469 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2470 }
79aefa45 2471}
021230d4 2472
9a799d71 2473/**
021230d4 2474 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2475 * @irq: interrupt number
2476 * @data: pointer to a network interface device structure
9a799d71
AK		 2477 **/
2478static irqreturn_t ixgbe_intr(int irq, void *data)
2479{
2480 struct net_device *netdev = data;
2481 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2482 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2483 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2484 u32 eicr;
2485
54037505 2486 /*
6af3b9eb 2487 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2488 * before the read of EICR.
2489 */
2490 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2491
021230d4
AV		 2492 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2493 * therefore no explict interrupt disable is necessary */
2494 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2495 if (!eicr) {
6af3b9eb
ET		 2496 /*
2497 * shared interrupt alert!
f47cf66e 2498 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2499 * have disabled interrupts due to EIAM
2500 * finish the workaround of silicon errata on 82598. Unmask
2501 * the interrupt that we masked before the EICR read.
2502 */
2503 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2504 ixgbe_irq_enable(adapter, true, true);
9a799d71 2505 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2506 }
9a799d71 2507
cf8280ee
JB		 2508 if (eicr & IXGBE_EICR_LSC)
2509 ixgbe_check_lsc(adapter);
021230d4 2510
bd508178
AD		 2511 switch (hw->mac.type) {
2512 case ixgbe_mac_82599EB:
e8e26350 2513 ixgbe_check_sfp_event(adapter, eicr);
bd508178
AD		 2514 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2515 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2516 adapter->interrupt_event = eicr;
2517 schedule_work(&adapter->check_overtemp_task);
2518 }
2519 break;
2520 default:
2521 break;
2522 }
e8e26350 2523
0befdb3e
JB		 2524 ixgbe_check_fan_failure(adapter, eicr);
2525
7a921c93 2526 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2527 adapter->tx_ring[0]->total_packets = 0;
2528 adapter->tx_ring[0]->total_bytes = 0;
2529 adapter->rx_ring[0]->total_packets = 0;
2530 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2531 /* would disable interrupts here but EIAM disabled it */
7a921c93 2532 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2533 }
2534
6af3b9eb
ET		 2535 /*
2536 * re-enable link(maybe) and non-queue interrupts, no flush.
2537 * ixgbe_poll will re-enable the queue interrupts
2538 */
2539
2540 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2541 ixgbe_irq_enable(adapter, false, false);
2542
9a799d71
AK		 2543 return IRQ_HANDLED;
2544}
2545
021230d4
AV		 2546static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2547{
2548 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2549
2550 for (i = 0; i < q_vectors; i++) {
7a921c93 2551 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2552 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2553 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2554 q_vector->rxr_count = 0;
2555 q_vector->txr_count = 0;
2556 }
2557}
2558
9a799d71
AK		 2559/**
2560 * ixgbe_request_irq - initialize interrupts
2561 * @adapter: board private structure
2562 *
2563 * Attempts to configure interrupts using the best available
2564 * capabilities of the hardware and kernel.
2565 **/
021230d4 2566static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2567{
2568 struct net_device *netdev = adapter->netdev;
021230d4 2569 int err;
9a799d71 2570
021230d4
AV		 2571 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2572 err = ixgbe_request_msix_irqs(adapter);
2573 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2574 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2575 netdev->name, netdev);
021230d4 2576 } else {
a0607fd3 2577 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2578 netdev->name, netdev);
9a799d71
AK		 2579 }
2580
9a799d71 2581 if (err)
396e799c 2582 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2583
9a799d71
AK		 2584 return err;
2585}
2586
2587static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2588{
2589 struct net_device *netdev = adapter->netdev;
2590
2591 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2592 int i, q_vectors;
9a799d71 2593
021230d4
AV		 2594 q_vectors = adapter->num_msix_vectors;
2595
2596 i = q_vectors - 1;
9a799d71 2597 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2598
021230d4
AV		 2599 i--;
2600 for (; i >= 0; i--) {
894ff7cf
AD		 2601 /* free only the irqs that were actually requested */
2602 if (!adapter->q_vector[i]->rxr_count &&
2603 !adapter->q_vector[i]->txr_count)
2604 continue;
2605
021230d4 2606 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2607 adapter->q_vector[i]);
021230d4
AV		 2608 }
2609
2610 ixgbe_reset_q_vectors(adapter);
2611 } else {
2612 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2613 }
2614}
2615
22d5a71b
JB		 2616/**
2617 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2618 * @adapter: board private structure
2619 **/
2620static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2621{
bd508178
AD		 2622 switch (adapter->hw.mac.type) {
2623 case ixgbe_mac_82598EB:
835462fc 2624 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2625 break;
2626 case ixgbe_mac_82599EB:
b93a2226 2627 case ixgbe_mac_X540:
835462fc
NS		 2628 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2629 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2630 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2631 if (adapter->num_vfs > 32)
2632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
bd508178
AD		 2633 break;
2634 default:
2635 break;
22d5a71b
JB		 2636 }
2637 IXGBE_WRITE_FLUSH(&adapter->hw);
2638 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2639 int i;
2640 for (i = 0; i < adapter->num_msix_vectors; i++)
2641 synchronize_irq(adapter->msix_entries[i].vector);
2642 } else {
2643 synchronize_irq(adapter->pdev->irq);
2644 }
2645}
2646
9a799d71
AK		 2647/**
2648 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2649 *
2650 **/
2651static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2652{
9a799d71
AK		 2653 struct ixgbe_hw *hw = &adapter->hw;
2654
021230d4 2655 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2656 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2657
e8e26350
PW		 2658 ixgbe_set_ivar(adapter, 0, 0, 0);
2659 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2660
2661 map_vector_to_rxq(adapter, 0, 0);
2662 map_vector_to_txq(adapter, 0, 0);
2663
396e799c 2664 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2665}
2666
43e69bf0
AD		 2667/**
2668 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2669 * @adapter: board private structure
2670 * @ring: structure containing ring specific data
2671 *
2672 * Configure the Tx descriptor ring after a reset.
2673 **/
84418e3b
AD		 2674void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2675 struct ixgbe_ring *ring)
43e69bf0
AD		 2676{
2677 struct ixgbe_hw *hw = &adapter->hw;
2678 u64 tdba = ring->dma;
2f1860b8
AD		 2679 int wait_loop = 10;
2680 u32 txdctl;
bf29ee6c 2681 u8 reg_idx = ring->reg_idx;
43e69bf0 2682
2f1860b8
AD		 2683 /* disable queue to avoid issues while updating state */
2684 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2685 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2686 txdctl & ~IXGBE_TXDCTL_ENABLE);
2687 IXGBE_WRITE_FLUSH(hw);
2688
43e69bf0 2689 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2690 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2691 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2692 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2693 ring->count * sizeof(union ixgbe_adv_tx_desc));
2694 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2695 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2696 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2697
2f1860b8
AD		 2698 /* configure fetching thresholds */
2699 if (adapter->rx_itr_setting == 0) {
2700 /* cannot set wthresh when itr==0 */
2701 txdctl &= ~0x007F0000;
2702 } else {
2703 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2704 txdctl |= (8 << 16);
2705 }
2706 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2707 /* PThresh workaround for Tx hang with DFP enabled. */
2708 txdctl |= 32;
2709 }
2710
2711 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2712 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2713 adapter->atr_sample_rate) {
2714 ring->atr_sample_rate = adapter->atr_sample_rate;
2715 ring->atr_count = 0;
2716 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2717 } else {
2718 ring->atr_sample_rate = 0;
2719 }
2f1860b8 2720
c84d324c
JF		 2721 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2722
2f1860b8
AD		 2723 /* enable queue */
2724 txdctl |= IXGBE_TXDCTL_ENABLE;
2725 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2726
2727 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2728 if (hw->mac.type == ixgbe_mac_82598EB &&
2729 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2730 return;
2731
2732 /* poll to verify queue is enabled */
2733 do {
2734 msleep(1);
2735 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2736 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2737 if (!wait_loop)
2738 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2739}
2740
120ff942
AD		 2741static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2742{
2743 struct ixgbe_hw *hw = &adapter->hw;
2744 u32 rttdcs;
2745 u32 mask;
2746
2747 if (hw->mac.type == ixgbe_mac_82598EB)
2748 return;
2749
2750 /* disable the arbiter while setting MTQC */
2751 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2752 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2753 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2754
2755 /* set transmit pool layout */
2756 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2757 switch (adapter->flags & mask) {
2758
2759 case (IXGBE_FLAG_SRIOV_ENABLED):
2760 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2761 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2762 break;
2763
2764 case (IXGBE_FLAG_DCB_ENABLED):
2765 /* We enable 8 traffic classes, DCB only */
2766 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2767 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2768 break;
2769
2770 default:
2771 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2772 break;
2773 }
2774
2775 /* re-enable the arbiter */
2776 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2777 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2778}
2779
9a799d71 2780/**
3a581073 2781 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2782 * @adapter: board private structure
2783 *
2784 * Configure the Tx unit of the MAC after a reset.
2785 **/
2786static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2787{
2f1860b8
AD		 2788 struct ixgbe_hw *hw = &adapter->hw;
2789 u32 dmatxctl;
43e69bf0 2790 u32 i;
9a799d71 2791
2f1860b8
AD		 2792 ixgbe_setup_mtqc(adapter);
2793
2794 if (hw->mac.type != ixgbe_mac_82598EB) {
2795 /* DMATXCTL.EN must be before Tx queues are enabled */
2796 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2797 dmatxctl |= IXGBE_DMATXCTL_TE;
2798 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2799 }
2800
9a799d71 2801 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2802 for (i = 0; i < adapter->num_tx_queues; i++)
2803 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2804}
2805
e8e26350 2806#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2807
a6616b42 2808static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2809 struct ixgbe_ring *rx_ring)
cc41ac7c 2810{
cc41ac7c 2811 u32 srrctl;
bf29ee6c 2812 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2813
bd508178
AD		 2814 switch (adapter->hw.mac.type) {
2815 case ixgbe_mac_82598EB: {
2816 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2817 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2818 reg_idx = reg_idx & mask;
cc41ac7c 2819 }
bd508178
AD		 2820 break;
2821 case ixgbe_mac_82599EB:
b93a2226 2822 case ixgbe_mac_X540:
bd508178
AD		 2823 default:
2824 break;
2825 }
2826
bf29ee6c 2827 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2828
2829 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2830 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2831 if (adapter->num_vfs)
2832 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2833
afafd5b0
AD		 2834 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2835 IXGBE_SRRCTL_BSIZEHDR_MASK;
2836
7d637bcc 2837 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2838#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2839 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2840#else
2841 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2842#endif
cc41ac7c 2843 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2844 } else {
afafd5b0
AD		 2845 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2846 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2847 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2848 }
e8e26350 2849
bf29ee6c 2850 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2851}
9a799d71 2852
05abb126 2853static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2854{
05abb126
AD		 2855 struct ixgbe_hw *hw = &adapter->hw;
2856 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2857 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2858 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2859 u32 mrqc = 0, reta = 0;
2860 u32 rxcsum;
2861 int i, j;
0cefafad
JB		 2862 int mask;
2863
05abb126
AD		 2864 /* Fill out hash function seeds */
2865 for (i = 0; i < 10; i++)
2866 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2867
2868 /* Fill out redirection table */
2869 for (i = 0, j = 0; i < 128; i++, j++) {
2870 if (j == adapter->ring_feature[RING_F_RSS].indices)
2871 j = 0;
2872 /* reta = 4-byte sliding window of
2873 * 0x00..(indices-1)(indices-1)00..etc. */
2874 reta = (reta << 8) | (j * 0x11);
2875 if ((i & 3) == 3)
2876 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2877 }
0cefafad 2878
05abb126
AD		 2879 /* Disable indicating checksum in descriptor, enables RSS hash */
2880 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2881 rxcsum |= IXGBE_RXCSUM_PCSD;
2882 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2883
2884 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2885 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2886 else
2887 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2888#ifdef CONFIG_IXGBE_DCB
05abb126 2889 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2890#endif
05abb126
AD		 2891 | IXGBE_FLAG_SRIOV_ENABLED
2892 );
0cefafad
JB		 2893
2894 switch (mask) {
2895 case (IXGBE_FLAG_RSS_ENABLED):
2896 mrqc = IXGBE_MRQC_RSSEN;
2897 break;
1cdd1ec8
GR		 2898 case (IXGBE_FLAG_SRIOV_ENABLED):
2899 mrqc = IXGBE_MRQC_VMDQEN;
2900 break;
0cefafad
JB		 2901#ifdef CONFIG_IXGBE_DCB
2902 case (IXGBE_FLAG_DCB_ENABLED):
2903 mrqc = IXGBE_MRQC_RT8TCEN;
2904 break;
2905#endif /* CONFIG_IXGBE_DCB */
2906 default:
2907 break;
2908 }
2909
05abb126
AD		 2910 /* Perform hash on these packet types */
2911 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2912 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2913 | IXGBE_MRQC_RSS_FIELD_IPV6
2914 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2915
2916 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2917}
2918
b93a2226
DS		 2919/**
2920 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2921 * @adapter: address of board private structure
2922 * @ring: structure containing ring specific data
2923 **/
2924void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2925 struct ixgbe_ring *ring)
2926{
2927 struct ixgbe_hw *hw = &adapter->hw;
2928 u32 rscctrl;
2929 u8 reg_idx = ring->reg_idx;
2930
2931 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2932 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2933 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2934}
2935
bb5a9ad2
NS		 2936/**
2937 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2938 * @adapter: address of board private structure
2939 * @index: index of ring to set
bb5a9ad2 2940 **/
b93a2226 2941void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2942 struct ixgbe_ring *ring)
bb5a9ad2 2943{
bb5a9ad2 2944 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2945 u32 rscctrl;
edd2ea55 2946 int rx_buf_len;
bf29ee6c 2947 u8 reg_idx = ring->reg_idx;
7367096a 2948
7d637bcc 2949 if (!ring_is_rsc_enabled(ring))
7367096a 2950 return;
bb5a9ad2 2951
7367096a
AD		 2952 rx_buf_len = ring->rx_buf_len;
2953 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2954 rscctrl |= IXGBE_RSCCTL_RSCEN;
2955 /*
2956 * we must limit the number of descriptors so that the
2957 * total size of max desc * buf_len is not greater
2958 * than 65535
2959 */
7d637bcc 2960 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2961#if (MAX_SKB_FRAGS > 16)
2962 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2963#elif (MAX_SKB_FRAGS > 8)
2964 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2965#elif (MAX_SKB_FRAGS > 4)
2966 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2967#else
2968 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2969#endif
2970 } else {
2971 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2972 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2973 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2974 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2975 else
2976 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2977 }
7367096a 2978 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2979}
2980
9e10e045
AD		 2981/**
2982 * ixgbe_set_uta - Set unicast filter table address
2983 * @adapter: board private structure
2984 *
2985 * The unicast table address is a register array of 32-bit registers.
2986 * The table is meant to be used in a way similar to how the MTA is used
2987 * however due to certain limitations in the hardware it is necessary to
2988 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2989 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2990 **/
2991static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2992{
2993 struct ixgbe_hw *hw = &adapter->hw;
2994 int i;
2995
2996 /* The UTA table only exists on 82599 hardware and newer */
2997 if (hw->mac.type < ixgbe_mac_82599EB)
2998 return;
2999
3000 /* we only need to do this if VMDq is enabled */
3001 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3002 return;
3003
3004 for (i = 0; i < 128; i++)
3005 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3006}
3007
3008#define IXGBE_MAX_RX_DESC_POLL 10
3009static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3010 struct ixgbe_ring *ring)
3011{
3012 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3013 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3014 u32 rxdctl;
bf29ee6c 3015 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3016
3017 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3018 if (hw->mac.type == ixgbe_mac_82598EB &&
3019 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3020 return;
3021
3022 do {
3023 msleep(1);
3024 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3025 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3026
3027 if (!wait_loop) {
3028 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3029 "the polling period\n", reg_idx);
3030 }
3031}
3032
2d39d576
YZ		 3033void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3034 struct ixgbe_ring *ring)
3035{
3036 struct ixgbe_hw *hw = &adapter->hw;
3037 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3038 u32 rxdctl;
3039 u8 reg_idx = ring->reg_idx;
3040
3041 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3042 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3043
3044 /* write value back with RXDCTL.ENABLE bit cleared */
3045 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3046
3047 if (hw->mac.type == ixgbe_mac_82598EB &&
3048 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3049 return;
3050
3051 /* the hardware may take up to 100us to really disable the rx queue */
3052 do {
3053 udelay(10);
3054 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3055 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3056
3057 if (!wait_loop) {
3058 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3059 "the polling period\n", reg_idx);
3060 }
3061}
3062
84418e3b
AD		 3063void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3064 struct ixgbe_ring *ring)
acd37177
AD		 3065{
3066 struct ixgbe_hw *hw = &adapter->hw;
3067 u64 rdba = ring->dma;
9e10e045 3068 u32 rxdctl;
bf29ee6c 3069 u8 reg_idx = ring->reg_idx;
acd37177 3070
9e10e045
AD		 3071 /* disable queue to avoid issues while updating state */
3072 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3073 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3074
acd37177
AD		 3075 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3076 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3077 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3078 ring->count * sizeof(union ixgbe_adv_rx_desc));
3079 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3080 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3081 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3082
3083 ixgbe_configure_srrctl(adapter, ring);
3084 ixgbe_configure_rscctl(adapter, ring);
3085
e9f98072
GR		 3086 /* If operating in IOV mode set RLPML for X540 */
3087 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3088 hw->mac.type == ixgbe_mac_X540) {
3089 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3090 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3091 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3092 }
3093
9e10e045
AD		 3094 if (hw->mac.type == ixgbe_mac_82598EB) {
3095 /*
3096 * enable cache line friendly hardware writes:
3097 * PTHRESH=32 descriptors (half the internal cache),
3098 * this also removes ugly rx_no_buffer_count increment
3099 * HTHRESH=4 descriptors (to minimize latency on fetch)
3100 * WTHRESH=8 burst writeback up to two cache lines
3101 */
3102 rxdctl &= ~0x3FFFFF;
3103 rxdctl |= 0x080420;
3104 }
3105
3106 /* enable receive descriptor ring */
3107 rxdctl |= IXGBE_RXDCTL_ENABLE;
3108 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3109
3110 ixgbe_rx_desc_queue_enable(adapter, ring);
fc77dc3c 3111 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 3112}
3113
48654521
AD		 3114static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3115{
3116 struct ixgbe_hw *hw = &adapter->hw;
3117 int p;
3118
3119 /* PSRTYPE must be initialized in non 82598 adapters */
3120 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3121 IXGBE_PSRTYPE_UDPHDR |
3122 IXGBE_PSRTYPE_IPV4HDR |
48654521 3123 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3124 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3125
3126 if (hw->mac.type == ixgbe_mac_82598EB)
3127 return;
3128
3129 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3130 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3131
3132 for (p = 0; p < adapter->num_rx_pools; p++)
3133 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3134 psrtype);
3135}
3136
f5b4a52e
AD		 3137static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3138{
3139 struct ixgbe_hw *hw = &adapter->hw;
3140 u32 gcr_ext;
3141 u32 vt_reg_bits;
3142 u32 reg_offset, vf_shift;
3143 u32 vmdctl;
3144
3145 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3146 return;
3147
3148 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3149 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3150 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3151 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3152
3153 vf_shift = adapter->num_vfs % 32;
3154 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3155
3156 /* Enable only the PF's pool for Tx/Rx */
3157 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3158 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3159 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3160 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3161 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3162
3163 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3164 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3165
3166 /*
3167 * Set up VF register offsets for selected VT Mode,
3168 * i.e. 32 or 64 VFs for SR-IOV
3169 */
3170 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3171 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3172 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3173 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3174
3175 /* enable Tx loopback for VF/PF communication */
3176 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3
GR		 3177 /* Enable MAC Anti-Spoofing */
3178 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3179 adapter->num_vfs);
f5b4a52e
AD		 3180}
3181
477de6ed 3182static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3183{
9a799d71
AK		 3184 struct ixgbe_hw *hw = &adapter->hw;
3185 struct net_device *netdev = adapter->netdev;
3186 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3187 int rx_buf_len;
477de6ed
AD		 3188 struct ixgbe_ring *rx_ring;
3189 int i;
3190 u32 mhadd, hlreg0;
48654521 3191
9a799d71 3192 /* Decide whether to use packet split mode or not */
a124339a
DS		 3193 /* On by default */
3194 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3195
1cdd1ec8 3196 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 3197 if (adapter->num_vfs)
3198 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3199
3200 /* Disable packet split due to 82599 erratum #45 */
3201 if (hw->mac.type == ixgbe_mac_82599EB)
3202 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 3203
3204 /* Set the RX buffer length according to the mode */
3205 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 3206 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 3207 } else {
0c19d6af 3208 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 3209 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 3210 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 3211 else
477de6ed 3212 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 3213 }
3214
63f39bd1 3215#ifdef IXGBE_FCOE
477de6ed
AD		 3216 /* adjust max frame to be able to do baby jumbo for FCoE */
3217 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3218 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3219 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3220
477de6ed
AD		 3221#endif /* IXGBE_FCOE */
3222 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3223 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3224 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3225 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3226
3227 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3228 }
3229
3230 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3231 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3232 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3233 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3234
0cefafad
JB		 3235 /*
3236 * Setup the HW Rx Head and Tail Descriptor Pointers and
3237 * the Base and Length of the Rx Descriptor Ring
3238 */
9a799d71 3239 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3240 rx_ring = adapter->rx_ring[i];
a6616b42 3241 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3242
6e455b89 3243 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3244 set_ring_ps_enabled(rx_ring);
3245 else
3246 clear_ring_ps_enabled(rx_ring);
3247
3248 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3249 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3250 else
7d637bcc 3251 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3252
63f39bd1 3253#ifdef IXGBE_FCOE
e8e9f696 3254 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3255 struct ixgbe_ring_feature *f;
3256 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3257 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3258 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3259 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3260 rx_ring->rx_buf_len =
e8e9f696 3261 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3262 } else if (!ring_is_rsc_enabled(rx_ring) &&
3263 !ring_is_ps_enabled(rx_ring)) {
3264 rx_ring->rx_buf_len =
3265 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3266 }
63f39bd1 3267 }
63f39bd1 3268#endif /* IXGBE_FCOE */
477de6ed 3269 }
477de6ed
AD		 3270}
3271
7367096a
AD		 3272static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3273{
3274 struct ixgbe_hw *hw = &adapter->hw;
3275 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3276
3277 switch (hw->mac.type) {
3278 case ixgbe_mac_82598EB:
3279 /*
3280 * For VMDq support of different descriptor types or
3281 * buffer sizes through the use of multiple SRRCTL
3282 * registers, RDRXCTL.MVMEN must be set to 1
3283 *
3284 * also, the manual doesn't mention it clearly but DCA hints
3285 * will only use queue 0's tags unless this bit is set. Side
3286 * effects of setting this bit are only that SRRCTL must be
3287 * fully programmed [0..15]
3288 */
3289 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3290 break;
3291 case ixgbe_mac_82599EB:
b93a2226 3292 case ixgbe_mac_X540:
7367096a
AD		 3293 /* Disable RSC for ACK packets */
3294 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3295 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3296 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3297 /* hardware requires some bits to be set by default */
3298 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3299 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3300 break;
3301 default:
3302 /* We should do nothing since we don't know this hardware */
3303 return;
3304 }
3305
3306 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3307}
3308
477de6ed
AD		 3309/**
3310 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3311 * @adapter: board private structure
3312 *
3313 * Configure the Rx unit of the MAC after a reset.
3314 **/
3315static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3316{
3317 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3318 int i;
3319 u32 rxctrl;
477de6ed
AD		 3320
3321 /* disable receives while setting up the descriptors */
3322 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3323 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3324
3325 ixgbe_setup_psrtype(adapter);
7367096a 3326 ixgbe_setup_rdrxctl(adapter);
477de6ed 3327
9e10e045 3328 /* Program registers for the distribution of queues */
f5b4a52e 3329 ixgbe_setup_mrqc(adapter);
f5b4a52e 3330
9e10e045
AD		 3331 ixgbe_set_uta(adapter);
3332
477de6ed
AD		 3333 /* set_rx_buffer_len must be called before ring initialization */
3334 ixgbe_set_rx_buffer_len(adapter);
3335
3336 /*
3337 * Setup the HW Rx Head and Tail Descriptor Pointers and
3338 * the Base and Length of the Rx Descriptor Ring
3339 */
9e10e045
AD		 3340 for (i = 0; i < adapter->num_rx_queues; i++)
3341 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3342
9e10e045
AD		 3343 /* disable drop enable for 82598 parts */
3344 if (hw->mac.type == ixgbe_mac_82598EB)
3345 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3346
3347 /* enable all receives */
3348 rxctrl |= IXGBE_RXCTRL_RXEN;
3349 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3350}
3351
068c89b0
DS		 3352static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3353{
3354 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3355 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3356 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3357
3358 /* add VID to filter table */
1ada1b1b 3359 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3360 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3361}
3362
3363static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3364{
3365 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3366 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3367 int pool_ndx = adapter->num_vfs;
068c89b0 3368
068c89b0 3369 /* remove VID from filter table */
1ada1b1b 3370 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3371 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3372}
3373
5f6c0181
JB		 3374/**
3375 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3376 * @adapter: driver data
3377 */
3378static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3379{
3380 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3381 u32 vlnctrl;
3382
3383 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3384 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3385 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3386}
3387
3388/**
3389 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3390 * @adapter: driver data
3391 */
3392static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3393{
3394 struct ixgbe_hw *hw = &adapter->hw;
3395 u32 vlnctrl;
3396
3397 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3398 vlnctrl |= IXGBE_VLNCTRL_VFE;
3399 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3400 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3401}
3402
3403/**
3404 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3405 * @adapter: driver data
3406 */
3407static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3408{
3409 struct ixgbe_hw *hw = &adapter->hw;
3410 u32 vlnctrl;
5f6c0181
JB		 3411 int i, j;
3412
3413 switch (hw->mac.type) {
3414 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3415 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3416 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3417 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3418 break;
3419 case ixgbe_mac_82599EB:
b93a2226 3420 case ixgbe_mac_X540:
5f6c0181
JB		 3421 for (i = 0; i < adapter->num_rx_queues; i++) {
3422 j = adapter->rx_ring[i]->reg_idx;
3423 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3424 vlnctrl &= ~IXGBE_RXDCTL_VME;
3425 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3426 }
3427 break;
3428 default:
3429 break;
3430 }
3431}
3432
3433/**
f62bbb5e 3434 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3435 * @adapter: driver data
3436 */
f62bbb5e 3437static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3438{
3439 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3440 u32 vlnctrl;
5f6c0181
JB		 3441 int i, j;
3442
3443 switch (hw->mac.type) {
3444 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3445 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3446 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3447 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3448 break;
3449 case ixgbe_mac_82599EB:
b93a2226 3450 case ixgbe_mac_X540:
5f6c0181
JB		 3451 for (i = 0; i < adapter->num_rx_queues; i++) {
3452 j = adapter->rx_ring[i]->reg_idx;
3453 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3454 vlnctrl |= IXGBE_RXDCTL_VME;
3455 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3456 }
3457 break;
3458 default:
3459 break;
3460 }
3461}
3462
9a799d71
AK		 3463static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3464{
f62bbb5e 3465 u16 vid;
9a799d71 3466
f62bbb5e
JG		 3467 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3468
3469 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3470 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3471}
3472
2850062a
AD		 3473/**
3474 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3475 * @netdev: network interface device structure
3476 *
3477 * Writes unicast address list to the RAR table.
3478 * Returns: -ENOMEM on failure/insufficient address space
3479 * 0 on no addresses written
3480 * X on writing X addresses to the RAR table
3481 **/
3482static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3483{
3484 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3485 struct ixgbe_hw *hw = &adapter->hw;
3486 unsigned int vfn = adapter->num_vfs;
3487 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3488 int count = 0;
3489
3490 /* return ENOMEM indicating insufficient memory for addresses */
3491 if (netdev_uc_count(netdev) > rar_entries)
3492 return -ENOMEM;
3493
3494 if (!netdev_uc_empty(netdev) && rar_entries) {
3495 struct netdev_hw_addr *ha;
3496 /* return error if we do not support writing to RAR table */
3497 if (!hw->mac.ops.set_rar)
3498 return -ENOMEM;
3499
3500 netdev_for_each_uc_addr(ha, netdev) {
3501 if (!rar_entries)
3502 break;
3503 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3504 vfn, IXGBE_RAH_AV);
3505 count++;
3506 }
3507 }
3508 /* write the addresses in reverse order to avoid write combining */
3509 for (; rar_entries > 0 ; rar_entries--)
3510 hw->mac.ops.clear_rar(hw, rar_entries);
3511
3512 return count;
3513}
3514
9a799d71 3515/**
2c5645cf 3516 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3517 * @netdev: network interface device structure
3518 *
2c5645cf
CL		 3519 * The set_rx_method entry point is called whenever the unicast/multicast
3520 * address list or the network interface flags are updated. This routine is
3521 * responsible for configuring the hardware for proper unicast, multicast and
3522 * promiscuous mode.
9a799d71 3523 **/
7f870475 3524void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3525{
3526 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3527 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3528 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3529 int count;
9a799d71
AK		 3530
3531 /* Check for Promiscuous and All Multicast modes */
3532
3533 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3534
f5dc442b
AD		 3535 /* set all bits that we expect to always be set */
3536 fctrl |= IXGBE_FCTRL_BAM;
3537 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3538 fctrl |= IXGBE_FCTRL_PMCF;
3539
2850062a
AD		 3540 /* clear the bits we are changing the status of */
3541 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3542
9a799d71 3543 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3544 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3545 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3546 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3547 /* don't hardware filter vlans in promisc mode */
3548 ixgbe_vlan_filter_disable(adapter);
9a799d71 3549 } else {
746b9f02
PM		 3550 if (netdev->flags & IFF_ALLMULTI) {
3551 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3552 vmolr |= IXGBE_VMOLR_MPE;
3553 } else {
3554 /*
3555 * Write addresses to the MTA, if the attempt fails
3556 * then we should just turn on promiscous mode so
3557 * that we can at least receive multicast traffic
3558 */
3559 hw->mac.ops.update_mc_addr_list(hw, netdev);
3560 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3561 }
5f6c0181 3562 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3563 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3564 /*
3565 * Write addresses to available RAR registers, if there is not
3566 * sufficient space to store all the addresses then enable
3567 * unicast promiscous mode
3568 */
3569 count = ixgbe_write_uc_addr_list(netdev);
3570 if (count < 0) {
3571 fctrl |= IXGBE_FCTRL_UPE;
3572 vmolr |= IXGBE_VMOLR_ROPE;
3573 }
9a799d71
AK		 3574 }
3575
2850062a 3576 if (adapter->num_vfs) {
1cdd1ec8 3577 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3578 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3579 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3580 IXGBE_VMOLR_ROPE);
3581 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3582 }
3583
3584 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3585
3586 if (netdev->features & NETIF_F_HW_VLAN_RX)
3587 ixgbe_vlan_strip_enable(adapter);
3588 else
3589 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3590}
3591
021230d4
AV		 3592static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3593{
3594 int q_idx;
3595 struct ixgbe_q_vector *q_vector;
3596 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3597
3598 /* legacy and MSI only use one vector */
3599 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3600 q_vectors = 1;
3601
3602 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3603 struct napi_struct *napi;
7a921c93 3604 q_vector = adapter->q_vector[q_idx];
f0848276 3605 napi = &q_vector->napi;
91281fd3
AD		 3606 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3607 if (!q_vector->rxr_count || !q_vector->txr_count) {
3608 if (q_vector->txr_count == 1)
3609 napi->poll = &ixgbe_clean_txonly;
3610 else if (q_vector->rxr_count == 1)
3611 napi->poll = &ixgbe_clean_rxonly;
3612 }
3613 }
f0848276
JB		 3614
3615 napi_enable(napi);
021230d4
AV		 3616 }
3617}
3618
3619static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3620{
3621 int q_idx;
3622 struct ixgbe_q_vector *q_vector;
3623 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3624
3625 /* legacy and MSI only use one vector */
3626 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3627 q_vectors = 1;
3628
3629 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3630 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3631 napi_disable(&q_vector->napi);
3632 }
3633}
3634
7a6b6f51 3635#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3636/*
3637 * ixgbe_configure_dcb - Configure DCB hardware
3638 * @adapter: ixgbe adapter struct
3639 *
3640 * This is called by the driver on open to configure the DCB hardware.
3641 * This is also called by the gennetlink interface when reconfiguring
3642 * the DCB state.
3643 */
3644static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3645{
3646 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3647 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3648
67ebd791
AD		 3649 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3650 if (hw->mac.type == ixgbe_mac_82598EB)
3651 netif_set_gso_max_size(adapter->netdev, 65536);
3652 return;
3653 }
3654
3655 if (hw->mac.type == ixgbe_mac_82598EB)
3656 netif_set_gso_max_size(adapter->netdev, 32768);
3657
9806307a
JF		 3658#ifdef CONFIG_FCOE
3659 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3660 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3661#endif
3662
80ab193d 3663 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3664 DCB_TX_CONFIG);
80ab193d 3665 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3666 DCB_RX_CONFIG);
2f90b865 3667
2f90b865 3668 /* Enable VLAN tag insert/strip */
f62bbb5e 3669 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3670
2f90b865 3671 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3672
3673 /* reconfigure the hardware */
3674 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
2f90b865
AD		 3675}
3676
3677#endif
9a799d71
AK		 3678static void ixgbe_configure(struct ixgbe_adapter *adapter)
3679{
3680 struct net_device *netdev = adapter->netdev;
c4cf55e5 3681 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3682 int i;
3683
7a6b6f51 3684#ifdef CONFIG_IXGBE_DCB
67ebd791 3685 ixgbe_configure_dcb(adapter);
2f90b865 3686#endif
9a799d71 3687
f62bbb5e
JG		 3688 ixgbe_set_rx_mode(netdev);
3689 ixgbe_restore_vlan(adapter);
3690
eacd73f7
YZ		 3691#ifdef IXGBE_FCOE
3692 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3693 ixgbe_configure_fcoe(adapter);
3694
3695#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3696 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3697 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3698 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3699 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3700 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3701 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3702 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3703 }
933d41f1 3704 ixgbe_configure_virtualization(adapter);
c4cf55e5 3705
9a799d71
AK		 3706 ixgbe_configure_tx(adapter);
3707 ixgbe_configure_rx(adapter);
9a799d71
AK		 3708}
3709
e8e26350
PW		 3710static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3711{
3712 switch (hw->phy.type) {
3713 case ixgbe_phy_sfp_avago:
3714 case ixgbe_phy_sfp_ftl:
3715 case ixgbe_phy_sfp_intel:
3716 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3717 case ixgbe_phy_sfp_passive_tyco:
3718 case ixgbe_phy_sfp_passive_unknown:
3719 case ixgbe_phy_sfp_active_unknown:
3720 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3721 return true;
3722 default:
3723 return false;
3724 }
3725}
3726
0ecc061d 3727/**
e8e26350
PW		 3728 * ixgbe_sfp_link_config - set up SFP+ link
3729 * @adapter: pointer to private adapter struct
3730 **/
3731static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3732{
3733 struct ixgbe_hw *hw = &adapter->hw;
3734
3735 if (hw->phy.multispeed_fiber) {
3736 /*
3737 * In multispeed fiber setups, the device may not have
3738 * had a physical connection when the driver loaded.
3739 * If that's the case, the initial link configuration
3740 * couldn't get the MAC into 10G or 1G mode, so we'll
3741 * never have a link status change interrupt fire.
3742 * We need to try and force an autonegotiation
3743 * session, then bring up link.
3744 */
4c7e604b
AG		 3745 if (hw->mac.ops.setup_sfp)
3746 hw->mac.ops.setup_sfp(hw);
e8e26350
PW		 3747 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3748 schedule_work(&adapter->multispeed_fiber_task);
3749 } else {
3750 /*
3751 * Direct Attach Cu and non-multispeed fiber modules
3752 * still need to be configured properly prior to
3753 * attempting link.
3754 */
3755 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3756 schedule_work(&adapter->sfp_config_module_task);
3757 }
3758}
3759
3760/**
3761 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3762 * @hw: pointer to private hardware struct
3763 *
3764 * Returns 0 on success, negative on failure
3765 **/
e8e26350 3766static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3767{
3768 u32 autoneg;
8620a103 3769 bool negotiation, link_up = false;
0ecc061d
PWJ		 3770 u32 ret = IXGBE_ERR_LINK_SETUP;
3771
3772 if (hw->mac.ops.check_link)
3773 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3774
3775 if (ret)
3776 goto link_cfg_out;
3777
0b0c2b31
ET		 3778 autoneg = hw->phy.autoneg_advertised;
3779 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3780 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3781 &negotiation);
0ecc061d
PWJ		 3782 if (ret)
3783 goto link_cfg_out;
3784
8620a103
MC		 3785 if (hw->mac.ops.setup_link)
3786 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3787link_cfg_out:
3788 return ret;
3789}
3790
a34bcfff 3791static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3792{
9a799d71 3793 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3794 u32 gpie = 0;
9a799d71 3795
9b471446 3796 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3797 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3798 IXGBE_GPIE_OCD;
3799 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3800 /*
3801 * use EIAM to auto-mask when MSI-X interrupt is asserted
3802 * this saves a register write for every interrupt
3803 */
3804 switch (hw->mac.type) {
3805 case ixgbe_mac_82598EB:
3806 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3807 break;
9b471446 3808 case ixgbe_mac_82599EB:
b93a2226
DS		 3809 case ixgbe_mac_X540:
3810 default:
9b471446
JB		 3811 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3812 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3813 break;
3814 }
3815 } else {
021230d4
AV		 3816 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3817 * specifically only auto mask tx and rx interrupts */
3818 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3819 }
9a799d71 3820
a34bcfff
AD		 3821 /* XXX: to interrupt immediately for EICS writes, enable this */
3822 /* gpie |= IXGBE_GPIE_EIMEN; */
3823
3824 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3825 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3826 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3827 }
3828
a34bcfff
AD		 3829 /* Enable fan failure interrupt */
3830 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3831 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3832
a34bcfff 3833 if (hw->mac.type == ixgbe_mac_82599EB)
e8e26350
PW		 3834 gpie |= IXGBE_SDP1_GPIEN;
3835 gpie |= IXGBE_SDP2_GPIEN;
a34bcfff
AD		 3836
3837 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3838}
3839
3840static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3841{
3842 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3843 int err;
a34bcfff
AD		 3844 u32 ctrl_ext;
3845
3846 ixgbe_get_hw_control(adapter);
3847 ixgbe_setup_gpie(adapter);
e8e26350 3848
9a799d71
AK		 3849 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3850 ixgbe_configure_msix(adapter);
3851 else
3852 ixgbe_configure_msi_and_legacy(adapter);
3853
c6ecf39a
DS		 3854 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3855 if (hw->mac.ops.enable_tx_laser &&
3856 ((hw->phy.multispeed_fiber) ||
9f911707 3857 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3858 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3859 hw->mac.ops.enable_tx_laser(hw);
3860
9a799d71 3861 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3862 ixgbe_napi_enable_all(adapter);
3863
73c4b7cd
AD		 3864 if (ixgbe_is_sfp(hw)) {
3865 ixgbe_sfp_link_config(adapter);
3866 } else {
3867 err = ixgbe_non_sfp_link_config(hw);
3868 if (err)
3869 e_err(probe, "link_config FAILED %d\n", err);
3870 }
3871
021230d4
AV		 3872 /* clear any pending interrupts, may auto mask */
3873 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3874 ixgbe_irq_enable(adapter, true, true);
9a799d71 3875
bf069c97
DS		 3876 /*
3877 * If this adapter has a fan, check to see if we had a failure
3878 * before we enabled the interrupt.
3879 */
3880 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3881 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3882 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3883 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3884 }
3885
e8e26350
PW		 3886 /*
3887 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3888 * arrived before interrupts were enabled but after probe. Such
3889 * devices wouldn't have their type identified yet. We need to
3890 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3891 * If we're not hot-pluggable SFP+, we just need to configure link
3892 * and bring it up.
3893 */
21cc5b4f 3894 if (hw->phy.type == ixgbe_phy_none)
73c4b7cd 3895 schedule_work(&adapter->sfp_config_module_task);
0ecc061d 3896
1da100bb 3897 /* enable transmits */
477de6ed 3898 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3899
9a799d71
AK		 3900 /* bring the link up in the watchdog, this could race with our first
3901 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3902 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3903 adapter->link_check_timeout = jiffies;
9a799d71 3904 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3905
3906 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3907 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3908 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3909 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3910
9a799d71
AK		 3911 return 0;
3912}
3913
d4f80882
AV		 3914void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3915{
3916 WARN_ON(in_interrupt());
3917 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3918 msleep(1);
3919 ixgbe_down(adapter);
5809a1ae
GR		 3920 /*
3921 * If SR-IOV enabled then wait a bit before bringing the adapter
3922 * back up to give the VFs time to respond to the reset. The
3923 * two second wait is based upon the watchdog timer cycle in
3924 * the VF driver.
3925 */
3926 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3927 msleep(2000);
d4f80882
AV		 3928 ixgbe_up(adapter);
3929 clear_bit(__IXGBE_RESETTING, &adapter->state);
3930}
3931
9a799d71
AK		 3932int ixgbe_up(struct ixgbe_adapter *adapter)
3933{
3934 /* hardware has been reset, we need to reload some things */
3935 ixgbe_configure(adapter);
3936
3937 return ixgbe_up_complete(adapter);
3938}
3939
3940void ixgbe_reset(struct ixgbe_adapter *adapter)
3941{
c44ade9e 3942 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3943 int err;
3944
3945 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3946 switch (err) {
3947 case 0:
3948 case IXGBE_ERR_SFP_NOT_PRESENT:
3949 break;
3950 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3951 e_dev_err("master disable timed out\n");
da4dd0f7 3952 break;
794caeb2
PWJ		 3953 case IXGBE_ERR_EEPROM_VERSION:
3954 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3955 e_dev_warn("This device is a pre-production adapter/LOM. "
3956 "Please be aware there may be issuesassociated with "
3957 "your hardware. If you are experiencing problems "
3958 "please contact your Intel or hardware "
3959 "representative who provided you with this "
3960 "hardware.\n");
794caeb2 3961 break;
da4dd0f7 3962 default:
849c4542 3963 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3964 }
9a799d71
AK		 3965
3966 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3967 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3968 IXGBE_RAH_AV);
9a799d71
AK		 3969}
3970
9a799d71
AK		 3971/**
3972 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3973 * @rx_ring: ring to free buffers from
3974 **/
b6ec895e 3975static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3976{
b6ec895e 3977 struct device *dev = rx_ring->dev;
9a799d71 3978 unsigned long size;
b6ec895e 3979 u16 i;
9a799d71 3980
84418e3b
AD		 3981 /* ring already cleared, nothing to do */
3982 if (!rx_ring->rx_buffer_info)
3983 return;
9a799d71 3984
84418e3b 3985 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3986 for (i = 0; i < rx_ring->count; i++) {
3987 struct ixgbe_rx_buffer *rx_buffer_info;
3988
3989 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3990 if (rx_buffer_info->dma) {
b6ec895e 3991 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 3992 rx_ring->rx_buf_len,
1b507730 3993 DMA_FROM_DEVICE);
9a799d71
AK		 3994 rx_buffer_info->dma = 0;
3995 }
3996 if (rx_buffer_info->skb) {
f8212f97 3997 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3998 rx_buffer_info->skb = NULL;
f8212f97
AD		 3999 do {
4000 struct sk_buff *this = skb;
e8171aaa 4001 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 4002 dma_unmap_single(dev,
1b507730 4003 IXGBE_RSC_CB(this)->dma,
e8e9f696 4004 rx_ring->rx_buf_len,
1b507730 4005 DMA_FROM_DEVICE);
fd3686a8 4006 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 4007 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 4008 }
f8212f97
AD		 4009 skb = skb->prev;
4010 dev_kfree_skb(this);
4011 } while (skb);
9a799d71
AK		 4012 }
4013 if (!rx_buffer_info->page)
4014 continue;
4f57ca6e 4015 if (rx_buffer_info->page_dma) {
b6ec895e 4016 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 4017 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 4018 rx_buffer_info->page_dma = 0;
4019 }
9a799d71
AK		 4020 put_page(rx_buffer_info->page);
4021 rx_buffer_info->page = NULL;
762f4c57 4022 rx_buffer_info->page_offset = 0;
9a799d71
AK		 4023 }
4024
4025 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4026 memset(rx_ring->rx_buffer_info, 0, size);
4027
4028 /* Zero out the descriptor ring */
4029 memset(rx_ring->desc, 0, rx_ring->size);
4030
4031 rx_ring->next_to_clean = 0;
4032 rx_ring->next_to_use = 0;
9a799d71
AK		 4033}
4034
4035/**
4036 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4037 * @tx_ring: ring to be cleaned
4038 **/
b6ec895e 4039static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4040{
4041 struct ixgbe_tx_buffer *tx_buffer_info;
4042 unsigned long size;
b6ec895e 4043 u16 i;
9a799d71 4044
84418e3b
AD		 4045 /* ring already cleared, nothing to do */
4046 if (!tx_ring->tx_buffer_info)
4047 return;
9a799d71 4048
84418e3b 4049 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4050 for (i = 0; i < tx_ring->count; i++) {
4051 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4052 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4053 }
4054
4055 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4056 memset(tx_ring->tx_buffer_info, 0, size);
4057
4058 /* Zero out the descriptor ring */
4059 memset(tx_ring->desc, 0, tx_ring->size);
4060
4061 tx_ring->next_to_use = 0;
4062 tx_ring->next_to_clean = 0;
9a799d71
AK		 4063}
4064
4065/**
021230d4 4066 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4067 * @adapter: board private structure
4068 **/
021230d4 4069static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4070{
4071 int i;
4072
021230d4 4073 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4074 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4075}
4076
4077/**
021230d4 4078 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4079 * @adapter: board private structure
4080 **/
021230d4 4081static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4082{
4083 int i;
4084
021230d4 4085 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4086 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4087}
4088
4089void ixgbe_down(struct ixgbe_adapter *adapter)
4090{
4091 struct net_device *netdev = adapter->netdev;
7f821875 4092 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4093 u32 rxctrl;
7f821875 4094 u32 txdctl;
bf29ee6c 4095 int i;
b25ebfd2 4096 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 4097
4098 /* signal that we are down to the interrupt handler */
4099 set_bit(__IXGBE_DOWN, &adapter->state);
4100
767081ad
GR		 4101 /* disable receive for all VFs and wait one second */
4102 if (adapter->num_vfs) {
767081ad
GR		 4103 /* ping all the active vfs to let them know we are going down */
4104 ixgbe_ping_all_vfs(adapter);
581d1aa7 4105
767081ad
GR		 4106 /* Disable all VFTE/VFRE TX/RX */
4107 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 4108
4109 /* Mark all the VFs as inactive */
4110 for (i = 0 ; i < adapter->num_vfs; i++)
4111 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 4112 }
4113
9a799d71 4114 /* disable receives */
7f821875
JB		 4115 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4116 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4117
2d39d576
YZ		 4118 /* disable all enabled rx queues */
4119 for (i = 0; i < adapter->num_rx_queues; i++)
4120 /* this call also flushes the previous write */
4121 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4122
9a799d71
AK		 4123 msleep(10);
4124
7f821875
JB		 4125 netif_tx_stop_all_queues(netdev);
4126
0a1f87cb
DS		 4127 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4128 del_timer_sync(&adapter->sfp_timer);
9a799d71 4129 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 4130 cancel_work_sync(&adapter->watchdog_task);
9a799d71 4131
c0dfb90e
JF		 4132 netif_carrier_off(netdev);
4133 netif_tx_disable(netdev);
4134
4135 ixgbe_irq_disable(adapter);
4136
4137 ixgbe_napi_disable_all(adapter);
4138
b25ebfd2
PW		 4139 /* Cleanup the affinity_hint CPU mask memory and callback */
4140 for (i = 0; i < num_q_vectors; i++) {
4141 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4142 /* clear the affinity_mask in the IRQ descriptor */
4143 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4144 /* release the CPU mask memory */
4145 free_cpumask_var(q_vector->affinity_mask);
4146 }
4147
c4cf55e5
PWJ		 4148 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4149 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4150 cancel_work_sync(&adapter->fdir_reinit_task);
4151
119fc60a
MC		 4152 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4153 cancel_work_sync(&adapter->check_overtemp_task);
4154
7f821875
JB		 4155 /* disable transmits in the hardware now that interrupts are off */
4156 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c
AD		 4157 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4158 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4159 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
e8e9f696 4160 (txdctl & ~IXGBE_TXDCTL_ENABLE));
7f821875 4161 }
88512539 4162 /* Disable the Tx DMA engine on 82599 */
bd508178
AD		 4163 switch (hw->mac.type) {
4164 case ixgbe_mac_82599EB:
b93a2226 4165 case ixgbe_mac_X540:
88512539 4166 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4167 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4168 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4169 break;
4170 default:
4171 break;
4172 }
7f821875 4173
9a713e7c
PW		 4174 /* clear n-tuple filters that are cached */
4175 ethtool_ntuple_flush(netdev);
4176
6f4a0e45
PL		 4177 if (!pci_channel_offline(adapter->pdev))
4178 ixgbe_reset(adapter);
c6ecf39a
DS		 4179
4180 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4181 if (hw->mac.ops.disable_tx_laser &&
4182 ((hw->phy.multispeed_fiber) ||
9f911707 4183 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4184 (hw->mac.type == ixgbe_mac_82599EB))))
4185 hw->mac.ops.disable_tx_laser(hw);
4186
9a799d71
AK		 4187 ixgbe_clean_all_tx_rings(adapter);
4188 ixgbe_clean_all_rx_rings(adapter);
4189
5dd2d332 4190#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4191 /* since we reset the hardware DCA settings were cleared */
e35ec126 4192 ixgbe_setup_dca(adapter);
96b0e0f6 4193#endif
9a799d71
AK		 4194}
4195
9a799d71 4196/**
021230d4
AV		 4197 * ixgbe_poll - NAPI Rx polling callback
4198 * @napi: structure for representing this polling device
4199 * @budget: how many packets driver is allowed to clean
4200 *
4201 * This function is used for legacy and MSI, NAPI mode
9a799d71 4202 **/
021230d4 4203static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4204{
9a1a69ad 4205 struct ixgbe_q_vector *q_vector =
e8e9f696 4206 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4207 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 4208 int tx_clean_complete, work_done = 0;
9a799d71 4209
5dd2d332 4210#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4211 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4212 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4213#endif
4214
4a0b9ca0
PW		 4215 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4216 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 4217
9a1a69ad 4218 if (!tx_clean_complete)
d2c7ddd6
DM		 4219 work_done = budget;
4220
53e52c72
DM		 4221 /* If budget not fully consumed, exit the polling mode */
4222 if (work_done < budget) {
288379f0 4223 napi_complete(napi);
f7554a2b 4224 if (adapter->rx_itr_setting & 1)
f494e8fa 4225 ixgbe_set_itr(adapter);
d4f80882 4226 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 4227 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 4228 }
9a799d71
AK		 4229 return work_done;
4230}
4231
4232/**
4233 * ixgbe_tx_timeout - Respond to a Tx Hang
4234 * @netdev: network interface device structure
4235 **/
4236static void ixgbe_tx_timeout(struct net_device *netdev)
4237{
4238 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4239
c84d324c
JF		 4240 adapter->tx_timeout_count++;
4241
9a799d71
AK		 4242 /* Do the reset outside of interrupt context */
4243 schedule_work(&adapter->reset_task);
4244}
4245
4246static void ixgbe_reset_task(struct work_struct *work)
4247{
4248 struct ixgbe_adapter *adapter;
4249 adapter = container_of(work, struct ixgbe_adapter, reset_task);
4250
2f90b865
AD		 4251 /* If we're already down or resetting, just bail */
4252 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4253 test_bit(__IXGBE_RESETTING, &adapter->state))
4254 return;
4255
dcd79aeb
TI		 4256 ixgbe_dump(adapter);
4257 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 4258 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4259}
4260
4df10466
JB		 4261/**
4262 * ixgbe_set_rss_queues: Allocate queues for RSS
4263 * @adapter: board private structure to initialize
4264 *
4265 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4266 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4267 *
4268 **/
bc97114d
PWJ		 4269static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4270{
4271 bool ret = false;
0cefafad 4272 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4273
4274 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4275 f->mask = 0xF;
4276 adapter->num_rx_queues = f->indices;
4277 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4278 ret = true;
4279 } else {
bc97114d 4280 ret = false;
b9804972
JB		 4281 }
4282
bc97114d
PWJ		 4283 return ret;
4284}
4285
c4cf55e5
PWJ		 4286/**
4287 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4288 * @adapter: board private structure to initialize
4289 *
4290 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4291 * to the original CPU that initiated the Tx session. This runs in addition
4292 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4293 * Rx load across CPUs using RSS.
4294 *
4295 **/
e8e9f696 4296static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4297{
4298 bool ret = false;
4299 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4300
4301 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4302 f_fdir->mask = 0;
4303
4304 /* Flow Director must have RSS enabled */
4305 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4306 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4307 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4308 adapter->num_tx_queues = f_fdir->indices;
4309 adapter->num_rx_queues = f_fdir->indices;
4310 ret = true;
4311 } else {
4312 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4313 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4314 }
4315 return ret;
4316}
4317
0331a832
YZ		 4318#ifdef IXGBE_FCOE
4319/**
4320 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4321 * @adapter: board private structure to initialize
4322 *
4323 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4324 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4325 * rx queues out of the max number of rx queues, instead, it is used as the
4326 * index of the first rx queue used by FCoE.
4327 *
4328 **/
4329static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4330{
0331a832
YZ		 4331 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4332
e5b64635
JF		 4333 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4334 return false;
4335
4336 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
0331a832 4337#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4338 int tc;
4339 struct net_device *dev = adapter->netdev;
4340
4341 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4342 f->indices = dev->tc_to_txq[tc].count;
4343 f->mask = dev->tc_to_txq[tc].offset;
0331a832 4344#endif
e5b64635
JF		 4345 } else {
4346 f->indices = min((int)num_online_cpus(), f->indices);
4347
4348 adapter->num_rx_queues = 1;
4349 adapter->num_tx_queues = 1;
4350
0331a832 4351 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 4352 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 4353 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4354 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4355 ixgbe_set_fdir_queues(adapter);
4356 else
4357 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 4358 }
4359 /* adding FCoE rx rings to the end */
4360 f->mask = adapter->num_rx_queues;
4361 adapter->num_rx_queues += f->indices;
8de8b2e6 4362 adapter->num_tx_queues += f->indices;
e5b64635 4363 }
0331a832 4364
e5b64635
JF		 4365 return true;
4366}
4367#endif /* IXGBE_FCOE */
4368
4369#ifdef CONFIG_IXGBE_DCB
4370static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4371{
4372 bool ret = false;
4373 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4374 int i, q;
4375
4376 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4377 return ret;
4378
4379 f->indices = 0;
4380 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
4381 q = min((int)num_online_cpus(), MAX_TRAFFIC_CLASS);
4382 f->indices += q;
0331a832
YZ		 4383 }
4384
e5b64635
JF		 4385 f->mask = 0x7 << 3;
4386 adapter->num_rx_queues = f->indices;
4387 adapter->num_tx_queues = f->indices;
4388 ret = true;
4389
4390#ifdef IXGBE_FCOE
4391 /* FCoE enabled queues require special configuration done through
4392 * configure_fcoe() and others. Here we map FCoE indices onto the
4393 * DCB queue pairs allowing FCoE to own configuration later.
4394 */
4395 ixgbe_set_fcoe_queues(adapter);
4396#endif
4397
0331a832
YZ		 4398 return ret;
4399}
e5b64635 4400#endif
0331a832 4401
1cdd1ec8
GR		 4402/**
4403 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4404 * @adapter: board private structure to initialize
4405 *
4406 * IOV doesn't actually use anything, so just NAK the
4407 * request for now and let the other queue routines
4408 * figure out what to do.
4409 */
4410static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4411{
4412 return false;
4413}
4414
4df10466
JB		 4415/*
4416 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4417 * @adapter: board private structure to initialize
4418 *
4419 * This is the top level queue allocation routine. The order here is very
4420 * important, starting with the "most" number of features turned on at once,
4421 * and ending with the smallest set of features. This way large combinations
4422 * can be allocated if they're turned on, and smaller combinations are the
4423 * fallthrough conditions.
4424 *
4425 **/
847f53ff 4426static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4427{
1cdd1ec8
GR		 4428 /* Start with base case */
4429 adapter->num_rx_queues = 1;
4430 adapter->num_tx_queues = 1;
4431 adapter->num_rx_pools = adapter->num_rx_queues;
4432 adapter->num_rx_queues_per_pool = 1;
4433
4434 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4435 goto done;
1cdd1ec8 4436
bc97114d
PWJ		 4437#ifdef CONFIG_IXGBE_DCB
4438 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4439 goto done;
bc97114d
PWJ		 4440
4441#endif
e5b64635
JF		 4442#ifdef IXGBE_FCOE
4443 if (ixgbe_set_fcoe_queues(adapter))
4444 goto done;
4445
4446#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4447 if (ixgbe_set_fdir_queues(adapter))
4448 goto done;
4449
bc97114d 4450 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4451 goto done;
4452
4453 /* fallback to base case */
4454 adapter->num_rx_queues = 1;
4455 adapter->num_tx_queues = 1;
4456
4457done:
847f53ff 4458 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4459 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4460 return netif_set_real_num_rx_queues(adapter->netdev,
4461 adapter->num_rx_queues);
b9804972
JB		 4462}
4463
021230d4 4464static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4465 int vectors)
021230d4
AV		 4466{
4467 int err, vector_threshold;
4468
4469 /* We'll want at least 3 (vector_threshold):
4470 * 1) TxQ[0] Cleanup
4471 * 2) RxQ[0] Cleanup
4472 * 3) Other (Link Status Change, etc.)
4473 * 4) TCP Timer (optional)
4474 */
4475 vector_threshold = MIN_MSIX_COUNT;
4476
4477 /* The more we get, the more we will assign to Tx/Rx Cleanup
4478 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4479 * Right now, we simply care about how many we'll get; we'll
4480 * set them up later while requesting irq's.
4481 */
4482 while (vectors >= vector_threshold) {
4483 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4484 vectors);
021230d4
AV		 4485 if (!err) /* Success in acquiring all requested vectors. */
4486 break;
4487 else if (err < 0)
4488 vectors = 0; /* Nasty failure, quit now */
4489 else /* err == number of vectors we should try again with */
4490 vectors = err;
4491 }
4492
4493 if (vectors < vector_threshold) {
4494 /* Can't allocate enough MSI-X interrupts? Oh well.
4495 * This just means we'll go with either a single MSI
4496 * vector or fall back to legacy interrupts.
4497 */
849c4542
ET		 4498 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4499 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4500 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4501 kfree(adapter->msix_entries);
4502 adapter->msix_entries = NULL;
021230d4
AV		 4503 } else {
4504 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4505 /*
4506 * Adjust for only the vectors we'll use, which is minimum
4507 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4508 * vectors we were allocated.
4509 */
4510 adapter->num_msix_vectors = min(vectors,
e8e9f696 4511 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4512 }
4513}
4514
021230d4 4515/**
bc97114d 4516 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4517 * @adapter: board private structure to initialize
4518 *
bc97114d
PWJ		 4519 * Cache the descriptor ring offsets for RSS to the assigned rings.
4520 *
021230d4 4521 **/
bc97114d 4522static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4523{
bc97114d 4524 int i;
bc97114d 4525
9d6b758f
AD		 4526 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4527 return false;
bc97114d 4528
9d6b758f
AD		 4529 for (i = 0; i < adapter->num_rx_queues; i++)
4530 adapter->rx_ring[i]->reg_idx = i;
4531 for (i = 0; i < adapter->num_tx_queues; i++)
4532 adapter->tx_ring[i]->reg_idx = i;
4533
4534 return true;
bc97114d
PWJ		 4535}
4536
4537#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4538
4539/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4540void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4541 unsigned int *tx, unsigned int *rx)
4542{
4543 struct net_device *dev = adapter->netdev;
4544 struct ixgbe_hw *hw = &adapter->hw;
4545 u8 num_tcs = netdev_get_num_tc(dev);
4546
4547 *tx = 0;
4548 *rx = 0;
4549
4550 switch (hw->mac.type) {
4551 case ixgbe_mac_82598EB:
4552 *tx = tc << 3;
4553 *rx = tc << 2;
4554 break;
4555 case ixgbe_mac_82599EB:
4556 case ixgbe_mac_X540:
4557 if (num_tcs == 8) {
4558 if (tc < 3) {
4559 *tx = tc << 5;
4560 *rx = tc << 4;
4561 } else if (tc < 5) {
4562 *tx = ((tc + 2) << 4);
4563 *rx = tc << 4;
4564 } else if (tc < num_tcs) {
4565 *tx = ((tc + 8) << 3);
4566 *rx = tc << 4;
4567 }
4568 } else if (num_tcs == 4) {
4569 *rx = tc << 5;
4570 switch (tc) {
4571 case 0:
4572 *tx = 0;
4573 break;
4574 case 1:
4575 *tx = 64;
4576 break;
4577 case 2:
4578 *tx = 96;
4579 break;
4580 case 3:
4581 *tx = 112;
4582 break;
4583 default:
4584 break;
4585 }
4586 }
4587 break;
4588 default:
4589 break;
4590 }
4591}
4592
4593#define IXGBE_MAX_Q_PER_TC (IXGBE_MAX_DCB_INDICES / MAX_TRAFFIC_CLASS)
4594
4595/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
4596 * classes.
4597 *
4598 * @netdev: net device to configure
4599 * @tc: number of traffic classes to enable
4600 */
4601int ixgbe_setup_tc(struct net_device *dev, u8 tc)
4602{
4603 int i;
4604 unsigned int q, offset = 0;
4605
4606 if (!tc) {
4607 netdev_reset_tc(dev);
4608 } else {
4609 if (netdev_set_num_tc(dev, tc))
4610 return -EINVAL;
4611
4612 /* Partition Tx queues evenly amongst traffic classes */
4613 for (i = 0; i < tc; i++) {
4614 q = min((int)num_online_cpus(), IXGBE_MAX_Q_PER_TC);
4615 netdev_set_prio_tc_map(dev, i, i);
4616 netdev_set_tc_queue(dev, i, q, offset);
4617 offset += q;
4618 }
4619 }
4620 return 0;
4621}
4622
bc97114d
PWJ		 4623/**
4624 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4625 * @adapter: board private structure to initialize
4626 *
4627 * Cache the descriptor ring offsets for DCB to the assigned rings.
4628 *
4629 **/
4630static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4631{
e5b64635
JF		 4632 struct net_device *dev = adapter->netdev;
4633 int i, j, k;
4634 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4635
bd508178
AD		 4636 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4637 return false;
f92ef202 4638
e5b64635
JF		 4639 for (i = 0, k = 0; i < num_tcs; i++) {
4640 unsigned int tx_s, rx_s;
4641 u16 count = dev->tc_to_txq[i].count;
4642
4643 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4644 for (j = 0; j < count; j++, k++) {
4645 adapter->tx_ring[k]->reg_idx = tx_s + j;
4646 adapter->rx_ring[k]->reg_idx = rx_s + j;
4647 adapter->tx_ring[k]->dcb_tc = i;
4648 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4649 }
021230d4 4650 }
e5b64635
JF		 4651
4652 return true;
bc97114d
PWJ		 4653}
4654#endif
4655
c4cf55e5
PWJ		 4656/**
4657 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4658 * @adapter: board private structure to initialize
4659 *
4660 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4661 *
4662 **/
e8e9f696 4663static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4664{
4665 int i;
4666 bool ret = false;
4667
4668 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4669 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4670 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4671 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4672 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4673 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4674 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4675 ret = true;
4676 }
4677
4678 return ret;
4679}
4680
0331a832
YZ		 4681#ifdef IXGBE_FCOE
4682/**
4683 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4684 * @adapter: board private structure to initialize
4685 *
4686 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4687 *
4688 */
4689static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4690{
0331a832 4691 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4692 int i;
4693 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4694
4695 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4696 return false;
0331a832 4697
bf29ee6c
AD		 4698 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4699 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4700 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4701 ixgbe_cache_ring_fdir(adapter);
4702 else
4703 ixgbe_cache_ring_rss(adapter);
8faa2a78 4704
bf29ee6c
AD		 4705 fcoe_rx_i = f->mask;
4706 fcoe_tx_i = f->mask;
0331a832 4707 }
bf29ee6c
AD		 4708 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4709 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4710 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4711 }
4712 return true;
0331a832
YZ		 4713}
4714
4715#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4716/**
4717 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4718 * @adapter: board private structure to initialize
4719 *
4720 * SR-IOV doesn't use any descriptor rings but changes the default if
4721 * no other mapping is used.
4722 *
4723 */
4724static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4725{
4a0b9ca0
PW		 4726 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4727 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4728 if (adapter->num_vfs)
4729 return true;
4730 else
4731 return false;
4732}
4733
bc97114d
PWJ		 4734/**
4735 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4736 * @adapter: board private structure to initialize
4737 *
4738 * Once we know the feature-set enabled for the device, we'll cache
4739 * the register offset the descriptor ring is assigned to.
4740 *
4741 * Note, the order the various feature calls is important. It must start with
4742 * the "most" features enabled at the same time, then trickle down to the
4743 * least amount of features turned on at once.
4744 **/
4745static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4746{
4747 /* start with default case */
4a0b9ca0
PW		 4748 adapter->rx_ring[0]->reg_idx = 0;
4749 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4750
1cdd1ec8
GR		 4751 if (ixgbe_cache_ring_sriov(adapter))
4752 return;
4753
e5b64635
JF		 4754#ifdef CONFIG_IXGBE_DCB
4755 if (ixgbe_cache_ring_dcb(adapter))
4756 return;
4757#endif
4758
0331a832
YZ		 4759#ifdef IXGBE_FCOE
4760 if (ixgbe_cache_ring_fcoe(adapter))
4761 return;
0331a832 4762#endif /* IXGBE_FCOE */
bc97114d 4763
c4cf55e5
PWJ		 4764 if (ixgbe_cache_ring_fdir(adapter))
4765 return;
4766
bc97114d
PWJ		 4767 if (ixgbe_cache_ring_rss(adapter))
4768 return;
021230d4
AV		 4769}
4770
9a799d71
AK		 4771/**
4772 * ixgbe_alloc_queues - Allocate memory for all rings
4773 * @adapter: board private structure to initialize
4774 *
4775 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4776 * number of queues at compile-time. The polling_netdev array is
4777 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4778 **/
2f90b865 4779static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4780{
e2ddeba9 4781 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4782
e2ddeba9
ED		 4783 if (nid < 0 || !node_online(nid))
4784 nid = first_online_node;
4785
4786 for (; tx < adapter->num_tx_queues; tx++) {
4787 struct ixgbe_ring *ring;
4788
4789 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4790 if (!ring)
e2ddeba9 4791 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4792 if (!ring)
e2ddeba9 4793 goto err_allocation;
4a0b9ca0 4794 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4795 ring->queue_index = tx;
4796 ring->numa_node = nid;
b6ec895e 4797 ring->dev = &adapter->pdev->dev;
fc77dc3c 4798 ring->netdev = adapter->netdev;
4a0b9ca0 4799
e2ddeba9 4800 adapter->tx_ring[tx] = ring;
021230d4 4801 }
b9804972 4802
e2ddeba9
ED		 4803 for (; rx < adapter->num_rx_queues; rx++) {
4804 struct ixgbe_ring *ring;
4a0b9ca0 4805
e2ddeba9 4806 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4807 if (!ring)
e2ddeba9 4808 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4809 if (!ring)
e2ddeba9
ED		 4810 goto err_allocation;
4811 ring->count = adapter->rx_ring_count;
4812 ring->queue_index = rx;
4813 ring->numa_node = nid;
b6ec895e 4814 ring->dev = &adapter->pdev->dev;
fc77dc3c 4815 ring->netdev = adapter->netdev;
4a0b9ca0 4816
e2ddeba9 4817 adapter->rx_ring[rx] = ring;
021230d4
AV		 4818 }
4819
4820 ixgbe_cache_ring_register(adapter);
4821
4822 return 0;
4823
e2ddeba9
ED		 4824err_allocation:
4825 while (tx)
4826 kfree(adapter->tx_ring[--tx]);
4827
4828 while (rx)
4829 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4830 return -ENOMEM;
4831}
4832
4833/**
4834 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4835 * @adapter: board private structure to initialize
4836 *
4837 * Attempt to configure the interrupts using the best available
4838 * capabilities of the hardware and the kernel.
4839 **/
feea6a57 4840static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4841{
8be0e467 4842 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4843 int err = 0;
4844 int vector, v_budget;
4845
4846 /*
4847 * It's easy to be greedy for MSI-X vectors, but it really
4848 * doesn't do us much good if we have a lot more vectors
4849 * than CPU's. So let's be conservative and only ask for
342bde1b 4850 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4851 */
4852 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4853 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4854
4855 /*
4856 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4857 * hw.mac->max_msix_vectors vectors. With features
4858 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4859 * descriptor queues supported by our device. Thus, we cap it off in
4860 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4861 */
8be0e467 4862 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4863
4864 /* A failure in MSI-X entry allocation isn't fatal, but it does
4865 * mean we disable MSI-X capabilities of the adapter. */
4866 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4867 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4868 if (adapter->msix_entries) {
4869 for (vector = 0; vector < v_budget; vector++)
4870 adapter->msix_entries[vector].entry = vector;
021230d4 4871
7a921c93 4872 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4873
7a921c93
AD		 4874 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4875 goto out;
4876 }
26d27844 4877
7a921c93
AD		 4878 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4879 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
45b9f509
AD		 4880 if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4881 IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4882 e_err(probe,
4883 "Flow Director is not supported while multiple "
4884 "queues are disabled. Disabling Flow Director\n");
4885 }
c4cf55e5
PWJ		 4886 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4887 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4888 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4889 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4890 ixgbe_disable_sriov(adapter);
4891
847f53ff
BH		 4892 err = ixgbe_set_num_queues(adapter);
4893 if (err)
4894 return err;
021230d4 4895
021230d4
AV		 4896 err = pci_enable_msi(adapter->pdev);
4897 if (!err) {
4898 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4899 } else {
849c4542
ET		 4900 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4901 "Unable to allocate MSI interrupt, "
4902 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4903 /* reset err */
4904 err = 0;
4905 }
4906
4907out:
021230d4
AV		 4908 return err;
4909}
4910
7a921c93
AD		 4911/**
4912 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4913 * @adapter: board private structure to initialize
4914 *
4915 * We allocate one q_vector per queue interrupt. If allocation fails we
4916 * return -ENOMEM.
4917 **/
4918static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4919{
4920 int q_idx, num_q_vectors;
4921 struct ixgbe_q_vector *q_vector;
7a921c93
AD		 4922 int (*poll)(struct napi_struct *, int);
4923
4924 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4925 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4926 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4927 } else {
4928 num_q_vectors = 1;
7a921c93
AD		 4929 poll = &ixgbe_poll;
4930 }
4931
4932 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4933 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4934 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4935 if (!q_vector)
4936 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4937 GFP_KERNEL);
7a921c93
AD		 4938 if (!q_vector)
4939 goto err_out;
4940 q_vector->adapter = adapter;
f7554a2b
NS		 4941 if (q_vector->txr_count && !q_vector->rxr_count)
4942 q_vector->eitr = adapter->tx_eitr_param;
4943 else
4944 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4945 q_vector->v_idx = q_idx;
91281fd3 4946 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4947 adapter->q_vector[q_idx] = q_vector;
4948 }
4949
4950 return 0;
4951
4952err_out:
4953 while (q_idx) {
4954 q_idx--;
4955 q_vector = adapter->q_vector[q_idx];
4956 netif_napi_del(&q_vector->napi);
4957 kfree(q_vector);
4958 adapter->q_vector[q_idx] = NULL;
4959 }
4960 return -ENOMEM;
4961}
4962
4963/**
4964 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4965 * @adapter: board private structure to initialize
4966 *
4967 * This function frees the memory allocated to the q_vectors. In addition if
4968 * NAPI is enabled it will delete any references to the NAPI struct prior
4969 * to freeing the q_vector.
4970 **/
4971static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4972{
4973 int q_idx, num_q_vectors;
7a921c93 4974
91281fd3 4975 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4976 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4977 else
7a921c93 4978 num_q_vectors = 1;
7a921c93
AD		 4979
4980 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4981 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4982 adapter->q_vector[q_idx] = NULL;
91281fd3 4983 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4984 kfree(q_vector);
4985 }
4986}
4987
7b25cdba 4988static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4989{
4990 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4991 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4992 pci_disable_msix(adapter->pdev);
4993 kfree(adapter->msix_entries);
4994 adapter->msix_entries = NULL;
4995 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4996 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4997 pci_disable_msi(adapter->pdev);
4998 }
021230d4
AV		 4999}
5000
5001/**
5002 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5003 * @adapter: board private structure to initialize
5004 *
5005 * We determine which interrupt scheme to use based on...
5006 * - Kernel support (MSI, MSI-X)
5007 * - which can be user-defined (via MODULE_PARAM)
5008 * - Hardware queue count (num_*_queues)
5009 * - defined by miscellaneous hardware support/features (RSS, etc.)
5010 **/
2f90b865 5011int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 5012{
5013 int err;
5014
5015 /* Number of supported queues */
847f53ff
BH		 5016 err = ixgbe_set_num_queues(adapter);
5017 if (err)
5018 return err;
021230d4 5019
021230d4
AV		 5020 err = ixgbe_set_interrupt_capability(adapter);
5021 if (err) {
849c4542 5022 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 5023 goto err_set_interrupt;
9a799d71
AK		 5024 }
5025
7a921c93
AD		 5026 err = ixgbe_alloc_q_vectors(adapter);
5027 if (err) {
849c4542 5028 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 5029 goto err_alloc_q_vectors;
5030 }
5031
5032 err = ixgbe_alloc_queues(adapter);
5033 if (err) {
849c4542 5034 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 5035 goto err_alloc_queues;
5036 }
5037
849c4542 5038 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 5039 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5040 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 5041
5042 set_bit(__IXGBE_DOWN, &adapter->state);
5043
9a799d71 5044 return 0;
021230d4 5045
7a921c93
AD		 5046err_alloc_queues:
5047 ixgbe_free_q_vectors(adapter);
5048err_alloc_q_vectors:
5049 ixgbe_reset_interrupt_capability(adapter);
021230d4 5050err_set_interrupt:
7a921c93
AD		 5051 return err;
5052}
5053
1a51502b
ED		 5054static void ring_free_rcu(struct rcu_head *head)
5055{
5056 kfree(container_of(head, struct ixgbe_ring, rcu));
5057}
5058
7a921c93
AD		 5059/**
5060 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5061 * @adapter: board private structure to clear interrupt scheme on
5062 *
5063 * We go through and clear interrupt specific resources and reset the structure
5064 * to pre-load conditions
5065 **/
5066void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5067{
4a0b9ca0
PW		 5068 int i;
5069
5070 for (i = 0; i < adapter->num_tx_queues; i++) {
5071 kfree(adapter->tx_ring[i]);
5072 adapter->tx_ring[i] = NULL;
5073 }
5074 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 5075 struct ixgbe_ring *ring = adapter->rx_ring[i];
5076
5077 /* ixgbe_get_stats64() might access this ring, we must wait
5078 * a grace period before freeing it.
5079 */
5080 call_rcu(&ring->rcu, ring_free_rcu);
4a0b9ca0
PW		 5081 adapter->rx_ring[i] = NULL;
5082 }
7a921c93 5083
b8eb3a10
DS		 5084 adapter->num_tx_queues = 0;
5085 adapter->num_rx_queues = 0;
5086
7a921c93
AD		 5087 ixgbe_free_q_vectors(adapter);
5088 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5089}
5090
c4900be0
DS		 5091/**
5092 * ixgbe_sfp_timer - worker thread to find a missing module
5093 * @data: pointer to our adapter struct
5094 **/
5095static void ixgbe_sfp_timer(unsigned long data)
5096{
5097 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5098
4df10466
JB		 5099 /*
5100 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 5101 * delays that sfp+ detection requires
5102 */
5103 schedule_work(&adapter->sfp_task);
5104}
5105
5106/**
5107 * ixgbe_sfp_task - worker thread to find a missing module
5108 * @work: pointer to work_struct containing our data
5109 **/
5110static void ixgbe_sfp_task(struct work_struct *work)
5111{
5112 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5113 struct ixgbe_adapter,
5114 sfp_task);
c4900be0
DS		 5115 struct ixgbe_hw *hw = &adapter->hw;
5116
5117 if ((hw->phy.type == ixgbe_phy_nl) &&
5118 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
5119 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5120 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 5121 goto reschedule;
5122 ret = hw->phy.ops.reset(hw);
5123 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5124 e_dev_err("failed to initialize because an unsupported "
5125 "SFP+ module type was detected.\n");
5126 e_dev_err("Reload the driver after installing a "
5127 "supported module.\n");
c4900be0
DS		 5128 unregister_netdev(adapter->netdev);
5129 } else {
396e799c 5130 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 5131 }
5132 /* don't need this routine any more */
5133 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5134 }
5135 return;
5136reschedule:
5137 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
5138 mod_timer(&adapter->sfp_timer,
e8e9f696 5139 round_jiffies(jiffies + (2 * HZ)));
c4900be0
DS		 5140}
5141
9a799d71
AK		 5142/**
5143 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5144 * @adapter: board private structure to initialize
5145 *
5146 * ixgbe_sw_init initializes the Adapter private data structure.
5147 * Fields are initialized based on PCI device information and
5148 * OS network device settings (MTU size).
5149 **/
5150static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5151{
5152 struct ixgbe_hw *hw = &adapter->hw;
5153 struct pci_dev *pdev = adapter->pdev;
9a713e7c 5154 struct net_device *dev = adapter->netdev;
021230d4 5155 unsigned int rss;
7a6b6f51 5156#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5157 int j;
5158 struct tc_configuration *tc;
5159#endif
16b61beb 5160 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 5161
c44ade9e
JB		 5162 /* PCI config space info */
5163
5164 hw->vendor_id = pdev->vendor;
5165 hw->device_id = pdev->device;
5166 hw->revision_id = pdev->revision;
5167 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5168 hw->subsystem_device_id = pdev->subsystem_device;
5169
021230d4
AV		 5170 /* Set capability flags */
5171 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5172 adapter->ring_feature[RING_F_RSS].indices = rss;
5173 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 5174 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bd508178
AD		 5175 switch (hw->mac.type) {
5176 case ixgbe_mac_82598EB:
bf069c97
DS		 5177 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5178 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5179 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178
AD		 5180 break;
5181 case ixgbe_mac_82599EB:
b93a2226 5182 case ixgbe_mac_X540:
e8e26350 5183 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5184 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5185 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5186 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5187 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5188 /* n-tuple support exists, always init our spinlock */
5189 spin_lock_init(&adapter->fdir_perfect_lock);
5190 /* Flow Director hash filters enabled */
5191 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5192 adapter->atr_sample_rate = 20;
c4cf55e5 5193 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5194 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 5195 adapter->fdir_pballoc = 0;
eacd73f7 5196#ifdef IXGBE_FCOE
0d551589
YZ		 5197 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5198 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5199 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5200#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 5201 /* Default traffic class to use for FCoE */
5202 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 5203 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5204#endif
eacd73f7 5205#endif /* IXGBE_FCOE */
bd508178
AD		 5206 break;
5207 default:
5208 break;
f8212f97 5209 }
2f90b865 5210
7a6b6f51 5211#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5212 /* Configure DCB traffic classes */
5213 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5214 tc = &adapter->dcb_cfg.tc_config[j];
5215 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5216 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5217 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5218 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5219 tc->dcb_pfc = pfc_disabled;
5220 }
5221 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5222 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5223 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 5224 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5225 adapter->dcb_set_bitmap = 0x00;
3032309b 5226 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5227 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5228 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5229
5230#endif
9a799d71
AK		 5231
5232 /* default flow control settings */
cd7664f6 5233 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5234 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5235#ifdef CONFIG_DCB
5236 adapter->last_lfc_mode = hw->fc.current_mode;
5237#endif
16b61beb
JF		 5238 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5239 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 5240 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5241 hw->fc.send_xon = true;
71fd570b 5242 hw->fc.disable_fc_autoneg = false;
9a799d71 5243
30efa5a3 5244 /* enable itr by default in dynamic mode */
f7554a2b
NS		 5245 adapter->rx_itr_setting = 1;
5246 adapter->rx_eitr_param = 20000;
5247 adapter->tx_itr_setting = 1;
5248 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 5249
5250 /* set defaults for eitr in MegaBytes */
5251 adapter->eitr_low = 10;
5252 adapter->eitr_high = 20;
5253
5254 /* set default ring sizes */
5255 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5256 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5257
9a799d71 5258 /* initialize eeprom parameters */
c44ade9e 5259 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5260 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5261 return -EIO;
5262 }
5263
021230d4 5264 /* enable rx csum by default */
9a799d71
AK		 5265 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5266
1a6c14a2
JB		 5267 /* get assigned NUMA node */
5268 adapter->node = dev_to_node(&pdev->dev);
5269
9a799d71
AK		 5270 set_bit(__IXGBE_DOWN, &adapter->state);
5271
5272 return 0;
5273}
5274
5275/**
5276 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5277 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5278 *
5279 * Return 0 on success, negative on failure
5280 **/
b6ec895e 5281int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5282{
b6ec895e 5283 struct device *dev = tx_ring->dev;
9a799d71
AK		 5284 int size;
5285
3a581073 5286 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5287 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5288 if (!tx_ring->tx_buffer_info)
89bf67f1 5289 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5290 if (!tx_ring->tx_buffer_info)
5291 goto err;
9a799d71
AK		 5292
5293 /* round up to nearest 4K */
12207e49 5294 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5295 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5296
b6ec895e 5297 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5298 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5299 if (!tx_ring->desc)
5300 goto err;
9a799d71 5301
3a581073
JB		 5302 tx_ring->next_to_use = 0;
5303 tx_ring->next_to_clean = 0;
5304 tx_ring->work_limit = tx_ring->count;
9a799d71 5305 return 0;
e01c31a5
JB		 5306
5307err:
5308 vfree(tx_ring->tx_buffer_info);
5309 tx_ring->tx_buffer_info = NULL;
b6ec895e 5310 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5311 return -ENOMEM;
9a799d71
AK		 5312}
5313
69888674
AD		 5314/**
5315 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5316 * @adapter: board private structure
5317 *
5318 * If this function returns with an error, then it's possible one or
5319 * more of the rings is populated (while the rest are not). It is the
5320 * callers duty to clean those orphaned rings.
5321 *
5322 * Return 0 on success, negative on failure
5323 **/
5324static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5325{
5326 int i, err = 0;
5327
5328 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5329 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5330 if (!err)
5331 continue;
396e799c 5332 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5333 break;
5334 }
5335
5336 return err;
5337}
5338
9a799d71
AK		 5339/**
5340 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5341 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5342 *
5343 * Returns 0 on success, negative on failure
5344 **/
b6ec895e 5345int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5346{
b6ec895e 5347 struct device *dev = rx_ring->dev;
021230d4 5348 int size;
9a799d71 5349
3a581073 5350 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5351 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5352 if (!rx_ring->rx_buffer_info)
89bf67f1 5353 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5354 if (!rx_ring->rx_buffer_info)
5355 goto err;
9a799d71 5356
9a799d71 5357 /* Round up to nearest 4K */
3a581073
JB		 5358 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5359 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5360
b6ec895e 5361 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5362 &rx_ring->dma, GFP_KERNEL);
9a799d71 5363
b6ec895e
AD		 5364 if (!rx_ring->desc)
5365 goto err;
9a799d71 5366
3a581073
JB		 5367 rx_ring->next_to_clean = 0;
5368 rx_ring->next_to_use = 0;
9a799d71
AK		 5369
5370 return 0;
b6ec895e
AD		 5371err:
5372 vfree(rx_ring->rx_buffer_info);
5373 rx_ring->rx_buffer_info = NULL;
5374 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5375 return -ENOMEM;
9a799d71
AK		 5376}
5377
69888674
AD		 5378/**
5379 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5380 * @adapter: board private structure
5381 *
5382 * If this function returns with an error, then it's possible one or
5383 * more of the rings is populated (while the rest are not). It is the
5384 * callers duty to clean those orphaned rings.
5385 *
5386 * Return 0 on success, negative on failure
5387 **/
69888674
AD		 5388static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5389{
5390 int i, err = 0;
5391
5392 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5393 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5394 if (!err)
5395 continue;
396e799c 5396 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5397 break;
5398 }
5399
5400 return err;
5401}
5402
9a799d71
AK		 5403/**
5404 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5405 * @tx_ring: Tx descriptor ring for a specific queue
5406 *
5407 * Free all transmit software resources
5408 **/
b6ec895e 5409void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5410{
b6ec895e 5411 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5412
5413 vfree(tx_ring->tx_buffer_info);
5414 tx_ring->tx_buffer_info = NULL;
5415
b6ec895e
AD		 5416 /* if not set, then don't free */
5417 if (!tx_ring->desc)
5418 return;
5419
5420 dma_free_coherent(tx_ring->dev, tx_ring->size,
5421 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5422
5423 tx_ring->desc = NULL;
5424}
5425
5426/**
5427 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5428 * @adapter: board private structure
5429 *
5430 * Free all transmit software resources
5431 **/
5432static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5433{
5434 int i;
5435
5436 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5437 if (adapter->tx_ring[i]->desc)
b6ec895e 5438 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5439}
5440
5441/**
b4617240 5442 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5443 * @rx_ring: ring to clean the resources from
5444 *
5445 * Free all receive software resources
5446 **/
b6ec895e 5447void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5448{
b6ec895e 5449 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5450
5451 vfree(rx_ring->rx_buffer_info);
5452 rx_ring->rx_buffer_info = NULL;
5453
b6ec895e
AD		 5454 /* if not set, then don't free */
5455 if (!rx_ring->desc)
5456 return;
5457
5458 dma_free_coherent(rx_ring->dev, rx_ring->size,
5459 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5460
5461 rx_ring->desc = NULL;
5462}
5463
5464/**
5465 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5466 * @adapter: board private structure
5467 *
5468 * Free all receive software resources
5469 **/
5470static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5471{
5472 int i;
5473
5474 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5475 if (adapter->rx_ring[i]->desc)
b6ec895e 5476 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5477}
5478
9a799d71
AK		 5479/**
5480 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5481 * @netdev: network interface device structure
5482 * @new_mtu: new value for maximum frame size
5483 *
5484 * Returns 0 on success, negative on failure
5485 **/
5486static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5487{
5488 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5489 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5490 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5491
42c783c5 5492 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5493 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5494 hw->mac.type != ixgbe_mac_X540) {
5495 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5496 return -EINVAL;
5497 } else {
5498 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5499 return -EINVAL;
5500 }
9a799d71 5501
396e799c 5502 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5503 /* must set new MTU before calling down or up */
9a799d71
AK		 5504 netdev->mtu = new_mtu;
5505
16b61beb
JF		 5506 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5507 hw->fc.low_water = FC_LOW_WATER(max_frame);
5508
d4f80882
AV		 5509 if (netif_running(netdev))
5510 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5511
5512 return 0;
5513}
5514
5515/**
5516 * ixgbe_open - Called when a network interface is made active
5517 * @netdev: network interface device structure
5518 *
5519 * Returns 0 on success, negative value on failure
5520 *
5521 * The open entry point is called when a network interface is made
5522 * active by the system (IFF_UP). At this point all resources needed
5523 * for transmit and receive operations are allocated, the interrupt
5524 * handler is registered with the OS, the watchdog timer is started,
5525 * and the stack is notified that the interface is ready.
5526 **/
5527static int ixgbe_open(struct net_device *netdev)
5528{
5529 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5530 int err;
4bebfaa5
AK		 5531
5532 /* disallow open during test */
5533 if (test_bit(__IXGBE_TESTING, &adapter->state))
5534 return -EBUSY;
9a799d71 5535
54386467
JB		 5536 netif_carrier_off(netdev);
5537
9a799d71
AK		 5538 /* allocate transmit descriptors */
5539 err = ixgbe_setup_all_tx_resources(adapter);
5540 if (err)
5541 goto err_setup_tx;
5542
9a799d71
AK		 5543 /* allocate receive descriptors */
5544 err = ixgbe_setup_all_rx_resources(adapter);
5545 if (err)
5546 goto err_setup_rx;
5547
5548 ixgbe_configure(adapter);
5549
021230d4 5550 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5551 if (err)
5552 goto err_req_irq;
5553
9a799d71
AK		 5554 err = ixgbe_up_complete(adapter);
5555 if (err)
5556 goto err_up;
5557
d55b53ff
JK		 5558 netif_tx_start_all_queues(netdev);
5559
9a799d71
AK		 5560 return 0;
5561
5562err_up:
5eba3699 5563 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5564 ixgbe_free_irq(adapter);
5565err_req_irq:
9a799d71 5566err_setup_rx:
a20a1199 5567 ixgbe_free_all_rx_resources(adapter);
9a799d71 5568err_setup_tx:
a20a1199 5569 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5570 ixgbe_reset(adapter);
5571
5572 return err;
5573}
5574
5575/**
5576 * ixgbe_close - Disables a network interface
5577 * @netdev: network interface device structure
5578 *
5579 * Returns 0, this is not allowed to fail
5580 *
5581 * The close entry point is called when an interface is de-activated
5582 * by the OS. The hardware is still under the drivers control, but
5583 * needs to be disabled. A global MAC reset is issued to stop the
5584 * hardware, and all transmit and receive resources are freed.
5585 **/
5586static int ixgbe_close(struct net_device *netdev)
5587{
5588 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5589
5590 ixgbe_down(adapter);
5591 ixgbe_free_irq(adapter);
5592
5593 ixgbe_free_all_tx_resources(adapter);
5594 ixgbe_free_all_rx_resources(adapter);
5595
5eba3699 5596 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5597
5598 return 0;
5599}
5600
b3c8b4ba
AD		 5601#ifdef CONFIG_PM
5602static int ixgbe_resume(struct pci_dev *pdev)
5603{
c60fbb00
AD		 5604 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5605 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5606 u32 err;
5607
5608 pci_set_power_state(pdev, PCI_D0);
5609 pci_restore_state(pdev);
656ab817
DS		 5610 /*
5611 * pci_restore_state clears dev->state_saved so call
5612 * pci_save_state to restore it.
5613 */
5614 pci_save_state(pdev);
9ce77666 5615
5616 err = pci_enable_device_mem(pdev);
b3c8b4ba 5617 if (err) {
849c4542 5618 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5619 return err;
5620 }
5621 pci_set_master(pdev);
5622
dd4d8ca6 5623 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5624
5625 err = ixgbe_init_interrupt_scheme(adapter);
5626 if (err) {
849c4542 5627 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5628 return err;
5629 }
5630
b3c8b4ba
AD		 5631 ixgbe_reset(adapter);
5632
495dce12
WJP		 5633 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5634
b3c8b4ba 5635 if (netif_running(netdev)) {
c60fbb00 5636 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5637 if (err)
5638 return err;
5639 }
5640
5641 netif_device_attach(netdev);
5642
5643 return 0;
5644}
b3c8b4ba 5645#endif /* CONFIG_PM */
9d8d05ae
RW		 5646
5647static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5648{
c60fbb00
AD		 5649 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5650 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5651 struct ixgbe_hw *hw = &adapter->hw;
5652 u32 ctrl, fctrl;
5653 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5654#ifdef CONFIG_PM
5655 int retval = 0;
5656#endif
5657
5658 netif_device_detach(netdev);
5659
5660 if (netif_running(netdev)) {
5661 ixgbe_down(adapter);
5662 ixgbe_free_irq(adapter);
5663 ixgbe_free_all_tx_resources(adapter);
5664 ixgbe_free_all_rx_resources(adapter);
5665 }
b3c8b4ba 5666
5f5ae6fc 5667 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5668#ifdef CONFIG_DCB
5669 kfree(adapter->ixgbe_ieee_pfc);
5670 kfree(adapter->ixgbe_ieee_ets);
5671#endif
5f5ae6fc 5672
b3c8b4ba
AD		 5673#ifdef CONFIG_PM
5674 retval = pci_save_state(pdev);
5675 if (retval)
5676 return retval;
4df10466 5677
b3c8b4ba 5678#endif
e8e26350
PW		 5679 if (wufc) {
5680 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5681
e8e26350
PW		 5682 /* turn on all-multi mode if wake on multicast is enabled */
5683 if (wufc & IXGBE_WUFC_MC) {
5684 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5685 fctrl |= IXGBE_FCTRL_MPE;
5686 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5687 }
5688
5689 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5690 ctrl |= IXGBE_CTRL_GIO_DIS;
5691 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5692
5693 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5694 } else {
5695 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5696 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5697 }
5698
bd508178
AD		 5699 switch (hw->mac.type) {
5700 case ixgbe_mac_82598EB:
dd4d8ca6 5701 pci_wake_from_d3(pdev, false);
bd508178
AD		 5702 break;
5703 case ixgbe_mac_82599EB:
b93a2226 5704 case ixgbe_mac_X540:
bd508178
AD		 5705 pci_wake_from_d3(pdev, !!wufc);
5706 break;
5707 default:
5708 break;
5709 }
b3c8b4ba 5710
9d8d05ae
RW		 5711 *enable_wake = !!wufc;
5712
b3c8b4ba
AD		 5713 ixgbe_release_hw_control(adapter);
5714
5715 pci_disable_device(pdev);
5716
9d8d05ae
RW		 5717 return 0;
5718}
5719
5720#ifdef CONFIG_PM
5721static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5722{
5723 int retval;
5724 bool wake;
5725
5726 retval = __ixgbe_shutdown(pdev, &wake);
5727 if (retval)
5728 return retval;
5729
5730 if (wake) {
5731 pci_prepare_to_sleep(pdev);
5732 } else {
5733 pci_wake_from_d3(pdev, false);
5734 pci_set_power_state(pdev, PCI_D3hot);
5735 }
b3c8b4ba
AD		 5736
5737 return 0;
5738}
9d8d05ae 5739#endif /* CONFIG_PM */
b3c8b4ba
AD		 5740
5741static void ixgbe_shutdown(struct pci_dev *pdev)
5742{
9d8d05ae
RW		 5743 bool wake;
5744
5745 __ixgbe_shutdown(pdev, &wake);
5746
5747 if (system_state == SYSTEM_POWER_OFF) {
5748 pci_wake_from_d3(pdev, wake);
5749 pci_set_power_state(pdev, PCI_D3hot);
5750 }
b3c8b4ba
AD		 5751}
5752
9a799d71
AK		 5753/**
5754 * ixgbe_update_stats - Update the board statistics counters.
5755 * @adapter: board private structure
5756 **/
5757void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5758{
2d86f139 5759 struct net_device *netdev = adapter->netdev;
9a799d71 5760 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5761 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5762 u64 total_mpc = 0;
5763 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5764 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5765 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5766 u64 bytes = 0, packets = 0;
9a799d71 5767
d08935c2
DS		 5768 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5769 test_bit(__IXGBE_RESETTING, &adapter->state))
5770 return;
5771
94b982b2 5772 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5773 u64 rsc_count = 0;
94b982b2 5774 u64 rsc_flush = 0;
d51019a4
PW		 5775 for (i = 0; i < 16; i++)
5776 adapter->hw_rx_no_dma_resources +=
7ca647bd 5777 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5778 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5779 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5780 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5781 }
5782 adapter->rsc_total_count = rsc_count;
5783 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5784 }
5785
5b7da515
AD		 5786 for (i = 0; i < adapter->num_rx_queues; i++) {
5787 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5788 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5789 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5790 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5791 bytes += rx_ring->stats.bytes;
5792 packets += rx_ring->stats.packets;
5793 }
5794 adapter->non_eop_descs = non_eop_descs;
5795 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5796 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5797 netdev->stats.rx_bytes = bytes;
5798 netdev->stats.rx_packets = packets;
5799
5800 bytes = 0;
5801 packets = 0;
7ca3bc58 5802 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5803 for (i = 0; i < adapter->num_tx_queues; i++) {
5804 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5805 restart_queue += tx_ring->tx_stats.restart_queue;
5806 tx_busy += tx_ring->tx_stats.tx_busy;
5807 bytes += tx_ring->stats.bytes;
5808 packets += tx_ring->stats.packets;
5809 }
eb985f09 5810 adapter->restart_queue = restart_queue;
5b7da515
AD		 5811 adapter->tx_busy = tx_busy;
5812 netdev->stats.tx_bytes = bytes;
5813 netdev->stats.tx_packets = packets;
7ca3bc58 5814
7ca647bd 5815 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5816 for (i = 0; i < 8; i++) {
5817 /* for packet buffers not used, the register should read 0 */
5818 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5819 missed_rx += mpc;
7ca647bd
JP		 5820 hwstats->mpc[i] += mpc;
5821 total_mpc += hwstats->mpc[i];
e8e26350 5822 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5823 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5824 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5825 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5826 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5827 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
bd508178
AD		 5828 switch (hw->mac.type) {
5829 case ixgbe_mac_82598EB:
7ca647bd
JP		 5830 hwstats->pxonrxc[i] +=
5831 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5832 break;
5833 case ixgbe_mac_82599EB:
b93a2226 5834 case ixgbe_mac_X540:
bd508178
AD		 5835 hwstats->pxonrxc[i] +=
5836 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5837 break;
5838 default:
5839 break;
e8e26350 5840 }
7ca647bd
JP		 5841 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5842 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5843 }
7ca647bd 5844 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5845 /* work around hardware counting issue */
7ca647bd 5846 hwstats->gprc -= missed_rx;
6f11eef7 5847
c84d324c
JF		 5848 ixgbe_update_xoff_received(adapter);
5849
6f11eef7 5850 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5851 switch (hw->mac.type) {
5852 case ixgbe_mac_82598EB:
5853 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5854 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5855 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5856 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5857 break;
5858 case ixgbe_mac_82599EB:
b93a2226 5859 case ixgbe_mac_X540:
7ca647bd 5860 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5861 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5862 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5863 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5864 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5865 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5866 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5867 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5868 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5869#ifdef IXGBE_FCOE
7ca647bd
JP		 5870 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5871 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5872 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5873 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5874 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5875 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5876#endif /* IXGBE_FCOE */
bd508178
AD		 5877 break;
5878 default:
5879 break;
e8e26350 5880 }
9a799d71 5881 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5882 hwstats->bprc += bprc;
5883 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5884 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5885 hwstats->mprc -= bprc;
5886 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5887 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5888 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5889 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5890 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5891 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5892 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5893 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5894 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5895 hwstats->lxontxc += lxon;
6f11eef7 5896 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5897 hwstats->lxofftxc += lxoff;
5898 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5899 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5900 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5901 /*
5902 * 82598 errata - tx of flow control packets is included in tx counters
5903 */
5904 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5905 hwstats->gptc -= xon_off_tot;
5906 hwstats->mptc -= xon_off_tot;
5907 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5908 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5909 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5910 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5911 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5912 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5913 hwstats->ptc64 -= xon_off_tot;
5914 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5915 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5916 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5917 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5918 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5919 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5920
5921 /* Fill out the OS statistics structure */
7ca647bd 5922 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5923
5924 /* Rx Errors */
7ca647bd 5925 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5926 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5927 netdev->stats.rx_length_errors = hwstats->rlec;
5928 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5929 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5930}
5931
5932/**
5933 * ixgbe_watchdog - Timer Call-back
5934 * @data: pointer to adapter cast into an unsigned long
5935 **/
5936static void ixgbe_watchdog(unsigned long data)
5937{
5938 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5939 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5940 u64 eics = 0;
5941 int i;
cf8280ee 5942
fe49f04a
AD		 5943 /*
5944 * Do the watchdog outside of interrupt context due to the lovely
5945 * delays that some of the newer hardware requires
5946 */
22d5a71b 5947
fe49f04a
AD		 5948 if (test_bit(__IXGBE_DOWN, &adapter->state))
5949 goto watchdog_short_circuit;
22d5a71b 5950
fe49f04a
AD		 5951 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5952 /*
5953 * for legacy and MSI interrupts don't set any bits
5954 * that are enabled for EIAM, because this operation
5955 * would set *both* EIMS and EICS for any bit in EIAM
5956 */
5957 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5958 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5959 goto watchdog_reschedule;
5960 }
5961
5962 /* get one bit for every active tx/rx interrupt vector */
5963 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5964 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5965 if (qv->rxr_count || qv->txr_count)
5966 eics |= ((u64)1 << i);
cf8280ee 5967 }
9a799d71 5968
fe49f04a
AD		 5969 /* Cause software interrupt to ensure rx rings are cleaned */
5970 ixgbe_irq_rearm_queues(adapter, eics);
5971
5972watchdog_reschedule:
5973 /* Reset the timer */
5974 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5975
5976watchdog_short_circuit:
cf8280ee
JB		 5977 schedule_work(&adapter->watchdog_task);
5978}
5979
e8e26350
PW		 5980/**
5981 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5982 * @work: pointer to work_struct containing our data
5983 **/
5984static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5985{
5986 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5987 struct ixgbe_adapter,
5988 multispeed_fiber_task);
e8e26350
PW		 5989 struct ixgbe_hw *hw = &adapter->hw;
5990 u32 autoneg;
8620a103 5991 bool negotiation;
e8e26350
PW		 5992
5993 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5994 autoneg = hw->phy.autoneg_advertised;
5995 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5996 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5997 hw->mac.autotry_restart = false;
8620a103
MC		 5998 if (hw->mac.ops.setup_link)
5999 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 6000 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6001 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
6002}
6003
6004/**
6005 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
6006 * @work: pointer to work_struct containing our data
6007 **/
6008static void ixgbe_sfp_config_module_task(struct work_struct *work)
6009{
6010 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 6011 struct ixgbe_adapter,
6012 sfp_config_module_task);
e8e26350
PW		 6013 struct ixgbe_hw *hw = &adapter->hw;
6014 u32 err;
6015
6016 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 6017
6018 /* Time for electrical oscillations to settle down */
6019 msleep(100);
e8e26350 6020 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 6021
e8e26350 6022 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 6023 e_dev_err("failed to initialize because an unsupported SFP+ "
6024 "module type was detected.\n");
6025 e_dev_err("Reload the driver after installing a supported "
6026 "module.\n");
63d6e1d8 6027 unregister_netdev(adapter->netdev);
e8e26350
PW		 6028 return;
6029 }
4c7e604b
AG		 6030 if (hw->mac.ops.setup_sfp)
6031 hw->mac.ops.setup_sfp(hw);
e8e26350 6032
8d1c3c07 6033 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 6034 /* This will also work for DA Twinax connections */
6035 schedule_work(&adapter->multispeed_fiber_task);
6036 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
6037}
6038
c4cf55e5
PWJ		 6039/**
6040 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
6041 * @work: pointer to work_struct containing our data
6042 **/
6043static void ixgbe_fdir_reinit_task(struct work_struct *work)
6044{
6045 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 6046 struct ixgbe_adapter,
6047 fdir_reinit_task);
c4cf55e5
PWJ		 6048 struct ixgbe_hw *hw = &adapter->hw;
6049 int i;
6050
6051 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6052 for (i = 0; i < adapter->num_tx_queues; i++)
7d637bcc
AD		 6053 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6054 &(adapter->tx_ring[i]->state));
c4cf55e5 6055 } else {
396e799c 6056 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 6057 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 6058 }
6059 /* Done FDIR Re-initialization, enable transmits */
6060 netif_tx_start_all_queues(adapter->netdev);
6061}
6062
a985b6c3
GR		 6063static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6064{
6065 u32 ssvpc;
6066
6067 /* Do not perform spoof check for 82598 */
6068 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6069 return;
6070
6071 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6072
6073 /*
6074 * ssvpc register is cleared on read, if zero then no
6075 * spoofed packets in the last interval.
6076 */
6077 if (!ssvpc)
6078 return;
6079
6080 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6081}
6082
10eec955
JF		 6083static DEFINE_MUTEX(ixgbe_watchdog_lock);
6084
cf8280ee 6085/**
69888674
AD		 6086 * ixgbe_watchdog_task - worker thread to bring link up
6087 * @work: pointer to work_struct containing our data
cf8280ee
JB		 6088 **/
6089static void ixgbe_watchdog_task(struct work_struct *work)
6090{
6091 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 6092 struct ixgbe_adapter,
6093 watchdog_task);
cf8280ee
JB		 6094 struct net_device *netdev = adapter->netdev;
6095 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 6096 u32 link_speed;
6097 bool link_up;
bc59fcda
NS		 6098 int i;
6099 struct ixgbe_ring *tx_ring;
6100 int some_tx_pending = 0;
cf8280ee 6101
10eec955
JF		 6102 mutex_lock(&ixgbe_watchdog_lock);
6103
6104 link_up = adapter->link_up;
6105 link_speed = adapter->link_speed;
cf8280ee
JB		 6106
6107 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
6108 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 6109 if (link_up) {
6110#ifdef CONFIG_DCB
6111 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6112 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 6113 hw->mac.ops.fc_enable(hw, i);
264857b8 6114 } else {
620fa036 6115 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 6116 }
6117#else
620fa036 6118 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 6119#endif
6120 }
6121
cf8280ee
JB		 6122 if (link_up ||
6123 time_after(jiffies, (adapter->link_check_timeout +
e8e9f696 6124 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 6125 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 6126 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 6127 }
6128 adapter->link_up = link_up;
6129 adapter->link_speed = link_speed;
6130 }
9a799d71
AK		 6131
6132 if (link_up) {
6133 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 6134 bool flow_rx, flow_tx;
6135
bd508178
AD		 6136 switch (hw->mac.type) {
6137 case ixgbe_mac_82598EB: {
e8e26350
PW		 6138 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6139 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 6140 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6141 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350 6142 }
bd508178 6143 break;
b93a2226
DS		 6144 case ixgbe_mac_82599EB:
6145 case ixgbe_mac_X540: {
bd508178
AD		 6146 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6147 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6148 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6149 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6150 }
6151 break;
6152 default:
6153 flow_tx = false;
6154 flow_rx = false;
6155 break;
6156 }
e8e26350 6157
396e799c 6158 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 6159 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 6160 "10 Gbps" :
6161 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
1b1c0a48
AS		 6162 "1 Gbps" :
6163 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6164 "100 Mbps" :
6165 "unknown speed"))),
e8e26350 6166 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 6167 (flow_rx ? "RX" :
6168 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 6169
6170 netif_carrier_on(netdev);
9a799d71
AK		 6171 } else {
6172 /* Force detection of hung controller */
7d637bcc
AD		 6173 for (i = 0; i < adapter->num_tx_queues; i++) {
6174 tx_ring = adapter->tx_ring[i];
6175 set_check_for_tx_hang(tx_ring);
6176 }
9a799d71
AK		 6177 }
6178 } else {
cf8280ee
JB		 6179 adapter->link_up = false;
6180 adapter->link_speed = 0;
9a799d71 6181 if (netif_carrier_ok(netdev)) {
396e799c 6182 e_info(drv, "NIC Link is Down\n");
9a799d71 6183 netif_carrier_off(netdev);
9a799d71
AK		 6184 }
6185 }
6186
bc59fcda
NS		 6187 if (!netif_carrier_ok(netdev)) {
6188 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 6189 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6190 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6191 some_tx_pending = 1;
6192 break;
6193 }
6194 }
6195
6196 if (some_tx_pending) {
6197 /* We've lost link, so the controller stops DMA,
6198 * but we've got queued Tx work that's never going
6199 * to get done, so reset controller to flush Tx.
6200 * (Do the reset outside of interrupt context).
6201 */
6202 schedule_work(&adapter->reset_task);
6203 }
6204 }
6205
a985b6c3 6206 ixgbe_spoof_check(adapter);
9a799d71 6207 ixgbe_update_stats(adapter);
10eec955 6208 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 6209}
6210
9a799d71 6211static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696 6212 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5e09a105 6213 u32 tx_flags, u8 *hdr_len, __be16 protocol)
9a799d71
AK		 6214{
6215 struct ixgbe_adv_tx_context_desc *context_desc;
6216 unsigned int i;
6217 int err;
6218 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 6219 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6220 u32 mss_l4len_idx, l4len;
9a799d71
AK		 6221
6222 if (skb_is_gso(skb)) {
6223 if (skb_header_cloned(skb)) {
6224 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6225 if (err)
6226 return err;
6227 }
6228 l4len = tcp_hdrlen(skb);
6229 *hdr_len += l4len;
6230
5e09a105 6231 if (protocol == htons(ETH_P_IP)) {
9a799d71
AK		 6232 struct iphdr *iph = ip_hdr(skb);
6233 iph->tot_len = 0;
6234 iph->check = 0;
6235 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 6236 iph->daddr, 0,
6237 IPPROTO_TCP,
6238 0);
8e1e8a47 6239 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 6240 ipv6_hdr(skb)->payload_len = 0;
6241 tcp_hdr(skb)->check =
6242 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 6243 &ipv6_hdr(skb)->daddr,
6244 0, IPPROTO_TCP, 0);
9a799d71
AK		 6245 }
6246
6247 i = tx_ring->next_to_use;
6248
6249 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6250 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6251
6252 /* VLAN MACLEN IPLEN */
6253 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6254 vlan_macip_lens |=
6255 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6256 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 6257 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6258 *hdr_len += skb_network_offset(skb);
6259 vlan_macip_lens |=
6260 (skb_transport_header(skb) - skb_network_header(skb));
6261 *hdr_len +=
6262 (skb_transport_header(skb) - skb_network_header(skb));
6263 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6264 context_desc->seqnum_seed = 0;
6265
6266 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 6267 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 6268 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6269
5e09a105 6270 if (protocol == htons(ETH_P_IP))
9a799d71
AK		 6271 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6272 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6273 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6274
6275 /* MSS L4LEN IDX */
9f8cdf4f 6276 mss_l4len_idx =
9a799d71
AK		 6277 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6278 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 6279 /* use index 1 for TSO */
6280 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6281 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6282
6283 tx_buffer_info->time_stamp = jiffies;
6284 tx_buffer_info->next_to_watch = i;
6285
6286 i++;
6287 if (i == tx_ring->count)
6288 i = 0;
6289 tx_ring->next_to_use = i;
6290
6291 return true;
6292 }
6293 return false;
6294}
6295
5e09a105
HZ		 6296static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6297 __be16 protocol)
7ca647bd
JP		 6298{
6299 u32 rtn = 0;
7ca647bd
JP		 6300
6301 switch (protocol) {
6302 case cpu_to_be16(ETH_P_IP):
6303 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6304 switch (ip_hdr(skb)->protocol) {
6305 case IPPROTO_TCP:
6306 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6307 break;
6308 case IPPROTO_SCTP:
6309 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6310 break;
6311 }
6312 break;
6313 case cpu_to_be16(ETH_P_IPV6):
6314 /* XXX what about other V6 headers?? */
6315 switch (ipv6_hdr(skb)->nexthdr) {
6316 case IPPROTO_TCP:
6317 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6318 break;
6319 case IPPROTO_SCTP:
6320 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6321 break;
6322 }
6323 break;
6324 default:
6325 if (unlikely(net_ratelimit()))
6326 e_warn(probe, "partial checksum but proto=%x!\n",
5e09a105 6327 protocol);
7ca647bd
JP		 6328 break;
6329 }
6330
6331 return rtn;
6332}
6333
9a799d71 6334static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696 6335 struct ixgbe_ring *tx_ring,
5e09a105
HZ		 6336 struct sk_buff *skb, u32 tx_flags,
6337 __be16 protocol)
9a799d71
AK		 6338{
6339 struct ixgbe_adv_tx_context_desc *context_desc;
6340 unsigned int i;
6341 struct ixgbe_tx_buffer *tx_buffer_info;
6342 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6343
6344 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6345 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6346 i = tx_ring->next_to_use;
6347 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6348 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6349
6350 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6351 vlan_macip_lens |=
6352 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6353 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 6354 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6355 if (skb->ip_summed == CHECKSUM_PARTIAL)
6356 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 6357 skb_network_header(skb));
9a799d71
AK		 6358
6359 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6360 context_desc->seqnum_seed = 0;
6361
6362 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 6363 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6364
7ca647bd 6365 if (skb->ip_summed == CHECKSUM_PARTIAL)
5e09a105 6366 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
9a799d71
AK		 6367
6368 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 6369 /* use index zero for tx checksum offload */
9a799d71
AK		 6370 context_desc->mss_l4len_idx = 0;
6371
6372 tx_buffer_info->time_stamp = jiffies;
6373 tx_buffer_info->next_to_watch = i;
9f8cdf4f 6374
9a799d71
AK		 6375 i++;
6376 if (i == tx_ring->count)
6377 i = 0;
6378 tx_ring->next_to_use = i;
6379
6380 return true;
6381 }
9f8cdf4f 6382
9a799d71
AK		 6383 return false;
6384}
6385
6386static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6387 struct ixgbe_ring *tx_ring,
6388 struct sk_buff *skb, u32 tx_flags,
8ad494b0 6389 unsigned int first, const u8 hdr_len)
9a799d71 6390{
b6ec895e 6391 struct device *dev = tx_ring->dev;
9a799d71 6392 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6393 unsigned int len;
6394 unsigned int total = skb->len;
9a799d71
AK		 6395 unsigned int offset = 0, size, count = 0, i;
6396 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6397 unsigned int f;
8ad494b0
AD		 6398 unsigned int bytecount = skb->len;
6399 u16 gso_segs = 1;
9a799d71
AK		 6400
6401 i = tx_ring->next_to_use;
6402
eacd73f7
YZ		 6403 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6404 /* excluding fcoe_crc_eof for FCoE */
6405 total -= sizeof(struct fcoe_crc_eof);
6406
6407 len = min(skb_headlen(skb), total);
9a799d71
AK		 6408 while (len) {
6409 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6410 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6411
6412 tx_buffer_info->length = size;
e5a43549 6413 tx_buffer_info->mapped_as_page = false;
b6ec895e 6414 tx_buffer_info->dma = dma_map_single(dev,
e5a43549 6415 skb->data + offset,
1b507730 6416 size, DMA_TO_DEVICE);
b6ec895e 6417 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6418 goto dma_error;
9a799d71
AK		 6419 tx_buffer_info->time_stamp = jiffies;
6420 tx_buffer_info->next_to_watch = i;
6421
6422 len -= size;
eacd73f7 6423 total -= size;
9a799d71
AK		 6424 offset += size;
6425 count++;
44df32c5
AD		 6426
6427 if (len) {
6428 i++;
6429 if (i == tx_ring->count)
6430 i = 0;
6431 }
9a799d71
AK		 6432 }
6433
6434 for (f = 0; f < nr_frags; f++) {
6435 struct skb_frag_struct *frag;
6436
6437 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6438 len = min((unsigned int)frag->size, total);
e5a43549 6439 offset = frag->page_offset;
9a799d71
AK		 6440
6441 while (len) {
44df32c5
AD		 6442 i++;
6443 if (i == tx_ring->count)
6444 i = 0;
6445
9a799d71
AK		 6446 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6447 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6448
6449 tx_buffer_info->length = size;
b6ec895e 6450 tx_buffer_info->dma = dma_map_page(dev,
e5a43549
AD		 6451 frag->page,
6452 offset, size,
1b507730 6453 DMA_TO_DEVICE);
e5a43549 6454 tx_buffer_info->mapped_as_page = true;
b6ec895e 6455 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6456 goto dma_error;
9a799d71
AK		 6457 tx_buffer_info->time_stamp = jiffies;
6458 tx_buffer_info->next_to_watch = i;
6459
6460 len -= size;
eacd73f7 6461 total -= size;
9a799d71
AK		 6462 offset += size;
6463 count++;
9a799d71 6464 }
eacd73f7
YZ		 6465 if (total == 0)
6466 break;
9a799d71 6467 }
44df32c5 6468
8ad494b0
AD		 6469 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6470 gso_segs = skb_shinfo(skb)->gso_segs;
6471#ifdef IXGBE_FCOE
6472 /* adjust for FCoE Sequence Offload */
6473 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6474 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6475 skb_shinfo(skb)->gso_size);
6476#endif /* IXGBE_FCOE */
6477 bytecount += (gso_segs - 1) * hdr_len;
6478
6479 /* multiply data chunks by size of headers */
6480 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6481 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
9a799d71
AK		 6482 tx_ring->tx_buffer_info[i].skb = skb;
6483 tx_ring->tx_buffer_info[first].next_to_watch = i;
6484
e5a43549
AD		 6485 return count;
6486
6487dma_error:
849c4542 6488 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6489
6490 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6491 tx_buffer_info->dma = 0;
6492 tx_buffer_info->time_stamp = 0;
6493 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6494 if (count)
6495 count--;
e5a43549
AD		 6496
6497 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6498 while (count--) {
e8e9f696 6499 if (i == 0)
e5a43549 6500 i += tx_ring->count;
c1fa347f 6501 i--;
e5a43549 6502 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 6503 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
e5a43549
AD		 6504 }
6505
e44d38e1 6506 return 0;
9a799d71
AK		 6507}
6508
84ea2591 6509static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
e8e9f696 6510 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6511{
6512 union ixgbe_adv_tx_desc *tx_desc = NULL;
6513 struct ixgbe_tx_buffer *tx_buffer_info;
6514 u32 olinfo_status = 0, cmd_type_len = 0;
6515 unsigned int i;
6516 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6517
6518 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6519
6520 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6521
6522 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6523 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6524
6525 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6526 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6527
6528 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6529 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6530
4eeae6fd
PW		 6531 /* use index 1 context for tso */
6532 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6533 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6534 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6535 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6536
6537 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6538 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6539 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6540
eacd73f7
YZ		 6541 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6542 olinfo_status |= IXGBE_ADVTXD_CC;
6543 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6544 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6545 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6546 }
6547
9a799d71
AK		 6548 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6549
6550 i = tx_ring->next_to_use;
6551 while (count--) {
6552 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6553 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6554 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6555 tx_desc->read.cmd_type_len =
e8e9f696 6556 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6557 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6558 i++;
6559 if (i == tx_ring->count)
6560 i = 0;
6561 }
6562
6563 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6564
6565 /*
6566 * Force memory writes to complete before letting h/w
6567 * know there are new descriptors to fetch. (Only
6568 * applicable for weak-ordered memory model archs,
6569 * such as IA-64).
6570 */
6571 wmb();
6572
6573 tx_ring->next_to_use = i;
84ea2591 6574 writel(i, tx_ring->tail);
9a799d71
AK		 6575}
6576
69830529
AD		 6577static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6578 u32 tx_flags, __be16 protocol)
6579{
6580 struct ixgbe_q_vector *q_vector = ring->q_vector;
6581 union ixgbe_atr_hash_dword input = { .dword = 0 };
6582 union ixgbe_atr_hash_dword common = { .dword = 0 };
6583 union {
6584 unsigned char *network;
6585 struct iphdr *ipv4;
6586 struct ipv6hdr *ipv6;
6587 } hdr;
ee9e0f0b 6588 struct tcphdr *th;
905e4a41 6589 __be16 vlan_id;
c4cf55e5 6590
69830529
AD		 6591 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6592 if (!q_vector)
6593 return;
6594
6595 /* do nothing if sampling is disabled */
6596 if (!ring->atr_sample_rate)
d3ead241 6597 return;
c4cf55e5 6598
69830529 6599 ring->atr_count++;
c4cf55e5 6600
69830529
AD		 6601 /* snag network header to get L4 type and address */
6602 hdr.network = skb_network_header(skb);
6603
6604 /* Currently only IPv4/IPv6 with TCP is supported */
6605 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6606 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6607 (protocol != __constant_htons(ETH_P_IP) ||
6608 hdr.ipv4->protocol != IPPROTO_TCP))
6609 return;
ee9e0f0b
AD		 6610
6611 th = tcp_hdr(skb);
c4cf55e5 6612
69830529
AD		 6613 /* skip this packet since the socket is closing */
6614 if (th->fin)
6615 return;
6616
6617 /* sample on all syn packets or once every atr sample count */
6618 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6619 return;
6620
6621 /* reset sample count */
6622 ring->atr_count = 0;
6623
6624 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6625
6626 /*
6627 * src and dst are inverted, think how the receiver sees them
6628 *
6629 * The input is broken into two sections, a non-compressed section
6630 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6631 * is XORed together and stored in the compressed dword.
6632 */
6633 input.formatted.vlan_id = vlan_id;
6634
6635 /*
6636 * since src port and flex bytes occupy the same word XOR them together
6637 * and write the value to source port portion of compressed dword
6638 */
6639 if (vlan_id)
6640 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6641 else
6642 common.port.src ^= th->dest ^ protocol;
6643 common.port.dst ^= th->source;
6644
6645 if (protocol == __constant_htons(ETH_P_IP)) {
6646 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6647 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6648 } else {
6649 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6650 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6651 hdr.ipv6->saddr.s6_addr32[1] ^
6652 hdr.ipv6->saddr.s6_addr32[2] ^
6653 hdr.ipv6->saddr.s6_addr32[3] ^
6654 hdr.ipv6->daddr.s6_addr32[0] ^
6655 hdr.ipv6->daddr.s6_addr32[1] ^
6656 hdr.ipv6->daddr.s6_addr32[2] ^
6657 hdr.ipv6->daddr.s6_addr32[3];
6658 }
c4cf55e5
PWJ		 6659
6660 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6661 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6662 input, common, ring->queue_index);
c4cf55e5
PWJ		 6663}
6664
fc77dc3c 6665static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60 6666{
fc77dc3c 6667 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6668 /* Herbert's original patch had:
6669 * smp_mb__after_netif_stop_queue();
6670 * but since that doesn't exist yet, just open code it. */
6671 smp_mb();
6672
6673 /* We need to check again in a case another CPU has just
6674 * made room available. */
6675 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6676 return -EBUSY;
6677
6678 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6679 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6680 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6681 return 0;
6682}
6683
fc77dc3c 6684static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6685{
6686 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6687 return 0;
fc77dc3c 6688 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6689}
6690
09a3b1f8
SH		 6691static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6692{
6693 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6694 int txq = smp_processor_id();
56075a98 6695#ifdef IXGBE_FCOE
5e09a105
HZ		 6696 __be16 protocol;
6697
6698 protocol = vlan_get_protocol(skb);
6699
e5b64635
JF		 6700 if (((protocol == htons(ETH_P_FCOE)) ||
6701 (protocol == htons(ETH_P_FIP))) &&
6702 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6703 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6704 txq += adapter->ring_feature[RING_F_FCOE].mask;
6705 return txq;
56075a98
JF		 6706 }
6707#endif
6708
fdd3d631
KK		 6709 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6710 while (unlikely(txq >= dev->real_num_tx_queues))
6711 txq -= dev->real_num_tx_queues;
5f715823 6712 return txq;
fdd3d631 6713 }
c4cf55e5 6714
09a3b1f8
SH		 6715 return skb_tx_hash(dev, skb);
6716}
6717
fc77dc3c 6718netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6719 struct ixgbe_adapter *adapter,
6720 struct ixgbe_ring *tx_ring)
9a799d71 6721{
9a799d71
AK		 6722 unsigned int first;
6723 unsigned int tx_flags = 0;
30eba97a 6724 u8 hdr_len = 0;
5f715823 6725 int tso;
9a799d71
AK		 6726 int count = 0;
6727 unsigned int f;
5e09a105
HZ		 6728 __be16 protocol;
6729
6730 protocol = vlan_get_protocol(skb);
9f8cdf4f 6731
eab6d18d 6732 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6733 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6734 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6735 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
e5b64635 6736 tx_flags |= tx_ring->dcb_tc << 13;
2f90b865
AD		 6737 }
6738 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6739 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6740 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6741 skb->priority != TC_PRIO_CONTROL) {
e5b64635 6742 tx_flags |= tx_ring->dcb_tc << 13;
2ea186ae
JF		 6743 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6744 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6745 }
eacd73f7 6746
09ad1cc0 6747#ifdef IXGBE_FCOE
56075a98
JF		 6748 /* for FCoE with DCB, we force the priority to what
6749 * was specified by the switch */
6750 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
e5b64635
JF		 6751 (protocol == htons(ETH_P_FCOE)))
6752 tx_flags |= IXGBE_TX_FLAGS_FCOE;
ca77cd59
RL		 6753#endif
6754
eacd73f7 6755 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6756 if (skb_is_gso(skb) ||
6757 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6758 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6759 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6760 count++;
6761
9f8cdf4f
JB		 6762 count += TXD_USE_COUNT(skb_headlen(skb));
6763 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6764 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6765
fc77dc3c 6766 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
5b7da515 6767 tx_ring->tx_stats.tx_busy++;
9a799d71
AK		 6768 return NETDEV_TX_BUSY;
6769 }
9a799d71 6770
9a799d71 6771 first = tx_ring->next_to_use;
eacd73f7
YZ		 6772 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6773#ifdef IXGBE_FCOE
6774 /* setup tx offload for FCoE */
6775 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6776 if (tso < 0) {
6777 dev_kfree_skb_any(skb);
6778 return NETDEV_TX_OK;
6779 }
6780 if (tso)
6781 tx_flags |= IXGBE_TX_FLAGS_FSO;
6782#endif /* IXGBE_FCOE */
6783 } else {
5e09a105 6784 if (protocol == htons(ETH_P_IP))
eacd73f7 6785 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5e09a105
HZ		 6786 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6787 protocol);
eacd73f7
YZ		 6788 if (tso < 0) {
6789 dev_kfree_skb_any(skb);
6790 return NETDEV_TX_OK;
6791 }
9a799d71 6792
eacd73f7
YZ		 6793 if (tso)
6794 tx_flags |= IXGBE_TX_FLAGS_TSO;
5e09a105
HZ		 6795 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6796 protocol) &&
eacd73f7
YZ		 6797 (skb->ip_summed == CHECKSUM_PARTIAL))
6798 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6799 }
9a799d71 6800
8ad494b0 6801 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
44df32c5 6802 if (count) {
c4cf55e5 6803 /* add the ATR filter if ATR is on */
69830529
AD		 6804 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6805 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
84ea2591 6806 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
fc77dc3c 6807 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71 6808
44df32c5
AD		 6809 } else {
6810 dev_kfree_skb_any(skb);
6811 tx_ring->tx_buffer_info[first].time_stamp = 0;
6812 tx_ring->next_to_use = first;
6813 }
9a799d71
AK		 6814
6815 return NETDEV_TX_OK;
6816}
6817
84418e3b
AD		 6818static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6819{
6820 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6821 struct ixgbe_ring *tx_ring;
6822
6823 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6824 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6825}
6826
9a799d71
AK		 6827/**
6828 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6829 * @netdev: network interface device structure
6830 * @p: pointer to an address structure
6831 *
6832 * Returns 0 on success, negative on failure
6833 **/
6834static int ixgbe_set_mac(struct net_device *netdev, void *p)
6835{
6836 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6837 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6838 struct sockaddr *addr = p;
6839
6840 if (!is_valid_ether_addr(addr->sa_data))
6841 return -EADDRNOTAVAIL;
6842
6843 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6844 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6845
1cdd1ec8
GR		 6846 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6847 IXGBE_RAH_AV);
9a799d71
AK		 6848
6849 return 0;
6850}
6851
6b73e10d
BH		 6852static int
6853ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6854{
6855 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6856 struct ixgbe_hw *hw = &adapter->hw;
6857 u16 value;
6858 int rc;
6859
6860 if (prtad != hw->phy.mdio.prtad)
6861 return -EINVAL;
6862 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6863 if (!rc)
6864 rc = value;
6865 return rc;
6866}
6867
6868static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6869 u16 addr, u16 value)
6870{
6871 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6872 struct ixgbe_hw *hw = &adapter->hw;
6873
6874 if (prtad != hw->phy.mdio.prtad)
6875 return -EINVAL;
6876 return hw->phy.ops.write_reg(hw, addr, devad, value);
6877}
6878
6879static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6880{
6881 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6882
6883 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6884}
6885
0365e6e4
PW		 6886/**
6887 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6888 * netdev->dev_addrs
0365e6e4
PW		 6889 * @netdev: network interface device structure
6890 *
6891 * Returns non-zero on failure
6892 **/
6893static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6894{
6895 int err = 0;
6896 struct ixgbe_adapter *adapter = netdev_priv(dev);
6897 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6898
6899 if (is_valid_ether_addr(mac->san_addr)) {
6900 rtnl_lock();
6901 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6902 rtnl_unlock();
6903 }
6904 return err;
6905}
6906
6907/**
6908 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6909 * netdev->dev_addrs
0365e6e4
PW		 6910 * @netdev: network interface device structure
6911 *
6912 * Returns non-zero on failure
6913 **/
6914static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6915{
6916 int err = 0;
6917 struct ixgbe_adapter *adapter = netdev_priv(dev);
6918 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6919
6920 if (is_valid_ether_addr(mac->san_addr)) {
6921 rtnl_lock();
6922 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6923 rtnl_unlock();
6924 }
6925 return err;
6926}
6927
9a799d71
AK		 6928#ifdef CONFIG_NET_POLL_CONTROLLER
6929/*
6930 * Polling 'interrupt' - used by things like netconsole to send skbs
6931 * without having to re-enable interrupts. It's not called while
6932 * the interrupt routine is executing.
6933 */
6934static void ixgbe_netpoll(struct net_device *netdev)
6935{
6936 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6937 int i;
9a799d71 6938
1a647bd2
AD		 6939 /* if interface is down do nothing */
6940 if (test_bit(__IXGBE_DOWN, &adapter->state))
6941 return;
6942
9a799d71 6943 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6944 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6945 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6946 for (i = 0; i < num_q_vectors; i++) {
6947 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6948 ixgbe_msix_clean_many(0, q_vector);
6949 }
6950 } else {
6951 ixgbe_intr(adapter->pdev->irq, netdev);
6952 }
9a799d71 6953 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6954}
6955#endif
6956
de1036b1
ED		 6957static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6958 struct rtnl_link_stats64 *stats)
6959{
6960 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6961 int i;
6962
1a51502b 6963 rcu_read_lock();
de1036b1 6964 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6965 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6966 u64 bytes, packets;
6967 unsigned int start;
6968
1a51502b
ED		 6969 if (ring) {
6970 do {
6971 start = u64_stats_fetch_begin_bh(&ring->syncp);
6972 packets = ring->stats.packets;
6973 bytes = ring->stats.bytes;
6974 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6975 stats->rx_packets += packets;
6976 stats->rx_bytes += bytes;
6977 }
de1036b1 6978 }
1ac9ad13
ED		 6979
6980 for (i = 0; i < adapter->num_tx_queues; i++) {
6981 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6982 u64 bytes, packets;
6983 unsigned int start;
6984
6985 if (ring) {
6986 do {
6987 start = u64_stats_fetch_begin_bh(&ring->syncp);
6988 packets = ring->stats.packets;
6989 bytes = ring->stats.bytes;
6990 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6991 stats->tx_packets += packets;
6992 stats->tx_bytes += bytes;
6993 }
6994 }
1a51502b 6995 rcu_read_unlock();
de1036b1
ED		 6996 /* following stats updated by ixgbe_watchdog_task() */
6997 stats->multicast = netdev->stats.multicast;
6998 stats->rx_errors = netdev->stats.rx_errors;
6999 stats->rx_length_errors = netdev->stats.rx_length_errors;
7000 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7001 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7002 return stats;
7003}
7004
7005
0edc3527 7006static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7007 .ndo_open = ixgbe_open,
0edc3527 7008 .ndo_stop = ixgbe_close,
00829823 7009 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7010 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7011 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7012 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7013 .ndo_validate_addr = eth_validate_addr,
7014 .ndo_set_mac_address = ixgbe_set_mac,
7015 .ndo_change_mtu = ixgbe_change_mtu,
7016 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7017 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7018 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7019 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7020 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7021 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7022 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7023 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7024 .ndo_get_stats64 = ixgbe_get_stats64,
0edc3527
SH		 7025#ifdef CONFIG_NET_POLL_CONTROLLER
7026 .ndo_poll_controller = ixgbe_netpoll,
7027#endif
332d4a7d
YZ		 7028#ifdef IXGBE_FCOE
7029 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7030 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7031 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7032 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7033 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7034 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7035#endif /* IXGBE_FCOE */
0edc3527
SH		 7036};
7037
1cdd1ec8
GR		 7038static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7039 const struct ixgbe_info *ii)
7040{
7041#ifdef CONFIG_PCI_IOV
7042 struct ixgbe_hw *hw = &adapter->hw;
7043 int err;
7044
3377eba7 7045 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
1cdd1ec8
GR		 7046 return;
7047
7048 /* The 82599 supports up to 64 VFs per physical function
7049 * but this implementation limits allocation to 63 so that
7050 * basic networking resources are still available to the
7051 * physical function
7052 */
7053 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7054 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7055 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7056 if (err) {
396e799c 7057 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 7058 goto err_novfs;
7059 }
7060 /* If call to enable VFs succeeded then allocate memory
7061 * for per VF control structures.
7062 */
7063 adapter->vfinfo =
7064 kcalloc(adapter->num_vfs,
7065 sizeof(struct vf_data_storage), GFP_KERNEL);
7066 if (adapter->vfinfo) {
7067 /* Now that we're sure SR-IOV is enabled
7068 * and memory allocated set up the mailbox parameters
7069 */
7070 ixgbe_init_mbx_params_pf(hw);
7071 memcpy(&hw->mbx.ops, ii->mbx_ops,
7072 sizeof(hw->mbx.ops));
7073
7074 /* Disable RSC when in SR-IOV mode */
7075 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7076 IXGBE_FLAG2_RSC_ENABLED);
7077 return;
7078 }
7079
7080 /* Oh oh */
396e799c
ET		 7081 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7082 "SRIOV disabled\n");
1cdd1ec8
GR		 7083 pci_disable_sriov(adapter->pdev);
7084
7085err_novfs:
7086 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7087 adapter->num_vfs = 0;
7088#endif /* CONFIG_PCI_IOV */
7089}
7090
9a799d71
AK		 7091/**
7092 * ixgbe_probe - Device Initialization Routine
7093 * @pdev: PCI device information struct
7094 * @ent: entry in ixgbe_pci_tbl
7095 *
7096 * Returns 0 on success, negative on failure
7097 *
7098 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7099 * The OS initialization, configuring of the adapter private structure,
7100 * and a hardware reset occur.
7101 **/
7102static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7103 const struct pci_device_id *ent)
9a799d71
AK		 7104{
7105 struct net_device *netdev;
7106 struct ixgbe_adapter *adapter = NULL;
7107 struct ixgbe_hw *hw;
7108 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7109 static int cards_found;
7110 int i, err, pci_using_dac;
289700db 7111 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7112 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7113#ifdef IXGBE_FCOE
7114 u16 device_caps;
7115#endif
289700db 7116 u32 eec;
9a799d71 7117
bded64a7
AG		 7118 /* Catch broken hardware that put the wrong VF device ID in
7119 * the PCIe SR-IOV capability.
7120 */
7121 if (pdev->is_virtfn) {
7122 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7123 pci_name(pdev), pdev->vendor, pdev->device);
7124 return -EINVAL;
7125 }
7126
9ce77666 7127 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7128 if (err)
7129 return err;
7130
1b507730
NN		 7131 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7132 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7133 pci_using_dac = 1;
7134 } else {
1b507730 7135 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7136 if (err) {
1b507730
NN		 7137 err = dma_set_coherent_mask(&pdev->dev,
7138 DMA_BIT_MASK(32));
9a799d71 7139 if (err) {
b8bc0421
DC		 7140 dev_err(&pdev->dev,
7141 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7142 goto err_dma;
7143 }
7144 }
7145 pci_using_dac = 0;
7146 }
7147
9ce77666 7148 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7149 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7150 if (err) {
b8bc0421
DC		 7151 dev_err(&pdev->dev,
7152 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7153 goto err_pci_reg;
7154 }
7155
19d5afd4 7156 pci_enable_pcie_error_reporting(pdev);
6fabd715 7157
9a799d71 7158 pci_set_master(pdev);
fb3b27bc 7159 pci_save_state(pdev);
9a799d71 7160
c85a2618
JF		 7161 if (ii->mac == ixgbe_mac_82598EB)
7162 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7163 else
7164 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7165
e5b64635 7166#if defined(CONFIG_DCB)
c85a2618 7167 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
e5b64635 7168#elif defined(IXGBE_FCOE)
c85a2618
JF		 7169 indices += min_t(unsigned int, num_possible_cpus(),
7170 IXGBE_MAX_FCOE_INDICES);
7171#endif
c85a2618 7172 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7173 if (!netdev) {
7174 err = -ENOMEM;
7175 goto err_alloc_etherdev;
7176 }
7177
9a799d71
AK		 7178 SET_NETDEV_DEV(netdev, &pdev->dev);
7179
9a799d71 7180 adapter = netdev_priv(netdev);
c60fbb00 7181 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7182
7183 adapter->netdev = netdev;
7184 adapter->pdev = pdev;
7185 hw = &adapter->hw;
7186 hw->back = adapter;
7187 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7188
05857980 7189 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7190 pci_resource_len(pdev, 0));
9a799d71
AK		 7191 if (!hw->hw_addr) {
7192 err = -EIO;
7193 goto err_ioremap;
7194 }
7195
7196 for (i = 1; i <= 5; i++) {
7197 if (pci_resource_len(pdev, i) == 0)
7198 continue;
7199 }
7200
0edc3527 7201 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7202 ixgbe_set_ethtool_ops(netdev);
9a799d71 7203 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7204 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7205
9a799d71
AK		 7206 adapter->bd_number = cards_found;
7207
9a799d71
AK		 7208 /* Setup hw api */
7209 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7210 hw->mac.type = ii->mac;
9a799d71 7211
c44ade9e
JB		 7212 /* EEPROM */
7213 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7214 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7215 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7216 if (!(eec & (1 << 8)))
7217 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7218
7219 /* PHY */
7220 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7221 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7222 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7223 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7224 hw->phy.mdio.mmds = 0;
7225 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7226 hw->phy.mdio.dev = netdev;
7227 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7228 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 7229
7230 /* set up this timer and work struct before calling get_invariants
7231 * which might start the timer
7232 */
7233 init_timer(&adapter->sfp_timer);
c061b18d 7234 adapter->sfp_timer.function = ixgbe_sfp_timer;
c4900be0
DS		 7235 adapter->sfp_timer.data = (unsigned long) adapter;
7236
7237 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 7238
e8e26350
PW		 7239 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7240 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
7241
7242 /* a new SFP+ module arrival, called from GPI SDP2 context */
7243 INIT_WORK(&adapter->sfp_config_module_task,
e8e9f696 7244 ixgbe_sfp_config_module_task);
e8e26350 7245
8ca783ab 7246 ii->get_invariants(hw);
9a799d71
AK		 7247
7248 /* setup the private structure */
7249 err = ixgbe_sw_init(adapter);
7250 if (err)
7251 goto err_sw_init;
7252
e86bff0e 7253 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7254 switch (adapter->hw.mac.type) {
7255 case ixgbe_mac_82599EB:
7256 case ixgbe_mac_X540:
e86bff0e 7257 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7258 break;
7259 default:
7260 break;
7261 }
e86bff0e 7262
bf069c97
DS		 7263 /*
7264 * If there is a fan on this device and it has failed log the
7265 * failure.
7266 */
7267 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7268 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7269 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7270 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7271 }
7272
c44ade9e 7273 /* reset_hw fills in the perm_addr as well */
119fc60a 7274 hw->phy.reset_if_overtemp = true;
c44ade9e 7275 err = hw->mac.ops.reset_hw(hw);
119fc60a 7276 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7277 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7278 hw->mac.type == ixgbe_mac_82598EB) {
7279 /*
7280 * Start a kernel thread to watch for a module to arrive.
7281 * Only do this for 82598, since 82599 will generate
7282 * interrupts on module arrival.
7283 */
7284 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7285 mod_timer(&adapter->sfp_timer,
7286 round_jiffies(jiffies + (2 * HZ)));
7287 err = 0;
7288 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 7289 e_dev_err("failed to initialize because an unsupported SFP+ "
7290 "module type was detected.\n");
7291 e_dev_err("Reload the driver after installing a supported "
7292 "module.\n");
04f165ef
PW		 7293 goto err_sw_init;
7294 } else if (err) {
849c4542 7295 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7296 goto err_sw_init;
7297 }
7298
1cdd1ec8
GR		 7299 ixgbe_probe_vf(adapter, ii);
7300
396e799c 7301 netdev->features = NETIF_F_SG |
e8e9f696
JP		 7302 NETIF_F_IP_CSUM |
7303 NETIF_F_HW_VLAN_TX |
7304 NETIF_F_HW_VLAN_RX |
7305 NETIF_F_HW_VLAN_FILTER;
9a799d71 7306
e9990a9c 7307 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 7308 netdev->features |= NETIF_F_TSO;
9a799d71 7309 netdev->features |= NETIF_F_TSO6;
78b6f4ce 7310 netdev->features |= NETIF_F_GRO;
ad31c402 7311
45a5ead0
JB		 7312 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7313 netdev->features |= NETIF_F_SCTP_CSUM;
7314
ad31c402
JK		 7315 netdev->vlan_features |= NETIF_F_TSO;
7316 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7317 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7318 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7319 netdev->vlan_features |= NETIF_F_SG;
7320
1cdd1ec8
GR		 7321 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7322 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7323 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 7324 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7325 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7326
7a6b6f51 7327#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7328 netdev->dcbnl_ops = &dcbnl_ops;
7329#endif
7330
eacd73f7 7331#ifdef IXGBE_FCOE
0d551589 7332 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7333 if (hw->mac.ops.get_device_caps) {
7334 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7335 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7336 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7337 }
7338 }
5e09d7f6
YZ		 7339 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7340 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7341 netdev->vlan_features |= NETIF_F_FSO;
7342 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7343 }
eacd73f7 7344#endif /* IXGBE_FCOE */
7b872a55 7345 if (pci_using_dac) {
9a799d71 7346 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7347 netdev->vlan_features |= NETIF_F_HIGHDMA;
7348 }
9a799d71 7349
0c19d6af 7350 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7351 netdev->features |= NETIF_F_LRO;
7352
9a799d71 7353 /* make sure the EEPROM is good */
c44ade9e 7354 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7355 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7356 err = -EIO;
7357 goto err_eeprom;
7358 }
7359
7360 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7361 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7362
c44ade9e 7363 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7364 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7365 err = -EIO;
7366 goto err_eeprom;
7367 }
7368
c6ecf39a
DS		 7369 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7370 if (hw->mac.ops.disable_tx_laser &&
7371 ((hw->phy.multispeed_fiber) ||
9f911707 7372 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 7373 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 7374 hw->mac.ops.disable_tx_laser(hw);
7375
9a799d71 7376 init_timer(&adapter->watchdog_timer);
c061b18d 7377 adapter->watchdog_timer.function = ixgbe_watchdog;
9a799d71
AK		 7378 adapter->watchdog_timer.data = (unsigned long)adapter;
7379
7380 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 7381 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 7382
021230d4
AV		 7383 err = ixgbe_init_interrupt_scheme(adapter);
7384 if (err)
7385 goto err_sw_init;
9a799d71 7386
e8e26350 7387 switch (pdev->device) {
0b077fea
DS		 7388 case IXGBE_DEV_ID_82599_SFP:
7389 /* Only this subdevice supports WOL */
7390 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7391 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7392 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7393 break;
50d6c681
AD		 7394 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7395 /* All except this subdevice support WOL */
0b077fea
DS		 7396 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7397 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7398 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7399 break;
e8e26350 7400 case IXGBE_DEV_ID_82599_KX4:
495dce12 7401 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 7402 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 7403 break;
7404 default:
7405 adapter->wol = 0;
7406 break;
7407 }
e8e26350
PW		 7408 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7409
04f165ef
PW		 7410 /* pick up the PCI bus settings for reporting later */
7411 hw->mac.ops.get_bus_info(hw);
7412
9a799d71 7413 /* print bus type/speed/width info */
849c4542 7414 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8e9f696
JP		 7415 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7416 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7417 "Unknown"),
7418 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7419 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7420 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7421 "Unknown"),
7422 netdev->dev_addr);
289700db
DS		 7423
7424 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7425 if (err)
9fe93afd 7426 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7427 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7428 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7429 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7430 part_str);
e8e26350 7431 else
289700db
DS		 7432 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7433 hw->mac.type, hw->phy.type, part_str);
9a799d71 7434
e8e26350 7435 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7436 e_dev_warn("PCI-Express bandwidth available for this card is "
7437 "not sufficient for optimal performance.\n");
7438 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7439 "is required.\n");
0c254d86
AK		 7440 }
7441
34b0368c
PWJ		 7442 /* save off EEPROM version number */
7443 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7444
9a799d71 7445 /* reset the hardware with the new settings */
794caeb2 7446 err = hw->mac.ops.start_hw(hw);
c44ade9e 7447
794caeb2
PWJ		 7448 if (err == IXGBE_ERR_EEPROM_VERSION) {
7449 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7450 e_dev_warn("This device is a pre-production adapter/LOM. "
7451 "Please be aware there may be issues associated "
7452 "with your hardware. If you are experiencing "
7453 "problems please contact your Intel or hardware "
7454 "representative who provided you with this "
7455 "hardware.\n");
794caeb2 7456 }
9a799d71
AK		 7457 strcpy(netdev->name, "eth%d");
7458 err = register_netdev(netdev);
7459 if (err)
7460 goto err_register;
7461
54386467
JB		 7462 /* carrier off reporting is important to ethtool even BEFORE open */
7463 netif_carrier_off(netdev);
7464
c4cf55e5
PWJ		 7465 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7466 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7467 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7468
119fc60a 7469 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
e8e9f696
JP		 7470 INIT_WORK(&adapter->check_overtemp_task,
7471 ixgbe_check_overtemp_task);
5dd2d332 7472#ifdef CONFIG_IXGBE_DCA
652f093f 7473 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7474 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7475 ixgbe_setup_dca(adapter);
7476 }
7477#endif
1cdd1ec8 7478 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7479 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7480 for (i = 0; i < adapter->num_vfs; i++)
7481 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7482 }
7483
0365e6e4
PW		 7484 /* add san mac addr to netdev */
7485 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7486
849c4542 7487 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7488 cards_found++;
7489 return 0;
7490
7491err_register:
5eba3699 7492 ixgbe_release_hw_control(adapter);
7a921c93 7493 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7494err_sw_init:
7495err_eeprom:
1cdd1ec8
GR		 7496 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7497 ixgbe_disable_sriov(adapter);
c4900be0
DS		 7498 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7499 del_timer_sync(&adapter->sfp_timer);
7500 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7501 cancel_work_sync(&adapter->multispeed_fiber_task);
7502 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 7503 iounmap(hw->hw_addr);
7504err_ioremap:
7505 free_netdev(netdev);
7506err_alloc_etherdev:
e8e9f696
JP		 7507 pci_release_selected_regions(pdev,
7508 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7509err_pci_reg:
7510err_dma:
7511 pci_disable_device(pdev);
7512 return err;
7513}
7514
7515/**
7516 * ixgbe_remove - Device Removal Routine
7517 * @pdev: PCI device information struct
7518 *
7519 * ixgbe_remove is called by the PCI subsystem to alert the driver
7520 * that it should release a PCI device. The could be caused by a
7521 * Hot-Plug event, or because the driver is going to be removed from
7522 * memory.
7523 **/
7524static void __devexit ixgbe_remove(struct pci_dev *pdev)
7525{
c60fbb00
AD		 7526 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7527 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7528
7529 set_bit(__IXGBE_DOWN, &adapter->state);
760141a5
TH		 7530
7531 /*
7532 * The timers may be rescheduled, so explicitly disable them
7533 * from being rescheduled.
c4900be0
DS		 7534 */
7535 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71 7536 del_timer_sync(&adapter->watchdog_timer);
c4900be0 7537 del_timer_sync(&adapter->sfp_timer);
760141a5 7538
c4900be0
DS		 7539 cancel_work_sync(&adapter->watchdog_task);
7540 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7541 cancel_work_sync(&adapter->multispeed_fiber_task);
7542 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 7543 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7544 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7545 cancel_work_sync(&adapter->fdir_reinit_task);
760141a5
TH		 7546 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7547 cancel_work_sync(&adapter->check_overtemp_task);
9a799d71 7548
5dd2d332 7549#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7550 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7551 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7552 dca_remove_requester(&pdev->dev);
7553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7554 }
7555
7556#endif
332d4a7d
YZ		 7557#ifdef IXGBE_FCOE
7558 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7559 ixgbe_cleanup_fcoe(adapter);
7560
7561#endif /* IXGBE_FCOE */
0365e6e4
PW		 7562
7563 /* remove the added san mac */
7564 ixgbe_del_sanmac_netdev(netdev);
7565
c4900be0
DS		 7566 if (netdev->reg_state == NETREG_REGISTERED)
7567 unregister_netdev(netdev);
9a799d71 7568
1cdd1ec8
GR		 7569 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7570 ixgbe_disable_sriov(adapter);
7571
7a921c93 7572 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7573
021230d4 7574 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7575
7576 iounmap(adapter->hw.hw_addr);
9ce77666 7577 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7578 IORESOURCE_MEM));
9a799d71 7579
849c4542 7580 e_dev_info("complete\n");
021230d4 7581
9a799d71
AK		 7582 free_netdev(netdev);
7583
19d5afd4 7584 pci_disable_pcie_error_reporting(pdev);
6fabd715 7585
9a799d71
AK		 7586 pci_disable_device(pdev);
7587}
7588
7589/**
7590 * ixgbe_io_error_detected - called when PCI error is detected
7591 * @pdev: Pointer to PCI device
7592 * @state: The current pci connection state
7593 *
7594 * This function is called after a PCI bus error affecting
7595 * this device has been detected.
7596 */
7597static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7598 pci_channel_state_t state)
9a799d71 7599{
c60fbb00
AD		 7600 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7601 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7602
7603 netif_device_detach(netdev);
7604
3044b8d1
BL		 7605 if (state == pci_channel_io_perm_failure)
7606 return PCI_ERS_RESULT_DISCONNECT;
7607
9a799d71
AK		 7608 if (netif_running(netdev))
7609 ixgbe_down(adapter);
7610 pci_disable_device(pdev);
7611
b4617240 7612 /* Request a slot reset. */
9a799d71
AK		 7613 return PCI_ERS_RESULT_NEED_RESET;
7614}
7615
7616/**
7617 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7618 * @pdev: Pointer to PCI device
7619 *
7620 * Restart the card from scratch, as if from a cold-boot.
7621 */
7622static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7623{
c60fbb00 7624 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7625 pci_ers_result_t result;
7626 int err;
9a799d71 7627
9ce77666 7628 if (pci_enable_device_mem(pdev)) {
396e799c 7629 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7630 result = PCI_ERS_RESULT_DISCONNECT;
7631 } else {
7632 pci_set_master(pdev);
7633 pci_restore_state(pdev);
c0e1f68b 7634 pci_save_state(pdev);
9a799d71 7635
dd4d8ca6 7636 pci_wake_from_d3(pdev, false);
9a799d71 7637
6fabd715 7638 ixgbe_reset(adapter);
88512539 7639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7640 result = PCI_ERS_RESULT_RECOVERED;
7641 }
7642
7643 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7644 if (err) {
849c4542
ET		 7645 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7646 "failed 0x%0x\n", err);
6fabd715
PWJ		 7647 /* non-fatal, continue */
7648 }
9a799d71 7649
6fabd715 7650 return result;
9a799d71
AK		 7651}
7652
7653/**
7654 * ixgbe_io_resume - called when traffic can start flowing again.
7655 * @pdev: Pointer to PCI device
7656 *
7657 * This callback is called when the error recovery driver tells us that
7658 * its OK to resume normal operation.
7659 */
7660static void ixgbe_io_resume(struct pci_dev *pdev)
7661{
c60fbb00
AD		 7662 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7663 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7664
7665 if (netif_running(netdev)) {
7666 if (ixgbe_up(adapter)) {
396e799c 7667 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7668 return;
7669 }
7670 }
7671
7672 netif_device_attach(netdev);
9a799d71
AK		 7673}
7674
7675static struct pci_error_handlers ixgbe_err_handler = {
7676 .error_detected = ixgbe_io_error_detected,
7677 .slot_reset = ixgbe_io_slot_reset,
7678 .resume = ixgbe_io_resume,
7679};
7680
7681static struct pci_driver ixgbe_driver = {
7682 .name = ixgbe_driver_name,
7683 .id_table = ixgbe_pci_tbl,
7684 .probe = ixgbe_probe,
7685 .remove = __devexit_p(ixgbe_remove),
7686#ifdef CONFIG_PM
7687 .suspend = ixgbe_suspend,
7688 .resume = ixgbe_resume,
7689#endif
7690 .shutdown = ixgbe_shutdown,
7691 .err_handler = &ixgbe_err_handler
7692};
7693
7694/**
7695 * ixgbe_init_module - Driver Registration Routine
7696 *
7697 * ixgbe_init_module is the first routine called when the driver is
7698 * loaded. All it does is register with the PCI subsystem.
7699 **/
7700static int __init ixgbe_init_module(void)
7701{
7702 int ret;
c7689578 7703 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7704 pr_info("%s\n", ixgbe_copyright);
9a799d71 7705
5dd2d332 7706#ifdef CONFIG_IXGBE_DCA
bd0362dd 7707 dca_register_notify(&dca_notifier);
bd0362dd 7708#endif
5dd2d332 7709
9a799d71
AK		 7710 ret = pci_register_driver(&ixgbe_driver);
7711 return ret;
7712}
b4617240 7713
9a799d71
AK		 7714module_init(ixgbe_init_module);
7715
7716/**
7717 * ixgbe_exit_module - Driver Exit Cleanup Routine
7718 *
7719 * ixgbe_exit_module is called just before the driver is removed
7720 * from memory.
7721 **/
7722static void __exit ixgbe_exit_module(void)
7723{
5dd2d332 7724#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7725 dca_unregister_notify(&dca_notifier);
7726#endif
9a799d71 7727 pci_unregister_driver(&ixgbe_driver);
1a51502b 7728 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7729}
bd0362dd 7730
5dd2d332 7731#ifdef CONFIG_IXGBE_DCA
bd0362dd 7732static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7733 void *p)
bd0362dd
JC		 7734{
7735 int ret_val;
7736
7737 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7738 __ixgbe_notify_dca);
bd0362dd
JC		 7739
7740 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7741}
b453368d 7742
5dd2d332 7743#endif /* CONFIG_IXGBE_DCA */
849c4542 7744
9a799d71
AK		 7745module_exit(ixgbe_exit_module);
7746
7747/* ixgbe_main.c */
Linux kernel - Deliverables
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