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ixgbe: enable extremely low latency
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
b4617240 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
92eb879f 55#define DRV_VERSION "2.0.62-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
312eb931
DS		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
112 board_82599 },
9a799d71
AK		 113
114 /* required last entry */
115 {0, }
116};
117MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
118
5dd2d332 119#ifdef CONFIG_IXGBE_DCA
bd0362dd 120static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 121 void *p);
bd0362dd
JC		 122static struct notifier_block dca_notifier = {
123 .notifier_call = ixgbe_notify_dca,
124 .next = NULL,
125 .priority = 0
126};
127#endif
128
1cdd1ec8
GR		 129#ifdef CONFIG_PCI_IOV
130static unsigned int max_vfs;
131module_param(max_vfs, uint, 0);
132MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
133 "per physical function");
134#endif /* CONFIG_PCI_IOV */
135
9a799d71
AK		 136MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
137MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
138MODULE_LICENSE("GPL");
139MODULE_VERSION(DRV_VERSION);
140
141#define DEFAULT_DEBUG_LEVEL_SHIFT 3
142
1cdd1ec8
GR		 143static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
144{
145 struct ixgbe_hw *hw = &adapter->hw;
146 u32 gcr;
147 u32 gpie;
148 u32 vmdctl;
149
150#ifdef CONFIG_PCI_IOV
151 /* disable iov and allow time for transactions to clear */
152 pci_disable_sriov(adapter->pdev);
153#endif
154
155 /* turn off device IOV mode */
156 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
157 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
158 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
159 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
160 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
161 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
162
163 /* set default pool back to 0 */
164 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
165 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
166 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
167
168 /* take a breather then clean up driver data */
169 msleep(100);
170 if (adapter->vfinfo)
171 kfree(adapter->vfinfo);
172 adapter->vfinfo = NULL;
173
174 adapter->num_vfs = 0;
175 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
176}
177
5eba3699
AV		 178static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
179{
180 u32 ctrl_ext;
181
182 /* Let firmware take over control of h/w */
183 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
184 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 185 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 186}
187
188static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
189{
190 u32 ctrl_ext;
191
192 /* Let firmware know the driver has taken over */
193 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
194 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 195 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 196}
9a799d71 197
e8e26350
PW		 198/*
199 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
200 * @adapter: pointer to adapter struct
201 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
202 * @queue: queue to map the corresponding interrupt to
203 * @msix_vector: the vector to map to the corresponding queue
204 *
205 */
206static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
207 u8 queue, u8 msix_vector)
9a799d71
AK		 208{
209 u32 ivar, index;
e8e26350
PW		 210 struct ixgbe_hw *hw = &adapter->hw;
211 switch (hw->mac.type) {
212 case ixgbe_mac_82598EB:
213 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
214 if (direction == -1)
215 direction = 0;
216 index = (((direction * 64) + queue) >> 2) & 0x1F;
217 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
218 ivar &= ~(0xFF << (8 * (queue & 0x3)));
219 ivar |= (msix_vector << (8 * (queue & 0x3)));
220 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
221 break;
222 case ixgbe_mac_82599EB:
223 if (direction == -1) {
224 /* other causes */
225 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
226 index = ((queue & 1) * 8);
227 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
228 ivar &= ~(0xFF << index);
229 ivar |= (msix_vector << index);
230 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
231 break;
232 } else {
233 /* tx or rx causes */
234 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
235 index = ((16 * (queue & 1)) + (8 * direction));
236 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
237 ivar &= ~(0xFF << index);
238 ivar |= (msix_vector << index);
239 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
240 break;
241 }
242 default:
243 break;
244 }
9a799d71
AK		 245}
246
fe49f04a
AD		 247static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
248 u64 qmask)
249{
250 u32 mask;
251
252 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
253 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
254 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
255 } else {
256 mask = (qmask & 0xFFFFFFFF);
257 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
258 mask = (qmask >> 32);
259 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
260 }
261}
262
9a799d71 263static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 264 struct ixgbe_tx_buffer
265 *tx_buffer_info)
9a799d71 266{
e5a43549
AD		 267 if (tx_buffer_info->dma) {
268 if (tx_buffer_info->mapped_as_page)
269 pci_unmap_page(adapter->pdev,
270 tx_buffer_info->dma,
271 tx_buffer_info->length,
272 PCI_DMA_TODEVICE);
273 else
274 pci_unmap_single(adapter->pdev,
275 tx_buffer_info->dma,
276 tx_buffer_info->length,
277 PCI_DMA_TODEVICE);
278 tx_buffer_info->dma = 0;
279 }
9a799d71
AK		 280 if (tx_buffer_info->skb) {
281 dev_kfree_skb_any(tx_buffer_info->skb);
282 tx_buffer_info->skb = NULL;
283 }
44df32c5 284 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 285 /* tx_buffer_info must be completely set up in the transmit path */
286}
287
26f23d82
YZ		 288/**
289 * ixgbe_tx_is_paused - check if the tx ring is paused
290 * @adapter: the ixgbe adapter
291 * @tx_ring: the corresponding tx_ring
292 *
293 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
294 * corresponding TC of this tx_ring when checking TFCS.
295 *
296 * Returns : true if paused
297 */
298static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
299 struct ixgbe_ring *tx_ring)
300{
26f23d82
YZ		 301 u32 txoff = IXGBE_TFCS_TXOFF;
302
303#ifdef CONFIG_IXGBE_DCB
304 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
30b76832 305 int tc;
26f23d82
YZ		 306 int reg_idx = tx_ring->reg_idx;
307 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
308
6837e895
PW		 309 switch (adapter->hw.mac.type) {
310 case ixgbe_mac_82598EB:
26f23d82
YZ		 311 tc = reg_idx >> 2;
312 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 313 break;
314 case ixgbe_mac_82599EB:
26f23d82
YZ		 315 tc = 0;
316 txoff = IXGBE_TFCS_TXOFF;
317 if (dcb_i == 8) {
318 /* TC0, TC1 */
319 tc = reg_idx >> 5;
320 if (tc == 2) /* TC2, TC3 */
321 tc += (reg_idx - 64) >> 4;
322 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
323 tc += 1 + ((reg_idx - 96) >> 3);
324 } else if (dcb_i == 4) {
325 /* TC0, TC1 */
326 tc = reg_idx >> 6;
327 if (tc == 1) {
328 tc += (reg_idx - 64) >> 5;
329 if (tc == 2) /* TC2, TC3 */
330 tc += (reg_idx - 96) >> 4;
331 }
332 }
6837e895
PW		 333 break;
334 default:
335 tc = 0;
26f23d82
YZ		 336 }
337 txoff <<= tc;
338 }
339#endif
340 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
341}
342
9a799d71 343static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 344 struct ixgbe_ring *tx_ring,
345 unsigned int eop)
9a799d71 346{
e01c31a5 347 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 348
9a799d71 349 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 350 * check with the clearing of time_stamp and movement of eop */
9a799d71 351 adapter->detect_tx_hung = false;
44df32c5 352 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 353 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
26f23d82 354 !ixgbe_tx_is_paused(adapter, tx_ring)) {
9a799d71 355 /* detected Tx unit hang */
e01c31a5
JB		 356 union ixgbe_adv_tx_desc *tx_desc;
357 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 358 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 359 " Tx Queue <%d>\n"
360 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 361 " next_to_use <%x>\n"
362 " next_to_clean <%x>\n"
363 "tx_buffer_info[next_to_clean]\n"
364 " time_stamp <%lx>\n"
e01c31a5
JB		 365 " jiffies <%lx>\n",
366 tx_ring->queue_index,
44df32c5
AD		 367 IXGBE_READ_REG(hw, tx_ring->head),
368 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 369 tx_ring->next_to_use, eop,
370 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 371 return true;
372 }
373
374 return false;
375}
376
b4617240
PW		 377#define IXGBE_MAX_TXD_PWR 14
378#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 379
380/* Tx Descriptors needed, worst case */
381#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
382 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
383#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 384 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 385
e01c31a5
JB		 386static void ixgbe_tx_timeout(struct net_device *netdev);
387
9a799d71
AK		 388/**
389 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 390 * @q_vector: structure containing interrupt and ring information
e01c31a5 391 * @tx_ring: tx ring to clean
9a799d71 392 **/
fe49f04a 393static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 394 struct ixgbe_ring *tx_ring)
9a799d71 395{
fe49f04a 396 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 397 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 398 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
399 struct ixgbe_tx_buffer *tx_buffer_info;
400 unsigned int i, eop, count = 0;
e01c31a5 401 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 402
403 i = tx_ring->next_to_clean;
12207e49
PWJ		 404 eop = tx_ring->tx_buffer_info[i].next_to_watch;
405 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
406
407 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 408 (count < tx_ring->work_limit)) {
12207e49
PWJ		 409 bool cleaned = false;
410 for ( ; !cleaned; count++) {
411 struct sk_buff *skb;
9a799d71
AK		 412 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
413 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 414 cleaned = (i == eop);
e01c31a5 415 skb = tx_buffer_info->skb;
9a799d71 416
12207e49 417 if (cleaned && skb) {
e092be60 418 unsigned int segs, bytecount;
3d8fd385 419 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 420
421 /* gso_segs is currently only valid for tcp */
e092be60 422 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 423#ifdef IXGBE_FCOE
424 /* adjust for FCoE Sequence Offload */
425 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
426 && (skb->protocol == htons(ETH_P_FCOE)) &&
427 skb_is_gso(skb)) {
428 hlen = skb_transport_offset(skb) +
429 sizeof(struct fc_frame_header) +
430 sizeof(struct fcoe_crc_eof);
431 segs = DIV_ROUND_UP(skb->len - hlen,
432 skb_shinfo(skb)->gso_size);
433 }
434#endif /* IXGBE_FCOE */
e092be60 435 /* multiply data chunks by size of headers */
3d8fd385 436 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 437 total_packets += segs;
438 total_bytes += bytecount;
e092be60 439 }
e01c31a5 440
9a799d71 441 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 442 tx_buffer_info);
9a799d71 443
12207e49
PWJ		 444 tx_desc->wb.status = 0;
445
9a799d71
AK		 446 i++;
447 if (i == tx_ring->count)
448 i = 0;
e01c31a5 449 }
12207e49
PWJ		 450
451 eop = tx_ring->tx_buffer_info[i].next_to_watch;
452 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
453 }
454
9a799d71
AK		 455 tx_ring->next_to_clean = i;
456
e092be60 457#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 458 if (unlikely(count && netif_carrier_ok(netdev) &&
459 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 460 /* Make sure that anybody stopping the queue after this
461 * sees the new next_to_clean.
462 */
463 smp_mb();
30eba97a
AV		 464 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
465 !test_bit(__IXGBE_DOWN, &adapter->state)) {
466 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 467 ++tx_ring->restart_queue;
30eba97a 468 }
e092be60 469 }
9a799d71 470
e01c31a5
JB		 471 if (adapter->detect_tx_hung) {
472 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
473 /* schedule immediate reset if we believe we hung */
474 DPRINTK(PROBE, INFO,
475 "tx hang %d detected, resetting adapter\n",
476 adapter->tx_timeout_count + 1);
477 ixgbe_tx_timeout(adapter->netdev);
478 }
479 }
9a799d71 480
e01c31a5 481 /* re-arm the interrupt */
fe49f04a
AD		 482 if (count >= tx_ring->work_limit)
483 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 484
e01c31a5
JB		 485 tx_ring->total_bytes += total_bytes;
486 tx_ring->total_packets += total_packets;
e01c31a5 487 tx_ring->stats.packets += total_packets;
12207e49 488 tx_ring->stats.bytes += total_bytes;
9a1a69ad 489 return (count < tx_ring->work_limit);
9a799d71
AK		 490}
491
5dd2d332 492#ifdef CONFIG_IXGBE_DCA
bd0362dd 493static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 494 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 495{
496 u32 rxctrl;
497 int cpu = get_cpu();
4a0b9ca0 498 int q = rx_ring->reg_idx;
bd0362dd 499
3a581073 500 if (rx_ring->cpu != cpu) {
bd0362dd 501 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 502 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
503 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
504 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
505 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
506 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
507 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
508 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
509 }
bd0362dd
JC		 510 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
511 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 512 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
513 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 514 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 516 rx_ring->cpu = cpu;
bd0362dd
JC		 517 }
518 put_cpu();
519}
520
521static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 522 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 523{
524 u32 txctrl;
525 int cpu = get_cpu();
4a0b9ca0 526 int q = tx_ring->reg_idx;
ee5f784a 527 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 528
3a581073 529 if (tx_ring->cpu != cpu) {
e8e26350 530 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 531 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 532 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
533 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 534 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
535 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 536 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 537 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 538 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
539 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 540 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
541 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
542 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 543 }
3a581073 544 tx_ring->cpu = cpu;
bd0362dd
JC		 545 }
546 put_cpu();
547}
548
549static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
550{
551 int i;
552
553 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
554 return;
555
e35ec126
AD		 556 /* always use CB2 mode, difference is masked in the CB driver */
557 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
558
bd0362dd 559 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 560 adapter->tx_ring[i]->cpu = -1;
561 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 562 }
563 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 564 adapter->rx_ring[i]->cpu = -1;
565 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 566 }
567}
568
569static int __ixgbe_notify_dca(struct device *dev, void *data)
570{
571 struct net_device *netdev = dev_get_drvdata(dev);
572 struct ixgbe_adapter *adapter = netdev_priv(netdev);
573 unsigned long event = *(unsigned long *)data;
574
575 switch (event) {
576 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 577 /* if we're already enabled, don't do it again */
578 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
579 break;
652f093f 580 if (dca_add_requester(dev) == 0) {
96b0e0f6 581 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 582 ixgbe_setup_dca(adapter);
583 break;
584 }
585 /* Fall Through since DCA is disabled. */
586 case DCA_PROVIDER_REMOVE:
587 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
588 dca_remove_requester(dev);
589 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
590 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
591 }
592 break;
593 }
594
652f093f 595 return 0;
bd0362dd
JC		 596}
597
5dd2d332 598#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 599/**
600 * ixgbe_receive_skb - Send a completed packet up the stack
601 * @adapter: board private structure
602 * @skb: packet to send up
177db6ff
MC		 603 * @status: hardware indication of status of receive
604 * @rx_ring: rx descriptor ring (for a specific queue) to setup
605 * @rx_desc: rx descriptor
9a799d71 606 **/
78b6f4ce 607static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 608 struct sk_buff *skb, u8 status,
fdaff1ce 609 struct ixgbe_ring *ring,
177db6ff 610 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 611{
78b6f4ce
HX		 612 struct ixgbe_adapter *adapter = q_vector->adapter;
613 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 614 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
615 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 616
fdaff1ce 617 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 618 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 619 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 620 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 621 else
78b6f4ce 622 napi_gro_receive(napi, skb);
177db6ff 623 } else {
8a62babf 624 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 625 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
626 else
627 netif_rx(skb);
9a799d71
AK		 628 }
629}
630
e59bd25d
AV		 631/**
632 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
633 * @adapter: address of board private structure
634 * @status_err: hardware indication of status of receive
635 * @skb: skb currently being received and modified
636 **/
9a799d71 637static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 638 union ixgbe_adv_rx_desc *rx_desc,
639 struct sk_buff *skb)
9a799d71 640{
8bae1b2b
DS		 641 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
642
9a799d71
AK		 643 skb->ip_summed = CHECKSUM_NONE;
644
712744be
JB		 645 /* Rx csum disabled */
646 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 647 return;
e59bd25d
AV		 648
649 /* if IP and error */
650 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
651 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 652 adapter->hw_csum_rx_error++;
653 return;
654 }
e59bd25d
AV		 655
656 if (!(status_err & IXGBE_RXD_STAT_L4CS))
657 return;
658
659 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 660 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
661
662 /*
663 * 82599 errata, UDP frames with a 0 checksum can be marked as
664 * checksum errors.
665 */
666 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
667 (adapter->hw.mac.type == ixgbe_mac_82599EB))
668 return;
669
e59bd25d
AV		 670 adapter->hw_csum_rx_error++;
671 return;
672 }
673
9a799d71 674 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 675 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 676}
677
e8e26350
PW		 678static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
679 struct ixgbe_ring *rx_ring, u32 val)
680{
681 /*
682 * Force memory writes to complete before letting h/w
683 * know there are new descriptors to fetch. (Only
684 * applicable for weak-ordered memory model archs,
685 * such as IA-64).
686 */
687 wmb();
688 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
689}
690
9a799d71
AK		 691/**
692 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
693 * @adapter: address of board private structure
694 **/
695static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 696 struct ixgbe_ring *rx_ring,
697 int cleaned_count)
9a799d71 698{
9a799d71
AK		 699 struct pci_dev *pdev = adapter->pdev;
700 union ixgbe_adv_rx_desc *rx_desc;
3a581073 701 struct ixgbe_rx_buffer *bi;
9a799d71 702 unsigned int i;
9a799d71
AK		 703
704 i = rx_ring->next_to_use;
3a581073 705 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 706
707 while (cleaned_count--) {
708 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
709
762f4c57 710 if (!bi->page_dma &&
6e455b89 711 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 712 if (!bi->page) {
762f4c57
JB		 713 bi->page = alloc_page(GFP_ATOMIC);
714 if (!bi->page) {
715 adapter->alloc_rx_page_failed++;
716 goto no_buffers;
717 }
718 bi->page_offset = 0;
719 } else {
720 /* use a half page if we're re-using */
721 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 722 }
762f4c57
JB		 723
724 bi->page_dma = pci_map_page(pdev, bi->page,
725 bi->page_offset,
726 (PAGE_SIZE / 2),
727 PCI_DMA_FROMDEVICE);
9a799d71
AK		 728 }
729
3a581073 730 if (!bi->skb) {
5ecc3614 731 struct sk_buff *skb;
7ca3bc58
JB		 732 /* netdev_alloc_skb reserves 32 bytes up front!! */
733 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
734 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 735
736 if (!skb) {
737 adapter->alloc_rx_buff_failed++;
738 goto no_buffers;
739 }
740
7ca3bc58
JB		 741 /* advance the data pointer to the next cache line */
742 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
743 - skb->data));
744
3a581073 745 bi->skb = skb;
4f57ca6e
JB		 746 bi->dma = pci_map_single(pdev, skb->data,
747 rx_ring->rx_buf_len,
3a581073 748 PCI_DMA_FROMDEVICE);
9a799d71
AK		 749 }
750 /* Refresh the desc even if buffer_addrs didn't change because
751 * each write-back erases this info. */
6e455b89 752 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 753 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
754 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 755 } else {
3a581073 756 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 757 }
758
759 i++;
760 if (i == rx_ring->count)
761 i = 0;
3a581073 762 bi = &rx_ring->rx_buffer_info[i];
9a799d71 763 }
7c6e0a43 764
9a799d71
AK		 765no_buffers:
766 if (rx_ring->next_to_use != i) {
767 rx_ring->next_to_use = i;
768 if (i-- == 0)
769 i = (rx_ring->count - 1);
770
e8e26350 771 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 772 }
773}
774
7c6e0a43
JB		 775static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
776{
777 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
778}
779
780static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
781{
782 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
783}
784
f8212f97
AD		 785static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
786{
787 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
788 IXGBE_RXDADV_RSCCNT_MASK) >>
789 IXGBE_RXDADV_RSCCNT_SHIFT;
790}
791
792/**
793 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
794 * @skb: pointer to the last skb in the rsc queue
94b982b2 795 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 796 *
797 * This function changes a queue full of hw rsc buffers into a completed
798 * packet. It uses the ->prev pointers to find the first packet and then
799 * turns it into the frag list owner.
800 **/
94b982b2
MC		 801static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
802 u64 *count)
f8212f97
AD		 803{
804 unsigned int frag_list_size = 0;
805
806 while (skb->prev) {
807 struct sk_buff *prev = skb->prev;
808 frag_list_size += skb->len;
809 skb->prev = NULL;
810 skb = prev;
94b982b2 811 *count += 1;
f8212f97
AD		 812 }
813
814 skb_shinfo(skb)->frag_list = skb->next;
815 skb->next = NULL;
816 skb->len += frag_list_size;
817 skb->data_len += frag_list_size;
818 skb->truesize += frag_list_size;
819 return skb;
820}
821
43634e82
MC		 822struct ixgbe_rsc_cb {
823 dma_addr_t dma;
824};
825
826#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
827
78b6f4ce 828static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 829 struct ixgbe_ring *rx_ring,
830 int *work_done, int work_to_do)
9a799d71 831{
78b6f4ce 832 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 833 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 834 struct pci_dev *pdev = adapter->pdev;
835 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
836 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
837 struct sk_buff *skb;
f8212f97 838 unsigned int i, rsc_count = 0;
7c6e0a43 839 u32 len, staterr;
177db6ff
MC		 840 u16 hdr_info;
841 bool cleaned = false;
9a799d71 842 int cleaned_count = 0;
d2f4fbe2 843 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 844#ifdef IXGBE_FCOE
845 int ddp_bytes = 0;
846#endif /* IXGBE_FCOE */
9a799d71
AK		 847
848 i = rx_ring->next_to_clean;
9a799d71
AK		 849 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
850 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
851 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 852
853 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 854 u32 upper_len = 0;
9a799d71
AK		 855 if (*work_done >= work_to_do)
856 break;
857 (*work_done)++;
858
3c945e5b 859 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 860 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 861 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
862 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 863 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 864 if (len > IXGBE_RX_HDR_SIZE)
865 len = IXGBE_RX_HDR_SIZE;
866 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 867 } else {
9a799d71 868 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 869 }
9a799d71
AK		 870
871 cleaned = true;
872 skb = rx_buffer_info->skb;
7ca3bc58 873 prefetch(skb->data);
9a799d71
AK		 874 rx_buffer_info->skb = NULL;
875
21fa4e66 876 if (rx_buffer_info->dma) {
43634e82
MC		 877 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
878 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
879 (!(skb->prev)))
880 /*
881 * When HWRSC is enabled, delay unmapping
882 * of the first packet. It carries the
883 * header information, HW may still
884 * access the header after the writeback.
885 * Only unmap it when EOP is reached
886 */
887 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
888 else
889 pci_unmap_single(pdev, rx_buffer_info->dma,
890 rx_ring->rx_buf_len,
891 PCI_DMA_FROMDEVICE);
4f57ca6e 892 rx_buffer_info->dma = 0;
9a799d71
AK		 893 skb_put(skb, len);
894 }
895
896 if (upper_len) {
897 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 898 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 899 rx_buffer_info->page_dma = 0;
900 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 901 rx_buffer_info->page,
902 rx_buffer_info->page_offset,
903 upper_len);
904
905 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
906 (page_count(rx_buffer_info->page) != 1))
907 rx_buffer_info->page = NULL;
908 else
909 get_page(rx_buffer_info->page);
9a799d71
AK		 910
911 skb->len += upper_len;
912 skb->data_len += upper_len;
913 skb->truesize += upper_len;
914 }
915
916 i++;
917 if (i == rx_ring->count)
918 i = 0;
9a799d71
AK		 919
920 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
921 prefetch(next_rxd);
9a799d71 922 cleaned_count++;
f8212f97 923
0c19d6af 924 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 925 rsc_count = ixgbe_get_rsc_count(rx_desc);
926
927 if (rsc_count) {
928 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
929 IXGBE_RXDADV_NEXTP_SHIFT;
930 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 931 } else {
932 next_buffer = &rx_ring->rx_buffer_info[i];
933 }
934
9a799d71 935 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 936 if (skb->prev)
94b982b2
MC		 937 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
938 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
fd3686a8 939 if (IXGBE_RSC_CB(skb)->dma) {
43634e82
MC		 940 pci_unmap_single(pdev, IXGBE_RSC_CB(skb)->dma,
941 rx_ring->rx_buf_len,
942 PCI_DMA_FROMDEVICE);
fd3686a8
MC		 943 IXGBE_RSC_CB(skb)->dma = 0;
944 }
94b982b2
MC		 945 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
946 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
947 else
948 rx_ring->rsc_count++;
949 rx_ring->rsc_flush++;
950 }
9a799d71
AK		 951 rx_ring->stats.packets++;
952 rx_ring->stats.bytes += skb->len;
953 } else {
6e455b89 954 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 955 rx_buffer_info->skb = next_buffer->skb;
956 rx_buffer_info->dma = next_buffer->dma;
957 next_buffer->skb = skb;
958 next_buffer->dma = 0;
959 } else {
960 skb->next = next_buffer->skb;
961 skb->next->prev = skb;
962 }
7ca3bc58 963 rx_ring->non_eop_descs++;
9a799d71
AK		 964 goto next_desc;
965 }
966
967 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
968 dev_kfree_skb_irq(skb);
969 goto next_desc;
970 }
971
8bae1b2b 972 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 973
974 /* probably a little skewed due to removing CRC */
975 total_rx_bytes += skb->len;
976 total_rx_packets++;
977
74ce8dd2 978 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 979#ifdef IXGBE_FCOE
980 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 981 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
982 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
983 if (!ddp_bytes)
332d4a7d 984 goto next_desc;
3d8fd385 985 }
332d4a7d 986#endif /* IXGBE_FCOE */
fdaff1ce 987 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 988
989next_desc:
990 rx_desc->wb.upper.status_error = 0;
991
992 /* return some buffers to hardware, one at a time is too slow */
993 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
994 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
995 cleaned_count = 0;
996 }
997
998 /* use prefetched values */
999 rx_desc = next_rxd;
f8212f97 1000 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1001
1002 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1003 }
1004
9a799d71
AK		 1005 rx_ring->next_to_clean = i;
1006 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1007
1008 if (cleaned_count)
1009 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1010
3d8fd385
YZ		 1011#ifdef IXGBE_FCOE
1012 /* include DDPed FCoE data */
1013 if (ddp_bytes > 0) {
1014 unsigned int mss;
1015
1016 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1017 sizeof(struct fc_frame_header) -
1018 sizeof(struct fcoe_crc_eof);
1019 if (mss > 512)
1020 mss &= ~511;
1021 total_rx_bytes += ddp_bytes;
1022 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1023 }
1024#endif /* IXGBE_FCOE */
1025
f494e8fa
AV		 1026 rx_ring->total_packets += total_rx_packets;
1027 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 1028 netdev->stats.rx_bytes += total_rx_bytes;
1029 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 1030
9a799d71
AK		 1031 return cleaned;
1032}
1033
021230d4 1034static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1035/**
1036 * ixgbe_configure_msix - Configure MSI-X hardware
1037 * @adapter: board private structure
1038 *
1039 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1040 * interrupts.
1041 **/
1042static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1043{
021230d4
AV		 1044 struct ixgbe_q_vector *q_vector;
1045 int i, j, q_vectors, v_idx, r_idx;
1046 u32 mask;
9a799d71 1047
021230d4 1048 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1049
4df10466
JB		 1050 /*
1051 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1052 * corresponding register.
1053 */
1054 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1055 q_vector = adapter->q_vector[v_idx];
984b3f57 1056 /* XXX for_each_set_bit(...) */
021230d4 1057 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 1058 adapter->num_rx_queues);
021230d4
AV		 1059
1060 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1061 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1062 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1063 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 1064 adapter->num_rx_queues,
1065 r_idx + 1);
021230d4
AV		 1066 }
1067 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 1068 adapter->num_tx_queues);
021230d4
AV		 1069
1070 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1071 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1072 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1073 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 1074 adapter->num_tx_queues,
1075 r_idx + 1);
021230d4
AV		 1076 }
1077
021230d4 1078 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1079 /* tx only */
1080 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1081 else if (q_vector->rxr_count)
f7554a2b
NS		 1082 /* rx or mixed */
1083 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1084
fe49f04a 1085 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1086 }
1087
e8e26350
PW		 1088 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1089 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1090 v_idx);
1091 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1092 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1093 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1094
41fb9248 1095 /* set up to autoclear timer, and the vectors */
021230d4 1096 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1097 if (adapter->num_vfs)
1098 mask &= ~(IXGBE_EIMS_OTHER |
1099 IXGBE_EIMS_MAILBOX |
1100 IXGBE_EIMS_LSC);
1101 else
1102 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1103 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1104}
1105
f494e8fa
AV		 1106enum latency_range {
1107 lowest_latency = 0,
1108 low_latency = 1,
1109 bulk_latency = 2,
1110 latency_invalid = 255
1111};
1112
1113/**
1114 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1115 * @adapter: pointer to adapter
1116 * @eitr: eitr setting (ints per sec) to give last timeslice
1117 * @itr_setting: current throttle rate in ints/second
1118 * @packets: the number of packets during this measurement interval
1119 * @bytes: the number of bytes during this measurement interval
1120 *
1121 * Stores a new ITR value based on packets and byte
1122 * counts during the last interrupt. The advantage of per interrupt
1123 * computation is faster updates and more accurate ITR for the current
1124 * traffic pattern. Constants in this function were computed
1125 * based on theoretical maximum wire speed and thresholds were set based
1126 * on testing data as well as attempting to minimize response time
1127 * while increasing bulk throughput.
1128 * this functionality is controlled by the InterruptThrottleRate module
1129 * parameter (see ixgbe_param.c)
1130 **/
1131static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1132 u32 eitr, u8 itr_setting,
1133 int packets, int bytes)
f494e8fa
AV		 1134{
1135 unsigned int retval = itr_setting;
1136 u32 timepassed_us;
1137 u64 bytes_perint;
1138
1139 if (packets == 0)
1140 goto update_itr_done;
1141
1142
1143 /* simple throttlerate management
1144 * 0-20MB/s lowest (100000 ints/s)
1145 * 20-100MB/s low (20000 ints/s)
1146 * 100-1249MB/s bulk (8000 ints/s)
1147 */
1148 /* what was last interrupt timeslice? */
1149 timepassed_us = 1000000/eitr;
1150 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1151
1152 switch (itr_setting) {
1153 case lowest_latency:
1154 if (bytes_perint > adapter->eitr_low)
1155 retval = low_latency;
1156 break;
1157 case low_latency:
1158 if (bytes_perint > adapter->eitr_high)
1159 retval = bulk_latency;
1160 else if (bytes_perint <= adapter->eitr_low)
1161 retval = lowest_latency;
1162 break;
1163 case bulk_latency:
1164 if (bytes_perint <= adapter->eitr_high)
1165 retval = low_latency;
1166 break;
1167 }
1168
1169update_itr_done:
1170 return retval;
1171}
1172
509ee935
JB		 1173/**
1174 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1175 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1176 *
1177 * This function is made to be called by ethtool and by the driver
1178 * when it needs to update EITR registers at runtime. Hardware
1179 * specific quirks/differences are taken care of here.
1180 */
fe49f04a 1181void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1182{
fe49f04a 1183 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1184 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1185 int v_idx = q_vector->v_idx;
1186 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1187
509ee935
JB		 1188 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1189 /* must write high and low 16 bits to reset counter */
1190 itr_reg |= (itr_reg << 16);
1191 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f8d1dcaf
JB		 1192 /*
1193 * 82599 can support a value of zero, so allow it for
1194 * max interrupt rate, but there is an errata where it can
1195 * not be zero with RSC
1196 */
1197 if (itr_reg == 8 &&
1198 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1199 itr_reg = 0;
1200
509ee935
JB		 1201 /*
1202 * set the WDIS bit to not clear the timer bits and cause an
1203 * immediate assertion of the interrupt
1204 */
1205 itr_reg |= IXGBE_EITR_CNT_WDIS;
1206 }
1207 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1208}
1209
f494e8fa
AV		 1210static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1211{
1212 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1213 u32 new_itr;
1214 u8 current_itr, ret_itr;
fe49f04a 1215 int i, r_idx;
f494e8fa
AV		 1216 struct ixgbe_ring *rx_ring, *tx_ring;
1217
1218 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1219 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1220 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1221 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1222 q_vector->tx_itr,
1223 tx_ring->total_packets,
1224 tx_ring->total_bytes);
f494e8fa
AV		 1225 /* if the result for this queue would decrease interrupt
1226 * rate for this vector then use that result */
30efa5a3 1227 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1228 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1229 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1230 r_idx + 1);
f494e8fa
AV		 1231 }
1232
1233 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1234 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1235 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1236 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1237 q_vector->rx_itr,
1238 rx_ring->total_packets,
1239 rx_ring->total_bytes);
f494e8fa
AV		 1240 /* if the result for this queue would decrease interrupt
1241 * rate for this vector then use that result */
30efa5a3 1242 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1243 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1244 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1245 r_idx + 1);
f494e8fa
AV		 1246 }
1247
30efa5a3 1248 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1249
1250 switch (current_itr) {
1251 /* counts and packets in update_itr are dependent on these numbers */
1252 case lowest_latency:
1253 new_itr = 100000;
1254 break;
1255 case low_latency:
1256 new_itr = 20000; /* aka hwitr = ~200 */
1257 break;
1258 case bulk_latency:
1259 default:
1260 new_itr = 8000;
1261 break;
1262 }
1263
1264 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1265 /* do an exponential smoothing */
1266 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1267
1268 /* save the algorithm value here, not the smoothed one */
1269 q_vector->eitr = new_itr;
fe49f04a
AD		 1270
1271 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1272 }
1273
1274 return;
1275}
1276
0befdb3e
JB		 1277static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1278{
1279 struct ixgbe_hw *hw = &adapter->hw;
1280
1281 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1282 (eicr & IXGBE_EICR_GPI_SDP1)) {
1283 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1284 /* write to clear the interrupt */
1285 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1286 }
1287}
cf8280ee 1288
e8e26350
PW		 1289static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1290{
1291 struct ixgbe_hw *hw = &adapter->hw;
1292
1293 if (eicr & IXGBE_EICR_GPI_SDP1) {
1294 /* Clear the interrupt */
1295 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1296 schedule_work(&adapter->multispeed_fiber_task);
1297 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1298 /* Clear the interrupt */
1299 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1300 schedule_work(&adapter->sfp_config_module_task);
1301 } else {
1302 /* Interrupt isn't for us... */
1303 return;
1304 }
1305}
1306
cf8280ee
JB		 1307static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1308{
1309 struct ixgbe_hw *hw = &adapter->hw;
1310
1311 adapter->lsc_int++;
1312 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1313 adapter->link_check_timeout = jiffies;
1314 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1315 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1316 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1317 schedule_work(&adapter->watchdog_task);
1318 }
1319}
1320
9a799d71
AK		 1321static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1322{
1323 struct net_device *netdev = data;
1324 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1325 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1326 u32 eicr;
1327
1328 /*
1329 * Workaround for Silicon errata. Use clear-by-write instead
1330 * of clear-by-read. Reading with EICS will return the
1331 * interrupt causes without clearing, which later be done
1332 * with the write to EICR.
1333 */
1334 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1335 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1336
cf8280ee
JB		 1337 if (eicr & IXGBE_EICR_LSC)
1338 ixgbe_check_lsc(adapter);
d4f80882 1339
1cdd1ec8
GR		 1340 if (eicr & IXGBE_EICR_MAILBOX)
1341 ixgbe_msg_task(adapter);
1342
e8e26350
PW		 1343 if (hw->mac.type == ixgbe_mac_82598EB)
1344 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1345
c4cf55e5 1346 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1347 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1348
1349 /* Handle Flow Director Full threshold interrupt */
1350 if (eicr & IXGBE_EICR_FLOW_DIR) {
1351 int i;
1352 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1353 /* Disable transmits before FDIR Re-initialization */
1354 netif_tx_stop_all_queues(netdev);
1355 for (i = 0; i < adapter->num_tx_queues; i++) {
1356 struct ixgbe_ring *tx_ring =
4a0b9ca0 1357 adapter->tx_ring[i];
c4cf55e5
PWJ		 1358 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1359 &tx_ring->reinit_state))
1360 schedule_work(&adapter->fdir_reinit_task);
1361 }
1362 }
1363 }
d4f80882
AV		 1364 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1365 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1366
1367 return IRQ_HANDLED;
1368}
1369
fe49f04a
AD		 1370static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1371 u64 qmask)
1372{
1373 u32 mask;
1374
1375 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1376 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1377 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1378 } else {
1379 mask = (qmask & 0xFFFFFFFF);
1380 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1381 mask = (qmask >> 32);
1382 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1383 }
1384 /* skip the flush */
1385}
1386
1387static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1388 u64 qmask)
1389{
1390 u32 mask;
1391
1392 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1393 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1395 } else {
1396 mask = (qmask & 0xFFFFFFFF);
1397 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1398 mask = (qmask >> 32);
1399 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1400 }
1401 /* skip the flush */
1402}
1403
9a799d71
AK		 1404static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1405{
021230d4
AV		 1406 struct ixgbe_q_vector *q_vector = data;
1407 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1408 struct ixgbe_ring *tx_ring;
021230d4
AV		 1409 int i, r_idx;
1410
1411 if (!q_vector->txr_count)
1412 return IRQ_HANDLED;
1413
1414 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1415 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1416 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1417 tx_ring->total_bytes = 0;
1418 tx_ring->total_packets = 0;
021230d4 1419 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1420 r_idx + 1);
021230d4 1421 }
9a799d71 1422
9b471446 1423 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1424 napi_schedule(&q_vector->napi);
1425
9a799d71
AK		 1426 return IRQ_HANDLED;
1427}
1428
021230d4
AV		 1429/**
1430 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1431 * @irq: unused
1432 * @data: pointer to our q_vector struct for this interrupt vector
1433 **/
9a799d71
AK		 1434static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1435{
021230d4
AV		 1436 struct ixgbe_q_vector *q_vector = data;
1437 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1438 struct ixgbe_ring *rx_ring;
021230d4 1439 int r_idx;
30efa5a3 1440 int i;
021230d4
AV		 1441
1442 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1443 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1444 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1445 rx_ring->total_bytes = 0;
1446 rx_ring->total_packets = 0;
1447 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1448 r_idx + 1);
1449 }
1450
021230d4
AV		 1451 if (!q_vector->rxr_count)
1452 return IRQ_HANDLED;
1453
021230d4 1454 /* disable interrupts on this vector only */
9b471446 1455 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1456 napi_schedule(&q_vector->napi);
021230d4
AV		 1457
1458 return IRQ_HANDLED;
1459}
1460
1461static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1462{
91281fd3
AD		 1463 struct ixgbe_q_vector *q_vector = data;
1464 struct ixgbe_adapter *adapter = q_vector->adapter;
1465 struct ixgbe_ring *ring;
1466 int r_idx;
1467 int i;
1468
1469 if (!q_vector->txr_count && !q_vector->rxr_count)
1470 return IRQ_HANDLED;
1471
1472 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1473 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1474 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1475 ring->total_bytes = 0;
1476 ring->total_packets = 0;
1477 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1478 r_idx + 1);
1479 }
1480
1481 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1482 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1483 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1484 ring->total_bytes = 0;
1485 ring->total_packets = 0;
1486 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1487 r_idx + 1);
1488 }
1489
9b471446 1490 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1491 napi_schedule(&q_vector->napi);
9a799d71 1492
9a799d71
AK		 1493 return IRQ_HANDLED;
1494}
1495
021230d4
AV		 1496/**
1497 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1498 * @napi: napi struct with our devices info in it
1499 * @budget: amount of work driver is allowed to do this pass, in packets
1500 *
f0848276
JB		 1501 * This function is optimized for cleaning one queue only on a single
1502 * q_vector!!!
021230d4 1503 **/
9a799d71
AK		 1504static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1505{
021230d4 1506 struct ixgbe_q_vector *q_vector =
b4617240 1507 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1508 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1509 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1510 int work_done = 0;
021230d4 1511 long r_idx;
9a799d71 1512
021230d4 1513 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1514 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1515#ifdef CONFIG_IXGBE_DCA
bd0362dd 1516 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1517 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1518#endif
9a799d71 1519
78b6f4ce 1520 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1521
021230d4
AV		 1522 /* If all Rx work done, exit the polling mode */
1523 if (work_done < budget) {
288379f0 1524 napi_complete(napi);
f7554a2b 1525 if (adapter->rx_itr_setting & 1)
f494e8fa 1526 ixgbe_set_itr_msix(q_vector);
9a799d71 1527 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1528 ixgbe_irq_enable_queues(adapter,
1529 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1530 }
1531
1532 return work_done;
1533}
1534
f0848276 1535/**
91281fd3 1536 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1537 * @napi: napi struct with our devices info in it
1538 * @budget: amount of work driver is allowed to do this pass, in packets
1539 *
1540 * This function will clean more than one rx queue associated with a
1541 * q_vector.
1542 **/
91281fd3 1543static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1544{
1545 struct ixgbe_q_vector *q_vector =
1546 container_of(napi, struct ixgbe_q_vector, napi);
1547 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1548 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1549 int work_done = 0, i;
1550 long r_idx;
91281fd3
AD		 1551 bool tx_clean_complete = true;
1552
1553 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1554 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1555 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1556#ifdef CONFIG_IXGBE_DCA
1557 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1558 ixgbe_update_tx_dca(adapter, ring);
1559#endif
1560 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1561 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1562 r_idx + 1);
1563 }
f0848276
JB		 1564
1565 /* attempt to distribute budget to each queue fairly, but don't allow
1566 * the budget to go below 1 because we'll exit polling */
1567 budget /= (q_vector->rxr_count ?: 1);
1568 budget = max(budget, 1);
1569 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1570 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1571 ring = adapter->rx_ring[r_idx];
5dd2d332 1572#ifdef CONFIG_IXGBE_DCA
f0848276 1573 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1574 ixgbe_update_rx_dca(adapter, ring);
f0848276 1575#endif
91281fd3 1576 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1577 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1578 r_idx + 1);
1579 }
1580
1581 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1582 ring = adapter->rx_ring[r_idx];
f0848276 1583 /* If all Rx work done, exit the polling mode */
7f821875 1584 if (work_done < budget) {
288379f0 1585 napi_complete(napi);
f7554a2b 1586 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1587 ixgbe_set_itr_msix(q_vector);
1588 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1589 ixgbe_irq_enable_queues(adapter,
1590 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1591 return 0;
1592 }
1593
1594 return work_done;
1595}
91281fd3
AD		 1596
1597/**
1598 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1599 * @napi: napi struct with our devices info in it
1600 * @budget: amount of work driver is allowed to do this pass, in packets
1601 *
1602 * This function is optimized for cleaning one queue only on a single
1603 * q_vector!!!
1604 **/
1605static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1606{
1607 struct ixgbe_q_vector *q_vector =
1608 container_of(napi, struct ixgbe_q_vector, napi);
1609 struct ixgbe_adapter *adapter = q_vector->adapter;
1610 struct ixgbe_ring *tx_ring = NULL;
1611 int work_done = 0;
1612 long r_idx;
1613
1614 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 1615 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1616#ifdef CONFIG_IXGBE_DCA
1617 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1618 ixgbe_update_tx_dca(adapter, tx_ring);
1619#endif
1620
1621 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1622 work_done = budget;
1623
f7554a2b 1624 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 1625 if (work_done < budget) {
1626 napi_complete(napi);
f7554a2b 1627 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 1628 ixgbe_set_itr_msix(q_vector);
1629 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1630 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1631 }
1632
1633 return work_done;
1634}
1635
021230d4 1636static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1637 int r_idx)
021230d4 1638{
7a921c93
AD		 1639 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1640
1641 set_bit(r_idx, q_vector->rxr_idx);
1642 q_vector->rxr_count++;
021230d4
AV		 1643}
1644
1645static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1646 int t_idx)
021230d4 1647{
7a921c93
AD		 1648 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1649
1650 set_bit(t_idx, q_vector->txr_idx);
1651 q_vector->txr_count++;
021230d4
AV		 1652}
1653
9a799d71 1654/**
021230d4
AV		 1655 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1656 * @adapter: board private structure to initialize
1657 * @vectors: allotted vector count for descriptor rings
9a799d71 1658 *
021230d4
AV		 1659 * This function maps descriptor rings to the queue-specific vectors
1660 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1661 * one vector per ring/queue, but on a constrained vector budget, we
1662 * group the rings as "efficiently" as possible. You would add new
1663 * mapping configurations in here.
9a799d71 1664 **/
021230d4 1665static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1666 int vectors)
021230d4
AV		 1667{
1668 int v_start = 0;
1669 int rxr_idx = 0, txr_idx = 0;
1670 int rxr_remaining = adapter->num_rx_queues;
1671 int txr_remaining = adapter->num_tx_queues;
1672 int i, j;
1673 int rqpv, tqpv;
1674 int err = 0;
1675
1676 /* No mapping required if MSI-X is disabled. */
1677 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1678 goto out;
9a799d71 1679
021230d4
AV		 1680 /*
1681 * The ideal configuration...
1682 * We have enough vectors to map one per queue.
1683 */
1684 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1685 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1686 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1687
021230d4
AV		 1688 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1689 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1690
9a799d71 1691 goto out;
021230d4 1692 }
9a799d71 1693
021230d4
AV		 1694 /*
1695 * If we don't have enough vectors for a 1-to-1
1696 * mapping, we'll have to group them so there are
1697 * multiple queues per vector.
1698 */
1699 /* Re-adjusting *qpv takes care of the remainder. */
1700 for (i = v_start; i < vectors; i++) {
1701 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1702 for (j = 0; j < rqpv; j++) {
1703 map_vector_to_rxq(adapter, i, rxr_idx);
1704 rxr_idx++;
1705 rxr_remaining--;
1706 }
1707 }
1708 for (i = v_start; i < vectors; i++) {
1709 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1710 for (j = 0; j < tqpv; j++) {
1711 map_vector_to_txq(adapter, i, txr_idx);
1712 txr_idx++;
1713 txr_remaining--;
9a799d71 1714 }
9a799d71
AK		 1715 }
1716
021230d4
AV		 1717out:
1718 return err;
1719}
1720
1721/**
1722 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1723 * @adapter: board private structure
1724 *
1725 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1726 * interrupts from the kernel.
1727 **/
1728static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1729{
1730 struct net_device *netdev = adapter->netdev;
1731 irqreturn_t (*handler)(int, void *);
1732 int i, vector, q_vectors, err;
cb13fc20 1733 int ri=0, ti=0;
021230d4
AV		 1734
1735 /* Decrement for Other and TCP Timer vectors */
1736 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1737
1738 /* Map the Tx/Rx rings to the vectors we were allotted. */
1739 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1740 if (err)
1741 goto out;
1742
1743#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1744 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1745 &ixgbe_msix_clean_many)
021230d4 1746 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1747 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1748
1749 if(handler == &ixgbe_msix_clean_rx) {
1750 sprintf(adapter->name[vector], "%s-%s-%d",
1751 netdev->name, "rx", ri++);
1752 }
1753 else if(handler == &ixgbe_msix_clean_tx) {
1754 sprintf(adapter->name[vector], "%s-%s-%d",
1755 netdev->name, "tx", ti++);
1756 }
1757 else
1758 sprintf(adapter->name[vector], "%s-%s-%d",
1759 netdev->name, "TxRx", vector);
1760
021230d4 1761 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1762 handler, 0, adapter->name[vector],
7a921c93 1763 adapter->q_vector[vector]);
9a799d71
AK		 1764 if (err) {
1765 DPRINTK(PROBE, ERR,
b4617240
PW		 1766 "request_irq failed for MSIX interrupt "
1767 "Error: %d\n", err);
021230d4 1768 goto free_queue_irqs;
9a799d71 1769 }
9a799d71
AK		 1770 }
1771
021230d4
AV		 1772 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1773 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1774 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1775 if (err) {
1776 DPRINTK(PROBE, ERR,
1777 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1778 goto free_queue_irqs;
9a799d71
AK		 1779 }
1780
9a799d71
AK		 1781 return 0;
1782
021230d4
AV		 1783free_queue_irqs:
1784 for (i = vector - 1; i >= 0; i--)
1785 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1786 adapter->q_vector[i]);
021230d4
AV		 1787 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1788 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1789 kfree(adapter->msix_entries);
1790 adapter->msix_entries = NULL;
021230d4 1791out:
9a799d71
AK		 1792 return err;
1793}
1794
f494e8fa
AV		 1795static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1796{
7a921c93 1797 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1798 u8 current_itr;
1799 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 1800 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
1801 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 1802
30efa5a3 1803 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1804 q_vector->tx_itr,
1805 tx_ring->total_packets,
1806 tx_ring->total_bytes);
30efa5a3 1807 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1808 q_vector->rx_itr,
1809 rx_ring->total_packets,
1810 rx_ring->total_bytes);
f494e8fa 1811
30efa5a3 1812 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1813
1814 switch (current_itr) {
1815 /* counts and packets in update_itr are dependent on these numbers */
1816 case lowest_latency:
1817 new_itr = 100000;
1818 break;
1819 case low_latency:
1820 new_itr = 20000; /* aka hwitr = ~200 */
1821 break;
1822 case bulk_latency:
1823 new_itr = 8000;
1824 break;
1825 default:
1826 break;
1827 }
1828
1829 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1830 /* do an exponential smoothing */
1831 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1832
1833 /* save the algorithm value here, not the smoothed one */
1834 q_vector->eitr = new_itr;
fe49f04a
AD		 1835
1836 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1837 }
1838
1839 return;
1840}
1841
79aefa45
AD		 1842/**
1843 * ixgbe_irq_enable - Enable default interrupt generation settings
1844 * @adapter: board private structure
1845 **/
1846static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1847{
1848 u32 mask;
835462fc
NS		 1849
1850 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1851 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1852 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1853 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1854 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1855 mask |= IXGBE_EIMS_GPI_SDP1;
1856 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 1857 if (adapter->num_vfs)
1858 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 1859 }
c4cf55e5
PWJ		 1860 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1861 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1862 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1863
79aefa45 1864 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1865 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45 1866 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 1867
1868 if (adapter->num_vfs > 32) {
1869 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1870 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1871 }
79aefa45 1872}
021230d4 1873
9a799d71 1874/**
021230d4 1875 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1876 * @irq: interrupt number
1877 * @data: pointer to a network interface device structure
9a799d71
AK		 1878 **/
1879static irqreturn_t ixgbe_intr(int irq, void *data)
1880{
1881 struct net_device *netdev = data;
1882 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1883 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1884 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1885 u32 eicr;
1886
54037505
DS		 1887 /*
1888 * Workaround for silicon errata. Mask the interrupts
1889 * before the read of EICR.
1890 */
1891 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1892
021230d4
AV		 1893 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1894 * therefore no explict interrupt disable is necessary */
1895 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1896 if (!eicr) {
1897 /* shared interrupt alert!
1898 * make sure interrupts are enabled because the read will
1899 * have disabled interrupts due to EIAM */
1900 ixgbe_irq_enable(adapter);
9a799d71 1901 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1902 }
9a799d71 1903
cf8280ee
JB		 1904 if (eicr & IXGBE_EICR_LSC)
1905 ixgbe_check_lsc(adapter);
021230d4 1906
e8e26350
PW		 1907 if (hw->mac.type == ixgbe_mac_82599EB)
1908 ixgbe_check_sfp_event(adapter, eicr);
1909
0befdb3e
JB		 1910 ixgbe_check_fan_failure(adapter, eicr);
1911
7a921c93 1912 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 1913 adapter->tx_ring[0]->total_packets = 0;
1914 adapter->tx_ring[0]->total_bytes = 0;
1915 adapter->rx_ring[0]->total_packets = 0;
1916 adapter->rx_ring[0]->total_bytes = 0;
021230d4 1917 /* would disable interrupts here but EIAM disabled it */
7a921c93 1918 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1919 }
1920
1921 return IRQ_HANDLED;
1922}
1923
021230d4
AV		 1924static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1925{
1926 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1927
1928 for (i = 0; i < q_vectors; i++) {
7a921c93 1929 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1930 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1931 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1932 q_vector->rxr_count = 0;
1933 q_vector->txr_count = 0;
1934 }
1935}
1936
9a799d71
AK		 1937/**
1938 * ixgbe_request_irq - initialize interrupts
1939 * @adapter: board private structure
1940 *
1941 * Attempts to configure interrupts using the best available
1942 * capabilities of the hardware and kernel.
1943 **/
021230d4 1944static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1945{
1946 struct net_device *netdev = adapter->netdev;
021230d4 1947 int err;
9a799d71 1948
021230d4
AV		 1949 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1950 err = ixgbe_request_msix_irqs(adapter);
1951 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 1952 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
b4617240 1953 netdev->name, netdev);
021230d4 1954 } else {
a0607fd3 1955 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
b4617240 1956 netdev->name, netdev);
9a799d71
AK		 1957 }
1958
9a799d71
AK		 1959 if (err)
1960 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1961
9a799d71
AK		 1962 return err;
1963}
1964
1965static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1966{
1967 struct net_device *netdev = adapter->netdev;
1968
1969 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1970 int i, q_vectors;
9a799d71 1971
021230d4
AV		 1972 q_vectors = adapter->num_msix_vectors;
1973
1974 i = q_vectors - 1;
9a799d71 1975 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1976
021230d4
AV		 1977 i--;
1978 for (; i >= 0; i--) {
1979 free_irq(adapter->msix_entries[i].vector,
7a921c93 1980 adapter->q_vector[i]);
021230d4
AV		 1981 }
1982
1983 ixgbe_reset_q_vectors(adapter);
1984 } else {
1985 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1986 }
1987}
1988
22d5a71b
JB		 1989/**
1990 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1991 * @adapter: board private structure
1992 **/
1993static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1994{
835462fc
NS		 1995 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1996 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1997 } else {
1998 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1999 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2000 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2001 if (adapter->num_vfs > 32)
2002 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 2003 }
2004 IXGBE_WRITE_FLUSH(&adapter->hw);
2005 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2006 int i;
2007 for (i = 0; i < adapter->num_msix_vectors; i++)
2008 synchronize_irq(adapter->msix_entries[i].vector);
2009 } else {
2010 synchronize_irq(adapter->pdev->irq);
2011 }
2012}
2013
9a799d71
AK		 2014/**
2015 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2016 *
2017 **/
2018static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2019{
9a799d71
AK		 2020 struct ixgbe_hw *hw = &adapter->hw;
2021
021230d4 2022 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 2023 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2024
e8e26350
PW		 2025 ixgbe_set_ivar(adapter, 0, 0, 0);
2026 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2027
2028 map_vector_to_rxq(adapter, 0, 0);
2029 map_vector_to_txq(adapter, 0, 0);
2030
2031 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2032}
2033
2034/**
3a581073 2035 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2036 * @adapter: board private structure
2037 *
2038 * Configure the Tx unit of the MAC after a reset.
2039 **/
2040static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2041{
12207e49 2042 u64 tdba;
9a799d71 2043 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2044 u32 i, j, tdlen, txctrl;
9a799d71
AK		 2045
2046 /* Setup the HW Tx Head and Tail descriptor pointers */
2047 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2048 struct ixgbe_ring *ring = adapter->tx_ring[i];
e01c31a5
JB		 2049 j = ring->reg_idx;
2050 tdba = ring->dma;
2051 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 2052 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 2053 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 2054 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2055 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2056 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2057 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
4a0b9ca0
PW		 2058 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2059 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
84f62d4b
PWJ		 2060 /*
2061 * Disable Tx Head Writeback RO bit, since this hoses
021230d4
AV		 2062 * bookkeeping if things aren't delivered in order.
2063 */
84f62d4b
PWJ		 2064 switch (hw->mac.type) {
2065 case ixgbe_mac_82598EB:
2066 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2067 break;
2068 case ixgbe_mac_82599EB:
2069 default:
2070 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2071 break;
2072 }
021230d4 2073 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
84f62d4b
PWJ		 2074 switch (hw->mac.type) {
2075 case ixgbe_mac_82598EB:
2076 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2077 break;
2078 case ixgbe_mac_82599EB:
2079 default:
2080 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2081 break;
2082 }
9a799d71 2083 }
ee5f784a 2084
e8e26350 2085 if (hw->mac.type == ixgbe_mac_82599EB) {
ee5f784a 2086 u32 rttdcs;
1cdd1ec8 2087 u32 mask;
ee5f784a
DS		 2088
2089 /* disable the arbiter while setting MTQC */
2090 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2091 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2092 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2093
1cdd1ec8
GR		 2094 /* set transmit pool layout */
2095 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2096 switch (adapter->flags & mask) {
2097
2098 case (IXGBE_FLAG_SRIOV_ENABLED):
2099 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2100 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2101 break;
2102
2103 case (IXGBE_FLAG_DCB_ENABLED):
2104 /* We enable 8 traffic classes, DCB only */
2105 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2106 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2107 break;
2108
2109 default:
ee5f784a 2110 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1cdd1ec8
GR		 2111 break;
2112 }
ee5f784a
DS		 2113
2114 /* re-eable the arbiter */
2115 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2116 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
e8e26350 2117 }
9a799d71
AK		 2118}
2119
e8e26350 2120#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2121
a6616b42
YZ		 2122static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2123 struct ixgbe_ring *rx_ring)
cc41ac7c 2124{
cc41ac7c 2125 u32 srrctl;
a6616b42 2126 int index;
0cefafad 2127 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2128
a6616b42
YZ		 2129 index = rx_ring->reg_idx;
2130 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2131 unsigned long mask;
0cefafad 2132 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2133 index = index & mask;
cc41ac7c 2134 }
cc41ac7c
JB		 2135 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2136
2137 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2138 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2139
afafd5b0
AD		 2140 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2141 IXGBE_SRRCTL_BSIZEHDR_MASK;
2142
6e455b89 2143 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2144#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2145 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2146#else
2147 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2148#endif
cc41ac7c 2149 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2150 } else {
afafd5b0
AD		 2151 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2152 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2153 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2154 }
e8e26350 2155
cc41ac7c
JB		 2156 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2157}
9a799d71 2158
0cefafad
JB		 2159static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2160{
2161 u32 mrqc = 0;
2162 int mask;
2163
2164 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2165 return mrqc;
2166
2167 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2168#ifdef CONFIG_IXGBE_DCB
2169 | IXGBE_FLAG_DCB_ENABLED
2170#endif
1cdd1ec8 2171 | IXGBE_FLAG_SRIOV_ENABLED
0cefafad
JB		 2172 );
2173
2174 switch (mask) {
2175 case (IXGBE_FLAG_RSS_ENABLED):
2176 mrqc = IXGBE_MRQC_RSSEN;
2177 break;
1cdd1ec8
GR		 2178 case (IXGBE_FLAG_SRIOV_ENABLED):
2179 mrqc = IXGBE_MRQC_VMDQEN;
2180 break;
0cefafad
JB		 2181#ifdef CONFIG_IXGBE_DCB
2182 case (IXGBE_FLAG_DCB_ENABLED):
2183 mrqc = IXGBE_MRQC_RT8TCEN;
2184 break;
2185#endif /* CONFIG_IXGBE_DCB */
2186 default:
2187 break;
2188 }
2189
2190 return mrqc;
2191}
2192
bb5a9ad2
NS		 2193/**
2194 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2195 * @adapter: address of board private structure
2196 * @index: index of ring to set
bb5a9ad2 2197 **/
edd2ea55 2198static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
bb5a9ad2
NS		 2199{
2200 struct ixgbe_ring *rx_ring;
2201 struct ixgbe_hw *hw = &adapter->hw;
2202 int j;
2203 u32 rscctrl;
edd2ea55 2204 int rx_buf_len;
bb5a9ad2 2205
4a0b9ca0 2206 rx_ring = adapter->rx_ring[index];
bb5a9ad2 2207 j = rx_ring->reg_idx;
edd2ea55 2208 rx_buf_len = rx_ring->rx_buf_len;
bb5a9ad2
NS		 2209 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2210 rscctrl |= IXGBE_RSCCTL_RSCEN;
2211 /*
2212 * we must limit the number of descriptors so that the
2213 * total size of max desc * buf_len is not greater
2214 * than 65535
2215 */
2216 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2217#if (MAX_SKB_FRAGS > 16)
2218 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2219#elif (MAX_SKB_FRAGS > 8)
2220 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2221#elif (MAX_SKB_FRAGS > 4)
2222 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2223#else
2224 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2225#endif
2226 } else {
2227 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2228 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2229 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2230 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2231 else
2232 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2233 }
2234 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2235}
2236
9a799d71 2237/**
3a581073 2238 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 2239 * @adapter: board private structure
2240 *
2241 * Configure the Rx unit of the MAC after a reset.
2242 **/
2243static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2244{
2245 u64 rdba;
2246 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 2247 struct ixgbe_ring *rx_ring;
9a799d71
AK		 2248 struct net_device *netdev = adapter->netdev;
2249 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2250 int i, j;
9a799d71 2251 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 2252 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2253 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2254 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 2255 u32 fctrl, hlreg0;
509ee935 2256 u32 reta = 0, mrqc = 0;
cc41ac7c 2257 u32 rdrxctl;
7c6e0a43 2258 int rx_buf_len;
9a799d71
AK		 2259
2260 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2261 /* Do not use packet split if we're in SR-IOV Mode */
2262 if (!adapter->num_vfs)
2263 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2264
2265 /* Set the RX buffer length according to the mode */
2266 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2267 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2268 if (hw->mac.type == ixgbe_mac_82599EB) {
2269 /* PSRTYPE must be initialized in 82599 */
2270 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2271 IXGBE_PSRTYPE_UDPHDR |
2272 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2273 IXGBE_PSRTYPE_IPV6HDR |
2274 IXGBE_PSRTYPE_L2HDR;
1cdd1ec8
GR		 2275 IXGBE_WRITE_REG(hw,
2276 IXGBE_PSRTYPE(adapter->num_vfs),
2277 psrtype);
e8e26350 2278 }
9a799d71 2279 } else {
0c19d6af 2280 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2281 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2282 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2283 else
7c6e0a43 2284 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2285 }
2286
2287 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2288 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2289 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2290 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2291 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2292
2293 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2294 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2295 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2296 else
2297 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2298#ifdef IXGBE_FCOE
f34c5c82 2299 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2300 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2301#endif
9a799d71
AK		 2302 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2303
4a0b9ca0 2304 rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
9a799d71
AK		 2305 /* disable receives while setting up the descriptors */
2306 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2307 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2308
0cefafad
JB		 2309 /*
2310 * Setup the HW Rx Head and Tail Descriptor Pointers and
2311 * the Base and Length of the Rx Descriptor Ring
2312 */
9a799d71 2313 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2314 rx_ring = adapter->rx_ring[i];
a6616b42
YZ		 2315 rdba = rx_ring->dma;
2316 j = rx_ring->reg_idx;
284901a9 2317 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2318 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2319 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2320 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2321 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2322 rx_ring->head = IXGBE_RDH(j);
2323 rx_ring->tail = IXGBE_RDT(j);
2324 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2325
6e455b89
YZ		 2326 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2327 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2328 else
2329 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2330
63f39bd1 2331#ifdef IXGBE_FCOE
f34c5c82 2332 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2333 struct ixgbe_ring_feature *f;
2334 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2335 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2336 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2337 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2338 rx_ring->rx_buf_len =
2339 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2340 }
63f39bd1
YZ		 2341 }
2342
2343#endif /* IXGBE_FCOE */
a6616b42 2344 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2345 }
2346
e8e26350
PW		 2347 if (hw->mac.type == ixgbe_mac_82598EB) {
2348 /*
2349 * For VMDq support of different descriptor types or
2350 * buffer sizes through the use of multiple SRRCTL
2351 * registers, RDRXCTL.MVMEN must be set to 1
2352 *
2353 * also, the manual doesn't mention it clearly but DCA hints
2354 * will only use queue 0's tags unless this bit is set. Side
2355 * effects of setting this bit are only that SRRCTL must be
2356 * fully programmed [0..15]
2357 */
2a41ff81
JB		 2358 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2359 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2360 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2361 }
177db6ff 2362
1cdd1ec8
GR		 2363 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2364 u32 vt_reg_bits;
2365 u32 reg_offset, vf_shift;
2366 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2367 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2368 | IXGBE_VT_CTL_REPLEN;
2369 vt_reg_bits |= (adapter->num_vfs <<
2370 IXGBE_VT_CTL_POOL_SHIFT);
2371 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2372 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2373
2374 vf_shift = adapter->num_vfs % 32;
2375 reg_offset = adapter->num_vfs / 32;
2376 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2377 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2378 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2379 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2380 /* Enable only the PF's pool for Tx/Rx */
2381 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2382 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2383 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2384 ixgbe_set_vmolr(hw, adapter->num_vfs);
2385 }
2386
e8e26350 2387 /* Program MRQC for the distribution of queues */
0cefafad 2388 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2389
021230d4 2390 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2391 /* Fill out redirection table */
021230d4
AV		 2392 for (i = 0, j = 0; i < 128; i++, j++) {
2393 if (j == adapter->ring_feature[RING_F_RSS].indices)
2394 j = 0;
2395 /* reta = 4-byte sliding window of
2396 * 0x00..(indices-1)(indices-1)00..etc. */
2397 reta = (reta << 8) | (j * 0x11);
2398 if ((i & 3) == 3)
2399 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2400 }
2401
2402 /* Fill out hash function seeds */
2403 for (i = 0; i < 10; i++)
7c6e0a43 2404 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2405
2a41ff81
JB		 2406 if (hw->mac.type == ixgbe_mac_82598EB)
2407 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2408 /* Perform hash on these packet types */
2a41ff81
JB		 2409 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2410 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2411 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2412 | IXGBE_MRQC_RSS_FIELD_IPV6
2413 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2414 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2415 }
2a41ff81 2416 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2417
1cdd1ec8
GR		 2418 if (adapter->num_vfs) {
2419 u32 reg;
2420
2421 /* Map PF MAC address in RAR Entry 0 to first pool
2422 * following VFs */
2423 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2424
2425 /* Set up VF register offsets for selected VT Mode, i.e.
2426 * 64 VFs for SR-IOV */
2427 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2428 reg |= IXGBE_GCR_EXT_SRIOV;
2429 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2430 }
2431
021230d4
AV		 2432 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2433
2434 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2435 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2436 /* Disable indicating checksum in descriptor, enables
2437 * RSS hash */
9a799d71 2438 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2439 }
021230d4
AV		 2440 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2441 /* Enable IPv4 payload checksum for UDP fragments
2442 * if PCSD is not set */
2443 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2444 }
2445
2446 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2447
2448 if (hw->mac.type == ixgbe_mac_82599EB) {
2449 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2450 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2451 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2452 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2453 }
f8212f97 2454
0c19d6af 2455 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2456 /* Enable 82599 HW-RSC */
bb5a9ad2 2457 for (i = 0; i < adapter->num_rx_queues; i++)
edd2ea55 2458 ixgbe_configure_rscctl(adapter, i);
bb5a9ad2 2459
f8212f97
AD		 2460 /* Disable RSC for ACK packets */
2461 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2462 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2463 }
9a799d71
AK		 2464}
2465
068c89b0
DS		 2466static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2467{
2468 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2469 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2470 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2471
2472 /* add VID to filter table */
1ada1b1b 2473 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
068c89b0
DS		 2474}
2475
2476static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2477{
2478 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2479 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2480 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2481
2482 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2483 ixgbe_irq_disable(adapter);
2484
2485 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2486
2487 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2488 ixgbe_irq_enable(adapter);
2489
2490 /* remove VID from filter table */
1ada1b1b 2491 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
068c89b0
DS		 2492}
2493
5f6c0181
JB		 2494/**
2495 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2496 * @adapter: driver data
2497 */
2498static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2499{
2500 struct ixgbe_hw *hw = &adapter->hw;
2501 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2502 int i, j;
2503
2504 switch (hw->mac.type) {
2505 case ixgbe_mac_82598EB:
2506 vlnctrl &= ~(IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE);
2507 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2508 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2509 break;
2510 case ixgbe_mac_82599EB:
2511 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2512 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2513 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2514 for (i = 0; i < adapter->num_rx_queues; i++) {
2515 j = adapter->rx_ring[i]->reg_idx;
2516 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2517 vlnctrl &= ~IXGBE_RXDCTL_VME;
2518 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2519 }
2520 break;
2521 default:
2522 break;
2523 }
2524}
2525
2526/**
2527 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2528 * @adapter: driver data
2529 */
2530static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2531{
2532 struct ixgbe_hw *hw = &adapter->hw;
2533 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2534 int i, j;
2535
2536 switch (hw->mac.type) {
2537 case ixgbe_mac_82598EB:
2538 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2539 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2540 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2541 break;
2542 case ixgbe_mac_82599EB:
2543 vlnctrl |= IXGBE_VLNCTRL_VFE;
2544 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2545 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2546 for (i = 0; i < adapter->num_rx_queues; i++) {
2547 j = adapter->rx_ring[i]->reg_idx;
2548 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2549 vlnctrl |= IXGBE_RXDCTL_VME;
2550 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2551 }
2552 break;
2553 default:
2554 break;
2555 }
2556}
2557
9a799d71 2558static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2559 struct vlan_group *grp)
9a799d71
AK		 2560{
2561 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 2562
d4f80882
AV		 2563 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2564 ixgbe_irq_disable(adapter);
9a799d71
AK		 2565 adapter->vlgrp = grp;
2566
2f90b865
AD		 2567 /*
2568 * For a DCB driver, always enable VLAN tag stripping so we can
2569 * still receive traffic from a DCB-enabled host even if we're
2570 * not in DCB mode.
2571 */
5f6c0181 2572 ixgbe_vlan_filter_enable(adapter);
dc63d377 2573
e8e26350 2574 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2575
d4f80882
AV		 2576 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2577 ixgbe_irq_enable(adapter);
9a799d71
AK		 2578}
2579
9a799d71
AK		 2580static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2581{
2582 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2583
2584 if (adapter->vlgrp) {
2585 u16 vid;
2586 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2587 if (!vlan_group_get_device(adapter->vlgrp, vid))
2588 continue;
2589 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2590 }
2591 }
2592}
2593
2594/**
2c5645cf 2595 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2596 * @netdev: network interface device structure
2597 *
2c5645cf
CL		 2598 * The set_rx_method entry point is called whenever the unicast/multicast
2599 * address list or the network interface flags are updated. This routine is
2600 * responsible for configuring the hardware for proper unicast, multicast and
2601 * promiscuous mode.
9a799d71 2602 **/
7f870475 2603void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2604{
2605 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2606 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 2607 u32 fctrl;
9a799d71
AK		 2608
2609 /* Check for Promiscuous and All Multicast modes */
2610
2611 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2612
2613 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2614 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2615 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
5f6c0181
JB		 2616 /* don't hardware filter vlans in promisc mode */
2617 ixgbe_vlan_filter_disable(adapter);
9a799d71 2618 } else {
746b9f02
PM		 2619 if (netdev->flags & IFF_ALLMULTI) {
2620 fctrl |= IXGBE_FCTRL_MPE;
2621 fctrl &= ~IXGBE_FCTRL_UPE;
2622 } else {
2623 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2624 }
5f6c0181 2625 ixgbe_vlan_filter_enable(adapter);
2c5645cf 2626 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2627 }
2628
2629 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2630
2c5645cf 2631 /* reprogram secondary unicast list */
32e7bfc4 2632 hw->mac.ops.update_uc_addr_list(hw, netdev);
9a799d71 2633
2c5645cf 2634 /* reprogram multicast list */
2853eb89
JP		 2635 hw->mac.ops.update_mc_addr_list(hw, netdev);
2636
1cdd1ec8
GR		 2637 if (adapter->num_vfs)
2638 ixgbe_restore_vf_multicasts(adapter);
9a799d71
AK		 2639}
2640
021230d4
AV		 2641static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2642{
2643 int q_idx;
2644 struct ixgbe_q_vector *q_vector;
2645 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2646
2647 /* legacy and MSI only use one vector */
2648 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2649 q_vectors = 1;
2650
2651 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2652 struct napi_struct *napi;
7a921c93 2653 q_vector = adapter->q_vector[q_idx];
f0848276 2654 napi = &q_vector->napi;
91281fd3
AD		 2655 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2656 if (!q_vector->rxr_count || !q_vector->txr_count) {
2657 if (q_vector->txr_count == 1)
2658 napi->poll = &ixgbe_clean_txonly;
2659 else if (q_vector->rxr_count == 1)
2660 napi->poll = &ixgbe_clean_rxonly;
2661 }
2662 }
f0848276
JB		 2663
2664 napi_enable(napi);
021230d4
AV		 2665 }
2666}
2667
2668static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2669{
2670 int q_idx;
2671 struct ixgbe_q_vector *q_vector;
2672 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2673
2674 /* legacy and MSI only use one vector */
2675 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2676 q_vectors = 1;
2677
2678 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2679 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2680 napi_disable(&q_vector->napi);
2681 }
2682}
2683
7a6b6f51 2684#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2685/*
2686 * ixgbe_configure_dcb - Configure DCB hardware
2687 * @adapter: ixgbe adapter struct
2688 *
2689 * This is called by the driver on open to configure the DCB hardware.
2690 * This is also called by the gennetlink interface when reconfiguring
2691 * the DCB state.
2692 */
2693static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2694{
2695 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 2696 u32 txdctl;
2f90b865
AD		 2697 int i, j;
2698
2699 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2700 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2701 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2702
2703 /* reconfigure the hardware */
2704 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2705
2706 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2707 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 2708 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2709 /* PThresh workaround for Tx hang with DFP enabled. */
2710 txdctl |= 32;
2711 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2712 }
2713 /* Enable VLAN tag insert/strip */
5f6c0181
JB		 2714 ixgbe_vlan_filter_enable(adapter);
2715
2f90b865
AD		 2716 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2717}
2718
2719#endif
9a799d71
AK		 2720static void ixgbe_configure(struct ixgbe_adapter *adapter)
2721{
2722 struct net_device *netdev = adapter->netdev;
c4cf55e5 2723 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2724 int i;
2725
2c5645cf 2726 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2727
2728 ixgbe_restore_vlan(adapter);
7a6b6f51 2729#ifdef CONFIG_IXGBE_DCB
2f90b865 2730 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
b352e40d
YZ		 2731 if (hw->mac.type == ixgbe_mac_82598EB)
2732 netif_set_gso_max_size(netdev, 32768);
2733 else
2734 netif_set_gso_max_size(netdev, 65536);
2f90b865
AD		 2735 ixgbe_configure_dcb(adapter);
2736 } else {
2737 netif_set_gso_max_size(netdev, 65536);
2738 }
2739#else
2740 netif_set_gso_max_size(netdev, 65536);
2741#endif
9a799d71 2742
eacd73f7
YZ		 2743#ifdef IXGBE_FCOE
2744 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2745 ixgbe_configure_fcoe(adapter);
2746
2747#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2748 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2749 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 2750 adapter->tx_ring[i]->atr_sample_rate =
c4cf55e5
PWJ		 2751 adapter->atr_sample_rate;
2752 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2753 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2754 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2755 }
2756
9a799d71
AK		 2757 ixgbe_configure_tx(adapter);
2758 ixgbe_configure_rx(adapter);
2759 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 2760 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
2761 (adapter->rx_ring[i]->count - 1));
9a799d71
AK		 2762}
2763
e8e26350
PW		 2764static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2765{
2766 switch (hw->phy.type) {
2767 case ixgbe_phy_sfp_avago:
2768 case ixgbe_phy_sfp_ftl:
2769 case ixgbe_phy_sfp_intel:
2770 case ixgbe_phy_sfp_unknown:
2771 case ixgbe_phy_tw_tyco:
2772 case ixgbe_phy_tw_unknown:
2773 return true;
2774 default:
2775 return false;
2776 }
2777}
2778
0ecc061d 2779/**
e8e26350
PW		 2780 * ixgbe_sfp_link_config - set up SFP+ link
2781 * @adapter: pointer to private adapter struct
2782 **/
2783static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2784{
2785 struct ixgbe_hw *hw = &adapter->hw;
2786
2787 if (hw->phy.multispeed_fiber) {
2788 /*
2789 * In multispeed fiber setups, the device may not have
2790 * had a physical connection when the driver loaded.
2791 * If that's the case, the initial link configuration
2792 * couldn't get the MAC into 10G or 1G mode, so we'll
2793 * never have a link status change interrupt fire.
2794 * We need to try and force an autonegotiation
2795 * session, then bring up link.
2796 */
2797 hw->mac.ops.setup_sfp(hw);
2798 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2799 schedule_work(&adapter->multispeed_fiber_task);
2800 } else {
2801 /*
2802 * Direct Attach Cu and non-multispeed fiber modules
2803 * still need to be configured properly prior to
2804 * attempting link.
2805 */
2806 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2807 schedule_work(&adapter->sfp_config_module_task);
2808 }
2809}
2810
2811/**
2812 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2813 * @hw: pointer to private hardware struct
2814 *
2815 * Returns 0 on success, negative on failure
2816 **/
e8e26350 2817static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2818{
2819 u32 autoneg;
8620a103 2820 bool negotiation, link_up = false;
0ecc061d
PWJ		 2821 u32 ret = IXGBE_ERR_LINK_SETUP;
2822
2823 if (hw->mac.ops.check_link)
2824 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2825
2826 if (ret)
2827 goto link_cfg_out;
2828
2829 if (hw->mac.ops.get_link_capabilities)
8620a103 2830 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 2831 if (ret)
2832 goto link_cfg_out;
2833
8620a103
MC		 2834 if (hw->mac.ops.setup_link)
2835 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 2836link_cfg_out:
2837 return ret;
2838}
2839
e8e26350
PW		 2840#define IXGBE_MAX_RX_DESC_POLL 10
2841static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2842 int rxr)
2843{
4a0b9ca0 2844 int j = adapter->rx_ring[rxr]->reg_idx;
e8e26350
PW		 2845 int k;
2846
2847 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2848 if (IXGBE_READ_REG(&adapter->hw,
2849 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2850 break;
2851 else
2852 msleep(1);
2853 }
2854 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2855 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2856 "not set within the polling period\n", rxr);
2857 }
4a0b9ca0
PW		 2858 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
2859 (adapter->rx_ring[rxr]->count - 1));
e8e26350
PW		 2860}
2861
9a799d71
AK		 2862static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2863{
2864 struct net_device *netdev = adapter->netdev;
9a799d71 2865 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2866 int i, j = 0;
e8e26350 2867 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2868 int err;
9a799d71 2869 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2870 u32 txdctl, rxdctl, mhadd;
e8e26350 2871 u32 dmatxctl;
021230d4 2872 u32 gpie;
c9205697 2873 u32 ctrl_ext;
9a799d71 2874
5eba3699
AV		 2875 ixgbe_get_hw_control(adapter);
2876
021230d4
AV		 2877 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2878 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2879 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2880 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2881 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2882 } else {
2883 /* MSI only */
021230d4 2884 gpie = 0;
9a799d71 2885 }
1cdd1ec8
GR		 2886 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2887 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
2888 gpie |= IXGBE_GPIE_VTMODE_64;
2889 }
021230d4
AV		 2890 /* XXX: to interrupt immediately for EICS writes, enable this */
2891 /* gpie |= IXGBE_GPIE_EIMEN; */
2892 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2893 }
2894
9b471446
JB		 2895 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2896 /*
2897 * use EIAM to auto-mask when MSI-X interrupt is asserted
2898 * this saves a register write for every interrupt
2899 */
2900 switch (hw->mac.type) {
2901 case ixgbe_mac_82598EB:
2902 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2903 break;
2904 default:
2905 case ixgbe_mac_82599EB:
2906 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2907 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2908 break;
2909 }
2910 } else {
021230d4
AV		 2911 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2912 * specifically only auto mask tx and rx interrupts */
2913 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2914 }
9a799d71 2915
0befdb3e
JB		 2916 /* Enable fan failure interrupt if media type is copper */
2917 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2918 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2919 gpie |= IXGBE_SDP1_GPIEN;
2920 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2921 }
2922
e8e26350
PW		 2923 if (hw->mac.type == ixgbe_mac_82599EB) {
2924 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2925 gpie |= IXGBE_SDP1_GPIEN;
2926 gpie |= IXGBE_SDP2_GPIEN;
2927 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2928 }
2929
63f39bd1
YZ		 2930#ifdef IXGBE_FCOE
2931 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 2932 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 2933 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2934 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2935
2936#endif /* IXGBE_FCOE */
021230d4 2937 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2938 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2939 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2940 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2941
2942 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2943 }
2944
2945 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2946 j = adapter->tx_ring[i]->reg_idx;
021230d4 2947 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2948 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2949 txdctl |= (8 << 16);
e8e26350
PW		 2950 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2951 }
2952
2953 if (hw->mac.type == ixgbe_mac_82599EB) {
2954 /* DMATXCTL.EN must be set after all Tx queue config is done */
2955 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2956 dmatxctl |= IXGBE_DMATXCTL_TE;
2957 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2958 }
2959 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2960 j = adapter->tx_ring[i]->reg_idx;
e8e26350 2961 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2962 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2963 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1cdd1ec8
GR		 2964 if (hw->mac.type == ixgbe_mac_82599EB) {
2965 int wait_loop = 10;
2966 /* poll for Tx Enable ready */
2967 do {
2968 msleep(1);
2969 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2970 } while (--wait_loop &&
2971 !(txdctl & IXGBE_TXDCTL_ENABLE));
2972 if (!wait_loop)
2973 DPRINTK(DRV, ERR, "Could not enable "
2974 "Tx Queue %d\n", j);
2975 }
9a799d71
AK		 2976 }
2977
e8e26350 2978 for (i = 0; i < num_rx_rings; i++) {
4a0b9ca0 2979 j = adapter->rx_ring[i]->reg_idx;
021230d4
AV		 2980 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2981 /* enable PTHRESH=32 descriptors (half the internal cache)
2982 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2983 * this also removes a pesky rx_no_buffer_count increment */
2984 rxdctl |= 0x0020;
9a799d71 2985 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2986 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2987 if (hw->mac.type == ixgbe_mac_82599EB)
2988 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2989 }
2990 /* enable all receives */
2991 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2992 if (hw->mac.type == ixgbe_mac_82598EB)
2993 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2994 else
2995 rxdctl |= IXGBE_RXCTRL_RXEN;
2996 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2997
2998 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2999 ixgbe_configure_msix(adapter);
3000 else
3001 ixgbe_configure_msi_and_legacy(adapter);
3002
61fac744
PW		 3003 /* enable the optics */
3004 if (hw->phy.multispeed_fiber)
3005 hw->mac.ops.enable_tx_laser(hw);
3006
9a799d71 3007 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3008 ixgbe_napi_enable_all(adapter);
3009
3010 /* clear any pending interrupts, may auto mask */
3011 IXGBE_READ_REG(hw, IXGBE_EICR);
3012
9a799d71
AK		 3013 ixgbe_irq_enable(adapter);
3014
bf069c97
DS		 3015 /*
3016 * If this adapter has a fan, check to see if we had a failure
3017 * before we enabled the interrupt.
3018 */
3019 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3020 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3021 if (esdp & IXGBE_ESDP_SDP1)
3022 DPRINTK(DRV, CRIT,
3023 "Fan has stopped, replace the adapter\n");
3024 }
3025
e8e26350
PW		 3026 /*
3027 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3028 * arrived before interrupts were enabled but after probe. Such
3029 * devices wouldn't have their type identified yet. We need to
3030 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3031 * If we're not hot-pluggable SFP+, we just need to configure link
3032 * and bring it up.
3033 */
19343de2
DS		 3034 if (hw->phy.type == ixgbe_phy_unknown) {
3035 err = hw->phy.ops.identify(hw);
3036 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3037 /*
3038 * Take the device down and schedule the sfp tasklet
3039 * which will unregister_netdev and log it.
3040 */
19343de2 3041 ixgbe_down(adapter);
5da43c1a 3042 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3043 return err;
3044 }
e8e26350
PW		 3045 }
3046
3047 if (ixgbe_is_sfp(hw)) {
3048 ixgbe_sfp_link_config(adapter);
3049 } else {
3050 err = ixgbe_non_sfp_link_config(hw);
3051 if (err)
3052 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3053 }
0ecc061d 3054
c4cf55e5
PWJ		 3055 for (i = 0; i < adapter->num_tx_queues; i++)
3056 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 3057 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 3058
1da100bb
PWJ		 3059 /* enable transmits */
3060 netif_tx_start_all_queues(netdev);
3061
9a799d71
AK		 3062 /* bring the link up in the watchdog, this could race with our first
3063 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3064 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3065 adapter->link_check_timeout = jiffies;
9a799d71 3066 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3067
3068 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3069 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3070 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3071 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3072
9a799d71
AK		 3073 return 0;
3074}
3075
d4f80882
AV		 3076void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3077{
3078 WARN_ON(in_interrupt());
3079 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3080 msleep(1);
3081 ixgbe_down(adapter);
5809a1ae
GR		 3082 /*
3083 * If SR-IOV enabled then wait a bit before bringing the adapter
3084 * back up to give the VFs time to respond to the reset. The
3085 * two second wait is based upon the watchdog timer cycle in
3086 * the VF driver.
3087 */
3088 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3089 msleep(2000);
d4f80882
AV		 3090 ixgbe_up(adapter);
3091 clear_bit(__IXGBE_RESETTING, &adapter->state);
3092}
3093
9a799d71
AK		 3094int ixgbe_up(struct ixgbe_adapter *adapter)
3095{
3096 /* hardware has been reset, we need to reload some things */
3097 ixgbe_configure(adapter);
3098
3099 return ixgbe_up_complete(adapter);
3100}
3101
3102void ixgbe_reset(struct ixgbe_adapter *adapter)
3103{
c44ade9e 3104 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3105 int err;
3106
3107 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3108 switch (err) {
3109 case 0:
3110 case IXGBE_ERR_SFP_NOT_PRESENT:
3111 break;
3112 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3113 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3114 break;
794caeb2
PWJ		 3115 case IXGBE_ERR_EEPROM_VERSION:
3116 /* We are running on a pre-production device, log a warning */
3117 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3118 "adapter/LOM. Please be aware there may be issues "
3119 "associated with your hardware. If you are "
3120 "experiencing problems please contact your Intel or "
3121 "hardware representative who provided you with this "
3122 "hardware.\n");
3123 break;
da4dd0f7
PWJ		 3124 default:
3125 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3126 }
9a799d71
AK		 3127
3128 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3129 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3130 IXGBE_RAH_AV);
9a799d71
AK		 3131}
3132
9a799d71
AK		 3133/**
3134 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3135 * @adapter: board private structure
3136 * @rx_ring: ring to free buffers from
3137 **/
3138static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 3139 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3140{
3141 struct pci_dev *pdev = adapter->pdev;
3142 unsigned long size;
3143 unsigned int i;
3144
3145 /* Free all the Rx ring sk_buffs */
3146
3147 for (i = 0; i < rx_ring->count; i++) {
3148 struct ixgbe_rx_buffer *rx_buffer_info;
3149
3150 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3151 if (rx_buffer_info->dma) {
3152 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 3153 rx_ring->rx_buf_len,
3154 PCI_DMA_FROMDEVICE);
9a799d71
AK		 3155 rx_buffer_info->dma = 0;
3156 }
3157 if (rx_buffer_info->skb) {
f8212f97 3158 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3159 rx_buffer_info->skb = NULL;
f8212f97
AD		 3160 do {
3161 struct sk_buff *this = skb;
fd3686a8 3162 if (IXGBE_RSC_CB(this)->dma) {
43634e82
MC		 3163 pci_unmap_single(pdev, IXGBE_RSC_CB(this)->dma,
3164 rx_ring->rx_buf_len,
3165 PCI_DMA_FROMDEVICE);
fd3686a8
MC		 3166 IXGBE_RSC_CB(this)->dma = 0;
3167 }
f8212f97
AD		 3168 skb = skb->prev;
3169 dev_kfree_skb(this);
3170 } while (skb);
9a799d71
AK		 3171 }
3172 if (!rx_buffer_info->page)
3173 continue;
4f57ca6e
JB		 3174 if (rx_buffer_info->page_dma) {
3175 pci_unmap_page(pdev, rx_buffer_info->page_dma,
3176 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3177 rx_buffer_info->page_dma = 0;
3178 }
9a799d71
AK		 3179 put_page(rx_buffer_info->page);
3180 rx_buffer_info->page = NULL;
762f4c57 3181 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3182 }
3183
3184 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3185 memset(rx_ring->rx_buffer_info, 0, size);
3186
3187 /* Zero out the descriptor ring */
3188 memset(rx_ring->desc, 0, rx_ring->size);
3189
3190 rx_ring->next_to_clean = 0;
3191 rx_ring->next_to_use = 0;
3192
9891ca7c
JB		 3193 if (rx_ring->head)
3194 writel(0, adapter->hw.hw_addr + rx_ring->head);
3195 if (rx_ring->tail)
3196 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3197}
3198
3199/**
3200 * ixgbe_clean_tx_ring - Free Tx Buffers
3201 * @adapter: board private structure
3202 * @tx_ring: ring to be cleaned
3203 **/
3204static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 3205 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3206{
3207 struct ixgbe_tx_buffer *tx_buffer_info;
3208 unsigned long size;
3209 unsigned int i;
3210
3211 /* Free all the Tx ring sk_buffs */
3212
3213 for (i = 0; i < tx_ring->count; i++) {
3214 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3215 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3216 }
3217
3218 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3219 memset(tx_ring->tx_buffer_info, 0, size);
3220
3221 /* Zero out the descriptor ring */
3222 memset(tx_ring->desc, 0, tx_ring->size);
3223
3224 tx_ring->next_to_use = 0;
3225 tx_ring->next_to_clean = 0;
3226
9891ca7c
JB		 3227 if (tx_ring->head)
3228 writel(0, adapter->hw.hw_addr + tx_ring->head);
3229 if (tx_ring->tail)
3230 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3231}
3232
3233/**
021230d4 3234 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3235 * @adapter: board private structure
3236 **/
021230d4 3237static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3238{
3239 int i;
3240
021230d4 3241 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3242 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3243}
3244
3245/**
021230d4 3246 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3247 * @adapter: board private structure
3248 **/
021230d4 3249static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3250{
3251 int i;
3252
021230d4 3253 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3254 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3255}
3256
3257void ixgbe_down(struct ixgbe_adapter *adapter)
3258{
3259 struct net_device *netdev = adapter->netdev;
7f821875 3260 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3261 u32 rxctrl;
7f821875
JB		 3262 u32 txdctl;
3263 int i, j;
9a799d71
AK		 3264
3265 /* signal that we are down to the interrupt handler */
3266 set_bit(__IXGBE_DOWN, &adapter->state);
3267
61fac744
PW		 3268 /* power down the optics */
3269 if (hw->phy.multispeed_fiber)
3270 hw->mac.ops.disable_tx_laser(hw);
3271
767081ad
GR		 3272 /* disable receive for all VFs and wait one second */
3273 if (adapter->num_vfs) {
767081ad
GR		 3274 /* ping all the active vfs to let them know we are going down */
3275 ixgbe_ping_all_vfs(adapter);
581d1aa7 3276
767081ad
GR		 3277 /* Disable all VFTE/VFRE TX/RX */
3278 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3279
3280 /* Mark all the VFs as inactive */
3281 for (i = 0 ; i < adapter->num_vfs; i++)
3282 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3283 }
3284
9a799d71 3285 /* disable receives */
7f821875
JB		 3286 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3287 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 3288
3289 netif_tx_disable(netdev);
3290
7f821875 3291 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3292 msleep(10);
3293
7f821875
JB		 3294 netif_tx_stop_all_queues(netdev);
3295
9a799d71
AK		 3296 ixgbe_irq_disable(adapter);
3297
021230d4 3298 ixgbe_napi_disable_all(adapter);
7f821875 3299
0a1f87cb
DS		 3300 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3301 del_timer_sync(&adapter->sfp_timer);
9a799d71 3302 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3303 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3304
c4cf55e5
PWJ		 3305 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3306 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3307 cancel_work_sync(&adapter->fdir_reinit_task);
3308
7f821875
JB		 3309 /* disable transmits in the hardware now that interrupts are off */
3310 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3311 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3312 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3313 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3314 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3315 }
88512539
PW		 3316 /* Disable the Tx DMA engine on 82599 */
3317 if (hw->mac.type == ixgbe_mac_82599EB)
3318 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3319 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3320 ~IXGBE_DMATXCTL_TE));
7f821875 3321
9a799d71 3322 netif_carrier_off(netdev);
9a799d71 3323
9a713e7c
PW		 3324 /* clear n-tuple filters that are cached */
3325 ethtool_ntuple_flush(netdev);
3326
6f4a0e45
PL		 3327 if (!pci_channel_offline(adapter->pdev))
3328 ixgbe_reset(adapter);
9a799d71
AK		 3329 ixgbe_clean_all_tx_rings(adapter);
3330 ixgbe_clean_all_rx_rings(adapter);
3331
5dd2d332 3332#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3333 /* since we reset the hardware DCA settings were cleared */
e35ec126 3334 ixgbe_setup_dca(adapter);
96b0e0f6 3335#endif
9a799d71
AK		 3336}
3337
9a799d71 3338/**
021230d4
AV		 3339 * ixgbe_poll - NAPI Rx polling callback
3340 * @napi: structure for representing this polling device
3341 * @budget: how many packets driver is allowed to clean
3342 *
3343 * This function is used for legacy and MSI, NAPI mode
9a799d71 3344 **/
021230d4 3345static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3346{
9a1a69ad
JB		 3347 struct ixgbe_q_vector *q_vector =
3348 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3349 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3350 int tx_clean_complete, work_done = 0;
9a799d71 3351
5dd2d332 3352#ifdef CONFIG_IXGBE_DCA
bd0362dd 3353 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3354 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3355 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3356 }
3357#endif
3358
4a0b9ca0
PW		 3359 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3360 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3361
9a1a69ad 3362 if (!tx_clean_complete)
d2c7ddd6
DM		 3363 work_done = budget;
3364
53e52c72
DM		 3365 /* If budget not fully consumed, exit the polling mode */
3366 if (work_done < budget) {
288379f0 3367 napi_complete(napi);
f7554a2b 3368 if (adapter->rx_itr_setting & 1)
f494e8fa 3369 ixgbe_set_itr(adapter);
d4f80882 3370 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3371 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3372 }
9a799d71
AK		 3373 return work_done;
3374}
3375
3376/**
3377 * ixgbe_tx_timeout - Respond to a Tx Hang
3378 * @netdev: network interface device structure
3379 **/
3380static void ixgbe_tx_timeout(struct net_device *netdev)
3381{
3382 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3383
3384 /* Do the reset outside of interrupt context */
3385 schedule_work(&adapter->reset_task);
3386}
3387
3388static void ixgbe_reset_task(struct work_struct *work)
3389{
3390 struct ixgbe_adapter *adapter;
3391 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3392
2f90b865
AD		 3393 /* If we're already down or resetting, just bail */
3394 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3395 test_bit(__IXGBE_RESETTING, &adapter->state))
3396 return;
3397
9a799d71
AK		 3398 adapter->tx_timeout_count++;
3399
d4f80882 3400 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3401}
3402
bc97114d
PWJ		 3403#ifdef CONFIG_IXGBE_DCB
3404static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3405{
bc97114d 3406 bool ret = false;
0cefafad 3407 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3408
0cefafad
JB		 3409 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3410 return ret;
3411
3412 f->mask = 0x7 << 3;
3413 adapter->num_rx_queues = f->indices;
3414 adapter->num_tx_queues = f->indices;
3415 ret = true;
2f90b865 3416
bc97114d
PWJ		 3417 return ret;
3418}
3419#endif
3420
4df10466
JB		 3421/**
3422 * ixgbe_set_rss_queues: Allocate queues for RSS
3423 * @adapter: board private structure to initialize
3424 *
3425 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3426 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3427 *
3428 **/
bc97114d
PWJ		 3429static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3430{
3431 bool ret = false;
0cefafad 3432 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3433
3434 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3435 f->mask = 0xF;
3436 adapter->num_rx_queues = f->indices;
3437 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3438 ret = true;
3439 } else {
bc97114d 3440 ret = false;
b9804972
JB		 3441 }
3442
bc97114d
PWJ		 3443 return ret;
3444}
3445
c4cf55e5
PWJ		 3446/**
3447 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3448 * @adapter: board private structure to initialize
3449 *
3450 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3451 * to the original CPU that initiated the Tx session. This runs in addition
3452 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3453 * Rx load across CPUs using RSS.
3454 *
3455 **/
3456static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3457{
3458 bool ret = false;
3459 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3460
3461 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3462 f_fdir->mask = 0;
3463
3464 /* Flow Director must have RSS enabled */
3465 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3466 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3467 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3468 adapter->num_tx_queues = f_fdir->indices;
3469 adapter->num_rx_queues = f_fdir->indices;
3470 ret = true;
3471 } else {
3472 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3473 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3474 }
3475 return ret;
3476}
3477
0331a832
YZ		 3478#ifdef IXGBE_FCOE
3479/**
3480 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3481 * @adapter: board private structure to initialize
3482 *
3483 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3484 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3485 * rx queues out of the max number of rx queues, instead, it is used as the
3486 * index of the first rx queue used by FCoE.
3487 *
3488 **/
3489static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3490{
3491 bool ret = false;
3492 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3493
3494 f->indices = min((int)num_online_cpus(), f->indices);
3495 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3496 adapter->num_rx_queues = 1;
3497 adapter->num_tx_queues = 1;
0331a832
YZ		 3498#ifdef CONFIG_IXGBE_DCB
3499 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
d6dbee86 3500 DPRINTK(PROBE, INFO, "FCoE enabled with DCB\n");
0331a832
YZ		 3501 ixgbe_set_dcb_queues(adapter);
3502 }
3503#endif
3504 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
d6dbee86 3505 DPRINTK(PROBE, INFO, "FCoE enabled with RSS\n");
8faa2a78
YZ		 3506 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3507 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3508 ixgbe_set_fdir_queues(adapter);
3509 else
3510 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3511 }
3512 /* adding FCoE rx rings to the end */
3513 f->mask = adapter->num_rx_queues;
3514 adapter->num_rx_queues += f->indices;
8de8b2e6 3515 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3516
3517 ret = true;
3518 }
3519
3520 return ret;
3521}
3522
3523#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3524/**
3525 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3526 * @adapter: board private structure to initialize
3527 *
3528 * IOV doesn't actually use anything, so just NAK the
3529 * request for now and let the other queue routines
3530 * figure out what to do.
3531 */
3532static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3533{
3534 return false;
3535}
3536
4df10466
JB		 3537/*
3538 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3539 * @adapter: board private structure to initialize
3540 *
3541 * This is the top level queue allocation routine. The order here is very
3542 * important, starting with the "most" number of features turned on at once,
3543 * and ending with the smallest set of features. This way large combinations
3544 * can be allocated if they're turned on, and smaller combinations are the
3545 * fallthrough conditions.
3546 *
3547 **/
bc97114d
PWJ		 3548static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3549{
1cdd1ec8
GR		 3550 /* Start with base case */
3551 adapter->num_rx_queues = 1;
3552 adapter->num_tx_queues = 1;
3553 adapter->num_rx_pools = adapter->num_rx_queues;
3554 adapter->num_rx_queues_per_pool = 1;
3555
3556 if (ixgbe_set_sriov_queues(adapter))
3557 return;
3558
0331a832
YZ		 3559#ifdef IXGBE_FCOE
3560 if (ixgbe_set_fcoe_queues(adapter))
3561 goto done;
3562
3563#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3564#ifdef CONFIG_IXGBE_DCB
3565 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3566 goto done;
bc97114d
PWJ		 3567
3568#endif
c4cf55e5
PWJ		 3569 if (ixgbe_set_fdir_queues(adapter))
3570 goto done;
3571
bc97114d 3572 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3573 goto done;
3574
3575 /* fallback to base case */
3576 adapter->num_rx_queues = 1;
3577 adapter->num_tx_queues = 1;
3578
3579done:
3580 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3581 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3582}
3583
021230d4 3584static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3585 int vectors)
021230d4
AV		 3586{
3587 int err, vector_threshold;
3588
3589 /* We'll want at least 3 (vector_threshold):
3590 * 1) TxQ[0] Cleanup
3591 * 2) RxQ[0] Cleanup
3592 * 3) Other (Link Status Change, etc.)
3593 * 4) TCP Timer (optional)
3594 */
3595 vector_threshold = MIN_MSIX_COUNT;
3596
3597 /* The more we get, the more we will assign to Tx/Rx Cleanup
3598 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3599 * Right now, we simply care about how many we'll get; we'll
3600 * set them up later while requesting irq's.
3601 */
3602 while (vectors >= vector_threshold) {
3603 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3604 vectors);
021230d4
AV		 3605 if (!err) /* Success in acquiring all requested vectors. */
3606 break;
3607 else if (err < 0)
3608 vectors = 0; /* Nasty failure, quit now */
3609 else /* err == number of vectors we should try again with */
3610 vectors = err;
3611 }
3612
3613 if (vectors < vector_threshold) {
3614 /* Can't allocate enough MSI-X interrupts? Oh well.
3615 * This just means we'll go with either a single MSI
3616 * vector or fall back to legacy interrupts.
3617 */
3618 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3619 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3620 kfree(adapter->msix_entries);
3621 adapter->msix_entries = NULL;
021230d4
AV		 3622 } else {
3623 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3624 /*
3625 * Adjust for only the vectors we'll use, which is minimum
3626 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3627 * vectors we were allocated.
3628 */
3629 adapter->num_msix_vectors = min(vectors,
3630 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3631 }
3632}
3633
021230d4 3634/**
bc97114d 3635 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3636 * @adapter: board private structure to initialize
3637 *
bc97114d
PWJ		 3638 * Cache the descriptor ring offsets for RSS to the assigned rings.
3639 *
021230d4 3640 **/
bc97114d 3641static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3642{
bc97114d
PWJ		 3643 int i;
3644 bool ret = false;
3645
3646 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3647 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3648 adapter->rx_ring[i]->reg_idx = i;
bc97114d 3649 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3650 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 3651 ret = true;
3652 } else {
3653 ret = false;
3654 }
3655
3656 return ret;
3657}
3658
3659#ifdef CONFIG_IXGBE_DCB
3660/**
3661 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3662 * @adapter: board private structure to initialize
3663 *
3664 * Cache the descriptor ring offsets for DCB to the assigned rings.
3665 *
3666 **/
3667static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3668{
3669 int i;
3670 bool ret = false;
3671 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3672
3673 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3674 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3675 /* the number of queues is assumed to be symmetric */
3676 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 3677 adapter->rx_ring[i]->reg_idx = i << 3;
3678 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 3679 }
bc97114d 3680 ret = true;
e8e26350 3681 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3682 if (dcb_i == 8) {
3683 /*
3684 * Tx TC0 starts at: descriptor queue 0
3685 * Tx TC1 starts at: descriptor queue 32
3686 * Tx TC2 starts at: descriptor queue 64
3687 * Tx TC3 starts at: descriptor queue 80
3688 * Tx TC4 starts at: descriptor queue 96
3689 * Tx TC5 starts at: descriptor queue 104
3690 * Tx TC6 starts at: descriptor queue 112
3691 * Tx TC7 starts at: descriptor queue 120
3692 *
3693 * Rx TC0-TC7 are offset by 16 queues each
3694 */
3695 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 3696 adapter->tx_ring[i]->reg_idx = i << 5;
3697 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3698 }
3699 for ( ; i < 5; i++) {
4a0b9ca0 3700 adapter->tx_ring[i]->reg_idx =
f92ef202 3701 ((i + 2) << 4);
4a0b9ca0 3702 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3703 }
3704 for ( ; i < dcb_i; i++) {
4a0b9ca0 3705 adapter->tx_ring[i]->reg_idx =
f92ef202 3706 ((i + 8) << 3);
4a0b9ca0 3707 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3708 }
3709
3710 ret = true;
3711 } else if (dcb_i == 4) {
3712 /*
3713 * Tx TC0 starts at: descriptor queue 0
3714 * Tx TC1 starts at: descriptor queue 64
3715 * Tx TC2 starts at: descriptor queue 96
3716 * Tx TC3 starts at: descriptor queue 112
3717 *
3718 * Rx TC0-TC3 are offset by 32 queues each
3719 */
4a0b9ca0
PW		 3720 adapter->tx_ring[0]->reg_idx = 0;
3721 adapter->tx_ring[1]->reg_idx = 64;
3722 adapter->tx_ring[2]->reg_idx = 96;
3723 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 3724 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 3725 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 3726
3727 ret = true;
3728 } else {
3729 ret = false;
e8e26350 3730 }
bc97114d
PWJ		 3731 } else {
3732 ret = false;
021230d4 3733 }
bc97114d
PWJ		 3734 } else {
3735 ret = false;
021230d4 3736 }
bc97114d
PWJ		 3737
3738 return ret;
3739}
3740#endif
3741
c4cf55e5
PWJ		 3742/**
3743 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3744 * @adapter: board private structure to initialize
3745 *
3746 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3747 *
3748 **/
3749static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3750{
3751 int i;
3752 bool ret = false;
3753
3754 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3755 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3756 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3757 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3758 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 3759 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3760 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 3761 ret = true;
3762 }
3763
3764 return ret;
3765}
3766
0331a832
YZ		 3767#ifdef IXGBE_FCOE
3768/**
3769 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3770 * @adapter: board private structure to initialize
3771 *
3772 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3773 *
3774 */
3775static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3776{
8de8b2e6 3777 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 3778 bool ret = false;
3779 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3780
3781 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3782#ifdef CONFIG_IXGBE_DCB
3783 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 3784 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3785
0331a832 3786 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 3787 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 3788 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
3789 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 3790 /*
3791 * In 82599, the number of Tx queues for each traffic
3792 * class for both 8-TC and 4-TC modes are:
3793 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3794 * 8 TCs: 32 32 16 16 8 8 8 8
3795 * 4 TCs: 64 64 32 32
3796 * We have max 8 queues for FCoE, where 8 the is
3797 * FCoE redirection table size. If TC for FCoE is
3798 * less than or equal to TC3, we have enough queues
3799 * to add max of 8 queues for FCoE, so we start FCoE
3800 * tx descriptor from the next one, i.e., reg_idx + 1.
3801 * If TC for FCoE is above TC3, implying 8 TC mode,
3802 * and we need 8 for FCoE, we have to take all queues
3803 * in that traffic class for FCoE.
3804 */
3805 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3806 fcoe_tx_i--;
0331a832
YZ		 3807 }
3808#endif /* CONFIG_IXGBE_DCB */
3809 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3810 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3811 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3812 ixgbe_cache_ring_fdir(adapter);
3813 else
3814 ixgbe_cache_ring_rss(adapter);
3815
8de8b2e6
YZ		 3816 fcoe_rx_i = f->mask;
3817 fcoe_tx_i = f->mask;
3818 }
3819 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 3820 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
3821 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 3822 }
0331a832
YZ		 3823 ret = true;
3824 }
3825 return ret;
3826}
3827
3828#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3829/**
3830 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3831 * @adapter: board private structure to initialize
3832 *
3833 * SR-IOV doesn't use any descriptor rings but changes the default if
3834 * no other mapping is used.
3835 *
3836 */
3837static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
3838{
4a0b9ca0
PW		 3839 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
3840 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 3841 if (adapter->num_vfs)
3842 return true;
3843 else
3844 return false;
3845}
3846
bc97114d
PWJ		 3847/**
3848 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3849 * @adapter: board private structure to initialize
3850 *
3851 * Once we know the feature-set enabled for the device, we'll cache
3852 * the register offset the descriptor ring is assigned to.
3853 *
3854 * Note, the order the various feature calls is important. It must start with
3855 * the "most" features enabled at the same time, then trickle down to the
3856 * least amount of features turned on at once.
3857 **/
3858static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3859{
3860 /* start with default case */
4a0b9ca0
PW		 3861 adapter->rx_ring[0]->reg_idx = 0;
3862 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 3863
1cdd1ec8
GR		 3864 if (ixgbe_cache_ring_sriov(adapter))
3865 return;
3866
0331a832
YZ		 3867#ifdef IXGBE_FCOE
3868 if (ixgbe_cache_ring_fcoe(adapter))
3869 return;
3870
3871#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3872#ifdef CONFIG_IXGBE_DCB
3873 if (ixgbe_cache_ring_dcb(adapter))
3874 return;
3875
3876#endif
c4cf55e5
PWJ		 3877 if (ixgbe_cache_ring_fdir(adapter))
3878 return;
3879
bc97114d
PWJ		 3880 if (ixgbe_cache_ring_rss(adapter))
3881 return;
021230d4
AV		 3882}
3883
9a799d71
AK		 3884/**
3885 * ixgbe_alloc_queues - Allocate memory for all rings
3886 * @adapter: board private structure to initialize
3887 *
3888 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3889 * number of queues at compile-time. The polling_netdev array is
3890 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3891 **/
2f90b865 3892static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3893{
3894 int i;
4a0b9ca0 3895 int orig_node = adapter->node;
9a799d71 3896
021230d4 3897 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 3898 struct ixgbe_ring *ring = adapter->tx_ring[i];
3899 if (orig_node == -1) {
3900 int cur_node = next_online_node(adapter->node);
3901 if (cur_node == MAX_NUMNODES)
3902 cur_node = first_online_node;
3903 adapter->node = cur_node;
3904 }
3905 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3906 adapter->node);
3907 if (!ring)
3908 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3909 if (!ring)
3910 goto err_tx_ring_allocation;
3911 ring->count = adapter->tx_ring_count;
3912 ring->queue_index = i;
3913 ring->numa_node = adapter->node;
3914
3915 adapter->tx_ring[i] = ring;
021230d4 3916 }
b9804972 3917
4a0b9ca0
PW		 3918 /* Restore the adapter's original node */
3919 adapter->node = orig_node;
3920
9a799d71 3921 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 3922 struct ixgbe_ring *ring = adapter->rx_ring[i];
3923 if (orig_node == -1) {
3924 int cur_node = next_online_node(adapter->node);
3925 if (cur_node == MAX_NUMNODES)
3926 cur_node = first_online_node;
3927 adapter->node = cur_node;
3928 }
3929 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3930 adapter->node);
3931 if (!ring)
3932 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3933 if (!ring)
3934 goto err_rx_ring_allocation;
3935 ring->count = adapter->rx_ring_count;
3936 ring->queue_index = i;
3937 ring->numa_node = adapter->node;
3938
3939 adapter->rx_ring[i] = ring;
021230d4
AV		 3940 }
3941
4a0b9ca0
PW		 3942 /* Restore the adapter's original node */
3943 adapter->node = orig_node;
3944
021230d4
AV		 3945 ixgbe_cache_ring_register(adapter);
3946
3947 return 0;
3948
3949err_rx_ring_allocation:
4a0b9ca0
PW		 3950 for (i = 0; i < adapter->num_tx_queues; i++)
3951 kfree(adapter->tx_ring[i]);
021230d4
AV		 3952err_tx_ring_allocation:
3953 return -ENOMEM;
3954}
3955
3956/**
3957 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3958 * @adapter: board private structure to initialize
3959 *
3960 * Attempt to configure the interrupts using the best available
3961 * capabilities of the hardware and the kernel.
3962 **/
feea6a57 3963static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3964{
8be0e467 3965 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3966 int err = 0;
3967 int vector, v_budget;
3968
3969 /*
3970 * It's easy to be greedy for MSI-X vectors, but it really
3971 * doesn't do us much good if we have a lot more vectors
3972 * than CPU's. So let's be conservative and only ask for
342bde1b 3973 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 3974 */
3975 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 3976 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 3977
3978 /*
3979 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3980 * hw.mac->max_msix_vectors vectors. With features
3981 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3982 * descriptor queues supported by our device. Thus, we cap it off in
3983 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3984 */
8be0e467 3985 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3986
3987 /* A failure in MSI-X entry allocation isn't fatal, but it does
3988 * mean we disable MSI-X capabilities of the adapter. */
3989 adapter->msix_entries = kcalloc(v_budget,
b4617240 3990 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3991 if (adapter->msix_entries) {
3992 for (vector = 0; vector < v_budget; vector++)
3993 adapter->msix_entries[vector].entry = vector;
021230d4 3994
7a921c93 3995 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3996
7a921c93
AD		 3997 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3998 goto out;
3999 }
021230d4 4000
7a921c93
AD		 4001 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4002 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4003 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4004 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4005 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4006 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4007 ixgbe_disable_sriov(adapter);
4008
7a921c93 4009 ixgbe_set_num_queues(adapter);
021230d4 4010
021230d4
AV		 4011 err = pci_enable_msi(adapter->pdev);
4012 if (!err) {
4013 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4014 } else {
4015 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 4016 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4017 /* reset err */
4018 err = 0;
4019 }
4020
4021out:
021230d4
AV		 4022 return err;
4023}
4024
7a921c93
AD		 4025/**
4026 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4027 * @adapter: board private structure to initialize
4028 *
4029 * We allocate one q_vector per queue interrupt. If allocation fails we
4030 * return -ENOMEM.
4031 **/
4032static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4033{
4034 int q_idx, num_q_vectors;
4035 struct ixgbe_q_vector *q_vector;
4036 int napi_vectors;
4037 int (*poll)(struct napi_struct *, int);
4038
4039 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4040 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4041 napi_vectors = adapter->num_rx_queues;
91281fd3 4042 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4043 } else {
4044 num_q_vectors = 1;
4045 napi_vectors = 1;
4046 poll = &ixgbe_poll;
4047 }
4048
4049 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2
JB		 4050 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4051 GFP_KERNEL, adapter->node);
4052 if (!q_vector)
4053 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4054 GFP_KERNEL);
7a921c93
AD		 4055 if (!q_vector)
4056 goto err_out;
4057 q_vector->adapter = adapter;
f7554a2b
NS		 4058 if (q_vector->txr_count && !q_vector->rxr_count)
4059 q_vector->eitr = adapter->tx_eitr_param;
4060 else
4061 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4062 q_vector->v_idx = q_idx;
91281fd3 4063 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4064 adapter->q_vector[q_idx] = q_vector;
4065 }
4066
4067 return 0;
4068
4069err_out:
4070 while (q_idx) {
4071 q_idx--;
4072 q_vector = adapter->q_vector[q_idx];
4073 netif_napi_del(&q_vector->napi);
4074 kfree(q_vector);
4075 adapter->q_vector[q_idx] = NULL;
4076 }
4077 return -ENOMEM;
4078}
4079
4080/**
4081 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4082 * @adapter: board private structure to initialize
4083 *
4084 * This function frees the memory allocated to the q_vectors. In addition if
4085 * NAPI is enabled it will delete any references to the NAPI struct prior
4086 * to freeing the q_vector.
4087 **/
4088static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4089{
4090 int q_idx, num_q_vectors;
7a921c93 4091
91281fd3 4092 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4093 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4094 else
7a921c93 4095 num_q_vectors = 1;
7a921c93
AD		 4096
4097 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4098 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4099 adapter->q_vector[q_idx] = NULL;
91281fd3 4100 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4101 kfree(q_vector);
4102 }
4103}
4104
7b25cdba 4105static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4106{
4107 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4108 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4109 pci_disable_msix(adapter->pdev);
4110 kfree(adapter->msix_entries);
4111 adapter->msix_entries = NULL;
4112 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4113 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4114 pci_disable_msi(adapter->pdev);
4115 }
4116 return;
4117}
4118
4119/**
4120 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4121 * @adapter: board private structure to initialize
4122 *
4123 * We determine which interrupt scheme to use based on...
4124 * - Kernel support (MSI, MSI-X)
4125 * - which can be user-defined (via MODULE_PARAM)
4126 * - Hardware queue count (num_*_queues)
4127 * - defined by miscellaneous hardware support/features (RSS, etc.)
4128 **/
2f90b865 4129int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4130{
4131 int err;
4132
4133 /* Number of supported queues */
4134 ixgbe_set_num_queues(adapter);
4135
021230d4
AV		 4136 err = ixgbe_set_interrupt_capability(adapter);
4137 if (err) {
4138 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4139 goto err_set_interrupt;
9a799d71
AK		 4140 }
4141
7a921c93
AD		 4142 err = ixgbe_alloc_q_vectors(adapter);
4143 if (err) {
4144 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4145 "vectors\n");
4146 goto err_alloc_q_vectors;
4147 }
4148
4149 err = ixgbe_alloc_queues(adapter);
4150 if (err) {
4151 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4152 goto err_alloc_queues;
4153 }
4154
021230d4 4155 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 4156 "Tx Queue count = %u\n",
4157 (adapter->num_rx_queues > 1) ? "Enabled" :
4158 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4159
4160 set_bit(__IXGBE_DOWN, &adapter->state);
4161
9a799d71 4162 return 0;
021230d4 4163
7a921c93
AD		 4164err_alloc_queues:
4165 ixgbe_free_q_vectors(adapter);
4166err_alloc_q_vectors:
4167 ixgbe_reset_interrupt_capability(adapter);
021230d4 4168err_set_interrupt:
7a921c93
AD		 4169 return err;
4170}
4171
4172/**
4173 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4174 * @adapter: board private structure to clear interrupt scheme on
4175 *
4176 * We go through and clear interrupt specific resources and reset the structure
4177 * to pre-load conditions
4178 **/
4179void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4180{
4a0b9ca0
PW		 4181 int i;
4182
4183 for (i = 0; i < adapter->num_tx_queues; i++) {
4184 kfree(adapter->tx_ring[i]);
4185 adapter->tx_ring[i] = NULL;
4186 }
4187 for (i = 0; i < adapter->num_rx_queues; i++) {
4188 kfree(adapter->rx_ring[i]);
4189 adapter->rx_ring[i] = NULL;
4190 }
7a921c93
AD		 4191
4192 ixgbe_free_q_vectors(adapter);
4193 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4194}
4195
c4900be0
DS		 4196/**
4197 * ixgbe_sfp_timer - worker thread to find a missing module
4198 * @data: pointer to our adapter struct
4199 **/
4200static void ixgbe_sfp_timer(unsigned long data)
4201{
4202 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4203
4df10466
JB		 4204 /*
4205 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4206 * delays that sfp+ detection requires
4207 */
4208 schedule_work(&adapter->sfp_task);
4209}
4210
4211/**
4212 * ixgbe_sfp_task - worker thread to find a missing module
4213 * @work: pointer to work_struct containing our data
4214 **/
4215static void ixgbe_sfp_task(struct work_struct *work)
4216{
4217 struct ixgbe_adapter *adapter = container_of(work,
4218 struct ixgbe_adapter,
4219 sfp_task);
4220 struct ixgbe_hw *hw = &adapter->hw;
4221
4222 if ((hw->phy.type == ixgbe_phy_nl) &&
4223 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4224 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4225 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4226 goto reschedule;
4227 ret = hw->phy.ops.reset(hw);
4228 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4229 dev_err(&adapter->pdev->dev, "failed to initialize "
4230 "because an unsupported SFP+ module type "
4231 "was detected.\n"
4232 "Reload the driver after installing a "
4233 "supported module.\n");
c4900be0
DS		 4234 unregister_netdev(adapter->netdev);
4235 } else {
4236 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4237 hw->phy.sfp_type);
4238 }
4239 /* don't need this routine any more */
4240 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4241 }
4242 return;
4243reschedule:
4244 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4245 mod_timer(&adapter->sfp_timer,
4246 round_jiffies(jiffies + (2 * HZ)));
4247}
4248
9a799d71
AK		 4249/**
4250 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4251 * @adapter: board private structure to initialize
4252 *
4253 * ixgbe_sw_init initializes the Adapter private data structure.
4254 * Fields are initialized based on PCI device information and
4255 * OS network device settings (MTU size).
4256 **/
4257static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4258{
4259 struct ixgbe_hw *hw = &adapter->hw;
4260 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4261 struct net_device *dev = adapter->netdev;
021230d4 4262 unsigned int rss;
7a6b6f51 4263#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4264 int j;
4265 struct tc_configuration *tc;
4266#endif
021230d4 4267
c44ade9e
JB		 4268 /* PCI config space info */
4269
4270 hw->vendor_id = pdev->vendor;
4271 hw->device_id = pdev->device;
4272 hw->revision_id = pdev->revision;
4273 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4274 hw->subsystem_device_id = pdev->subsystem_device;
4275
021230d4
AV		 4276 /* Set capability flags */
4277 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4278 adapter->ring_feature[RING_F_RSS].indices = rss;
4279 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4280 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4281 if (hw->mac.type == ixgbe_mac_82598EB) {
4282 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4283 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4284 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4285 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4286 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4287 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4288 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9a713e7c
PW		 4289 if (dev->features & NETIF_F_NTUPLE) {
4290 /* Flow Director perfect filter enabled */
4291 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4292 adapter->atr_sample_rate = 0;
4293 spin_lock_init(&adapter->fdir_perfect_lock);
4294 } else {
4295 /* Flow Director hash filters enabled */
4296 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4297 adapter->atr_sample_rate = 20;
4298 }
c4cf55e5
PWJ		 4299 adapter->ring_feature[RING_F_FDIR].indices =
4300 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4301 adapter->fdir_pballoc = 0;
eacd73f7 4302#ifdef IXGBE_FCOE
0d551589
YZ		 4303 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4304 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4305 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4306#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4307 /* Default traffic class to use for FCoE */
4308 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
61a0f421 4309#endif
eacd73f7 4310#endif /* IXGBE_FCOE */
f8212f97 4311 }
2f90b865 4312
7a6b6f51 4313#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4314 /* Configure DCB traffic classes */
4315 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4316 tc = &adapter->dcb_cfg.tc_config[j];
4317 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4318 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4319 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4320 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4321 tc->dcb_pfc = pfc_disabled;
4322 }
4323 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4324 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4325 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4326 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4327 adapter->dcb_cfg.round_robin_enable = false;
4328 adapter->dcb_set_bitmap = 0x00;
4329 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4330 adapter->ring_feature[RING_F_DCB].indices);
4331
4332#endif
9a799d71
AK		 4333
4334 /* default flow control settings */
cd7664f6 4335 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4336 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4337#ifdef CONFIG_DCB
4338 adapter->last_lfc_mode = hw->fc.current_mode;
4339#endif
2b9ade93
JB		 4340 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4341 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4342 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4343 hw->fc.send_xon = true;
71fd570b 4344 hw->fc.disable_fc_autoneg = false;
9a799d71 4345
30efa5a3 4346 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4347 adapter->rx_itr_setting = 1;
4348 adapter->rx_eitr_param = 20000;
4349 adapter->tx_itr_setting = 1;
4350 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4351
4352 /* set defaults for eitr in MegaBytes */
4353 adapter->eitr_low = 10;
4354 adapter->eitr_high = 20;
4355
4356 /* set default ring sizes */
4357 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4358 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4359
9a799d71 4360 /* initialize eeprom parameters */
c44ade9e 4361 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 4362 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4363 return -EIO;
4364 }
4365
021230d4 4366 /* enable rx csum by default */
9a799d71
AK		 4367 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4368
1a6c14a2
JB		 4369 /* get assigned NUMA node */
4370 adapter->node = dev_to_node(&pdev->dev);
4371
9a799d71
AK		 4372 set_bit(__IXGBE_DOWN, &adapter->state);
4373
4374 return 0;
4375}
4376
4377/**
4378 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4379 * @adapter: board private structure
3a581073 4380 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4381 *
4382 * Return 0 on success, negative on failure
4383 **/
4384int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4385 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4386{
4387 struct pci_dev *pdev = adapter->pdev;
4388 int size;
4389
3a581073 4390 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4391 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4392 if (!tx_ring->tx_buffer_info)
4393 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4394 if (!tx_ring->tx_buffer_info)
4395 goto err;
3a581073 4396 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4397
4398 /* round up to nearest 4K */
12207e49 4399 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4400 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4401
3a581073
JB		 4402 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4403 &tx_ring->dma);
e01c31a5
JB		 4404 if (!tx_ring->desc)
4405 goto err;
9a799d71 4406
3a581073
JB		 4407 tx_ring->next_to_use = 0;
4408 tx_ring->next_to_clean = 0;
4409 tx_ring->work_limit = tx_ring->count;
9a799d71 4410 return 0;
e01c31a5
JB		 4411
4412err:
4413 vfree(tx_ring->tx_buffer_info);
4414 tx_ring->tx_buffer_info = NULL;
4415 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4416 "descriptor ring\n");
4417 return -ENOMEM;
9a799d71
AK		 4418}
4419
69888674
AD		 4420/**
4421 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4422 * @adapter: board private structure
4423 *
4424 * If this function returns with an error, then it's possible one or
4425 * more of the rings is populated (while the rest are not). It is the
4426 * callers duty to clean those orphaned rings.
4427 *
4428 * Return 0 on success, negative on failure
4429 **/
4430static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4431{
4432 int i, err = 0;
4433
4434 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 4435 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 4436 if (!err)
4437 continue;
4438 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4439 break;
4440 }
4441
4442 return err;
4443}
4444
9a799d71
AK		 4445/**
4446 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4447 * @adapter: board private structure
3a581073 4448 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4449 *
4450 * Returns 0 on success, negative on failure
4451 **/
4452int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4453 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4454{
4455 struct pci_dev *pdev = adapter->pdev;
021230d4 4456 int size;
9a799d71 4457
3a581073 4458 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 4459 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4460 if (!rx_ring->rx_buffer_info)
4461 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 4462 if (!rx_ring->rx_buffer_info) {
9a799d71 4463 DPRINTK(PROBE, ERR,
b4617240 4464 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 4465 goto alloc_failed;
9a799d71 4466 }
3a581073 4467 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4468
9a799d71 4469 /* Round up to nearest 4K */
3a581073
JB		 4470 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4471 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4472
3a581073 4473 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 4474
3a581073 4475 if (!rx_ring->desc) {
9a799d71 4476 DPRINTK(PROBE, ERR,
b4617240 4477 "Memory allocation failed for the rx desc ring\n");
3a581073 4478 vfree(rx_ring->rx_buffer_info);
177db6ff 4479 goto alloc_failed;
9a799d71
AK		 4480 }
4481
3a581073
JB		 4482 rx_ring->next_to_clean = 0;
4483 rx_ring->next_to_use = 0;
9a799d71
AK		 4484
4485 return 0;
177db6ff
MC		 4486
4487alloc_failed:
177db6ff 4488 return -ENOMEM;
9a799d71
AK		 4489}
4490
69888674
AD		 4491/**
4492 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4493 * @adapter: board private structure
4494 *
4495 * If this function returns with an error, then it's possible one or
4496 * more of the rings is populated (while the rest are not). It is the
4497 * callers duty to clean those orphaned rings.
4498 *
4499 * Return 0 on success, negative on failure
4500 **/
4501
4502static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4503{
4504 int i, err = 0;
4505
4506 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 4507 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 4508 if (!err)
4509 continue;
4510 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4511 break;
4512 }
4513
4514 return err;
4515}
4516
9a799d71
AK		 4517/**
4518 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4519 * @adapter: board private structure
4520 * @tx_ring: Tx descriptor ring for a specific queue
4521 *
4522 * Free all transmit software resources
4523 **/
c431f97e
JB		 4524void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4525 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4526{
4527 struct pci_dev *pdev = adapter->pdev;
4528
4529 ixgbe_clean_tx_ring(adapter, tx_ring);
4530
4531 vfree(tx_ring->tx_buffer_info);
4532 tx_ring->tx_buffer_info = NULL;
4533
4534 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4535
4536 tx_ring->desc = NULL;
4537}
4538
4539/**
4540 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4541 * @adapter: board private structure
4542 *
4543 * Free all transmit software resources
4544 **/
4545static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4546{
4547 int i;
4548
4549 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 4550 if (adapter->tx_ring[i]->desc)
4551 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 4552}
4553
4554/**
b4617240 4555 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4556 * @adapter: board private structure
4557 * @rx_ring: ring to clean the resources from
4558 *
4559 * Free all receive software resources
4560 **/
c431f97e
JB		 4561void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4562 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4563{
4564 struct pci_dev *pdev = adapter->pdev;
4565
4566 ixgbe_clean_rx_ring(adapter, rx_ring);
4567
4568 vfree(rx_ring->rx_buffer_info);
4569 rx_ring->rx_buffer_info = NULL;
4570
4571 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4572
4573 rx_ring->desc = NULL;
4574}
4575
4576/**
4577 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4578 * @adapter: board private structure
4579 *
4580 * Free all receive software resources
4581 **/
4582static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4583{
4584 int i;
4585
4586 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 4587 if (adapter->rx_ring[i]->desc)
4588 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 4589}
4590
9a799d71
AK		 4591/**
4592 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4593 * @netdev: network interface device structure
4594 * @new_mtu: new value for maximum frame size
4595 *
4596 * Returns 0 on success, negative on failure
4597 **/
4598static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4599{
4600 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4601 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4602
42c783c5
JB		 4603 /* MTU < 68 is an error and causes problems on some kernels */
4604 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4605 return -EINVAL;
4606
021230d4 4607 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4608 netdev->mtu, new_mtu);
021230d4 4609 /* must set new MTU before calling down or up */
9a799d71
AK		 4610 netdev->mtu = new_mtu;
4611
d4f80882
AV		 4612 if (netif_running(netdev))
4613 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4614
4615 return 0;
4616}
4617
4618/**
4619 * ixgbe_open - Called when a network interface is made active
4620 * @netdev: network interface device structure
4621 *
4622 * Returns 0 on success, negative value on failure
4623 *
4624 * The open entry point is called when a network interface is made
4625 * active by the system (IFF_UP). At this point all resources needed
4626 * for transmit and receive operations are allocated, the interrupt
4627 * handler is registered with the OS, the watchdog timer is started,
4628 * and the stack is notified that the interface is ready.
4629 **/
4630static int ixgbe_open(struct net_device *netdev)
4631{
4632 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4633 int err;
4bebfaa5
AK		 4634
4635 /* disallow open during test */
4636 if (test_bit(__IXGBE_TESTING, &adapter->state))
4637 return -EBUSY;
9a799d71 4638
54386467
JB		 4639 netif_carrier_off(netdev);
4640
9a799d71
AK		 4641 /* allocate transmit descriptors */
4642 err = ixgbe_setup_all_tx_resources(adapter);
4643 if (err)
4644 goto err_setup_tx;
4645
9a799d71
AK		 4646 /* allocate receive descriptors */
4647 err = ixgbe_setup_all_rx_resources(adapter);
4648 if (err)
4649 goto err_setup_rx;
4650
4651 ixgbe_configure(adapter);
4652
021230d4 4653 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4654 if (err)
4655 goto err_req_irq;
4656
9a799d71
AK		 4657 err = ixgbe_up_complete(adapter);
4658 if (err)
4659 goto err_up;
4660
d55b53ff
JK		 4661 netif_tx_start_all_queues(netdev);
4662
9a799d71
AK		 4663 return 0;
4664
4665err_up:
5eba3699 4666 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4667 ixgbe_free_irq(adapter);
4668err_req_irq:
9a799d71 4669err_setup_rx:
a20a1199 4670 ixgbe_free_all_rx_resources(adapter);
9a799d71 4671err_setup_tx:
a20a1199 4672 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4673 ixgbe_reset(adapter);
4674
4675 return err;
4676}
4677
4678/**
4679 * ixgbe_close - Disables a network interface
4680 * @netdev: network interface device structure
4681 *
4682 * Returns 0, this is not allowed to fail
4683 *
4684 * The close entry point is called when an interface is de-activated
4685 * by the OS. The hardware is still under the drivers control, but
4686 * needs to be disabled. A global MAC reset is issued to stop the
4687 * hardware, and all transmit and receive resources are freed.
4688 **/
4689static int ixgbe_close(struct net_device *netdev)
4690{
4691 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4692
4693 ixgbe_down(adapter);
4694 ixgbe_free_irq(adapter);
4695
4696 ixgbe_free_all_tx_resources(adapter);
4697 ixgbe_free_all_rx_resources(adapter);
4698
5eba3699 4699 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4700
4701 return 0;
4702}
4703
b3c8b4ba
AD		 4704#ifdef CONFIG_PM
4705static int ixgbe_resume(struct pci_dev *pdev)
4706{
4707 struct net_device *netdev = pci_get_drvdata(pdev);
4708 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4709 u32 err;
4710
4711 pci_set_power_state(pdev, PCI_D0);
4712 pci_restore_state(pdev);
656ab817
DS		 4713 /*
4714 * pci_restore_state clears dev->state_saved so call
4715 * pci_save_state to restore it.
4716 */
4717 pci_save_state(pdev);
9ce77666 4718
4719 err = pci_enable_device_mem(pdev);
b3c8b4ba 4720 if (err) {
69888674 4721 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4722 "suspend\n");
4723 return err;
4724 }
4725 pci_set_master(pdev);
4726
dd4d8ca6 4727 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4728
4729 err = ixgbe_init_interrupt_scheme(adapter);
4730 if (err) {
4731 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4732 "device\n");
4733 return err;
4734 }
4735
b3c8b4ba
AD		 4736 ixgbe_reset(adapter);
4737
495dce12
WJP		 4738 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4739
b3c8b4ba
AD		 4740 if (netif_running(netdev)) {
4741 err = ixgbe_open(adapter->netdev);
4742 if (err)
4743 return err;
4744 }
4745
4746 netif_device_attach(netdev);
4747
4748 return 0;
4749}
b3c8b4ba 4750#endif /* CONFIG_PM */
9d8d05ae
RW		 4751
4752static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4753{
4754 struct net_device *netdev = pci_get_drvdata(pdev);
4755 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4756 struct ixgbe_hw *hw = &adapter->hw;
4757 u32 ctrl, fctrl;
4758 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4759#ifdef CONFIG_PM
4760 int retval = 0;
4761#endif
4762
4763 netif_device_detach(netdev);
4764
4765 if (netif_running(netdev)) {
4766 ixgbe_down(adapter);
4767 ixgbe_free_irq(adapter);
4768 ixgbe_free_all_tx_resources(adapter);
4769 ixgbe_free_all_rx_resources(adapter);
4770 }
7a921c93 4771 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4772
4773#ifdef CONFIG_PM
4774 retval = pci_save_state(pdev);
4775 if (retval)
4776 return retval;
4df10466 4777
b3c8b4ba 4778#endif
e8e26350
PW		 4779 if (wufc) {
4780 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4781
e8e26350
PW		 4782 /* turn on all-multi mode if wake on multicast is enabled */
4783 if (wufc & IXGBE_WUFC_MC) {
4784 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4785 fctrl |= IXGBE_FCTRL_MPE;
4786 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4787 }
4788
4789 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4790 ctrl |= IXGBE_CTRL_GIO_DIS;
4791 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4792
4793 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4794 } else {
4795 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4796 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4797 }
4798
dd4d8ca6
DS		 4799 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4800 pci_wake_from_d3(pdev, true);
4801 else
4802 pci_wake_from_d3(pdev, false);
b3c8b4ba 4803
9d8d05ae
RW		 4804 *enable_wake = !!wufc;
4805
b3c8b4ba
AD		 4806 ixgbe_release_hw_control(adapter);
4807
4808 pci_disable_device(pdev);
4809
9d8d05ae
RW		 4810 return 0;
4811}
4812
4813#ifdef CONFIG_PM
4814static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4815{
4816 int retval;
4817 bool wake;
4818
4819 retval = __ixgbe_shutdown(pdev, &wake);
4820 if (retval)
4821 return retval;
4822
4823 if (wake) {
4824 pci_prepare_to_sleep(pdev);
4825 } else {
4826 pci_wake_from_d3(pdev, false);
4827 pci_set_power_state(pdev, PCI_D3hot);
4828 }
b3c8b4ba
AD		 4829
4830 return 0;
4831}
9d8d05ae 4832#endif /* CONFIG_PM */
b3c8b4ba
AD		 4833
4834static void ixgbe_shutdown(struct pci_dev *pdev)
4835{
9d8d05ae
RW		 4836 bool wake;
4837
4838 __ixgbe_shutdown(pdev, &wake);
4839
4840 if (system_state == SYSTEM_POWER_OFF) {
4841 pci_wake_from_d3(pdev, wake);
4842 pci_set_power_state(pdev, PCI_D3hot);
4843 }
b3c8b4ba
AD		 4844}
4845
9a799d71
AK		 4846/**
4847 * ixgbe_update_stats - Update the board statistics counters.
4848 * @adapter: board private structure
4849 **/
4850void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4851{
2d86f139 4852 struct net_device *netdev = adapter->netdev;
9a799d71 4853 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4854 u64 total_mpc = 0;
4855 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 4856 u64 non_eop_descs = 0, restart_queue = 0;
9a799d71 4857
94b982b2 4858 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 4859 u64 rsc_count = 0;
94b982b2 4860 u64 rsc_flush = 0;
d51019a4
PW		 4861 for (i = 0; i < 16; i++)
4862 adapter->hw_rx_no_dma_resources +=
4863 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 4864 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4865 rsc_count += adapter->rx_ring[i]->rsc_count;
4866 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 4867 }
4868 adapter->rsc_total_count = rsc_count;
4869 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 4870 }
4871
7ca3bc58
JB		 4872 /* gather some stats to the adapter struct that are per queue */
4873 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4874 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 4875 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 4876
4877 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4878 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 4879 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 4880
9a799d71 4881 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4882 for (i = 0; i < 8; i++) {
4883 /* for packet buffers not used, the register should read 0 */
4884 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4885 missed_rx += mpc;
4886 adapter->stats.mpc[i] += mpc;
4887 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4888 if (hw->mac.type == ixgbe_mac_82598EB)
4889 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4890 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4891 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4892 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4893 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4894 if (hw->mac.type == ixgbe_mac_82599EB) {
4895 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4896 IXGBE_PXONRXCNT(i));
4897 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4898 IXGBE_PXOFFRXCNT(i));
4899 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4900 } else {
4901 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4902 IXGBE_PXONRXC(i));
4903 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4904 IXGBE_PXOFFRXC(i));
4905 }
2f90b865
AD		 4906 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4907 IXGBE_PXONTXC(i));
2f90b865 4908 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4909 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4910 }
4911 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4912 /* work around hardware counting issue */
4913 adapter->stats.gprc -= missed_rx;
4914
4915 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 4916 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 4917 u64 tmp;
e8e26350 4918 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 4919 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4920 adapter->stats.gorc += (tmp << 32);
e8e26350 4921 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 4922 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4923 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 4924 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4925 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4926 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4927 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4928 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4929 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4930#ifdef IXGBE_FCOE
4931 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4932 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4933 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4934 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4935 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4936 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4937#endif /* IXGBE_FCOE */
e8e26350
PW		 4938 } else {
4939 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4940 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4941 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4942 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4943 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4944 }
9a799d71
AK		 4945 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4946 adapter->stats.bprc += bprc;
4947 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4948 if (hw->mac.type == ixgbe_mac_82598EB)
4949 adapter->stats.mprc -= bprc;
9a799d71
AK		 4950 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4951 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4952 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4953 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4954 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4955 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4956 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4957 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4958 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4959 adapter->stats.lxontxc += lxon;
4960 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4961 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4962 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4963 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4964 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4965 /*
4966 * 82598 errata - tx of flow control packets is included in tx counters
4967 */
4968 xon_off_tot = lxon + lxoff;
4969 adapter->stats.gptc -= xon_off_tot;
4970 adapter->stats.mptc -= xon_off_tot;
4971 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4972 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4973 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4974 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4975 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4976 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4977 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4978 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4979 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4980 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4981 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4982 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4983 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4984
4985 /* Fill out the OS statistics structure */
2d86f139 4986 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 4987
4988 /* Rx Errors */
2d86f139 4989 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 4990 adapter->stats.rlec;
2d86f139
AK		 4991 netdev->stats.rx_dropped = 0;
4992 netdev->stats.rx_length_errors = adapter->stats.rlec;
4993 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4994 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4995}
4996
4997/**
4998 * ixgbe_watchdog - Timer Call-back
4999 * @data: pointer to adapter cast into an unsigned long
5000 **/
5001static void ixgbe_watchdog(unsigned long data)
5002{
5003 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5004 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5005 u64 eics = 0;
5006 int i;
cf8280ee 5007
fe49f04a
AD		 5008 /*
5009 * Do the watchdog outside of interrupt context due to the lovely
5010 * delays that some of the newer hardware requires
5011 */
22d5a71b 5012
fe49f04a
AD		 5013 if (test_bit(__IXGBE_DOWN, &adapter->state))
5014 goto watchdog_short_circuit;
22d5a71b 5015
fe49f04a
AD		 5016 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5017 /*
5018 * for legacy and MSI interrupts don't set any bits
5019 * that are enabled for EIAM, because this operation
5020 * would set *both* EIMS and EICS for any bit in EIAM
5021 */
5022 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5023 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5024 goto watchdog_reschedule;
5025 }
5026
5027 /* get one bit for every active tx/rx interrupt vector */
5028 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5029 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5030 if (qv->rxr_count || qv->txr_count)
5031 eics |= ((u64)1 << i);
cf8280ee 5032 }
9a799d71 5033
fe49f04a
AD		 5034 /* Cause software interrupt to ensure rx rings are cleaned */
5035 ixgbe_irq_rearm_queues(adapter, eics);
5036
5037watchdog_reschedule:
5038 /* Reset the timer */
5039 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5040
5041watchdog_short_circuit:
cf8280ee
JB		 5042 schedule_work(&adapter->watchdog_task);
5043}
5044
e8e26350
PW		 5045/**
5046 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5047 * @work: pointer to work_struct containing our data
5048 **/
5049static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5050{
5051 struct ixgbe_adapter *adapter = container_of(work,
5052 struct ixgbe_adapter,
5053 multispeed_fiber_task);
5054 struct ixgbe_hw *hw = &adapter->hw;
5055 u32 autoneg;
8620a103 5056 bool negotiation;
e8e26350
PW		 5057
5058 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5059 autoneg = hw->phy.autoneg_advertised;
5060 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5061 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5062 hw->mac.autotry_restart = false;
8620a103
MC		 5063 if (hw->mac.ops.setup_link)
5064 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5065 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5066 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5067}
5068
5069/**
5070 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5071 * @work: pointer to work_struct containing our data
5072 **/
5073static void ixgbe_sfp_config_module_task(struct work_struct *work)
5074{
5075 struct ixgbe_adapter *adapter = container_of(work,
5076 struct ixgbe_adapter,
5077 sfp_config_module_task);
5078 struct ixgbe_hw *hw = &adapter->hw;
5079 u32 err;
5080
5081 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5082
5083 /* Time for electrical oscillations to settle down */
5084 msleep(100);
e8e26350 5085 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5086
e8e26350 5087 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5088 dev_err(&adapter->pdev->dev, "failed to initialize because "
5089 "an unsupported SFP+ module type was detected.\n"
5090 "Reload the driver after installing a supported "
5091 "module.\n");
63d6e1d8 5092 unregister_netdev(adapter->netdev);
e8e26350
PW		 5093 return;
5094 }
5095 hw->mac.ops.setup_sfp(hw);
5096
8d1c3c07 5097 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5098 /* This will also work for DA Twinax connections */
5099 schedule_work(&adapter->multispeed_fiber_task);
5100 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5101}
5102
c4cf55e5
PWJ		 5103/**
5104 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5105 * @work: pointer to work_struct containing our data
5106 **/
5107static void ixgbe_fdir_reinit_task(struct work_struct *work)
5108{
5109 struct ixgbe_adapter *adapter = container_of(work,
5110 struct ixgbe_adapter,
5111 fdir_reinit_task);
5112 struct ixgbe_hw *hw = &adapter->hw;
5113 int i;
5114
5115 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5116 for (i = 0; i < adapter->num_tx_queues; i++)
5117 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 5118 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5
PWJ		 5119 } else {
5120 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
d6dbee86 5121 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5122 }
5123 /* Done FDIR Re-initialization, enable transmits */
5124 netif_tx_start_all_queues(adapter->netdev);
5125}
5126
10eec955
JF		 5127static DEFINE_MUTEX(ixgbe_watchdog_lock);
5128
cf8280ee 5129/**
69888674
AD		 5130 * ixgbe_watchdog_task - worker thread to bring link up
5131 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5132 **/
5133static void ixgbe_watchdog_task(struct work_struct *work)
5134{
5135 struct ixgbe_adapter *adapter = container_of(work,
5136 struct ixgbe_adapter,
5137 watchdog_task);
5138 struct net_device *netdev = adapter->netdev;
5139 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5140 u32 link_speed;
5141 bool link_up;
bc59fcda
NS		 5142 int i;
5143 struct ixgbe_ring *tx_ring;
5144 int some_tx_pending = 0;
cf8280ee 5145
10eec955
JF		 5146 mutex_lock(&ixgbe_watchdog_lock);
5147
5148 link_up = adapter->link_up;
5149 link_speed = adapter->link_speed;
cf8280ee
JB		 5150
5151 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5152 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5153 if (link_up) {
5154#ifdef CONFIG_DCB
5155 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5156 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5157 hw->mac.ops.fc_enable(hw, i);
264857b8 5158 } else {
620fa036 5159 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5160 }
5161#else
620fa036 5162 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5163#endif
5164 }
5165
cf8280ee
JB		 5166 if (link_up ||
5167 time_after(jiffies, (adapter->link_check_timeout +
5168 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5169 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5170 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5171 }
5172 adapter->link_up = link_up;
5173 adapter->link_speed = link_speed;
5174 }
9a799d71
AK		 5175
5176 if (link_up) {
5177 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5178 bool flow_rx, flow_tx;
5179
5180 if (hw->mac.type == ixgbe_mac_82599EB) {
5181 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5182 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5183 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5184 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5185 } else {
5186 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5187 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5188 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5189 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5190 }
5191
a46e534b
JK		 5192 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5193 "Flow Control: %s\n",
5194 netdev->name,
5195 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5196 "10 Gbps" :
5197 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5198 "1 Gbps" : "unknown speed")),
e8e26350
PW		 5199 ((flow_rx && flow_tx) ? "RX/TX" :
5200 (flow_rx ? "RX" :
5201 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5202
5203 netif_carrier_on(netdev);
9a799d71
AK		 5204 } else {
5205 /* Force detection of hung controller */
5206 adapter->detect_tx_hung = true;
5207 }
5208 } else {
cf8280ee
JB		 5209 adapter->link_up = false;
5210 adapter->link_speed = 0;
9a799d71 5211 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 5212 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5213 netdev->name);
9a799d71 5214 netif_carrier_off(netdev);
9a799d71
AK		 5215 }
5216 }
5217
bc59fcda
NS		 5218 if (!netif_carrier_ok(netdev)) {
5219 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5220 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5221 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5222 some_tx_pending = 1;
5223 break;
5224 }
5225 }
5226
5227 if (some_tx_pending) {
5228 /* We've lost link, so the controller stops DMA,
5229 * but we've got queued Tx work that's never going
5230 * to get done, so reset controller to flush Tx.
5231 * (Do the reset outside of interrupt context).
5232 */
5233 schedule_work(&adapter->reset_task);
5234 }
5235 }
5236
9a799d71 5237 ixgbe_update_stats(adapter);
10eec955 5238 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5239}
5240
9a799d71 5241static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 5242 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5243 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5244{
5245 struct ixgbe_adv_tx_context_desc *context_desc;
5246 unsigned int i;
5247 int err;
5248 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5249 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5250 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5251
5252 if (skb_is_gso(skb)) {
5253 if (skb_header_cloned(skb)) {
5254 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5255 if (err)
5256 return err;
5257 }
5258 l4len = tcp_hdrlen(skb);
5259 *hdr_len += l4len;
5260
8327d000 5261 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5262 struct iphdr *iph = ip_hdr(skb);
5263 iph->tot_len = 0;
5264 iph->check = 0;
5265 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 5266 iph->daddr, 0,
5267 IPPROTO_TCP,
5268 0);
8e1e8a47 5269 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5270 ipv6_hdr(skb)->payload_len = 0;
5271 tcp_hdr(skb)->check =
5272 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 5273 &ipv6_hdr(skb)->daddr,
5274 0, IPPROTO_TCP, 0);
9a799d71
AK		 5275 }
5276
5277 i = tx_ring->next_to_use;
5278
5279 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5280 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5281
5282 /* VLAN MACLEN IPLEN */
5283 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5284 vlan_macip_lens |=
5285 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5286 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 5287 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5288 *hdr_len += skb_network_offset(skb);
5289 vlan_macip_lens |=
5290 (skb_transport_header(skb) - skb_network_header(skb));
5291 *hdr_len +=
5292 (skb_transport_header(skb) - skb_network_header(skb));
5293 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5294 context_desc->seqnum_seed = 0;
5295
5296 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5297 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 5298 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5299
8327d000 5300 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5301 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5302 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5303 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5304
5305 /* MSS L4LEN IDX */
9f8cdf4f 5306 mss_l4len_idx =
9a799d71
AK		 5307 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5308 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5309 /* use index 1 for TSO */
5310 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5311 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5312
5313 tx_buffer_info->time_stamp = jiffies;
5314 tx_buffer_info->next_to_watch = i;
5315
5316 i++;
5317 if (i == tx_ring->count)
5318 i = 0;
5319 tx_ring->next_to_use = i;
5320
5321 return true;
5322 }
5323 return false;
5324}
5325
5326static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 5327 struct ixgbe_ring *tx_ring,
5328 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5329{
5330 struct ixgbe_adv_tx_context_desc *context_desc;
5331 unsigned int i;
5332 struct ixgbe_tx_buffer *tx_buffer_info;
5333 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5334
5335 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5336 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5337 i = tx_ring->next_to_use;
5338 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5339 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5340
5341 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5342 vlan_macip_lens |=
5343 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5344 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 5345 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5346 if (skb->ip_summed == CHECKSUM_PARTIAL)
5347 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 5348 skb_network_header(skb));
9a799d71
AK		 5349
5350 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5351 context_desc->seqnum_seed = 0;
5352
5353 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 5354 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 5355
5356 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ca553980
GS		 5357 __be16 protocol;
5358
5359 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5360 const struct vlan_ethhdr *vhdr =
5361 (const struct vlan_ethhdr *)skb->data;
5362
5363 protocol = vhdr->h_vlan_encapsulated_proto;
5364 } else {
5365 protocol = skb->protocol;
5366 }
5367
5368 switch (protocol) {
09640e63 5369 case cpu_to_be16(ETH_P_IP):
9a799d71 5370 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 5371 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5372 type_tucmd_mlhl |=
b4617240 5373 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5374 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5375 type_tucmd_mlhl |=
5376 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5377 break;
09640e63 5378 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5379 /* XXX what about other V6 headers?? */
5380 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5381 type_tucmd_mlhl |=
b4617240 5382 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5383 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5384 type_tucmd_mlhl |=
5385 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5386 break;
41825d71
AK		 5387 default:
5388 if (unlikely(net_ratelimit())) {
5389 DPRINTK(PROBE, WARNING,
5390 "partial checksum but proto=%x!\n",
5391 skb->protocol);
5392 }
5393 break;
5394 }
9a799d71
AK		 5395 }
5396
5397 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5398 /* use index zero for tx checksum offload */
9a799d71
AK		 5399 context_desc->mss_l4len_idx = 0;
5400
5401 tx_buffer_info->time_stamp = jiffies;
5402 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5403
9a799d71
AK		 5404 i++;
5405 if (i == tx_ring->count)
5406 i = 0;
5407 tx_ring->next_to_use = i;
5408
5409 return true;
5410 }
9f8cdf4f 5411
9a799d71
AK		 5412 return false;
5413}
5414
5415static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5416 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5417 struct sk_buff *skb, u32 tx_flags,
5418 unsigned int first)
9a799d71 5419{
e5a43549 5420 struct pci_dev *pdev = adapter->pdev;
9a799d71 5421 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5422 unsigned int len;
5423 unsigned int total = skb->len;
9a799d71
AK		 5424 unsigned int offset = 0, size, count = 0, i;
5425 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5426 unsigned int f;
9a799d71
AK		 5427
5428 i = tx_ring->next_to_use;
5429
eacd73f7
YZ		 5430 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5431 /* excluding fcoe_crc_eof for FCoE */
5432 total -= sizeof(struct fcoe_crc_eof);
5433
5434 len = min(skb_headlen(skb), total);
9a799d71
AK		 5435 while (len) {
5436 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5437 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5438
5439 tx_buffer_info->length = size;
e5a43549
AD		 5440 tx_buffer_info->mapped_as_page = false;
5441 tx_buffer_info->dma = pci_map_single(pdev,
5442 skb->data + offset,
5443 size, PCI_DMA_TODEVICE);
5444 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5445 goto dma_error;
9a799d71
AK		 5446 tx_buffer_info->time_stamp = jiffies;
5447 tx_buffer_info->next_to_watch = i;
5448
5449 len -= size;
eacd73f7 5450 total -= size;
9a799d71
AK		 5451 offset += size;
5452 count++;
44df32c5
AD		 5453
5454 if (len) {
5455 i++;
5456 if (i == tx_ring->count)
5457 i = 0;
5458 }
9a799d71
AK		 5459 }
5460
5461 for (f = 0; f < nr_frags; f++) {
5462 struct skb_frag_struct *frag;
5463
5464 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5465 len = min((unsigned int)frag->size, total);
e5a43549 5466 offset = frag->page_offset;
9a799d71
AK		 5467
5468 while (len) {
44df32c5
AD		 5469 i++;
5470 if (i == tx_ring->count)
5471 i = 0;
5472
9a799d71
AK		 5473 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5474 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5475
5476 tx_buffer_info->length = size;
e5a43549
AD		 5477 tx_buffer_info->dma = pci_map_page(adapter->pdev,
5478 frag->page,
5479 offset, size,
5480 PCI_DMA_TODEVICE);
5481 tx_buffer_info->mapped_as_page = true;
5482 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5483 goto dma_error;
9a799d71
AK		 5484 tx_buffer_info->time_stamp = jiffies;
5485 tx_buffer_info->next_to_watch = i;
5486
5487 len -= size;
eacd73f7 5488 total -= size;
9a799d71
AK		 5489 offset += size;
5490 count++;
9a799d71 5491 }
eacd73f7
YZ		 5492 if (total == 0)
5493 break;
9a799d71 5494 }
44df32c5 5495
9a799d71
AK		 5496 tx_ring->tx_buffer_info[i].skb = skb;
5497 tx_ring->tx_buffer_info[first].next_to_watch = i;
5498
e5a43549
AD		 5499 return count;
5500
5501dma_error:
5502 dev_err(&pdev->dev, "TX DMA map failed\n");
5503
5504 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5505 tx_buffer_info->dma = 0;
5506 tx_buffer_info->time_stamp = 0;
5507 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 5508 if (count)
5509 count--;
e5a43549
AD		 5510
5511 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f
RK		 5512 while (count--) {
5513 if (i==0)
e5a43549 5514 i += tx_ring->count;
c1fa347f 5515 i--;
e5a43549
AD		 5516 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5517 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5518 }
5519
e44d38e1 5520 return 0;
9a799d71
AK		 5521}
5522
5523static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 5524 struct ixgbe_ring *tx_ring,
5525 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 5526{
5527 union ixgbe_adv_tx_desc *tx_desc = NULL;
5528 struct ixgbe_tx_buffer *tx_buffer_info;
5529 u32 olinfo_status = 0, cmd_type_len = 0;
5530 unsigned int i;
5531 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5532
5533 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5534
5535 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5536
5537 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5538 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5539
5540 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5541 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5542
5543 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5544 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5545
4eeae6fd
PW		 5546 /* use index 1 context for tso */
5547 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5548 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5549 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 5550 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5551
5552 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5553 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5554 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5555
eacd73f7
YZ		 5556 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5557 olinfo_status |= IXGBE_ADVTXD_CC;
5558 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5559 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5560 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5561 }
5562
9a799d71
AK		 5563 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5564
5565 i = tx_ring->next_to_use;
5566 while (count--) {
5567 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5568 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5569 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5570 tx_desc->read.cmd_type_len =
b4617240 5571 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5572 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5573 i++;
5574 if (i == tx_ring->count)
5575 i = 0;
5576 }
5577
5578 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5579
5580 /*
5581 * Force memory writes to complete before letting h/w
5582 * know there are new descriptors to fetch. (Only
5583 * applicable for weak-ordered memory model archs,
5584 * such as IA-64).
5585 */
5586 wmb();
5587
5588 tx_ring->next_to_use = i;
5589 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5590}
5591
c4cf55e5
PWJ		 5592static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5593 int queue, u32 tx_flags)
5594{
5595 /* Right now, we support IPv4 only */
5596 struct ixgbe_atr_input atr_input;
5597 struct tcphdr *th;
c4cf55e5
PWJ		 5598 struct iphdr *iph = ip_hdr(skb);
5599 struct ethhdr *eth = (struct ethhdr *)skb->data;
5600 u16 vlan_id, src_port, dst_port, flex_bytes;
5601 u32 src_ipv4_addr, dst_ipv4_addr;
5602 u8 l4type = 0;
5603
5604 /* check if we're UDP or TCP */
5605 if (iph->protocol == IPPROTO_TCP) {
5606 th = tcp_hdr(skb);
5607 src_port = th->source;
5608 dst_port = th->dest;
5609 l4type |= IXGBE_ATR_L4TYPE_TCP;
5610 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 5611 } else {
5612 /* Unsupported L4 header, just bail here */
5613 return;
5614 }
5615
5616 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5617
5618 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5619 IXGBE_TX_FLAGS_VLAN_SHIFT;
5620 src_ipv4_addr = iph->saddr;
5621 dst_ipv4_addr = iph->daddr;
5622 flex_bytes = eth->h_proto;
5623
5624 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5625 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5626 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5627 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5628 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5629 /* src and dst are inverted, think how the receiver sees them */
5630 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5631 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5632
5633 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5634 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5635}
5636
e092be60 5637static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5638 struct ixgbe_ring *tx_ring, int size)
e092be60 5639{
30eba97a 5640 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5641 /* Herbert's original patch had:
5642 * smp_mb__after_netif_stop_queue();
5643 * but since that doesn't exist yet, just open code it. */
5644 smp_mb();
5645
5646 /* We need to check again in a case another CPU has just
5647 * made room available. */
5648 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5649 return -EBUSY;
5650
5651 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5652 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 5653 ++tx_ring->restart_queue;
e092be60
AV		 5654 return 0;
5655}
5656
5657static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5658 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5659{
5660 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5661 return 0;
5662 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5663}
5664
09a3b1f8
SH		 5665static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5666{
5667 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 5668 int txq = smp_processor_id();
09a3b1f8 5669
fdd3d631
KK		 5670 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5671 while (unlikely(txq >= dev->real_num_tx_queues))
5672 txq -= dev->real_num_tx_queues;
5f715823 5673 return txq;
fdd3d631 5674 }
c4cf55e5 5675
5f715823
YZ		 5676#ifdef IXGBE_FCOE
5677 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
ca77cd59
RL		 5678 ((skb->protocol == htons(ETH_P_FCOE)) ||
5679 (skb->protocol == htons(ETH_P_FIP)))) {
5f715823
YZ		 5680 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5681 txq += adapter->ring_feature[RING_F_FCOE].mask;
5682 return txq;
5683 }
5684#endif
2ea186ae
JF		 5685 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5686 if (skb->priority == TC_PRIO_CONTROL)
5687 txq = adapter->ring_feature[RING_F_DCB].indices-1;
5688 else
5689 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
5690 >> 13;
5691 return txq;
5692 }
09a3b1f8
SH		 5693
5694 return skb_tx_hash(dev, skb);
5695}
5696
3b29a56d
SH		 5697static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5698 struct net_device *netdev)
9a799d71
AK		 5699{
5700 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5701 struct ixgbe_ring *tx_ring;
60d51134 5702 struct netdev_queue *txq;
9a799d71
AK		 5703 unsigned int first;
5704 unsigned int tx_flags = 0;
30eba97a 5705 u8 hdr_len = 0;
5f715823 5706 int tso;
9a799d71
AK		 5707 int count = 0;
5708 unsigned int f;
9f8cdf4f 5709
9f8cdf4f
JB		 5710 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5711 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5712 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5713 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 5714 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 5715 }
5716 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5717 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5718 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2ea186ae
JF		 5719 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5720 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5721 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 5722 }
eacd73f7 5723
4a0b9ca0 5724 tx_ring = adapter->tx_ring[skb->queue_mapping];
60127865 5725
09ad1cc0 5726#ifdef IXGBE_FCOE
ca77cd59 5727 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
61a0f421 5728#ifdef CONFIG_IXGBE_DCB
ca77cd59
RL		 5729 /* for FCoE with DCB, we force the priority to what
5730 * was specified by the switch */
5731 if ((skb->protocol == htons(ETH_P_FCOE)) ||
5732 (skb->protocol == htons(ETH_P_FIP))) {
5733 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5734 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5735 tx_flags |= ((adapter->fcoe.up << 13)
5736 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5737 }
09ad1cc0 5738#endif
ca77cd59
RL		 5739 /* flag for FCoE offloads */
5740 if (skb->protocol == htons(ETH_P_FCOE))
5741 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 5742 }
ca77cd59
RL		 5743#endif
5744
eacd73f7 5745 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5746 if (skb_is_gso(skb) ||
5747 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5748 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5749 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5750 count++;
5751
9f8cdf4f
JB		 5752 count += TXD_USE_COUNT(skb_headlen(skb));
5753 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5754 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5755
e092be60 5756 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5757 adapter->tx_busy++;
9a799d71
AK		 5758 return NETDEV_TX_BUSY;
5759 }
9a799d71 5760
9a799d71 5761 first = tx_ring->next_to_use;
eacd73f7
YZ		 5762 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5763#ifdef IXGBE_FCOE
5764 /* setup tx offload for FCoE */
5765 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5766 if (tso < 0) {
5767 dev_kfree_skb_any(skb);
5768 return NETDEV_TX_OK;
5769 }
5770 if (tso)
5771 tx_flags |= IXGBE_TX_FLAGS_FSO;
5772#endif /* IXGBE_FCOE */
5773 } else {
5774 if (skb->protocol == htons(ETH_P_IP))
5775 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5776 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5777 if (tso < 0) {
5778 dev_kfree_skb_any(skb);
5779 return NETDEV_TX_OK;
5780 }
9a799d71 5781
eacd73f7
YZ		 5782 if (tso)
5783 tx_flags |= IXGBE_TX_FLAGS_TSO;
5784 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5785 (skb->ip_summed == CHECKSUM_PARTIAL))
5786 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5787 }
9a799d71 5788
eacd73f7 5789 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5790 if (count) {
c4cf55e5
PWJ		 5791 /* add the ATR filter if ATR is on */
5792 if (tx_ring->atr_sample_rate) {
5793 ++tx_ring->atr_count;
5794 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5795 test_bit(__IXGBE_FDIR_INIT_DONE,
5796 &tx_ring->reinit_state)) {
5797 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5798 tx_flags);
5799 tx_ring->atr_count = 0;
5800 }
5801 }
60d51134
ED		 5802 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
5803 txq->tx_bytes += skb->len;
5804 txq->tx_packets++;
44df32c5
AD		 5805 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5806 hdr_len);
44df32c5 5807 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5808
44df32c5
AD		 5809 } else {
5810 dev_kfree_skb_any(skb);
5811 tx_ring->tx_buffer_info[first].time_stamp = 0;
5812 tx_ring->next_to_use = first;
5813 }
9a799d71
AK		 5814
5815 return NETDEV_TX_OK;
5816}
5817
9a799d71
AK		 5818/**
5819 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5820 * @netdev: network interface device structure
5821 * @p: pointer to an address structure
5822 *
5823 * Returns 0 on success, negative on failure
5824 **/
5825static int ixgbe_set_mac(struct net_device *netdev, void *p)
5826{
5827 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5828 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5829 struct sockaddr *addr = p;
5830
5831 if (!is_valid_ether_addr(addr->sa_data))
5832 return -EADDRNOTAVAIL;
5833
5834 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5835 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5836
1cdd1ec8
GR		 5837 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
5838 IXGBE_RAH_AV);
9a799d71
AK		 5839
5840 return 0;
5841}
5842
6b73e10d
BH		 5843static int
5844ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5845{
5846 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5847 struct ixgbe_hw *hw = &adapter->hw;
5848 u16 value;
5849 int rc;
5850
5851 if (prtad != hw->phy.mdio.prtad)
5852 return -EINVAL;
5853 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5854 if (!rc)
5855 rc = value;
5856 return rc;
5857}
5858
5859static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5860 u16 addr, u16 value)
5861{
5862 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5863 struct ixgbe_hw *hw = &adapter->hw;
5864
5865 if (prtad != hw->phy.mdio.prtad)
5866 return -EINVAL;
5867 return hw->phy.ops.write_reg(hw, addr, devad, value);
5868}
5869
5870static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5871{
5872 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5873
5874 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5875}
5876
0365e6e4
PW		 5877/**
5878 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5879 * netdev->dev_addrs
0365e6e4
PW		 5880 * @netdev: network interface device structure
5881 *
5882 * Returns non-zero on failure
5883 **/
5884static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5885{
5886 int err = 0;
5887 struct ixgbe_adapter *adapter = netdev_priv(dev);
5888 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5889
5890 if (is_valid_ether_addr(mac->san_addr)) {
5891 rtnl_lock();
5892 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5893 rtnl_unlock();
5894 }
5895 return err;
5896}
5897
5898/**
5899 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5900 * netdev->dev_addrs
0365e6e4
PW		 5901 * @netdev: network interface device structure
5902 *
5903 * Returns non-zero on failure
5904 **/
5905static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5906{
5907 int err = 0;
5908 struct ixgbe_adapter *adapter = netdev_priv(dev);
5909 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5910
5911 if (is_valid_ether_addr(mac->san_addr)) {
5912 rtnl_lock();
5913 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5914 rtnl_unlock();
5915 }
5916 return err;
5917}
5918
9a799d71
AK		 5919#ifdef CONFIG_NET_POLL_CONTROLLER
5920/*
5921 * Polling 'interrupt' - used by things like netconsole to send skbs
5922 * without having to re-enable interrupts. It's not called while
5923 * the interrupt routine is executing.
5924 */
5925static void ixgbe_netpoll(struct net_device *netdev)
5926{
5927 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5928 int i;
9a799d71 5929
1a647bd2
AD		 5930 /* if interface is down do nothing */
5931 if (test_bit(__IXGBE_DOWN, &adapter->state))
5932 return;
5933
9a799d71 5934 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5935 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5936 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5937 for (i = 0; i < num_q_vectors; i++) {
5938 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5939 ixgbe_msix_clean_many(0, q_vector);
5940 }
5941 } else {
5942 ixgbe_intr(adapter->pdev->irq, netdev);
5943 }
9a799d71 5944 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5945}
5946#endif
5947
0edc3527
SH		 5948static const struct net_device_ops ixgbe_netdev_ops = {
5949 .ndo_open = ixgbe_open,
5950 .ndo_stop = ixgbe_close,
00829823 5951 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5952 .ndo_select_queue = ixgbe_select_queue,
e90d400c 5953 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5954 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5955 .ndo_validate_addr = eth_validate_addr,
5956 .ndo_set_mac_address = ixgbe_set_mac,
5957 .ndo_change_mtu = ixgbe_change_mtu,
5958 .ndo_tx_timeout = ixgbe_tx_timeout,
5959 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5960 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5961 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5962 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5963#ifdef CONFIG_NET_POLL_CONTROLLER
5964 .ndo_poll_controller = ixgbe_netpoll,
5965#endif
332d4a7d
YZ		 5966#ifdef IXGBE_FCOE
5967 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5968 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 5969 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5970 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 5971 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 5972#endif /* IXGBE_FCOE */
0edc3527
SH		 5973};
5974
1cdd1ec8
GR		 5975static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
5976 const struct ixgbe_info *ii)
5977{
5978#ifdef CONFIG_PCI_IOV
5979 struct ixgbe_hw *hw = &adapter->hw;
5980 int err;
5981
5982 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
5983 return;
5984
5985 /* The 82599 supports up to 64 VFs per physical function
5986 * but this implementation limits allocation to 63 so that
5987 * basic networking resources are still available to the
5988 * physical function
5989 */
5990 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
5991 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
5992 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
5993 if (err) {
5994 DPRINTK(PROBE, ERR,
5995 "Failed to enable PCI sriov: %d\n", err);
5996 goto err_novfs;
5997 }
5998 /* If call to enable VFs succeeded then allocate memory
5999 * for per VF control structures.
6000 */
6001 adapter->vfinfo =
6002 kcalloc(adapter->num_vfs,
6003 sizeof(struct vf_data_storage), GFP_KERNEL);
6004 if (adapter->vfinfo) {
6005 /* Now that we're sure SR-IOV is enabled
6006 * and memory allocated set up the mailbox parameters
6007 */
6008 ixgbe_init_mbx_params_pf(hw);
6009 memcpy(&hw->mbx.ops, ii->mbx_ops,
6010 sizeof(hw->mbx.ops));
6011
6012 /* Disable RSC when in SR-IOV mode */
6013 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6014 IXGBE_FLAG2_RSC_ENABLED);
6015 return;
6016 }
6017
6018 /* Oh oh */
6019 DPRINTK(PROBE, ERR,
6020 "Unable to allocate memory for VF "
6021 "Data Storage - SRIOV disabled\n");
6022 pci_disable_sriov(adapter->pdev);
6023
6024err_novfs:
6025 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6026 adapter->num_vfs = 0;
6027#endif /* CONFIG_PCI_IOV */
6028}
6029
9a799d71
AK		 6030/**
6031 * ixgbe_probe - Device Initialization Routine
6032 * @pdev: PCI device information struct
6033 * @ent: entry in ixgbe_pci_tbl
6034 *
6035 * Returns 0 on success, negative on failure
6036 *
6037 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6038 * The OS initialization, configuring of the adapter private structure,
6039 * and a hardware reset occur.
6040 **/
6041static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 6042 const struct pci_device_id *ent)
9a799d71
AK		 6043{
6044 struct net_device *netdev;
6045 struct ixgbe_adapter *adapter = NULL;
6046 struct ixgbe_hw *hw;
6047 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6048 static int cards_found;
6049 int i, err, pci_using_dac;
c85a2618 6050 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6051#ifdef IXGBE_FCOE
6052 u16 device_caps;
6053#endif
c44ade9e 6054 u32 part_num, eec;
9a799d71 6055
9ce77666 6056 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6057 if (err)
6058 return err;
6059
6a35528a
YH		 6060 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
6061 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6062 pci_using_dac = 1;
6063 } else {
284901a9 6064 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 6065 if (err) {
284901a9 6066 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 6067 if (err) {
b4617240
PW		 6068 dev_err(&pdev->dev, "No usable DMA "
6069 "configuration, aborting\n");
9a799d71
AK		 6070 goto err_dma;
6071 }
6072 }
6073 pci_using_dac = 0;
6074 }
6075
9ce77666 6076 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6077 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6078 if (err) {
9ce77666 6079 dev_err(&pdev->dev,
6080 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6081 goto err_pci_reg;
6082 }
6083
19d5afd4 6084 pci_enable_pcie_error_reporting(pdev);
6fabd715 6085
9a799d71 6086 pci_set_master(pdev);
fb3b27bc 6087 pci_save_state(pdev);
9a799d71 6088
c85a2618
JF		 6089 if (ii->mac == ixgbe_mac_82598EB)
6090 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6091 else
6092 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6093
6094 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6095#ifdef IXGBE_FCOE
6096 indices += min_t(unsigned int, num_possible_cpus(),
6097 IXGBE_MAX_FCOE_INDICES);
6098#endif
c85a2618 6099 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6100 if (!netdev) {
6101 err = -ENOMEM;
6102 goto err_alloc_etherdev;
6103 }
6104
9a799d71
AK		 6105 SET_NETDEV_DEV(netdev, &pdev->dev);
6106
6107 pci_set_drvdata(pdev, netdev);
6108 adapter = netdev_priv(netdev);
6109
6110 adapter->netdev = netdev;
6111 adapter->pdev = pdev;
6112 hw = &adapter->hw;
6113 hw->back = adapter;
6114 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6115
05857980
JK		 6116 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6117 pci_resource_len(pdev, 0));
9a799d71
AK		 6118 if (!hw->hw_addr) {
6119 err = -EIO;
6120 goto err_ioremap;
6121 }
6122
6123 for (i = 1; i <= 5; i++) {
6124 if (pci_resource_len(pdev, i) == 0)
6125 continue;
6126 }
6127
0edc3527 6128 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6129 ixgbe_set_ethtool_ops(netdev);
9a799d71 6130 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6131 strcpy(netdev->name, pci_name(pdev));
6132
9a799d71
AK		 6133 adapter->bd_number = cards_found;
6134
9a799d71
AK		 6135 /* Setup hw api */
6136 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6137 hw->mac.type = ii->mac;
9a799d71 6138
c44ade9e
JB		 6139 /* EEPROM */
6140 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6141 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6142 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6143 if (!(eec & (1 << 8)))
6144 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6145
6146 /* PHY */
6147 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6148 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6149 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6150 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6151 hw->phy.mdio.mmds = 0;
6152 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6153 hw->phy.mdio.dev = netdev;
6154 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6155 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6156
6157 /* set up this timer and work struct before calling get_invariants
6158 * which might start the timer
6159 */
6160 init_timer(&adapter->sfp_timer);
6161 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6162 adapter->sfp_timer.data = (unsigned long) adapter;
6163
6164 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6165
e8e26350
PW		 6166 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6167 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6168
6169 /* a new SFP+ module arrival, called from GPI SDP2 context */
6170 INIT_WORK(&adapter->sfp_config_module_task,
6171 ixgbe_sfp_config_module_task);
6172
8ca783ab 6173 ii->get_invariants(hw);
9a799d71
AK		 6174
6175 /* setup the private structure */
6176 err = ixgbe_sw_init(adapter);
6177 if (err)
6178 goto err_sw_init;
6179
e86bff0e
DS		 6180 /* Make it possible the adapter to be woken up via WOL */
6181 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6182 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6183
bf069c97
DS		 6184 /*
6185 * If there is a fan on this device and it has failed log the
6186 * failure.
6187 */
6188 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6189 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6190 if (esdp & IXGBE_ESDP_SDP1)
6191 DPRINTK(PROBE, CRIT,
6192 "Fan has stopped, replace the adapter\n");
6193 }
6194
c44ade9e
JB		 6195 /* reset_hw fills in the perm_addr as well */
6196 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 6197 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6198 hw->mac.type == ixgbe_mac_82598EB) {
6199 /*
6200 * Start a kernel thread to watch for a module to arrive.
6201 * Only do this for 82598, since 82599 will generate
6202 * interrupts on module arrival.
6203 */
6204 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6205 mod_timer(&adapter->sfp_timer,
6206 round_jiffies(jiffies + (2 * HZ)));
6207 err = 0;
6208 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 6209 dev_err(&adapter->pdev->dev, "failed to initialize because "
6210 "an unsupported SFP+ module type was detected.\n"
6211 "Reload the driver after installing a supported "
6212 "module.\n");
04f165ef
PW		 6213 goto err_sw_init;
6214 } else if (err) {
c44ade9e
JB		 6215 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6216 goto err_sw_init;
6217 }
6218
1cdd1ec8
GR		 6219 ixgbe_probe_vf(adapter, ii);
6220
9a799d71 6221 netdev->features = NETIF_F_SG |
b4617240
PW		 6222 NETIF_F_IP_CSUM |
6223 NETIF_F_HW_VLAN_TX |
6224 NETIF_F_HW_VLAN_RX |
6225 NETIF_F_HW_VLAN_FILTER;
9a799d71 6226
e9990a9c 6227 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6228 netdev->features |= NETIF_F_TSO;
9a799d71 6229 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6230 netdev->features |= NETIF_F_GRO;
ad31c402 6231
45a5ead0
JB		 6232 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6233 netdev->features |= NETIF_F_SCTP_CSUM;
6234
ad31c402
JK		 6235 netdev->vlan_features |= NETIF_F_TSO;
6236 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6237 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6238 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6239 netdev->vlan_features |= NETIF_F_SG;
6240
1cdd1ec8
GR		 6241 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6242 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6243 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6244 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6245 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6246
7a6b6f51 6247#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6248 netdev->dcbnl_ops = &dcbnl_ops;
6249#endif
6250
eacd73f7 6251#ifdef IXGBE_FCOE
0d551589 6252 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6253 if (hw->mac.ops.get_device_caps) {
6254 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6255 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6256 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6257 }
6258 }
6259#endif /* IXGBE_FCOE */
9a799d71
AK		 6260 if (pci_using_dac)
6261 netdev->features |= NETIF_F_HIGHDMA;
6262
0c19d6af 6263 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6264 netdev->features |= NETIF_F_LRO;
6265
9a799d71 6266 /* make sure the EEPROM is good */
c44ade9e 6267 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 6268 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6269 err = -EIO;
6270 goto err_eeprom;
6271 }
6272
6273 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6274 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6275
c44ade9e
JB		 6276 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6277 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 6278 err = -EIO;
6279 goto err_eeprom;
6280 }
6281
61fac744
PW		 6282 /* power down the optics */
6283 if (hw->phy.multispeed_fiber)
6284 hw->mac.ops.disable_tx_laser(hw);
6285
9a799d71
AK		 6286 init_timer(&adapter->watchdog_timer);
6287 adapter->watchdog_timer.function = &ixgbe_watchdog;
6288 adapter->watchdog_timer.data = (unsigned long)adapter;
6289
6290 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6291 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6292
021230d4
AV		 6293 err = ixgbe_init_interrupt_scheme(adapter);
6294 if (err)
6295 goto err_sw_init;
9a799d71 6296
e8e26350
PW		 6297 switch (pdev->device) {
6298 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 6299 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6300 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6301 break;
6302 default:
6303 adapter->wol = 0;
6304 break;
6305 }
e8e26350
PW		 6306 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6307
04f165ef
PW		 6308 /* pick up the PCI bus settings for reporting later */
6309 hw->mac.ops.get_bus_info(hw);
6310
9a799d71 6311 /* print bus type/speed/width info */
7c510e4b 6312 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 6313 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6314 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6315 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6316 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6317 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 6318 "Unknown"),
7c510e4b 6319 netdev->dev_addr);
c44ade9e 6320 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 6321 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6322 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6323 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6324 (part_num >> 8), (part_num & 0xff));
6325 else
6326 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6327 hw->mac.type, hw->phy.type,
6328 (part_num >> 8), (part_num & 0xff));
9a799d71 6329
e8e26350 6330 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 6331 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 6332 "this card is not sufficient for optimal "
6333 "performance.\n");
0c254d86 6334 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 6335 "PCI-Express slot is required.\n");
0c254d86
AK		 6336 }
6337
34b0368c
PWJ		 6338 /* save off EEPROM version number */
6339 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6340
9a799d71 6341 /* reset the hardware with the new settings */
794caeb2 6342 err = hw->mac.ops.start_hw(hw);
c44ade9e 6343
794caeb2
PWJ		 6344 if (err == IXGBE_ERR_EEPROM_VERSION) {
6345 /* We are running on a pre-production device, log a warning */
6346 dev_warn(&pdev->dev, "This device is a pre-production "
6347 "adapter/LOM. Please be aware there may be issues "
6348 "associated with your hardware. If you are "
6349 "experiencing problems please contact your Intel or "
6350 "hardware representative who provided you with this "
6351 "hardware.\n");
6352 }
9a799d71
AK		 6353 strcpy(netdev->name, "eth%d");
6354 err = register_netdev(netdev);
6355 if (err)
6356 goto err_register;
6357
54386467
JB		 6358 /* carrier off reporting is important to ethtool even BEFORE open */
6359 netif_carrier_off(netdev);
6360
c4cf55e5
PWJ		 6361 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6362 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6363 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6364
5dd2d332 6365#ifdef CONFIG_IXGBE_DCA
652f093f 6366 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 6367 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 6368 ixgbe_setup_dca(adapter);
6369 }
6370#endif
1cdd1ec8
GR		 6371 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6372 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6373 adapter->num_vfs);
6374 for (i = 0; i < adapter->num_vfs; i++)
6375 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6376 }
6377
0365e6e4
PW		 6378 /* add san mac addr to netdev */
6379 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 6380
6381 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6382 cards_found++;
6383 return 0;
6384
6385err_register:
5eba3699 6386 ixgbe_release_hw_control(adapter);
7a921c93 6387 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 6388err_sw_init:
6389err_eeprom:
1cdd1ec8
GR		 6390 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6391 ixgbe_disable_sriov(adapter);
c4900be0
DS		 6392 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6393 del_timer_sync(&adapter->sfp_timer);
6394 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6395 cancel_work_sync(&adapter->multispeed_fiber_task);
6396 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 6397 iounmap(hw->hw_addr);
6398err_ioremap:
6399 free_netdev(netdev);
6400err_alloc_etherdev:
9ce77666 6401 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6402 IORESOURCE_MEM));
9a799d71
AK		 6403err_pci_reg:
6404err_dma:
6405 pci_disable_device(pdev);
6406 return err;
6407}
6408
6409/**
6410 * ixgbe_remove - Device Removal Routine
6411 * @pdev: PCI device information struct
6412 *
6413 * ixgbe_remove is called by the PCI subsystem to alert the driver
6414 * that it should release a PCI device. The could be caused by a
6415 * Hot-Plug event, or because the driver is going to be removed from
6416 * memory.
6417 **/
6418static void __devexit ixgbe_remove(struct pci_dev *pdev)
6419{
6420 struct net_device *netdev = pci_get_drvdata(pdev);
6421 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6422
6423 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 6424 /* clear the module not found bit to make sure the worker won't
6425 * reschedule
6426 */
6427 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 6428 del_timer_sync(&adapter->watchdog_timer);
6429
c4900be0
DS		 6430 del_timer_sync(&adapter->sfp_timer);
6431 cancel_work_sync(&adapter->watchdog_task);
6432 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6433 cancel_work_sync(&adapter->multispeed_fiber_task);
6434 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 6435 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6436 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6437 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 6438 flush_scheduled_work();
6439
5dd2d332 6440#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6441 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6442 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6443 dca_remove_requester(&pdev->dev);
6444 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6445 }
6446
6447#endif
332d4a7d
YZ		 6448#ifdef IXGBE_FCOE
6449 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6450 ixgbe_cleanup_fcoe(adapter);
6451
6452#endif /* IXGBE_FCOE */
0365e6e4
PW		 6453
6454 /* remove the added san mac */
6455 ixgbe_del_sanmac_netdev(netdev);
6456
c4900be0
DS		 6457 if (netdev->reg_state == NETREG_REGISTERED)
6458 unregister_netdev(netdev);
9a799d71 6459
1cdd1ec8
GR		 6460 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6461 ixgbe_disable_sriov(adapter);
6462
7a921c93 6463 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 6464
021230d4 6465 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6466
6467 iounmap(adapter->hw.hw_addr);
9ce77666 6468 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6469 IORESOURCE_MEM));
9a799d71 6470
021230d4 6471 DPRINTK(PROBE, INFO, "complete\n");
021230d4 6472
9a799d71
AK		 6473 free_netdev(netdev);
6474
19d5afd4 6475 pci_disable_pcie_error_reporting(pdev);
6fabd715 6476
9a799d71
AK		 6477 pci_disable_device(pdev);
6478}
6479
6480/**
6481 * ixgbe_io_error_detected - called when PCI error is detected
6482 * @pdev: Pointer to PCI device
6483 * @state: The current pci connection state
6484 *
6485 * This function is called after a PCI bus error affecting
6486 * this device has been detected.
6487 */
6488static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 6489 pci_channel_state_t state)
9a799d71
AK		 6490{
6491 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6492 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6493
6494 netif_device_detach(netdev);
6495
3044b8d1
BL		 6496 if (state == pci_channel_io_perm_failure)
6497 return PCI_ERS_RESULT_DISCONNECT;
6498
9a799d71
AK		 6499 if (netif_running(netdev))
6500 ixgbe_down(adapter);
6501 pci_disable_device(pdev);
6502
b4617240 6503 /* Request a slot reset. */
9a799d71
AK		 6504 return PCI_ERS_RESULT_NEED_RESET;
6505}
6506
6507/**
6508 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6509 * @pdev: Pointer to PCI device
6510 *
6511 * Restart the card from scratch, as if from a cold-boot.
6512 */
6513static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6514{
6515 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6516 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 6517 pci_ers_result_t result;
6518 int err;
9a799d71 6519
9ce77666 6520 if (pci_enable_device_mem(pdev)) {
9a799d71 6521 DPRINTK(PROBE, ERR,
b4617240 6522 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 6523 result = PCI_ERS_RESULT_DISCONNECT;
6524 } else {
6525 pci_set_master(pdev);
6526 pci_restore_state(pdev);
c0e1f68b 6527 pci_save_state(pdev);
9a799d71 6528
dd4d8ca6 6529 pci_wake_from_d3(pdev, false);
9a799d71 6530
6fabd715 6531 ixgbe_reset(adapter);
88512539 6532 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 6533 result = PCI_ERS_RESULT_RECOVERED;
6534 }
6535
6536 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6537 if (err) {
6538 dev_err(&pdev->dev,
6539 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6540 /* non-fatal, continue */
6541 }
9a799d71 6542
6fabd715 6543 return result;
9a799d71
AK		 6544}
6545
6546/**
6547 * ixgbe_io_resume - called when traffic can start flowing again.
6548 * @pdev: Pointer to PCI device
6549 *
6550 * This callback is called when the error recovery driver tells us that
6551 * its OK to resume normal operation.
6552 */
6553static void ixgbe_io_resume(struct pci_dev *pdev)
6554{
6555 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6556 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6557
6558 if (netif_running(netdev)) {
6559 if (ixgbe_up(adapter)) {
6560 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6561 return;
6562 }
6563 }
6564
6565 netif_device_attach(netdev);
9a799d71
AK		 6566}
6567
6568static struct pci_error_handlers ixgbe_err_handler = {
6569 .error_detected = ixgbe_io_error_detected,
6570 .slot_reset = ixgbe_io_slot_reset,
6571 .resume = ixgbe_io_resume,
6572};
6573
6574static struct pci_driver ixgbe_driver = {
6575 .name = ixgbe_driver_name,
6576 .id_table = ixgbe_pci_tbl,
6577 .probe = ixgbe_probe,
6578 .remove = __devexit_p(ixgbe_remove),
6579#ifdef CONFIG_PM
6580 .suspend = ixgbe_suspend,
6581 .resume = ixgbe_resume,
6582#endif
6583 .shutdown = ixgbe_shutdown,
6584 .err_handler = &ixgbe_err_handler
6585};
6586
6587/**
6588 * ixgbe_init_module - Driver Registration Routine
6589 *
6590 * ixgbe_init_module is the first routine called when the driver is
6591 * loaded. All it does is register with the PCI subsystem.
6592 **/
6593static int __init ixgbe_init_module(void)
6594{
6595 int ret;
6596 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6597 ixgbe_driver_string, ixgbe_driver_version);
6598
6599 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6600
5dd2d332 6601#ifdef CONFIG_IXGBE_DCA
bd0362dd 6602 dca_register_notify(&dca_notifier);
bd0362dd 6603#endif
5dd2d332 6604
9a799d71
AK		 6605 ret = pci_register_driver(&ixgbe_driver);
6606 return ret;
6607}
b4617240 6608
9a799d71
AK		 6609module_init(ixgbe_init_module);
6610
6611/**
6612 * ixgbe_exit_module - Driver Exit Cleanup Routine
6613 *
6614 * ixgbe_exit_module is called just before the driver is removed
6615 * from memory.
6616 **/
6617static void __exit ixgbe_exit_module(void)
6618{
5dd2d332 6619#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6620 dca_unregister_notify(&dca_notifier);
6621#endif
9a799d71
AK		 6622 pci_unregister_driver(&ixgbe_driver);
6623}
bd0362dd 6624
5dd2d332 6625#ifdef CONFIG_IXGBE_DCA
bd0362dd 6626static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 6627 void *p)
bd0362dd
JC		 6628{
6629 int ret_val;
6630
6631 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 6632 __ixgbe_notify_dca);
bd0362dd
JC		 6633
6634 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6635}
b453368d 6636
5dd2d332 6637#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 6638#ifdef DEBUG
6639/**
6640 * ixgbe_get_hw_dev_name - return device name string
6641 * used by hardware layer to print debugging information
6642 **/
6643char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6644{
6645 struct ixgbe_adapter *adapter = hw->back;
6646 return adapter->netdev->name;
6647}
bd0362dd 6648
b453368d 6649#endif
9a799d71
AK		 6650module_exit(ixgbe_exit_module);
6651
6652/* ixgbe_main.c */
Linux kernel - Deliverables
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