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ixgbe: DCB, remove unneeded ixgbe_dcb_txq_to_tc() routine
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
60127865 38#include <linux/pkt_sched.h>
9a799d71 39#include <linux/ipv6.h>
5a0e3ad6 40#include <linux/slab.h>
9a799d71
AK		 41#include <net/checksum.h>
42#include <net/ip6_checksum.h>
43#include <linux/ethtool.h>
44#include <linux/if_vlan.h>
70c71606 45#include <linux/prefetch.h>
eacd73f7 46#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 47
48#include "ixgbe.h"
49#include "ixgbe_common.h"
ee5f784a 50#include "ixgbe_dcb_82599.h"
1cdd1ec8 51#include "ixgbe_sriov.h"
9a799d71
AK		 52
53char ixgbe_driver_name[] = "ixgbe";
9c8eb720 54static const char ixgbe_driver_string[] =
e8e9f696 55 "Intel(R) 10 Gigabit PCI Express Network Driver";
75e3d3c6 56#define MAJ 3
c89c7112
DS		 57#define MIN 3
58#define BUILD 8
75e3d3c6
JK		 59#define KFIX 2
60#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
61 __stringify(BUILD) "-k" __stringify(KFIX)
9c8eb720 62const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 63static const char ixgbe_copyright[] =
64 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 65
66static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 67 [board_82598] = &ixgbe_82598_info,
e8e26350 68 [board_82599] = &ixgbe_82599_info,
fe15e8e1 69 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 70};
71
72/* ixgbe_pci_tbl - PCI Device ID Table
73 *
74 * Wildcard entries (PCI_ANY_ID) should come last
75 * Last entry must be all 0s
76 *
77 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
78 * Class, Class Mask, private data (not used) }
79 */
a3aa1884 80static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 84 board_82598 },
9a799d71 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 86 board_82598 },
0befdb3e
JB		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
88 board_82598 },
3845bec0
PWJ		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
90 board_82598 },
9a799d71 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 92 board_82598 },
8d792cd9
JB		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
94 board_82598 },
c4900be0
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
96 board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
98 board_82598 },
b95f5fcb
JB		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
100 board_82598 },
c4900be0
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
102 board_82598 },
2f21bdd3
DS		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
104 board_82598 },
e8e26350
PW		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
106 board_82599 },
1fcf03e6
PWJ		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
108 board_82599 },
74757d49
DS		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
110 board_82599 },
e8e26350
PW		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
112 board_82599 },
38ad1c8e
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
114 board_82599 },
dbfec662
DS		 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
116 board_82599 },
8911184f
PWJ		 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
118 board_82599 },
dbffcb21
DS		 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
120 board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
122 board_82599 },
119fc60a
MC		 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
124 board_82599 },
312eb931
DS		 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
126 board_82599 },
b93a2226 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
d994653d 128 board_X540 },
4c40ef02
ET		 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
130 board_82599 },
4f6290cf
DS		 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
132 board_82599 },
9a799d71
AK		 133
134 /* required last entry */
135 {0, }
136};
137MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
138
5dd2d332 139#ifdef CONFIG_IXGBE_DCA
bd0362dd 140static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 141 void *p);
bd0362dd
JC		 142static struct notifier_block dca_notifier = {
143 .notifier_call = ixgbe_notify_dca,
144 .next = NULL,
145 .priority = 0
146};
147#endif
148
1cdd1ec8
GR		 149#ifdef CONFIG_PCI_IOV
150static unsigned int max_vfs;
151module_param(max_vfs, uint, 0);
e8e9f696
JP		 152MODULE_PARM_DESC(max_vfs,
153 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 154#endif /* CONFIG_PCI_IOV */
155
9a799d71
AK		 156MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
157MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
158MODULE_LICENSE("GPL");
159MODULE_VERSION(DRV_VERSION);
160
161#define DEFAULT_DEBUG_LEVEL_SHIFT 3
162
1cdd1ec8
GR		 163static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
164{
165 struct ixgbe_hw *hw = &adapter->hw;
166 u32 gcr;
167 u32 gpie;
168 u32 vmdctl;
169
170#ifdef CONFIG_PCI_IOV
171 /* disable iov and allow time for transactions to clear */
172 pci_disable_sriov(adapter->pdev);
173#endif
174
175 /* turn off device IOV mode */
176 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
177 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
178 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
179 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
180 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
181 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
182
183 /* set default pool back to 0 */
184 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
185 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
186 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
187
188 /* take a breather then clean up driver data */
189 msleep(100);
e8e9f696
JP		 190
191 kfree(adapter->vfinfo);
1cdd1ec8
GR		 192 adapter->vfinfo = NULL;
193
194 adapter->num_vfs = 0;
195 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
196}
197
7086400d
AD		 198static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
199{
200 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
202 schedule_work(&adapter->service_task);
203}
204
205static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
206{
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
208
209 /* flush memory to make sure state is correct before next watchog */
210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
212}
213
dcd79aeb
TI		 214struct ixgbe_reg_info {
215 u32 ofs;
216 char *name;
217};
218
219static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
220
221 /* General Registers */
222 {IXGBE_CTRL, "CTRL"},
223 {IXGBE_STATUS, "STATUS"},
224 {IXGBE_CTRL_EXT, "CTRL_EXT"},
225
226 /* Interrupt Registers */
227 {IXGBE_EICR, "EICR"},
228
229 /* RX Registers */
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
238
239 /* TX Registers */
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
246
247 /* List Terminator */
248 {}
249};
250
251
252/*
253 * ixgbe_regdump - register printout routine
254 */
255static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
256{
257 int i = 0, j = 0;
258 char rname[16];
259 u32 regs[64];
260
261 switch (reginfo->ofs) {
262 case IXGBE_SRRCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
265 break;
266 case IXGBE_DCA_RXCTRL(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
269 break;
270 case IXGBE_RDLEN(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
273 break;
274 case IXGBE_RDH(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
277 break;
278 case IXGBE_RDT(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
281 break;
282 case IXGBE_RXDCTL(0):
283 for (i = 0; i < 64; i++)
284 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
285 break;
286 case IXGBE_RDBAL(0):
287 for (i = 0; i < 64; i++)
288 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
289 break;
290 case IXGBE_RDBAH(0):
291 for (i = 0; i < 64; i++)
292 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
293 break;
294 case IXGBE_TDBAL(0):
295 for (i = 0; i < 64; i++)
296 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
297 break;
298 case IXGBE_TDBAH(0):
299 for (i = 0; i < 64; i++)
300 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
301 break;
302 case IXGBE_TDLEN(0):
303 for (i = 0; i < 64; i++)
304 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
305 break;
306 case IXGBE_TDH(0):
307 for (i = 0; i < 64; i++)
308 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
309 break;
310 case IXGBE_TDT(0):
311 for (i = 0; i < 64; i++)
312 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
313 break;
314 case IXGBE_TXDCTL(0):
315 for (i = 0; i < 64; i++)
316 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
317 break;
318 default:
c7689578 319 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 320 IXGBE_READ_REG(hw, reginfo->ofs));
321 return;
322 }
323
324 for (i = 0; i < 8; i++) {
325 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 326 pr_err("%-15s", rname);
dcd79aeb 327 for (j = 0; j < 8; j++)
c7689578
JP		 328 pr_cont(" %08x", regs[i*8+j]);
329 pr_cont("\n");
dcd79aeb
TI		 330 }
331
332}
333
334/*
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
336 */
337static void ixgbe_dump(struct ixgbe_adapter *adapter)
338{
339 struct net_device *netdev = adapter->netdev;
340 struct ixgbe_hw *hw = &adapter->hw;
341 struct ixgbe_reg_info *reginfo;
342 int n = 0;
343 struct ixgbe_ring *tx_ring;
344 struct ixgbe_tx_buffer *tx_buffer_info;
345 union ixgbe_adv_tx_desc *tx_desc;
346 struct my_u0 { u64 a; u64 b; } *u0;
347 struct ixgbe_ring *rx_ring;
348 union ixgbe_adv_rx_desc *rx_desc;
349 struct ixgbe_rx_buffer *rx_buffer_info;
350 u32 staterr;
351 int i = 0;
352
353 if (!netif_msg_hw(adapter))
354 return;
355
356 /* Print netdevice Info */
357 if (netdev) {
358 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 359 pr_info("Device Name state "
dcd79aeb 360 "trans_start last_rx\n");
c7689578
JP		 361 pr_info("%-15s %016lX %016lX %016lX\n",
362 netdev->name,
363 netdev->state,
364 netdev->trans_start,
365 netdev->last_rx);
dcd79aeb
TI		 366 }
367
368 /* Print Registers */
369 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 370 pr_info(" Register Name Value\n");
dcd79aeb
TI		 371 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
372 reginfo->name; reginfo++) {
373 ixgbe_regdump(hw, reginfo);
374 }
375
376 /* Print TX Ring Summary */
377 if (!netdev || !netif_running(netdev))
378 goto exit;
379
380 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 381 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 382 for (n = 0; n < adapter->num_tx_queues; n++) {
383 tx_ring = adapter->tx_ring[n];
384 tx_buffer_info =
385 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 386 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 387 n, tx_ring->next_to_use, tx_ring->next_to_clean,
388 (u64)tx_buffer_info->dma,
389 tx_buffer_info->length,
390 tx_buffer_info->next_to_watch,
391 (u64)tx_buffer_info->time_stamp);
392 }
393
394 /* Print TX Rings */
395 if (!netif_msg_tx_done(adapter))
396 goto rx_ring_summary;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
399
400 /* Transmit Descriptor Formats
401 *
402 * Advanced Transmit Descriptor
403 * +--------------------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +--------------------------------------------------------------+
406 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
407 * +--------------------------------------------------------------+
408 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
409 */
410
411 for (n = 0; n < adapter->num_tx_queues; n++) {
412 tx_ring = adapter->tx_ring[n];
c7689578
JP		 413 pr_info("------------------------------------\n");
414 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
415 pr_info("------------------------------------\n");
416 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 417 "[PlPOIdStDDt Ln] [bi->dma ] "
418 "leng ntw timestamp bi->skb\n");
419
420 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 421 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 422 tx_buffer_info = &tx_ring->tx_buffer_info[i];
423 u0 = (struct my_u0 *)tx_desc;
c7689578 424 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 425 " %04X %3X %016llX %p", i,
426 le64_to_cpu(u0->a),
427 le64_to_cpu(u0->b),
428 (u64)tx_buffer_info->dma,
429 tx_buffer_info->length,
430 tx_buffer_info->next_to_watch,
431 (u64)tx_buffer_info->time_stamp,
432 tx_buffer_info->skb);
433 if (i == tx_ring->next_to_use &&
434 i == tx_ring->next_to_clean)
c7689578 435 pr_cont(" NTC/U\n");
dcd79aeb 436 else if (i == tx_ring->next_to_use)
c7689578 437 pr_cont(" NTU\n");
dcd79aeb 438 else if (i == tx_ring->next_to_clean)
c7689578 439 pr_cont(" NTC\n");
dcd79aeb 440 else
c7689578 441 pr_cont("\n");
dcd79aeb
TI		 442
443 if (netif_msg_pktdata(adapter) &&
444 tx_buffer_info->dma != 0)
445 print_hex_dump(KERN_INFO, "",
446 DUMP_PREFIX_ADDRESS, 16, 1,
447 phys_to_virt(tx_buffer_info->dma),
448 tx_buffer_info->length, true);
449 }
450 }
451
452 /* Print RX Rings Summary */
453rx_ring_summary:
454 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 455 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 456 for (n = 0; n < adapter->num_rx_queues; n++) {
457 rx_ring = adapter->rx_ring[n];
c7689578
JP		 458 pr_info("%5d %5X %5X\n",
459 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 460 }
461
462 /* Print RX Rings */
463 if (!netif_msg_rx_status(adapter))
464 goto exit;
465
466 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
467
468 /* Advanced Receive Descriptor (Read) Format
469 * 63 1 0
470 * +-----------------------------------------------------+
471 * 0 | Packet Buffer Address [63:1] |A0/NSE|
472 * +----------------------------------------------+------+
473 * 8 | Header Buffer Address [63:1] | DD |
474 * +-----------------------------------------------------+
475 *
476 *
477 * Advanced Receive Descriptor (Write-Back) Format
478 *
479 * 63 48 47 32 31 30 21 20 16 15 4 3 0
480 * +------------------------------------------------------+
481 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
482 * | Checksum Ident | | | | Type | Type |
483 * +------------------------------------------------------+
484 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
485 * +------------------------------------------------------+
486 * 63 48 47 32 31 20 19 0
487 */
488 for (n = 0; n < adapter->num_rx_queues; n++) {
489 rx_ring = adapter->rx_ring[n];
c7689578
JP		 490 pr_info("------------------------------------\n");
491 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
492 pr_info("------------------------------------\n");
493 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 494 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
495 "<-- Adv Rx Read format\n");
c7689578 496 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 497 "[vl er S cks ln] ---------------- [bi->skb] "
498 "<-- Adv Rx Write-Back format\n");
499
500 for (i = 0; i < rx_ring->count; i++) {
501 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 502 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 503 u0 = (struct my_u0 *)rx_desc;
504 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
505 if (staterr & IXGBE_RXD_STAT_DD) {
506 /* Descriptor Done */
c7689578 507 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 508 "%016llX ---------------- %p", i,
509 le64_to_cpu(u0->a),
510 le64_to_cpu(u0->b),
511 rx_buffer_info->skb);
512 } else {
c7689578 513 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 514 "%016llX %016llX %p", i,
515 le64_to_cpu(u0->a),
516 le64_to_cpu(u0->b),
517 (u64)rx_buffer_info->dma,
518 rx_buffer_info->skb);
519
520 if (netif_msg_pktdata(adapter)) {
521 print_hex_dump(KERN_INFO, "",
522 DUMP_PREFIX_ADDRESS, 16, 1,
523 phys_to_virt(rx_buffer_info->dma),
524 rx_ring->rx_buf_len, true);
525
526 if (rx_ring->rx_buf_len
527 < IXGBE_RXBUFFER_2048)
528 print_hex_dump(KERN_INFO, "",
529 DUMP_PREFIX_ADDRESS, 16, 1,
530 phys_to_virt(
531 rx_buffer_info->page_dma +
532 rx_buffer_info->page_offset
533 ),
534 PAGE_SIZE/2, true);
535 }
536 }
537
538 if (i == rx_ring->next_to_use)
c7689578 539 pr_cont(" NTU\n");
dcd79aeb 540 else if (i == rx_ring->next_to_clean)
c7689578 541 pr_cont(" NTC\n");
dcd79aeb 542 else
c7689578 543 pr_cont("\n");
dcd79aeb
TI		 544
545 }
546 }
547
548exit:
549 return;
550}
551
5eba3699
AV		 552static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
553{
554 u32 ctrl_ext;
555
556 /* Let firmware take over control of h/w */
557 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
558 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 559 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 560}
561
562static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
563{
564 u32 ctrl_ext;
565
566 /* Let firmware know the driver has taken over */
567 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
568 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 569 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 570}
9a799d71 571
e8e26350
PW		 572/*
573 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
574 * @adapter: pointer to adapter struct
575 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
576 * @queue: queue to map the corresponding interrupt to
577 * @msix_vector: the vector to map to the corresponding queue
578 *
579 */
580static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 581 u8 queue, u8 msix_vector)
9a799d71
AK		 582{
583 u32 ivar, index;
e8e26350
PW		 584 struct ixgbe_hw *hw = &adapter->hw;
585 switch (hw->mac.type) {
586 case ixgbe_mac_82598EB:
587 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
588 if (direction == -1)
589 direction = 0;
590 index = (((direction * 64) + queue) >> 2) & 0x1F;
591 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
592 ivar &= ~(0xFF << (8 * (queue & 0x3)));
593 ivar |= (msix_vector << (8 * (queue & 0x3)));
594 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
595 break;
596 case ixgbe_mac_82599EB:
b93a2226 597 case ixgbe_mac_X540:
e8e26350
PW		 598 if (direction == -1) {
599 /* other causes */
600 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
601 index = ((queue & 1) * 8);
602 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
603 ivar &= ~(0xFF << index);
604 ivar |= (msix_vector << index);
605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
606 break;
607 } else {
608 /* tx or rx causes */
609 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
610 index = ((16 * (queue & 1)) + (8 * direction));
611 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
612 ivar &= ~(0xFF << index);
613 ivar |= (msix_vector << index);
614 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
615 break;
616 }
617 default:
618 break;
619 }
9a799d71
AK		 620}
621
fe49f04a 622static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 623 u64 qmask)
fe49f04a
AD		 624{
625 u32 mask;
626
bd508178
AD		 627 switch (adapter->hw.mac.type) {
628 case ixgbe_mac_82598EB:
fe49f04a
AD		 629 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
630 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 631 break;
632 case ixgbe_mac_82599EB:
b93a2226 633 case ixgbe_mac_X540:
fe49f04a
AD		 634 mask = (qmask & 0xFFFFFFFF);
635 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
636 mask = (qmask >> 32);
637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 638 break;
639 default:
640 break;
fe49f04a
AD		 641 }
642}
643
b6ec895e
AD		 644void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
645 struct ixgbe_tx_buffer *tx_buffer_info)
9a799d71 646{
e5a43549
AD		 647 if (tx_buffer_info->dma) {
648 if (tx_buffer_info->mapped_as_page)
b6ec895e 649 dma_unmap_page(tx_ring->dev,
e5a43549
AD		 650 tx_buffer_info->dma,
651 tx_buffer_info->length,
1b507730 652 DMA_TO_DEVICE);
e5a43549 653 else
b6ec895e 654 dma_unmap_single(tx_ring->dev,
e5a43549
AD		 655 tx_buffer_info->dma,
656 tx_buffer_info->length,
1b507730 657 DMA_TO_DEVICE);
e5a43549
AD		 658 tx_buffer_info->dma = 0;
659 }
9a799d71
AK		 660 if (tx_buffer_info->skb) {
661 dev_kfree_skb_any(tx_buffer_info->skb);
662 tx_buffer_info->skb = NULL;
663 }
44df32c5 664 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 665 /* tx_buffer_info must be completely set up in the transmit path */
666}
667
c84d324c
JF		 668static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
669{
670 struct ixgbe_hw *hw = &adapter->hw;
671 struct ixgbe_hw_stats *hwstats = &adapter->stats;
672 u32 data = 0;
673 u32 xoff[8] = {0};
674 int i;
675
676 if ((hw->fc.current_mode == ixgbe_fc_full) ||
677 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
678 switch (hw->mac.type) {
679 case ixgbe_mac_82598EB:
680 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 681 break;
682 default:
c84d324c
JF		 683 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
684 }
685 hwstats->lxoffrxc += data;
686
687 /* refill credits (no tx hang) if we received xoff */
688 if (!data)
689 return;
690
691 for (i = 0; i < adapter->num_tx_queues; i++)
692 clear_bit(__IXGBE_HANG_CHECK_ARMED,
693 &adapter->tx_ring[i]->state);
694 return;
695 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
696 return;
697
698 /* update stats for each tc, only valid with PFC enabled */
699 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
700 switch (hw->mac.type) {
701 case ixgbe_mac_82598EB:
702 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 703 break;
c84d324c
JF		 704 default:
705 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 706 }
c84d324c
JF		 707 hwstats->pxoffrxc[i] += xoff[i];
708 }
709
710 /* disarm tx queues that have received xoff frames */
711 for (i = 0; i < adapter->num_tx_queues; i++) {
712 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 713 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 714
715 if (xoff[tc])
716 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 717 }
26f23d82
YZ		 718}
719
c84d324c 720static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 721{
c84d324c
JF		 722 return ring->tx_stats.completed;
723}
724
725static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
726{
727 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 728 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 729
c84d324c
JF		 730 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
731 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
732
733 if (head != tail)
734 return (head < tail) ?
735 tail - head : (tail + ring->count - head);
736
737 return 0;
738}
739
740static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
741{
742 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
743 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
744 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
745 bool ret = false;
746
7d637bcc 747 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 748
749 /*
750 * Check for a hung queue, but be thorough. This verifies
751 * that a transmit has been completed since the previous
752 * check AND there is at least one packet pending. The
753 * ARMED bit is set to indicate a potential hang. The
754 * bit is cleared if a pause frame is received to remove
755 * false hang detection due to PFC or 802.3x frames. By
756 * requiring this to fail twice we avoid races with
757 * pfc clearing the ARMED bit and conditions where we
758 * run the check_tx_hang logic with a transmit completion
759 * pending but without time to complete it yet.
760 */
761 if ((tx_done_old == tx_done) && tx_pending) {
762 /* make sure it is true for two checks in a row */
763 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
764 &tx_ring->state);
765 } else {
766 /* update completed stats and continue */
767 tx_ring->tx_stats.tx_done_old = tx_done;
768 /* reset the countdown */
769 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 770 }
771
c84d324c 772 return ret;
9a799d71
AK		 773}
774
b4617240
PW		 775#define IXGBE_MAX_TXD_PWR 14
776#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 777
778/* Tx Descriptors needed, worst case */
779#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
780 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
781#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 782 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 783
c83c6cbd
AD		 784/**
785 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
786 * @adapter: driver private struct
787 **/
788static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
789{
790
791 /* Do the reset outside of interrupt context */
792 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
793 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
794 ixgbe_service_event_schedule(adapter);
795 }
796}
e01c31a5 797
9a799d71
AK		 798/**
799 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 800 * @q_vector: structure containing interrupt and ring information
e01c31a5 801 * @tx_ring: tx ring to clean
9a799d71 802 **/
fe49f04a 803static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 804 struct ixgbe_ring *tx_ring)
9a799d71 805{
fe49f04a 806 struct ixgbe_adapter *adapter = q_vector->adapter;
12207e49
PWJ		 807 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
808 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5 809 unsigned int total_bytes = 0, total_packets = 0;
b953799e 810 u16 i, eop, count = 0;
9a799d71
AK		 811
812 i = tx_ring->next_to_clean;
12207e49 813 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 814 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 815
816 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 817 (count < tx_ring->work_limit)) {
12207e49 818 bool cleaned = false;
2d0bb1c1 819 rmb(); /* read buffer_info after eop_desc */
12207e49 820 for ( ; !cleaned; count++) {
31f05a2d 821 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 822 tx_buffer_info = &tx_ring->tx_buffer_info[i];
8ad494b0
AD		 823
824 tx_desc->wb.status = 0;
12207e49 825 cleaned = (i == eop);
9a799d71 826
8ad494b0
AD		 827 i++;
828 if (i == tx_ring->count)
829 i = 0;
e01c31a5 830
8ad494b0
AD		 831 if (cleaned && tx_buffer_info->skb) {
832 total_bytes += tx_buffer_info->bytecount;
833 total_packets += tx_buffer_info->gso_segs;
e092be60 834 }
e01c31a5 835
b6ec895e 836 ixgbe_unmap_and_free_tx_resource(tx_ring,
e8e9f696 837 tx_buffer_info);
e01c31a5 838 }
12207e49 839
c84d324c 840 tx_ring->tx_stats.completed++;
12207e49 841 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 842 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 843 }
844
9a799d71 845 tx_ring->next_to_clean = i;
b953799e
AD		 846 tx_ring->total_bytes += total_bytes;
847 tx_ring->total_packets += total_packets;
848 u64_stats_update_begin(&tx_ring->syncp);
849 tx_ring->stats.packets += total_packets;
850 tx_ring->stats.bytes += total_bytes;
851 u64_stats_update_end(&tx_ring->syncp);
852
c84d324c
JF		 853 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
854 /* schedule immediate reset if we believe we hung */
855 struct ixgbe_hw *hw = &adapter->hw;
856 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
857 e_err(drv, "Detected Tx Unit Hang\n"
858 " Tx Queue <%d>\n"
859 " TDH, TDT <%x>, <%x>\n"
860 " next_to_use <%x>\n"
861 " next_to_clean <%x>\n"
862 "tx_buffer_info[next_to_clean]\n"
863 " time_stamp <%lx>\n"
864 " jiffies <%lx>\n",
865 tx_ring->queue_index,
866 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
867 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
868 tx_ring->next_to_use, eop,
869 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
870
871 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
872
873 e_info(probe,
874 "tx hang %d detected on queue %d, resetting adapter\n",
875 adapter->tx_timeout_count + 1, tx_ring->queue_index);
876
b953799e 877 /* schedule immediate reset if we believe we hung */
c83c6cbd 878 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 879
880 /* the adapter is about to reset, no point in enabling stuff */
881 return true;
882 }
9a799d71 883
e092be60 884#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
fc77dc3c 885 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
e8e9f696 886 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 887 /* Make sure that anybody stopping the queue after this
888 * sees the new next_to_clean.
889 */
890 smp_mb();
fc77dc3c 891 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 892 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 893 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 894 ++tx_ring->tx_stats.restart_queue;
30eba97a 895 }
e092be60 896 }
9a799d71 897
807540ba 898 return count < tx_ring->work_limit;
9a799d71
AK		 899}
900
5dd2d332 901#ifdef CONFIG_IXGBE_DCA
bd0362dd 902static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 903 struct ixgbe_ring *rx_ring,
904 int cpu)
bd0362dd 905{
33cf09c9 906 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 907 u32 rxctrl;
33cf09c9
AD		 908 u8 reg_idx = rx_ring->reg_idx;
909
910 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
911 switch (hw->mac.type) {
912 case ixgbe_mac_82598EB:
913 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
914 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
915 break;
916 case ixgbe_mac_82599EB:
b93a2226 917 case ixgbe_mac_X540:
33cf09c9
AD		 918 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
919 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
920 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
921 break;
922 default:
923 break;
bd0362dd 924 }
33cf09c9
AD		 925 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
926 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
927 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 928 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 929}
930
931static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 932 struct ixgbe_ring *tx_ring,
933 int cpu)
bd0362dd 934{
33cf09c9 935 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 936 u32 txctrl;
33cf09c9
AD		 937 u8 reg_idx = tx_ring->reg_idx;
938
939 switch (hw->mac.type) {
940 case ixgbe_mac_82598EB:
941 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
942 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
943 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
944 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 945 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
946 break;
947 case ixgbe_mac_82599EB:
b93a2226 948 case ixgbe_mac_X540:
33cf09c9
AD		 949 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
950 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
951 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
952 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
953 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 954 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
955 break;
956 default:
957 break;
958 }
959}
960
961static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
962{
963 struct ixgbe_adapter *adapter = q_vector->adapter;
bd0362dd 964 int cpu = get_cpu();
33cf09c9
AD		 965 long r_idx;
966 int i;
bd0362dd 967
33cf09c9
AD		 968 if (q_vector->cpu == cpu)
969 goto out_no_update;
970
971 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
972 for (i = 0; i < q_vector->txr_count; i++) {
973 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
974 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
975 r_idx + 1);
bd0362dd 976 }
33cf09c9
AD		 977
978 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
979 for (i = 0; i < q_vector->rxr_count; i++) {
980 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
981 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
982 r_idx + 1);
983 }
984
985 q_vector->cpu = cpu;
986out_no_update:
bd0362dd
JC		 987 put_cpu();
988}
989
990static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
991{
33cf09c9 992 int num_q_vectors;
bd0362dd
JC		 993 int i;
994
995 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
996 return;
997
e35ec126
AD		 998 /* always use CB2 mode, difference is masked in the CB driver */
999 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1000
33cf09c9
AD		 1001 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1002 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1003 else
1004 num_q_vectors = 1;
1005
1006 for (i = 0; i < num_q_vectors; i++) {
1007 adapter->q_vector[i]->cpu = -1;
1008 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1009 }
1010}
1011
1012static int __ixgbe_notify_dca(struct device *dev, void *data)
1013{
c60fbb00 1014 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1015 unsigned long event = *(unsigned long *)data;
1016
33cf09c9
AD		 1017 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1018 return 0;
1019
bd0362dd
JC		 1020 switch (event) {
1021 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1022 /* if we're already enabled, don't do it again */
1023 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1024 break;
652f093f 1025 if (dca_add_requester(dev) == 0) {
96b0e0f6 1026 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1027 ixgbe_setup_dca(adapter);
1028 break;
1029 }
1030 /* Fall Through since DCA is disabled. */
1031 case DCA_PROVIDER_REMOVE:
1032 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1033 dca_remove_requester(dev);
1034 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1035 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1036 }
1037 break;
1038 }
1039
652f093f 1040 return 0;
bd0362dd 1041}
5dd2d332 1042#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 1043
1044static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1045 struct sk_buff *skb)
1046{
1047 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1048}
1049
9a799d71
AK		 1050/**
1051 * ixgbe_receive_skb - Send a completed packet up the stack
1052 * @adapter: board private structure
1053 * @skb: packet to send up
177db6ff
MC		 1054 * @status: hardware indication of status of receive
1055 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1056 * @rx_desc: rx descriptor
9a799d71 1057 **/
78b6f4ce 1058static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1059 struct sk_buff *skb, u8 status,
1060 struct ixgbe_ring *ring,
1061 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1062{
78b6f4ce
HX		 1063 struct ixgbe_adapter *adapter = q_vector->adapter;
1064 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1065 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1066 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1067
f62bbb5e
JG		 1068 if (is_vlan && (tag & VLAN_VID_MASK))
1069 __vlan_hwaccel_put_tag(skb, tag);
1070
1071 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1072 napi_gro_receive(napi, skb);
1073 else
1074 netif_rx(skb);
9a799d71
AK		 1075}
1076
e59bd25d
AV		 1077/**
1078 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1079 * @adapter: address of board private structure
1080 * @status_err: hardware indication of status of receive
1081 * @skb: skb currently being received and modified
1082 **/
9a799d71 1083static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 1084 union ixgbe_adv_rx_desc *rx_desc,
1085 struct sk_buff *skb)
9a799d71 1086{
8bae1b2b
DS		 1087 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1088
bc8acf2c 1089 skb_checksum_none_assert(skb);
9a799d71 1090
712744be
JB		 1091 /* Rx csum disabled */
1092 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1093 return;
e59bd25d
AV		 1094
1095 /* if IP and error */
1096 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1097 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1098 adapter->hw_csum_rx_error++;
1099 return;
1100 }
e59bd25d
AV		 1101
1102 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1103 return;
1104
1105 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1106 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1107
1108 /*
1109 * 82599 errata, UDP frames with a 0 checksum can be marked as
1110 * checksum errors.
1111 */
1112 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1113 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1114 return;
1115
e59bd25d
AV		 1116 adapter->hw_csum_rx_error++;
1117 return;
1118 }
1119
9a799d71 1120 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1121 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1122}
1123
84ea2591 1124static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1125{
1126 /*
1127 * Force memory writes to complete before letting h/w
1128 * know there are new descriptors to fetch. (Only
1129 * applicable for weak-ordered memory model archs,
1130 * such as IA-64).
1131 */
1132 wmb();
84ea2591 1133 writel(val, rx_ring->tail);
e8e26350
PW		 1134}
1135
9a799d71
AK		 1136/**
1137 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1138 * @rx_ring: ring to place buffers on
1139 * @cleaned_count: number of buffers to replace
9a799d71 1140 **/
fc77dc3c 1141void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1142{
9a799d71 1143 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1144 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1145 struct sk_buff *skb;
1146 u16 i = rx_ring->next_to_use;
9a799d71 1147
fc77dc3c
AD		 1148 /* do nothing if no valid netdev defined */
1149 if (!rx_ring->netdev)
1150 return;
1151
9a799d71 1152 while (cleaned_count--) {
31f05a2d 1153 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1154 bi = &rx_ring->rx_buffer_info[i];
1155 skb = bi->skb;
9a799d71 1156
d5f398ed 1157 if (!skb) {
fc77dc3c 1158 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1159 rx_ring->rx_buf_len);
9a799d71 1160 if (!skb) {
5b7da515 1161 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1162 goto no_buffers;
1163 }
d716a7d8
AD		 1164 /* initialize queue mapping */
1165 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1166 bi->skb = skb;
d716a7d8 1167 }
9a799d71 1168
d716a7d8 1169 if (!bi->dma) {
b6ec895e 1170 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1171 skb->data,
e8e9f696 1172 rx_ring->rx_buf_len,
1b507730 1173 DMA_FROM_DEVICE);
b6ec895e 1174 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1175 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1176 bi->dma = 0;
1177 goto no_buffers;
1178 }
9a799d71 1179 }
d5f398ed 1180
7d637bcc 1181 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1182 if (!bi->page) {
fc77dc3c 1183 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1184 if (!bi->page) {
5b7da515 1185 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1186 goto no_buffers;
1187 }
1188 }
1189
1190 if (!bi->page_dma) {
1191 /* use a half page if we're re-using */
1192 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1193 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1194 bi->page,
1195 bi->page_offset,
1196 PAGE_SIZE / 2,
1197 DMA_FROM_DEVICE);
b6ec895e 1198 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1199 bi->page_dma)) {
5b7da515 1200 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1201 bi->page_dma = 0;
1202 goto no_buffers;
1203 }
1204 }
1205
1206 /* Refresh the desc even if buffer_addrs didn't change
1207 * because each write-back erases this info. */
3a581073
JB		 1208 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1209 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1210 } else {
3a581073 1211 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1212 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1213 }
1214
1215 i++;
1216 if (i == rx_ring->count)
1217 i = 0;
9a799d71 1218 }
7c6e0a43 1219
9a799d71
AK		 1220no_buffers:
1221 if (rx_ring->next_to_use != i) {
1222 rx_ring->next_to_use = i;
84ea2591 1223 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1224 }
1225}
1226
c267fc16 1227static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1228{
c267fc16
AD		 1229 /* HW will not DMA in data larger than the given buffer, even if it
1230 * parses the (NFS, of course) header to be larger. In that case, it
1231 * fills the header buffer and spills the rest into the page.
1232 */
1233 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1234 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1235 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1236 if (hlen > IXGBE_RX_HDR_SIZE)
1237 hlen = IXGBE_RX_HDR_SIZE;
1238 return hlen;
7c6e0a43
JB		 1239}
1240
f8212f97
AD		 1241/**
1242 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1243 * @skb: pointer to the last skb in the rsc queue
1244 *
1245 * This function changes a queue full of hw rsc buffers into a completed
1246 * packet. It uses the ->prev pointers to find the first packet and then
1247 * turns it into the frag list owner.
1248 **/
aa80175a 1249static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1250{
1251 unsigned int frag_list_size = 0;
aa80175a 1252 unsigned int skb_cnt = 1;
f8212f97
AD		 1253
1254 while (skb->prev) {
1255 struct sk_buff *prev = skb->prev;
1256 frag_list_size += skb->len;
1257 skb->prev = NULL;
1258 skb = prev;
aa80175a 1259 skb_cnt++;
f8212f97
AD		 1260 }
1261
1262 skb_shinfo(skb)->frag_list = skb->next;
1263 skb->next = NULL;
1264 skb->len += frag_list_size;
1265 skb->data_len += frag_list_size;
1266 skb->truesize += frag_list_size;
aa80175a
AD		 1267 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1268
f8212f97
AD		 1269 return skb;
1270}
1271
aa80175a
AD		 1272static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1273{
1274 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1275 IXGBE_RXDADV_RSCCNT_MASK);
1276}
43634e82 1277
c267fc16 1278static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1279 struct ixgbe_ring *rx_ring,
1280 int *work_done, int work_to_do)
9a799d71 1281{
78b6f4ce 1282 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1283 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1284 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1285 struct sk_buff *skb;
d2f4fbe2 1286 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1287 const int current_node = numa_node_id();
3d8fd385
YZ		 1288#ifdef IXGBE_FCOE
1289 int ddp_bytes = 0;
1290#endif /* IXGBE_FCOE */
c267fc16
AD		 1291 u32 staterr;
1292 u16 i;
1293 u16 cleaned_count = 0;
aa80175a 1294 bool pkt_is_rsc = false;
9a799d71
AK		 1295
1296 i = rx_ring->next_to_clean;
31f05a2d 1297 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1298 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1299
1300 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1301 u32 upper_len = 0;
9a799d71 1302
3c945e5b 1303 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1304
c267fc16
AD		 1305 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1306
9a799d71 1307 skb = rx_buffer_info->skb;
9a799d71 1308 rx_buffer_info->skb = NULL;
c267fc16 1309 prefetch(skb->data);
9a799d71 1310
c267fc16 1311 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1312 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16
AD		 1313
1314 /* if this is a skb from previous receive DMA will be 0 */
21fa4e66 1315 if (rx_buffer_info->dma) {
c267fc16 1316 u16 hlen;
aa80175a 1317 if (pkt_is_rsc &&
c267fc16
AD		 1318 !(staterr & IXGBE_RXD_STAT_EOP) &&
1319 !skb->prev) {
43634e82
MC		 1320 /*
1321 * When HWRSC is enabled, delay unmapping
1322 * of the first packet. It carries the
1323 * header information, HW may still
1324 * access the header after the writeback.
1325 * Only unmap it when EOP is reached
1326 */
e8171aaa 1327 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1328 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1329 } else {
b6ec895e 1330 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1331 rx_buffer_info->dma,
1332 rx_ring->rx_buf_len,
1333 DMA_FROM_DEVICE);
e8171aaa 1334 }
4f57ca6e 1335 rx_buffer_info->dma = 0;
c267fc16
AD		 1336
1337 if (ring_is_ps_enabled(rx_ring)) {
1338 hlen = ixgbe_get_hlen(rx_desc);
1339 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1340 } else {
1341 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1342 }
1343
1344 skb_put(skb, hlen);
1345 } else {
1346 /* assume packet split since header is unmapped */
1347 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1348 }
1349
1350 if (upper_len) {
b6ec895e
AD		 1351 dma_unmap_page(rx_ring->dev,
1352 rx_buffer_info->page_dma,
1353 PAGE_SIZE / 2,
1354 DMA_FROM_DEVICE);
9a799d71
AK		 1355 rx_buffer_info->page_dma = 0;
1356 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1357 rx_buffer_info->page,
1358 rx_buffer_info->page_offset,
1359 upper_len);
762f4c57 1360
c267fc16
AD		 1361 if ((page_count(rx_buffer_info->page) == 1) &&
1362 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1363 get_page(rx_buffer_info->page);
c267fc16
AD		 1364 else
1365 rx_buffer_info->page = NULL;
9a799d71
AK		 1366
1367 skb->len += upper_len;
1368 skb->data_len += upper_len;
1369 skb->truesize += upper_len;
1370 }
1371
1372 i++;
1373 if (i == rx_ring->count)
1374 i = 0;
9a799d71 1375
31f05a2d 1376 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1377 prefetch(next_rxd);
9a799d71 1378 cleaned_count++;
f8212f97 1379
aa80175a 1380 if (pkt_is_rsc) {
f8212f97
AD		 1381 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1382 IXGBE_RXDADV_NEXTP_SHIFT;
1383 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1384 } else {
1385 next_buffer = &rx_ring->rx_buffer_info[i];
1386 }
1387
c267fc16 1388 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1389 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1390 rx_buffer_info->skb = next_buffer->skb;
1391 rx_buffer_info->dma = next_buffer->dma;
1392 next_buffer->skb = skb;
1393 next_buffer->dma = 0;
1394 } else {
1395 skb->next = next_buffer->skb;
1396 skb->next->prev = skb;
1397 }
5b7da515 1398 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1399 goto next_desc;
1400 }
1401
aa80175a
AD		 1402 if (skb->prev) {
1403 skb = ixgbe_transform_rsc_queue(skb);
1404 /* if we got here without RSC the packet is invalid */
1405 if (!pkt_is_rsc) {
1406 __pskb_trim(skb, 0);
1407 rx_buffer_info->skb = skb;
1408 goto next_desc;
1409 }
1410 }
c267fc16
AD		 1411
1412 if (ring_is_rsc_enabled(rx_ring)) {
1413 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1414 dma_unmap_single(rx_ring->dev,
1415 IXGBE_RSC_CB(skb)->dma,
1416 rx_ring->rx_buf_len,
1417 DMA_FROM_DEVICE);
1418 IXGBE_RSC_CB(skb)->dma = 0;
1419 IXGBE_RSC_CB(skb)->delay_unmap = false;
1420 }
aa80175a
AD		 1421 }
1422 if (pkt_is_rsc) {
c267fc16
AD		 1423 if (ring_is_ps_enabled(rx_ring))
1424 rx_ring->rx_stats.rsc_count +=
aa80175a 1425 skb_shinfo(skb)->nr_frags;
c267fc16 1426 else
aa80175a
AD		 1427 rx_ring->rx_stats.rsc_count +=
1428 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1429 rx_ring->rx_stats.rsc_flush++;
1430 }
1431
1432 /* ERR_MASK will only have valid bits if EOP set */
9a799d71 1433 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
c267fc16
AD		 1434 /* trim packet back to size 0 and recycle it */
1435 __pskb_trim(skb, 0);
1436 rx_buffer_info->skb = skb;
9a799d71
AK		 1437 goto next_desc;
1438 }
1439
8bae1b2b 1440 ixgbe_rx_checksum(adapter, rx_desc, skb);
67a74ee2
ET		 1441 if (adapter->netdev->features & NETIF_F_RXHASH)
1442 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1443
1444 /* probably a little skewed due to removing CRC */
1445 total_rx_bytes += skb->len;
1446 total_rx_packets++;
1447
fc77dc3c 1448 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1449#ifdef IXGBE_FCOE
1450 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1451 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1452 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1453 if (!ddp_bytes)
332d4a7d 1454 goto next_desc;
3d8fd385 1455 }
332d4a7d 1456#endif /* IXGBE_FCOE */
fdaff1ce 1457 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1458
1459next_desc:
1460 rx_desc->wb.upper.status_error = 0;
1461
c267fc16
AD		 1462 (*work_done)++;
1463 if (*work_done >= work_to_do)
1464 break;
1465
9a799d71
AK		 1466 /* return some buffers to hardware, one at a time is too slow */
1467 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1468 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1469 cleaned_count = 0;
1470 }
1471
1472 /* use prefetched values */
1473 rx_desc = next_rxd;
9a799d71 1474 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1475 }
1476
9a799d71
AK		 1477 rx_ring->next_to_clean = i;
1478 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1479
1480 if (cleaned_count)
fc77dc3c 1481 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1482
3d8fd385
YZ		 1483#ifdef IXGBE_FCOE
1484 /* include DDPed FCoE data */
1485 if (ddp_bytes > 0) {
1486 unsigned int mss;
1487
fc77dc3c 1488 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1489 sizeof(struct fc_frame_header) -
1490 sizeof(struct fcoe_crc_eof);
1491 if (mss > 512)
1492 mss &= ~511;
1493 total_rx_bytes += ddp_bytes;
1494 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1495 }
1496#endif /* IXGBE_FCOE */
1497
f494e8fa
AV		 1498 rx_ring->total_packets += total_rx_packets;
1499 rx_ring->total_bytes += total_rx_bytes;
c267fc16
AD		 1500 u64_stats_update_begin(&rx_ring->syncp);
1501 rx_ring->stats.packets += total_rx_packets;
1502 rx_ring->stats.bytes += total_rx_bytes;
1503 u64_stats_update_end(&rx_ring->syncp);
9a799d71
AK		 1504}
1505
021230d4 1506static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1507/**
1508 * ixgbe_configure_msix - Configure MSI-X hardware
1509 * @adapter: board private structure
1510 *
1511 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1512 * interrupts.
1513 **/
1514static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1515{
021230d4 1516 struct ixgbe_q_vector *q_vector;
bf29ee6c 1517 int i, q_vectors, v_idx, r_idx;
021230d4 1518 u32 mask;
9a799d71 1519
021230d4 1520 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1521
4df10466
JB		 1522 /*
1523 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1524 * corresponding register.
1525 */
1526 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1527 q_vector = adapter->q_vector[v_idx];
984b3f57 1528 /* XXX for_each_set_bit(...) */
021230d4 1529 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1530 adapter->num_rx_queues);
021230d4
AV		 1531
1532 for (i = 0; i < q_vector->rxr_count; i++) {
bf29ee6c
AD		 1533 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1534 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
021230d4 1535 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1536 adapter->num_rx_queues,
1537 r_idx + 1);
021230d4
AV		 1538 }
1539 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1540 adapter->num_tx_queues);
021230d4
AV		 1541
1542 for (i = 0; i < q_vector->txr_count; i++) {
bf29ee6c
AD		 1543 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1544 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
021230d4 1545 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1546 adapter->num_tx_queues,
1547 r_idx + 1);
021230d4
AV		 1548 }
1549
021230d4 1550 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1551 /* tx only */
1552 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1553 else if (q_vector->rxr_count)
f7554a2b
NS		 1554 /* rx or mixed */
1555 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1556
fe49f04a 1557 ixgbe_write_eitr(q_vector);
b25ebfd2
PW		 1558 /* If Flow Director is enabled, set interrupt affinity */
1559 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1560 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1561 /*
1562 * Allocate the affinity_hint cpumask, assign the mask
1563 * for this vector, and set our affinity_hint for
1564 * this irq.
1565 */
1566 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1567 GFP_KERNEL))
1568 return;
1569 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1570 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1571 q_vector->affinity_mask);
1572 }
9a799d71
AK		 1573 }
1574
bd508178
AD		 1575 switch (adapter->hw.mac.type) {
1576 case ixgbe_mac_82598EB:
e8e26350 1577 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1578 v_idx);
bd508178
AD		 1579 break;
1580 case ixgbe_mac_82599EB:
b93a2226 1581 case ixgbe_mac_X540:
e8e26350 1582 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178
AD		 1583 break;
1584
1585 default:
1586 break;
1587 }
021230d4
AV		 1588 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1589
41fb9248 1590 /* set up to autoclear timer, and the vectors */
021230d4 1591 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1592 if (adapter->num_vfs)
1593 mask &= ~(IXGBE_EIMS_OTHER |
1594 IXGBE_EIMS_MAILBOX |
1595 IXGBE_EIMS_LSC);
1596 else
1597 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1599}
1600
f494e8fa
AV		 1601enum latency_range {
1602 lowest_latency = 0,
1603 low_latency = 1,
1604 bulk_latency = 2,
1605 latency_invalid = 255
1606};
1607
1608/**
1609 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1610 * @adapter: pointer to adapter
1611 * @eitr: eitr setting (ints per sec) to give last timeslice
1612 * @itr_setting: current throttle rate in ints/second
1613 * @packets: the number of packets during this measurement interval
1614 * @bytes: the number of bytes during this measurement interval
1615 *
1616 * Stores a new ITR value based on packets and byte
1617 * counts during the last interrupt. The advantage of per interrupt
1618 * computation is faster updates and more accurate ITR for the current
1619 * traffic pattern. Constants in this function were computed
1620 * based on theoretical maximum wire speed and thresholds were set based
1621 * on testing data as well as attempting to minimize response time
1622 * while increasing bulk throughput.
1623 * this functionality is controlled by the InterruptThrottleRate module
1624 * parameter (see ixgbe_param.c)
1625 **/
1626static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1627 u32 eitr, u8 itr_setting,
1628 int packets, int bytes)
f494e8fa
AV		 1629{
1630 unsigned int retval = itr_setting;
1631 u32 timepassed_us;
1632 u64 bytes_perint;
1633
1634 if (packets == 0)
1635 goto update_itr_done;
1636
1637
1638 /* simple throttlerate management
1639 * 0-20MB/s lowest (100000 ints/s)
1640 * 20-100MB/s low (20000 ints/s)
1641 * 100-1249MB/s bulk (8000 ints/s)
1642 */
1643 /* what was last interrupt timeslice? */
1644 timepassed_us = 1000000/eitr;
1645 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1646
1647 switch (itr_setting) {
1648 case lowest_latency:
1649 if (bytes_perint > adapter->eitr_low)
1650 retval = low_latency;
1651 break;
1652 case low_latency:
1653 if (bytes_perint > adapter->eitr_high)
1654 retval = bulk_latency;
1655 else if (bytes_perint <= adapter->eitr_low)
1656 retval = lowest_latency;
1657 break;
1658 case bulk_latency:
1659 if (bytes_perint <= adapter->eitr_high)
1660 retval = low_latency;
1661 break;
1662 }
1663
1664update_itr_done:
1665 return retval;
1666}
1667
509ee935
JB		 1668/**
1669 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1670 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1671 *
1672 * This function is made to be called by ethtool and by the driver
1673 * when it needs to update EITR registers at runtime. Hardware
1674 * specific quirks/differences are taken care of here.
1675 */
fe49f04a 1676void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1677{
fe49f04a 1678 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1679 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1680 int v_idx = q_vector->v_idx;
1681 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1682
bd508178
AD		 1683 switch (adapter->hw.mac.type) {
1684 case ixgbe_mac_82598EB:
509ee935
JB		 1685 /* must write high and low 16 bits to reset counter */
1686 itr_reg |= (itr_reg << 16);
bd508178
AD		 1687 break;
1688 case ixgbe_mac_82599EB:
b93a2226 1689 case ixgbe_mac_X540:
f8d1dcaf 1690 /*
b93a2226 1691 * 82599 and X540 can support a value of zero, so allow it for
f8d1dcaf
JB		 1692 * max interrupt rate, but there is an errata where it can
1693 * not be zero with RSC
1694 */
1695 if (itr_reg == 8 &&
1696 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1697 itr_reg = 0;
1698
509ee935
JB		 1699 /*
1700 * set the WDIS bit to not clear the timer bits and cause an
1701 * immediate assertion of the interrupt
1702 */
1703 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1704 break;
1705 default:
1706 break;
509ee935
JB		 1707 }
1708 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1709}
1710
f494e8fa
AV		 1711static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1712{
1713 struct ixgbe_adapter *adapter = q_vector->adapter;
125601bf 1714 int i, r_idx;
f494e8fa
AV		 1715 u32 new_itr;
1716 u8 current_itr, ret_itr;
f494e8fa
AV		 1717
1718 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1719 for (i = 0; i < q_vector->txr_count; i++) {
125601bf 1720 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1721 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1722 q_vector->tx_itr,
1723 tx_ring->total_packets,
1724 tx_ring->total_bytes);
f494e8fa
AV		 1725 /* if the result for this queue would decrease interrupt
1726 * rate for this vector then use that result */
30efa5a3 1727 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1728 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1729 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1730 r_idx + 1);
f494e8fa
AV		 1731 }
1732
1733 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1734 for (i = 0; i < q_vector->rxr_count; i++) {
125601bf 1735 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1736 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1737 q_vector->rx_itr,
1738 rx_ring->total_packets,
1739 rx_ring->total_bytes);
f494e8fa
AV		 1740 /* if the result for this queue would decrease interrupt
1741 * rate for this vector then use that result */
30efa5a3 1742 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1743 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1744 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1745 r_idx + 1);
f494e8fa
AV		 1746 }
1747
30efa5a3 1748 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1749
1750 switch (current_itr) {
1751 /* counts and packets in update_itr are dependent on these numbers */
1752 case lowest_latency:
1753 new_itr = 100000;
1754 break;
1755 case low_latency:
1756 new_itr = 20000; /* aka hwitr = ~200 */
1757 break;
1758 case bulk_latency:
1759 default:
1760 new_itr = 8000;
1761 break;
1762 }
1763
1764 if (new_itr != q_vector->eitr) {
fe49f04a 1765 /* do an exponential smoothing */
125601bf 1766 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935
JB		 1767
1768 /* save the algorithm value here, not the smoothed one */
1769 q_vector->eitr = new_itr;
fe49f04a
AD		 1770
1771 ixgbe_write_eitr(q_vector);
f494e8fa 1772 }
f494e8fa
AV		 1773}
1774
119fc60a 1775/**
f0f9778d
AD		 1776 * ixgbe_check_overtemp_subtask - check for over tempurature
1777 * @adapter: pointer to adapter
119fc60a 1778 **/
f0f9778d 1779static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1780{
119fc60a
MC		 1781 struct ixgbe_hw *hw = &adapter->hw;
1782 u32 eicr = adapter->interrupt_event;
1783
f0f9778d 1784 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1785 return;
1786
f0f9778d
AD		 1787 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1788 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1789 return;
1790
1791 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1792
7ca647bd 1793 switch (hw->device_id) {
f0f9778d
AD		 1794 case IXGBE_DEV_ID_82599_T3_LOM:
1795 /*
1796 * Since the warning interrupt is for both ports
1797 * we don't have to check if:
1798 * - This interrupt wasn't for our port.
1799 * - We may have missed the interrupt so always have to
1800 * check if we got a LSC
1801 */
1802 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1803 !(eicr & IXGBE_EICR_LSC))
1804 return;
1805
1806 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1807 u32 autoneg;
1808 bool link_up = false;
7ca647bd 1809
7ca647bd
JP		 1810 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1811
f0f9778d
AD		 1812 if (link_up)
1813 return;
1814 }
1815
1816 /* Check if this is not due to overtemp */
1817 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1818 return;
1819
1820 break;
7ca647bd
JP		 1821 default:
1822 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1823 return;
7ca647bd 1824 break;
119fc60a 1825 }
7ca647bd
JP		 1826 e_crit(drv,
1827 "Network adapter has been stopped because it has over heated. "
1828 "Restart the computer. If the problem persists, "
1829 "power off the system and replace the adapter\n");
f0f9778d
AD		 1830
1831 adapter->interrupt_event = 0;
119fc60a
MC		 1832}
1833
0befdb3e
JB		 1834static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1835{
1836 struct ixgbe_hw *hw = &adapter->hw;
1837
1838 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1839 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1840 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1841 /* write to clear the interrupt */
1842 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1843 }
1844}
cf8280ee 1845
e8e26350
PW		 1846static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1847{
1848 struct ixgbe_hw *hw = &adapter->hw;
1849
73c4b7cd
AD		 1850 if (eicr & IXGBE_EICR_GPI_SDP2) {
1851 /* Clear the interrupt */
1852 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 1853 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1854 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1855 ixgbe_service_event_schedule(adapter);
1856 }
73c4b7cd
AD		 1857 }
1858
e8e26350
PW		 1859 if (eicr & IXGBE_EICR_GPI_SDP1) {
1860 /* Clear the interrupt */
1861 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 1862 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1863 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1864 ixgbe_service_event_schedule(adapter);
1865 }
e8e26350
PW		 1866 }
1867}
1868
cf8280ee
JB		 1869static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1870{
1871 struct ixgbe_hw *hw = &adapter->hw;
1872
1873 adapter->lsc_int++;
1874 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1875 adapter->link_check_timeout = jiffies;
1876 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1877 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1878 IXGBE_WRITE_FLUSH(hw);
93c52dd0 1879 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 1880 }
1881}
1882
9a799d71
AK		 1883static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1884{
1885 struct net_device *netdev = data;
1886 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1887 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1888 u32 eicr;
1889
1890 /*
1891 * Workaround for Silicon errata. Use clear-by-write instead
1892 * of clear-by-read. Reading with EICS will return the
1893 * interrupt causes without clearing, which later be done
1894 * with the write to EICR.
1895 */
1896 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1897 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1898
cf8280ee
JB		 1899 if (eicr & IXGBE_EICR_LSC)
1900 ixgbe_check_lsc(adapter);
d4f80882 1901
1cdd1ec8
GR		 1902 if (eicr & IXGBE_EICR_MAILBOX)
1903 ixgbe_msg_task(adapter);
1904
bd508178
AD		 1905 switch (hw->mac.type) {
1906 case ixgbe_mac_82599EB:
b93a2226 1907 case ixgbe_mac_X540:
c4cf55e5
PWJ		 1908 /* Handle Flow Director Full threshold interrupt */
1909 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 1910 int reinit_count = 0;
c4cf55e5 1911 int i;
c4cf55e5 1912 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 1913 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 1914 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 1915 &ring->state))
1916 reinit_count++;
1917 }
1918 if (reinit_count) {
1919 /* no more flow director interrupts until after init */
1920 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1921 eicr &= ~IXGBE_EICR_FLOW_DIR;
1922 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1923 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1924 }
1925 }
f0f9778d
AD		 1926 ixgbe_check_sfp_event(adapter, eicr);
1927 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1928 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1929 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1930 adapter->interrupt_event = eicr;
1931 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1932 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1933 }
1934 }
bd508178
AD		 1935 break;
1936 default:
1937 break;
c4cf55e5 1938 }
bd508178
AD		 1939
1940 ixgbe_check_fan_failure(adapter, eicr);
1941
7086400d 1942 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 1943 if (!test_bit(__IXGBE_DOWN, &adapter->state))
7086400d
AD		 1944 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1945 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
9a799d71
AK		 1946
1947 return IRQ_HANDLED;
1948}
1949
fe49f04a
AD		 1950static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1951 u64 qmask)
1952{
1953 u32 mask;
bd508178 1954 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1955
bd508178
AD		 1956 switch (hw->mac.type) {
1957 case ixgbe_mac_82598EB:
fe49f04a 1958 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1959 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1960 break;
1961 case ixgbe_mac_82599EB:
b93a2226 1962 case ixgbe_mac_X540:
fe49f04a 1963 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1964 if (mask)
1965 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1966 mask = (qmask >> 32);
bd508178
AD		 1967 if (mask)
1968 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1969 break;
1970 default:
1971 break;
fe49f04a
AD		 1972 }
1973 /* skip the flush */
1974}
1975
1976static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1977 u64 qmask)
fe49f04a
AD		 1978{
1979 u32 mask;
bd508178 1980 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1981
bd508178
AD		 1982 switch (hw->mac.type) {
1983 case ixgbe_mac_82598EB:
fe49f04a 1984 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1985 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1986 break;
1987 case ixgbe_mac_82599EB:
b93a2226 1988 case ixgbe_mac_X540:
fe49f04a 1989 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1990 if (mask)
1991 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1992 mask = (qmask >> 32);
bd508178
AD		 1993 if (mask)
1994 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1995 break;
1996 default:
1997 break;
fe49f04a
AD		 1998 }
1999 /* skip the flush */
2000}
2001
9a799d71
AK		 2002static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
2003{
021230d4
AV		 2004 struct ixgbe_q_vector *q_vector = data;
2005 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2006 struct ixgbe_ring *tx_ring;
021230d4
AV		 2007 int i, r_idx;
2008
2009 if (!q_vector->txr_count)
2010 return IRQ_HANDLED;
2011
2012 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2013 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2014 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 2015 tx_ring->total_bytes = 0;
2016 tx_ring->total_packets = 0;
021230d4 2017 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2018 r_idx + 1);
021230d4 2019 }
9a799d71 2020
9b471446 2021 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 2022 napi_schedule(&q_vector->napi);
2023
9a799d71
AK		 2024 return IRQ_HANDLED;
2025}
2026
021230d4
AV		 2027/**
2028 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2029 * @irq: unused
2030 * @data: pointer to our q_vector struct for this interrupt vector
2031 **/
9a799d71
AK		 2032static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2033{
021230d4
AV		 2034 struct ixgbe_q_vector *q_vector = data;
2035 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2036 struct ixgbe_ring *rx_ring;
021230d4 2037 int r_idx;
30efa5a3 2038 int i;
021230d4 2039
33cf09c9
AD		 2040#ifdef CONFIG_IXGBE_DCA
2041 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2042 ixgbe_update_dca(q_vector);
2043#endif
2044
021230d4 2045 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
33cf09c9 2046 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2047 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 2048 rx_ring->total_bytes = 0;
2049 rx_ring->total_packets = 0;
2050 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2051 r_idx + 1);
30efa5a3
JB		 2052 }
2053
021230d4
AV		 2054 if (!q_vector->rxr_count)
2055 return IRQ_HANDLED;
2056
9b471446 2057 /* EIAM disabled interrupts (on this vector) for us */
288379f0 2058 napi_schedule(&q_vector->napi);
021230d4
AV		 2059
2060 return IRQ_HANDLED;
2061}
2062
2063static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2064{
91281fd3
AD		 2065 struct ixgbe_q_vector *q_vector = data;
2066 struct ixgbe_adapter *adapter = q_vector->adapter;
2067 struct ixgbe_ring *ring;
2068 int r_idx;
2069 int i;
2070
2071 if (!q_vector->txr_count && !q_vector->rxr_count)
2072 return IRQ_HANDLED;
2073
2074 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2075 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2076 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2077 ring->total_bytes = 0;
2078 ring->total_packets = 0;
2079 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2080 r_idx + 1);
91281fd3
AD		 2081 }
2082
2083 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2084 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2085 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 2086 ring->total_bytes = 0;
2087 ring->total_packets = 0;
2088 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2089 r_idx + 1);
91281fd3
AD		 2090 }
2091
9b471446 2092 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2093 napi_schedule(&q_vector->napi);
9a799d71 2094
9a799d71
AK		 2095 return IRQ_HANDLED;
2096}
2097
021230d4
AV		 2098/**
2099 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2100 * @napi: napi struct with our devices info in it
2101 * @budget: amount of work driver is allowed to do this pass, in packets
2102 *
f0848276
JB		 2103 * This function is optimized for cleaning one queue only on a single
2104 * q_vector!!!
021230d4 2105 **/
9a799d71
AK		 2106static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2107{
021230d4 2108 struct ixgbe_q_vector *q_vector =
e8e9f696 2109 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2110 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 2111 struct ixgbe_ring *rx_ring = NULL;
9a799d71 2112 int work_done = 0;
021230d4 2113 long r_idx;
9a799d71 2114
5dd2d332 2115#ifdef CONFIG_IXGBE_DCA
bd0362dd 2116 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2117 ixgbe_update_dca(q_vector);
bd0362dd 2118#endif
9a799d71 2119
33cf09c9
AD		 2120 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2121 rx_ring = adapter->rx_ring[r_idx];
2122
78b6f4ce 2123 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 2124
021230d4
AV		 2125 /* If all Rx work done, exit the polling mode */
2126 if (work_done < budget) {
288379f0 2127 napi_complete(napi);
f7554a2b 2128 if (adapter->rx_itr_setting & 1)
f494e8fa 2129 ixgbe_set_itr_msix(q_vector);
9a799d71 2130 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2131 ixgbe_irq_enable_queues(adapter,
e8e9f696 2132 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 2133 }
2134
2135 return work_done;
2136}
2137
f0848276 2138/**
91281fd3 2139 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 2140 * @napi: napi struct with our devices info in it
2141 * @budget: amount of work driver is allowed to do this pass, in packets
2142 *
2143 * This function will clean more than one rx queue associated with a
2144 * q_vector.
2145 **/
91281fd3 2146static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 2147{
2148 struct ixgbe_q_vector *q_vector =
e8e9f696 2149 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 2150 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 2151 struct ixgbe_ring *ring = NULL;
f0848276
JB		 2152 int work_done = 0, i;
2153 long r_idx;
91281fd3
AD		 2154 bool tx_clean_complete = true;
2155
33cf09c9
AD		 2156#ifdef CONFIG_IXGBE_DCA
2157 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2158 ixgbe_update_dca(q_vector);
2159#endif
2160
91281fd3
AD		 2161 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2162 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2163 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2164 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2165 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2166 r_idx + 1);
91281fd3 2167 }
f0848276
JB		 2168
2169 /* attempt to distribute budget to each queue fairly, but don't allow
2170 * the budget to go below 1 because we'll exit polling */
2171 budget /= (q_vector->rxr_count ?: 1);
2172 budget = max(budget, 1);
2173 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2174 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2175 ring = adapter->rx_ring[r_idx];
91281fd3 2176 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 2177 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2178 r_idx + 1);
f0848276
JB		 2179 }
2180
2181 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 2182 ring = adapter->rx_ring[r_idx];
f0848276 2183 /* If all Rx work done, exit the polling mode */
7f821875 2184 if (work_done < budget) {
288379f0 2185 napi_complete(napi);
f7554a2b 2186 if (adapter->rx_itr_setting & 1)
f0848276
JB		 2187 ixgbe_set_itr_msix(q_vector);
2188 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2189 ixgbe_irq_enable_queues(adapter,
e8e9f696 2190 ((u64)1 << q_vector->v_idx));
f0848276
JB		 2191 return 0;
2192 }
2193
2194 return work_done;
2195}
91281fd3
AD		 2196
2197/**
2198 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2199 * @napi: napi struct with our devices info in it
2200 * @budget: amount of work driver is allowed to do this pass, in packets
2201 *
2202 * This function is optimized for cleaning one queue only on a single
2203 * q_vector!!!
2204 **/
2205static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2206{
2207 struct ixgbe_q_vector *q_vector =
e8e9f696 2208 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2209 struct ixgbe_adapter *adapter = q_vector->adapter;
2210 struct ixgbe_ring *tx_ring = NULL;
2211 int work_done = 0;
2212 long r_idx;
2213
91281fd3
AD		 2214#ifdef CONFIG_IXGBE_DCA
2215 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2216 ixgbe_update_dca(q_vector);
91281fd3
AD		 2217#endif
2218
33cf09c9
AD		 2219 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2220 tx_ring = adapter->tx_ring[r_idx];
2221
91281fd3
AD		 2222 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2223 work_done = budget;
2224
f7554a2b 2225 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2226 if (work_done < budget) {
2227 napi_complete(napi);
f7554a2b 2228 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2229 ixgbe_set_itr_msix(q_vector);
2230 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2231 ixgbe_irq_enable_queues(adapter,
2232 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2233 }
2234
2235 return work_done;
2236}
2237
021230d4 2238static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2239 int r_idx)
021230d4 2240{
7a921c93 2241 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2242 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93
AD		 2243
2244 set_bit(r_idx, q_vector->rxr_idx);
2245 q_vector->rxr_count++;
2274543f 2246 rx_ring->q_vector = q_vector;
021230d4
AV		 2247}
2248
2249static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2250 int t_idx)
021230d4 2251{
7a921c93 2252 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2253 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93
AD		 2254
2255 set_bit(t_idx, q_vector->txr_idx);
2256 q_vector->txr_count++;
2274543f 2257 tx_ring->q_vector = q_vector;
021230d4
AV		 2258}
2259
9a799d71 2260/**
021230d4
AV		 2261 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2262 * @adapter: board private structure to initialize
9a799d71 2263 *
021230d4
AV		 2264 * This function maps descriptor rings to the queue-specific vectors
2265 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2266 * one vector per ring/queue, but on a constrained vector budget, we
2267 * group the rings as "efficiently" as possible. You would add new
2268 * mapping configurations in here.
9a799d71 2269 **/
d0759ebb 2270static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2271{
d0759ebb 2272 int q_vectors;
021230d4
AV		 2273 int v_start = 0;
2274 int rxr_idx = 0, txr_idx = 0;
2275 int rxr_remaining = adapter->num_rx_queues;
2276 int txr_remaining = adapter->num_tx_queues;
2277 int i, j;
2278 int rqpv, tqpv;
2279 int err = 0;
2280
2281 /* No mapping required if MSI-X is disabled. */
2282 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2283 goto out;
9a799d71 2284
d0759ebb
AD		 2285 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2286
021230d4
AV		 2287 /*
2288 * The ideal configuration...
2289 * We have enough vectors to map one per queue.
2290 */
d0759ebb 2291 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
021230d4
AV		 2292 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2293 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2294
021230d4
AV		 2295 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2296 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2297
9a799d71 2298 goto out;
021230d4 2299 }
9a799d71 2300
021230d4
AV		 2301 /*
2302 * If we don't have enough vectors for a 1-to-1
2303 * mapping, we'll have to group them so there are
2304 * multiple queues per vector.
2305 */
2306 /* Re-adjusting *qpv takes care of the remainder. */
d0759ebb
AD		 2307 for (i = v_start; i < q_vectors; i++) {
2308 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
021230d4
AV		 2309 for (j = 0; j < rqpv; j++) {
2310 map_vector_to_rxq(adapter, i, rxr_idx);
2311 rxr_idx++;
2312 rxr_remaining--;
2313 }
d0759ebb 2314 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
021230d4
AV		 2315 for (j = 0; j < tqpv; j++) {
2316 map_vector_to_txq(adapter, i, txr_idx);
2317 txr_idx++;
2318 txr_remaining--;
9a799d71 2319 }
9a799d71 2320 }
021230d4
AV		 2321out:
2322 return err;
2323}
2324
2325/**
2326 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2327 * @adapter: board private structure
2328 *
2329 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2330 * interrupts from the kernel.
2331 **/
2332static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2333{
2334 struct net_device *netdev = adapter->netdev;
2335 irqreturn_t (*handler)(int, void *);
2336 int i, vector, q_vectors, err;
e8e9f696 2337 int ri = 0, ti = 0;
021230d4
AV		 2338
2339 /* Decrement for Other and TCP Timer vectors */
2340 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2341
d0759ebb 2342 err = ixgbe_map_rings_to_vectors(adapter);
021230d4 2343 if (err)
d0759ebb 2344 return err;
021230d4 2345
d0759ebb
AD		 2346#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2347 ? &ixgbe_msix_clean_many : \
2348 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2349 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2350 NULL)
021230d4 2351 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb
AD		 2352 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2353 handler = SET_HANDLER(q_vector);
cb13fc20 2354
e8e9f696 2355 if (handler == &ixgbe_msix_clean_rx) {
9fe93afd
DS		 2356 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2357 "%s-%s-%d", netdev->name, "rx", ri++);
e8e9f696 2358 } else if (handler == &ixgbe_msix_clean_tx) {
9fe93afd
DS		 2359 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2360 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb 2361 } else if (handler == &ixgbe_msix_clean_many) {
9fe93afd
DS		 2362 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2363 "%s-%s-%d", netdev->name, "TxRx", ri++);
32aa77a4 2364 ti++;
d0759ebb
AD		 2365 } else {
2366 /* skip this unused q_vector */
2367 continue;
32aa77a4 2368 }
021230d4 2369 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb
AD		 2370 handler, 0, q_vector->name,
2371 q_vector);
9a799d71 2372 if (err) {
396e799c 2373 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2374 "Error: %d\n", err);
021230d4 2375 goto free_queue_irqs;
9a799d71 2376 }
9a799d71
AK		 2377 }
2378
d0759ebb 2379 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
021230d4 2380 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb 2381 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
9a799d71 2382 if (err) {
396e799c 2383 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2384 goto free_queue_irqs;
9a799d71
AK		 2385 }
2386
9a799d71
AK		 2387 return 0;
2388
021230d4
AV		 2389free_queue_irqs:
2390 for (i = vector - 1; i >= 0; i--)
2391 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2392 adapter->q_vector[i]);
021230d4
AV		 2393 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2394 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2395 kfree(adapter->msix_entries);
2396 adapter->msix_entries = NULL;
9a799d71
AK		 2397 return err;
2398}
2399
f494e8fa
AV		 2400static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2401{
7a921c93 2402 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
4a0b9ca0
PW		 2403 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2404 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
125601bf
AD		 2405 u32 new_itr = q_vector->eitr;
2406 u8 current_itr;
f494e8fa 2407
30efa5a3 2408 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2409 q_vector->tx_itr,
2410 tx_ring->total_packets,
2411 tx_ring->total_bytes);
30efa5a3 2412 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2413 q_vector->rx_itr,
2414 rx_ring->total_packets,
2415 rx_ring->total_bytes);
f494e8fa 2416
30efa5a3 2417 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2418
2419 switch (current_itr) {
2420 /* counts and packets in update_itr are dependent on these numbers */
2421 case lowest_latency:
2422 new_itr = 100000;
2423 break;
2424 case low_latency:
2425 new_itr = 20000; /* aka hwitr = ~200 */
2426 break;
2427 case bulk_latency:
2428 new_itr = 8000;
2429 break;
2430 default:
2431 break;
2432 }
2433
2434 if (new_itr != q_vector->eitr) {
fe49f04a 2435 /* do an exponential smoothing */
125601bf 2436 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935 2437
125601bf 2438 /* save the algorithm value here */
509ee935 2439 q_vector->eitr = new_itr;
fe49f04a
AD		 2440
2441 ixgbe_write_eitr(q_vector);
f494e8fa 2442 }
f494e8fa
AV		 2443}
2444
79aefa45
AD		 2445/**
2446 * ixgbe_irq_enable - Enable default interrupt generation settings
2447 * @adapter: board private structure
2448 **/
6af3b9eb
ET		 2449static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2450 bool flush)
79aefa45
AD		 2451{
2452 u32 mask;
835462fc
NS		 2453
2454 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2455 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2456 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2457 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2458 mask |= IXGBE_EIMS_GPI_SDP1;
bd508178
AD		 2459 switch (adapter->hw.mac.type) {
2460 case ixgbe_mac_82599EB:
b93a2226 2461 case ixgbe_mac_X540:
2a41ff81 2462 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2463 mask |= IXGBE_EIMS_GPI_SDP1;
2464 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2465 if (adapter->num_vfs)
2466 mask |= IXGBE_EIMS_MAILBOX;
bd508178
AD		 2467 break;
2468 default:
2469 break;
e8e26350 2470 }
c4cf55e5
PWJ		 2471 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2472 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2473 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2474
79aefa45 2475 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2476 if (queues)
2477 ixgbe_irq_enable_queues(adapter, ~0);
2478 if (flush)
2479 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2480
2481 if (adapter->num_vfs > 32) {
2482 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2483 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2484 }
79aefa45 2485}
021230d4 2486
9a799d71 2487/**
021230d4 2488 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2489 * @irq: interrupt number
2490 * @data: pointer to a network interface device structure
9a799d71
AK		 2491 **/
2492static irqreturn_t ixgbe_intr(int irq, void *data)
2493{
2494 struct net_device *netdev = data;
2495 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2496 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2497 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2498 u32 eicr;
2499
54037505 2500 /*
6af3b9eb 2501 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2502 * before the read of EICR.
2503 */
2504 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2505
021230d4
AV		 2506 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2507 * therefore no explict interrupt disable is necessary */
2508 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2509 if (!eicr) {
6af3b9eb
ET		 2510 /*
2511 * shared interrupt alert!
f47cf66e 2512 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2513 * have disabled interrupts due to EIAM
2514 * finish the workaround of silicon errata on 82598. Unmask
2515 * the interrupt that we masked before the EICR read.
2516 */
2517 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2518 ixgbe_irq_enable(adapter, true, true);
9a799d71 2519 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2520 }
9a799d71 2521
cf8280ee
JB		 2522 if (eicr & IXGBE_EICR_LSC)
2523 ixgbe_check_lsc(adapter);
021230d4 2524
bd508178
AD		 2525 switch (hw->mac.type) {
2526 case ixgbe_mac_82599EB:
e8e26350 2527 ixgbe_check_sfp_event(adapter, eicr);
bd508178
AD		 2528 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2529 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
f0f9778d
AD		 2530 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2531 adapter->interrupt_event = eicr;
2532 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2533 ixgbe_service_event_schedule(adapter);
2534 }
bd508178
AD		 2535 }
2536 break;
2537 default:
2538 break;
2539 }
e8e26350 2540
0befdb3e
JB		 2541 ixgbe_check_fan_failure(adapter, eicr);
2542
7a921c93 2543 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2544 adapter->tx_ring[0]->total_packets = 0;
2545 adapter->tx_ring[0]->total_bytes = 0;
2546 adapter->rx_ring[0]->total_packets = 0;
2547 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2548 /* would disable interrupts here but EIAM disabled it */
7a921c93 2549 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2550 }
2551
6af3b9eb
ET		 2552 /*
2553 * re-enable link(maybe) and non-queue interrupts, no flush.
2554 * ixgbe_poll will re-enable the queue interrupts
2555 */
2556
2557 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2558 ixgbe_irq_enable(adapter, false, false);
2559
9a799d71
AK		 2560 return IRQ_HANDLED;
2561}
2562
021230d4
AV		 2563static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2564{
2565 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2566
2567 for (i = 0; i < q_vectors; i++) {
7a921c93 2568 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2569 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2570 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2571 q_vector->rxr_count = 0;
2572 q_vector->txr_count = 0;
2573 }
2574}
2575
9a799d71
AK		 2576/**
2577 * ixgbe_request_irq - initialize interrupts
2578 * @adapter: board private structure
2579 *
2580 * Attempts to configure interrupts using the best available
2581 * capabilities of the hardware and kernel.
2582 **/
021230d4 2583static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2584{
2585 struct net_device *netdev = adapter->netdev;
021230d4 2586 int err;
9a799d71 2587
021230d4
AV		 2588 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2589 err = ixgbe_request_msix_irqs(adapter);
2590 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2591 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2592 netdev->name, netdev);
021230d4 2593 } else {
a0607fd3 2594 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2595 netdev->name, netdev);
9a799d71
AK		 2596 }
2597
9a799d71 2598 if (err)
396e799c 2599 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2600
9a799d71
AK		 2601 return err;
2602}
2603
2604static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2605{
2606 struct net_device *netdev = adapter->netdev;
2607
2608 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2609 int i, q_vectors;
9a799d71 2610
021230d4
AV		 2611 q_vectors = adapter->num_msix_vectors;
2612
2613 i = q_vectors - 1;
9a799d71 2614 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2615
021230d4
AV		 2616 i--;
2617 for (; i >= 0; i--) {
894ff7cf
AD		 2618 /* free only the irqs that were actually requested */
2619 if (!adapter->q_vector[i]->rxr_count &&
2620 !adapter->q_vector[i]->txr_count)
2621 continue;
2622
021230d4 2623 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2624 adapter->q_vector[i]);
021230d4
AV		 2625 }
2626
2627 ixgbe_reset_q_vectors(adapter);
2628 } else {
2629 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2630 }
2631}
2632
22d5a71b
JB		 2633/**
2634 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2635 * @adapter: board private structure
2636 **/
2637static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2638{
bd508178
AD		 2639 switch (adapter->hw.mac.type) {
2640 case ixgbe_mac_82598EB:
835462fc 2641 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2642 break;
2643 case ixgbe_mac_82599EB:
b93a2226 2644 case ixgbe_mac_X540:
835462fc
NS		 2645 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2646 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2647 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2648 if (adapter->num_vfs > 32)
2649 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
bd508178
AD		 2650 break;
2651 default:
2652 break;
22d5a71b
JB		 2653 }
2654 IXGBE_WRITE_FLUSH(&adapter->hw);
2655 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2656 int i;
2657 for (i = 0; i < adapter->num_msix_vectors; i++)
2658 synchronize_irq(adapter->msix_entries[i].vector);
2659 } else {
2660 synchronize_irq(adapter->pdev->irq);
2661 }
2662}
2663
9a799d71
AK		 2664/**
2665 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2666 *
2667 **/
2668static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2669{
9a799d71
AK		 2670 struct ixgbe_hw *hw = &adapter->hw;
2671
021230d4 2672 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2673 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2674
e8e26350
PW		 2675 ixgbe_set_ivar(adapter, 0, 0, 0);
2676 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2677
2678 map_vector_to_rxq(adapter, 0, 0);
2679 map_vector_to_txq(adapter, 0, 0);
2680
396e799c 2681 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2682}
2683
43e69bf0
AD		 2684/**
2685 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2686 * @adapter: board private structure
2687 * @ring: structure containing ring specific data
2688 *
2689 * Configure the Tx descriptor ring after a reset.
2690 **/
84418e3b
AD		 2691void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2692 struct ixgbe_ring *ring)
43e69bf0
AD		 2693{
2694 struct ixgbe_hw *hw = &adapter->hw;
2695 u64 tdba = ring->dma;
2f1860b8
AD		 2696 int wait_loop = 10;
2697 u32 txdctl;
bf29ee6c 2698 u8 reg_idx = ring->reg_idx;
43e69bf0 2699
2f1860b8
AD		 2700 /* disable queue to avoid issues while updating state */
2701 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2702 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2703 txdctl & ~IXGBE_TXDCTL_ENABLE);
2704 IXGBE_WRITE_FLUSH(hw);
2705
43e69bf0 2706 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2707 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2708 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2709 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2710 ring->count * sizeof(union ixgbe_adv_tx_desc));
2711 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2712 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2713 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2714
2f1860b8
AD		 2715 /* configure fetching thresholds */
2716 if (adapter->rx_itr_setting == 0) {
2717 /* cannot set wthresh when itr==0 */
2718 txdctl &= ~0x007F0000;
2719 } else {
2720 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2721 txdctl |= (8 << 16);
2722 }
2723 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2724 /* PThresh workaround for Tx hang with DFP enabled. */
2725 txdctl |= 32;
2726 }
2727
2728 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2729 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2730 adapter->atr_sample_rate) {
2731 ring->atr_sample_rate = adapter->atr_sample_rate;
2732 ring->atr_count = 0;
2733 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2734 } else {
2735 ring->atr_sample_rate = 0;
2736 }
2f1860b8 2737
c84d324c
JF		 2738 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2739
2f1860b8
AD		 2740 /* enable queue */
2741 txdctl |= IXGBE_TXDCTL_ENABLE;
2742 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2743
2744 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2745 if (hw->mac.type == ixgbe_mac_82598EB &&
2746 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2747 return;
2748
2749 /* poll to verify queue is enabled */
2750 do {
032b4325 2751 usleep_range(1000, 2000);
2f1860b8
AD		 2752 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2753 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2754 if (!wait_loop)
2755 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2756}
2757
120ff942
AD		 2758static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2759{
2760 struct ixgbe_hw *hw = &adapter->hw;
2761 u32 rttdcs;
72a32f1f 2762 u32 reg;
8b1c0b24 2763 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2764
2765 if (hw->mac.type == ixgbe_mac_82598EB)
2766 return;
2767
2768 /* disable the arbiter while setting MTQC */
2769 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2770 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2771 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2772
2773 /* set transmit pool layout */
8b1c0b24 2774 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2775 case (IXGBE_FLAG_SRIOV_ENABLED):
2776 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2777 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2778 break;
8b1c0b24
JF		 2779 default:
2780 if (!tcs)
2781 reg = IXGBE_MTQC_64Q_1PB;
2782 else if (tcs <= 4)
2783 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2784 else
2785 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2786
8b1c0b24 2787 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2788
8b1c0b24
JF		 2789 /* Enable Security TX Buffer IFG for multiple pb */
2790 if (tcs) {
2791 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2792 reg |= IXGBE_SECTX_DCB;
2793 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2794 }
120ff942
AD		 2795 break;
2796 }
2797
2798 /* re-enable the arbiter */
2799 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2800 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2801}
2802
9a799d71 2803/**
3a581073 2804 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2805 * @adapter: board private structure
2806 *
2807 * Configure the Tx unit of the MAC after a reset.
2808 **/
2809static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2810{
2f1860b8
AD		 2811 struct ixgbe_hw *hw = &adapter->hw;
2812 u32 dmatxctl;
43e69bf0 2813 u32 i;
9a799d71 2814
2f1860b8
AD		 2815 ixgbe_setup_mtqc(adapter);
2816
2817 if (hw->mac.type != ixgbe_mac_82598EB) {
2818 /* DMATXCTL.EN must be before Tx queues are enabled */
2819 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2820 dmatxctl |= IXGBE_DMATXCTL_TE;
2821 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2822 }
2823
9a799d71 2824 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2825 for (i = 0; i < adapter->num_tx_queues; i++)
2826 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2827}
2828
e8e26350 2829#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2830
a6616b42 2831static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2832 struct ixgbe_ring *rx_ring)
cc41ac7c 2833{
cc41ac7c 2834 u32 srrctl;
bf29ee6c 2835 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2836
bd508178
AD		 2837 switch (adapter->hw.mac.type) {
2838 case ixgbe_mac_82598EB: {
2839 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2840 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2841 reg_idx = reg_idx & mask;
cc41ac7c 2842 }
bd508178
AD		 2843 break;
2844 case ixgbe_mac_82599EB:
b93a2226 2845 case ixgbe_mac_X540:
bd508178
AD		 2846 default:
2847 break;
2848 }
2849
bf29ee6c 2850 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2851
2852 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2853 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2854 if (adapter->num_vfs)
2855 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2856
afafd5b0
AD		 2857 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2858 IXGBE_SRRCTL_BSIZEHDR_MASK;
2859
7d637bcc 2860 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2861#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2862 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2863#else
2864 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2865#endif
cc41ac7c 2866 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2867 } else {
afafd5b0
AD		 2868 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2869 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2870 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2871 }
e8e26350 2872
bf29ee6c 2873 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2874}
9a799d71 2875
05abb126 2876static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2877{
05abb126
AD		 2878 struct ixgbe_hw *hw = &adapter->hw;
2879 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2880 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2881 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2882 u32 mrqc = 0, reta = 0;
2883 u32 rxcsum;
2884 int i, j;
8b1c0b24 2885 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2886 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2887
2888 if (tcs)
2889 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2890
05abb126
AD		 2891 /* Fill out hash function seeds */
2892 for (i = 0; i < 10; i++)
2893 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2894
2895 /* Fill out redirection table */
2896 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2897 if (j == maxq)
05abb126
AD		 2898 j = 0;
2899 /* reta = 4-byte sliding window of
2900 * 0x00..(indices-1)(indices-1)00..etc. */
2901 reta = (reta << 8) | (j * 0x11);
2902 if ((i & 3) == 3)
2903 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2904 }
0cefafad 2905
05abb126
AD		 2906 /* Disable indicating checksum in descriptor, enables RSS hash */
2907 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2908 rxcsum |= IXGBE_RXCSUM_PCSD;
2909 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2910
8b1c0b24
JF		 2911 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2912 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2913 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2914 } else {
2915 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2916 | IXGBE_FLAG_SRIOV_ENABLED);
2917
2918 switch (mask) {
2919 case (IXGBE_FLAG_RSS_ENABLED):
2920 if (!tcs)
2921 mrqc = IXGBE_MRQC_RSSEN;
2922 else if (tcs <= 4)
2923 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2924 else
2925 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2926 break;
2927 case (IXGBE_FLAG_SRIOV_ENABLED):
2928 mrqc = IXGBE_MRQC_VMDQEN;
2929 break;
2930 default:
2931 break;
2932 }
0cefafad
JB		 2933 }
2934
05abb126
AD		 2935 /* Perform hash on these packet types */
2936 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2937 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2938 | IXGBE_MRQC_RSS_FIELD_IPV6
2939 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2940
2941 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2942}
2943
b93a2226
DS		 2944/**
2945 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2946 * @adapter: address of board private structure
2947 * @ring: structure containing ring specific data
2948 **/
2949void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2950 struct ixgbe_ring *ring)
2951{
2952 struct ixgbe_hw *hw = &adapter->hw;
2953 u32 rscctrl;
2954 u8 reg_idx = ring->reg_idx;
2955
2956 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2957 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2958 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2959}
2960
bb5a9ad2
NS		 2961/**
2962 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2963 * @adapter: address of board private structure
2964 * @index: index of ring to set
bb5a9ad2 2965 **/
b93a2226 2966void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2967 struct ixgbe_ring *ring)
bb5a9ad2 2968{
bb5a9ad2 2969 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2970 u32 rscctrl;
edd2ea55 2971 int rx_buf_len;
bf29ee6c 2972 u8 reg_idx = ring->reg_idx;
7367096a 2973
7d637bcc 2974 if (!ring_is_rsc_enabled(ring))
7367096a 2975 return;
bb5a9ad2 2976
7367096a
AD		 2977 rx_buf_len = ring->rx_buf_len;
2978 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2979 rscctrl |= IXGBE_RSCCTL_RSCEN;
2980 /*
2981 * we must limit the number of descriptors so that the
2982 * total size of max desc * buf_len is not greater
2983 * than 65535
2984 */
7d637bcc 2985 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2986#if (MAX_SKB_FRAGS > 16)
2987 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2988#elif (MAX_SKB_FRAGS > 8)
2989 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2990#elif (MAX_SKB_FRAGS > 4)
2991 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2992#else
2993 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2994#endif
2995 } else {
2996 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2997 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2998 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2999 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
3000 else
3001 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
3002 }
7367096a 3003 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3004}
3005
9e10e045
AD		 3006/**
3007 * ixgbe_set_uta - Set unicast filter table address
3008 * @adapter: board private structure
3009 *
3010 * The unicast table address is a register array of 32-bit registers.
3011 * The table is meant to be used in a way similar to how the MTA is used
3012 * however due to certain limitations in the hardware it is necessary to
3013 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
3014 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
3015 **/
3016static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
3017{
3018 struct ixgbe_hw *hw = &adapter->hw;
3019 int i;
3020
3021 /* The UTA table only exists on 82599 hardware and newer */
3022 if (hw->mac.type < ixgbe_mac_82599EB)
3023 return;
3024
3025 /* we only need to do this if VMDq is enabled */
3026 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3027 return;
3028
3029 for (i = 0; i < 128; i++)
3030 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3031}
3032
3033#define IXGBE_MAX_RX_DESC_POLL 10
3034static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3035 struct ixgbe_ring *ring)
3036{
3037 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3038 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3039 u32 rxdctl;
bf29ee6c 3040 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3041
3042 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3043 if (hw->mac.type == ixgbe_mac_82598EB &&
3044 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3045 return;
3046
3047 do {
032b4325 3048 usleep_range(1000, 2000);
9e10e045
AD		 3049 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3050 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3051
3052 if (!wait_loop) {
3053 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3054 "the polling period\n", reg_idx);
3055 }
3056}
3057
2d39d576
YZ		 3058void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3059 struct ixgbe_ring *ring)
3060{
3061 struct ixgbe_hw *hw = &adapter->hw;
3062 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3063 u32 rxdctl;
3064 u8 reg_idx = ring->reg_idx;
3065
3066 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3067 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3068
3069 /* write value back with RXDCTL.ENABLE bit cleared */
3070 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3071
3072 if (hw->mac.type == ixgbe_mac_82598EB &&
3073 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3074 return;
3075
3076 /* the hardware may take up to 100us to really disable the rx queue */
3077 do {
3078 udelay(10);
3079 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3080 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3081
3082 if (!wait_loop) {
3083 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3084 "the polling period\n", reg_idx);
3085 }
3086}
3087
84418e3b
AD		 3088void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3089 struct ixgbe_ring *ring)
acd37177
AD		 3090{
3091 struct ixgbe_hw *hw = &adapter->hw;
3092 u64 rdba = ring->dma;
9e10e045 3093 u32 rxdctl;
bf29ee6c 3094 u8 reg_idx = ring->reg_idx;
acd37177 3095
9e10e045
AD		 3096 /* disable queue to avoid issues while updating state */
3097 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3098 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3099
acd37177
AD		 3100 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3101 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3102 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3103 ring->count * sizeof(union ixgbe_adv_rx_desc));
3104 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3105 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3106 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3107
3108 ixgbe_configure_srrctl(adapter, ring);
3109 ixgbe_configure_rscctl(adapter, ring);
3110
e9f98072
GR		 3111 /* If operating in IOV mode set RLPML for X540 */
3112 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3113 hw->mac.type == ixgbe_mac_X540) {
3114 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3115 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3116 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3117 }
3118
9e10e045
AD		 3119 if (hw->mac.type == ixgbe_mac_82598EB) {
3120 /*
3121 * enable cache line friendly hardware writes:
3122 * PTHRESH=32 descriptors (half the internal cache),
3123 * this also removes ugly rx_no_buffer_count increment
3124 * HTHRESH=4 descriptors (to minimize latency on fetch)
3125 * WTHRESH=8 burst writeback up to two cache lines
3126 */
3127 rxdctl &= ~0x3FFFFF;
3128 rxdctl |= 0x080420;
3129 }
3130
3131 /* enable receive descriptor ring */
3132 rxdctl |= IXGBE_RXDCTL_ENABLE;
3133 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3134
3135 ixgbe_rx_desc_queue_enable(adapter, ring);
fc77dc3c 3136 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 3137}
3138
48654521
AD		 3139static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3140{
3141 struct ixgbe_hw *hw = &adapter->hw;
3142 int p;
3143
3144 /* PSRTYPE must be initialized in non 82598 adapters */
3145 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3146 IXGBE_PSRTYPE_UDPHDR |
3147 IXGBE_PSRTYPE_IPV4HDR |
48654521 3148 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3149 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3150
3151 if (hw->mac.type == ixgbe_mac_82598EB)
3152 return;
3153
3154 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3155 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3156
3157 for (p = 0; p < adapter->num_rx_pools; p++)
3158 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3159 psrtype);
3160}
3161
f5b4a52e
AD		 3162static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3163{
3164 struct ixgbe_hw *hw = &adapter->hw;
3165 u32 gcr_ext;
3166 u32 vt_reg_bits;
3167 u32 reg_offset, vf_shift;
3168 u32 vmdctl;
3169
3170 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3171 return;
3172
3173 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3174 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3175 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3176 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3177
3178 vf_shift = adapter->num_vfs % 32;
3179 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3180
3181 /* Enable only the PF's pool for Tx/Rx */
3182 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3183 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3184 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3185 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3186 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3187
3188 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3189 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3190
3191 /*
3192 * Set up VF register offsets for selected VT Mode,
3193 * i.e. 32 or 64 VFs for SR-IOV
3194 */
3195 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3196 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3197 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3198 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3199
3200 /* enable Tx loopback for VF/PF communication */
3201 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 3202 /* Enable MAC Anti-Spoofing */
a1cbb15c
GR		 3203 hw->mac.ops.set_mac_anti_spoofing(hw,
3204 (adapter->antispoofing_enabled =
3205 (adapter->num_vfs != 0)),
a985b6c3 3206 adapter->num_vfs);
f5b4a52e
AD		 3207}
3208
477de6ed 3209static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3210{
9a799d71
AK		 3211 struct ixgbe_hw *hw = &adapter->hw;
3212 struct net_device *netdev = adapter->netdev;
3213 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3214 int rx_buf_len;
477de6ed
AD		 3215 struct ixgbe_ring *rx_ring;
3216 int i;
3217 u32 mhadd, hlreg0;
48654521 3218
9a799d71 3219 /* Decide whether to use packet split mode or not */
a124339a
DS		 3220 /* On by default */
3221 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3222
1cdd1ec8 3223 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 3224 if (adapter->num_vfs)
3225 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3226
3227 /* Disable packet split due to 82599 erratum #45 */
3228 if (hw->mac.type == ixgbe_mac_82599EB)
3229 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 3230
3231 /* Set the RX buffer length according to the mode */
3232 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 3233 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 3234 } else {
0c19d6af 3235 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 3236 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 3237 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 3238 else
477de6ed 3239 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 3240 }
3241
63f39bd1 3242#ifdef IXGBE_FCOE
477de6ed
AD		 3243 /* adjust max frame to be able to do baby jumbo for FCoE */
3244 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3245 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3246 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3247
477de6ed
AD		 3248#endif /* IXGBE_FCOE */
3249 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3250 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3251 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3252 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3253
3254 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3255 }
3256
3257 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3258 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3259 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3260 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3261
0cefafad
JB		 3262 /*
3263 * Setup the HW Rx Head and Tail Descriptor Pointers and
3264 * the Base and Length of the Rx Descriptor Ring
3265 */
9a799d71 3266 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3267 rx_ring = adapter->rx_ring[i];
a6616b42 3268 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3269
6e455b89 3270 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3271 set_ring_ps_enabled(rx_ring);
3272 else
3273 clear_ring_ps_enabled(rx_ring);
3274
3275 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3276 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3277 else
7d637bcc 3278 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3279
63f39bd1 3280#ifdef IXGBE_FCOE
e8e9f696 3281 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3282 struct ixgbe_ring_feature *f;
3283 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3284 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3285 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3286 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3287 rx_ring->rx_buf_len =
e8e9f696 3288 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3289 } else if (!ring_is_rsc_enabled(rx_ring) &&
3290 !ring_is_ps_enabled(rx_ring)) {
3291 rx_ring->rx_buf_len =
3292 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3293 }
63f39bd1 3294 }
63f39bd1 3295#endif /* IXGBE_FCOE */
477de6ed 3296 }
477de6ed
AD		 3297}
3298
7367096a
AD		 3299static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3300{
3301 struct ixgbe_hw *hw = &adapter->hw;
3302 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3303
3304 switch (hw->mac.type) {
3305 case ixgbe_mac_82598EB:
3306 /*
3307 * For VMDq support of different descriptor types or
3308 * buffer sizes through the use of multiple SRRCTL
3309 * registers, RDRXCTL.MVMEN must be set to 1
3310 *
3311 * also, the manual doesn't mention it clearly but DCA hints
3312 * will only use queue 0's tags unless this bit is set. Side
3313 * effects of setting this bit are only that SRRCTL must be
3314 * fully programmed [0..15]
3315 */
3316 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3317 break;
3318 case ixgbe_mac_82599EB:
b93a2226 3319 case ixgbe_mac_X540:
7367096a
AD		 3320 /* Disable RSC for ACK packets */
3321 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3322 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3323 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3324 /* hardware requires some bits to be set by default */
3325 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3326 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3327 break;
3328 default:
3329 /* We should do nothing since we don't know this hardware */
3330 return;
3331 }
3332
3333 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3334}
3335
477de6ed
AD		 3336/**
3337 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3338 * @adapter: board private structure
3339 *
3340 * Configure the Rx unit of the MAC after a reset.
3341 **/
3342static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3343{
3344 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3345 int i;
3346 u32 rxctrl;
477de6ed
AD		 3347
3348 /* disable receives while setting up the descriptors */
3349 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3350 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3351
3352 ixgbe_setup_psrtype(adapter);
7367096a 3353 ixgbe_setup_rdrxctl(adapter);
477de6ed 3354
9e10e045 3355 /* Program registers for the distribution of queues */
f5b4a52e 3356 ixgbe_setup_mrqc(adapter);
f5b4a52e 3357
9e10e045
AD		 3358 ixgbe_set_uta(adapter);
3359
477de6ed
AD		 3360 /* set_rx_buffer_len must be called before ring initialization */
3361 ixgbe_set_rx_buffer_len(adapter);
3362
3363 /*
3364 * Setup the HW Rx Head and Tail Descriptor Pointers and
3365 * the Base and Length of the Rx Descriptor Ring
3366 */
9e10e045
AD		 3367 for (i = 0; i < adapter->num_rx_queues; i++)
3368 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3369
9e10e045
AD		 3370 /* disable drop enable for 82598 parts */
3371 if (hw->mac.type == ixgbe_mac_82598EB)
3372 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3373
3374 /* enable all receives */
3375 rxctrl |= IXGBE_RXCTRL_RXEN;
3376 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3377}
3378
068c89b0
DS		 3379static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3380{
3381 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3382 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3383 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3384
3385 /* add VID to filter table */
1ada1b1b 3386 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3387 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3388}
3389
3390static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3391{
3392 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3393 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3394 int pool_ndx = adapter->num_vfs;
068c89b0 3395
068c89b0 3396 /* remove VID from filter table */
1ada1b1b 3397 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3398 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3399}
3400
5f6c0181
JB		 3401/**
3402 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3403 * @adapter: driver data
3404 */
3405static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3406{
3407 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3408 u32 vlnctrl;
3409
3410 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3411 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3412 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3413}
3414
3415/**
3416 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3417 * @adapter: driver data
3418 */
3419static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3420{
3421 struct ixgbe_hw *hw = &adapter->hw;
3422 u32 vlnctrl;
3423
3424 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3425 vlnctrl |= IXGBE_VLNCTRL_VFE;
3426 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3427 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3428}
3429
3430/**
3431 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3432 * @adapter: driver data
3433 */
3434static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3435{
3436 struct ixgbe_hw *hw = &adapter->hw;
3437 u32 vlnctrl;
5f6c0181
JB		 3438 int i, j;
3439
3440 switch (hw->mac.type) {
3441 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3442 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3443 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3444 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3445 break;
3446 case ixgbe_mac_82599EB:
b93a2226 3447 case ixgbe_mac_X540:
5f6c0181
JB		 3448 for (i = 0; i < adapter->num_rx_queues; i++) {
3449 j = adapter->rx_ring[i]->reg_idx;
3450 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3451 vlnctrl &= ~IXGBE_RXDCTL_VME;
3452 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3453 }
3454 break;
3455 default:
3456 break;
3457 }
3458}
3459
3460/**
f62bbb5e 3461 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3462 * @adapter: driver data
3463 */
f62bbb5e 3464static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3465{
3466 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3467 u32 vlnctrl;
5f6c0181
JB		 3468 int i, j;
3469
3470 switch (hw->mac.type) {
3471 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3472 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3473 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3474 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3475 break;
3476 case ixgbe_mac_82599EB:
b93a2226 3477 case ixgbe_mac_X540:
5f6c0181
JB		 3478 for (i = 0; i < adapter->num_rx_queues; i++) {
3479 j = adapter->rx_ring[i]->reg_idx;
3480 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3481 vlnctrl |= IXGBE_RXDCTL_VME;
3482 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3483 }
3484 break;
3485 default:
3486 break;
3487 }
3488}
3489
9a799d71
AK		 3490static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3491{
f62bbb5e 3492 u16 vid;
9a799d71 3493
f62bbb5e
JG		 3494 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3495
3496 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3497 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3498}
3499
2850062a
AD		 3500/**
3501 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3502 * @netdev: network interface device structure
3503 *
3504 * Writes unicast address list to the RAR table.
3505 * Returns: -ENOMEM on failure/insufficient address space
3506 * 0 on no addresses written
3507 * X on writing X addresses to the RAR table
3508 **/
3509static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3510{
3511 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3512 struct ixgbe_hw *hw = &adapter->hw;
3513 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3514 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3515 int count = 0;
3516
3517 /* return ENOMEM indicating insufficient memory for addresses */
3518 if (netdev_uc_count(netdev) > rar_entries)
3519 return -ENOMEM;
3520
3521 if (!netdev_uc_empty(netdev) && rar_entries) {
3522 struct netdev_hw_addr *ha;
3523 /* return error if we do not support writing to RAR table */
3524 if (!hw->mac.ops.set_rar)
3525 return -ENOMEM;
3526
3527 netdev_for_each_uc_addr(ha, netdev) {
3528 if (!rar_entries)
3529 break;
3530 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3531 vfn, IXGBE_RAH_AV);
3532 count++;
3533 }
3534 }
3535 /* write the addresses in reverse order to avoid write combining */
3536 for (; rar_entries > 0 ; rar_entries--)
3537 hw->mac.ops.clear_rar(hw, rar_entries);
3538
3539 return count;
3540}
3541
9a799d71 3542/**
2c5645cf 3543 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3544 * @netdev: network interface device structure
3545 *
2c5645cf
CL		 3546 * The set_rx_method entry point is called whenever the unicast/multicast
3547 * address list or the network interface flags are updated. This routine is
3548 * responsible for configuring the hardware for proper unicast, multicast and
3549 * promiscuous mode.
9a799d71 3550 **/
7f870475 3551void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3552{
3553 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3554 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3555 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3556 int count;
9a799d71
AK		 3557
3558 /* Check for Promiscuous and All Multicast modes */
3559
3560 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3561
f5dc442b
AD		 3562 /* set all bits that we expect to always be set */
3563 fctrl |= IXGBE_FCTRL_BAM;
3564 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3565 fctrl |= IXGBE_FCTRL_PMCF;
3566
2850062a
AD		 3567 /* clear the bits we are changing the status of */
3568 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3569
9a799d71 3570 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3571 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3572 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3573 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3574 /* don't hardware filter vlans in promisc mode */
3575 ixgbe_vlan_filter_disable(adapter);
9a799d71 3576 } else {
746b9f02
PM		 3577 if (netdev->flags & IFF_ALLMULTI) {
3578 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3579 vmolr |= IXGBE_VMOLR_MPE;
3580 } else {
3581 /*
3582 * Write addresses to the MTA, if the attempt fails
25985edc 3583 * then we should just turn on promiscuous mode so
2850062a
AD		 3584 * that we can at least receive multicast traffic
3585 */
3586 hw->mac.ops.update_mc_addr_list(hw, netdev);
3587 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3588 }
5f6c0181 3589 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3590 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3591 /*
3592 * Write addresses to available RAR registers, if there is not
3593 * sufficient space to store all the addresses then enable
25985edc 3594 * unicast promiscuous mode
2850062a
AD		 3595 */
3596 count = ixgbe_write_uc_addr_list(netdev);
3597 if (count < 0) {
3598 fctrl |= IXGBE_FCTRL_UPE;
3599 vmolr |= IXGBE_VMOLR_ROPE;
3600 }
9a799d71
AK		 3601 }
3602
2850062a 3603 if (adapter->num_vfs) {
1cdd1ec8 3604 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3605 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3606 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3607 IXGBE_VMOLR_ROPE);
3608 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3609 }
3610
3611 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3612
3613 if (netdev->features & NETIF_F_HW_VLAN_RX)
3614 ixgbe_vlan_strip_enable(adapter);
3615 else
3616 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3617}
3618
021230d4
AV		 3619static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3620{
3621 int q_idx;
3622 struct ixgbe_q_vector *q_vector;
3623 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3624
3625 /* legacy and MSI only use one vector */
3626 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3627 q_vectors = 1;
3628
3629 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3630 struct napi_struct *napi;
7a921c93 3631 q_vector = adapter->q_vector[q_idx];
f0848276 3632 napi = &q_vector->napi;
91281fd3
AD		 3633 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3634 if (!q_vector->rxr_count || !q_vector->txr_count) {
3635 if (q_vector->txr_count == 1)
3636 napi->poll = &ixgbe_clean_txonly;
3637 else if (q_vector->rxr_count == 1)
3638 napi->poll = &ixgbe_clean_rxonly;
3639 }
3640 }
f0848276
JB		 3641
3642 napi_enable(napi);
021230d4
AV		 3643 }
3644}
3645
3646static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3647{
3648 int q_idx;
3649 struct ixgbe_q_vector *q_vector;
3650 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3651
3652 /* legacy and MSI only use one vector */
3653 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3654 q_vectors = 1;
3655
3656 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3657 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3658 napi_disable(&q_vector->napi);
3659 }
3660}
3661
7a6b6f51 3662#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3663/*
3664 * ixgbe_configure_dcb - Configure DCB hardware
3665 * @adapter: ixgbe adapter struct
3666 *
3667 * This is called by the driver on open to configure the DCB hardware.
3668 * This is also called by the gennetlink interface when reconfiguring
3669 * the DCB state.
3670 */
3671static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3672{
3673 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3674 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3675
67ebd791
AD		 3676 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3677 if (hw->mac.type == ixgbe_mac_82598EB)
3678 netif_set_gso_max_size(adapter->netdev, 65536);
3679 return;
3680 }
3681
3682 if (hw->mac.type == ixgbe_mac_82598EB)
3683 netif_set_gso_max_size(adapter->netdev, 32768);
3684
2f90b865 3685
2f90b865 3686 /* Enable VLAN tag insert/strip */
f62bbb5e 3687 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3688
2f90b865 3689 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3690
3691 /* reconfigure the hardware */
6f70f6ac 3692 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3693#ifdef CONFIG_FCOE
3694 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3695 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3696#endif
3697 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3698 DCB_TX_CONFIG);
3699 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3700 DCB_RX_CONFIG);
3701 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3702 } else {
3703 struct net_device *dev = adapter->netdev;
3704
3705 if (adapter->ixgbe_ieee_ets)
3706 dev->dcbnl_ops->ieee_setets(dev,
3707 adapter->ixgbe_ieee_ets);
3708 if (adapter->ixgbe_ieee_pfc)
3709 dev->dcbnl_ops->ieee_setpfc(dev,
3710 adapter->ixgbe_ieee_pfc);
3711 }
8187cd48
JF		 3712
3713 /* Enable RSS Hash per TC */
3714 if (hw->mac.type != ixgbe_mac_82598EB) {
3715 int i;
3716 u32 reg = 0;
3717
3718 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3719 u8 msb = 0;
3720 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3721
3722 while (cnt >>= 1)
3723 msb++;
3724
3725 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3726 }
3727 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3728 }
2f90b865
AD		 3729}
3730
3731#endif
80605c65
JF		 3732
3733static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3734{
3735 int hdrm = 0;
3736 int num_tc = netdev_get_num_tc(adapter->netdev);
3737 struct ixgbe_hw *hw = &adapter->hw;
3738
3739 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3740 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3741 hdrm = 64 << adapter->fdir_pballoc;
3742
3743 hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3744}
3745
9a799d71
AK		 3746static void ixgbe_configure(struct ixgbe_adapter *adapter)
3747{
3748 struct net_device *netdev = adapter->netdev;
c4cf55e5 3749 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3750 int i;
3751
80605c65 3752 ixgbe_configure_pb(adapter);
7a6b6f51 3753#ifdef CONFIG_IXGBE_DCB
67ebd791 3754 ixgbe_configure_dcb(adapter);
2f90b865 3755#endif
9a799d71 3756
f62bbb5e
JG		 3757 ixgbe_set_rx_mode(netdev);
3758 ixgbe_restore_vlan(adapter);
3759
eacd73f7
YZ		 3760#ifdef IXGBE_FCOE
3761 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3762 ixgbe_configure_fcoe(adapter);
3763
3764#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3765 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3766 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3767 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3768 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3769 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3770 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3771 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3772 }
933d41f1 3773 ixgbe_configure_virtualization(adapter);
c4cf55e5 3774
9a799d71
AK		 3775 ixgbe_configure_tx(adapter);
3776 ixgbe_configure_rx(adapter);
9a799d71
AK		 3777}
3778
e8e26350
PW		 3779static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3780{
3781 switch (hw->phy.type) {
3782 case ixgbe_phy_sfp_avago:
3783 case ixgbe_phy_sfp_ftl:
3784 case ixgbe_phy_sfp_intel:
3785 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3786 case ixgbe_phy_sfp_passive_tyco:
3787 case ixgbe_phy_sfp_passive_unknown:
3788 case ixgbe_phy_sfp_active_unknown:
3789 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3790 return true;
3791 default:
3792 return false;
3793 }
3794}
3795
0ecc061d 3796/**
e8e26350
PW		 3797 * ixgbe_sfp_link_config - set up SFP+ link
3798 * @adapter: pointer to private adapter struct
3799 **/
3800static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3801{
7086400d
AD		 3802 /*
3803 * We are assuming the worst case scenerio here, and that
3804 * is that an SFP was inserted/removed after the reset
3805 * but before SFP detection was enabled. As such the best
3806 * solution is to just start searching as soon as we start
3807 */
3808 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3809 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3810
7086400d 3811 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3812}
3813
3814/**
3815 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3816 * @hw: pointer to private hardware struct
3817 *
3818 * Returns 0 on success, negative on failure
3819 **/
e8e26350 3820static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3821{
3822 u32 autoneg;
8620a103 3823 bool negotiation, link_up = false;
0ecc061d
PWJ		 3824 u32 ret = IXGBE_ERR_LINK_SETUP;
3825
3826 if (hw->mac.ops.check_link)
3827 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3828
3829 if (ret)
3830 goto link_cfg_out;
3831
0b0c2b31
ET		 3832 autoneg = hw->phy.autoneg_advertised;
3833 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3834 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3835 &negotiation);
0ecc061d
PWJ		 3836 if (ret)
3837 goto link_cfg_out;
3838
8620a103
MC		 3839 if (hw->mac.ops.setup_link)
3840 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3841link_cfg_out:
3842 return ret;
3843}
3844
a34bcfff 3845static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3846{
9a799d71 3847 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3848 u32 gpie = 0;
9a799d71 3849
9b471446 3850 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3851 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3852 IXGBE_GPIE_OCD;
3853 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3854 /*
3855 * use EIAM to auto-mask when MSI-X interrupt is asserted
3856 * this saves a register write for every interrupt
3857 */
3858 switch (hw->mac.type) {
3859 case ixgbe_mac_82598EB:
3860 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3861 break;
9b471446 3862 case ixgbe_mac_82599EB:
b93a2226
DS		 3863 case ixgbe_mac_X540:
3864 default:
9b471446
JB		 3865 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3866 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3867 break;
3868 }
3869 } else {
021230d4
AV		 3870 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3871 * specifically only auto mask tx and rx interrupts */
3872 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3873 }
9a799d71 3874
a34bcfff
AD		 3875 /* XXX: to interrupt immediately for EICS writes, enable this */
3876 /* gpie |= IXGBE_GPIE_EIMEN; */
3877
3878 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3879 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3880 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3881 }
3882
a34bcfff
AD		 3883 /* Enable fan failure interrupt */
3884 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3885 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3886
2698b208 3887 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3888 gpie |= IXGBE_SDP1_GPIEN;
3889 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3890 }
a34bcfff
AD		 3891
3892 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3893}
3894
3895static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3896{
3897 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3898 int err;
a34bcfff
AD		 3899 u32 ctrl_ext;
3900
3901 ixgbe_get_hw_control(adapter);
3902 ixgbe_setup_gpie(adapter);
e8e26350 3903
9a799d71
AK		 3904 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3905 ixgbe_configure_msix(adapter);
3906 else
3907 ixgbe_configure_msi_and_legacy(adapter);
3908
c6ecf39a
DS		 3909 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3910 if (hw->mac.ops.enable_tx_laser &&
3911 ((hw->phy.multispeed_fiber) ||
9f911707 3912 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3913 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3914 hw->mac.ops.enable_tx_laser(hw);
3915
9a799d71 3916 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3917 ixgbe_napi_enable_all(adapter);
3918
73c4b7cd
AD		 3919 if (ixgbe_is_sfp(hw)) {
3920 ixgbe_sfp_link_config(adapter);
3921 } else {
3922 err = ixgbe_non_sfp_link_config(hw);
3923 if (err)
3924 e_err(probe, "link_config FAILED %d\n", err);
3925 }
3926
021230d4
AV		 3927 /* clear any pending interrupts, may auto mask */
3928 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3929 ixgbe_irq_enable(adapter, true, true);
9a799d71 3930
bf069c97
DS		 3931 /*
3932 * If this adapter has a fan, check to see if we had a failure
3933 * before we enabled the interrupt.
3934 */
3935 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3936 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3937 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3938 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3939 }
3940
1da100bb 3941 /* enable transmits */
477de6ed 3942 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3943
9a799d71
AK		 3944 /* bring the link up in the watchdog, this could race with our first
3945 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3946 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3947 adapter->link_check_timeout = jiffies;
7086400d 3948 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3949
3950 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3951 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3952 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3953 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3954
9a799d71
AK		 3955 return 0;
3956}
3957
d4f80882
AV		 3958void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3959{
3960 WARN_ON(in_interrupt());
7086400d
AD		 3961 /* put off any impending NetWatchDogTimeout */
3962 adapter->netdev->trans_start = jiffies;
3963
d4f80882 3964 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3965 usleep_range(1000, 2000);
d4f80882 3966 ixgbe_down(adapter);
5809a1ae
GR		 3967 /*
3968 * If SR-IOV enabled then wait a bit before bringing the adapter
3969 * back up to give the VFs time to respond to the reset. The
3970 * two second wait is based upon the watchdog timer cycle in
3971 * the VF driver.
3972 */
3973 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3974 msleep(2000);
d4f80882
AV		 3975 ixgbe_up(adapter);
3976 clear_bit(__IXGBE_RESETTING, &adapter->state);
3977}
3978
9a799d71
AK		 3979int ixgbe_up(struct ixgbe_adapter *adapter)
3980{
3981 /* hardware has been reset, we need to reload some things */
3982 ixgbe_configure(adapter);
3983
3984 return ixgbe_up_complete(adapter);
3985}
3986
3987void ixgbe_reset(struct ixgbe_adapter *adapter)
3988{
c44ade9e 3989 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3990 int err;
3991
7086400d
AD		 3992 /* lock SFP init bit to prevent race conditions with the watchdog */
3993 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3994 usleep_range(1000, 2000);
3995
3996 /* clear all SFP and link config related flags while holding SFP_INIT */
3997 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3998 IXGBE_FLAG2_SFP_NEEDS_RESET);
3999 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4000
8ca783ab 4001 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4002 switch (err) {
4003 case 0:
4004 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4005 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4006 break;
4007 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4008 e_dev_err("master disable timed out\n");
da4dd0f7 4009 break;
794caeb2
PWJ		 4010 case IXGBE_ERR_EEPROM_VERSION:
4011 /* We are running on a pre-production device, log a warning */
849c4542
ET		 4012 e_dev_warn("This device is a pre-production adapter/LOM. "
4013 "Please be aware there may be issuesassociated with "
4014 "your hardware. If you are experiencing problems "
4015 "please contact your Intel or hardware "
4016 "representative who provided you with this "
4017 "hardware.\n");
794caeb2 4018 break;
da4dd0f7 4019 default:
849c4542 4020 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4021 }
9a799d71 4022
7086400d
AD		 4023 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4024
9a799d71 4025 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 4026 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4027 IXGBE_RAH_AV);
9a799d71
AK		 4028}
4029
9a799d71
AK		 4030/**
4031 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4032 * @rx_ring: ring to free buffers from
4033 **/
b6ec895e 4034static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4035{
b6ec895e 4036 struct device *dev = rx_ring->dev;
9a799d71 4037 unsigned long size;
b6ec895e 4038 u16 i;
9a799d71 4039
84418e3b
AD		 4040 /* ring already cleared, nothing to do */
4041 if (!rx_ring->rx_buffer_info)
4042 return;
9a799d71 4043
84418e3b 4044 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 4045 for (i = 0; i < rx_ring->count; i++) {
4046 struct ixgbe_rx_buffer *rx_buffer_info;
4047
4048 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4049 if (rx_buffer_info->dma) {
b6ec895e 4050 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 4051 rx_ring->rx_buf_len,
1b507730 4052 DMA_FROM_DEVICE);
9a799d71
AK		 4053 rx_buffer_info->dma = 0;
4054 }
4055 if (rx_buffer_info->skb) {
f8212f97 4056 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 4057 rx_buffer_info->skb = NULL;
f8212f97
AD		 4058 do {
4059 struct sk_buff *this = skb;
e8171aaa 4060 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 4061 dma_unmap_single(dev,
1b507730 4062 IXGBE_RSC_CB(this)->dma,
e8e9f696 4063 rx_ring->rx_buf_len,
1b507730 4064 DMA_FROM_DEVICE);
fd3686a8 4065 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 4066 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 4067 }
f8212f97
AD		 4068 skb = skb->prev;
4069 dev_kfree_skb(this);
4070 } while (skb);
9a799d71
AK		 4071 }
4072 if (!rx_buffer_info->page)
4073 continue;
4f57ca6e 4074 if (rx_buffer_info->page_dma) {
b6ec895e 4075 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 4076 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 4077 rx_buffer_info->page_dma = 0;
4078 }
9a799d71
AK		 4079 put_page(rx_buffer_info->page);
4080 rx_buffer_info->page = NULL;
762f4c57 4081 rx_buffer_info->page_offset = 0;
9a799d71
AK		 4082 }
4083
4084 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4085 memset(rx_ring->rx_buffer_info, 0, size);
4086
4087 /* Zero out the descriptor ring */
4088 memset(rx_ring->desc, 0, rx_ring->size);
4089
4090 rx_ring->next_to_clean = 0;
4091 rx_ring->next_to_use = 0;
9a799d71
AK		 4092}
4093
4094/**
4095 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4096 * @tx_ring: ring to be cleaned
4097 **/
b6ec895e 4098static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4099{
4100 struct ixgbe_tx_buffer *tx_buffer_info;
4101 unsigned long size;
b6ec895e 4102 u16 i;
9a799d71 4103
84418e3b
AD		 4104 /* ring already cleared, nothing to do */
4105 if (!tx_ring->tx_buffer_info)
4106 return;
9a799d71 4107
84418e3b 4108 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4109 for (i = 0; i < tx_ring->count; i++) {
4110 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4111 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4112 }
4113
4114 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4115 memset(tx_ring->tx_buffer_info, 0, size);
4116
4117 /* Zero out the descriptor ring */
4118 memset(tx_ring->desc, 0, tx_ring->size);
4119
4120 tx_ring->next_to_use = 0;
4121 tx_ring->next_to_clean = 0;
9a799d71
AK		 4122}
4123
4124/**
021230d4 4125 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4126 * @adapter: board private structure
4127 **/
021230d4 4128static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4129{
4130 int i;
4131
021230d4 4132 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4133 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4134}
4135
4136/**
021230d4 4137 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4138 * @adapter: board private structure
4139 **/
021230d4 4140static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4141{
4142 int i;
4143
021230d4 4144 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4145 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4146}
4147
4148void ixgbe_down(struct ixgbe_adapter *adapter)
4149{
4150 struct net_device *netdev = adapter->netdev;
7f821875 4151 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4152 u32 rxctrl;
bf29ee6c 4153 int i;
b25ebfd2 4154 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 4155
4156 /* signal that we are down to the interrupt handler */
4157 set_bit(__IXGBE_DOWN, &adapter->state);
4158
4159 /* disable receives */
7f821875
JB		 4160 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4161 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4162
2d39d576
YZ		 4163 /* disable all enabled rx queues */
4164 for (i = 0; i < adapter->num_rx_queues; i++)
4165 /* this call also flushes the previous write */
4166 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4167
032b4325 4168 usleep_range(10000, 20000);
9a799d71 4169
7f821875
JB		 4170 netif_tx_stop_all_queues(netdev);
4171
7086400d 4172 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4173 netif_carrier_off(netdev);
4174 netif_tx_disable(netdev);
4175
4176 ixgbe_irq_disable(adapter);
4177
4178 ixgbe_napi_disable_all(adapter);
4179
d034acf1
AD		 4180 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4181 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4182 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4183
4184 del_timer_sync(&adapter->service_timer);
4185
34cecbbf
AD		 4186 /* disable receive for all VFs and wait one second */
4187 if (adapter->num_vfs) {
4188 /* ping all the active vfs to let them know we are going down */
4189 ixgbe_ping_all_vfs(adapter);
4190
4191 /* Disable all VFTE/VFRE TX/RX */
4192 ixgbe_disable_tx_rx(adapter);
4193
4194 /* Mark all the VFs as inactive */
4195 for (i = 0 ; i < adapter->num_vfs; i++)
4196 adapter->vfinfo[i].clear_to_send = 0;
4197 }
4198
b25ebfd2
PW		 4199 /* Cleanup the affinity_hint CPU mask memory and callback */
4200 for (i = 0; i < num_q_vectors; i++) {
4201 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4202 /* clear the affinity_mask in the IRQ descriptor */
4203 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4204 /* release the CPU mask memory */
4205 free_cpumask_var(q_vector->affinity_mask);
4206 }
4207
7f821875
JB		 4208 /* disable transmits in the hardware now that interrupts are off */
4209 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4210 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4211 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4212 }
34cecbbf
AD		 4213
4214 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4215 switch (hw->mac.type) {
4216 case ixgbe_mac_82599EB:
b93a2226 4217 case ixgbe_mac_X540:
88512539 4218 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4219 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4220 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4221 break;
4222 default:
4223 break;
4224 }
7f821875 4225
6f4a0e45
PL		 4226 if (!pci_channel_offline(adapter->pdev))
4227 ixgbe_reset(adapter);
c6ecf39a
DS		 4228
4229 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4230 if (hw->mac.ops.disable_tx_laser &&
4231 ((hw->phy.multispeed_fiber) ||
9f911707 4232 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4233 (hw->mac.type == ixgbe_mac_82599EB))))
4234 hw->mac.ops.disable_tx_laser(hw);
4235
9a799d71
AK		 4236 ixgbe_clean_all_tx_rings(adapter);
4237 ixgbe_clean_all_rx_rings(adapter);
4238
5dd2d332 4239#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4240 /* since we reset the hardware DCA settings were cleared */
e35ec126 4241 ixgbe_setup_dca(adapter);
96b0e0f6 4242#endif
9a799d71
AK		 4243}
4244
9a799d71 4245/**
021230d4
AV		 4246 * ixgbe_poll - NAPI Rx polling callback
4247 * @napi: structure for representing this polling device
4248 * @budget: how many packets driver is allowed to clean
4249 *
4250 * This function is used for legacy and MSI, NAPI mode
9a799d71 4251 **/
021230d4 4252static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4253{
9a1a69ad 4254 struct ixgbe_q_vector *q_vector =
e8e9f696 4255 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4256 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 4257 int tx_clean_complete, work_done = 0;
9a799d71 4258
5dd2d332 4259#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4260 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4261 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4262#endif
4263
4a0b9ca0
PW		 4264 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4265 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 4266
9a1a69ad 4267 if (!tx_clean_complete)
d2c7ddd6
DM		 4268 work_done = budget;
4269
53e52c72
DM		 4270 /* If budget not fully consumed, exit the polling mode */
4271 if (work_done < budget) {
288379f0 4272 napi_complete(napi);
f7554a2b 4273 if (adapter->rx_itr_setting & 1)
f494e8fa 4274 ixgbe_set_itr(adapter);
d4f80882 4275 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 4276 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 4277 }
9a799d71
AK		 4278 return work_done;
4279}
4280
4281/**
4282 * ixgbe_tx_timeout - Respond to a Tx Hang
4283 * @netdev: network interface device structure
4284 **/
4285static void ixgbe_tx_timeout(struct net_device *netdev)
4286{
4287 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4288
4289 /* Do the reset outside of interrupt context */
c83c6cbd 4290 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4291}
4292
4df10466
JB		 4293/**
4294 * ixgbe_set_rss_queues: Allocate queues for RSS
4295 * @adapter: board private structure to initialize
4296 *
4297 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4298 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4299 *
4300 **/
bc97114d
PWJ		 4301static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4302{
4303 bool ret = false;
0cefafad 4304 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4305
4306 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4307 f->mask = 0xF;
4308 adapter->num_rx_queues = f->indices;
4309 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4310 ret = true;
4311 } else {
bc97114d 4312 ret = false;
b9804972
JB		 4313 }
4314
bc97114d
PWJ		 4315 return ret;
4316}
4317
c4cf55e5
PWJ		 4318/**
4319 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4320 * @adapter: board private structure to initialize
4321 *
4322 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4323 * to the original CPU that initiated the Tx session. This runs in addition
4324 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4325 * Rx load across CPUs using RSS.
4326 *
4327 **/
e8e9f696 4328static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4329{
4330 bool ret = false;
4331 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4332
4333 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4334 f_fdir->mask = 0;
4335
4336 /* Flow Director must have RSS enabled */
4337 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4338 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4339 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4340 adapter->num_tx_queues = f_fdir->indices;
4341 adapter->num_rx_queues = f_fdir->indices;
4342 ret = true;
4343 } else {
4344 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4345 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4346 }
4347 return ret;
4348}
4349
0331a832
YZ		 4350#ifdef IXGBE_FCOE
4351/**
4352 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4353 * @adapter: board private structure to initialize
4354 *
4355 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4356 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4357 * rx queues out of the max number of rx queues, instead, it is used as the
4358 * index of the first rx queue used by FCoE.
4359 *
4360 **/
4361static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4362{
0331a832
YZ		 4363 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4364
e5b64635
JF		 4365 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4366 return false;
4367
e901acd6 4368 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4369
e901acd6
JF		 4370 adapter->num_rx_queues = 1;
4371 adapter->num_tx_queues = 1;
e5b64635 4372
e901acd6
JF		 4373 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4374 e_info(probe, "FCoE enabled with RSS\n");
4375 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4376 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4377 ixgbe_set_fdir_queues(adapter);
4378 else
4379 ixgbe_set_rss_queues(adapter);
e5b64635 4380 }
e901acd6
JF		 4381 /* adding FCoE rx rings to the end */
4382 f->mask = adapter->num_rx_queues;
4383 adapter->num_rx_queues += f->indices;
4384 adapter->num_tx_queues += f->indices;
0331a832 4385
e5b64635
JF		 4386 return true;
4387}
4388#endif /* IXGBE_FCOE */
4389
e901acd6
JF		 4390/* Artificial max queue cap per traffic class in DCB mode */
4391#define DCB_QUEUE_CAP 8
4392
e5b64635
JF		 4393#ifdef CONFIG_IXGBE_DCB
4394static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4395{
e901acd6
JF		 4396 int per_tc_q, q, i, offset = 0;
4397 struct net_device *dev = adapter->netdev;
4398 int tcs = netdev_get_num_tc(dev);
e5b64635 4399
e901acd6
JF		 4400 if (!tcs)
4401 return false;
e5b64635 4402
e901acd6
JF		 4403 /* Map queue offset and counts onto allocated tx queues */
4404 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4405 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4406
8b1c0b24 4407 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4408 netdev_set_prio_tc_map(dev, i, i);
4409 netdev_set_tc_queue(dev, i, q, offset);
4410 offset += q;
0331a832
YZ		 4411 }
4412
e901acd6
JF		 4413 adapter->num_tx_queues = q * tcs;
4414 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4415
4416#ifdef IXGBE_FCOE
e901acd6
JF		 4417 /* FCoE enabled queues require special configuration indexed
4418 * by feature specific indices and mask. Here we map FCoE
4419 * indices onto the DCB queue pairs allowing FCoE to own
4420 * configuration later.
e5b64635 4421 */
e901acd6
JF		 4422 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4423 int tc;
4424 struct ixgbe_ring_feature *f =
4425 &adapter->ring_feature[RING_F_FCOE];
4426
4427 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4428 f->indices = dev->tc_to_txq[tc].count;
4429 f->mask = dev->tc_to_txq[tc].offset;
4430 }
e5b64635
JF		 4431#endif
4432
e901acd6 4433 return true;
0331a832 4434}
e5b64635 4435#endif
0331a832 4436
1cdd1ec8
GR		 4437/**
4438 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4439 * @adapter: board private structure to initialize
4440 *
4441 * IOV doesn't actually use anything, so just NAK the
4442 * request for now and let the other queue routines
4443 * figure out what to do.
4444 */
4445static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4446{
4447 return false;
4448}
4449
4df10466 4450/*
25985edc 4451 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4452 * @adapter: board private structure to initialize
4453 *
4454 * This is the top level queue allocation routine. The order here is very
4455 * important, starting with the "most" number of features turned on at once,
4456 * and ending with the smallest set of features. This way large combinations
4457 * can be allocated if they're turned on, and smaller combinations are the
4458 * fallthrough conditions.
4459 *
4460 **/
847f53ff 4461static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4462{
1cdd1ec8
GR		 4463 /* Start with base case */
4464 adapter->num_rx_queues = 1;
4465 adapter->num_tx_queues = 1;
4466 adapter->num_rx_pools = adapter->num_rx_queues;
4467 adapter->num_rx_queues_per_pool = 1;
4468
4469 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4470 goto done;
1cdd1ec8 4471
bc97114d
PWJ		 4472#ifdef CONFIG_IXGBE_DCB
4473 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4474 goto done;
bc97114d
PWJ		 4475
4476#endif
e5b64635
JF		 4477#ifdef IXGBE_FCOE
4478 if (ixgbe_set_fcoe_queues(adapter))
4479 goto done;
4480
4481#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4482 if (ixgbe_set_fdir_queues(adapter))
4483 goto done;
4484
bc97114d 4485 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4486 goto done;
4487
4488 /* fallback to base case */
4489 adapter->num_rx_queues = 1;
4490 adapter->num_tx_queues = 1;
4491
4492done:
847f53ff 4493 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4494 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4495 return netif_set_real_num_rx_queues(adapter->netdev,
4496 adapter->num_rx_queues);
b9804972
JB		 4497}
4498
021230d4 4499static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4500 int vectors)
021230d4
AV		 4501{
4502 int err, vector_threshold;
4503
4504 /* We'll want at least 3 (vector_threshold):
4505 * 1) TxQ[0] Cleanup
4506 * 2) RxQ[0] Cleanup
4507 * 3) Other (Link Status Change, etc.)
4508 * 4) TCP Timer (optional)
4509 */
4510 vector_threshold = MIN_MSIX_COUNT;
4511
4512 /* The more we get, the more we will assign to Tx/Rx Cleanup
4513 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4514 * Right now, we simply care about how many we'll get; we'll
4515 * set them up later while requesting irq's.
4516 */
4517 while (vectors >= vector_threshold) {
4518 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4519 vectors);
021230d4
AV		 4520 if (!err) /* Success in acquiring all requested vectors. */
4521 break;
4522 else if (err < 0)
4523 vectors = 0; /* Nasty failure, quit now */
4524 else /* err == number of vectors we should try again with */
4525 vectors = err;
4526 }
4527
4528 if (vectors < vector_threshold) {
4529 /* Can't allocate enough MSI-X interrupts? Oh well.
4530 * This just means we'll go with either a single MSI
4531 * vector or fall back to legacy interrupts.
4532 */
849c4542
ET		 4533 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4534 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4535 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4536 kfree(adapter->msix_entries);
4537 adapter->msix_entries = NULL;
021230d4
AV		 4538 } else {
4539 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4540 /*
4541 * Adjust for only the vectors we'll use, which is minimum
4542 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4543 * vectors we were allocated.
4544 */
4545 adapter->num_msix_vectors = min(vectors,
e8e9f696 4546 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4547 }
4548}
4549
021230d4 4550/**
bc97114d 4551 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4552 * @adapter: board private structure to initialize
4553 *
bc97114d
PWJ		 4554 * Cache the descriptor ring offsets for RSS to the assigned rings.
4555 *
021230d4 4556 **/
bc97114d 4557static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4558{
bc97114d 4559 int i;
bc97114d 4560
9d6b758f
AD		 4561 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4562 return false;
bc97114d 4563
9d6b758f
AD		 4564 for (i = 0; i < adapter->num_rx_queues; i++)
4565 adapter->rx_ring[i]->reg_idx = i;
4566 for (i = 0; i < adapter->num_tx_queues; i++)
4567 adapter->tx_ring[i]->reg_idx = i;
4568
4569 return true;
bc97114d
PWJ		 4570}
4571
4572#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4573
4574/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4575static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4576 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4577{
4578 struct net_device *dev = adapter->netdev;
4579 struct ixgbe_hw *hw = &adapter->hw;
4580 u8 num_tcs = netdev_get_num_tc(dev);
4581
4582 *tx = 0;
4583 *rx = 0;
4584
4585 switch (hw->mac.type) {
4586 case ixgbe_mac_82598EB:
aba70d5e
JF		 4587 *tx = tc << 2;
4588 *rx = tc << 3;
e5b64635
JF		 4589 break;
4590 case ixgbe_mac_82599EB:
4591 case ixgbe_mac_X540:
4592 if (num_tcs == 8) {
4593 if (tc < 3) {
4594 *tx = tc << 5;
4595 *rx = tc << 4;
4596 } else if (tc < 5) {
4597 *tx = ((tc + 2) << 4);
4598 *rx = tc << 4;
4599 } else if (tc < num_tcs) {
4600 *tx = ((tc + 8) << 3);
4601 *rx = tc << 4;
4602 }
4603 } else if (num_tcs == 4) {
4604 *rx = tc << 5;
4605 switch (tc) {
4606 case 0:
4607 *tx = 0;
4608 break;
4609 case 1:
4610 *tx = 64;
4611 break;
4612 case 2:
4613 *tx = 96;
4614 break;
4615 case 3:
4616 *tx = 112;
4617 break;
4618 default:
4619 break;
4620 }
4621 }
4622 break;
4623 default:
4624 break;
4625 }
4626}
4627
bc97114d
PWJ		 4628/**
4629 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4630 * @adapter: board private structure to initialize
4631 *
4632 * Cache the descriptor ring offsets for DCB to the assigned rings.
4633 *
4634 **/
4635static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4636{
e5b64635
JF		 4637 struct net_device *dev = adapter->netdev;
4638 int i, j, k;
4639 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4640
8b1c0b24 4641 if (!num_tcs)
bd508178 4642 return false;
f92ef202 4643
e5b64635
JF		 4644 for (i = 0, k = 0; i < num_tcs; i++) {
4645 unsigned int tx_s, rx_s;
4646 u16 count = dev->tc_to_txq[i].count;
4647
4648 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4649 for (j = 0; j < count; j++, k++) {
4650 adapter->tx_ring[k]->reg_idx = tx_s + j;
4651 adapter->rx_ring[k]->reg_idx = rx_s + j;
4652 adapter->tx_ring[k]->dcb_tc = i;
4653 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4654 }
021230d4 4655 }
e5b64635
JF		 4656
4657 return true;
bc97114d
PWJ		 4658}
4659#endif
4660
c4cf55e5
PWJ		 4661/**
4662 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4663 * @adapter: board private structure to initialize
4664 *
4665 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4666 *
4667 **/
e8e9f696 4668static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4669{
4670 int i;
4671 bool ret = false;
4672
4673 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4674 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4675 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4676 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4677 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4678 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4679 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4680 ret = true;
4681 }
4682
4683 return ret;
4684}
4685
0331a832
YZ		 4686#ifdef IXGBE_FCOE
4687/**
4688 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4689 * @adapter: board private structure to initialize
4690 *
4691 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4692 *
4693 */
4694static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4695{
0331a832 4696 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4697 int i;
4698 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4699
4700 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4701 return false;
0331a832 4702
bf29ee6c
AD		 4703 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4704 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4705 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4706 ixgbe_cache_ring_fdir(adapter);
4707 else
4708 ixgbe_cache_ring_rss(adapter);
8faa2a78 4709
bf29ee6c
AD		 4710 fcoe_rx_i = f->mask;
4711 fcoe_tx_i = f->mask;
0331a832 4712 }
bf29ee6c
AD		 4713 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4714 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4715 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4716 }
4717 return true;
0331a832
YZ		 4718}
4719
4720#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4721/**
4722 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4723 * @adapter: board private structure to initialize
4724 *
4725 * SR-IOV doesn't use any descriptor rings but changes the default if
4726 * no other mapping is used.
4727 *
4728 */
4729static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4730{
4a0b9ca0
PW		 4731 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4732 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4733 if (adapter->num_vfs)
4734 return true;
4735 else
4736 return false;
4737}
4738
bc97114d
PWJ		 4739/**
4740 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4741 * @adapter: board private structure to initialize
4742 *
4743 * Once we know the feature-set enabled for the device, we'll cache
4744 * the register offset the descriptor ring is assigned to.
4745 *
4746 * Note, the order the various feature calls is important. It must start with
4747 * the "most" features enabled at the same time, then trickle down to the
4748 * least amount of features turned on at once.
4749 **/
4750static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4751{
4752 /* start with default case */
4a0b9ca0
PW		 4753 adapter->rx_ring[0]->reg_idx = 0;
4754 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4755
1cdd1ec8
GR		 4756 if (ixgbe_cache_ring_sriov(adapter))
4757 return;
4758
e5b64635
JF		 4759#ifdef CONFIG_IXGBE_DCB
4760 if (ixgbe_cache_ring_dcb(adapter))
4761 return;
4762#endif
4763
0331a832
YZ		 4764#ifdef IXGBE_FCOE
4765 if (ixgbe_cache_ring_fcoe(adapter))
4766 return;
0331a832 4767#endif /* IXGBE_FCOE */
bc97114d 4768
c4cf55e5
PWJ		 4769 if (ixgbe_cache_ring_fdir(adapter))
4770 return;
4771
bc97114d
PWJ		 4772 if (ixgbe_cache_ring_rss(adapter))
4773 return;
021230d4
AV		 4774}
4775
9a799d71
AK		 4776/**
4777 * ixgbe_alloc_queues - Allocate memory for all rings
4778 * @adapter: board private structure to initialize
4779 *
4780 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4781 * number of queues at compile-time. The polling_netdev array is
4782 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4783 **/
2f90b865 4784static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4785{
e2ddeba9 4786 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4787
e2ddeba9
ED		 4788 if (nid < 0 || !node_online(nid))
4789 nid = first_online_node;
4790
4791 for (; tx < adapter->num_tx_queues; tx++) {
4792 struct ixgbe_ring *ring;
4793
4794 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4795 if (!ring)
e2ddeba9 4796 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4797 if (!ring)
e2ddeba9 4798 goto err_allocation;
4a0b9ca0 4799 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4800 ring->queue_index = tx;
4801 ring->numa_node = nid;
b6ec895e 4802 ring->dev = &adapter->pdev->dev;
fc77dc3c 4803 ring->netdev = adapter->netdev;
4a0b9ca0 4804
e2ddeba9 4805 adapter->tx_ring[tx] = ring;
021230d4 4806 }
b9804972 4807
e2ddeba9
ED		 4808 for (; rx < adapter->num_rx_queues; rx++) {
4809 struct ixgbe_ring *ring;
4a0b9ca0 4810
e2ddeba9 4811 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4812 if (!ring)
e2ddeba9 4813 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4814 if (!ring)
e2ddeba9
ED		 4815 goto err_allocation;
4816 ring->count = adapter->rx_ring_count;
4817 ring->queue_index = rx;
4818 ring->numa_node = nid;
b6ec895e 4819 ring->dev = &adapter->pdev->dev;
fc77dc3c 4820 ring->netdev = adapter->netdev;
4a0b9ca0 4821
e2ddeba9 4822 adapter->rx_ring[rx] = ring;
021230d4
AV		 4823 }
4824
4825 ixgbe_cache_ring_register(adapter);
4826
4827 return 0;
4828
e2ddeba9
ED		 4829err_allocation:
4830 while (tx)
4831 kfree(adapter->tx_ring[--tx]);
4832
4833 while (rx)
4834 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4835 return -ENOMEM;
4836}
4837
4838/**
4839 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4840 * @adapter: board private structure to initialize
4841 *
4842 * Attempt to configure the interrupts using the best available
4843 * capabilities of the hardware and the kernel.
4844 **/
feea6a57 4845static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4846{
8be0e467 4847 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4848 int err = 0;
4849 int vector, v_budget;
4850
4851 /*
4852 * It's easy to be greedy for MSI-X vectors, but it really
4853 * doesn't do us much good if we have a lot more vectors
4854 * than CPU's. So let's be conservative and only ask for
342bde1b 4855 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4856 */
4857 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4858 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4859
4860 /*
4861 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4862 * hw.mac->max_msix_vectors vectors. With features
4863 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4864 * descriptor queues supported by our device. Thus, we cap it off in
4865 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4866 */
8be0e467 4867 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4868
4869 /* A failure in MSI-X entry allocation isn't fatal, but it does
4870 * mean we disable MSI-X capabilities of the adapter. */
4871 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4872 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4873 if (adapter->msix_entries) {
4874 for (vector = 0; vector < v_budget; vector++)
4875 adapter->msix_entries[vector].entry = vector;
021230d4 4876
7a921c93 4877 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4878
7a921c93
AD		 4879 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4880 goto out;
4881 }
26d27844 4882
7a921c93
AD		 4883 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4884 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
45b9f509
AD		 4885 if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4886 IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4887 e_err(probe,
4888 "Flow Director is not supported while multiple "
4889 "queues are disabled. Disabling Flow Director\n");
4890 }
c4cf55e5
PWJ		 4891 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4892 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4893 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4894 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4895 ixgbe_disable_sriov(adapter);
4896
847f53ff
BH		 4897 err = ixgbe_set_num_queues(adapter);
4898 if (err)
4899 return err;
021230d4 4900
021230d4
AV		 4901 err = pci_enable_msi(adapter->pdev);
4902 if (!err) {
4903 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4904 } else {
849c4542
ET		 4905 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4906 "Unable to allocate MSI interrupt, "
4907 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4908 /* reset err */
4909 err = 0;
4910 }
4911
4912out:
021230d4
AV		 4913 return err;
4914}
4915
7a921c93
AD		 4916/**
4917 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4918 * @adapter: board private structure to initialize
4919 *
4920 * We allocate one q_vector per queue interrupt. If allocation fails we
4921 * return -ENOMEM.
4922 **/
4923static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4924{
4925 int q_idx, num_q_vectors;
4926 struct ixgbe_q_vector *q_vector;
7a921c93
AD		 4927 int (*poll)(struct napi_struct *, int);
4928
4929 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4930 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4931 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4932 } else {
4933 num_q_vectors = 1;
7a921c93
AD		 4934 poll = &ixgbe_poll;
4935 }
4936
4937 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4938 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4939 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4940 if (!q_vector)
4941 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4942 GFP_KERNEL);
7a921c93
AD		 4943 if (!q_vector)
4944 goto err_out;
4945 q_vector->adapter = adapter;
f7554a2b
NS		 4946 if (q_vector->txr_count && !q_vector->rxr_count)
4947 q_vector->eitr = adapter->tx_eitr_param;
4948 else
4949 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4950 q_vector->v_idx = q_idx;
91281fd3 4951 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4952 adapter->q_vector[q_idx] = q_vector;
4953 }
4954
4955 return 0;
4956
4957err_out:
4958 while (q_idx) {
4959 q_idx--;
4960 q_vector = adapter->q_vector[q_idx];
4961 netif_napi_del(&q_vector->napi);
4962 kfree(q_vector);
4963 adapter->q_vector[q_idx] = NULL;
4964 }
4965 return -ENOMEM;
4966}
4967
4968/**
4969 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4970 * @adapter: board private structure to initialize
4971 *
4972 * This function frees the memory allocated to the q_vectors. In addition if
4973 * NAPI is enabled it will delete any references to the NAPI struct prior
4974 * to freeing the q_vector.
4975 **/
4976static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4977{
4978 int q_idx, num_q_vectors;
7a921c93 4979
91281fd3 4980 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4981 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4982 else
7a921c93 4983 num_q_vectors = 1;
7a921c93
AD		 4984
4985 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4986 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4987 adapter->q_vector[q_idx] = NULL;
91281fd3 4988 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4989 kfree(q_vector);
4990 }
4991}
4992
7b25cdba 4993static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4994{
4995 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4996 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4997 pci_disable_msix(adapter->pdev);
4998 kfree(adapter->msix_entries);
4999 adapter->msix_entries = NULL;
5000 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5001 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5002 pci_disable_msi(adapter->pdev);
5003 }
021230d4
AV		 5004}
5005
5006/**
5007 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5008 * @adapter: board private structure to initialize
5009 *
5010 * We determine which interrupt scheme to use based on...
5011 * - Kernel support (MSI, MSI-X)
5012 * - which can be user-defined (via MODULE_PARAM)
5013 * - Hardware queue count (num_*_queues)
5014 * - defined by miscellaneous hardware support/features (RSS, etc.)
5015 **/
2f90b865 5016int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 5017{
5018 int err;
5019
5020 /* Number of supported queues */
847f53ff
BH		 5021 err = ixgbe_set_num_queues(adapter);
5022 if (err)
5023 return err;
021230d4 5024
021230d4
AV		 5025 err = ixgbe_set_interrupt_capability(adapter);
5026 if (err) {
849c4542 5027 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 5028 goto err_set_interrupt;
9a799d71
AK		 5029 }
5030
7a921c93
AD		 5031 err = ixgbe_alloc_q_vectors(adapter);
5032 if (err) {
849c4542 5033 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 5034 goto err_alloc_q_vectors;
5035 }
5036
5037 err = ixgbe_alloc_queues(adapter);
5038 if (err) {
849c4542 5039 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 5040 goto err_alloc_queues;
5041 }
5042
849c4542 5043 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 5044 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5045 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 5046
5047 set_bit(__IXGBE_DOWN, &adapter->state);
5048
9a799d71 5049 return 0;
021230d4 5050
7a921c93
AD		 5051err_alloc_queues:
5052 ixgbe_free_q_vectors(adapter);
5053err_alloc_q_vectors:
5054 ixgbe_reset_interrupt_capability(adapter);
021230d4 5055err_set_interrupt:
7a921c93
AD		 5056 return err;
5057}
5058
5059/**
5060 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5061 * @adapter: board private structure to clear interrupt scheme on
5062 *
5063 * We go through and clear interrupt specific resources and reset the structure
5064 * to pre-load conditions
5065 **/
5066void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5067{
4a0b9ca0
PW		 5068 int i;
5069
5070 for (i = 0; i < adapter->num_tx_queues; i++) {
5071 kfree(adapter->tx_ring[i]);
5072 adapter->tx_ring[i] = NULL;
5073 }
5074 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 5075 struct ixgbe_ring *ring = adapter->rx_ring[i];
5076
5077 /* ixgbe_get_stats64() might access this ring, we must wait
5078 * a grace period before freeing it.
5079 */
bcec8b65 5080 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 5081 adapter->rx_ring[i] = NULL;
5082 }
7a921c93 5083
b8eb3a10
DS		 5084 adapter->num_tx_queues = 0;
5085 adapter->num_rx_queues = 0;
5086
7a921c93
AD		 5087 ixgbe_free_q_vectors(adapter);
5088 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5089}
5090
5091/**
5092 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5093 * @adapter: board private structure to initialize
5094 *
5095 * ixgbe_sw_init initializes the Adapter private data structure.
5096 * Fields are initialized based on PCI device information and
5097 * OS network device settings (MTU size).
5098 **/
5099static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5100{
5101 struct ixgbe_hw *hw = &adapter->hw;
5102 struct pci_dev *pdev = adapter->pdev;
9a713e7c 5103 struct net_device *dev = adapter->netdev;
021230d4 5104 unsigned int rss;
7a6b6f51 5105#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5106 int j;
5107 struct tc_configuration *tc;
5108#endif
16b61beb 5109 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 5110
c44ade9e
JB		 5111 /* PCI config space info */
5112
5113 hw->vendor_id = pdev->vendor;
5114 hw->device_id = pdev->device;
5115 hw->revision_id = pdev->revision;
5116 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5117 hw->subsystem_device_id = pdev->subsystem_device;
5118
021230d4
AV		 5119 /* Set capability flags */
5120 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5121 adapter->ring_feature[RING_F_RSS].indices = rss;
5122 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 5123 switch (hw->mac.type) {
5124 case ixgbe_mac_82598EB:
bf069c97
DS		 5125 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5126 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5127 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178
AD		 5128 break;
5129 case ixgbe_mac_82599EB:
b93a2226 5130 case ixgbe_mac_X540:
e8e26350 5131 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5132 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5133 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5134 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5135 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5136 /* n-tuple support exists, always init our spinlock */
5137 spin_lock_init(&adapter->fdir_perfect_lock);
5138 /* Flow Director hash filters enabled */
5139 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5140 adapter->atr_sample_rate = 20;
c4cf55e5 5141 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5142 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 5143 adapter->fdir_pballoc = 0;
eacd73f7 5144#ifdef IXGBE_FCOE
0d551589
YZ		 5145 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5146 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5147 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5148#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 5149 /* Default traffic class to use for FCoE */
5150 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 5151 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5152#endif
eacd73f7 5153#endif /* IXGBE_FCOE */
bd508178
AD		 5154 break;
5155 default:
5156 break;
f8212f97 5157 }
2f90b865 5158
7a6b6f51 5159#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5160 /* Configure DCB traffic classes */
5161 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5162 tc = &adapter->dcb_cfg.tc_config[j];
5163 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5164 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5165 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5166 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5167 tc->dcb_pfc = pfc_disabled;
5168 }
5169 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5170 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5171 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5172 adapter->dcb_set_bitmap = 0x00;
3032309b 5173 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5174 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5175 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5176
5177#endif
9a799d71
AK		 5178
5179 /* default flow control settings */
cd7664f6 5180 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5181 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5182#ifdef CONFIG_DCB
5183 adapter->last_lfc_mode = hw->fc.current_mode;
5184#endif
16b61beb
JF		 5185 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5186 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 5187 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5188 hw->fc.send_xon = true;
71fd570b 5189 hw->fc.disable_fc_autoneg = false;
9a799d71 5190
30efa5a3 5191 /* enable itr by default in dynamic mode */
f7554a2b
NS		 5192 adapter->rx_itr_setting = 1;
5193 adapter->rx_eitr_param = 20000;
5194 adapter->tx_itr_setting = 1;
5195 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 5196
5197 /* set defaults for eitr in MegaBytes */
5198 adapter->eitr_low = 10;
5199 adapter->eitr_high = 20;
5200
5201 /* set default ring sizes */
5202 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5203 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5204
9a799d71 5205 /* initialize eeprom parameters */
c44ade9e 5206 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5207 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5208 return -EIO;
5209 }
5210
021230d4 5211 /* enable rx csum by default */
9a799d71
AK		 5212 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5213
1a6c14a2
JB		 5214 /* get assigned NUMA node */
5215 adapter->node = dev_to_node(&pdev->dev);
5216
9a799d71
AK		 5217 set_bit(__IXGBE_DOWN, &adapter->state);
5218
5219 return 0;
5220}
5221
5222/**
5223 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5224 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5225 *
5226 * Return 0 on success, negative on failure
5227 **/
b6ec895e 5228int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5229{
b6ec895e 5230 struct device *dev = tx_ring->dev;
9a799d71
AK		 5231 int size;
5232
3a581073 5233 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5234 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5235 if (!tx_ring->tx_buffer_info)
89bf67f1 5236 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5237 if (!tx_ring->tx_buffer_info)
5238 goto err;
9a799d71
AK		 5239
5240 /* round up to nearest 4K */
12207e49 5241 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5242 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5243
b6ec895e 5244 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5245 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5246 if (!tx_ring->desc)
5247 goto err;
9a799d71 5248
3a581073
JB		 5249 tx_ring->next_to_use = 0;
5250 tx_ring->next_to_clean = 0;
5251 tx_ring->work_limit = tx_ring->count;
9a799d71 5252 return 0;
e01c31a5
JB		 5253
5254err:
5255 vfree(tx_ring->tx_buffer_info);
5256 tx_ring->tx_buffer_info = NULL;
b6ec895e 5257 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5258 return -ENOMEM;
9a799d71
AK		 5259}
5260
69888674
AD		 5261/**
5262 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5263 * @adapter: board private structure
5264 *
5265 * If this function returns with an error, then it's possible one or
5266 * more of the rings is populated (while the rest are not). It is the
5267 * callers duty to clean those orphaned rings.
5268 *
5269 * Return 0 on success, negative on failure
5270 **/
5271static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5272{
5273 int i, err = 0;
5274
5275 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5276 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5277 if (!err)
5278 continue;
396e799c 5279 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5280 break;
5281 }
5282
5283 return err;
5284}
5285
9a799d71
AK		 5286/**
5287 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5288 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5289 *
5290 * Returns 0 on success, negative on failure
5291 **/
b6ec895e 5292int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5293{
b6ec895e 5294 struct device *dev = rx_ring->dev;
021230d4 5295 int size;
9a799d71 5296
3a581073 5297 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5298 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5299 if (!rx_ring->rx_buffer_info)
89bf67f1 5300 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5301 if (!rx_ring->rx_buffer_info)
5302 goto err;
9a799d71 5303
9a799d71 5304 /* Round up to nearest 4K */
3a581073
JB		 5305 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5306 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5307
b6ec895e 5308 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5309 &rx_ring->dma, GFP_KERNEL);
9a799d71 5310
b6ec895e
AD		 5311 if (!rx_ring->desc)
5312 goto err;
9a799d71 5313
3a581073
JB		 5314 rx_ring->next_to_clean = 0;
5315 rx_ring->next_to_use = 0;
9a799d71
AK		 5316
5317 return 0;
b6ec895e
AD		 5318err:
5319 vfree(rx_ring->rx_buffer_info);
5320 rx_ring->rx_buffer_info = NULL;
5321 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5322 return -ENOMEM;
9a799d71
AK		 5323}
5324
69888674
AD		 5325/**
5326 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5327 * @adapter: board private structure
5328 *
5329 * If this function returns with an error, then it's possible one or
5330 * more of the rings is populated (while the rest are not). It is the
5331 * callers duty to clean those orphaned rings.
5332 *
5333 * Return 0 on success, negative on failure
5334 **/
69888674
AD		 5335static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5336{
5337 int i, err = 0;
5338
5339 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5340 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5341 if (!err)
5342 continue;
396e799c 5343 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5344 break;
5345 }
5346
5347 return err;
5348}
5349
9a799d71
AK		 5350/**
5351 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5352 * @tx_ring: Tx descriptor ring for a specific queue
5353 *
5354 * Free all transmit software resources
5355 **/
b6ec895e 5356void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5357{
b6ec895e 5358 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5359
5360 vfree(tx_ring->tx_buffer_info);
5361 tx_ring->tx_buffer_info = NULL;
5362
b6ec895e
AD		 5363 /* if not set, then don't free */
5364 if (!tx_ring->desc)
5365 return;
5366
5367 dma_free_coherent(tx_ring->dev, tx_ring->size,
5368 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5369
5370 tx_ring->desc = NULL;
5371}
5372
5373/**
5374 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5375 * @adapter: board private structure
5376 *
5377 * Free all transmit software resources
5378 **/
5379static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5380{
5381 int i;
5382
5383 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5384 if (adapter->tx_ring[i]->desc)
b6ec895e 5385 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5386}
5387
5388/**
b4617240 5389 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5390 * @rx_ring: ring to clean the resources from
5391 *
5392 * Free all receive software resources
5393 **/
b6ec895e 5394void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5395{
b6ec895e 5396 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5397
5398 vfree(rx_ring->rx_buffer_info);
5399 rx_ring->rx_buffer_info = NULL;
5400
b6ec895e
AD		 5401 /* if not set, then don't free */
5402 if (!rx_ring->desc)
5403 return;
5404
5405 dma_free_coherent(rx_ring->dev, rx_ring->size,
5406 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5407
5408 rx_ring->desc = NULL;
5409}
5410
5411/**
5412 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5413 * @adapter: board private structure
5414 *
5415 * Free all receive software resources
5416 **/
5417static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5418{
5419 int i;
5420
5421 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5422 if (adapter->rx_ring[i]->desc)
b6ec895e 5423 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5424}
5425
9a799d71
AK		 5426/**
5427 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5428 * @netdev: network interface device structure
5429 * @new_mtu: new value for maximum frame size
5430 *
5431 * Returns 0 on success, negative on failure
5432 **/
5433static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5434{
5435 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5436 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5437 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5438
42c783c5 5439 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5440 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5441 hw->mac.type != ixgbe_mac_X540) {
5442 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5443 return -EINVAL;
5444 } else {
5445 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5446 return -EINVAL;
5447 }
9a799d71 5448
396e799c 5449 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5450 /* must set new MTU before calling down or up */
9a799d71
AK		 5451 netdev->mtu = new_mtu;
5452
16b61beb
JF		 5453 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5454 hw->fc.low_water = FC_LOW_WATER(max_frame);
5455
d4f80882
AV		 5456 if (netif_running(netdev))
5457 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5458
5459 return 0;
5460}
5461
5462/**
5463 * ixgbe_open - Called when a network interface is made active
5464 * @netdev: network interface device structure
5465 *
5466 * Returns 0 on success, negative value on failure
5467 *
5468 * The open entry point is called when a network interface is made
5469 * active by the system (IFF_UP). At this point all resources needed
5470 * for transmit and receive operations are allocated, the interrupt
5471 * handler is registered with the OS, the watchdog timer is started,
5472 * and the stack is notified that the interface is ready.
5473 **/
5474static int ixgbe_open(struct net_device *netdev)
5475{
5476 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5477 int err;
4bebfaa5
AK		 5478
5479 /* disallow open during test */
5480 if (test_bit(__IXGBE_TESTING, &adapter->state))
5481 return -EBUSY;
9a799d71 5482
54386467
JB		 5483 netif_carrier_off(netdev);
5484
9a799d71
AK		 5485 /* allocate transmit descriptors */
5486 err = ixgbe_setup_all_tx_resources(adapter);
5487 if (err)
5488 goto err_setup_tx;
5489
9a799d71
AK		 5490 /* allocate receive descriptors */
5491 err = ixgbe_setup_all_rx_resources(adapter);
5492 if (err)
5493 goto err_setup_rx;
5494
5495 ixgbe_configure(adapter);
5496
021230d4 5497 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5498 if (err)
5499 goto err_req_irq;
5500
9a799d71
AK		 5501 err = ixgbe_up_complete(adapter);
5502 if (err)
5503 goto err_up;
5504
d55b53ff
JK		 5505 netif_tx_start_all_queues(netdev);
5506
9a799d71
AK		 5507 return 0;
5508
5509err_up:
5eba3699 5510 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5511 ixgbe_free_irq(adapter);
5512err_req_irq:
9a799d71 5513err_setup_rx:
a20a1199 5514 ixgbe_free_all_rx_resources(adapter);
9a799d71 5515err_setup_tx:
a20a1199 5516 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5517 ixgbe_reset(adapter);
5518
5519 return err;
5520}
5521
5522/**
5523 * ixgbe_close - Disables a network interface
5524 * @netdev: network interface device structure
5525 *
5526 * Returns 0, this is not allowed to fail
5527 *
5528 * The close entry point is called when an interface is de-activated
5529 * by the OS. The hardware is still under the drivers control, but
5530 * needs to be disabled. A global MAC reset is issued to stop the
5531 * hardware, and all transmit and receive resources are freed.
5532 **/
5533static int ixgbe_close(struct net_device *netdev)
5534{
5535 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5536
5537 ixgbe_down(adapter);
5538 ixgbe_free_irq(adapter);
5539
5540 ixgbe_free_all_tx_resources(adapter);
5541 ixgbe_free_all_rx_resources(adapter);
5542
5eba3699 5543 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5544
5545 return 0;
5546}
5547
b3c8b4ba
AD		 5548#ifdef CONFIG_PM
5549static int ixgbe_resume(struct pci_dev *pdev)
5550{
c60fbb00
AD		 5551 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5552 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5553 u32 err;
5554
5555 pci_set_power_state(pdev, PCI_D0);
5556 pci_restore_state(pdev);
656ab817
DS		 5557 /*
5558 * pci_restore_state clears dev->state_saved so call
5559 * pci_save_state to restore it.
5560 */
5561 pci_save_state(pdev);
9ce77666 5562
5563 err = pci_enable_device_mem(pdev);
b3c8b4ba 5564 if (err) {
849c4542 5565 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5566 return err;
5567 }
5568 pci_set_master(pdev);
5569
dd4d8ca6 5570 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5571
5572 err = ixgbe_init_interrupt_scheme(adapter);
5573 if (err) {
849c4542 5574 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5575 return err;
5576 }
5577
b3c8b4ba
AD		 5578 ixgbe_reset(adapter);
5579
495dce12
WJP		 5580 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5581
b3c8b4ba 5582 if (netif_running(netdev)) {
c60fbb00 5583 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5584 if (err)
5585 return err;
5586 }
5587
5588 netif_device_attach(netdev);
5589
5590 return 0;
5591}
b3c8b4ba 5592#endif /* CONFIG_PM */
9d8d05ae
RW		 5593
5594static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5595{
c60fbb00
AD		 5596 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5597 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5598 struct ixgbe_hw *hw = &adapter->hw;
5599 u32 ctrl, fctrl;
5600 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5601#ifdef CONFIG_PM
5602 int retval = 0;
5603#endif
5604
5605 netif_device_detach(netdev);
5606
5607 if (netif_running(netdev)) {
5608 ixgbe_down(adapter);
5609 ixgbe_free_irq(adapter);
5610 ixgbe_free_all_tx_resources(adapter);
5611 ixgbe_free_all_rx_resources(adapter);
5612 }
b3c8b4ba 5613
5f5ae6fc 5614 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5615#ifdef CONFIG_DCB
5616 kfree(adapter->ixgbe_ieee_pfc);
5617 kfree(adapter->ixgbe_ieee_ets);
5618#endif
5f5ae6fc 5619
b3c8b4ba
AD		 5620#ifdef CONFIG_PM
5621 retval = pci_save_state(pdev);
5622 if (retval)
5623 return retval;
4df10466 5624
b3c8b4ba 5625#endif
e8e26350
PW		 5626 if (wufc) {
5627 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5628
e8e26350
PW		 5629 /* turn on all-multi mode if wake on multicast is enabled */
5630 if (wufc & IXGBE_WUFC_MC) {
5631 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5632 fctrl |= IXGBE_FCTRL_MPE;
5633 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5634 }
5635
5636 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5637 ctrl |= IXGBE_CTRL_GIO_DIS;
5638 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5639
5640 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5641 } else {
5642 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5643 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5644 }
5645
bd508178
AD		 5646 switch (hw->mac.type) {
5647 case ixgbe_mac_82598EB:
dd4d8ca6 5648 pci_wake_from_d3(pdev, false);
bd508178
AD		 5649 break;
5650 case ixgbe_mac_82599EB:
b93a2226 5651 case ixgbe_mac_X540:
bd508178
AD		 5652 pci_wake_from_d3(pdev, !!wufc);
5653 break;
5654 default:
5655 break;
5656 }
b3c8b4ba 5657
9d8d05ae
RW		 5658 *enable_wake = !!wufc;
5659
b3c8b4ba
AD		 5660 ixgbe_release_hw_control(adapter);
5661
5662 pci_disable_device(pdev);
5663
9d8d05ae
RW		 5664 return 0;
5665}
5666
5667#ifdef CONFIG_PM
5668static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5669{
5670 int retval;
5671 bool wake;
5672
5673 retval = __ixgbe_shutdown(pdev, &wake);
5674 if (retval)
5675 return retval;
5676
5677 if (wake) {
5678 pci_prepare_to_sleep(pdev);
5679 } else {
5680 pci_wake_from_d3(pdev, false);
5681 pci_set_power_state(pdev, PCI_D3hot);
5682 }
b3c8b4ba
AD		 5683
5684 return 0;
5685}
9d8d05ae 5686#endif /* CONFIG_PM */
b3c8b4ba
AD		 5687
5688static void ixgbe_shutdown(struct pci_dev *pdev)
5689{
9d8d05ae
RW		 5690 bool wake;
5691
5692 __ixgbe_shutdown(pdev, &wake);
5693
5694 if (system_state == SYSTEM_POWER_OFF) {
5695 pci_wake_from_d3(pdev, wake);
5696 pci_set_power_state(pdev, PCI_D3hot);
5697 }
b3c8b4ba
AD		 5698}
5699
9a799d71
AK		 5700/**
5701 * ixgbe_update_stats - Update the board statistics counters.
5702 * @adapter: board private structure
5703 **/
5704void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5705{
2d86f139 5706 struct net_device *netdev = adapter->netdev;
9a799d71 5707 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5708 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5709 u64 total_mpc = 0;
5710 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5711 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5712 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5713 u64 bytes = 0, packets = 0;
9a799d71 5714
d08935c2
DS		 5715 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5716 test_bit(__IXGBE_RESETTING, &adapter->state))
5717 return;
5718
94b982b2 5719 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5720 u64 rsc_count = 0;
94b982b2 5721 u64 rsc_flush = 0;
d51019a4
PW		 5722 for (i = 0; i < 16; i++)
5723 adapter->hw_rx_no_dma_resources +=
7ca647bd 5724 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5725 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5726 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5727 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5728 }
5729 adapter->rsc_total_count = rsc_count;
5730 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5731 }
5732
5b7da515
AD		 5733 for (i = 0; i < adapter->num_rx_queues; i++) {
5734 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5735 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5736 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5737 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5738 bytes += rx_ring->stats.bytes;
5739 packets += rx_ring->stats.packets;
5740 }
5741 adapter->non_eop_descs = non_eop_descs;
5742 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5743 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5744 netdev->stats.rx_bytes = bytes;
5745 netdev->stats.rx_packets = packets;
5746
5747 bytes = 0;
5748 packets = 0;
7ca3bc58 5749 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5750 for (i = 0; i < adapter->num_tx_queues; i++) {
5751 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5752 restart_queue += tx_ring->tx_stats.restart_queue;
5753 tx_busy += tx_ring->tx_stats.tx_busy;
5754 bytes += tx_ring->stats.bytes;
5755 packets += tx_ring->stats.packets;
5756 }
eb985f09 5757 adapter->restart_queue = restart_queue;
5b7da515
AD		 5758 adapter->tx_busy = tx_busy;
5759 netdev->stats.tx_bytes = bytes;
5760 netdev->stats.tx_packets = packets;
7ca3bc58 5761
7ca647bd 5762 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5763 for (i = 0; i < 8; i++) {
5764 /* for packet buffers not used, the register should read 0 */
5765 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5766 missed_rx += mpc;
7ca647bd
JP		 5767 hwstats->mpc[i] += mpc;
5768 total_mpc += hwstats->mpc[i];
e8e26350 5769 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5770 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5771 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5772 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5773 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5774 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
bd508178
AD		 5775 switch (hw->mac.type) {
5776 case ixgbe_mac_82598EB:
7ca647bd
JP		 5777 hwstats->pxonrxc[i] +=
5778 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5779 break;
5780 case ixgbe_mac_82599EB:
b93a2226 5781 case ixgbe_mac_X540:
bd508178
AD		 5782 hwstats->pxonrxc[i] +=
5783 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5784 break;
5785 default:
5786 break;
e8e26350 5787 }
7ca647bd
JP		 5788 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5789 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5790 }
7ca647bd 5791 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5792 /* work around hardware counting issue */
7ca647bd 5793 hwstats->gprc -= missed_rx;
6f11eef7 5794
c84d324c
JF		 5795 ixgbe_update_xoff_received(adapter);
5796
6f11eef7 5797 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5798 switch (hw->mac.type) {
5799 case ixgbe_mac_82598EB:
5800 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5801 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5802 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5803 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5804 break;
b93a2226 5805 case ixgbe_mac_X540:
58f6bcf9
ET		 5806 /* OS2BMC stats are X540 only*/
5807 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5808 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5809 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5810 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5811 case ixgbe_mac_82599EB:
7ca647bd 5812 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5813 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5814 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5815 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5816 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5817 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5818 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5819 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5820 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5821#ifdef IXGBE_FCOE
7ca647bd
JP		 5822 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5823 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5824 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5825 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5826 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5827 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5828#endif /* IXGBE_FCOE */
bd508178
AD		 5829 break;
5830 default:
5831 break;
e8e26350 5832 }
9a799d71 5833 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5834 hwstats->bprc += bprc;
5835 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5836 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5837 hwstats->mprc -= bprc;
5838 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5839 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5840 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5841 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5842 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5843 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5844 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5845 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5846 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5847 hwstats->lxontxc += lxon;
6f11eef7 5848 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5849 hwstats->lxofftxc += lxoff;
5850 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5851 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5852 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5853 /*
5854 * 82598 errata - tx of flow control packets is included in tx counters
5855 */
5856 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5857 hwstats->gptc -= xon_off_tot;
5858 hwstats->mptc -= xon_off_tot;
5859 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5860 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5861 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5862 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5863 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5864 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5865 hwstats->ptc64 -= xon_off_tot;
5866 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5867 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5868 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5869 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5870 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5871 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5872
5873 /* Fill out the OS statistics structure */
7ca647bd 5874 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5875
5876 /* Rx Errors */
7ca647bd 5877 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5878 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5879 netdev->stats.rx_length_errors = hwstats->rlec;
5880 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5881 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5882}
5883
5884/**
d034acf1
AD		 5885 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5886 * @adapter - pointer to the device adapter structure
9a799d71 5887 **/
d034acf1 5888static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5889{
cf8280ee 5890 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5891 int i;
cf8280ee 5892
d034acf1
AD		 5893 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5894 return;
5895
5896 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5897
d034acf1 5898 /* if interface is down do nothing */
fe49f04a 5899 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5900 return;
5901
5902 /* do nothing if we are not using signature filters */
5903 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5904 return;
5905
5906 adapter->fdir_overflow++;
5907
93c52dd0
AD		 5908 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5909 for (i = 0; i < adapter->num_tx_queues; i++)
5910 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5911 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5912 /* re-enable flow director interrupts */
5913 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5914 } else {
5915 e_err(probe, "failed to finish FDIR re-initialization, "
5916 "ignored adding FDIR ATR filters\n");
5917 }
93c52dd0
AD		 5918}
5919
5920/**
5921 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5922 * @adapter - pointer to the device adapter structure
5923 *
5924 * This function serves two purposes. First it strobes the interrupt lines
5925 * in order to make certain interrupts are occuring. Secondly it sets the
5926 * bits needed to check for TX hangs. As a result we should immediately
5927 * determine if a hang has occured.
5928 */
5929static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5930{
cf8280ee 5931 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5932 u64 eics = 0;
5933 int i;
cf8280ee 5934
93c52dd0
AD		 5935 /* If we're down or resetting, just bail */
5936 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5937 test_bit(__IXGBE_RESETTING, &adapter->state))
5938 return;
22d5a71b 5939
93c52dd0
AD		 5940 /* Force detection of hung controller */
5941 if (netif_carrier_ok(adapter->netdev)) {
5942 for (i = 0; i < adapter->num_tx_queues; i++)
5943 set_check_for_tx_hang(adapter->tx_ring[i]);
5944 }
22d5a71b 5945
fe49f04a
AD		 5946 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5947 /*
5948 * for legacy and MSI interrupts don't set any bits
5949 * that are enabled for EIAM, because this operation
5950 * would set *both* EIMS and EICS for any bit in EIAM
5951 */
5952 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5953 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5954 } else {
5955 /* get one bit for every active tx/rx interrupt vector */
5956 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5957 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5958 if (qv->rxr_count || qv->txr_count)
5959 eics |= ((u64)1 << i);
5960 }
cf8280ee 5961 }
9a799d71 5962
93c52dd0 5963 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5964 ixgbe_irq_rearm_queues(adapter, eics);
5965
cf8280ee
JB		 5966}
5967
e8e26350 5968/**
93c52dd0
AD		 5969 * ixgbe_watchdog_update_link - update the link status
5970 * @adapter - pointer to the device adapter structure
5971 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 5972 **/
93c52dd0 5973static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5974{
e8e26350 5975 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5976 u32 link_speed = adapter->link_speed;
5977 bool link_up = adapter->link_up;
c4cf55e5 5978 int i;
e8e26350 5979
93c52dd0
AD		 5980 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5981 return;
5982
5983 if (hw->mac.ops.check_link) {
5984 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5985 } else {
93c52dd0
AD		 5986 /* always assume link is up, if no check link function */
5987 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5988 link_up = true;
c4cf55e5 5989 }
93c52dd0
AD		 5990 if (link_up) {
5991 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5992 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5993 hw->mac.ops.fc_enable(hw, i);
5994 } else {
5995 hw->mac.ops.fc_enable(hw, 0);
5996 }
5997 }
5998
5999 if (link_up ||
6000 time_after(jiffies, (adapter->link_check_timeout +
6001 IXGBE_TRY_LINK_TIMEOUT))) {
6002 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6003 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6004 IXGBE_WRITE_FLUSH(hw);
6005 }
6006
6007 adapter->link_up = link_up;
6008 adapter->link_speed = link_speed;
e8e26350
PW		 6009}
6010
6011/**
93c52dd0
AD		 6012 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6013 * print link up message
6014 * @adapter - pointer to the device adapter structure
e8e26350 6015 **/
93c52dd0 6016static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6017{
93c52dd0 6018 struct net_device *netdev = adapter->netdev;
e8e26350 6019 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6020 u32 link_speed = adapter->link_speed;
6021 bool flow_rx, flow_tx;
e8e26350 6022
93c52dd0
AD		 6023 /* only continue if link was previously down */
6024 if (netif_carrier_ok(netdev))
a985b6c3 6025 return;
63d6e1d8 6026
93c52dd0 6027 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6028
93c52dd0
AD		 6029 switch (hw->mac.type) {
6030 case ixgbe_mac_82598EB: {
6031 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6032 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6033 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6034 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6035 }
6036 break;
6037 case ixgbe_mac_X540:
6038 case ixgbe_mac_82599EB: {
6039 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6040 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6041 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6042 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6043 }
6044 break;
6045 default:
6046 flow_tx = false;
6047 flow_rx = false;
6048 break;
e8e26350 6049 }
93c52dd0
AD		 6050 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6051 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6052 "10 Gbps" :
6053 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6054 "1 Gbps" :
6055 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6056 "100 Mbps" :
6057 "unknown speed"))),
6058 ((flow_rx && flow_tx) ? "RX/TX" :
6059 (flow_rx ? "RX" :
6060 (flow_tx ? "TX" : "None"))));
e8e26350 6061
93c52dd0
AD		 6062 netif_carrier_on(netdev);
6063#ifdef HAVE_IPLINK_VF_CONFIG
6064 ixgbe_check_vf_rate_limit(adapter);
6065#endif /* HAVE_IPLINK_VF_CONFIG */
e8e26350
PW		 6066}
6067
c4cf55e5 6068/**
93c52dd0
AD		 6069 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6070 * print link down message
6071 * @adapter - pointer to the adapter structure
c4cf55e5 6072 **/
93c52dd0 6073static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 6074{
cf8280ee 6075 struct net_device *netdev = adapter->netdev;
c4cf55e5 6076 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6077
93c52dd0
AD		 6078 adapter->link_up = false;
6079 adapter->link_speed = 0;
cf8280ee 6080
93c52dd0
AD		 6081 /* only continue if link was up previously */
6082 if (!netif_carrier_ok(netdev))
6083 return;
264857b8 6084
93c52dd0
AD		 6085 /* poll for SFP+ cable when link is down */
6086 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6087 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6088
93c52dd0
AD		 6089 e_info(drv, "NIC Link is Down\n");
6090 netif_carrier_off(netdev);
6091}
e8e26350 6092
93c52dd0
AD		 6093/**
6094 * ixgbe_watchdog_flush_tx - flush queues on link down
6095 * @adapter - pointer to the device adapter structure
6096 **/
6097static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6098{
c4cf55e5 6099 int i;
93c52dd0 6100 int some_tx_pending = 0;
c4cf55e5 6101
93c52dd0 6102 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6103 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6104 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6105 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6106 some_tx_pending = 1;
6107 break;
6108 }
6109 }
6110
6111 if (some_tx_pending) {
6112 /* We've lost link, so the controller stops DMA,
6113 * but we've got queued Tx work that's never going
6114 * to get done, so reset controller to flush Tx.
6115 * (Do the reset outside of interrupt context).
6116 */
c83c6cbd 6117 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6118 }
c4cf55e5 6119 }
c4cf55e5
PWJ		 6120}
6121
a985b6c3
GR		 6122static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6123{
6124 u32 ssvpc;
6125
6126 /* Do not perform spoof check for 82598 */
6127 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6128 return;
6129
6130 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6131
6132 /*
6133 * ssvpc register is cleared on read, if zero then no
6134 * spoofed packets in the last interval.
6135 */
6136 if (!ssvpc)
6137 return;
6138
6139 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6140}
6141
93c52dd0
AD		 6142/**
6143 * ixgbe_watchdog_subtask - check and bring link up
6144 * @adapter - pointer to the device adapter structure
6145 **/
6146static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6147{
6148 /* if interface is down do nothing */
6149 if (test_bit(__IXGBE_DOWN, &adapter->state))
6150 return;
6151
6152 ixgbe_watchdog_update_link(adapter);
6153
6154 if (adapter->link_up)
6155 ixgbe_watchdog_link_is_up(adapter);
6156 else
6157 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6158
a985b6c3 6159 ixgbe_spoof_check(adapter);
9a799d71 6160 ixgbe_update_stats(adapter);
93c52dd0
AD		 6161
6162 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6163}
10eec955 6164
cf8280ee 6165/**
7086400d
AD		 6166 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6167 * @adapter - the ixgbe adapter structure
cf8280ee 6168 **/
7086400d 6169static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6170{
cf8280ee 6171 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6172 s32 err;
cf8280ee 6173
7086400d
AD		 6174 /* not searching for SFP so there is nothing to do here */
6175 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6176 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6177 return;
10eec955 6178
7086400d
AD		 6179 /* someone else is in init, wait until next service event */
6180 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6181 return;
cf8280ee 6182
7086400d
AD		 6183 err = hw->phy.ops.identify_sfp(hw);
6184 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6185 goto sfp_out;
264857b8 6186
7086400d
AD		 6187 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6188 /* If no cable is present, then we need to reset
6189 * the next time we find a good cable. */
6190 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6191 }
9a799d71 6192
7086400d
AD		 6193 /* exit on error */
6194 if (err)
6195 goto sfp_out;
e8e26350 6196
7086400d
AD		 6197 /* exit if reset not needed */
6198 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6199 goto sfp_out;
9a799d71 6200
7086400d 6201 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6202
7086400d
AD		 6203 /*
6204 * A module may be identified correctly, but the EEPROM may not have
6205 * support for that module. setup_sfp() will fail in that case, so
6206 * we should not allow that module to load.
6207 */
6208 if (hw->mac.type == ixgbe_mac_82598EB)
6209 err = hw->phy.ops.reset(hw);
6210 else
6211 err = hw->mac.ops.setup_sfp(hw);
6212
6213 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6214 goto sfp_out;
6215
6216 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6217 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6218
6219sfp_out:
6220 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6221
6222 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6223 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6224 e_dev_err("failed to initialize because an unsupported "
6225 "SFP+ module type was detected.\n");
6226 e_dev_err("Reload the driver after installing a "
6227 "supported module.\n");
6228 unregister_netdev(adapter->netdev);
bc59fcda 6229 }
7086400d 6230}
bc59fcda 6231
7086400d
AD		 6232/**
6233 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6234 * @adapter - the ixgbe adapter structure
6235 **/
6236static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6237{
6238 struct ixgbe_hw *hw = &adapter->hw;
6239 u32 autoneg;
6240 bool negotiation;
6241
6242 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6243 return;
6244
6245 /* someone else is in init, wait until next service event */
6246 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6247 return;
6248
6249 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6250
6251 autoneg = hw->phy.autoneg_advertised;
6252 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6253 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6254 hw->mac.autotry_restart = false;
6255 if (hw->mac.ops.setup_link)
6256 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6257
6258 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6259 adapter->link_check_timeout = jiffies;
6260 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6261}
6262
6263/**
6264 * ixgbe_service_timer - Timer Call-back
6265 * @data: pointer to adapter cast into an unsigned long
6266 **/
6267static void ixgbe_service_timer(unsigned long data)
6268{
6269 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6270 unsigned long next_event_offset;
6271
6272 /* poll faster when waiting for link */
6273 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6274 next_event_offset = HZ / 10;
6275 else
6276 next_event_offset = HZ * 2;
6277
6278 /* Reset the timer */
6279 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6280
6281 ixgbe_service_event_schedule(adapter);
6282}
6283
c83c6cbd
AD		 6284static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6285{
6286 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6287 return;
6288
6289 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6290
6291 /* If we're already down or resetting, just bail */
6292 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6293 test_bit(__IXGBE_RESETTING, &adapter->state))
6294 return;
6295
6296 ixgbe_dump(adapter);
6297 netdev_err(adapter->netdev, "Reset adapter\n");
6298 adapter->tx_timeout_count++;
6299
6300 ixgbe_reinit_locked(adapter);
6301}
6302
7086400d
AD		 6303/**
6304 * ixgbe_service_task - manages and runs subtasks
6305 * @work: pointer to work_struct containing our data
6306 **/
6307static void ixgbe_service_task(struct work_struct *work)
6308{
6309 struct ixgbe_adapter *adapter = container_of(work,
6310 struct ixgbe_adapter,
6311 service_task);
6312
c83c6cbd 6313 ixgbe_reset_subtask(adapter);
7086400d
AD		 6314 ixgbe_sfp_detection_subtask(adapter);
6315 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6316 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6317 ixgbe_watchdog_subtask(adapter);
d034acf1 6318 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6319 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6320
6321 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6322}
6323
9a799d71 6324static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696 6325 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5e09a105 6326 u32 tx_flags, u8 *hdr_len, __be16 protocol)
9a799d71
AK		 6327{
6328 struct ixgbe_adv_tx_context_desc *context_desc;
6329 unsigned int i;
6330 int err;
6331 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 6332 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6333 u32 mss_l4len_idx, l4len;
9a799d71
AK		 6334
6335 if (skb_is_gso(skb)) {
6336 if (skb_header_cloned(skb)) {
6337 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6338 if (err)
6339 return err;
6340 }
6341 l4len = tcp_hdrlen(skb);
6342 *hdr_len += l4len;
6343
5e09a105 6344 if (protocol == htons(ETH_P_IP)) {
9a799d71
AK		 6345 struct iphdr *iph = ip_hdr(skb);
6346 iph->tot_len = 0;
6347 iph->check = 0;
6348 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 6349 iph->daddr, 0,
6350 IPPROTO_TCP,
6351 0);
8e1e8a47 6352 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 6353 ipv6_hdr(skb)->payload_len = 0;
6354 tcp_hdr(skb)->check =
6355 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 6356 &ipv6_hdr(skb)->daddr,
6357 0, IPPROTO_TCP, 0);
9a799d71
AK		 6358 }
6359
6360 i = tx_ring->next_to_use;
6361
6362 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6363 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6364
6365 /* VLAN MACLEN IPLEN */
6366 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6367 vlan_macip_lens |=
6368 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6369 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 6370 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6371 *hdr_len += skb_network_offset(skb);
6372 vlan_macip_lens |=
6373 (skb_transport_header(skb) - skb_network_header(skb));
6374 *hdr_len +=
6375 (skb_transport_header(skb) - skb_network_header(skb));
6376 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6377 context_desc->seqnum_seed = 0;
6378
6379 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 6380 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 6381 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6382
5e09a105 6383 if (protocol == htons(ETH_P_IP))
9a799d71
AK		 6384 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6385 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6386 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6387
6388 /* MSS L4LEN IDX */
9f8cdf4f 6389 mss_l4len_idx =
9a799d71
AK		 6390 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6391 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 6392 /* use index 1 for TSO */
6393 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6394 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6395
6396 tx_buffer_info->time_stamp = jiffies;
6397 tx_buffer_info->next_to_watch = i;
6398
6399 i++;
6400 if (i == tx_ring->count)
6401 i = 0;
6402 tx_ring->next_to_use = i;
6403
6404 return true;
6405 }
6406 return false;
6407}
6408
5e09a105
HZ		 6409static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6410 __be16 protocol)
7ca647bd
JP		 6411{
6412 u32 rtn = 0;
7ca647bd
JP		 6413
6414 switch (protocol) {
6415 case cpu_to_be16(ETH_P_IP):
6416 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6417 switch (ip_hdr(skb)->protocol) {
6418 case IPPROTO_TCP:
6419 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6420 break;
6421 case IPPROTO_SCTP:
6422 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6423 break;
6424 }
6425 break;
6426 case cpu_to_be16(ETH_P_IPV6):
6427 /* XXX what about other V6 headers?? */
6428 switch (ipv6_hdr(skb)->nexthdr) {
6429 case IPPROTO_TCP:
6430 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6431 break;
6432 case IPPROTO_SCTP:
6433 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6434 break;
6435 }
6436 break;
6437 default:
6438 if (unlikely(net_ratelimit()))
6439 e_warn(probe, "partial checksum but proto=%x!\n",
5e09a105 6440 protocol);
7ca647bd
JP		 6441 break;
6442 }
6443
6444 return rtn;
6445}
6446
9a799d71 6447static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696 6448 struct ixgbe_ring *tx_ring,
5e09a105
HZ		 6449 struct sk_buff *skb, u32 tx_flags,
6450 __be16 protocol)
9a799d71
AK		 6451{
6452 struct ixgbe_adv_tx_context_desc *context_desc;
6453 unsigned int i;
6454 struct ixgbe_tx_buffer *tx_buffer_info;
6455 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6456
6457 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6458 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6459 i = tx_ring->next_to_use;
6460 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6461 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6462
6463 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6464 vlan_macip_lens |=
6465 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6466 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 6467 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6468 if (skb->ip_summed == CHECKSUM_PARTIAL)
6469 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 6470 skb_network_header(skb));
9a799d71
AK		 6471
6472 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6473 context_desc->seqnum_seed = 0;
6474
6475 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 6476 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6477
7ca647bd 6478 if (skb->ip_summed == CHECKSUM_PARTIAL)
5e09a105 6479 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
9a799d71
AK		 6480
6481 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 6482 /* use index zero for tx checksum offload */
9a799d71
AK		 6483 context_desc->mss_l4len_idx = 0;
6484
6485 tx_buffer_info->time_stamp = jiffies;
6486 tx_buffer_info->next_to_watch = i;
9f8cdf4f 6487
9a799d71
AK		 6488 i++;
6489 if (i == tx_ring->count)
6490 i = 0;
6491 tx_ring->next_to_use = i;
6492
6493 return true;
6494 }
9f8cdf4f 6495
9a799d71
AK		 6496 return false;
6497}
6498
6499static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6500 struct ixgbe_ring *tx_ring,
6501 struct sk_buff *skb, u32 tx_flags,
8ad494b0 6502 unsigned int first, const u8 hdr_len)
9a799d71 6503{
b6ec895e 6504 struct device *dev = tx_ring->dev;
9a799d71 6505 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6506 unsigned int len;
6507 unsigned int total = skb->len;
9a799d71
AK		 6508 unsigned int offset = 0, size, count = 0, i;
6509 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6510 unsigned int f;
8ad494b0
AD		 6511 unsigned int bytecount = skb->len;
6512 u16 gso_segs = 1;
9a799d71
AK		 6513
6514 i = tx_ring->next_to_use;
6515
eacd73f7
YZ		 6516 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6517 /* excluding fcoe_crc_eof for FCoE */
6518 total -= sizeof(struct fcoe_crc_eof);
6519
6520 len = min(skb_headlen(skb), total);
9a799d71
AK		 6521 while (len) {
6522 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6523 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6524
6525 tx_buffer_info->length = size;
e5a43549 6526 tx_buffer_info->mapped_as_page = false;
b6ec895e 6527 tx_buffer_info->dma = dma_map_single(dev,
e5a43549 6528 skb->data + offset,
1b507730 6529 size, DMA_TO_DEVICE);
b6ec895e 6530 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6531 goto dma_error;
9a799d71
AK		 6532 tx_buffer_info->time_stamp = jiffies;
6533 tx_buffer_info->next_to_watch = i;
6534
6535 len -= size;
eacd73f7 6536 total -= size;
9a799d71
AK		 6537 offset += size;
6538 count++;
44df32c5
AD		 6539
6540 if (len) {
6541 i++;
6542 if (i == tx_ring->count)
6543 i = 0;
6544 }
9a799d71
AK		 6545 }
6546
6547 for (f = 0; f < nr_frags; f++) {
6548 struct skb_frag_struct *frag;
6549
6550 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6551 len = min((unsigned int)frag->size, total);
e5a43549 6552 offset = frag->page_offset;
9a799d71
AK		 6553
6554 while (len) {
44df32c5
AD		 6555 i++;
6556 if (i == tx_ring->count)
6557 i = 0;
6558
9a799d71
AK		 6559 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6560 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6561
6562 tx_buffer_info->length = size;
b6ec895e 6563 tx_buffer_info->dma = dma_map_page(dev,
e5a43549
AD		 6564 frag->page,
6565 offset, size,
1b507730 6566 DMA_TO_DEVICE);
e5a43549 6567 tx_buffer_info->mapped_as_page = true;
b6ec895e 6568 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6569 goto dma_error;
9a799d71
AK		 6570 tx_buffer_info->time_stamp = jiffies;
6571 tx_buffer_info->next_to_watch = i;
6572
6573 len -= size;
eacd73f7 6574 total -= size;
9a799d71
AK		 6575 offset += size;
6576 count++;
9a799d71 6577 }
eacd73f7
YZ		 6578 if (total == 0)
6579 break;
9a799d71 6580 }
44df32c5 6581
8ad494b0
AD		 6582 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6583 gso_segs = skb_shinfo(skb)->gso_segs;
6584#ifdef IXGBE_FCOE
6585 /* adjust for FCoE Sequence Offload */
6586 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6587 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6588 skb_shinfo(skb)->gso_size);
6589#endif /* IXGBE_FCOE */
6590 bytecount += (gso_segs - 1) * hdr_len;
6591
6592 /* multiply data chunks by size of headers */
6593 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6594 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
9a799d71
AK		 6595 tx_ring->tx_buffer_info[i].skb = skb;
6596 tx_ring->tx_buffer_info[first].next_to_watch = i;
6597
e5a43549
AD		 6598 return count;
6599
6600dma_error:
849c4542 6601 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6602
6603 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6604 tx_buffer_info->dma = 0;
6605 tx_buffer_info->time_stamp = 0;
6606 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6607 if (count)
6608 count--;
e5a43549
AD		 6609
6610 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6611 while (count--) {
e8e9f696 6612 if (i == 0)
e5a43549 6613 i += tx_ring->count;
c1fa347f 6614 i--;
e5a43549 6615 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 6616 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
e5a43549
AD		 6617 }
6618
e44d38e1 6619 return 0;
9a799d71
AK		 6620}
6621
84ea2591 6622static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
e8e9f696 6623 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6624{
6625 union ixgbe_adv_tx_desc *tx_desc = NULL;
6626 struct ixgbe_tx_buffer *tx_buffer_info;
6627 u32 olinfo_status = 0, cmd_type_len = 0;
6628 unsigned int i;
6629 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6630
6631 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6632
6633 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6634
6635 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6636 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6637
6638 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6639 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6640
6641 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6642 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6643
4eeae6fd
PW		 6644 /* use index 1 context for tso */
6645 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6646 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6647 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6648 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6649
6650 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6651 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6652 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6653
eacd73f7
YZ		 6654 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6655 olinfo_status |= IXGBE_ADVTXD_CC;
6656 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6657 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6658 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6659 }
6660
9a799d71
AK		 6661 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6662
6663 i = tx_ring->next_to_use;
6664 while (count--) {
6665 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6666 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6667 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6668 tx_desc->read.cmd_type_len =
e8e9f696 6669 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6670 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6671 i++;
6672 if (i == tx_ring->count)
6673 i = 0;
6674 }
6675
6676 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6677
6678 /*
6679 * Force memory writes to complete before letting h/w
6680 * know there are new descriptors to fetch. (Only
6681 * applicable for weak-ordered memory model archs,
6682 * such as IA-64).
6683 */
6684 wmb();
6685
6686 tx_ring->next_to_use = i;
84ea2591 6687 writel(i, tx_ring->tail);
9a799d71
AK		 6688}
6689
69830529
AD		 6690static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6691 u32 tx_flags, __be16 protocol)
6692{
6693 struct ixgbe_q_vector *q_vector = ring->q_vector;
6694 union ixgbe_atr_hash_dword input = { .dword = 0 };
6695 union ixgbe_atr_hash_dword common = { .dword = 0 };
6696 union {
6697 unsigned char *network;
6698 struct iphdr *ipv4;
6699 struct ipv6hdr *ipv6;
6700 } hdr;
ee9e0f0b 6701 struct tcphdr *th;
905e4a41 6702 __be16 vlan_id;
c4cf55e5 6703
69830529
AD		 6704 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6705 if (!q_vector)
6706 return;
6707
6708 /* do nothing if sampling is disabled */
6709 if (!ring->atr_sample_rate)
d3ead241 6710 return;
c4cf55e5 6711
69830529 6712 ring->atr_count++;
c4cf55e5 6713
69830529
AD		 6714 /* snag network header to get L4 type and address */
6715 hdr.network = skb_network_header(skb);
6716
6717 /* Currently only IPv4/IPv6 with TCP is supported */
6718 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6719 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6720 (protocol != __constant_htons(ETH_P_IP) ||
6721 hdr.ipv4->protocol != IPPROTO_TCP))
6722 return;
ee9e0f0b
AD		 6723
6724 th = tcp_hdr(skb);
c4cf55e5 6725
69830529
AD		 6726 /* skip this packet since the socket is closing */
6727 if (th->fin)
6728 return;
6729
6730 /* sample on all syn packets or once every atr sample count */
6731 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6732 return;
6733
6734 /* reset sample count */
6735 ring->atr_count = 0;
6736
6737 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6738
6739 /*
6740 * src and dst are inverted, think how the receiver sees them
6741 *
6742 * The input is broken into two sections, a non-compressed section
6743 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6744 * is XORed together and stored in the compressed dword.
6745 */
6746 input.formatted.vlan_id = vlan_id;
6747
6748 /*
6749 * since src port and flex bytes occupy the same word XOR them together
6750 * and write the value to source port portion of compressed dword
6751 */
6752 if (vlan_id)
6753 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6754 else
6755 common.port.src ^= th->dest ^ protocol;
6756 common.port.dst ^= th->source;
6757
6758 if (protocol == __constant_htons(ETH_P_IP)) {
6759 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6760 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6761 } else {
6762 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6763 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6764 hdr.ipv6->saddr.s6_addr32[1] ^
6765 hdr.ipv6->saddr.s6_addr32[2] ^
6766 hdr.ipv6->saddr.s6_addr32[3] ^
6767 hdr.ipv6->daddr.s6_addr32[0] ^
6768 hdr.ipv6->daddr.s6_addr32[1] ^
6769 hdr.ipv6->daddr.s6_addr32[2] ^
6770 hdr.ipv6->daddr.s6_addr32[3];
6771 }
c4cf55e5
PWJ		 6772
6773 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6774 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6775 input, common, ring->queue_index);
c4cf55e5
PWJ		 6776}
6777
fc77dc3c 6778static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60 6779{
fc77dc3c 6780 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6781 /* Herbert's original patch had:
6782 * smp_mb__after_netif_stop_queue();
6783 * but since that doesn't exist yet, just open code it. */
6784 smp_mb();
6785
6786 /* We need to check again in a case another CPU has just
6787 * made room available. */
6788 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6789 return -EBUSY;
6790
6791 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6792 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6793 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6794 return 0;
6795}
6796
fc77dc3c 6797static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6798{
6799 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6800 return 0;
fc77dc3c 6801 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6802}
6803
09a3b1f8
SH		 6804static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6805{
6806 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6807 int txq = smp_processor_id();
56075a98 6808#ifdef IXGBE_FCOE
5e09a105
HZ		 6809 __be16 protocol;
6810
6811 protocol = vlan_get_protocol(skb);
6812
e5b64635
JF		 6813 if (((protocol == htons(ETH_P_FCOE)) ||
6814 (protocol == htons(ETH_P_FIP))) &&
6815 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6816 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6817 txq += adapter->ring_feature[RING_F_FCOE].mask;
6818 return txq;
56075a98
JF		 6819 }
6820#endif
6821
fdd3d631
KK		 6822 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6823 while (unlikely(txq >= dev->real_num_tx_queues))
6824 txq -= dev->real_num_tx_queues;
5f715823 6825 return txq;
fdd3d631 6826 }
c4cf55e5 6827
09a3b1f8
SH		 6828 return skb_tx_hash(dev, skb);
6829}
6830
fc77dc3c 6831netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6832 struct ixgbe_adapter *adapter,
6833 struct ixgbe_ring *tx_ring)
9a799d71 6834{
9a799d71
AK		 6835 unsigned int first;
6836 unsigned int tx_flags = 0;
30eba97a 6837 u8 hdr_len = 0;
5f715823 6838 int tso;
9a799d71
AK		 6839 int count = 0;
6840 unsigned int f;
5e09a105
HZ		 6841 __be16 protocol;
6842
6843 protocol = vlan_get_protocol(skb);
9f8cdf4f 6844
eab6d18d 6845 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6846 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6847 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6848 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
e5b64635 6849 tx_flags |= tx_ring->dcb_tc << 13;
2f90b865
AD		 6850 }
6851 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6852 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6853 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6854 skb->priority != TC_PRIO_CONTROL) {
e5b64635 6855 tx_flags |= tx_ring->dcb_tc << 13;
2ea186ae
JF		 6856 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6857 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6858 }
eacd73f7 6859
09ad1cc0 6860#ifdef IXGBE_FCOE
56075a98
JF		 6861 /* for FCoE with DCB, we force the priority to what
6862 * was specified by the switch */
6863 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
e5b64635
JF		 6864 (protocol == htons(ETH_P_FCOE)))
6865 tx_flags |= IXGBE_TX_FLAGS_FCOE;
ca77cd59
RL		 6866#endif
6867
eacd73f7 6868 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6869 if (skb_is_gso(skb) ||
6870 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6871 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6872 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6873 count++;
6874
9f8cdf4f
JB		 6875 count += TXD_USE_COUNT(skb_headlen(skb));
6876 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6877 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6878
fc77dc3c 6879 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
5b7da515 6880 tx_ring->tx_stats.tx_busy++;
9a799d71
AK		 6881 return NETDEV_TX_BUSY;
6882 }
9a799d71 6883
9a799d71 6884 first = tx_ring->next_to_use;
eacd73f7
YZ		 6885 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6886#ifdef IXGBE_FCOE
6887 /* setup tx offload for FCoE */
6888 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6889 if (tso < 0) {
6890 dev_kfree_skb_any(skb);
6891 return NETDEV_TX_OK;
6892 }
6893 if (tso)
6894 tx_flags |= IXGBE_TX_FLAGS_FSO;
6895#endif /* IXGBE_FCOE */
6896 } else {
5e09a105 6897 if (protocol == htons(ETH_P_IP))
eacd73f7 6898 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5e09a105
HZ		 6899 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6900 protocol);
eacd73f7
YZ		 6901 if (tso < 0) {
6902 dev_kfree_skb_any(skb);
6903 return NETDEV_TX_OK;
6904 }
9a799d71 6905
eacd73f7
YZ		 6906 if (tso)
6907 tx_flags |= IXGBE_TX_FLAGS_TSO;
5e09a105
HZ		 6908 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6909 protocol) &&
eacd73f7
YZ		 6910 (skb->ip_summed == CHECKSUM_PARTIAL))
6911 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6912 }
9a799d71 6913
8ad494b0 6914 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
44df32c5 6915 if (count) {
c4cf55e5 6916 /* add the ATR filter if ATR is on */
69830529
AD		 6917 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6918 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
84ea2591 6919 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
fc77dc3c 6920 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71 6921
44df32c5
AD		 6922 } else {
6923 dev_kfree_skb_any(skb);
6924 tx_ring->tx_buffer_info[first].time_stamp = 0;
6925 tx_ring->next_to_use = first;
6926 }
9a799d71
AK		 6927
6928 return NETDEV_TX_OK;
6929}
6930
84418e3b
AD		 6931static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6932{
6933 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6934 struct ixgbe_ring *tx_ring;
6935
6936 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6937 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6938}
6939
9a799d71
AK		 6940/**
6941 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6942 * @netdev: network interface device structure
6943 * @p: pointer to an address structure
6944 *
6945 * Returns 0 on success, negative on failure
6946 **/
6947static int ixgbe_set_mac(struct net_device *netdev, void *p)
6948{
6949 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6950 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6951 struct sockaddr *addr = p;
6952
6953 if (!is_valid_ether_addr(addr->sa_data))
6954 return -EADDRNOTAVAIL;
6955
6956 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6957 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6958
1cdd1ec8
GR		 6959 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6960 IXGBE_RAH_AV);
9a799d71
AK		 6961
6962 return 0;
6963}
6964
6b73e10d
BH		 6965static int
6966ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6967{
6968 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6969 struct ixgbe_hw *hw = &adapter->hw;
6970 u16 value;
6971 int rc;
6972
6973 if (prtad != hw->phy.mdio.prtad)
6974 return -EINVAL;
6975 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6976 if (!rc)
6977 rc = value;
6978 return rc;
6979}
6980
6981static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6982 u16 addr, u16 value)
6983{
6984 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6985 struct ixgbe_hw *hw = &adapter->hw;
6986
6987 if (prtad != hw->phy.mdio.prtad)
6988 return -EINVAL;
6989 return hw->phy.ops.write_reg(hw, addr, devad, value);
6990}
6991
6992static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6993{
6994 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6995
6996 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6997}
6998
0365e6e4
PW		 6999/**
7000 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7001 * netdev->dev_addrs
0365e6e4
PW		 7002 * @netdev: network interface device structure
7003 *
7004 * Returns non-zero on failure
7005 **/
7006static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7007{
7008 int err = 0;
7009 struct ixgbe_adapter *adapter = netdev_priv(dev);
7010 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7011
7012 if (is_valid_ether_addr(mac->san_addr)) {
7013 rtnl_lock();
7014 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7015 rtnl_unlock();
7016 }
7017 return err;
7018}
7019
7020/**
7021 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7022 * netdev->dev_addrs
0365e6e4
PW		 7023 * @netdev: network interface device structure
7024 *
7025 * Returns non-zero on failure
7026 **/
7027static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7028{
7029 int err = 0;
7030 struct ixgbe_adapter *adapter = netdev_priv(dev);
7031 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7032
7033 if (is_valid_ether_addr(mac->san_addr)) {
7034 rtnl_lock();
7035 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7036 rtnl_unlock();
7037 }
7038 return err;
7039}
7040
9a799d71
AK		 7041#ifdef CONFIG_NET_POLL_CONTROLLER
7042/*
7043 * Polling 'interrupt' - used by things like netconsole to send skbs
7044 * without having to re-enable interrupts. It's not called while
7045 * the interrupt routine is executing.
7046 */
7047static void ixgbe_netpoll(struct net_device *netdev)
7048{
7049 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7050 int i;
9a799d71 7051
1a647bd2
AD		 7052 /* if interface is down do nothing */
7053 if (test_bit(__IXGBE_DOWN, &adapter->state))
7054 return;
7055
9a799d71 7056 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7057 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7058 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7059 for (i = 0; i < num_q_vectors; i++) {
7060 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7061 ixgbe_msix_clean_many(0, q_vector);
7062 }
7063 } else {
7064 ixgbe_intr(adapter->pdev->irq, netdev);
7065 }
9a799d71 7066 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7067}
7068#endif
7069
de1036b1
ED		 7070static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7071 struct rtnl_link_stats64 *stats)
7072{
7073 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7074 int i;
7075
1a51502b 7076 rcu_read_lock();
de1036b1 7077 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7078 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7079 u64 bytes, packets;
7080 unsigned int start;
7081
1a51502b
ED		 7082 if (ring) {
7083 do {
7084 start = u64_stats_fetch_begin_bh(&ring->syncp);
7085 packets = ring->stats.packets;
7086 bytes = ring->stats.bytes;
7087 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7088 stats->rx_packets += packets;
7089 stats->rx_bytes += bytes;
7090 }
de1036b1 7091 }
1ac9ad13
ED		 7092
7093 for (i = 0; i < adapter->num_tx_queues; i++) {
7094 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7095 u64 bytes, packets;
7096 unsigned int start;
7097
7098 if (ring) {
7099 do {
7100 start = u64_stats_fetch_begin_bh(&ring->syncp);
7101 packets = ring->stats.packets;
7102 bytes = ring->stats.bytes;
7103 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7104 stats->tx_packets += packets;
7105 stats->tx_bytes += bytes;
7106 }
7107 }
1a51502b 7108 rcu_read_unlock();
de1036b1
ED		 7109 /* following stats updated by ixgbe_watchdog_task() */
7110 stats->multicast = netdev->stats.multicast;
7111 stats->rx_errors = netdev->stats.rx_errors;
7112 stats->rx_length_errors = netdev->stats.rx_length_errors;
7113 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7114 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7115 return stats;
7116}
7117
8b1c0b24
JF		 7118/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7119 * #adapter: pointer to ixgbe_adapter
7120 * @tc: number of traffic classes currently enabled
7121 *
7122 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7123 * 802.1Q priority maps to a packet buffer that exists.
7124 */
7125static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7126{
7127 struct ixgbe_hw *hw = &adapter->hw;
7128 u32 reg, rsave;
7129 int i;
7130
7131 /* 82598 have a static priority to TC mapping that can not
7132 * be changed so no validation is needed.
7133 */
7134 if (hw->mac.type == ixgbe_mac_82598EB)
7135 return;
7136
7137 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7138 rsave = reg;
7139
7140 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7141 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7142
7143 /* If up2tc is out of bounds default to zero */
7144 if (up2tc > tc)
7145 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7146 }
7147
7148 if (reg != rsave)
7149 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7150
7151 return;
7152}
7153
7154
7155/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7156 * classes.
7157 *
7158 * @netdev: net device to configure
7159 * @tc: number of traffic classes to enable
7160 */
7161int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7162{
8b1c0b24
JF		 7163 struct ixgbe_adapter *adapter = netdev_priv(dev);
7164 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24
JF		 7165
7166 /* If DCB is anabled do not remove traffic classes, multiple
7167 * traffic classes are required to implement DCB
7168 */
7169 if (!tc && (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7170 return 0;
7171
7172 /* Hardware supports up to 8 traffic classes */
7173 if (tc > MAX_TRAFFIC_CLASS ||
7174 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7175 return -EINVAL;
7176
7177 /* Hardware has to reinitialize queues and interrupts to
7178 * match packet buffer alignment. Unfortunantly, the
7179 * hardware is not flexible enough to do this dynamically.
7180 */
7181 if (netif_running(dev))
7182 ixgbe_close(dev);
7183 ixgbe_clear_interrupt_scheme(adapter);
7184
7185 if (tc)
7186 netdev_set_num_tc(dev, tc);
7187 else
7188 netdev_reset_tc(dev);
7189
8b1c0b24
JF		 7190 ixgbe_init_interrupt_scheme(adapter);
7191 ixgbe_validate_rtr(adapter, tc);
7192 if (netif_running(dev))
7193 ixgbe_open(dev);
7194
7195 return 0;
7196}
de1036b1 7197
0edc3527 7198static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7199 .ndo_open = ixgbe_open,
0edc3527 7200 .ndo_stop = ixgbe_close,
00829823 7201 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7202 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7203 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7204 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7205 .ndo_validate_addr = eth_validate_addr,
7206 .ndo_set_mac_address = ixgbe_set_mac,
7207 .ndo_change_mtu = ixgbe_change_mtu,
7208 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7209 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7210 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7211 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7212 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7213 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7214 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7215 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7216 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7217 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7218#ifdef CONFIG_NET_POLL_CONTROLLER
7219 .ndo_poll_controller = ixgbe_netpoll,
7220#endif
332d4a7d
YZ		 7221#ifdef IXGBE_FCOE
7222 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7223 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7224 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7225 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7226 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7227 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7228#endif /* IXGBE_FCOE */
0edc3527
SH		 7229};
7230
1cdd1ec8
GR		 7231static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7232 const struct ixgbe_info *ii)
7233{
7234#ifdef CONFIG_PCI_IOV
7235 struct ixgbe_hw *hw = &adapter->hw;
7236 int err;
a1cbb15c
GR		 7237 int num_vf_macvlans, i;
7238 struct vf_macvlans *mv_list;
1cdd1ec8 7239
3377eba7 7240 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
1cdd1ec8
GR		 7241 return;
7242
7243 /* The 82599 supports up to 64 VFs per physical function
7244 * but this implementation limits allocation to 63 so that
7245 * basic networking resources are still available to the
7246 * physical function
7247 */
7248 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7249 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7250 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7251 if (err) {
396e799c 7252 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 7253 goto err_novfs;
7254 }
a1cbb15c
GR		 7255
7256 num_vf_macvlans = hw->mac.num_rar_entries -
7257 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7258
7259 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7260 sizeof(struct vf_macvlans),
7261 GFP_KERNEL);
7262 if (mv_list) {
7263 /* Initialize list of VF macvlans */
7264 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7265 for (i = 0; i < num_vf_macvlans; i++) {
7266 mv_list->vf = -1;
7267 mv_list->free = true;
7268 mv_list->rar_entry = hw->mac.num_rar_entries -
7269 (i + adapter->num_vfs + 1);
7270 list_add(&mv_list->l, &adapter->vf_mvs.l);
7271 mv_list++;
7272 }
7273 }
7274
1cdd1ec8
GR		 7275 /* If call to enable VFs succeeded then allocate memory
7276 * for per VF control structures.
7277 */
7278 adapter->vfinfo =
7279 kcalloc(adapter->num_vfs,
7280 sizeof(struct vf_data_storage), GFP_KERNEL);
7281 if (adapter->vfinfo) {
7282 /* Now that we're sure SR-IOV is enabled
7283 * and memory allocated set up the mailbox parameters
7284 */
7285 ixgbe_init_mbx_params_pf(hw);
7286 memcpy(&hw->mbx.ops, ii->mbx_ops,
7287 sizeof(hw->mbx.ops));
7288
7289 /* Disable RSC when in SR-IOV mode */
7290 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7291 IXGBE_FLAG2_RSC_ENABLED);
7292 return;
7293 }
7294
7295 /* Oh oh */
396e799c
ET		 7296 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7297 "SRIOV disabled\n");
1cdd1ec8
GR		 7298 pci_disable_sriov(adapter->pdev);
7299
7300err_novfs:
7301 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7302 adapter->num_vfs = 0;
7303#endif /* CONFIG_PCI_IOV */
7304}
7305
9a799d71
AK		 7306/**
7307 * ixgbe_probe - Device Initialization Routine
7308 * @pdev: PCI device information struct
7309 * @ent: entry in ixgbe_pci_tbl
7310 *
7311 * Returns 0 on success, negative on failure
7312 *
7313 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7314 * The OS initialization, configuring of the adapter private structure,
7315 * and a hardware reset occur.
7316 **/
7317static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7318 const struct pci_device_id *ent)
9a799d71
AK		 7319{
7320 struct net_device *netdev;
7321 struct ixgbe_adapter *adapter = NULL;
7322 struct ixgbe_hw *hw;
7323 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7324 static int cards_found;
7325 int i, err, pci_using_dac;
289700db 7326 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7327 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7328#ifdef IXGBE_FCOE
7329 u16 device_caps;
7330#endif
289700db 7331 u32 eec;
9a799d71 7332
bded64a7
AG		 7333 /* Catch broken hardware that put the wrong VF device ID in
7334 * the PCIe SR-IOV capability.
7335 */
7336 if (pdev->is_virtfn) {
7337 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7338 pci_name(pdev), pdev->vendor, pdev->device);
7339 return -EINVAL;
7340 }
7341
9ce77666 7342 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7343 if (err)
7344 return err;
7345
1b507730
NN		 7346 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7347 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7348 pci_using_dac = 1;
7349 } else {
1b507730 7350 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7351 if (err) {
1b507730
NN		 7352 err = dma_set_coherent_mask(&pdev->dev,
7353 DMA_BIT_MASK(32));
9a799d71 7354 if (err) {
b8bc0421
DC		 7355 dev_err(&pdev->dev,
7356 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7357 goto err_dma;
7358 }
7359 }
7360 pci_using_dac = 0;
7361 }
7362
9ce77666 7363 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7364 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7365 if (err) {
b8bc0421
DC		 7366 dev_err(&pdev->dev,
7367 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7368 goto err_pci_reg;
7369 }
7370
19d5afd4 7371 pci_enable_pcie_error_reporting(pdev);
6fabd715 7372
9a799d71 7373 pci_set_master(pdev);
fb3b27bc 7374 pci_save_state(pdev);
9a799d71 7375
e901acd6
JF		 7376#ifdef CONFIG_IXGBE_DCB
7377 indices *= MAX_TRAFFIC_CLASS;
7378#endif
7379
c85a2618
JF		 7380 if (ii->mac == ixgbe_mac_82598EB)
7381 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7382 else
7383 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7384
e901acd6 7385#ifdef IXGBE_FCOE
c85a2618
JF		 7386 indices += min_t(unsigned int, num_possible_cpus(),
7387 IXGBE_MAX_FCOE_INDICES);
7388#endif
c85a2618 7389 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7390 if (!netdev) {
7391 err = -ENOMEM;
7392 goto err_alloc_etherdev;
7393 }
7394
9a799d71
AK		 7395 SET_NETDEV_DEV(netdev, &pdev->dev);
7396
9a799d71 7397 adapter = netdev_priv(netdev);
c60fbb00 7398 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7399
7400 adapter->netdev = netdev;
7401 adapter->pdev = pdev;
7402 hw = &adapter->hw;
7403 hw->back = adapter;
7404 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7405
05857980 7406 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7407 pci_resource_len(pdev, 0));
9a799d71
AK		 7408 if (!hw->hw_addr) {
7409 err = -EIO;
7410 goto err_ioremap;
7411 }
7412
7413 for (i = 1; i <= 5; i++) {
7414 if (pci_resource_len(pdev, i) == 0)
7415 continue;
7416 }
7417
0edc3527 7418 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7419 ixgbe_set_ethtool_ops(netdev);
9a799d71 7420 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7421 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7422
9a799d71
AK		 7423 adapter->bd_number = cards_found;
7424
9a799d71
AK		 7425 /* Setup hw api */
7426 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7427 hw->mac.type = ii->mac;
9a799d71 7428
c44ade9e
JB		 7429 /* EEPROM */
7430 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7431 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7432 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7433 if (!(eec & (1 << 8)))
7434 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7435
7436 /* PHY */
7437 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7438 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7439 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7440 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7441 hw->phy.mdio.mmds = 0;
7442 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7443 hw->phy.mdio.dev = netdev;
7444 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7445 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7446
8ca783ab 7447 ii->get_invariants(hw);
9a799d71
AK		 7448
7449 /* setup the private structure */
7450 err = ixgbe_sw_init(adapter);
7451 if (err)
7452 goto err_sw_init;
7453
e86bff0e 7454 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7455 switch (adapter->hw.mac.type) {
7456 case ixgbe_mac_82599EB:
7457 case ixgbe_mac_X540:
e86bff0e 7458 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7459 break;
7460 default:
7461 break;
7462 }
e86bff0e 7463
bf069c97
DS		 7464 /*
7465 * If there is a fan on this device and it has failed log the
7466 * failure.
7467 */
7468 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7469 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7470 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7471 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7472 }
7473
c44ade9e 7474 /* reset_hw fills in the perm_addr as well */
119fc60a 7475 hw->phy.reset_if_overtemp = true;
c44ade9e 7476 err = hw->mac.ops.reset_hw(hw);
119fc60a 7477 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7478 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7479 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7480 err = 0;
7481 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7482 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7483 "module type was detected.\n");
7484 e_dev_err("Reload the driver after installing a supported "
7485 "module.\n");
04f165ef
PW		 7486 goto err_sw_init;
7487 } else if (err) {
849c4542 7488 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7489 goto err_sw_init;
7490 }
7491
1cdd1ec8
GR		 7492 ixgbe_probe_vf(adapter, ii);
7493
396e799c 7494 netdev->features = NETIF_F_SG |
e8e9f696
JP		 7495 NETIF_F_IP_CSUM |
7496 NETIF_F_HW_VLAN_TX |
7497 NETIF_F_HW_VLAN_RX |
7498 NETIF_F_HW_VLAN_FILTER;
9a799d71 7499
e9990a9c 7500 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 7501 netdev->features |= NETIF_F_TSO;
9a799d71 7502 netdev->features |= NETIF_F_TSO6;
78b6f4ce 7503 netdev->features |= NETIF_F_GRO;
67a74ee2 7504 netdev->features |= NETIF_F_RXHASH;
ad31c402 7505
58be7666
DS		 7506 switch (adapter->hw.mac.type) {
7507 case ixgbe_mac_82599EB:
7508 case ixgbe_mac_X540:
45a5ead0 7509 netdev->features |= NETIF_F_SCTP_CSUM;
58be7666
DS		 7510 break;
7511 default:
7512 break;
7513 }
45a5ead0 7514
ad31c402
JK		 7515 netdev->vlan_features |= NETIF_F_TSO;
7516 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7517 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7518 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7519 netdev->vlan_features |= NETIF_F_SG;
7520
1cdd1ec8
GR		 7521 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7522 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7523 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7524
7a6b6f51 7525#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7526 netdev->dcbnl_ops = &dcbnl_ops;
7527#endif
7528
eacd73f7 7529#ifdef IXGBE_FCOE
0d551589 7530 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7531 if (hw->mac.ops.get_device_caps) {
7532 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7533 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7534 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7535 }
7536 }
5e09d7f6
YZ		 7537 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7538 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7539 netdev->vlan_features |= NETIF_F_FSO;
7540 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7541 }
eacd73f7 7542#endif /* IXGBE_FCOE */
7b872a55 7543 if (pci_using_dac) {
9a799d71 7544 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7545 netdev->vlan_features |= NETIF_F_HIGHDMA;
7546 }
9a799d71 7547
0c19d6af 7548 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7549 netdev->features |= NETIF_F_LRO;
7550
9a799d71 7551 /* make sure the EEPROM is good */
c44ade9e 7552 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7553 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7554 err = -EIO;
7555 goto err_eeprom;
7556 }
7557
7558 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7559 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7560
c44ade9e 7561 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7562 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7563 err = -EIO;
7564 goto err_eeprom;
7565 }
7566
c6ecf39a
DS		 7567 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7568 if (hw->mac.ops.disable_tx_laser &&
7569 ((hw->phy.multispeed_fiber) ||
9f911707 7570 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 7571 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 7572 hw->mac.ops.disable_tx_laser(hw);
7573
7086400d
AD		 7574 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7575 (unsigned long) adapter);
9a799d71 7576
7086400d
AD		 7577 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7578 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7579
021230d4
AV		 7580 err = ixgbe_init_interrupt_scheme(adapter);
7581 if (err)
7582 goto err_sw_init;
9a799d71 7583
67a74ee2
ET		 7584 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7585 netdev->features &= ~NETIF_F_RXHASH;
7586
e8e26350 7587 switch (pdev->device) {
0b077fea
DS		 7588 case IXGBE_DEV_ID_82599_SFP:
7589 /* Only this subdevice supports WOL */
7590 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7591 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7592 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7593 break;
50d6c681
AD		 7594 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7595 /* All except this subdevice support WOL */
0b077fea
DS		 7596 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7597 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7598 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7599 break;
e8e26350 7600 case IXGBE_DEV_ID_82599_KX4:
495dce12 7601 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 7602 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 7603 break;
7604 default:
7605 adapter->wol = 0;
7606 break;
7607 }
e8e26350
PW		 7608 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7609
04f165ef
PW		 7610 /* pick up the PCI bus settings for reporting later */
7611 hw->mac.ops.get_bus_info(hw);
7612
9a799d71 7613 /* print bus type/speed/width info */
849c4542 7614 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7615 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7616 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7617 "Unknown"),
7618 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7619 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7620 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7621 "Unknown"),
7622 netdev->dev_addr);
289700db
DS		 7623
7624 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7625 if (err)
9fe93afd 7626 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7627 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7628 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7629 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7630 part_str);
e8e26350 7631 else
289700db
DS		 7632 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7633 hw->mac.type, hw->phy.type, part_str);
9a799d71 7634
e8e26350 7635 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7636 e_dev_warn("PCI-Express bandwidth available for this card is "
7637 "not sufficient for optimal performance.\n");
7638 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7639 "is required.\n");
0c254d86
AK		 7640 }
7641
34b0368c
PWJ		 7642 /* save off EEPROM version number */
7643 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7644
9a799d71 7645 /* reset the hardware with the new settings */
794caeb2 7646 err = hw->mac.ops.start_hw(hw);
c44ade9e 7647
794caeb2
PWJ		 7648 if (err == IXGBE_ERR_EEPROM_VERSION) {
7649 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7650 e_dev_warn("This device is a pre-production adapter/LOM. "
7651 "Please be aware there may be issues associated "
7652 "with your hardware. If you are experiencing "
7653 "problems please contact your Intel or hardware "
7654 "representative who provided you with this "
7655 "hardware.\n");
794caeb2 7656 }
9a799d71
AK		 7657 strcpy(netdev->name, "eth%d");
7658 err = register_netdev(netdev);
7659 if (err)
7660 goto err_register;
7661
54386467
JB		 7662 /* carrier off reporting is important to ethtool even BEFORE open */
7663 netif_carrier_off(netdev);
7664
5dd2d332 7665#ifdef CONFIG_IXGBE_DCA
652f093f 7666 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7667 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7668 ixgbe_setup_dca(adapter);
7669 }
7670#endif
1cdd1ec8 7671 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7672 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7673 for (i = 0; i < adapter->num_vfs; i++)
7674 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7675 }
7676
0365e6e4
PW		 7677 /* add san mac addr to netdev */
7678 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7679
849c4542 7680 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7681 cards_found++;
7682 return 0;
7683
7684err_register:
5eba3699 7685 ixgbe_release_hw_control(adapter);
7a921c93 7686 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7687err_sw_init:
7688err_eeprom:
1cdd1ec8
GR		 7689 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7690 ixgbe_disable_sriov(adapter);
7086400d 7691 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7692 iounmap(hw->hw_addr);
7693err_ioremap:
7694 free_netdev(netdev);
7695err_alloc_etherdev:
e8e9f696
JP		 7696 pci_release_selected_regions(pdev,
7697 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7698err_pci_reg:
7699err_dma:
7700 pci_disable_device(pdev);
7701 return err;
7702}
7703
7704/**
7705 * ixgbe_remove - Device Removal Routine
7706 * @pdev: PCI device information struct
7707 *
7708 * ixgbe_remove is called by the PCI subsystem to alert the driver
7709 * that it should release a PCI device. The could be caused by a
7710 * Hot-Plug event, or because the driver is going to be removed from
7711 * memory.
7712 **/
7713static void __devexit ixgbe_remove(struct pci_dev *pdev)
7714{
c60fbb00
AD		 7715 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7716 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7717
7718 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7719 cancel_work_sync(&adapter->service_task);
9a799d71 7720
5dd2d332 7721#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7722 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7723 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7724 dca_remove_requester(&pdev->dev);
7725 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7726 }
7727
7728#endif
332d4a7d
YZ		 7729#ifdef IXGBE_FCOE
7730 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7731 ixgbe_cleanup_fcoe(adapter);
7732
7733#endif /* IXGBE_FCOE */
0365e6e4
PW		 7734
7735 /* remove the added san mac */
7736 ixgbe_del_sanmac_netdev(netdev);
7737
c4900be0
DS		 7738 if (netdev->reg_state == NETREG_REGISTERED)
7739 unregister_netdev(netdev);
9a799d71 7740
1cdd1ec8
GR		 7741 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7742 ixgbe_disable_sriov(adapter);
7743
7a921c93 7744 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7745
021230d4 7746 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7747
7748 iounmap(adapter->hw.hw_addr);
9ce77666 7749 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7750 IORESOURCE_MEM));
9a799d71 7751
849c4542 7752 e_dev_info("complete\n");
021230d4 7753
9a799d71
AK		 7754 free_netdev(netdev);
7755
19d5afd4 7756 pci_disable_pcie_error_reporting(pdev);
6fabd715 7757
9a799d71
AK		 7758 pci_disable_device(pdev);
7759}
7760
7761/**
7762 * ixgbe_io_error_detected - called when PCI error is detected
7763 * @pdev: Pointer to PCI device
7764 * @state: The current pci connection state
7765 *
7766 * This function is called after a PCI bus error affecting
7767 * this device has been detected.
7768 */
7769static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7770 pci_channel_state_t state)
9a799d71 7771{
c60fbb00
AD		 7772 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7773 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7774
7775 netif_device_detach(netdev);
7776
3044b8d1
BL		 7777 if (state == pci_channel_io_perm_failure)
7778 return PCI_ERS_RESULT_DISCONNECT;
7779
9a799d71
AK		 7780 if (netif_running(netdev))
7781 ixgbe_down(adapter);
7782 pci_disable_device(pdev);
7783
b4617240 7784 /* Request a slot reset. */
9a799d71
AK		 7785 return PCI_ERS_RESULT_NEED_RESET;
7786}
7787
7788/**
7789 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7790 * @pdev: Pointer to PCI device
7791 *
7792 * Restart the card from scratch, as if from a cold-boot.
7793 */
7794static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7795{
c60fbb00 7796 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7797 pci_ers_result_t result;
7798 int err;
9a799d71 7799
9ce77666 7800 if (pci_enable_device_mem(pdev)) {
396e799c 7801 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7802 result = PCI_ERS_RESULT_DISCONNECT;
7803 } else {
7804 pci_set_master(pdev);
7805 pci_restore_state(pdev);
c0e1f68b 7806 pci_save_state(pdev);
9a799d71 7807
dd4d8ca6 7808 pci_wake_from_d3(pdev, false);
9a799d71 7809
6fabd715 7810 ixgbe_reset(adapter);
88512539 7811 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7812 result = PCI_ERS_RESULT_RECOVERED;
7813 }
7814
7815 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7816 if (err) {
849c4542
ET		 7817 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7818 "failed 0x%0x\n", err);
6fabd715
PWJ		 7819 /* non-fatal, continue */
7820 }
9a799d71 7821
6fabd715 7822 return result;
9a799d71
AK		 7823}
7824
7825/**
7826 * ixgbe_io_resume - called when traffic can start flowing again.
7827 * @pdev: Pointer to PCI device
7828 *
7829 * This callback is called when the error recovery driver tells us that
7830 * its OK to resume normal operation.
7831 */
7832static void ixgbe_io_resume(struct pci_dev *pdev)
7833{
c60fbb00
AD		 7834 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7835 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7836
7837 if (netif_running(netdev)) {
7838 if (ixgbe_up(adapter)) {
396e799c 7839 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7840 return;
7841 }
7842 }
7843
7844 netif_device_attach(netdev);
9a799d71
AK		 7845}
7846
7847static struct pci_error_handlers ixgbe_err_handler = {
7848 .error_detected = ixgbe_io_error_detected,
7849 .slot_reset = ixgbe_io_slot_reset,
7850 .resume = ixgbe_io_resume,
7851};
7852
7853static struct pci_driver ixgbe_driver = {
7854 .name = ixgbe_driver_name,
7855 .id_table = ixgbe_pci_tbl,
7856 .probe = ixgbe_probe,
7857 .remove = __devexit_p(ixgbe_remove),
7858#ifdef CONFIG_PM
7859 .suspend = ixgbe_suspend,
7860 .resume = ixgbe_resume,
7861#endif
7862 .shutdown = ixgbe_shutdown,
7863 .err_handler = &ixgbe_err_handler
7864};
7865
7866/**
7867 * ixgbe_init_module - Driver Registration Routine
7868 *
7869 * ixgbe_init_module is the first routine called when the driver is
7870 * loaded. All it does is register with the PCI subsystem.
7871 **/
7872static int __init ixgbe_init_module(void)
7873{
7874 int ret;
c7689578 7875 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7876 pr_info("%s\n", ixgbe_copyright);
9a799d71 7877
5dd2d332 7878#ifdef CONFIG_IXGBE_DCA
bd0362dd 7879 dca_register_notify(&dca_notifier);
bd0362dd 7880#endif
5dd2d332 7881
9a799d71
AK		 7882 ret = pci_register_driver(&ixgbe_driver);
7883 return ret;
7884}
b4617240 7885
9a799d71
AK		 7886module_init(ixgbe_init_module);
7887
7888/**
7889 * ixgbe_exit_module - Driver Exit Cleanup Routine
7890 *
7891 * ixgbe_exit_module is called just before the driver is removed
7892 * from memory.
7893 **/
7894static void __exit ixgbe_exit_module(void)
7895{
5dd2d332 7896#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7897 dca_unregister_notify(&dca_notifier);
7898#endif
9a799d71 7899 pci_unregister_driver(&ixgbe_driver);
1a51502b 7900 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7901}
bd0362dd 7902
5dd2d332 7903#ifdef CONFIG_IXGBE_DCA
bd0362dd 7904static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7905 void *p)
bd0362dd
JC		 7906{
7907 int ret_val;
7908
7909 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7910 __ixgbe_notify_dca);
bd0362dd
JC		 7911
7912 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7913}
b453368d 7914
5dd2d332 7915#endif /* CONFIG_IXGBE_DCA */
849c4542 7916
9a799d71
AK		 7917module_exit(ixgbe_exit_module);
7918
7919/* ixgbe_main.c */
Linux kernel - Deliverables
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