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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
8c47eaa7 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/pci.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/sched.h> | |
31 | ||
32 | #include "ixgbe_common.h" | |
33 | #include "ixgbe_phy.h" | |
34 | ||
11afc1b1 PW |
35 | static void ixgbe_i2c_start(struct ixgbe_hw *hw); |
36 | static void ixgbe_i2c_stop(struct ixgbe_hw *hw); | |
37 | static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); | |
38 | static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); | |
39 | static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); | |
40 | static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); | |
41 | static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); | |
42 | static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); | |
43 | static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); | |
44 | static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); | |
45 | static bool ixgbe_get_i2c_data(u32 *i2cctl); | |
46 | static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); | |
9a799d71 AK |
47 | static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); |
48 | static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); | |
9a799d71 AK |
49 | |
50 | /** | |
c44ade9e | 51 | * ixgbe_identify_phy_generic - Get physical layer module |
9a799d71 AK |
52 | * @hw: pointer to hardware structure |
53 | * | |
54 | * Determines the physical layer module found on the current adapter. | |
55 | **/ | |
c44ade9e | 56 | s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
57 | { |
58 | s32 status = IXGBE_ERR_PHY_ADDR_INVALID; | |
59 | u32 phy_addr; | |
60 | ||
c44ade9e JB |
61 | if (hw->phy.type == ixgbe_phy_unknown) { |
62 | for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { | |
63d6e1d8 | 63 | hw->phy.mdio.prtad = phy_addr; |
6b73e10d | 64 | if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) { |
c44ade9e JB |
65 | ixgbe_get_phy_id(hw); |
66 | hw->phy.type = | |
67 | ixgbe_get_phy_type_from_id(hw->phy.id); | |
68 | status = 0; | |
69 | break; | |
70 | } | |
9a799d71 | 71 | } |
63d6e1d8 DS |
72 | /* clear value if nothing found */ |
73 | hw->phy.mdio.prtad = 0; | |
c44ade9e JB |
74 | } else { |
75 | status = 0; | |
9a799d71 | 76 | } |
c44ade9e | 77 | |
9a799d71 AK |
78 | return status; |
79 | } | |
80 | ||
9a799d71 AK |
81 | /** |
82 | * ixgbe_get_phy_id - Get the phy type | |
83 | * @hw: pointer to hardware structure | |
84 | * | |
85 | **/ | |
86 | static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) | |
87 | { | |
88 | u32 status; | |
89 | u16 phy_id_high = 0; | |
90 | u16 phy_id_low = 0; | |
91 | ||
6b73e10d | 92 | status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD, |
c44ade9e | 93 | &phy_id_high); |
9a799d71 AK |
94 | |
95 | if (status == 0) { | |
96 | hw->phy.id = (u32)(phy_id_high << 16); | |
6b73e10d | 97 | status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD, |
c44ade9e | 98 | &phy_id_low); |
9a799d71 AK |
99 | hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); |
100 | hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); | |
101 | } | |
9a799d71 AK |
102 | return status; |
103 | } | |
104 | ||
105 | /** | |
106 | * ixgbe_get_phy_type_from_id - Get the phy type | |
107 | * @hw: pointer to hardware structure | |
108 | * | |
109 | **/ | |
110 | static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) | |
111 | { | |
112 | enum ixgbe_phy_type phy_type; | |
113 | ||
114 | switch (phy_id) { | |
0befdb3e JB |
115 | case TN1010_PHY_ID: |
116 | phy_type = ixgbe_phy_tn; | |
117 | break; | |
9a799d71 AK |
118 | case QT2022_PHY_ID: |
119 | phy_type = ixgbe_phy_qt; | |
120 | break; | |
c4900be0 DS |
121 | case ATH_PHY_ID: |
122 | phy_type = ixgbe_phy_nl; | |
123 | break; | |
9a799d71 AK |
124 | default: |
125 | phy_type = ixgbe_phy_unknown; | |
126 | break; | |
127 | } | |
128 | ||
129 | return phy_type; | |
130 | } | |
131 | ||
132 | /** | |
c44ade9e | 133 | * ixgbe_reset_phy_generic - Performs a PHY reset |
9a799d71 AK |
134 | * @hw: pointer to hardware structure |
135 | **/ | |
c44ade9e | 136 | s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
137 | { |
138 | /* | |
139 | * Perform soft PHY reset to the PHY_XS. | |
140 | * This will cause a soft reset to the PHY | |
141 | */ | |
6b73e10d BH |
142 | return hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, |
143 | MDIO_CTRL1_RESET); | |
9a799d71 AK |
144 | } |
145 | ||
146 | /** | |
c44ade9e | 147 | * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register |
9a799d71 AK |
148 | * @hw: pointer to hardware structure |
149 | * @reg_addr: 32 bit address of PHY register to read | |
150 | * @phy_data: Pointer to read data from PHY register | |
151 | **/ | |
c44ade9e JB |
152 | s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, |
153 | u32 device_type, u16 *phy_data) | |
9a799d71 AK |
154 | { |
155 | u32 command; | |
156 | u32 i; | |
9a799d71 AK |
157 | u32 data; |
158 | s32 status = 0; | |
159 | u16 gssr; | |
160 | ||
161 | if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) | |
162 | gssr = IXGBE_GSSR_PHY1_SM; | |
163 | else | |
164 | gssr = IXGBE_GSSR_PHY0_SM; | |
165 | ||
166 | if (ixgbe_acquire_swfw_sync(hw, gssr) != 0) | |
167 | status = IXGBE_ERR_SWFW_SYNC; | |
168 | ||
169 | if (status == 0) { | |
170 | /* Setup and write the address cycle command */ | |
171 | command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | | |
c44ade9e | 172 | (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | |
6b73e10d | 173 | (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | |
c44ade9e | 174 | (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); |
9a799d71 AK |
175 | |
176 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); | |
177 | ||
178 | /* | |
179 | * Check every 10 usec to see if the address cycle completed. | |
180 | * The MDI Command bit will clear when the operation is | |
181 | * complete | |
182 | */ | |
c44ade9e | 183 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { |
9a799d71 AK |
184 | udelay(10); |
185 | ||
186 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); | |
187 | ||
188 | if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) | |
189 | break; | |
190 | } | |
191 | ||
192 | if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { | |
193 | hw_dbg(hw, "PHY address command did not complete.\n"); | |
194 | status = IXGBE_ERR_PHY; | |
195 | } | |
196 | ||
197 | if (status == 0) { | |
198 | /* | |
199 | * Address cycle complete, setup and write the read | |
200 | * command | |
201 | */ | |
202 | command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | | |
c44ade9e | 203 | (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | |
6b73e10d BH |
204 | (hw->phy.mdio.prtad << |
205 | IXGBE_MSCA_PHY_ADDR_SHIFT) | | |
c44ade9e | 206 | (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); |
9a799d71 AK |
207 | |
208 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); | |
209 | ||
210 | /* | |
211 | * Check every 10 usec to see if the address cycle | |
212 | * completed. The MDI Command bit will clear when the | |
213 | * operation is complete | |
214 | */ | |
c44ade9e | 215 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { |
9a799d71 AK |
216 | udelay(10); |
217 | ||
218 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); | |
219 | ||
220 | if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) | |
221 | break; | |
222 | } | |
223 | ||
224 | if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { | |
c44ade9e | 225 | hw_dbg(hw, "PHY read command didn't complete\n"); |
9a799d71 AK |
226 | status = IXGBE_ERR_PHY; |
227 | } else { | |
228 | /* | |
229 | * Read operation is complete. Get the data | |
230 | * from MSRWD | |
231 | */ | |
232 | data = IXGBE_READ_REG(hw, IXGBE_MSRWD); | |
233 | data >>= IXGBE_MSRWD_READ_DATA_SHIFT; | |
234 | *phy_data = (u16)(data); | |
235 | } | |
236 | } | |
237 | ||
238 | ixgbe_release_swfw_sync(hw, gssr); | |
239 | } | |
c44ade9e | 240 | |
9a799d71 AK |
241 | return status; |
242 | } | |
243 | ||
244 | /** | |
c44ade9e | 245 | * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register |
9a799d71 AK |
246 | * @hw: pointer to hardware structure |
247 | * @reg_addr: 32 bit PHY register to write | |
248 | * @device_type: 5 bit device type | |
249 | * @phy_data: Data to write to the PHY register | |
250 | **/ | |
c44ade9e JB |
251 | s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, |
252 | u32 device_type, u16 phy_data) | |
9a799d71 AK |
253 | { |
254 | u32 command; | |
255 | u32 i; | |
9a799d71 AK |
256 | s32 status = 0; |
257 | u16 gssr; | |
258 | ||
259 | if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) | |
260 | gssr = IXGBE_GSSR_PHY1_SM; | |
261 | else | |
262 | gssr = IXGBE_GSSR_PHY0_SM; | |
263 | ||
264 | if (ixgbe_acquire_swfw_sync(hw, gssr) != 0) | |
265 | status = IXGBE_ERR_SWFW_SYNC; | |
266 | ||
267 | if (status == 0) { | |
268 | /* Put the data in the MDI single read and write data register*/ | |
269 | IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); | |
270 | ||
271 | /* Setup and write the address cycle command */ | |
272 | command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | | |
c44ade9e | 273 | (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | |
6b73e10d | 274 | (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | |
c44ade9e | 275 | (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); |
9a799d71 AK |
276 | |
277 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); | |
278 | ||
279 | /* | |
280 | * Check every 10 usec to see if the address cycle completed. | |
281 | * The MDI Command bit will clear when the operation is | |
282 | * complete | |
283 | */ | |
c44ade9e | 284 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { |
9a799d71 AK |
285 | udelay(10); |
286 | ||
287 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); | |
288 | ||
c44ade9e | 289 | if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) |
9a799d71 | 290 | break; |
9a799d71 AK |
291 | } |
292 | ||
c44ade9e JB |
293 | if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { |
294 | hw_dbg(hw, "PHY address cmd didn't complete\n"); | |
9a799d71 | 295 | status = IXGBE_ERR_PHY; |
c44ade9e | 296 | } |
9a799d71 AK |
297 | |
298 | if (status == 0) { | |
299 | /* | |
300 | * Address cycle complete, setup and write the write | |
301 | * command | |
302 | */ | |
303 | command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | | |
c44ade9e | 304 | (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | |
6b73e10d BH |
305 | (hw->phy.mdio.prtad << |
306 | IXGBE_MSCA_PHY_ADDR_SHIFT) | | |
c44ade9e | 307 | (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); |
9a799d71 AK |
308 | |
309 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); | |
310 | ||
311 | /* | |
312 | * Check every 10 usec to see if the address cycle | |
313 | * completed. The MDI Command bit will clear when the | |
314 | * operation is complete | |
315 | */ | |
c44ade9e | 316 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { |
9a799d71 AK |
317 | udelay(10); |
318 | ||
319 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); | |
320 | ||
c44ade9e | 321 | if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) |
9a799d71 | 322 | break; |
9a799d71 AK |
323 | } |
324 | ||
c44ade9e JB |
325 | if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { |
326 | hw_dbg(hw, "PHY address cmd didn't complete\n"); | |
9a799d71 | 327 | status = IXGBE_ERR_PHY; |
c44ade9e | 328 | } |
9a799d71 AK |
329 | } |
330 | ||
331 | ixgbe_release_swfw_sync(hw, gssr); | |
332 | } | |
333 | ||
334 | return status; | |
335 | } | |
336 | ||
337 | /** | |
c44ade9e | 338 | * ixgbe_setup_phy_link_generic - Set and restart autoneg |
9a799d71 AK |
339 | * @hw: pointer to hardware structure |
340 | * | |
341 | * Restart autonegotiation and PHY and waits for completion. | |
342 | **/ | |
c44ade9e | 343 | s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
344 | { |
345 | s32 status = IXGBE_NOT_IMPLEMENTED; | |
346 | u32 time_out; | |
347 | u32 max_time_out = 10; | |
6b73e10d | 348 | u16 autoneg_reg; |
9a799d71 AK |
349 | |
350 | /* | |
351 | * Set advertisement settings in PHY based on autoneg_advertised | |
352 | * settings. If autoneg_advertised = 0, then advertise default values | |
c44ade9e | 353 | * tnx devices cannot be "forced" to a autoneg 10G and fail. But can |
9a799d71 AK |
354 | * for a 1G. |
355 | */ | |
6b73e10d | 356 | hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg); |
9a799d71 AK |
357 | |
358 | if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL) | |
6b73e10d | 359 | autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; |
9a799d71 | 360 | else |
6b73e10d | 361 | autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; |
9a799d71 | 362 | |
6b73e10d | 363 | hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg); |
9a799d71 AK |
364 | |
365 | /* Restart PHY autonegotiation and wait for completion */ | |
6b73e10d | 366 | hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg); |
9a799d71 | 367 | |
6b73e10d | 368 | autoneg_reg |= MDIO_AN_CTRL1_RESTART; |
9a799d71 | 369 | |
6b73e10d | 370 | hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg); |
9a799d71 AK |
371 | |
372 | /* Wait for autonegotiation to finish */ | |
373 | for (time_out = 0; time_out < max_time_out; time_out++) { | |
374 | udelay(10); | |
375 | /* Restart PHY autonegotiation and wait for completion */ | |
6b73e10d | 376 | status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, |
c44ade9e | 377 | &autoneg_reg); |
9a799d71 | 378 | |
6b73e10d BH |
379 | autoneg_reg &= MDIO_AN_STAT1_COMPLETE; |
380 | if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) { | |
9a799d71 AK |
381 | status = 0; |
382 | break; | |
383 | } | |
384 | } | |
385 | ||
386 | if (time_out == max_time_out) | |
387 | status = IXGBE_ERR_LINK_SETUP; | |
388 | ||
389 | return status; | |
390 | } | |
391 | ||
392 | /** | |
c44ade9e | 393 | * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities |
9a799d71 AK |
394 | * @hw: pointer to hardware structure |
395 | * @speed: new link speed | |
396 | * @autoneg: true if autonegotiation enabled | |
397 | **/ | |
c44ade9e JB |
398 | s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, |
399 | ixgbe_link_speed speed, | |
400 | bool autoneg, | |
401 | bool autoneg_wait_to_complete) | |
9a799d71 | 402 | { |
c44ade9e | 403 | |
9a799d71 AK |
404 | /* |
405 | * Clear autoneg_advertised and set new values based on input link | |
406 | * speed. | |
407 | */ | |
408 | hw->phy.autoneg_advertised = 0; | |
409 | ||
410 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) | |
411 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; | |
c44ade9e | 412 | |
9a799d71 AK |
413 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) |
414 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; | |
415 | ||
416 | /* Setup link based on the new speed settings */ | |
c44ade9e | 417 | hw->phy.ops.setup_link(hw); |
9a799d71 AK |
418 | |
419 | return 0; | |
420 | } | |
c44ade9e | 421 | |
c4900be0 DS |
422 | /** |
423 | * ixgbe_reset_phy_nl - Performs a PHY reset | |
424 | * @hw: pointer to hardware structure | |
425 | **/ | |
426 | s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) | |
427 | { | |
428 | u16 phy_offset, control, eword, edata, block_crc; | |
429 | bool end_data = false; | |
430 | u16 list_offset, data_offset; | |
431 | u16 phy_data = 0; | |
432 | s32 ret_val = 0; | |
433 | u32 i; | |
434 | ||
6b73e10d | 435 | hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data); |
c4900be0 DS |
436 | |
437 | /* reset the PHY and poll for completion */ | |
6b73e10d BH |
438 | hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, |
439 | (phy_data | MDIO_CTRL1_RESET)); | |
c4900be0 DS |
440 | |
441 | for (i = 0; i < 100; i++) { | |
6b73e10d BH |
442 | hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, |
443 | &phy_data); | |
444 | if ((phy_data & MDIO_CTRL1_RESET) == 0) | |
c4900be0 DS |
445 | break; |
446 | msleep(10); | |
447 | } | |
448 | ||
6b73e10d | 449 | if ((phy_data & MDIO_CTRL1_RESET) != 0) { |
c4900be0 DS |
450 | hw_dbg(hw, "PHY reset did not complete.\n"); |
451 | ret_val = IXGBE_ERR_PHY; | |
452 | goto out; | |
453 | } | |
454 | ||
455 | /* Get init offsets */ | |
456 | ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, | |
457 | &data_offset); | |
458 | if (ret_val != 0) | |
459 | goto out; | |
460 | ||
461 | ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); | |
462 | data_offset++; | |
463 | while (!end_data) { | |
464 | /* | |
465 | * Read control word from PHY init contents offset | |
466 | */ | |
467 | ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); | |
468 | control = (eword & IXGBE_CONTROL_MASK_NL) >> | |
469 | IXGBE_CONTROL_SHIFT_NL; | |
470 | edata = eword & IXGBE_DATA_MASK_NL; | |
471 | switch (control) { | |
472 | case IXGBE_DELAY_NL: | |
473 | data_offset++; | |
474 | hw_dbg(hw, "DELAY: %d MS\n", edata); | |
475 | msleep(edata); | |
476 | break; | |
477 | case IXGBE_DATA_NL: | |
d6dbee86 | 478 | hw_dbg(hw, "DATA:\n"); |
c4900be0 DS |
479 | data_offset++; |
480 | hw->eeprom.ops.read(hw, data_offset++, | |
481 | &phy_offset); | |
482 | for (i = 0; i < edata; i++) { | |
483 | hw->eeprom.ops.read(hw, data_offset, &eword); | |
484 | hw->phy.ops.write_reg(hw, phy_offset, | |
6b73e10d | 485 | MDIO_MMD_PMAPMD, eword); |
c4900be0 DS |
486 | hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, |
487 | phy_offset); | |
488 | data_offset++; | |
489 | phy_offset++; | |
490 | } | |
491 | break; | |
492 | case IXGBE_CONTROL_NL: | |
493 | data_offset++; | |
d6dbee86 | 494 | hw_dbg(hw, "CONTROL:\n"); |
c4900be0 DS |
495 | if (edata == IXGBE_CONTROL_EOL_NL) { |
496 | hw_dbg(hw, "EOL\n"); | |
497 | end_data = true; | |
498 | } else if (edata == IXGBE_CONTROL_SOL_NL) { | |
499 | hw_dbg(hw, "SOL\n"); | |
500 | } else { | |
501 | hw_dbg(hw, "Bad control value\n"); | |
502 | ret_val = IXGBE_ERR_PHY; | |
503 | goto out; | |
504 | } | |
505 | break; | |
506 | default: | |
507 | hw_dbg(hw, "Bad control type\n"); | |
508 | ret_val = IXGBE_ERR_PHY; | |
509 | goto out; | |
510 | } | |
511 | } | |
512 | ||
513 | out: | |
514 | return ret_val; | |
515 | } | |
516 | ||
517 | /** | |
518 | * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns | |
519 | * the PHY type. | |
520 | * @hw: pointer to hardware structure | |
521 | * | |
522 | * Searches for and indentifies the SFP module. Assings appropriate PHY type. | |
523 | **/ | |
524 | s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) | |
525 | { | |
526 | s32 status = IXGBE_ERR_PHY_ADDR_INVALID; | |
527 | u32 vendor_oui = 0; | |
553b4497 | 528 | enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; |
c4900be0 DS |
529 | u8 identifier = 0; |
530 | u8 comp_codes_1g = 0; | |
531 | u8 comp_codes_10g = 0; | |
11afc1b1 | 532 | u8 oui_bytes[3] = {0, 0, 0}; |
537d58a0 | 533 | u8 cable_tech = 0; |
11afc1b1 | 534 | u16 enforce_sfp = 0; |
c4900be0 | 535 | |
8ca783ab DS |
536 | if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { |
537 | hw->phy.sfp_type = ixgbe_sfp_type_not_present; | |
538 | status = IXGBE_ERR_SFP_NOT_PRESENT; | |
539 | goto out; | |
540 | } | |
541 | ||
c4900be0 DS |
542 | status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, |
543 | &identifier); | |
544 | ||
8ca783ab DS |
545 | if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) { |
546 | status = IXGBE_ERR_SFP_NOT_PRESENT; | |
c4900be0 | 547 | hw->phy.sfp_type = ixgbe_sfp_type_not_present; |
8ca783ab DS |
548 | if (hw->phy.type != ixgbe_phy_nl) { |
549 | hw->phy.id = 0; | |
550 | hw->phy.type = ixgbe_phy_unknown; | |
551 | } | |
c4900be0 DS |
552 | goto out; |
553 | } | |
554 | ||
555 | if (identifier == IXGBE_SFF_IDENTIFIER_SFP) { | |
556 | hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES, | |
557 | &comp_codes_1g); | |
558 | hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES, | |
559 | &comp_codes_10g); | |
537d58a0 PWJ |
560 | hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY, |
561 | &cable_tech); | |
c4900be0 DS |
562 | |
563 | /* ID Module | |
564 | * ========= | |
11afc1b1 PW |
565 | * 0 SFP_DA_CU |
566 | * 1 SFP_SR | |
567 | * 2 SFP_LR | |
568 | * 3 SFP_DA_CORE0 - 82599-specific | |
569 | * 4 SFP_DA_CORE1 - 82599-specific | |
570 | * 5 SFP_SR/LR_CORE0 - 82599-specific | |
571 | * 6 SFP_SR/LR_CORE1 - 82599-specific | |
c4900be0 | 572 | */ |
11afc1b1 | 573 | if (hw->mac.type == ixgbe_mac_82598EB) { |
537d58a0 | 574 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) |
11afc1b1 PW |
575 | hw->phy.sfp_type = ixgbe_sfp_type_da_cu; |
576 | else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) | |
577 | hw->phy.sfp_type = ixgbe_sfp_type_sr; | |
578 | else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) | |
579 | hw->phy.sfp_type = ixgbe_sfp_type_lr; | |
580 | else | |
581 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; | |
582 | } else if (hw->mac.type == ixgbe_mac_82599EB) { | |
537d58a0 | 583 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) |
11afc1b1 PW |
584 | if (hw->bus.lan_id == 0) |
585 | hw->phy.sfp_type = | |
586 | ixgbe_sfp_type_da_cu_core0; | |
587 | else | |
588 | hw->phy.sfp_type = | |
589 | ixgbe_sfp_type_da_cu_core1; | |
590 | else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) | |
591 | if (hw->bus.lan_id == 0) | |
592 | hw->phy.sfp_type = | |
593 | ixgbe_sfp_type_srlr_core0; | |
594 | else | |
595 | hw->phy.sfp_type = | |
596 | ixgbe_sfp_type_srlr_core1; | |
597 | else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) | |
598 | if (hw->bus.lan_id == 0) | |
599 | hw->phy.sfp_type = | |
600 | ixgbe_sfp_type_srlr_core0; | |
601 | else | |
602 | hw->phy.sfp_type = | |
603 | ixgbe_sfp_type_srlr_core1; | |
604 | else | |
605 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; | |
606 | } | |
c4900be0 | 607 | |
553b4497 PW |
608 | if (hw->phy.sfp_type != stored_sfp_type) |
609 | hw->phy.sfp_setup_needed = true; | |
610 | ||
611 | /* Determine if the SFP+ PHY is dual speed or not. */ | |
50ac58ba | 612 | hw->phy.multispeed_fiber = false; |
553b4497 PW |
613 | if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && |
614 | (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || | |
615 | ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && | |
616 | (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) | |
617 | hw->phy.multispeed_fiber = true; | |
618 | ||
c4900be0 | 619 | /* Determine PHY vendor */ |
04193058 | 620 | if (hw->phy.type != ixgbe_phy_nl) { |
c4900be0 DS |
621 | hw->phy.id = identifier; |
622 | hw->phy.ops.read_i2c_eeprom(hw, | |
623 | IXGBE_SFF_VENDOR_OUI_BYTE0, | |
624 | &oui_bytes[0]); | |
625 | hw->phy.ops.read_i2c_eeprom(hw, | |
626 | IXGBE_SFF_VENDOR_OUI_BYTE1, | |
627 | &oui_bytes[1]); | |
628 | hw->phy.ops.read_i2c_eeprom(hw, | |
629 | IXGBE_SFF_VENDOR_OUI_BYTE2, | |
630 | &oui_bytes[2]); | |
631 | ||
632 | vendor_oui = | |
633 | ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | | |
634 | (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | | |
635 | (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); | |
636 | ||
637 | switch (vendor_oui) { | |
638 | case IXGBE_SFF_VENDOR_OUI_TYCO: | |
537d58a0 | 639 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) |
c4900be0 DS |
640 | hw->phy.type = ixgbe_phy_tw_tyco; |
641 | break; | |
642 | case IXGBE_SFF_VENDOR_OUI_FTL: | |
643 | hw->phy.type = ixgbe_phy_sfp_ftl; | |
644 | break; | |
645 | case IXGBE_SFF_VENDOR_OUI_AVAGO: | |
646 | hw->phy.type = ixgbe_phy_sfp_avago; | |
647 | break; | |
11afc1b1 PW |
648 | case IXGBE_SFF_VENDOR_OUI_INTEL: |
649 | hw->phy.type = ixgbe_phy_sfp_intel; | |
650 | break; | |
c4900be0 | 651 | default: |
537d58a0 | 652 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) |
c4900be0 DS |
653 | hw->phy.type = ixgbe_phy_tw_unknown; |
654 | else | |
655 | hw->phy.type = ixgbe_phy_sfp_unknown; | |
656 | break; | |
657 | } | |
658 | } | |
fa466e91 | 659 | |
537d58a0 PWJ |
660 | /* All passive DA cables are supported */ |
661 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { | |
fa466e91 WJP |
662 | status = 0; |
663 | goto out; | |
664 | } | |
665 | ||
666 | /* 1G SFP modules are not supported */ | |
667 | if (comp_codes_10g == 0) { | |
668 | hw->phy.type = ixgbe_phy_sfp_unsupported; | |
669 | status = IXGBE_ERR_SFP_NOT_SUPPORTED; | |
670 | goto out; | |
671 | } | |
672 | ||
673 | /* Anything else 82598-based is supported */ | |
674 | if (hw->mac.type == ixgbe_mac_82598EB) { | |
11afc1b1 PW |
675 | status = 0; |
676 | goto out; | |
677 | } | |
678 | ||
04193058 PWJ |
679 | /* This is guaranteed to be 82599, no need to check for NULL */ |
680 | hw->mac.ops.get_device_caps(hw, &enforce_sfp); | |
681 | if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { | |
11afc1b1 PW |
682 | /* Make sure we're a supported PHY type */ |
683 | if (hw->phy.type == ixgbe_phy_sfp_intel) { | |
684 | status = 0; | |
685 | } else { | |
686 | hw_dbg(hw, "SFP+ module not supported\n"); | |
fa466e91 | 687 | hw->phy.type = ixgbe_phy_sfp_unsupported; |
11afc1b1 PW |
688 | status = IXGBE_ERR_SFP_NOT_SUPPORTED; |
689 | } | |
690 | } else { | |
691 | status = 0; | |
692 | } | |
c4900be0 DS |
693 | } |
694 | ||
695 | out: | |
696 | return status; | |
697 | } | |
698 | ||
699 | /** | |
700 | * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see | |
701 | * if it supports a given SFP+ module type, if so it returns the offsets to the | |
702 | * phy init sequence block. | |
703 | * @hw: pointer to hardware structure | |
704 | * @list_offset: offset to the SFP ID list | |
705 | * @data_offset: offset to the SFP data block | |
706 | **/ | |
707 | s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, | |
708 | u16 *list_offset, | |
709 | u16 *data_offset) | |
710 | { | |
711 | u16 sfp_id; | |
712 | ||
713 | if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) | |
714 | return IXGBE_ERR_SFP_NOT_SUPPORTED; | |
715 | ||
716 | if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) | |
717 | return IXGBE_ERR_SFP_NOT_PRESENT; | |
718 | ||
719 | if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && | |
720 | (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) | |
721 | return IXGBE_ERR_SFP_NOT_SUPPORTED; | |
722 | ||
723 | /* Read offset to PHY init contents */ | |
724 | hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); | |
725 | ||
726 | if ((!*list_offset) || (*list_offset == 0xFFFF)) | |
11afc1b1 | 727 | return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; |
c4900be0 DS |
728 | |
729 | /* Shift offset to first ID word */ | |
730 | (*list_offset)++; | |
731 | ||
732 | /* | |
733 | * Find the matching SFP ID in the EEPROM | |
734 | * and program the init sequence | |
735 | */ | |
736 | hw->eeprom.ops.read(hw, *list_offset, &sfp_id); | |
737 | ||
738 | while (sfp_id != IXGBE_PHY_INIT_END_NL) { | |
739 | if (sfp_id == hw->phy.sfp_type) { | |
740 | (*list_offset)++; | |
741 | hw->eeprom.ops.read(hw, *list_offset, data_offset); | |
742 | if ((!*data_offset) || (*data_offset == 0xFFFF)) { | |
743 | hw_dbg(hw, "SFP+ module not supported\n"); | |
744 | return IXGBE_ERR_SFP_NOT_SUPPORTED; | |
745 | } else { | |
746 | break; | |
747 | } | |
748 | } else { | |
749 | (*list_offset) += 2; | |
750 | if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) | |
751 | return IXGBE_ERR_PHY; | |
752 | } | |
753 | } | |
754 | ||
755 | if (sfp_id == IXGBE_PHY_INIT_END_NL) { | |
756 | hw_dbg(hw, "No matching SFP+ module found\n"); | |
757 | return IXGBE_ERR_SFP_NOT_SUPPORTED; | |
758 | } | |
759 | ||
760 | return 0; | |
761 | } | |
762 | ||
11afc1b1 PW |
763 | /** |
764 | * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface | |
765 | * @hw: pointer to hardware structure | |
766 | * @byte_offset: EEPROM byte offset to read | |
767 | * @eeprom_data: value read | |
768 | * | |
769 | * Performs byte read operation to SFP module's EEPROM over I2C interface. | |
770 | **/ | |
771 | s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, | |
772 | u8 *eeprom_data) | |
773 | { | |
774 | return hw->phy.ops.read_i2c_byte(hw, byte_offset, | |
775 | IXGBE_I2C_EEPROM_DEV_ADDR, | |
776 | eeprom_data); | |
777 | } | |
778 | ||
779 | /** | |
780 | * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface | |
781 | * @hw: pointer to hardware structure | |
782 | * @byte_offset: EEPROM byte offset to write | |
783 | * @eeprom_data: value to write | |
784 | * | |
785 | * Performs byte write operation to SFP module's EEPROM over I2C interface. | |
786 | **/ | |
787 | s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, | |
788 | u8 eeprom_data) | |
789 | { | |
790 | return hw->phy.ops.write_i2c_byte(hw, byte_offset, | |
791 | IXGBE_I2C_EEPROM_DEV_ADDR, | |
792 | eeprom_data); | |
793 | } | |
794 | ||
795 | /** | |
796 | * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C | |
797 | * @hw: pointer to hardware structure | |
798 | * @byte_offset: byte offset to read | |
799 | * @data: value read | |
800 | * | |
801 | * Performs byte read operation to SFP module's EEPROM over I2C interface at | |
802 | * a specified deivce address. | |
803 | **/ | |
804 | s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, | |
805 | u8 dev_addr, u8 *data) | |
806 | { | |
807 | s32 status = 0; | |
808 | u32 max_retry = 1; | |
809 | u32 retry = 0; | |
810 | bool nack = 1; | |
811 | ||
812 | do { | |
813 | ixgbe_i2c_start(hw); | |
814 | ||
815 | /* Device Address and write indication */ | |
816 | status = ixgbe_clock_out_i2c_byte(hw, dev_addr); | |
817 | if (status != 0) | |
818 | goto fail; | |
819 | ||
820 | status = ixgbe_get_i2c_ack(hw); | |
821 | if (status != 0) | |
822 | goto fail; | |
823 | ||
824 | status = ixgbe_clock_out_i2c_byte(hw, byte_offset); | |
825 | if (status != 0) | |
826 | goto fail; | |
827 | ||
828 | status = ixgbe_get_i2c_ack(hw); | |
829 | if (status != 0) | |
830 | goto fail; | |
831 | ||
832 | ixgbe_i2c_start(hw); | |
833 | ||
834 | /* Device Address and read indication */ | |
835 | status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); | |
836 | if (status != 0) | |
837 | goto fail; | |
838 | ||
839 | status = ixgbe_get_i2c_ack(hw); | |
840 | if (status != 0) | |
841 | goto fail; | |
842 | ||
843 | status = ixgbe_clock_in_i2c_byte(hw, data); | |
844 | if (status != 0) | |
845 | goto fail; | |
846 | ||
847 | status = ixgbe_clock_out_i2c_bit(hw, nack); | |
848 | if (status != 0) | |
849 | goto fail; | |
850 | ||
851 | ixgbe_i2c_stop(hw); | |
852 | break; | |
853 | ||
854 | fail: | |
855 | ixgbe_i2c_bus_clear(hw); | |
856 | retry++; | |
857 | if (retry < max_retry) | |
858 | hw_dbg(hw, "I2C byte read error - Retrying.\n"); | |
859 | else | |
860 | hw_dbg(hw, "I2C byte read error.\n"); | |
861 | ||
862 | } while (retry < max_retry); | |
863 | ||
864 | return status; | |
865 | } | |
866 | ||
867 | /** | |
868 | * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C | |
869 | * @hw: pointer to hardware structure | |
870 | * @byte_offset: byte offset to write | |
871 | * @data: value to write | |
872 | * | |
873 | * Performs byte write operation to SFP module's EEPROM over I2C interface at | |
874 | * a specified device address. | |
875 | **/ | |
876 | s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, | |
877 | u8 dev_addr, u8 data) | |
878 | { | |
879 | s32 status = 0; | |
880 | u32 max_retry = 1; | |
881 | u32 retry = 0; | |
882 | ||
883 | do { | |
884 | ixgbe_i2c_start(hw); | |
885 | ||
886 | status = ixgbe_clock_out_i2c_byte(hw, dev_addr); | |
887 | if (status != 0) | |
888 | goto fail; | |
889 | ||
890 | status = ixgbe_get_i2c_ack(hw); | |
891 | if (status != 0) | |
892 | goto fail; | |
893 | ||
894 | status = ixgbe_clock_out_i2c_byte(hw, byte_offset); | |
895 | if (status != 0) | |
896 | goto fail; | |
897 | ||
898 | status = ixgbe_get_i2c_ack(hw); | |
899 | if (status != 0) | |
900 | goto fail; | |
901 | ||
902 | status = ixgbe_clock_out_i2c_byte(hw, data); | |
903 | if (status != 0) | |
904 | goto fail; | |
905 | ||
906 | status = ixgbe_get_i2c_ack(hw); | |
907 | if (status != 0) | |
908 | goto fail; | |
909 | ||
910 | ixgbe_i2c_stop(hw); | |
911 | break; | |
912 | ||
913 | fail: | |
914 | ixgbe_i2c_bus_clear(hw); | |
915 | retry++; | |
916 | if (retry < max_retry) | |
917 | hw_dbg(hw, "I2C byte write error - Retrying.\n"); | |
918 | else | |
919 | hw_dbg(hw, "I2C byte write error.\n"); | |
920 | } while (retry < max_retry); | |
921 | ||
922 | return status; | |
923 | } | |
924 | ||
925 | /** | |
926 | * ixgbe_i2c_start - Sets I2C start condition | |
927 | * @hw: pointer to hardware structure | |
928 | * | |
929 | * Sets I2C start condition (High -> Low on SDA while SCL is High) | |
930 | **/ | |
931 | static void ixgbe_i2c_start(struct ixgbe_hw *hw) | |
932 | { | |
933 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); | |
934 | ||
935 | /* Start condition must begin with data and clock high */ | |
936 | ixgbe_set_i2c_data(hw, &i2cctl, 1); | |
937 | ixgbe_raise_i2c_clk(hw, &i2cctl); | |
938 | ||
939 | /* Setup time for start condition (4.7us) */ | |
940 | udelay(IXGBE_I2C_T_SU_STA); | |
941 | ||
942 | ixgbe_set_i2c_data(hw, &i2cctl, 0); | |
943 | ||
944 | /* Hold time for start condition (4us) */ | |
945 | udelay(IXGBE_I2C_T_HD_STA); | |
946 | ||
947 | ixgbe_lower_i2c_clk(hw, &i2cctl); | |
948 | ||
949 | /* Minimum low period of clock is 4.7 us */ | |
950 | udelay(IXGBE_I2C_T_LOW); | |
951 | ||
952 | } | |
953 | ||
954 | /** | |
955 | * ixgbe_i2c_stop - Sets I2C stop condition | |
956 | * @hw: pointer to hardware structure | |
957 | * | |
958 | * Sets I2C stop condition (Low -> High on SDA while SCL is High) | |
959 | **/ | |
960 | static void ixgbe_i2c_stop(struct ixgbe_hw *hw) | |
961 | { | |
962 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); | |
963 | ||
964 | /* Stop condition must begin with data low and clock high */ | |
965 | ixgbe_set_i2c_data(hw, &i2cctl, 0); | |
966 | ixgbe_raise_i2c_clk(hw, &i2cctl); | |
967 | ||
968 | /* Setup time for stop condition (4us) */ | |
969 | udelay(IXGBE_I2C_T_SU_STO); | |
970 | ||
971 | ixgbe_set_i2c_data(hw, &i2cctl, 1); | |
972 | ||
973 | /* bus free time between stop and start (4.7us)*/ | |
974 | udelay(IXGBE_I2C_T_BUF); | |
975 | } | |
976 | ||
977 | /** | |
978 | * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C | |
979 | * @hw: pointer to hardware structure | |
980 | * @data: data byte to clock in | |
981 | * | |
982 | * Clocks in one byte data via I2C data/clock | |
983 | **/ | |
984 | static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) | |
985 | { | |
986 | s32 status = 0; | |
987 | s32 i; | |
988 | bool bit = 0; | |
989 | ||
990 | for (i = 7; i >= 0; i--) { | |
991 | status = ixgbe_clock_in_i2c_bit(hw, &bit); | |
992 | *data |= bit << i; | |
993 | ||
994 | if (status != 0) | |
995 | break; | |
996 | } | |
997 | ||
998 | return status; | |
999 | } | |
1000 | ||
1001 | /** | |
1002 | * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C | |
1003 | * @hw: pointer to hardware structure | |
1004 | * @data: data byte clocked out | |
1005 | * | |
1006 | * Clocks out one byte data via I2C data/clock | |
1007 | **/ | |
1008 | static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) | |
1009 | { | |
1010 | s32 status = 0; | |
1011 | s32 i; | |
1012 | u32 i2cctl; | |
1013 | bool bit = 0; | |
1014 | ||
1015 | for (i = 7; i >= 0; i--) { | |
1016 | bit = (data >> i) & 0x1; | |
1017 | status = ixgbe_clock_out_i2c_bit(hw, bit); | |
1018 | ||
1019 | if (status != 0) | |
1020 | break; | |
1021 | } | |
1022 | ||
1023 | /* Release SDA line (set high) */ | |
1024 | i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); | |
1025 | i2cctl |= IXGBE_I2C_DATA_OUT; | |
1026 | IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); | |
1027 | ||
1028 | return status; | |
1029 | } | |
1030 | ||
1031 | /** | |
1032 | * ixgbe_get_i2c_ack - Polls for I2C ACK | |
1033 | * @hw: pointer to hardware structure | |
1034 | * | |
1035 | * Clocks in/out one bit via I2C data/clock | |
1036 | **/ | |
1037 | static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) | |
1038 | { | |
1039 | s32 status; | |
1040 | u32 i = 0; | |
1041 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); | |
1042 | u32 timeout = 10; | |
1043 | bool ack = 1; | |
1044 | ||
1045 | status = ixgbe_raise_i2c_clk(hw, &i2cctl); | |
1046 | ||
1047 | if (status != 0) | |
1048 | goto out; | |
1049 | ||
1050 | /* Minimum high period of clock is 4us */ | |
1051 | udelay(IXGBE_I2C_T_HIGH); | |
1052 | ||
1053 | /* Poll for ACK. Note that ACK in I2C spec is | |
1054 | * transition from 1 to 0 */ | |
1055 | for (i = 0; i < timeout; i++) { | |
1056 | i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); | |
1057 | ack = ixgbe_get_i2c_data(&i2cctl); | |
1058 | ||
1059 | udelay(1); | |
1060 | if (ack == 0) | |
1061 | break; | |
1062 | } | |
1063 | ||
1064 | if (ack == 1) { | |
1065 | hw_dbg(hw, "I2C ack was not received.\n"); | |
1066 | status = IXGBE_ERR_I2C; | |
1067 | } | |
1068 | ||
1069 | ixgbe_lower_i2c_clk(hw, &i2cctl); | |
1070 | ||
1071 | /* Minimum low period of clock is 4.7 us */ | |
1072 | udelay(IXGBE_I2C_T_LOW); | |
1073 | ||
1074 | out: | |
1075 | return status; | |
1076 | } | |
1077 | ||
1078 | /** | |
1079 | * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock | |
1080 | * @hw: pointer to hardware structure | |
1081 | * @data: read data value | |
1082 | * | |
1083 | * Clocks in one bit via I2C data/clock | |
1084 | **/ | |
1085 | static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) | |
1086 | { | |
1087 | s32 status; | |
1088 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); | |
1089 | ||
1090 | status = ixgbe_raise_i2c_clk(hw, &i2cctl); | |
1091 | ||
1092 | /* Minimum high period of clock is 4us */ | |
1093 | udelay(IXGBE_I2C_T_HIGH); | |
1094 | ||
1095 | i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); | |
1096 | *data = ixgbe_get_i2c_data(&i2cctl); | |
1097 | ||
1098 | ixgbe_lower_i2c_clk(hw, &i2cctl); | |
1099 | ||
1100 | /* Minimum low period of clock is 4.7 us */ | |
1101 | udelay(IXGBE_I2C_T_LOW); | |
1102 | ||
1103 | return status; | |
1104 | } | |
1105 | ||
1106 | /** | |
1107 | * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock | |
1108 | * @hw: pointer to hardware structure | |
1109 | * @data: data value to write | |
1110 | * | |
1111 | * Clocks out one bit via I2C data/clock | |
1112 | **/ | |
1113 | static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) | |
1114 | { | |
1115 | s32 status; | |
1116 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); | |
1117 | ||
1118 | status = ixgbe_set_i2c_data(hw, &i2cctl, data); | |
1119 | if (status == 0) { | |
1120 | status = ixgbe_raise_i2c_clk(hw, &i2cctl); | |
1121 | ||
1122 | /* Minimum high period of clock is 4us */ | |
1123 | udelay(IXGBE_I2C_T_HIGH); | |
1124 | ||
1125 | ixgbe_lower_i2c_clk(hw, &i2cctl); | |
1126 | ||
1127 | /* Minimum low period of clock is 4.7 us. | |
1128 | * This also takes care of the data hold time. | |
1129 | */ | |
1130 | udelay(IXGBE_I2C_T_LOW); | |
1131 | } else { | |
1132 | status = IXGBE_ERR_I2C; | |
1133 | hw_dbg(hw, "I2C data was not set to %X\n", data); | |
1134 | } | |
1135 | ||
1136 | return status; | |
1137 | } | |
1138 | /** | |
1139 | * ixgbe_raise_i2c_clk - Raises the I2C SCL clock | |
1140 | * @hw: pointer to hardware structure | |
1141 | * @i2cctl: Current value of I2CCTL register | |
1142 | * | |
1143 | * Raises the I2C clock line '0'->'1' | |
1144 | **/ | |
1145 | static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) | |
1146 | { | |
1147 | s32 status = 0; | |
1148 | ||
1149 | *i2cctl |= IXGBE_I2C_CLK_OUT; | |
1150 | ||
1151 | IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); | |
1152 | ||
1153 | /* SCL rise time (1000ns) */ | |
1154 | udelay(IXGBE_I2C_T_RISE); | |
1155 | ||
1156 | return status; | |
1157 | } | |
1158 | ||
1159 | /** | |
1160 | * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock | |
1161 | * @hw: pointer to hardware structure | |
1162 | * @i2cctl: Current value of I2CCTL register | |
1163 | * | |
1164 | * Lowers the I2C clock line '1'->'0' | |
1165 | **/ | |
1166 | static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) | |
1167 | { | |
1168 | ||
1169 | *i2cctl &= ~IXGBE_I2C_CLK_OUT; | |
1170 | ||
1171 | IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); | |
1172 | ||
1173 | /* SCL fall time (300ns) */ | |
1174 | udelay(IXGBE_I2C_T_FALL); | |
1175 | } | |
1176 | ||
1177 | /** | |
1178 | * ixgbe_set_i2c_data - Sets the I2C data bit | |
1179 | * @hw: pointer to hardware structure | |
1180 | * @i2cctl: Current value of I2CCTL register | |
1181 | * @data: I2C data value (0 or 1) to set | |
1182 | * | |
1183 | * Sets the I2C data bit | |
1184 | **/ | |
1185 | static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) | |
1186 | { | |
1187 | s32 status = 0; | |
1188 | ||
1189 | if (data) | |
1190 | *i2cctl |= IXGBE_I2C_DATA_OUT; | |
1191 | else | |
1192 | *i2cctl &= ~IXGBE_I2C_DATA_OUT; | |
1193 | ||
1194 | IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); | |
1195 | ||
1196 | /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ | |
1197 | udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); | |
1198 | ||
1199 | /* Verify data was set correctly */ | |
1200 | *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); | |
1201 | if (data != ixgbe_get_i2c_data(i2cctl)) { | |
1202 | status = IXGBE_ERR_I2C; | |
1203 | hw_dbg(hw, "Error - I2C data was not set to %X.\n", data); | |
1204 | } | |
1205 | ||
1206 | return status; | |
1207 | } | |
1208 | ||
1209 | /** | |
1210 | * ixgbe_get_i2c_data - Reads the I2C SDA data bit | |
1211 | * @hw: pointer to hardware structure | |
1212 | * @i2cctl: Current value of I2CCTL register | |
1213 | * | |
1214 | * Returns the I2C data bit value | |
1215 | **/ | |
1216 | static bool ixgbe_get_i2c_data(u32 *i2cctl) | |
1217 | { | |
1218 | bool data; | |
1219 | ||
1220 | if (*i2cctl & IXGBE_I2C_DATA_IN) | |
1221 | data = 1; | |
1222 | else | |
1223 | data = 0; | |
1224 | ||
1225 | return data; | |
1226 | } | |
1227 | ||
1228 | /** | |
1229 | * ixgbe_i2c_bus_clear - Clears the I2C bus | |
1230 | * @hw: pointer to hardware structure | |
1231 | * | |
1232 | * Clears the I2C bus by sending nine clock pulses. | |
1233 | * Used when data line is stuck low. | |
1234 | **/ | |
1235 | static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) | |
1236 | { | |
1237 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); | |
1238 | u32 i; | |
1239 | ||
1240 | ixgbe_set_i2c_data(hw, &i2cctl, 1); | |
1241 | ||
1242 | for (i = 0; i < 9; i++) { | |
1243 | ixgbe_raise_i2c_clk(hw, &i2cctl); | |
1244 | ||
1245 | /* Min high period of clock is 4us */ | |
1246 | udelay(IXGBE_I2C_T_HIGH); | |
1247 | ||
1248 | ixgbe_lower_i2c_clk(hw, &i2cctl); | |
1249 | ||
1250 | /* Min low period of clock is 4.7us*/ | |
1251 | udelay(IXGBE_I2C_T_LOW); | |
1252 | } | |
1253 | ||
1254 | /* Put the i2c bus back to default state */ | |
1255 | ixgbe_i2c_stop(hw); | |
1256 | } | |
1257 | ||
0befdb3e JB |
1258 | /** |
1259 | * ixgbe_check_phy_link_tnx - Determine link and speed status | |
1260 | * @hw: pointer to hardware structure | |
1261 | * | |
1262 | * Reads the VS1 register to determine if link is up and the current speed for | |
1263 | * the PHY. | |
1264 | **/ | |
1265 | s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, | |
1266 | bool *link_up) | |
1267 | { | |
1268 | s32 status = 0; | |
1269 | u32 time_out; | |
1270 | u32 max_time_out = 10; | |
1271 | u16 phy_link = 0; | |
1272 | u16 phy_speed = 0; | |
1273 | u16 phy_data = 0; | |
1274 | ||
1275 | /* Initialize speed and link to default case */ | |
1276 | *link_up = false; | |
1277 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
1278 | ||
1279 | /* | |
1280 | * Check current speed and link status of the PHY register. | |
1281 | * This is a vendor specific register and may have to | |
1282 | * be changed for other copper PHYs. | |
1283 | */ | |
1284 | for (time_out = 0; time_out < max_time_out; time_out++) { | |
1285 | udelay(10); | |
1286 | status = hw->phy.ops.read_reg(hw, | |
1287 | IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, | |
6b73e10d | 1288 | MDIO_MMD_VEND1, |
0befdb3e JB |
1289 | &phy_data); |
1290 | phy_link = phy_data & | |
1291 | IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; | |
1292 | phy_speed = phy_data & | |
1293 | IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; | |
1294 | if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { | |
1295 | *link_up = true; | |
1296 | if (phy_speed == | |
1297 | IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) | |
1298 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
1299 | break; | |
1300 | } | |
1301 | } | |
1302 | ||
1303 | return status; | |
1304 | } | |
1305 | ||
1306 | /** | |
1307 | * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version | |
1308 | * @hw: pointer to hardware structure | |
1309 | * @firmware_version: pointer to the PHY Firmware Version | |
1310 | **/ | |
1311 | s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, | |
1312 | u16 *firmware_version) | |
1313 | { | |
1314 | s32 status = 0; | |
1315 | ||
6b73e10d | 1316 | status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1, |
0befdb3e JB |
1317 | firmware_version); |
1318 | ||
1319 | return status; | |
1320 | } | |
1321 |