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[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_phy.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe_common.h"
33#include "ixgbe_phy.h"
34
11afc1b1
PW		 35static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
42static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
43static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45static bool ixgbe_get_i2c_data(u32 *i2cctl);
46static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
9a799d71
AK		 47static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
9a799d71
AK		 49
50/**
c44ade9e 51 * ixgbe_identify_phy_generic - Get physical layer module
9a799d71
AK		 52 * @hw: pointer to hardware structure
53 *
54 * Determines the physical layer module found on the current adapter.
55 **/
c44ade9e 56s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
9a799d71
AK		 57{
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
59 u32 phy_addr;
60
c44ade9e
JB		 61 if (hw->phy.type == ixgbe_phy_unknown) {
62 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
63d6e1d8 63 hw->phy.mdio.prtad = phy_addr;
6b73e10d 64 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
c44ade9e
JB		 65 ixgbe_get_phy_id(hw);
66 hw->phy.type =
67 ixgbe_get_phy_type_from_id(hw->phy.id);
68 status = 0;
69 break;
70 }
9a799d71 71 }
63d6e1d8
DS		 72 /* clear value if nothing found */
73 hw->phy.mdio.prtad = 0;
c44ade9e
JB		 74 } else {
75 status = 0;
9a799d71 76 }
c44ade9e 77
9a799d71
AK		 78 return status;
79}
80
9a799d71
AK		 81/**
82 * ixgbe_get_phy_id - Get the phy type
83 * @hw: pointer to hardware structure
84 *
85 **/
86static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
87{
88 u32 status;
89 u16 phy_id_high = 0;
90 u16 phy_id_low = 0;
91
6b73e10d 92 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
c44ade9e 93 &phy_id_high);
9a799d71
AK		 94
95 if (status == 0) {
96 hw->phy.id = (u32)(phy_id_high << 16);
6b73e10d 97 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
c44ade9e 98 &phy_id_low);
9a799d71
AK		 99 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
100 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
101 }
9a799d71
AK		 102 return status;
103}
104
105/**
106 * ixgbe_get_phy_type_from_id - Get the phy type
107 * @hw: pointer to hardware structure
108 *
109 **/
110static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
111{
112 enum ixgbe_phy_type phy_type;
113
114 switch (phy_id) {
0befdb3e
JB		 115 case TN1010_PHY_ID:
116 phy_type = ixgbe_phy_tn;
117 break;
2b264909 118 case X540_PHY_ID:
fe15e8e1
DS		 119 phy_type = ixgbe_phy_aq;
120 break;
9a799d71
AK		 121 case QT2022_PHY_ID:
122 phy_type = ixgbe_phy_qt;
123 break;
c4900be0
DS		 124 case ATH_PHY_ID:
125 phy_type = ixgbe_phy_nl;
126 break;
9a799d71
AK		 127 default:
128 phy_type = ixgbe_phy_unknown;
129 break;
130 }
131
132 return phy_type;
133}
134
135/**
c44ade9e 136 * ixgbe_reset_phy_generic - Performs a PHY reset
9a799d71
AK		 137 * @hw: pointer to hardware structure
138 **/
c44ade9e 139s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
9a799d71 140{
119fc60a
MC		 141 /* Don't reset PHY if it's shut down due to overtemp. */
142 if (!hw->phy.reset_if_overtemp &&
143 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
144 return 0;
145
9a799d71
AK		 146 /*
147 * Perform soft PHY reset to the PHY_XS.
148 * This will cause a soft reset to the PHY
149 */
6b73e10d
BH		 150 return hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
151 MDIO_CTRL1_RESET);
9a799d71
AK		 152}
153
154/**
c44ade9e 155 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
9a799d71
AK		 156 * @hw: pointer to hardware structure
157 * @reg_addr: 32 bit address of PHY register to read
158 * @phy_data: Pointer to read data from PHY register
159 **/
c44ade9e
JB		 160s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
161 u32 device_type, u16 *phy_data)
9a799d71
AK		 162{
163 u32 command;
164 u32 i;
9a799d71
AK		 165 u32 data;
166 s32 status = 0;
167 u16 gssr;
168
169 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
170 gssr = IXGBE_GSSR_PHY1_SM;
171 else
172 gssr = IXGBE_GSSR_PHY0_SM;
173
174 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
175 status = IXGBE_ERR_SWFW_SYNC;
176
177 if (status == 0) {
178 /* Setup and write the address cycle command */
179 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 180 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d 181 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 182 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 183
184 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
185
186 /*
187 * Check every 10 usec to see if the address cycle completed.
188 * The MDI Command bit will clear when the operation is
189 * complete
190 */
c44ade9e 191 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 192 udelay(10);
193
194 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
195
196 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
197 break;
198 }
199
200 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
201 hw_dbg(hw, "PHY address command did not complete.\n");
202 status = IXGBE_ERR_PHY;
203 }
204
205 if (status == 0) {
206 /*
207 * Address cycle complete, setup and write the read
208 * command
209 */
210 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 211 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d
BH		 212 (hw->phy.mdio.prtad <<
213 IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 214 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 215
216 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
217
218 /*
219 * Check every 10 usec to see if the address cycle
220 * completed. The MDI Command bit will clear when the
221 * operation is complete
222 */
c44ade9e 223 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 224 udelay(10);
225
226 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
227
228 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
229 break;
230 }
231
232 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
c44ade9e 233 hw_dbg(hw, "PHY read command didn't complete\n");
9a799d71
AK		 234 status = IXGBE_ERR_PHY;
235 } else {
236 /*
237 * Read operation is complete. Get the data
238 * from MSRWD
239 */
240 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
241 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
242 *phy_data = (u16)(data);
243 }
244 }
245
246 ixgbe_release_swfw_sync(hw, gssr);
247 }
c44ade9e 248
9a799d71
AK		 249 return status;
250}
251
252/**
c44ade9e 253 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
9a799d71
AK		 254 * @hw: pointer to hardware structure
255 * @reg_addr: 32 bit PHY register to write
256 * @device_type: 5 bit device type
257 * @phy_data: Data to write to the PHY register
258 **/
c44ade9e
JB		 259s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
260 u32 device_type, u16 phy_data)
9a799d71
AK		 261{
262 u32 command;
263 u32 i;
9a799d71
AK		 264 s32 status = 0;
265 u16 gssr;
266
267 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
268 gssr = IXGBE_GSSR_PHY1_SM;
269 else
270 gssr = IXGBE_GSSR_PHY0_SM;
271
272 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
273 status = IXGBE_ERR_SWFW_SYNC;
274
275 if (status == 0) {
276 /* Put the data in the MDI single read and write data register*/
277 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
278
279 /* Setup and write the address cycle command */
280 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 281 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d 282 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 283 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 284
285 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
286
287 /*
288 * Check every 10 usec to see if the address cycle completed.
289 * The MDI Command bit will clear when the operation is
290 * complete
291 */
c44ade9e 292 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 293 udelay(10);
294
295 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
296
c44ade9e 297 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71 298 break;
9a799d71
AK		 299 }
300
c44ade9e
JB		 301 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
302 hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71 303 status = IXGBE_ERR_PHY;
c44ade9e 304 }
9a799d71
AK		 305
306 if (status == 0) {
307 /*
308 * Address cycle complete, setup and write the write
309 * command
310 */
311 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 312 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d
BH		 313 (hw->phy.mdio.prtad <<
314 IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 315 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 316
317 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
318
319 /*
320 * Check every 10 usec to see if the address cycle
321 * completed. The MDI Command bit will clear when the
322 * operation is complete
323 */
c44ade9e 324 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 325 udelay(10);
326
327 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
328
c44ade9e 329 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71 330 break;
9a799d71
AK		 331 }
332
c44ade9e
JB		 333 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
334 hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71 335 status = IXGBE_ERR_PHY;
c44ade9e 336 }
9a799d71
AK		 337 }
338
339 ixgbe_release_swfw_sync(hw, gssr);
340 }
341
342 return status;
343}
344
345/**
c44ade9e 346 * ixgbe_setup_phy_link_generic - Set and restart autoneg
9a799d71
AK		 347 * @hw: pointer to hardware structure
348 *
349 * Restart autonegotiation and PHY and waits for completion.
350 **/
c44ade9e 351s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
9a799d71
AK		 352{
353 s32 status = IXGBE_NOT_IMPLEMENTED;
354 u32 time_out;
355 u32 max_time_out = 10;
6b73e10d 356 u16 autoneg_reg;
9a799d71
AK		 357
358 /*
359 * Set advertisement settings in PHY based on autoneg_advertised
360 * settings. If autoneg_advertised = 0, then advertise default values
c44ade9e 361 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can
9a799d71
AK		 362 * for a 1G.
363 */
6b73e10d 364 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
9a799d71
AK		 365
366 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
6b73e10d 367 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
9a799d71 368 else
6b73e10d 369 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
9a799d71 370
6b73e10d 371 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
9a799d71
AK		 372
373 /* Restart PHY autonegotiation and wait for completion */
6b73e10d 374 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg);
9a799d71 375
6b73e10d 376 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
9a799d71 377
6b73e10d 378 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg);
9a799d71
AK		 379
380 /* Wait for autonegotiation to finish */
381 for (time_out = 0; time_out < max_time_out; time_out++) {
382 udelay(10);
383 /* Restart PHY autonegotiation and wait for completion */
6b73e10d 384 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
c44ade9e 385 &autoneg_reg);
9a799d71 386
6b73e10d
BH		 387 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
388 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
9a799d71
AK		 389 status = 0;
390 break;
391 }
392 }
393
394 if (time_out == max_time_out)
395 status = IXGBE_ERR_LINK_SETUP;
396
397 return status;
398}
399
400/**
c44ade9e 401 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
9a799d71
AK		 402 * @hw: pointer to hardware structure
403 * @speed: new link speed
404 * @autoneg: true if autonegotiation enabled
405 **/
c44ade9e
JB		 406s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
407 ixgbe_link_speed speed,
408 bool autoneg,
409 bool autoneg_wait_to_complete)
9a799d71 410{
c44ade9e 411
9a799d71
AK		 412 /*
413 * Clear autoneg_advertised and set new values based on input link
414 * speed.
415 */
416 hw->phy.autoneg_advertised = 0;
417
418 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
419 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
c44ade9e 420
9a799d71
AK		 421 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
422 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
423
424 /* Setup link based on the new speed settings */
c44ade9e 425 hw->phy.ops.setup_link(hw);
9a799d71
AK		 426
427 return 0;
428}
c44ade9e 429
a391f1d5
DS		 430/**
431 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
432 * @hw: pointer to hardware structure
433 * @speed: pointer to link speed
434 * @autoneg: boolean auto-negotiation value
435 *
436 * Determines the link capabilities by reading the AUTOC register.
437 */
438s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
fe15e8e1
DS		 439 ixgbe_link_speed *speed,
440 bool *autoneg)
a391f1d5
DS		 441{
442 s32 status = IXGBE_ERR_LINK_SETUP;
443 u16 speed_ability;
444
445 *speed = 0;
446 *autoneg = true;
447
448 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
449 &speed_ability);
450
451 if (status == 0) {
452 if (speed_ability & MDIO_SPEED_10G)
453 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
454 if (speed_ability & MDIO_PMA_SPEED_1000)
455 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
456 if (speed_ability & MDIO_PMA_SPEED_100)
457 *speed |= IXGBE_LINK_SPEED_100_FULL;
458 }
459
460 return status;
461}
462
c4900be0
DS		 463/**
464 * ixgbe_reset_phy_nl - Performs a PHY reset
465 * @hw: pointer to hardware structure
466 **/
467s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
468{
469 u16 phy_offset, control, eword, edata, block_crc;
470 bool end_data = false;
471 u16 list_offset, data_offset;
472 u16 phy_data = 0;
473 s32 ret_val = 0;
474 u32 i;
475
6b73e10d 476 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
c4900be0
DS		 477
478 /* reset the PHY and poll for completion */
6b73e10d
BH		 479 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
480 (phy_data | MDIO_CTRL1_RESET));
c4900be0
DS		 481
482 for (i = 0; i < 100; i++) {
6b73e10d
BH		 483 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
484 &phy_data);
485 if ((phy_data & MDIO_CTRL1_RESET) == 0)
c4900be0
DS		 486 break;
487 msleep(10);
488 }
489
6b73e10d 490 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
c4900be0
DS		 491 hw_dbg(hw, "PHY reset did not complete.\n");
492 ret_val = IXGBE_ERR_PHY;
493 goto out;
494 }
495
496 /* Get init offsets */
497 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
498 &data_offset);
499 if (ret_val != 0)
500 goto out;
501
502 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
503 data_offset++;
504 while (!end_data) {
505 /*
506 * Read control word from PHY init contents offset
507 */
508 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
509 control = (eword & IXGBE_CONTROL_MASK_NL) >>
510 IXGBE_CONTROL_SHIFT_NL;
511 edata = eword & IXGBE_DATA_MASK_NL;
512 switch (control) {
513 case IXGBE_DELAY_NL:
514 data_offset++;
515 hw_dbg(hw, "DELAY: %d MS\n", edata);
516 msleep(edata);
517 break;
518 case IXGBE_DATA_NL:
d6dbee86 519 hw_dbg(hw, "DATA:\n");
c4900be0
DS		 520 data_offset++;
521 hw->eeprom.ops.read(hw, data_offset++,
522 &phy_offset);
523 for (i = 0; i < edata; i++) {
524 hw->eeprom.ops.read(hw, data_offset, &eword);
525 hw->phy.ops.write_reg(hw, phy_offset,
6b73e10d 526 MDIO_MMD_PMAPMD, eword);
c4900be0
DS		 527 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
528 phy_offset);
529 data_offset++;
530 phy_offset++;
531 }
532 break;
533 case IXGBE_CONTROL_NL:
534 data_offset++;
d6dbee86 535 hw_dbg(hw, "CONTROL:\n");
c4900be0
DS		 536 if (edata == IXGBE_CONTROL_EOL_NL) {
537 hw_dbg(hw, "EOL\n");
538 end_data = true;
539 } else if (edata == IXGBE_CONTROL_SOL_NL) {
540 hw_dbg(hw, "SOL\n");
541 } else {
542 hw_dbg(hw, "Bad control value\n");
543 ret_val = IXGBE_ERR_PHY;
544 goto out;
545 }
546 break;
547 default:
548 hw_dbg(hw, "Bad control type\n");
549 ret_val = IXGBE_ERR_PHY;
550 goto out;
551 }
552 }
553
554out:
555 return ret_val;
556}
557
558/**
76d97dd4 559 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
c4900be0
DS		 560 * @hw: pointer to hardware structure
561 *
76d97dd4 562 * Searches for and identifies the SFP module and assigns appropriate PHY type.
c4900be0
DS		 563 **/
564s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
565{
566 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
567 u32 vendor_oui = 0;
553b4497 568 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
c4900be0
DS		 569 u8 identifier = 0;
570 u8 comp_codes_1g = 0;
571 u8 comp_codes_10g = 0;
11afc1b1 572 u8 oui_bytes[3] = {0, 0, 0};
537d58a0 573 u8 cable_tech = 0;
ea0a04df 574 u8 cable_spec = 0;
11afc1b1 575 u16 enforce_sfp = 0;
c4900be0 576
8ca783ab
DS		 577 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
578 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
579 status = IXGBE_ERR_SFP_NOT_PRESENT;
580 goto out;
581 }
582
76d97dd4
ET		 583 status = hw->phy.ops.read_i2c_eeprom(hw,
584 IXGBE_SFF_IDENTIFIER,
c4900be0
DS		 585 &identifier);
586
76d97dd4
ET		 587 if (status == IXGBE_ERR_SWFW_SYNC ||
588 status == IXGBE_ERR_I2C ||
589 status == IXGBE_ERR_SFP_NOT_PRESENT)
590 goto err_read_i2c_eeprom;
c4900be0 591
76d97dd4
ET		 592 /* LAN ID is needed for sfp_type determination */
593 hw->mac.ops.set_lan_id(hw);
594
595 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
596 hw->phy.type = ixgbe_phy_sfp_unsupported;
597 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
598 } else {
599 status = hw->phy.ops.read_i2c_eeprom(hw,
600 IXGBE_SFF_1GBE_COMP_CODES,
601 &comp_codes_1g);
602
603 if (status == IXGBE_ERR_SWFW_SYNC ||
604 status == IXGBE_ERR_I2C ||
605 status == IXGBE_ERR_SFP_NOT_PRESENT)
606 goto err_read_i2c_eeprom;
607
608 status = hw->phy.ops.read_i2c_eeprom(hw,
609 IXGBE_SFF_10GBE_COMP_CODES,
610 &comp_codes_10g);
611
612 if (status == IXGBE_ERR_SWFW_SYNC ||
613 status == IXGBE_ERR_I2C ||
614 status == IXGBE_ERR_SFP_NOT_PRESENT)
615 goto err_read_i2c_eeprom;
616 status = hw->phy.ops.read_i2c_eeprom(hw,
617 IXGBE_SFF_CABLE_TECHNOLOGY,
618 &cable_tech);
619
620 if (status == IXGBE_ERR_SWFW_SYNC ||
621 status == IXGBE_ERR_I2C ||
622 status == IXGBE_ERR_SFP_NOT_PRESENT)
623 goto err_read_i2c_eeprom;
624
625 /* ID Module
626 * =========
627 * 0 SFP_DA_CU
628 * 1 SFP_SR
629 * 2 SFP_LR
630 * 3 SFP_DA_CORE0 - 82599-specific
631 * 4 SFP_DA_CORE1 - 82599-specific
632 * 5 SFP_SR/LR_CORE0 - 82599-specific
633 * 6 SFP_SR/LR_CORE1 - 82599-specific
634 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
635 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
636 * 9 SFP_1g_cu_CORE0 - 82599-specific
637 * 10 SFP_1g_cu_CORE1 - 82599-specific
638 */
11afc1b1 639 if (hw->mac.type == ixgbe_mac_82598EB) {
537d58a0 640 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
11afc1b1
PW		 641 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
642 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
643 hw->phy.sfp_type = ixgbe_sfp_type_sr;
644 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
645 hw->phy.sfp_type = ixgbe_sfp_type_lr;
646 else
647 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
648 } else if (hw->mac.type == ixgbe_mac_82599EB) {
ea0a04df 649 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
11afc1b1
PW		 650 if (hw->bus.lan_id == 0)
651 hw->phy.sfp_type =
652 ixgbe_sfp_type_da_cu_core0;
653 else
654 hw->phy.sfp_type =
655 ixgbe_sfp_type_da_cu_core1;
ea0a04df
DS		 656 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
657 hw->phy.ops.read_i2c_eeprom(
658 hw, IXGBE_SFF_CABLE_SPEC_COMP,
659 &cable_spec);
660 if (cable_spec &
661 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
662 if (hw->bus.lan_id == 0)
663 hw->phy.sfp_type =
664 ixgbe_sfp_type_da_act_lmt_core0;
665 else
666 hw->phy.sfp_type =
667 ixgbe_sfp_type_da_act_lmt_core1;
668 } else {
669 hw->phy.sfp_type =
76d97dd4 670 ixgbe_sfp_type_unknown;
ea0a04df 671 }
76d97dd4
ET		 672 } else if (comp_codes_10g &
673 (IXGBE_SFF_10GBASESR_CAPABLE |
674 IXGBE_SFF_10GBASELR_CAPABLE)) {
11afc1b1
PW		 675 if (hw->bus.lan_id == 0)
676 hw->phy.sfp_type =
677 ixgbe_sfp_type_srlr_core0;
678 else
679 hw->phy.sfp_type =
680 ixgbe_sfp_type_srlr_core1;
76d97dd4 681 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
cb836a97
DS		 682 if (hw->bus.lan_id == 0)
683 hw->phy.sfp_type =
684 ixgbe_sfp_type_1g_cu_core0;
685 else
686 hw->phy.sfp_type =
687 ixgbe_sfp_type_1g_cu_core1;
76d97dd4 688 } else {
11afc1b1 689 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
76d97dd4 690 }
11afc1b1 691 }
c4900be0 692
553b4497
PW		 693 if (hw->phy.sfp_type != stored_sfp_type)
694 hw->phy.sfp_setup_needed = true;
695
696 /* Determine if the SFP+ PHY is dual speed or not. */
50ac58ba 697 hw->phy.multispeed_fiber = false;
553b4497
PW		 698 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
699 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
700 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
701 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
702 hw->phy.multispeed_fiber = true;
703
c4900be0 704 /* Determine PHY vendor */
04193058 705 if (hw->phy.type != ixgbe_phy_nl) {
c4900be0 706 hw->phy.id = identifier;
76d97dd4 707 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 708 IXGBE_SFF_VENDOR_OUI_BYTE0,
709 &oui_bytes[0]);
76d97dd4
ET		 710
711 if (status == IXGBE_ERR_SWFW_SYNC ||
712 status == IXGBE_ERR_I2C ||
713 status == IXGBE_ERR_SFP_NOT_PRESENT)
714 goto err_read_i2c_eeprom;
715
716 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 717 IXGBE_SFF_VENDOR_OUI_BYTE1,
718 &oui_bytes[1]);
76d97dd4
ET		 719
720 if (status == IXGBE_ERR_SWFW_SYNC ||
721 status == IXGBE_ERR_I2C ||
722 status == IXGBE_ERR_SFP_NOT_PRESENT)
723 goto err_read_i2c_eeprom;
724
725 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 726 IXGBE_SFF_VENDOR_OUI_BYTE2,
727 &oui_bytes[2]);
728
76d97dd4
ET		 729 if (status == IXGBE_ERR_SWFW_SYNC ||
730 status == IXGBE_ERR_I2C ||
731 status == IXGBE_ERR_SFP_NOT_PRESENT)
732 goto err_read_i2c_eeprom;
733
c4900be0
DS		 734 vendor_oui =
735 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
736 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
737 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
738
739 switch (vendor_oui) {
740 case IXGBE_SFF_VENDOR_OUI_TYCO:
537d58a0 741 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
ea0a04df 742 hw->phy.type =
76d97dd4 743 ixgbe_phy_sfp_passive_tyco;
c4900be0
DS		 744 break;
745 case IXGBE_SFF_VENDOR_OUI_FTL:
ea0a04df
DS		 746 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
747 hw->phy.type = ixgbe_phy_sfp_ftl_active;
748 else
749 hw->phy.type = ixgbe_phy_sfp_ftl;
c4900be0
DS		 750 break;
751 case IXGBE_SFF_VENDOR_OUI_AVAGO:
752 hw->phy.type = ixgbe_phy_sfp_avago;
753 break;
11afc1b1
PW		 754 case IXGBE_SFF_VENDOR_OUI_INTEL:
755 hw->phy.type = ixgbe_phy_sfp_intel;
756 break;
c4900be0 757 default:
537d58a0 758 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
ea0a04df 759 hw->phy.type =
76d97dd4 760 ixgbe_phy_sfp_passive_unknown;
ea0a04df
DS		 761 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
762 hw->phy.type =
763 ixgbe_phy_sfp_active_unknown;
c4900be0
DS		 764 else
765 hw->phy.type = ixgbe_phy_sfp_unknown;
766 break;
767 }
768 }
fa466e91 769
76d97dd4 770 /* Allow any DA cable vendor */
ea0a04df
DS		 771 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
772 IXGBE_SFF_DA_ACTIVE_CABLE)) {
fa466e91
WJP		 773 status = 0;
774 goto out;
775 }
776
cb836a97
DS		 777 /* Verify supported 1G SFP modules */
778 if (comp_codes_10g == 0 &&
779 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
780 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
fa466e91
WJP		 781 hw->phy.type = ixgbe_phy_sfp_unsupported;
782 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
783 goto out;
784 }
785
786 /* Anything else 82598-based is supported */
787 if (hw->mac.type == ixgbe_mac_82598EB) {
11afc1b1
PW		 788 status = 0;
789 goto out;
790 }
791
04193058
PWJ		 792 /* This is guaranteed to be 82599, no need to check for NULL */
793 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
cb836a97
DS		 794 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
795 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
796 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
11afc1b1
PW		 797 /* Make sure we're a supported PHY type */
798 if (hw->phy.type == ixgbe_phy_sfp_intel) {
799 status = 0;
800 } else {
801 hw_dbg(hw, "SFP+ module not supported\n");
fa466e91 802 hw->phy.type = ixgbe_phy_sfp_unsupported;
11afc1b1
PW		 803 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
804 }
805 } else {
806 status = 0;
807 }
c4900be0
DS		 808 }
809
810out:
811 return status;
76d97dd4
ET		 812
813err_read_i2c_eeprom:
814 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
815 if (hw->phy.type != ixgbe_phy_nl) {
816 hw->phy.id = 0;
817 hw->phy.type = ixgbe_phy_unknown;
818 }
819 return IXGBE_ERR_SFP_NOT_PRESENT;
c4900be0
DS		 820}
821
822/**
76d97dd4 823 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
c4900be0
DS		 824 * @hw: pointer to hardware structure
825 * @list_offset: offset to the SFP ID list
826 * @data_offset: offset to the SFP data block
827 **/
828s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
829 u16 *list_offset,
830 u16 *data_offset)
831{
832 u16 sfp_id;
cb836a97 833 u16 sfp_type = hw->phy.sfp_type;
c4900be0
DS		 834
835 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
836 return IXGBE_ERR_SFP_NOT_SUPPORTED;
837
838 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
839 return IXGBE_ERR_SFP_NOT_PRESENT;
840
841 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
842 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
843 return IXGBE_ERR_SFP_NOT_SUPPORTED;
844
cb836a97
DS		 845 /*
846 * Limiting active cables and 1G Phys must be initialized as
847 * SR modules
848 */
849 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
850 sfp_type == ixgbe_sfp_type_1g_cu_core0)
851 sfp_type = ixgbe_sfp_type_srlr_core0;
852 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
853 sfp_type == ixgbe_sfp_type_1g_cu_core1)
854 sfp_type = ixgbe_sfp_type_srlr_core1;
855
c4900be0
DS		 856 /* Read offset to PHY init contents */
857 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
858
859 if ((!*list_offset) || (*list_offset == 0xFFFF))
11afc1b1 860 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
c4900be0
DS		 861
862 /* Shift offset to first ID word */
863 (*list_offset)++;
864
865 /*
866 * Find the matching SFP ID in the EEPROM
867 * and program the init sequence
868 */
869 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
870
871 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
cb836a97 872 if (sfp_id == sfp_type) {
c4900be0
DS		 873 (*list_offset)++;
874 hw->eeprom.ops.read(hw, *list_offset, data_offset);
875 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
876 hw_dbg(hw, "SFP+ module not supported\n");
877 return IXGBE_ERR_SFP_NOT_SUPPORTED;
878 } else {
879 break;
880 }
881 } else {
882 (*list_offset) += 2;
883 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
884 return IXGBE_ERR_PHY;
885 }
886 }
887
888 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
889 hw_dbg(hw, "No matching SFP+ module found\n");
890 return IXGBE_ERR_SFP_NOT_SUPPORTED;
891 }
892
893 return 0;
894}
895
11afc1b1
PW		 896/**
897 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
898 * @hw: pointer to hardware structure
899 * @byte_offset: EEPROM byte offset to read
900 * @eeprom_data: value read
901 *
902 * Performs byte read operation to SFP module's EEPROM over I2C interface.
903 **/
904s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
905 u8 *eeprom_data)
906{
907 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
908 IXGBE_I2C_EEPROM_DEV_ADDR,
909 eeprom_data);
910}
911
912/**
913 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
914 * @hw: pointer to hardware structure
915 * @byte_offset: EEPROM byte offset to write
916 * @eeprom_data: value to write
917 *
918 * Performs byte write operation to SFP module's EEPROM over I2C interface.
919 **/
920s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
921 u8 eeprom_data)
922{
923 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
924 IXGBE_I2C_EEPROM_DEV_ADDR,
925 eeprom_data);
926}
927
928/**
929 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
930 * @hw: pointer to hardware structure
931 * @byte_offset: byte offset to read
932 * @data: value read
933 *
934 * Performs byte read operation to SFP module's EEPROM over I2C interface at
935 * a specified deivce address.
936 **/
937s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
938 u8 dev_addr, u8 *data)
939{
940 s32 status = 0;
941 u32 max_retry = 1;
942 u32 retry = 0;
943 bool nack = 1;
944
945 do {
946 ixgbe_i2c_start(hw);
947
948 /* Device Address and write indication */
949 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
950 if (status != 0)
951 goto fail;
952
953 status = ixgbe_get_i2c_ack(hw);
954 if (status != 0)
955 goto fail;
956
957 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
958 if (status != 0)
959 goto fail;
960
961 status = ixgbe_get_i2c_ack(hw);
962 if (status != 0)
963 goto fail;
964
965 ixgbe_i2c_start(hw);
966
967 /* Device Address and read indication */
968 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
969 if (status != 0)
970 goto fail;
971
972 status = ixgbe_get_i2c_ack(hw);
973 if (status != 0)
974 goto fail;
975
976 status = ixgbe_clock_in_i2c_byte(hw, data);
977 if (status != 0)
978 goto fail;
979
980 status = ixgbe_clock_out_i2c_bit(hw, nack);
981 if (status != 0)
982 goto fail;
983
984 ixgbe_i2c_stop(hw);
985 break;
986
987fail:
988 ixgbe_i2c_bus_clear(hw);
989 retry++;
990 if (retry < max_retry)
991 hw_dbg(hw, "I2C byte read error - Retrying.\n");
992 else
993 hw_dbg(hw, "I2C byte read error.\n");
994
995 } while (retry < max_retry);
996
997 return status;
998}
999
1000/**
1001 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1002 * @hw: pointer to hardware structure
1003 * @byte_offset: byte offset to write
1004 * @data: value to write
1005 *
1006 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1007 * a specified device address.
1008 **/
1009s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1010 u8 dev_addr, u8 data)
1011{
1012 s32 status = 0;
1013 u32 max_retry = 1;
1014 u32 retry = 0;
1015
1016 do {
1017 ixgbe_i2c_start(hw);
1018
1019 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1020 if (status != 0)
1021 goto fail;
1022
1023 status = ixgbe_get_i2c_ack(hw);
1024 if (status != 0)
1025 goto fail;
1026
1027 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1028 if (status != 0)
1029 goto fail;
1030
1031 status = ixgbe_get_i2c_ack(hw);
1032 if (status != 0)
1033 goto fail;
1034
1035 status = ixgbe_clock_out_i2c_byte(hw, data);
1036 if (status != 0)
1037 goto fail;
1038
1039 status = ixgbe_get_i2c_ack(hw);
1040 if (status != 0)
1041 goto fail;
1042
1043 ixgbe_i2c_stop(hw);
1044 break;
1045
1046fail:
1047 ixgbe_i2c_bus_clear(hw);
1048 retry++;
1049 if (retry < max_retry)
1050 hw_dbg(hw, "I2C byte write error - Retrying.\n");
1051 else
1052 hw_dbg(hw, "I2C byte write error.\n");
1053 } while (retry < max_retry);
1054
1055 return status;
1056}
1057
1058/**
1059 * ixgbe_i2c_start - Sets I2C start condition
1060 * @hw: pointer to hardware structure
1061 *
1062 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1063 **/
1064static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1065{
1066 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1067
1068 /* Start condition must begin with data and clock high */
1069 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1070 ixgbe_raise_i2c_clk(hw, &i2cctl);
1071
1072 /* Setup time for start condition (4.7us) */
1073 udelay(IXGBE_I2C_T_SU_STA);
1074
1075 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1076
1077 /* Hold time for start condition (4us) */
1078 udelay(IXGBE_I2C_T_HD_STA);
1079
1080 ixgbe_lower_i2c_clk(hw, &i2cctl);
1081
1082 /* Minimum low period of clock is 4.7 us */
1083 udelay(IXGBE_I2C_T_LOW);
1084
1085}
1086
1087/**
1088 * ixgbe_i2c_stop - Sets I2C stop condition
1089 * @hw: pointer to hardware structure
1090 *
1091 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1092 **/
1093static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1094{
1095 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1096
1097 /* Stop condition must begin with data low and clock high */
1098 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1099 ixgbe_raise_i2c_clk(hw, &i2cctl);
1100
1101 /* Setup time for stop condition (4us) */
1102 udelay(IXGBE_I2C_T_SU_STO);
1103
1104 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1105
1106 /* bus free time between stop and start (4.7us)*/
1107 udelay(IXGBE_I2C_T_BUF);
1108}
1109
1110/**
1111 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1112 * @hw: pointer to hardware structure
1113 * @data: data byte to clock in
1114 *
1115 * Clocks in one byte data via I2C data/clock
1116 **/
1117static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1118{
1119 s32 status = 0;
1120 s32 i;
1121 bool bit = 0;
1122
1123 for (i = 7; i >= 0; i--) {
1124 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1125 *data |= bit << i;
1126
1127 if (status != 0)
1128 break;
1129 }
1130
1131 return status;
1132}
1133
1134/**
1135 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1136 * @hw: pointer to hardware structure
1137 * @data: data byte clocked out
1138 *
1139 * Clocks out one byte data via I2C data/clock
1140 **/
1141static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1142{
1143 s32 status = 0;
1144 s32 i;
1145 u32 i2cctl;
1146 bool bit = 0;
1147
1148 for (i = 7; i >= 0; i--) {
1149 bit = (data >> i) & 0x1;
1150 status = ixgbe_clock_out_i2c_bit(hw, bit);
1151
1152 if (status != 0)
1153 break;
1154 }
1155
1156 /* Release SDA line (set high) */
1157 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1158 i2cctl |= IXGBE_I2C_DATA_OUT;
1159 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1160
1161 return status;
1162}
1163
1164/**
1165 * ixgbe_get_i2c_ack - Polls for I2C ACK
1166 * @hw: pointer to hardware structure
1167 *
1168 * Clocks in/out one bit via I2C data/clock
1169 **/
1170static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1171{
1172 s32 status;
1173 u32 i = 0;
1174 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1175 u32 timeout = 10;
1176 bool ack = 1;
1177
1178 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1179
1180 if (status != 0)
1181 goto out;
1182
1183 /* Minimum high period of clock is 4us */
1184 udelay(IXGBE_I2C_T_HIGH);
1185
1186 /* Poll for ACK. Note that ACK in I2C spec is
1187 * transition from 1 to 0 */
1188 for (i = 0; i < timeout; i++) {
1189 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1190 ack = ixgbe_get_i2c_data(&i2cctl);
1191
1192 udelay(1);
1193 if (ack == 0)
1194 break;
1195 }
1196
1197 if (ack == 1) {
1198 hw_dbg(hw, "I2C ack was not received.\n");
1199 status = IXGBE_ERR_I2C;
1200 }
1201
1202 ixgbe_lower_i2c_clk(hw, &i2cctl);
1203
1204 /* Minimum low period of clock is 4.7 us */
1205 udelay(IXGBE_I2C_T_LOW);
1206
1207out:
1208 return status;
1209}
1210
1211/**
1212 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1213 * @hw: pointer to hardware structure
1214 * @data: read data value
1215 *
1216 * Clocks in one bit via I2C data/clock
1217 **/
1218static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1219{
1220 s32 status;
1221 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1222
1223 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1224
1225 /* Minimum high period of clock is 4us */
1226 udelay(IXGBE_I2C_T_HIGH);
1227
1228 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1229 *data = ixgbe_get_i2c_data(&i2cctl);
1230
1231 ixgbe_lower_i2c_clk(hw, &i2cctl);
1232
1233 /* Minimum low period of clock is 4.7 us */
1234 udelay(IXGBE_I2C_T_LOW);
1235
1236 return status;
1237}
1238
1239/**
1240 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1241 * @hw: pointer to hardware structure
1242 * @data: data value to write
1243 *
1244 * Clocks out one bit via I2C data/clock
1245 **/
1246static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1247{
1248 s32 status;
1249 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1250
1251 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1252 if (status == 0) {
1253 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1254
1255 /* Minimum high period of clock is 4us */
1256 udelay(IXGBE_I2C_T_HIGH);
1257
1258 ixgbe_lower_i2c_clk(hw, &i2cctl);
1259
1260 /* Minimum low period of clock is 4.7 us.
1261 * This also takes care of the data hold time.
1262 */
1263 udelay(IXGBE_I2C_T_LOW);
1264 } else {
1265 status = IXGBE_ERR_I2C;
1266 hw_dbg(hw, "I2C data was not set to %X\n", data);
1267 }
1268
1269 return status;
1270}
1271/**
1272 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1273 * @hw: pointer to hardware structure
1274 * @i2cctl: Current value of I2CCTL register
1275 *
1276 * Raises the I2C clock line '0'->'1'
1277 **/
1278static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1279{
1280 s32 status = 0;
1281
1282 *i2cctl |= IXGBE_I2C_CLK_OUT;
1283
1284 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1285
1286 /* SCL rise time (1000ns) */
1287 udelay(IXGBE_I2C_T_RISE);
1288
1289 return status;
1290}
1291
1292/**
1293 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1294 * @hw: pointer to hardware structure
1295 * @i2cctl: Current value of I2CCTL register
1296 *
1297 * Lowers the I2C clock line '1'->'0'
1298 **/
1299static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1300{
1301
1302 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1303
1304 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1305
1306 /* SCL fall time (300ns) */
1307 udelay(IXGBE_I2C_T_FALL);
1308}
1309
1310/**
1311 * ixgbe_set_i2c_data - Sets the I2C data bit
1312 * @hw: pointer to hardware structure
1313 * @i2cctl: Current value of I2CCTL register
1314 * @data: I2C data value (0 or 1) to set
1315 *
1316 * Sets the I2C data bit
1317 **/
1318static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1319{
1320 s32 status = 0;
1321
1322 if (data)
1323 *i2cctl |= IXGBE_I2C_DATA_OUT;
1324 else
1325 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1326
1327 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1328
1329 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1330 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1331
1332 /* Verify data was set correctly */
1333 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1334 if (data != ixgbe_get_i2c_data(i2cctl)) {
1335 status = IXGBE_ERR_I2C;
1336 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1337 }
1338
1339 return status;
1340}
1341
1342/**
1343 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1344 * @hw: pointer to hardware structure
1345 * @i2cctl: Current value of I2CCTL register
1346 *
1347 * Returns the I2C data bit value
1348 **/
1349static bool ixgbe_get_i2c_data(u32 *i2cctl)
1350{
1351 bool data;
1352
1353 if (*i2cctl & IXGBE_I2C_DATA_IN)
1354 data = 1;
1355 else
1356 data = 0;
1357
1358 return data;
1359}
1360
1361/**
1362 * ixgbe_i2c_bus_clear - Clears the I2C bus
1363 * @hw: pointer to hardware structure
1364 *
1365 * Clears the I2C bus by sending nine clock pulses.
1366 * Used when data line is stuck low.
1367 **/
1368static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1369{
1370 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1371 u32 i;
1372
1373 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1374
1375 for (i = 0; i < 9; i++) {
1376 ixgbe_raise_i2c_clk(hw, &i2cctl);
1377
1378 /* Min high period of clock is 4us */
1379 udelay(IXGBE_I2C_T_HIGH);
1380
1381 ixgbe_lower_i2c_clk(hw, &i2cctl);
1382
1383 /* Min low period of clock is 4.7us*/
1384 udelay(IXGBE_I2C_T_LOW);
1385 }
1386
1387 /* Put the i2c bus back to default state */
1388 ixgbe_i2c_stop(hw);
1389}
1390
0befdb3e
JB		 1391/**
1392 * ixgbe_check_phy_link_tnx - Determine link and speed status
1393 * @hw: pointer to hardware structure
1394 *
1395 * Reads the VS1 register to determine if link is up and the current speed for
1396 * the PHY.
1397 **/
1398s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1399 bool *link_up)
1400{
1401 s32 status = 0;
1402 u32 time_out;
1403 u32 max_time_out = 10;
1404 u16 phy_link = 0;
1405 u16 phy_speed = 0;
1406 u16 phy_data = 0;
1407
1408 /* Initialize speed and link to default case */
1409 *link_up = false;
1410 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1411
1412 /*
1413 * Check current speed and link status of the PHY register.
1414 * This is a vendor specific register and may have to
1415 * be changed for other copper PHYs.
1416 */
1417 for (time_out = 0; time_out < max_time_out; time_out++) {
1418 udelay(10);
1419 status = hw->phy.ops.read_reg(hw,
1420 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
6b73e10d 1421 MDIO_MMD_VEND1,
0befdb3e
JB		 1422 &phy_data);
1423 phy_link = phy_data &
1424 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1425 phy_speed = phy_data &
1426 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1427 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1428 *link_up = true;
1429 if (phy_speed ==
1430 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1431 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1432 break;
1433 }
1434 }
1435
1436 return status;
1437}
1438
1439/**
1440 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1441 * @hw: pointer to hardware structure
1442 * @firmware_version: pointer to the PHY Firmware Version
1443 **/
1444s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1445 u16 *firmware_version)
1446{
1447 s32 status = 0;
1448
6b73e10d 1449 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1,
0befdb3e
JB		 1450 firmware_version);
1451
1452 return status;
1453}
1454
fe15e8e1
DS		 1455/**
1456 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1457 * @hw: pointer to hardware structure
1458 * @firmware_version: pointer to the PHY Firmware Version
1459**/
1460s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1461 u16 *firmware_version)
1462{
1463 s32 status = 0;
1464
1465 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, MDIO_MMD_VEND1,
1466 firmware_version);
1467
1468 return status;
1469}
1470
119fc60a
MC		 1471/**
1472 * ixgbe_tn_check_overtemp - Checks if an overtemp occured.
1473 * @hw: pointer to hardware structure
1474 *
1475 * Checks if the LASI temp alarm status was triggered due to overtemp
1476 **/
1477s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1478{
1479 s32 status = 0;
1480 u16 phy_data = 0;
1481
1482 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1483 goto out;
1484
1485 /* Check that the LASI temp alarm status was triggered */
1486 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1487 MDIO_MMD_PMAPMD, &phy_data);
1488
1489 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1490 goto out;
1491
1492 status = IXGBE_ERR_OVERTEMP;
1493out:
1494 return status;
1495}
Linux kernel - Deliverables
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