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Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelv...
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_phy.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe_common.h"
33#include "ixgbe_phy.h"
34
11afc1b1
PW		 35static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
42static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
43static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45static bool ixgbe_get_i2c_data(u32 *i2cctl);
46static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
9a799d71
AK		 47static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
9a799d71
AK		 49
50/**
c44ade9e 51 * ixgbe_identify_phy_generic - Get physical layer module
9a799d71
AK		 52 * @hw: pointer to hardware structure
53 *
54 * Determines the physical layer module found on the current adapter.
55 **/
c44ade9e 56s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
9a799d71
AK		 57{
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
59 u32 phy_addr;
60
c44ade9e
JB		 61 if (hw->phy.type == ixgbe_phy_unknown) {
62 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
6b73e10d 63 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
c44ade9e
JB		 64 ixgbe_get_phy_id(hw);
65 hw->phy.type =
66 ixgbe_get_phy_type_from_id(hw->phy.id);
67 status = 0;
68 break;
69 }
9a799d71 70 }
c44ade9e
JB		 71 } else {
72 status = 0;
9a799d71 73 }
c44ade9e 74
9a799d71
AK		 75 return status;
76}
77
9a799d71
AK		 78/**
79 * ixgbe_get_phy_id - Get the phy type
80 * @hw: pointer to hardware structure
81 *
82 **/
83static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
84{
85 u32 status;
86 u16 phy_id_high = 0;
87 u16 phy_id_low = 0;
88
6b73e10d 89 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
c44ade9e 90 &phy_id_high);
9a799d71
AK		 91
92 if (status == 0) {
93 hw->phy.id = (u32)(phy_id_high << 16);
6b73e10d 94 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
c44ade9e 95 &phy_id_low);
9a799d71
AK		 96 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
97 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
98 }
9a799d71
AK		 99 return status;
100}
101
102/**
103 * ixgbe_get_phy_type_from_id - Get the phy type
104 * @hw: pointer to hardware structure
105 *
106 **/
107static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
108{
109 enum ixgbe_phy_type phy_type;
110
111 switch (phy_id) {
0befdb3e
JB		 112 case TN1010_PHY_ID:
113 phy_type = ixgbe_phy_tn;
114 break;
9a799d71
AK		 115 case QT2022_PHY_ID:
116 phy_type = ixgbe_phy_qt;
117 break;
c4900be0
DS		 118 case ATH_PHY_ID:
119 phy_type = ixgbe_phy_nl;
120 break;
9a799d71
AK		 121 default:
122 phy_type = ixgbe_phy_unknown;
123 break;
124 }
125
126 return phy_type;
127}
128
129/**
c44ade9e 130 * ixgbe_reset_phy_generic - Performs a PHY reset
9a799d71
AK		 131 * @hw: pointer to hardware structure
132 **/
c44ade9e 133s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
9a799d71
AK		 134{
135 /*
136 * Perform soft PHY reset to the PHY_XS.
137 * This will cause a soft reset to the PHY
138 */
6b73e10d
BH		 139 return hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
140 MDIO_CTRL1_RESET);
9a799d71
AK		 141}
142
143/**
c44ade9e 144 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
9a799d71
AK		 145 * @hw: pointer to hardware structure
146 * @reg_addr: 32 bit address of PHY register to read
147 * @phy_data: Pointer to read data from PHY register
148 **/
c44ade9e
JB		 149s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
150 u32 device_type, u16 *phy_data)
9a799d71
AK		 151{
152 u32 command;
153 u32 i;
9a799d71
AK		 154 u32 data;
155 s32 status = 0;
156 u16 gssr;
157
158 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
159 gssr = IXGBE_GSSR_PHY1_SM;
160 else
161 gssr = IXGBE_GSSR_PHY0_SM;
162
163 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
164 status = IXGBE_ERR_SWFW_SYNC;
165
166 if (status == 0) {
167 /* Setup and write the address cycle command */
168 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 169 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d 170 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 171 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 172
173 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
174
175 /*
176 * Check every 10 usec to see if the address cycle completed.
177 * The MDI Command bit will clear when the operation is
178 * complete
179 */
c44ade9e 180 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 181 udelay(10);
182
183 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
184
185 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
186 break;
187 }
188
189 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
190 hw_dbg(hw, "PHY address command did not complete.\n");
191 status = IXGBE_ERR_PHY;
192 }
193
194 if (status == 0) {
195 /*
196 * Address cycle complete, setup and write the read
197 * command
198 */
199 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 200 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d
BH		 201 (hw->phy.mdio.prtad <<
202 IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 203 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 204
205 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
206
207 /*
208 * Check every 10 usec to see if the address cycle
209 * completed. The MDI Command bit will clear when the
210 * operation is complete
211 */
c44ade9e 212 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 213 udelay(10);
214
215 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
216
217 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
218 break;
219 }
220
221 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
c44ade9e 222 hw_dbg(hw, "PHY read command didn't complete\n");
9a799d71
AK		 223 status = IXGBE_ERR_PHY;
224 } else {
225 /*
226 * Read operation is complete. Get the data
227 * from MSRWD
228 */
229 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
230 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
231 *phy_data = (u16)(data);
232 }
233 }
234
235 ixgbe_release_swfw_sync(hw, gssr);
236 }
c44ade9e 237
9a799d71
AK		 238 return status;
239}
240
241/**
c44ade9e 242 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
9a799d71
AK		 243 * @hw: pointer to hardware structure
244 * @reg_addr: 32 bit PHY register to write
245 * @device_type: 5 bit device type
246 * @phy_data: Data to write to the PHY register
247 **/
c44ade9e
JB		 248s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
249 u32 device_type, u16 phy_data)
9a799d71
AK		 250{
251 u32 command;
252 u32 i;
9a799d71
AK		 253 s32 status = 0;
254 u16 gssr;
255
256 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
257 gssr = IXGBE_GSSR_PHY1_SM;
258 else
259 gssr = IXGBE_GSSR_PHY0_SM;
260
261 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
262 status = IXGBE_ERR_SWFW_SYNC;
263
264 if (status == 0) {
265 /* Put the data in the MDI single read and write data register*/
266 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
267
268 /* Setup and write the address cycle command */
269 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 270 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d 271 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 272 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 273
274 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
275
276 /*
277 * Check every 10 usec to see if the address cycle completed.
278 * The MDI Command bit will clear when the operation is
279 * complete
280 */
c44ade9e 281 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 282 udelay(10);
283
284 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
285
c44ade9e 286 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71 287 break;
9a799d71
AK		 288 }
289
c44ade9e
JB		 290 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
291 hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71 292 status = IXGBE_ERR_PHY;
c44ade9e 293 }
9a799d71
AK		 294
295 if (status == 0) {
296 /*
297 * Address cycle complete, setup and write the write
298 * command
299 */
300 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 301 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d
BH		 302 (hw->phy.mdio.prtad <<
303 IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 304 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 305
306 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
307
308 /*
309 * Check every 10 usec to see if the address cycle
310 * completed. The MDI Command bit will clear when the
311 * operation is complete
312 */
c44ade9e 313 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 314 udelay(10);
315
316 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
317
c44ade9e 318 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71 319 break;
9a799d71
AK		 320 }
321
c44ade9e
JB		 322 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
323 hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71 324 status = IXGBE_ERR_PHY;
c44ade9e 325 }
9a799d71
AK		 326 }
327
328 ixgbe_release_swfw_sync(hw, gssr);
329 }
330
331 return status;
332}
333
334/**
c44ade9e 335 * ixgbe_setup_phy_link_generic - Set and restart autoneg
9a799d71
AK		 336 * @hw: pointer to hardware structure
337 *
338 * Restart autonegotiation and PHY and waits for completion.
339 **/
c44ade9e 340s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
9a799d71
AK		 341{
342 s32 status = IXGBE_NOT_IMPLEMENTED;
343 u32 time_out;
344 u32 max_time_out = 10;
6b73e10d 345 u16 autoneg_reg;
9a799d71
AK		 346
347 /*
348 * Set advertisement settings in PHY based on autoneg_advertised
349 * settings. If autoneg_advertised = 0, then advertise default values
c44ade9e 350 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can
9a799d71
AK		 351 * for a 1G.
352 */
6b73e10d 353 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
9a799d71
AK		 354
355 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
6b73e10d 356 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
9a799d71 357 else
6b73e10d 358 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
9a799d71 359
6b73e10d 360 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
9a799d71
AK		 361
362 /* Restart PHY autonegotiation and wait for completion */
6b73e10d 363 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg);
9a799d71 364
6b73e10d 365 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
9a799d71 366
6b73e10d 367 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg);
9a799d71
AK		 368
369 /* Wait for autonegotiation to finish */
370 for (time_out = 0; time_out < max_time_out; time_out++) {
371 udelay(10);
372 /* Restart PHY autonegotiation and wait for completion */
6b73e10d 373 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
c44ade9e 374 &autoneg_reg);
9a799d71 375
6b73e10d
BH		 376 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
377 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
9a799d71
AK		 378 status = 0;
379 break;
380 }
381 }
382
383 if (time_out == max_time_out)
384 status = IXGBE_ERR_LINK_SETUP;
385
386 return status;
387}
388
389/**
c44ade9e 390 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
9a799d71
AK		 391 * @hw: pointer to hardware structure
392 * @speed: new link speed
393 * @autoneg: true if autonegotiation enabled
394 **/
c44ade9e
JB		 395s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
396 ixgbe_link_speed speed,
397 bool autoneg,
398 bool autoneg_wait_to_complete)
9a799d71 399{
c44ade9e 400
9a799d71
AK		 401 /*
402 * Clear autoneg_advertised and set new values based on input link
403 * speed.
404 */
405 hw->phy.autoneg_advertised = 0;
406
407 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
408 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
c44ade9e 409
9a799d71
AK		 410 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
411 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
412
413 /* Setup link based on the new speed settings */
c44ade9e 414 hw->phy.ops.setup_link(hw);
9a799d71
AK		 415
416 return 0;
417}
c44ade9e 418
c4900be0
DS		 419/**
420 * ixgbe_reset_phy_nl - Performs a PHY reset
421 * @hw: pointer to hardware structure
422 **/
423s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
424{
425 u16 phy_offset, control, eword, edata, block_crc;
426 bool end_data = false;
427 u16 list_offset, data_offset;
428 u16 phy_data = 0;
429 s32 ret_val = 0;
430 u32 i;
431
6b73e10d 432 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
c4900be0
DS		 433
434 /* reset the PHY and poll for completion */
6b73e10d
BH		 435 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
436 (phy_data | MDIO_CTRL1_RESET));
c4900be0
DS		 437
438 for (i = 0; i < 100; i++) {
6b73e10d
BH		 439 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
440 &phy_data);
441 if ((phy_data & MDIO_CTRL1_RESET) == 0)
c4900be0
DS		 442 break;
443 msleep(10);
444 }
445
6b73e10d 446 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
c4900be0
DS		 447 hw_dbg(hw, "PHY reset did not complete.\n");
448 ret_val = IXGBE_ERR_PHY;
449 goto out;
450 }
451
452 /* Get init offsets */
453 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
454 &data_offset);
455 if (ret_val != 0)
456 goto out;
457
458 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
459 data_offset++;
460 while (!end_data) {
461 /*
462 * Read control word from PHY init contents offset
463 */
464 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
465 control = (eword & IXGBE_CONTROL_MASK_NL) >>
466 IXGBE_CONTROL_SHIFT_NL;
467 edata = eword & IXGBE_DATA_MASK_NL;
468 switch (control) {
469 case IXGBE_DELAY_NL:
470 data_offset++;
471 hw_dbg(hw, "DELAY: %d MS\n", edata);
472 msleep(edata);
473 break;
474 case IXGBE_DATA_NL:
475 hw_dbg(hw, "DATA: \n");
476 data_offset++;
477 hw->eeprom.ops.read(hw, data_offset++,
478 &phy_offset);
479 for (i = 0; i < edata; i++) {
480 hw->eeprom.ops.read(hw, data_offset, &eword);
481 hw->phy.ops.write_reg(hw, phy_offset,
6b73e10d 482 MDIO_MMD_PMAPMD, eword);
c4900be0
DS		 483 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
484 phy_offset);
485 data_offset++;
486 phy_offset++;
487 }
488 break;
489 case IXGBE_CONTROL_NL:
490 data_offset++;
491 hw_dbg(hw, "CONTROL: \n");
492 if (edata == IXGBE_CONTROL_EOL_NL) {
493 hw_dbg(hw, "EOL\n");
494 end_data = true;
495 } else if (edata == IXGBE_CONTROL_SOL_NL) {
496 hw_dbg(hw, "SOL\n");
497 } else {
498 hw_dbg(hw, "Bad control value\n");
499 ret_val = IXGBE_ERR_PHY;
500 goto out;
501 }
502 break;
503 default:
504 hw_dbg(hw, "Bad control type\n");
505 ret_val = IXGBE_ERR_PHY;
506 goto out;
507 }
508 }
509
510out:
511 return ret_val;
512}
513
514/**
515 * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns
516 * the PHY type.
517 * @hw: pointer to hardware structure
518 *
519 * Searches for and indentifies the SFP module. Assings appropriate PHY type.
520 **/
521s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
522{
523 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
524 u32 vendor_oui = 0;
553b4497 525 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
c4900be0
DS		 526 u8 identifier = 0;
527 u8 comp_codes_1g = 0;
528 u8 comp_codes_10g = 0;
11afc1b1 529 u8 oui_bytes[3] = {0, 0, 0};
537d58a0 530 u8 cable_tech = 0;
11afc1b1 531 u16 enforce_sfp = 0;
c4900be0 532
8ca783ab
DS		 533 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
534 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
535 status = IXGBE_ERR_SFP_NOT_PRESENT;
536 goto out;
537 }
538
c4900be0
DS		 539 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
540 &identifier);
541
8ca783ab
DS		 542 if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) {
543 status = IXGBE_ERR_SFP_NOT_PRESENT;
c4900be0 544 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
8ca783ab
DS		 545 if (hw->phy.type != ixgbe_phy_nl) {
546 hw->phy.id = 0;
547 hw->phy.type = ixgbe_phy_unknown;
548 }
c4900be0
DS		 549 goto out;
550 }
551
552 if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
553 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
554 &comp_codes_1g);
555 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
556 &comp_codes_10g);
537d58a0
PWJ		 557 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY,
558 &cable_tech);
c4900be0
DS		 559
560 /* ID Module
561 * =========
11afc1b1
PW		 562 * 0 SFP_DA_CU
563 * 1 SFP_SR
564 * 2 SFP_LR
565 * 3 SFP_DA_CORE0 - 82599-specific
566 * 4 SFP_DA_CORE1 - 82599-specific
567 * 5 SFP_SR/LR_CORE0 - 82599-specific
568 * 6 SFP_SR/LR_CORE1 - 82599-specific
c4900be0 569 */
11afc1b1 570 if (hw->mac.type == ixgbe_mac_82598EB) {
537d58a0 571 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
11afc1b1
PW		 572 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
573 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
574 hw->phy.sfp_type = ixgbe_sfp_type_sr;
575 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
576 hw->phy.sfp_type = ixgbe_sfp_type_lr;
577 else
578 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
579 } else if (hw->mac.type == ixgbe_mac_82599EB) {
537d58a0 580 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
11afc1b1
PW		 581 if (hw->bus.lan_id == 0)
582 hw->phy.sfp_type =
583 ixgbe_sfp_type_da_cu_core0;
584 else
585 hw->phy.sfp_type =
586 ixgbe_sfp_type_da_cu_core1;
587 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
588 if (hw->bus.lan_id == 0)
589 hw->phy.sfp_type =
590 ixgbe_sfp_type_srlr_core0;
591 else
592 hw->phy.sfp_type =
593 ixgbe_sfp_type_srlr_core1;
594 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
595 if (hw->bus.lan_id == 0)
596 hw->phy.sfp_type =
597 ixgbe_sfp_type_srlr_core0;
598 else
599 hw->phy.sfp_type =
600 ixgbe_sfp_type_srlr_core1;
601 else
602 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
603 }
c4900be0 604
553b4497
PW		 605 if (hw->phy.sfp_type != stored_sfp_type)
606 hw->phy.sfp_setup_needed = true;
607
608 /* Determine if the SFP+ PHY is dual speed or not. */
50ac58ba 609 hw->phy.multispeed_fiber = false;
553b4497
PW		 610 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
611 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
612 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
613 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
614 hw->phy.multispeed_fiber = true;
615
c4900be0 616 /* Determine PHY vendor */
04193058 617 if (hw->phy.type != ixgbe_phy_nl) {
c4900be0
DS		 618 hw->phy.id = identifier;
619 hw->phy.ops.read_i2c_eeprom(hw,
620 IXGBE_SFF_VENDOR_OUI_BYTE0,
621 &oui_bytes[0]);
622 hw->phy.ops.read_i2c_eeprom(hw,
623 IXGBE_SFF_VENDOR_OUI_BYTE1,
624 &oui_bytes[1]);
625 hw->phy.ops.read_i2c_eeprom(hw,
626 IXGBE_SFF_VENDOR_OUI_BYTE2,
627 &oui_bytes[2]);
628
629 vendor_oui =
630 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
631 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
632 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
633
634 switch (vendor_oui) {
635 case IXGBE_SFF_VENDOR_OUI_TYCO:
537d58a0 636 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
c4900be0
DS		 637 hw->phy.type = ixgbe_phy_tw_tyco;
638 break;
639 case IXGBE_SFF_VENDOR_OUI_FTL:
640 hw->phy.type = ixgbe_phy_sfp_ftl;
641 break;
642 case IXGBE_SFF_VENDOR_OUI_AVAGO:
643 hw->phy.type = ixgbe_phy_sfp_avago;
644 break;
11afc1b1
PW		 645 case IXGBE_SFF_VENDOR_OUI_INTEL:
646 hw->phy.type = ixgbe_phy_sfp_intel;
647 break;
c4900be0 648 default:
537d58a0 649 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
c4900be0
DS		 650 hw->phy.type = ixgbe_phy_tw_unknown;
651 else
652 hw->phy.type = ixgbe_phy_sfp_unknown;
653 break;
654 }
655 }
fa466e91 656
537d58a0
PWJ		 657 /* All passive DA cables are supported */
658 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
fa466e91
WJP		 659 status = 0;
660 goto out;
661 }
662
663 /* 1G SFP modules are not supported */
664 if (comp_codes_10g == 0) {
665 hw->phy.type = ixgbe_phy_sfp_unsupported;
666 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
667 goto out;
668 }
669
670 /* Anything else 82598-based is supported */
671 if (hw->mac.type == ixgbe_mac_82598EB) {
11afc1b1
PW		 672 status = 0;
673 goto out;
674 }
675
04193058
PWJ		 676 /* This is guaranteed to be 82599, no need to check for NULL */
677 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
678 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
11afc1b1
PW		 679 /* Make sure we're a supported PHY type */
680 if (hw->phy.type == ixgbe_phy_sfp_intel) {
681 status = 0;
682 } else {
683 hw_dbg(hw, "SFP+ module not supported\n");
fa466e91 684 hw->phy.type = ixgbe_phy_sfp_unsupported;
11afc1b1
PW		 685 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
686 }
687 } else {
688 status = 0;
689 }
c4900be0
DS		 690 }
691
692out:
693 return status;
694}
695
696/**
697 * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see
698 * if it supports a given SFP+ module type, if so it returns the offsets to the
699 * phy init sequence block.
700 * @hw: pointer to hardware structure
701 * @list_offset: offset to the SFP ID list
702 * @data_offset: offset to the SFP data block
703 **/
704s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
705 u16 *list_offset,
706 u16 *data_offset)
707{
708 u16 sfp_id;
709
710 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
711 return IXGBE_ERR_SFP_NOT_SUPPORTED;
712
713 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
714 return IXGBE_ERR_SFP_NOT_PRESENT;
715
716 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
717 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
718 return IXGBE_ERR_SFP_NOT_SUPPORTED;
719
720 /* Read offset to PHY init contents */
721 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
722
723 if ((!*list_offset) || (*list_offset == 0xFFFF))
11afc1b1 724 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
c4900be0
DS		 725
726 /* Shift offset to first ID word */
727 (*list_offset)++;
728
729 /*
730 * Find the matching SFP ID in the EEPROM
731 * and program the init sequence
732 */
733 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
734
735 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
736 if (sfp_id == hw->phy.sfp_type) {
737 (*list_offset)++;
738 hw->eeprom.ops.read(hw, *list_offset, data_offset);
739 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
740 hw_dbg(hw, "SFP+ module not supported\n");
741 return IXGBE_ERR_SFP_NOT_SUPPORTED;
742 } else {
743 break;
744 }
745 } else {
746 (*list_offset) += 2;
747 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
748 return IXGBE_ERR_PHY;
749 }
750 }
751
752 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
753 hw_dbg(hw, "No matching SFP+ module found\n");
754 return IXGBE_ERR_SFP_NOT_SUPPORTED;
755 }
756
757 return 0;
758}
759
11afc1b1
PW		 760/**
761 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
762 * @hw: pointer to hardware structure
763 * @byte_offset: EEPROM byte offset to read
764 * @eeprom_data: value read
765 *
766 * Performs byte read operation to SFP module's EEPROM over I2C interface.
767 **/
768s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
769 u8 *eeprom_data)
770{
771 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
772 IXGBE_I2C_EEPROM_DEV_ADDR,
773 eeprom_data);
774}
775
776/**
777 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
778 * @hw: pointer to hardware structure
779 * @byte_offset: EEPROM byte offset to write
780 * @eeprom_data: value to write
781 *
782 * Performs byte write operation to SFP module's EEPROM over I2C interface.
783 **/
784s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
785 u8 eeprom_data)
786{
787 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
788 IXGBE_I2C_EEPROM_DEV_ADDR,
789 eeprom_data);
790}
791
792/**
793 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
794 * @hw: pointer to hardware structure
795 * @byte_offset: byte offset to read
796 * @data: value read
797 *
798 * Performs byte read operation to SFP module's EEPROM over I2C interface at
799 * a specified deivce address.
800 **/
801s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
802 u8 dev_addr, u8 *data)
803{
804 s32 status = 0;
805 u32 max_retry = 1;
806 u32 retry = 0;
807 bool nack = 1;
808
809 do {
810 ixgbe_i2c_start(hw);
811
812 /* Device Address and write indication */
813 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
814 if (status != 0)
815 goto fail;
816
817 status = ixgbe_get_i2c_ack(hw);
818 if (status != 0)
819 goto fail;
820
821 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
822 if (status != 0)
823 goto fail;
824
825 status = ixgbe_get_i2c_ack(hw);
826 if (status != 0)
827 goto fail;
828
829 ixgbe_i2c_start(hw);
830
831 /* Device Address and read indication */
832 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
833 if (status != 0)
834 goto fail;
835
836 status = ixgbe_get_i2c_ack(hw);
837 if (status != 0)
838 goto fail;
839
840 status = ixgbe_clock_in_i2c_byte(hw, data);
841 if (status != 0)
842 goto fail;
843
844 status = ixgbe_clock_out_i2c_bit(hw, nack);
845 if (status != 0)
846 goto fail;
847
848 ixgbe_i2c_stop(hw);
849 break;
850
851fail:
852 ixgbe_i2c_bus_clear(hw);
853 retry++;
854 if (retry < max_retry)
855 hw_dbg(hw, "I2C byte read error - Retrying.\n");
856 else
857 hw_dbg(hw, "I2C byte read error.\n");
858
859 } while (retry < max_retry);
860
861 return status;
862}
863
864/**
865 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
866 * @hw: pointer to hardware structure
867 * @byte_offset: byte offset to write
868 * @data: value to write
869 *
870 * Performs byte write operation to SFP module's EEPROM over I2C interface at
871 * a specified device address.
872 **/
873s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
874 u8 dev_addr, u8 data)
875{
876 s32 status = 0;
877 u32 max_retry = 1;
878 u32 retry = 0;
879
880 do {
881 ixgbe_i2c_start(hw);
882
883 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
884 if (status != 0)
885 goto fail;
886
887 status = ixgbe_get_i2c_ack(hw);
888 if (status != 0)
889 goto fail;
890
891 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
892 if (status != 0)
893 goto fail;
894
895 status = ixgbe_get_i2c_ack(hw);
896 if (status != 0)
897 goto fail;
898
899 status = ixgbe_clock_out_i2c_byte(hw, data);
900 if (status != 0)
901 goto fail;
902
903 status = ixgbe_get_i2c_ack(hw);
904 if (status != 0)
905 goto fail;
906
907 ixgbe_i2c_stop(hw);
908 break;
909
910fail:
911 ixgbe_i2c_bus_clear(hw);
912 retry++;
913 if (retry < max_retry)
914 hw_dbg(hw, "I2C byte write error - Retrying.\n");
915 else
916 hw_dbg(hw, "I2C byte write error.\n");
917 } while (retry < max_retry);
918
919 return status;
920}
921
922/**
923 * ixgbe_i2c_start - Sets I2C start condition
924 * @hw: pointer to hardware structure
925 *
926 * Sets I2C start condition (High -> Low on SDA while SCL is High)
927 **/
928static void ixgbe_i2c_start(struct ixgbe_hw *hw)
929{
930 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
931
932 /* Start condition must begin with data and clock high */
933 ixgbe_set_i2c_data(hw, &i2cctl, 1);
934 ixgbe_raise_i2c_clk(hw, &i2cctl);
935
936 /* Setup time for start condition (4.7us) */
937 udelay(IXGBE_I2C_T_SU_STA);
938
939 ixgbe_set_i2c_data(hw, &i2cctl, 0);
940
941 /* Hold time for start condition (4us) */
942 udelay(IXGBE_I2C_T_HD_STA);
943
944 ixgbe_lower_i2c_clk(hw, &i2cctl);
945
946 /* Minimum low period of clock is 4.7 us */
947 udelay(IXGBE_I2C_T_LOW);
948
949}
950
951/**
952 * ixgbe_i2c_stop - Sets I2C stop condition
953 * @hw: pointer to hardware structure
954 *
955 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
956 **/
957static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
958{
959 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
960
961 /* Stop condition must begin with data low and clock high */
962 ixgbe_set_i2c_data(hw, &i2cctl, 0);
963 ixgbe_raise_i2c_clk(hw, &i2cctl);
964
965 /* Setup time for stop condition (4us) */
966 udelay(IXGBE_I2C_T_SU_STO);
967
968 ixgbe_set_i2c_data(hw, &i2cctl, 1);
969
970 /* bus free time between stop and start (4.7us)*/
971 udelay(IXGBE_I2C_T_BUF);
972}
973
974/**
975 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
976 * @hw: pointer to hardware structure
977 * @data: data byte to clock in
978 *
979 * Clocks in one byte data via I2C data/clock
980 **/
981static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
982{
983 s32 status = 0;
984 s32 i;
985 bool bit = 0;
986
987 for (i = 7; i >= 0; i--) {
988 status = ixgbe_clock_in_i2c_bit(hw, &bit);
989 *data |= bit << i;
990
991 if (status != 0)
992 break;
993 }
994
995 return status;
996}
997
998/**
999 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1000 * @hw: pointer to hardware structure
1001 * @data: data byte clocked out
1002 *
1003 * Clocks out one byte data via I2C data/clock
1004 **/
1005static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1006{
1007 s32 status = 0;
1008 s32 i;
1009 u32 i2cctl;
1010 bool bit = 0;
1011
1012 for (i = 7; i >= 0; i--) {
1013 bit = (data >> i) & 0x1;
1014 status = ixgbe_clock_out_i2c_bit(hw, bit);
1015
1016 if (status != 0)
1017 break;
1018 }
1019
1020 /* Release SDA line (set high) */
1021 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1022 i2cctl |= IXGBE_I2C_DATA_OUT;
1023 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1024
1025 return status;
1026}
1027
1028/**
1029 * ixgbe_get_i2c_ack - Polls for I2C ACK
1030 * @hw: pointer to hardware structure
1031 *
1032 * Clocks in/out one bit via I2C data/clock
1033 **/
1034static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1035{
1036 s32 status;
1037 u32 i = 0;
1038 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1039 u32 timeout = 10;
1040 bool ack = 1;
1041
1042 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1043
1044 if (status != 0)
1045 goto out;
1046
1047 /* Minimum high period of clock is 4us */
1048 udelay(IXGBE_I2C_T_HIGH);
1049
1050 /* Poll for ACK. Note that ACK in I2C spec is
1051 * transition from 1 to 0 */
1052 for (i = 0; i < timeout; i++) {
1053 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1054 ack = ixgbe_get_i2c_data(&i2cctl);
1055
1056 udelay(1);
1057 if (ack == 0)
1058 break;
1059 }
1060
1061 if (ack == 1) {
1062 hw_dbg(hw, "I2C ack was not received.\n");
1063 status = IXGBE_ERR_I2C;
1064 }
1065
1066 ixgbe_lower_i2c_clk(hw, &i2cctl);
1067
1068 /* Minimum low period of clock is 4.7 us */
1069 udelay(IXGBE_I2C_T_LOW);
1070
1071out:
1072 return status;
1073}
1074
1075/**
1076 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1077 * @hw: pointer to hardware structure
1078 * @data: read data value
1079 *
1080 * Clocks in one bit via I2C data/clock
1081 **/
1082static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1083{
1084 s32 status;
1085 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1086
1087 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1088
1089 /* Minimum high period of clock is 4us */
1090 udelay(IXGBE_I2C_T_HIGH);
1091
1092 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1093 *data = ixgbe_get_i2c_data(&i2cctl);
1094
1095 ixgbe_lower_i2c_clk(hw, &i2cctl);
1096
1097 /* Minimum low period of clock is 4.7 us */
1098 udelay(IXGBE_I2C_T_LOW);
1099
1100 return status;
1101}
1102
1103/**
1104 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1105 * @hw: pointer to hardware structure
1106 * @data: data value to write
1107 *
1108 * Clocks out one bit via I2C data/clock
1109 **/
1110static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1111{
1112 s32 status;
1113 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1114
1115 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1116 if (status == 0) {
1117 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1118
1119 /* Minimum high period of clock is 4us */
1120 udelay(IXGBE_I2C_T_HIGH);
1121
1122 ixgbe_lower_i2c_clk(hw, &i2cctl);
1123
1124 /* Minimum low period of clock is 4.7 us.
1125 * This also takes care of the data hold time.
1126 */
1127 udelay(IXGBE_I2C_T_LOW);
1128 } else {
1129 status = IXGBE_ERR_I2C;
1130 hw_dbg(hw, "I2C data was not set to %X\n", data);
1131 }
1132
1133 return status;
1134}
1135/**
1136 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1137 * @hw: pointer to hardware structure
1138 * @i2cctl: Current value of I2CCTL register
1139 *
1140 * Raises the I2C clock line '0'->'1'
1141 **/
1142static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1143{
1144 s32 status = 0;
1145
1146 *i2cctl |= IXGBE_I2C_CLK_OUT;
1147
1148 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1149
1150 /* SCL rise time (1000ns) */
1151 udelay(IXGBE_I2C_T_RISE);
1152
1153 return status;
1154}
1155
1156/**
1157 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1158 * @hw: pointer to hardware structure
1159 * @i2cctl: Current value of I2CCTL register
1160 *
1161 * Lowers the I2C clock line '1'->'0'
1162 **/
1163static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1164{
1165
1166 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1167
1168 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1169
1170 /* SCL fall time (300ns) */
1171 udelay(IXGBE_I2C_T_FALL);
1172}
1173
1174/**
1175 * ixgbe_set_i2c_data - Sets the I2C data bit
1176 * @hw: pointer to hardware structure
1177 * @i2cctl: Current value of I2CCTL register
1178 * @data: I2C data value (0 or 1) to set
1179 *
1180 * Sets the I2C data bit
1181 **/
1182static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1183{
1184 s32 status = 0;
1185
1186 if (data)
1187 *i2cctl |= IXGBE_I2C_DATA_OUT;
1188 else
1189 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1190
1191 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1192
1193 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1194 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1195
1196 /* Verify data was set correctly */
1197 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1198 if (data != ixgbe_get_i2c_data(i2cctl)) {
1199 status = IXGBE_ERR_I2C;
1200 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1201 }
1202
1203 return status;
1204}
1205
1206/**
1207 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1208 * @hw: pointer to hardware structure
1209 * @i2cctl: Current value of I2CCTL register
1210 *
1211 * Returns the I2C data bit value
1212 **/
1213static bool ixgbe_get_i2c_data(u32 *i2cctl)
1214{
1215 bool data;
1216
1217 if (*i2cctl & IXGBE_I2C_DATA_IN)
1218 data = 1;
1219 else
1220 data = 0;
1221
1222 return data;
1223}
1224
1225/**
1226 * ixgbe_i2c_bus_clear - Clears the I2C bus
1227 * @hw: pointer to hardware structure
1228 *
1229 * Clears the I2C bus by sending nine clock pulses.
1230 * Used when data line is stuck low.
1231 **/
1232static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1233{
1234 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1235 u32 i;
1236
1237 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1238
1239 for (i = 0; i < 9; i++) {
1240 ixgbe_raise_i2c_clk(hw, &i2cctl);
1241
1242 /* Min high period of clock is 4us */
1243 udelay(IXGBE_I2C_T_HIGH);
1244
1245 ixgbe_lower_i2c_clk(hw, &i2cctl);
1246
1247 /* Min low period of clock is 4.7us*/
1248 udelay(IXGBE_I2C_T_LOW);
1249 }
1250
1251 /* Put the i2c bus back to default state */
1252 ixgbe_i2c_stop(hw);
1253}
1254
0befdb3e
JB		 1255/**
1256 * ixgbe_check_phy_link_tnx - Determine link and speed status
1257 * @hw: pointer to hardware structure
1258 *
1259 * Reads the VS1 register to determine if link is up and the current speed for
1260 * the PHY.
1261 **/
1262s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1263 bool *link_up)
1264{
1265 s32 status = 0;
1266 u32 time_out;
1267 u32 max_time_out = 10;
1268 u16 phy_link = 0;
1269 u16 phy_speed = 0;
1270 u16 phy_data = 0;
1271
1272 /* Initialize speed and link to default case */
1273 *link_up = false;
1274 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1275
1276 /*
1277 * Check current speed and link status of the PHY register.
1278 * This is a vendor specific register and may have to
1279 * be changed for other copper PHYs.
1280 */
1281 for (time_out = 0; time_out < max_time_out; time_out++) {
1282 udelay(10);
1283 status = hw->phy.ops.read_reg(hw,
1284 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
6b73e10d 1285 MDIO_MMD_VEND1,
0befdb3e
JB		 1286 &phy_data);
1287 phy_link = phy_data &
1288 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1289 phy_speed = phy_data &
1290 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1291 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1292 *link_up = true;
1293 if (phy_speed ==
1294 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1295 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1296 break;
1297 }
1298 }
1299
1300 return status;
1301}
1302
1303/**
1304 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1305 * @hw: pointer to hardware structure
1306 * @firmware_version: pointer to the PHY Firmware Version
1307 **/
1308s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1309 u16 *firmware_version)
1310{
1311 s32 status = 0;
1312
6b73e10d 1313 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1,
0befdb3e
JB		 1314 firmware_version);
1315
1316 return status;
1317}
1318
Linux kernel - Deliverables
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