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ixgbe: X540 Cleanup
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_phy.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe_common.h"
33#include "ixgbe_phy.h"
34
11afc1b1
PW		 35static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
42static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
43static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45static bool ixgbe_get_i2c_data(u32 *i2cctl);
46static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
9a799d71
AK		 47static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
9a799d71
AK		 49
50/**
c44ade9e 51 * ixgbe_identify_phy_generic - Get physical layer module
9a799d71
AK		 52 * @hw: pointer to hardware structure
53 *
54 * Determines the physical layer module found on the current adapter.
55 **/
c44ade9e 56s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
9a799d71
AK		 57{
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
59 u32 phy_addr;
60
c44ade9e
JB		 61 if (hw->phy.type == ixgbe_phy_unknown) {
62 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
63d6e1d8 63 hw->phy.mdio.prtad = phy_addr;
6b73e10d 64 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
c44ade9e
JB		 65 ixgbe_get_phy_id(hw);
66 hw->phy.type =
67 ixgbe_get_phy_type_from_id(hw->phy.id);
68 status = 0;
69 break;
70 }
9a799d71 71 }
63d6e1d8
DS		 72 /* clear value if nothing found */
73 hw->phy.mdio.prtad = 0;
c44ade9e
JB		 74 } else {
75 status = 0;
9a799d71 76 }
c44ade9e 77
9a799d71
AK		 78 return status;
79}
80
9a799d71
AK		 81/**
82 * ixgbe_get_phy_id - Get the phy type
83 * @hw: pointer to hardware structure
84 *
85 **/
86static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
87{
88 u32 status;
89 u16 phy_id_high = 0;
90 u16 phy_id_low = 0;
91
6b73e10d 92 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
c44ade9e 93 &phy_id_high);
9a799d71
AK		 94
95 if (status == 0) {
96 hw->phy.id = (u32)(phy_id_high << 16);
6b73e10d 97 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
c44ade9e 98 &phy_id_low);
9a799d71
AK		 99 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
100 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
101 }
9a799d71
AK		 102 return status;
103}
104
105/**
106 * ixgbe_get_phy_type_from_id - Get the phy type
107 * @hw: pointer to hardware structure
108 *
109 **/
110static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
111{
112 enum ixgbe_phy_type phy_type;
113
114 switch (phy_id) {
0befdb3e
JB		 115 case TN1010_PHY_ID:
116 phy_type = ixgbe_phy_tn;
117 break;
2b264909 118 case X540_PHY_ID:
fe15e8e1
DS		 119 phy_type = ixgbe_phy_aq;
120 break;
9a799d71
AK		 121 case QT2022_PHY_ID:
122 phy_type = ixgbe_phy_qt;
123 break;
c4900be0
DS		 124 case ATH_PHY_ID:
125 phy_type = ixgbe_phy_nl;
126 break;
9a799d71
AK		 127 default:
128 phy_type = ixgbe_phy_unknown;
129 break;
130 }
131
132 return phy_type;
133}
134
135/**
c44ade9e 136 * ixgbe_reset_phy_generic - Performs a PHY reset
9a799d71
AK		 137 * @hw: pointer to hardware structure
138 **/
c44ade9e 139s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
9a799d71 140{
1783575c
ET		 141 u32 i;
142 u16 ctrl = 0;
143 s32 status = 0;
144
145 if (hw->phy.type == ixgbe_phy_unknown)
146 status = ixgbe_identify_phy_generic(hw);
147
148 if (status != 0 || hw->phy.type == ixgbe_phy_none)
149 goto out;
150
119fc60a
MC		 151 /* Don't reset PHY if it's shut down due to overtemp. */
152 if (!hw->phy.reset_if_overtemp &&
153 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
1783575c 154 goto out;
119fc60a 155
9a799d71
AK		 156 /*
157 * Perform soft PHY reset to the PHY_XS.
158 * This will cause a soft reset to the PHY
159 */
1783575c
ET		 160 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
161 MDIO_MMD_PHYXS,
162 MDIO_CTRL1_RESET);
163
164 /*
165 * Poll for reset bit to self-clear indicating reset is complete.
166 * Some PHYs could take up to 3 seconds to complete and need about
167 * 1.7 usec delay after the reset is complete.
168 */
169 for (i = 0; i < 30; i++) {
170 msleep(100);
171 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
172 MDIO_MMD_PHYXS, &ctrl);
173 if (!(ctrl & MDIO_CTRL1_RESET)) {
174 udelay(2);
175 break;
176 }
177 }
178
179 if (ctrl & MDIO_CTRL1_RESET) {
180 status = IXGBE_ERR_RESET_FAILED;
181 hw_dbg(hw, "PHY reset polling failed to complete.\n");
182 }
183
184out:
185 return status;
9a799d71
AK		 186}
187
188/**
c44ade9e 189 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
9a799d71
AK		 190 * @hw: pointer to hardware structure
191 * @reg_addr: 32 bit address of PHY register to read
192 * @phy_data: Pointer to read data from PHY register
193 **/
c44ade9e
JB		 194s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
195 u32 device_type, u16 *phy_data)
9a799d71
AK		 196{
197 u32 command;
198 u32 i;
9a799d71
AK		 199 u32 data;
200 s32 status = 0;
201 u16 gssr;
202
203 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
204 gssr = IXGBE_GSSR_PHY1_SM;
205 else
206 gssr = IXGBE_GSSR_PHY0_SM;
207
208 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
209 status = IXGBE_ERR_SWFW_SYNC;
210
211 if (status == 0) {
212 /* Setup and write the address cycle command */
213 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 214 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d 215 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 216 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 217
218 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
219
220 /*
221 * Check every 10 usec to see if the address cycle completed.
222 * The MDI Command bit will clear when the operation is
223 * complete
224 */
c44ade9e 225 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 226 udelay(10);
227
228 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
229
230 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
231 break;
232 }
233
234 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
235 hw_dbg(hw, "PHY address command did not complete.\n");
236 status = IXGBE_ERR_PHY;
237 }
238
239 if (status == 0) {
240 /*
241 * Address cycle complete, setup and write the read
242 * command
243 */
244 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 245 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d
BH		 246 (hw->phy.mdio.prtad <<
247 IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 248 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 249
250 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
251
252 /*
253 * Check every 10 usec to see if the address cycle
254 * completed. The MDI Command bit will clear when the
255 * operation is complete
256 */
c44ade9e 257 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 258 udelay(10);
259
260 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
261
262 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
263 break;
264 }
265
266 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
c44ade9e 267 hw_dbg(hw, "PHY read command didn't complete\n");
9a799d71
AK		 268 status = IXGBE_ERR_PHY;
269 } else {
270 /*
271 * Read operation is complete. Get the data
272 * from MSRWD
273 */
274 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
275 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
276 *phy_data = (u16)(data);
277 }
278 }
279
280 ixgbe_release_swfw_sync(hw, gssr);
281 }
c44ade9e 282
9a799d71
AK		 283 return status;
284}
285
286/**
c44ade9e 287 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
9a799d71
AK		 288 * @hw: pointer to hardware structure
289 * @reg_addr: 32 bit PHY register to write
290 * @device_type: 5 bit device type
291 * @phy_data: Data to write to the PHY register
292 **/
c44ade9e
JB		 293s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
294 u32 device_type, u16 phy_data)
9a799d71
AK		 295{
296 u32 command;
297 u32 i;
9a799d71
AK		 298 s32 status = 0;
299 u16 gssr;
300
301 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
302 gssr = IXGBE_GSSR_PHY1_SM;
303 else
304 gssr = IXGBE_GSSR_PHY0_SM;
305
306 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
307 status = IXGBE_ERR_SWFW_SYNC;
308
309 if (status == 0) {
310 /* Put the data in the MDI single read and write data register*/
311 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
312
313 /* Setup and write the address cycle command */
314 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 315 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d 316 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 317 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 318
319 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
320
321 /*
322 * Check every 10 usec to see if the address cycle completed.
323 * The MDI Command bit will clear when the operation is
324 * complete
325 */
c44ade9e 326 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 327 udelay(10);
328
329 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
330
c44ade9e 331 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71 332 break;
9a799d71
AK		 333 }
334
c44ade9e
JB		 335 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
336 hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71 337 status = IXGBE_ERR_PHY;
c44ade9e 338 }
9a799d71
AK		 339
340 if (status == 0) {
341 /*
342 * Address cycle complete, setup and write the write
343 * command
344 */
345 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 346 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d
BH		 347 (hw->phy.mdio.prtad <<
348 IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 349 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 350
351 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
352
353 /*
354 * Check every 10 usec to see if the address cycle
355 * completed. The MDI Command bit will clear when the
356 * operation is complete
357 */
c44ade9e 358 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 359 udelay(10);
360
361 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
362
c44ade9e 363 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71 364 break;
9a799d71
AK		 365 }
366
c44ade9e
JB		 367 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
368 hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71 369 status = IXGBE_ERR_PHY;
c44ade9e 370 }
9a799d71
AK		 371 }
372
373 ixgbe_release_swfw_sync(hw, gssr);
374 }
375
376 return status;
377}
378
379/**
c44ade9e 380 * ixgbe_setup_phy_link_generic - Set and restart autoneg
9a799d71
AK		 381 * @hw: pointer to hardware structure
382 *
383 * Restart autonegotiation and PHY and waits for completion.
384 **/
c44ade9e 385s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
9a799d71
AK		 386{
387 s32 status = IXGBE_NOT_IMPLEMENTED;
388 u32 time_out;
389 u32 max_time_out = 10;
6b73e10d 390 u16 autoneg_reg;
9a799d71
AK		 391
392 /*
393 * Set advertisement settings in PHY based on autoneg_advertised
394 * settings. If autoneg_advertised = 0, then advertise default values
c44ade9e 395 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can
9a799d71
AK		 396 * for a 1G.
397 */
6b73e10d 398 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
9a799d71
AK		 399
400 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
6b73e10d 401 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
9a799d71 402 else
6b73e10d 403 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
9a799d71 404
6b73e10d 405 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
9a799d71
AK		 406
407 /* Restart PHY autonegotiation and wait for completion */
6b73e10d 408 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg);
9a799d71 409
6b73e10d 410 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
9a799d71 411
6b73e10d 412 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg);
9a799d71
AK		 413
414 /* Wait for autonegotiation to finish */
415 for (time_out = 0; time_out < max_time_out; time_out++) {
416 udelay(10);
417 /* Restart PHY autonegotiation and wait for completion */
6b73e10d 418 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
c44ade9e 419 &autoneg_reg);
9a799d71 420
6b73e10d
BH		 421 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
422 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
9a799d71
AK		 423 status = 0;
424 break;
425 }
426 }
427
428 if (time_out == max_time_out)
429 status = IXGBE_ERR_LINK_SETUP;
430
431 return status;
432}
433
434/**
c44ade9e 435 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
9a799d71
AK		 436 * @hw: pointer to hardware structure
437 * @speed: new link speed
438 * @autoneg: true if autonegotiation enabled
439 **/
c44ade9e
JB		 440s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
441 ixgbe_link_speed speed,
442 bool autoneg,
443 bool autoneg_wait_to_complete)
9a799d71 444{
c44ade9e 445
9a799d71
AK		 446 /*
447 * Clear autoneg_advertised and set new values based on input link
448 * speed.
449 */
450 hw->phy.autoneg_advertised = 0;
451
452 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
453 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
c44ade9e 454
9a799d71
AK		 455 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
456 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
457
458 /* Setup link based on the new speed settings */
c44ade9e 459 hw->phy.ops.setup_link(hw);
9a799d71
AK		 460
461 return 0;
462}
c44ade9e 463
a391f1d5
DS		 464/**
465 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
466 * @hw: pointer to hardware structure
467 * @speed: pointer to link speed
468 * @autoneg: boolean auto-negotiation value
469 *
470 * Determines the link capabilities by reading the AUTOC register.
471 */
472s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
fe15e8e1
DS		 473 ixgbe_link_speed *speed,
474 bool *autoneg)
a391f1d5
DS		 475{
476 s32 status = IXGBE_ERR_LINK_SETUP;
477 u16 speed_ability;
478
479 *speed = 0;
480 *autoneg = true;
481
482 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
483 &speed_ability);
484
485 if (status == 0) {
486 if (speed_ability & MDIO_SPEED_10G)
487 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
488 if (speed_ability & MDIO_PMA_SPEED_1000)
489 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
490 if (speed_ability & MDIO_PMA_SPEED_100)
491 *speed |= IXGBE_LINK_SPEED_100_FULL;
492 }
493
494 return status;
495}
496
c4900be0
DS		 497/**
498 * ixgbe_reset_phy_nl - Performs a PHY reset
499 * @hw: pointer to hardware structure
500 **/
501s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
502{
503 u16 phy_offset, control, eword, edata, block_crc;
504 bool end_data = false;
505 u16 list_offset, data_offset;
506 u16 phy_data = 0;
507 s32 ret_val = 0;
508 u32 i;
509
6b73e10d 510 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
c4900be0
DS		 511
512 /* reset the PHY and poll for completion */
6b73e10d
BH		 513 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
514 (phy_data | MDIO_CTRL1_RESET));
c4900be0
DS		 515
516 for (i = 0; i < 100; i++) {
6b73e10d
BH		 517 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
518 &phy_data);
519 if ((phy_data & MDIO_CTRL1_RESET) == 0)
c4900be0
DS		 520 break;
521 msleep(10);
522 }
523
6b73e10d 524 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
c4900be0
DS		 525 hw_dbg(hw, "PHY reset did not complete.\n");
526 ret_val = IXGBE_ERR_PHY;
527 goto out;
528 }
529
530 /* Get init offsets */
531 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
532 &data_offset);
533 if (ret_val != 0)
534 goto out;
535
536 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
537 data_offset++;
538 while (!end_data) {
539 /*
540 * Read control word from PHY init contents offset
541 */
542 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
543 control = (eword & IXGBE_CONTROL_MASK_NL) >>
544 IXGBE_CONTROL_SHIFT_NL;
545 edata = eword & IXGBE_DATA_MASK_NL;
546 switch (control) {
547 case IXGBE_DELAY_NL:
548 data_offset++;
549 hw_dbg(hw, "DELAY: %d MS\n", edata);
550 msleep(edata);
551 break;
552 case IXGBE_DATA_NL:
d6dbee86 553 hw_dbg(hw, "DATA:\n");
c4900be0
DS		 554 data_offset++;
555 hw->eeprom.ops.read(hw, data_offset++,
556 &phy_offset);
557 for (i = 0; i < edata; i++) {
558 hw->eeprom.ops.read(hw, data_offset, &eword);
559 hw->phy.ops.write_reg(hw, phy_offset,
6b73e10d 560 MDIO_MMD_PMAPMD, eword);
c4900be0
DS		 561 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
562 phy_offset);
563 data_offset++;
564 phy_offset++;
565 }
566 break;
567 case IXGBE_CONTROL_NL:
568 data_offset++;
d6dbee86 569 hw_dbg(hw, "CONTROL:\n");
c4900be0
DS		 570 if (edata == IXGBE_CONTROL_EOL_NL) {
571 hw_dbg(hw, "EOL\n");
572 end_data = true;
573 } else if (edata == IXGBE_CONTROL_SOL_NL) {
574 hw_dbg(hw, "SOL\n");
575 } else {
576 hw_dbg(hw, "Bad control value\n");
577 ret_val = IXGBE_ERR_PHY;
578 goto out;
579 }
580 break;
581 default:
582 hw_dbg(hw, "Bad control type\n");
583 ret_val = IXGBE_ERR_PHY;
584 goto out;
585 }
586 }
587
588out:
589 return ret_val;
590}
591
592/**
76d97dd4 593 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
c4900be0
DS		 594 * @hw: pointer to hardware structure
595 *
76d97dd4 596 * Searches for and identifies the SFP module and assigns appropriate PHY type.
c4900be0
DS		 597 **/
598s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
599{
600 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
601 u32 vendor_oui = 0;
553b4497 602 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
c4900be0
DS		 603 u8 identifier = 0;
604 u8 comp_codes_1g = 0;
605 u8 comp_codes_10g = 0;
11afc1b1 606 u8 oui_bytes[3] = {0, 0, 0};
537d58a0 607 u8 cable_tech = 0;
ea0a04df 608 u8 cable_spec = 0;
11afc1b1 609 u16 enforce_sfp = 0;
c4900be0 610
8ca783ab
DS		 611 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
612 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
613 status = IXGBE_ERR_SFP_NOT_PRESENT;
614 goto out;
615 }
616
76d97dd4
ET		 617 status = hw->phy.ops.read_i2c_eeprom(hw,
618 IXGBE_SFF_IDENTIFIER,
c4900be0
DS		 619 &identifier);
620
76d97dd4
ET		 621 if (status == IXGBE_ERR_SWFW_SYNC ||
622 status == IXGBE_ERR_I2C ||
623 status == IXGBE_ERR_SFP_NOT_PRESENT)
624 goto err_read_i2c_eeprom;
c4900be0 625
76d97dd4
ET		 626 /* LAN ID is needed for sfp_type determination */
627 hw->mac.ops.set_lan_id(hw);
628
629 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
630 hw->phy.type = ixgbe_phy_sfp_unsupported;
631 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
632 } else {
633 status = hw->phy.ops.read_i2c_eeprom(hw,
634 IXGBE_SFF_1GBE_COMP_CODES,
635 &comp_codes_1g);
636
637 if (status == IXGBE_ERR_SWFW_SYNC ||
638 status == IXGBE_ERR_I2C ||
639 status == IXGBE_ERR_SFP_NOT_PRESENT)
640 goto err_read_i2c_eeprom;
641
642 status = hw->phy.ops.read_i2c_eeprom(hw,
643 IXGBE_SFF_10GBE_COMP_CODES,
644 &comp_codes_10g);
645
646 if (status == IXGBE_ERR_SWFW_SYNC ||
647 status == IXGBE_ERR_I2C ||
648 status == IXGBE_ERR_SFP_NOT_PRESENT)
649 goto err_read_i2c_eeprom;
650 status = hw->phy.ops.read_i2c_eeprom(hw,
651 IXGBE_SFF_CABLE_TECHNOLOGY,
652 &cable_tech);
653
654 if (status == IXGBE_ERR_SWFW_SYNC ||
655 status == IXGBE_ERR_I2C ||
656 status == IXGBE_ERR_SFP_NOT_PRESENT)
657 goto err_read_i2c_eeprom;
658
659 /* ID Module
660 * =========
661 * 0 SFP_DA_CU
662 * 1 SFP_SR
663 * 2 SFP_LR
664 * 3 SFP_DA_CORE0 - 82599-specific
665 * 4 SFP_DA_CORE1 - 82599-specific
666 * 5 SFP_SR/LR_CORE0 - 82599-specific
667 * 6 SFP_SR/LR_CORE1 - 82599-specific
668 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
669 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
670 * 9 SFP_1g_cu_CORE0 - 82599-specific
671 * 10 SFP_1g_cu_CORE1 - 82599-specific
672 */
11afc1b1 673 if (hw->mac.type == ixgbe_mac_82598EB) {
537d58a0 674 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
11afc1b1
PW		 675 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
676 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
677 hw->phy.sfp_type = ixgbe_sfp_type_sr;
678 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
679 hw->phy.sfp_type = ixgbe_sfp_type_lr;
680 else
681 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
682 } else if (hw->mac.type == ixgbe_mac_82599EB) {
ea0a04df 683 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
11afc1b1
PW		 684 if (hw->bus.lan_id == 0)
685 hw->phy.sfp_type =
686 ixgbe_sfp_type_da_cu_core0;
687 else
688 hw->phy.sfp_type =
689 ixgbe_sfp_type_da_cu_core1;
ea0a04df
DS		 690 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
691 hw->phy.ops.read_i2c_eeprom(
692 hw, IXGBE_SFF_CABLE_SPEC_COMP,
693 &cable_spec);
694 if (cable_spec &
695 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
696 if (hw->bus.lan_id == 0)
697 hw->phy.sfp_type =
698 ixgbe_sfp_type_da_act_lmt_core0;
699 else
700 hw->phy.sfp_type =
701 ixgbe_sfp_type_da_act_lmt_core1;
702 } else {
703 hw->phy.sfp_type =
76d97dd4 704 ixgbe_sfp_type_unknown;
ea0a04df 705 }
76d97dd4
ET		 706 } else if (comp_codes_10g &
707 (IXGBE_SFF_10GBASESR_CAPABLE |
708 IXGBE_SFF_10GBASELR_CAPABLE)) {
11afc1b1
PW		 709 if (hw->bus.lan_id == 0)
710 hw->phy.sfp_type =
711 ixgbe_sfp_type_srlr_core0;
712 else
713 hw->phy.sfp_type =
714 ixgbe_sfp_type_srlr_core1;
76d97dd4 715 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
cb836a97
DS		 716 if (hw->bus.lan_id == 0)
717 hw->phy.sfp_type =
718 ixgbe_sfp_type_1g_cu_core0;
719 else
720 hw->phy.sfp_type =
721 ixgbe_sfp_type_1g_cu_core1;
76d97dd4 722 } else {
11afc1b1 723 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
76d97dd4 724 }
11afc1b1 725 }
c4900be0 726
553b4497
PW		 727 if (hw->phy.sfp_type != stored_sfp_type)
728 hw->phy.sfp_setup_needed = true;
729
730 /* Determine if the SFP+ PHY is dual speed or not. */
50ac58ba 731 hw->phy.multispeed_fiber = false;
553b4497
PW		 732 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
733 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
734 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
735 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
736 hw->phy.multispeed_fiber = true;
737
c4900be0 738 /* Determine PHY vendor */
04193058 739 if (hw->phy.type != ixgbe_phy_nl) {
c4900be0 740 hw->phy.id = identifier;
76d97dd4 741 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 742 IXGBE_SFF_VENDOR_OUI_BYTE0,
743 &oui_bytes[0]);
76d97dd4
ET		 744
745 if (status == IXGBE_ERR_SWFW_SYNC ||
746 status == IXGBE_ERR_I2C ||
747 status == IXGBE_ERR_SFP_NOT_PRESENT)
748 goto err_read_i2c_eeprom;
749
750 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 751 IXGBE_SFF_VENDOR_OUI_BYTE1,
752 &oui_bytes[1]);
76d97dd4
ET		 753
754 if (status == IXGBE_ERR_SWFW_SYNC ||
755 status == IXGBE_ERR_I2C ||
756 status == IXGBE_ERR_SFP_NOT_PRESENT)
757 goto err_read_i2c_eeprom;
758
759 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 760 IXGBE_SFF_VENDOR_OUI_BYTE2,
761 &oui_bytes[2]);
762
76d97dd4
ET		 763 if (status == IXGBE_ERR_SWFW_SYNC ||
764 status == IXGBE_ERR_I2C ||
765 status == IXGBE_ERR_SFP_NOT_PRESENT)
766 goto err_read_i2c_eeprom;
767
c4900be0
DS		 768 vendor_oui =
769 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
770 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
771 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
772
773 switch (vendor_oui) {
774 case IXGBE_SFF_VENDOR_OUI_TYCO:
537d58a0 775 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
ea0a04df 776 hw->phy.type =
76d97dd4 777 ixgbe_phy_sfp_passive_tyco;
c4900be0
DS		 778 break;
779 case IXGBE_SFF_VENDOR_OUI_FTL:
ea0a04df
DS		 780 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
781 hw->phy.type = ixgbe_phy_sfp_ftl_active;
782 else
783 hw->phy.type = ixgbe_phy_sfp_ftl;
c4900be0
DS		 784 break;
785 case IXGBE_SFF_VENDOR_OUI_AVAGO:
786 hw->phy.type = ixgbe_phy_sfp_avago;
787 break;
11afc1b1
PW		 788 case IXGBE_SFF_VENDOR_OUI_INTEL:
789 hw->phy.type = ixgbe_phy_sfp_intel;
790 break;
c4900be0 791 default:
537d58a0 792 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
ea0a04df 793 hw->phy.type =
76d97dd4 794 ixgbe_phy_sfp_passive_unknown;
ea0a04df
DS		 795 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
796 hw->phy.type =
797 ixgbe_phy_sfp_active_unknown;
c4900be0
DS		 798 else
799 hw->phy.type = ixgbe_phy_sfp_unknown;
800 break;
801 }
802 }
fa466e91 803
76d97dd4 804 /* Allow any DA cable vendor */
ea0a04df
DS		 805 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
806 IXGBE_SFF_DA_ACTIVE_CABLE)) {
fa466e91
WJP		 807 status = 0;
808 goto out;
809 }
810
cb836a97
DS		 811 /* Verify supported 1G SFP modules */
812 if (comp_codes_10g == 0 &&
813 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
814 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
fa466e91
WJP		 815 hw->phy.type = ixgbe_phy_sfp_unsupported;
816 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
817 goto out;
818 }
819
820 /* Anything else 82598-based is supported */
821 if (hw->mac.type == ixgbe_mac_82598EB) {
11afc1b1
PW		 822 status = 0;
823 goto out;
824 }
825
04193058
PWJ		 826 /* This is guaranteed to be 82599, no need to check for NULL */
827 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
cb836a97
DS		 828 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
829 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
830 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
11afc1b1
PW		 831 /* Make sure we're a supported PHY type */
832 if (hw->phy.type == ixgbe_phy_sfp_intel) {
833 status = 0;
834 } else {
835 hw_dbg(hw, "SFP+ module not supported\n");
fa466e91 836 hw->phy.type = ixgbe_phy_sfp_unsupported;
11afc1b1
PW		 837 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
838 }
839 } else {
840 status = 0;
841 }
c4900be0
DS		 842 }
843
844out:
845 return status;
76d97dd4
ET		 846
847err_read_i2c_eeprom:
848 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
849 if (hw->phy.type != ixgbe_phy_nl) {
850 hw->phy.id = 0;
851 hw->phy.type = ixgbe_phy_unknown;
852 }
853 return IXGBE_ERR_SFP_NOT_PRESENT;
c4900be0
DS		 854}
855
856/**
76d97dd4 857 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
c4900be0
DS		 858 * @hw: pointer to hardware structure
859 * @list_offset: offset to the SFP ID list
860 * @data_offset: offset to the SFP data block
75f19c3c
ET		 861 *
862 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
863 * so it returns the offsets to the phy init sequence block.
c4900be0
DS		 864 **/
865s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
866 u16 *list_offset,
867 u16 *data_offset)
868{
869 u16 sfp_id;
cb836a97 870 u16 sfp_type = hw->phy.sfp_type;
c4900be0
DS		 871
872 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
873 return IXGBE_ERR_SFP_NOT_SUPPORTED;
874
875 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
876 return IXGBE_ERR_SFP_NOT_PRESENT;
877
878 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
879 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
880 return IXGBE_ERR_SFP_NOT_SUPPORTED;
881
cb836a97
DS		 882 /*
883 * Limiting active cables and 1G Phys must be initialized as
884 * SR modules
885 */
886 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
887 sfp_type == ixgbe_sfp_type_1g_cu_core0)
888 sfp_type = ixgbe_sfp_type_srlr_core0;
889 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
890 sfp_type == ixgbe_sfp_type_1g_cu_core1)
891 sfp_type = ixgbe_sfp_type_srlr_core1;
892
c4900be0
DS		 893 /* Read offset to PHY init contents */
894 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
895
896 if ((!*list_offset) || (*list_offset == 0xFFFF))
11afc1b1 897 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
c4900be0
DS		 898
899 /* Shift offset to first ID word */
900 (*list_offset)++;
901
902 /*
903 * Find the matching SFP ID in the EEPROM
904 * and program the init sequence
905 */
906 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
907
908 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
cb836a97 909 if (sfp_id == sfp_type) {
c4900be0
DS		 910 (*list_offset)++;
911 hw->eeprom.ops.read(hw, *list_offset, data_offset);
912 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
913 hw_dbg(hw, "SFP+ module not supported\n");
914 return IXGBE_ERR_SFP_NOT_SUPPORTED;
915 } else {
916 break;
917 }
918 } else {
919 (*list_offset) += 2;
920 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
921 return IXGBE_ERR_PHY;
922 }
923 }
924
925 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
926 hw_dbg(hw, "No matching SFP+ module found\n");
927 return IXGBE_ERR_SFP_NOT_SUPPORTED;
928 }
929
930 return 0;
931}
932
11afc1b1
PW		 933/**
934 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
935 * @hw: pointer to hardware structure
936 * @byte_offset: EEPROM byte offset to read
937 * @eeprom_data: value read
938 *
939 * Performs byte read operation to SFP module's EEPROM over I2C interface.
940 **/
941s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
942 u8 *eeprom_data)
943{
944 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
945 IXGBE_I2C_EEPROM_DEV_ADDR,
946 eeprom_data);
947}
948
949/**
950 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
951 * @hw: pointer to hardware structure
952 * @byte_offset: EEPROM byte offset to write
953 * @eeprom_data: value to write
954 *
955 * Performs byte write operation to SFP module's EEPROM over I2C interface.
956 **/
957s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
958 u8 eeprom_data)
959{
960 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
961 IXGBE_I2C_EEPROM_DEV_ADDR,
962 eeprom_data);
963}
964
965/**
966 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
967 * @hw: pointer to hardware structure
968 * @byte_offset: byte offset to read
969 * @data: value read
970 *
971 * Performs byte read operation to SFP module's EEPROM over I2C interface at
972 * a specified deivce address.
973 **/
974s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
975 u8 dev_addr, u8 *data)
976{
977 s32 status = 0;
75f19c3c 978 u32 max_retry = 10;
11afc1b1 979 u32 retry = 0;
75f19c3c 980 u16 swfw_mask = 0;
11afc1b1
PW		 981 bool nack = 1;
982
75f19c3c
ET		 983 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
984 swfw_mask = IXGBE_GSSR_PHY1_SM;
985 else
986 swfw_mask = IXGBE_GSSR_PHY0_SM;
987
11afc1b1 988 do {
75f19c3c
ET		 989 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) {
990 status = IXGBE_ERR_SWFW_SYNC;
991 goto read_byte_out;
992 }
993
11afc1b1
PW		 994 ixgbe_i2c_start(hw);
995
996 /* Device Address and write indication */
997 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
998 if (status != 0)
999 goto fail;
1000
1001 status = ixgbe_get_i2c_ack(hw);
1002 if (status != 0)
1003 goto fail;
1004
1005 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1006 if (status != 0)
1007 goto fail;
1008
1009 status = ixgbe_get_i2c_ack(hw);
1010 if (status != 0)
1011 goto fail;
1012
1013 ixgbe_i2c_start(hw);
1014
1015 /* Device Address and read indication */
1016 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1017 if (status != 0)
1018 goto fail;
1019
1020 status = ixgbe_get_i2c_ack(hw);
1021 if (status != 0)
1022 goto fail;
1023
1024 status = ixgbe_clock_in_i2c_byte(hw, data);
1025 if (status != 0)
1026 goto fail;
1027
1028 status = ixgbe_clock_out_i2c_bit(hw, nack);
1029 if (status != 0)
1030 goto fail;
1031
1032 ixgbe_i2c_stop(hw);
1033 break;
1034
1035fail:
75f19c3c
ET		 1036 ixgbe_release_swfw_sync(hw, swfw_mask);
1037 msleep(100);
11afc1b1
PW		 1038 ixgbe_i2c_bus_clear(hw);
1039 retry++;
1040 if (retry < max_retry)
1041 hw_dbg(hw, "I2C byte read error - Retrying.\n");
1042 else
1043 hw_dbg(hw, "I2C byte read error.\n");
1044
1045 } while (retry < max_retry);
1046
75f19c3c
ET		 1047 ixgbe_release_swfw_sync(hw, swfw_mask);
1048
1049read_byte_out:
11afc1b1
PW		 1050 return status;
1051}
1052
1053/**
1054 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1055 * @hw: pointer to hardware structure
1056 * @byte_offset: byte offset to write
1057 * @data: value to write
1058 *
1059 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1060 * a specified device address.
1061 **/
1062s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1063 u8 dev_addr, u8 data)
1064{
1065 s32 status = 0;
1066 u32 max_retry = 1;
1067 u32 retry = 0;
75f19c3c
ET		 1068 u16 swfw_mask = 0;
1069
1070 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1071 swfw_mask = IXGBE_GSSR_PHY1_SM;
1072 else
1073 swfw_mask = IXGBE_GSSR_PHY0_SM;
1074
1075 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) {
1076 status = IXGBE_ERR_SWFW_SYNC;
1077 goto write_byte_out;
1078 }
11afc1b1
PW		 1079
1080 do {
1081 ixgbe_i2c_start(hw);
1082
1083 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1084 if (status != 0)
1085 goto fail;
1086
1087 status = ixgbe_get_i2c_ack(hw);
1088 if (status != 0)
1089 goto fail;
1090
1091 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1092 if (status != 0)
1093 goto fail;
1094
1095 status = ixgbe_get_i2c_ack(hw);
1096 if (status != 0)
1097 goto fail;
1098
1099 status = ixgbe_clock_out_i2c_byte(hw, data);
1100 if (status != 0)
1101 goto fail;
1102
1103 status = ixgbe_get_i2c_ack(hw);
1104 if (status != 0)
1105 goto fail;
1106
1107 ixgbe_i2c_stop(hw);
1108 break;
1109
1110fail:
1111 ixgbe_i2c_bus_clear(hw);
1112 retry++;
1113 if (retry < max_retry)
1114 hw_dbg(hw, "I2C byte write error - Retrying.\n");
1115 else
1116 hw_dbg(hw, "I2C byte write error.\n");
1117 } while (retry < max_retry);
1118
75f19c3c
ET		 1119 ixgbe_release_swfw_sync(hw, swfw_mask);
1120
1121write_byte_out:
11afc1b1
PW		 1122 return status;
1123}
1124
1125/**
1126 * ixgbe_i2c_start - Sets I2C start condition
1127 * @hw: pointer to hardware structure
1128 *
1129 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1130 **/
1131static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1132{
1133 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1134
1135 /* Start condition must begin with data and clock high */
1136 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1137 ixgbe_raise_i2c_clk(hw, &i2cctl);
1138
1139 /* Setup time for start condition (4.7us) */
1140 udelay(IXGBE_I2C_T_SU_STA);
1141
1142 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1143
1144 /* Hold time for start condition (4us) */
1145 udelay(IXGBE_I2C_T_HD_STA);
1146
1147 ixgbe_lower_i2c_clk(hw, &i2cctl);
1148
1149 /* Minimum low period of clock is 4.7 us */
1150 udelay(IXGBE_I2C_T_LOW);
1151
1152}
1153
1154/**
1155 * ixgbe_i2c_stop - Sets I2C stop condition
1156 * @hw: pointer to hardware structure
1157 *
1158 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1159 **/
1160static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1161{
1162 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1163
1164 /* Stop condition must begin with data low and clock high */
1165 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1166 ixgbe_raise_i2c_clk(hw, &i2cctl);
1167
1168 /* Setup time for stop condition (4us) */
1169 udelay(IXGBE_I2C_T_SU_STO);
1170
1171 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1172
1173 /* bus free time between stop and start (4.7us)*/
1174 udelay(IXGBE_I2C_T_BUF);
1175}
1176
1177/**
1178 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1179 * @hw: pointer to hardware structure
1180 * @data: data byte to clock in
1181 *
1182 * Clocks in one byte data via I2C data/clock
1183 **/
1184static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1185{
1186 s32 status = 0;
1187 s32 i;
1188 bool bit = 0;
1189
1190 for (i = 7; i >= 0; i--) {
1191 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1192 *data |= bit << i;
1193
1194 if (status != 0)
1195 break;
1196 }
1197
1198 return status;
1199}
1200
1201/**
1202 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1203 * @hw: pointer to hardware structure
1204 * @data: data byte clocked out
1205 *
1206 * Clocks out one byte data via I2C data/clock
1207 **/
1208static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1209{
1210 s32 status = 0;
1211 s32 i;
1212 u32 i2cctl;
1213 bool bit = 0;
1214
1215 for (i = 7; i >= 0; i--) {
1216 bit = (data >> i) & 0x1;
1217 status = ixgbe_clock_out_i2c_bit(hw, bit);
1218
1219 if (status != 0)
1220 break;
1221 }
1222
1223 /* Release SDA line (set high) */
1224 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1225 i2cctl |= IXGBE_I2C_DATA_OUT;
1226 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1227
1228 return status;
1229}
1230
1231/**
1232 * ixgbe_get_i2c_ack - Polls for I2C ACK
1233 * @hw: pointer to hardware structure
1234 *
1235 * Clocks in/out one bit via I2C data/clock
1236 **/
1237static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1238{
1239 s32 status;
1240 u32 i = 0;
1241 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1242 u32 timeout = 10;
1243 bool ack = 1;
1244
1245 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1246
1247 if (status != 0)
1248 goto out;
1249
1250 /* Minimum high period of clock is 4us */
1251 udelay(IXGBE_I2C_T_HIGH);
1252
1253 /* Poll for ACK. Note that ACK in I2C spec is
1254 * transition from 1 to 0 */
1255 for (i = 0; i < timeout; i++) {
1256 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1257 ack = ixgbe_get_i2c_data(&i2cctl);
1258
1259 udelay(1);
1260 if (ack == 0)
1261 break;
1262 }
1263
1264 if (ack == 1) {
1265 hw_dbg(hw, "I2C ack was not received.\n");
1266 status = IXGBE_ERR_I2C;
1267 }
1268
1269 ixgbe_lower_i2c_clk(hw, &i2cctl);
1270
1271 /* Minimum low period of clock is 4.7 us */
1272 udelay(IXGBE_I2C_T_LOW);
1273
1274out:
1275 return status;
1276}
1277
1278/**
1279 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1280 * @hw: pointer to hardware structure
1281 * @data: read data value
1282 *
1283 * Clocks in one bit via I2C data/clock
1284 **/
1285static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1286{
1287 s32 status;
1288 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1289
1290 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1291
1292 /* Minimum high period of clock is 4us */
1293 udelay(IXGBE_I2C_T_HIGH);
1294
1295 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1296 *data = ixgbe_get_i2c_data(&i2cctl);
1297
1298 ixgbe_lower_i2c_clk(hw, &i2cctl);
1299
1300 /* Minimum low period of clock is 4.7 us */
1301 udelay(IXGBE_I2C_T_LOW);
1302
1303 return status;
1304}
1305
1306/**
1307 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1308 * @hw: pointer to hardware structure
1309 * @data: data value to write
1310 *
1311 * Clocks out one bit via I2C data/clock
1312 **/
1313static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1314{
1315 s32 status;
1316 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1317
1318 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1319 if (status == 0) {
1320 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1321
1322 /* Minimum high period of clock is 4us */
1323 udelay(IXGBE_I2C_T_HIGH);
1324
1325 ixgbe_lower_i2c_clk(hw, &i2cctl);
1326
1327 /* Minimum low period of clock is 4.7 us.
1328 * This also takes care of the data hold time.
1329 */
1330 udelay(IXGBE_I2C_T_LOW);
1331 } else {
1332 status = IXGBE_ERR_I2C;
1333 hw_dbg(hw, "I2C data was not set to %X\n", data);
1334 }
1335
1336 return status;
1337}
1338/**
1339 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1340 * @hw: pointer to hardware structure
1341 * @i2cctl: Current value of I2CCTL register
1342 *
1343 * Raises the I2C clock line '0'->'1'
1344 **/
1345static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1346{
1347 s32 status = 0;
1348
1349 *i2cctl |= IXGBE_I2C_CLK_OUT;
1350
1351 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1352
1353 /* SCL rise time (1000ns) */
1354 udelay(IXGBE_I2C_T_RISE);
1355
1356 return status;
1357}
1358
1359/**
1360 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1361 * @hw: pointer to hardware structure
1362 * @i2cctl: Current value of I2CCTL register
1363 *
1364 * Lowers the I2C clock line '1'->'0'
1365 **/
1366static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1367{
1368
1369 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1370
1371 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1372
1373 /* SCL fall time (300ns) */
1374 udelay(IXGBE_I2C_T_FALL);
1375}
1376
1377/**
1378 * ixgbe_set_i2c_data - Sets the I2C data bit
1379 * @hw: pointer to hardware structure
1380 * @i2cctl: Current value of I2CCTL register
1381 * @data: I2C data value (0 or 1) to set
1382 *
1383 * Sets the I2C data bit
1384 **/
1385static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1386{
1387 s32 status = 0;
1388
1389 if (data)
1390 *i2cctl |= IXGBE_I2C_DATA_OUT;
1391 else
1392 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1393
1394 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1395
1396 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1397 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1398
1399 /* Verify data was set correctly */
1400 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1401 if (data != ixgbe_get_i2c_data(i2cctl)) {
1402 status = IXGBE_ERR_I2C;
1403 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1404 }
1405
1406 return status;
1407}
1408
1409/**
1410 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1411 * @hw: pointer to hardware structure
1412 * @i2cctl: Current value of I2CCTL register
1413 *
1414 * Returns the I2C data bit value
1415 **/
1416static bool ixgbe_get_i2c_data(u32 *i2cctl)
1417{
1418 bool data;
1419
1420 if (*i2cctl & IXGBE_I2C_DATA_IN)
1421 data = 1;
1422 else
1423 data = 0;
1424
1425 return data;
1426}
1427
1428/**
1429 * ixgbe_i2c_bus_clear - Clears the I2C bus
1430 * @hw: pointer to hardware structure
1431 *
1432 * Clears the I2C bus by sending nine clock pulses.
1433 * Used when data line is stuck low.
1434 **/
1435static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1436{
1437 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1438 u32 i;
1439
75f19c3c
ET		 1440 ixgbe_i2c_start(hw);
1441
11afc1b1
PW		 1442 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1443
1444 for (i = 0; i < 9; i++) {
1445 ixgbe_raise_i2c_clk(hw, &i2cctl);
1446
1447 /* Min high period of clock is 4us */
1448 udelay(IXGBE_I2C_T_HIGH);
1449
1450 ixgbe_lower_i2c_clk(hw, &i2cctl);
1451
1452 /* Min low period of clock is 4.7us*/
1453 udelay(IXGBE_I2C_T_LOW);
1454 }
1455
75f19c3c
ET		 1456 ixgbe_i2c_start(hw);
1457
11afc1b1
PW		 1458 /* Put the i2c bus back to default state */
1459 ixgbe_i2c_stop(hw);
1460}
1461
0befdb3e
JB		 1462/**
1463 * ixgbe_check_phy_link_tnx - Determine link and speed status
1464 * @hw: pointer to hardware structure
1465 *
1466 * Reads the VS1 register to determine if link is up and the current speed for
1467 * the PHY.
1468 **/
1469s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1470 bool *link_up)
1471{
1472 s32 status = 0;
1473 u32 time_out;
1474 u32 max_time_out = 10;
1475 u16 phy_link = 0;
1476 u16 phy_speed = 0;
1477 u16 phy_data = 0;
1478
1479 /* Initialize speed and link to default case */
1480 *link_up = false;
1481 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1482
1483 /*
1484 * Check current speed and link status of the PHY register.
1485 * This is a vendor specific register and may have to
1486 * be changed for other copper PHYs.
1487 */
1488 for (time_out = 0; time_out < max_time_out; time_out++) {
1489 udelay(10);
1490 status = hw->phy.ops.read_reg(hw,
1491 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
6b73e10d 1492 MDIO_MMD_VEND1,
0befdb3e
JB		 1493 &phy_data);
1494 phy_link = phy_data &
1495 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1496 phy_speed = phy_data &
1497 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1498 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1499 *link_up = true;
1500 if (phy_speed ==
1501 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1502 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1503 break;
1504 }
1505 }
1506
1507 return status;
1508}
1509
1510/**
1511 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1512 * @hw: pointer to hardware structure
1513 * @firmware_version: pointer to the PHY Firmware Version
1514 **/
1515s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1516 u16 *firmware_version)
1517{
1518 s32 status = 0;
1519
6b73e10d 1520 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1,
0befdb3e
JB		 1521 firmware_version);
1522
1523 return status;
1524}
1525
fe15e8e1
DS		 1526/**
1527 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1528 * @hw: pointer to hardware structure
1529 * @firmware_version: pointer to the PHY Firmware Version
1530**/
1531s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1532 u16 *firmware_version)
1533{
1534 s32 status = 0;
1535
1536 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, MDIO_MMD_VEND1,
1537 firmware_version);
1538
1539 return status;
1540}
1541
119fc60a
MC		 1542/**
1543 * ixgbe_tn_check_overtemp - Checks if an overtemp occured.
1544 * @hw: pointer to hardware structure
1545 *
1546 * Checks if the LASI temp alarm status was triggered due to overtemp
1547 **/
1548s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1549{
1550 s32 status = 0;
1551 u16 phy_data = 0;
1552
1553 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1554 goto out;
1555
1556 /* Check that the LASI temp alarm status was triggered */
1557 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1558 MDIO_MMD_PMAPMD, &phy_data);
1559
1560 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1561 goto out;
1562
1563 status = IXGBE_ERR_OVERTEMP;
1564out:
1565 return status;
1566}
Linux kernel - Deliverables
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