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ixgbe: Add ethtool offline test support
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_phy.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe_common.h"
33#include "ixgbe_phy.h"
34
11afc1b1
PW		 35static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
42static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
43static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45static bool ixgbe_get_i2c_data(u32 *i2cctl);
46static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
9a799d71
AK		 47static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
9a799d71
AK		 49
50/**
c44ade9e 51 * ixgbe_identify_phy_generic - Get physical layer module
9a799d71
AK		 52 * @hw: pointer to hardware structure
53 *
54 * Determines the physical layer module found on the current adapter.
55 **/
c44ade9e 56s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
9a799d71
AK		 57{
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
59 u32 phy_addr;
60
c44ade9e
JB		 61 if (hw->phy.type == ixgbe_phy_unknown) {
62 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
6b73e10d 63 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
c44ade9e
JB		 64 ixgbe_get_phy_id(hw);
65 hw->phy.type =
66 ixgbe_get_phy_type_from_id(hw->phy.id);
67 status = 0;
68 break;
69 }
9a799d71 70 }
c44ade9e
JB		 71 } else {
72 status = 0;
9a799d71 73 }
c44ade9e 74
9a799d71
AK		 75 return status;
76}
77
9a799d71
AK		 78/**
79 * ixgbe_get_phy_id - Get the phy type
80 * @hw: pointer to hardware structure
81 *
82 **/
83static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
84{
85 u32 status;
86 u16 phy_id_high = 0;
87 u16 phy_id_low = 0;
88
6b73e10d 89 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
c44ade9e 90 &phy_id_high);
9a799d71
AK		 91
92 if (status == 0) {
93 hw->phy.id = (u32)(phy_id_high << 16);
6b73e10d 94 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
c44ade9e 95 &phy_id_low);
9a799d71
AK		 96 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
97 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
98 }
9a799d71
AK		 99 return status;
100}
101
102/**
103 * ixgbe_get_phy_type_from_id - Get the phy type
104 * @hw: pointer to hardware structure
105 *
106 **/
107static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
108{
109 enum ixgbe_phy_type phy_type;
110
111 switch (phy_id) {
0befdb3e
JB		 112 case TN1010_PHY_ID:
113 phy_type = ixgbe_phy_tn;
114 break;
9a799d71
AK		 115 case QT2022_PHY_ID:
116 phy_type = ixgbe_phy_qt;
117 break;
c4900be0
DS		 118 case ATH_PHY_ID:
119 phy_type = ixgbe_phy_nl;
120 break;
9a799d71
AK		 121 default:
122 phy_type = ixgbe_phy_unknown;
123 break;
124 }
125
126 return phy_type;
127}
128
129/**
c44ade9e 130 * ixgbe_reset_phy_generic - Performs a PHY reset
9a799d71
AK		 131 * @hw: pointer to hardware structure
132 **/
c44ade9e 133s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
9a799d71
AK		 134{
135 /*
136 * Perform soft PHY reset to the PHY_XS.
137 * This will cause a soft reset to the PHY
138 */
6b73e10d
BH		 139 return hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
140 MDIO_CTRL1_RESET);
9a799d71
AK		 141}
142
143/**
c44ade9e 144 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
9a799d71
AK		 145 * @hw: pointer to hardware structure
146 * @reg_addr: 32 bit address of PHY register to read
147 * @phy_data: Pointer to read data from PHY register
148 **/
c44ade9e
JB		 149s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
150 u32 device_type, u16 *phy_data)
9a799d71
AK		 151{
152 u32 command;
153 u32 i;
9a799d71
AK		 154 u32 data;
155 s32 status = 0;
156 u16 gssr;
157
158 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
159 gssr = IXGBE_GSSR_PHY1_SM;
160 else
161 gssr = IXGBE_GSSR_PHY0_SM;
162
163 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
164 status = IXGBE_ERR_SWFW_SYNC;
165
166 if (status == 0) {
167 /* Setup and write the address cycle command */
168 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 169 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d 170 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 171 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 172
173 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
174
175 /*
176 * Check every 10 usec to see if the address cycle completed.
177 * The MDI Command bit will clear when the operation is
178 * complete
179 */
c44ade9e 180 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 181 udelay(10);
182
183 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
184
185 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
186 break;
187 }
188
189 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
190 hw_dbg(hw, "PHY address command did not complete.\n");
191 status = IXGBE_ERR_PHY;
192 }
193
194 if (status == 0) {
195 /*
196 * Address cycle complete, setup and write the read
197 * command
198 */
199 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 200 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d
BH		 201 (hw->phy.mdio.prtad <<
202 IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 203 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 204
205 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
206
207 /*
208 * Check every 10 usec to see if the address cycle
209 * completed. The MDI Command bit will clear when the
210 * operation is complete
211 */
c44ade9e 212 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 213 udelay(10);
214
215 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
216
217 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
218 break;
219 }
220
221 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
c44ade9e 222 hw_dbg(hw, "PHY read command didn't complete\n");
9a799d71
AK		 223 status = IXGBE_ERR_PHY;
224 } else {
225 /*
226 * Read operation is complete. Get the data
227 * from MSRWD
228 */
229 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
230 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
231 *phy_data = (u16)(data);
232 }
233 }
234
235 ixgbe_release_swfw_sync(hw, gssr);
236 }
c44ade9e 237
9a799d71
AK		 238 return status;
239}
240
241/**
c44ade9e 242 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
9a799d71
AK		 243 * @hw: pointer to hardware structure
244 * @reg_addr: 32 bit PHY register to write
245 * @device_type: 5 bit device type
246 * @phy_data: Data to write to the PHY register
247 **/
c44ade9e
JB		 248s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
249 u32 device_type, u16 phy_data)
9a799d71
AK		 250{
251 u32 command;
252 u32 i;
9a799d71
AK		 253 s32 status = 0;
254 u16 gssr;
255
256 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
257 gssr = IXGBE_GSSR_PHY1_SM;
258 else
259 gssr = IXGBE_GSSR_PHY0_SM;
260
261 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
262 status = IXGBE_ERR_SWFW_SYNC;
263
264 if (status == 0) {
265 /* Put the data in the MDI single read and write data register*/
266 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
267
268 /* Setup and write the address cycle command */
269 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 270 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d 271 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 272 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 273
274 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
275
276 /*
277 * Check every 10 usec to see if the address cycle completed.
278 * The MDI Command bit will clear when the operation is
279 * complete
280 */
c44ade9e 281 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 282 udelay(10);
283
284 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
285
c44ade9e 286 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71 287 break;
9a799d71
AK		 288 }
289
c44ade9e
JB		 290 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
291 hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71 292 status = IXGBE_ERR_PHY;
c44ade9e 293 }
9a799d71
AK		 294
295 if (status == 0) {
296 /*
297 * Address cycle complete, setup and write the write
298 * command
299 */
300 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 301 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d
BH		 302 (hw->phy.mdio.prtad <<
303 IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 304 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 305
306 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
307
308 /*
309 * Check every 10 usec to see if the address cycle
310 * completed. The MDI Command bit will clear when the
311 * operation is complete
312 */
c44ade9e 313 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 314 udelay(10);
315
316 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
317
c44ade9e 318 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71 319 break;
9a799d71
AK		 320 }
321
c44ade9e
JB		 322 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
323 hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71 324 status = IXGBE_ERR_PHY;
c44ade9e 325 }
9a799d71
AK		 326 }
327
328 ixgbe_release_swfw_sync(hw, gssr);
329 }
330
331 return status;
332}
333
334/**
c44ade9e 335 * ixgbe_setup_phy_link_generic - Set and restart autoneg
9a799d71
AK		 336 * @hw: pointer to hardware structure
337 *
338 * Restart autonegotiation and PHY and waits for completion.
339 **/
c44ade9e 340s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
9a799d71
AK		 341{
342 s32 status = IXGBE_NOT_IMPLEMENTED;
343 u32 time_out;
344 u32 max_time_out = 10;
6b73e10d 345 u16 autoneg_reg;
9a799d71
AK		 346
347 /*
348 * Set advertisement settings in PHY based on autoneg_advertised
349 * settings. If autoneg_advertised = 0, then advertise default values
c44ade9e 350 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can
9a799d71
AK		 351 * for a 1G.
352 */
6b73e10d 353 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
9a799d71
AK		 354
355 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
6b73e10d 356 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
9a799d71 357 else
6b73e10d 358 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
9a799d71 359
6b73e10d 360 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
9a799d71
AK		 361
362 /* Restart PHY autonegotiation and wait for completion */
6b73e10d 363 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg);
9a799d71 364
6b73e10d 365 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
9a799d71 366
6b73e10d 367 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg);
9a799d71
AK		 368
369 /* Wait for autonegotiation to finish */
370 for (time_out = 0; time_out < max_time_out; time_out++) {
371 udelay(10);
372 /* Restart PHY autonegotiation and wait for completion */
6b73e10d 373 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
c44ade9e 374 &autoneg_reg);
9a799d71 375
6b73e10d
BH		 376 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
377 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
9a799d71
AK		 378 status = 0;
379 break;
380 }
381 }
382
383 if (time_out == max_time_out)
384 status = IXGBE_ERR_LINK_SETUP;
385
386 return status;
387}
388
389/**
c44ade9e 390 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
9a799d71
AK		 391 * @hw: pointer to hardware structure
392 * @speed: new link speed
393 * @autoneg: true if autonegotiation enabled
394 **/
c44ade9e
JB		 395s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
396 ixgbe_link_speed speed,
397 bool autoneg,
398 bool autoneg_wait_to_complete)
9a799d71 399{
c44ade9e 400
9a799d71
AK		 401 /*
402 * Clear autoneg_advertised and set new values based on input link
403 * speed.
404 */
405 hw->phy.autoneg_advertised = 0;
406
407 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
408 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
c44ade9e 409
9a799d71
AK		 410 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
411 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
412
413 /* Setup link based on the new speed settings */
c44ade9e 414 hw->phy.ops.setup_link(hw);
9a799d71
AK		 415
416 return 0;
417}
c44ade9e 418
c4900be0
DS		 419/**
420 * ixgbe_reset_phy_nl - Performs a PHY reset
421 * @hw: pointer to hardware structure
422 **/
423s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
424{
425 u16 phy_offset, control, eword, edata, block_crc;
426 bool end_data = false;
427 u16 list_offset, data_offset;
428 u16 phy_data = 0;
429 s32 ret_val = 0;
430 u32 i;
431
6b73e10d 432 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
c4900be0
DS		 433
434 /* reset the PHY and poll for completion */
6b73e10d
BH		 435 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
436 (phy_data | MDIO_CTRL1_RESET));
c4900be0
DS		 437
438 for (i = 0; i < 100; i++) {
6b73e10d
BH		 439 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
440 &phy_data);
441 if ((phy_data & MDIO_CTRL1_RESET) == 0)
c4900be0
DS		 442 break;
443 msleep(10);
444 }
445
6b73e10d 446 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
c4900be0
DS		 447 hw_dbg(hw, "PHY reset did not complete.\n");
448 ret_val = IXGBE_ERR_PHY;
449 goto out;
450 }
451
452 /* Get init offsets */
453 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
454 &data_offset);
455 if (ret_val != 0)
456 goto out;
457
458 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
459 data_offset++;
460 while (!end_data) {
461 /*
462 * Read control word from PHY init contents offset
463 */
464 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
465 control = (eword & IXGBE_CONTROL_MASK_NL) >>
466 IXGBE_CONTROL_SHIFT_NL;
467 edata = eword & IXGBE_DATA_MASK_NL;
468 switch (control) {
469 case IXGBE_DELAY_NL:
470 data_offset++;
471 hw_dbg(hw, "DELAY: %d MS\n", edata);
472 msleep(edata);
473 break;
474 case IXGBE_DATA_NL:
475 hw_dbg(hw, "DATA: \n");
476 data_offset++;
477 hw->eeprom.ops.read(hw, data_offset++,
478 &phy_offset);
479 for (i = 0; i < edata; i++) {
480 hw->eeprom.ops.read(hw, data_offset, &eword);
481 hw->phy.ops.write_reg(hw, phy_offset,
6b73e10d 482 MDIO_MMD_PMAPMD, eword);
c4900be0
DS		 483 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
484 phy_offset);
485 data_offset++;
486 phy_offset++;
487 }
488 break;
489 case IXGBE_CONTROL_NL:
490 data_offset++;
491 hw_dbg(hw, "CONTROL: \n");
492 if (edata == IXGBE_CONTROL_EOL_NL) {
493 hw_dbg(hw, "EOL\n");
494 end_data = true;
495 } else if (edata == IXGBE_CONTROL_SOL_NL) {
496 hw_dbg(hw, "SOL\n");
497 } else {
498 hw_dbg(hw, "Bad control value\n");
499 ret_val = IXGBE_ERR_PHY;
500 goto out;
501 }
502 break;
503 default:
504 hw_dbg(hw, "Bad control type\n");
505 ret_val = IXGBE_ERR_PHY;
506 goto out;
507 }
508 }
509
510out:
511 return ret_val;
512}
513
514/**
515 * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns
516 * the PHY type.
517 * @hw: pointer to hardware structure
518 *
519 * Searches for and indentifies the SFP module. Assings appropriate PHY type.
520 **/
521s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
522{
523 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
524 u32 vendor_oui = 0;
553b4497 525 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
c4900be0
DS		 526 u8 identifier = 0;
527 u8 comp_codes_1g = 0;
528 u8 comp_codes_10g = 0;
11afc1b1 529 u8 oui_bytes[3] = {0, 0, 0};
537d58a0 530 u8 cable_tech = 0;
11afc1b1 531 u16 enforce_sfp = 0;
c4900be0 532
8ca783ab
DS		 533 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
534 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
535 status = IXGBE_ERR_SFP_NOT_PRESENT;
536 goto out;
537 }
538
c4900be0
DS		 539 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
540 &identifier);
541
8ca783ab
DS		 542 if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) {
543 status = IXGBE_ERR_SFP_NOT_PRESENT;
c4900be0 544 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
8ca783ab
DS		 545 if (hw->phy.type != ixgbe_phy_nl) {
546 hw->phy.id = 0;
547 hw->phy.type = ixgbe_phy_unknown;
548 }
c4900be0
DS		 549 goto out;
550 }
551
552 if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
553 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
554 &comp_codes_1g);
555 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
556 &comp_codes_10g);
537d58a0
PWJ		 557 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY,
558 &cable_tech);
c4900be0
DS		 559
560 /* ID Module
561 * =========
11afc1b1
PW		 562 * 0 SFP_DA_CU
563 * 1 SFP_SR
564 * 2 SFP_LR
565 * 3 SFP_DA_CORE0 - 82599-specific
566 * 4 SFP_DA_CORE1 - 82599-specific
567 * 5 SFP_SR/LR_CORE0 - 82599-specific
568 * 6 SFP_SR/LR_CORE1 - 82599-specific
c4900be0 569 */
11afc1b1 570 if (hw->mac.type == ixgbe_mac_82598EB) {
537d58a0 571 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
11afc1b1
PW		 572 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
573 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
574 hw->phy.sfp_type = ixgbe_sfp_type_sr;
575 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
576 hw->phy.sfp_type = ixgbe_sfp_type_lr;
577 else
578 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
579 } else if (hw->mac.type == ixgbe_mac_82599EB) {
537d58a0 580 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
11afc1b1
PW		 581 if (hw->bus.lan_id == 0)
582 hw->phy.sfp_type =
583 ixgbe_sfp_type_da_cu_core0;
584 else
585 hw->phy.sfp_type =
586 ixgbe_sfp_type_da_cu_core1;
587 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
588 if (hw->bus.lan_id == 0)
589 hw->phy.sfp_type =
590 ixgbe_sfp_type_srlr_core0;
591 else
592 hw->phy.sfp_type =
593 ixgbe_sfp_type_srlr_core1;
594 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
595 if (hw->bus.lan_id == 0)
596 hw->phy.sfp_type =
597 ixgbe_sfp_type_srlr_core0;
598 else
599 hw->phy.sfp_type =
600 ixgbe_sfp_type_srlr_core1;
601 else
602 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
603 }
c4900be0 604
553b4497
PW		 605 if (hw->phy.sfp_type != stored_sfp_type)
606 hw->phy.sfp_setup_needed = true;
607
608 /* Determine if the SFP+ PHY is dual speed or not. */
609 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
610 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
611 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
612 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
613 hw->phy.multispeed_fiber = true;
614
c4900be0 615 /* Determine PHY vendor */
04193058 616 if (hw->phy.type != ixgbe_phy_nl) {
c4900be0
DS		 617 hw->phy.id = identifier;
618 hw->phy.ops.read_i2c_eeprom(hw,
619 IXGBE_SFF_VENDOR_OUI_BYTE0,
620 &oui_bytes[0]);
621 hw->phy.ops.read_i2c_eeprom(hw,
622 IXGBE_SFF_VENDOR_OUI_BYTE1,
623 &oui_bytes[1]);
624 hw->phy.ops.read_i2c_eeprom(hw,
625 IXGBE_SFF_VENDOR_OUI_BYTE2,
626 &oui_bytes[2]);
627
628 vendor_oui =
629 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
630 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
631 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
632
633 switch (vendor_oui) {
634 case IXGBE_SFF_VENDOR_OUI_TYCO:
537d58a0 635 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
c4900be0
DS		 636 hw->phy.type = ixgbe_phy_tw_tyco;
637 break;
638 case IXGBE_SFF_VENDOR_OUI_FTL:
639 hw->phy.type = ixgbe_phy_sfp_ftl;
640 break;
641 case IXGBE_SFF_VENDOR_OUI_AVAGO:
642 hw->phy.type = ixgbe_phy_sfp_avago;
643 break;
11afc1b1
PW		 644 case IXGBE_SFF_VENDOR_OUI_INTEL:
645 hw->phy.type = ixgbe_phy_sfp_intel;
646 break;
c4900be0 647 default:
537d58a0 648 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
c4900be0
DS		 649 hw->phy.type = ixgbe_phy_tw_unknown;
650 else
651 hw->phy.type = ixgbe_phy_sfp_unknown;
652 break;
653 }
654 }
fa466e91 655
537d58a0
PWJ		 656 /* All passive DA cables are supported */
657 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
fa466e91
WJP		 658 status = 0;
659 goto out;
660 }
661
662 /* 1G SFP modules are not supported */
663 if (comp_codes_10g == 0) {
664 hw->phy.type = ixgbe_phy_sfp_unsupported;
665 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
666 goto out;
667 }
668
669 /* Anything else 82598-based is supported */
670 if (hw->mac.type == ixgbe_mac_82598EB) {
11afc1b1
PW		 671 status = 0;
672 goto out;
673 }
674
04193058
PWJ		 675 /* This is guaranteed to be 82599, no need to check for NULL */
676 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
677 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
11afc1b1
PW		 678 /* Make sure we're a supported PHY type */
679 if (hw->phy.type == ixgbe_phy_sfp_intel) {
680 status = 0;
681 } else {
682 hw_dbg(hw, "SFP+ module not supported\n");
fa466e91 683 hw->phy.type = ixgbe_phy_sfp_unsupported;
11afc1b1
PW		 684 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
685 }
686 } else {
687 status = 0;
688 }
c4900be0
DS		 689 }
690
691out:
692 return status;
693}
694
695/**
696 * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see
697 * if it supports a given SFP+ module type, if so it returns the offsets to the
698 * phy init sequence block.
699 * @hw: pointer to hardware structure
700 * @list_offset: offset to the SFP ID list
701 * @data_offset: offset to the SFP data block
702 **/
703s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
704 u16 *list_offset,
705 u16 *data_offset)
706{
707 u16 sfp_id;
708
709 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
710 return IXGBE_ERR_SFP_NOT_SUPPORTED;
711
712 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
713 return IXGBE_ERR_SFP_NOT_PRESENT;
714
715 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
716 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
717 return IXGBE_ERR_SFP_NOT_SUPPORTED;
718
719 /* Read offset to PHY init contents */
720 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
721
722 if ((!*list_offset) || (*list_offset == 0xFFFF))
11afc1b1 723 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
c4900be0
DS		 724
725 /* Shift offset to first ID word */
726 (*list_offset)++;
727
728 /*
729 * Find the matching SFP ID in the EEPROM
730 * and program the init sequence
731 */
732 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
733
734 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
735 if (sfp_id == hw->phy.sfp_type) {
736 (*list_offset)++;
737 hw->eeprom.ops.read(hw, *list_offset, data_offset);
738 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
739 hw_dbg(hw, "SFP+ module not supported\n");
740 return IXGBE_ERR_SFP_NOT_SUPPORTED;
741 } else {
742 break;
743 }
744 } else {
745 (*list_offset) += 2;
746 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
747 return IXGBE_ERR_PHY;
748 }
749 }
750
751 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
752 hw_dbg(hw, "No matching SFP+ module found\n");
753 return IXGBE_ERR_SFP_NOT_SUPPORTED;
754 }
755
756 return 0;
757}
758
11afc1b1
PW		 759/**
760 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
761 * @hw: pointer to hardware structure
762 * @byte_offset: EEPROM byte offset to read
763 * @eeprom_data: value read
764 *
765 * Performs byte read operation to SFP module's EEPROM over I2C interface.
766 **/
767s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
768 u8 *eeprom_data)
769{
770 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
771 IXGBE_I2C_EEPROM_DEV_ADDR,
772 eeprom_data);
773}
774
775/**
776 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
777 * @hw: pointer to hardware structure
778 * @byte_offset: EEPROM byte offset to write
779 * @eeprom_data: value to write
780 *
781 * Performs byte write operation to SFP module's EEPROM over I2C interface.
782 **/
783s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
784 u8 eeprom_data)
785{
786 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
787 IXGBE_I2C_EEPROM_DEV_ADDR,
788 eeprom_data);
789}
790
791/**
792 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
793 * @hw: pointer to hardware structure
794 * @byte_offset: byte offset to read
795 * @data: value read
796 *
797 * Performs byte read operation to SFP module's EEPROM over I2C interface at
798 * a specified deivce address.
799 **/
800s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
801 u8 dev_addr, u8 *data)
802{
803 s32 status = 0;
804 u32 max_retry = 1;
805 u32 retry = 0;
806 bool nack = 1;
807
808 do {
809 ixgbe_i2c_start(hw);
810
811 /* Device Address and write indication */
812 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
813 if (status != 0)
814 goto fail;
815
816 status = ixgbe_get_i2c_ack(hw);
817 if (status != 0)
818 goto fail;
819
820 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
821 if (status != 0)
822 goto fail;
823
824 status = ixgbe_get_i2c_ack(hw);
825 if (status != 0)
826 goto fail;
827
828 ixgbe_i2c_start(hw);
829
830 /* Device Address and read indication */
831 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
832 if (status != 0)
833 goto fail;
834
835 status = ixgbe_get_i2c_ack(hw);
836 if (status != 0)
837 goto fail;
838
839 status = ixgbe_clock_in_i2c_byte(hw, data);
840 if (status != 0)
841 goto fail;
842
843 status = ixgbe_clock_out_i2c_bit(hw, nack);
844 if (status != 0)
845 goto fail;
846
847 ixgbe_i2c_stop(hw);
848 break;
849
850fail:
851 ixgbe_i2c_bus_clear(hw);
852 retry++;
853 if (retry < max_retry)
854 hw_dbg(hw, "I2C byte read error - Retrying.\n");
855 else
856 hw_dbg(hw, "I2C byte read error.\n");
857
858 } while (retry < max_retry);
859
860 return status;
861}
862
863/**
864 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
865 * @hw: pointer to hardware structure
866 * @byte_offset: byte offset to write
867 * @data: value to write
868 *
869 * Performs byte write operation to SFP module's EEPROM over I2C interface at
870 * a specified device address.
871 **/
872s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
873 u8 dev_addr, u8 data)
874{
875 s32 status = 0;
876 u32 max_retry = 1;
877 u32 retry = 0;
878
879 do {
880 ixgbe_i2c_start(hw);
881
882 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
883 if (status != 0)
884 goto fail;
885
886 status = ixgbe_get_i2c_ack(hw);
887 if (status != 0)
888 goto fail;
889
890 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
891 if (status != 0)
892 goto fail;
893
894 status = ixgbe_get_i2c_ack(hw);
895 if (status != 0)
896 goto fail;
897
898 status = ixgbe_clock_out_i2c_byte(hw, data);
899 if (status != 0)
900 goto fail;
901
902 status = ixgbe_get_i2c_ack(hw);
903 if (status != 0)
904 goto fail;
905
906 ixgbe_i2c_stop(hw);
907 break;
908
909fail:
910 ixgbe_i2c_bus_clear(hw);
911 retry++;
912 if (retry < max_retry)
913 hw_dbg(hw, "I2C byte write error - Retrying.\n");
914 else
915 hw_dbg(hw, "I2C byte write error.\n");
916 } while (retry < max_retry);
917
918 return status;
919}
920
921/**
922 * ixgbe_i2c_start - Sets I2C start condition
923 * @hw: pointer to hardware structure
924 *
925 * Sets I2C start condition (High -> Low on SDA while SCL is High)
926 **/
927static void ixgbe_i2c_start(struct ixgbe_hw *hw)
928{
929 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
930
931 /* Start condition must begin with data and clock high */
932 ixgbe_set_i2c_data(hw, &i2cctl, 1);
933 ixgbe_raise_i2c_clk(hw, &i2cctl);
934
935 /* Setup time for start condition (4.7us) */
936 udelay(IXGBE_I2C_T_SU_STA);
937
938 ixgbe_set_i2c_data(hw, &i2cctl, 0);
939
940 /* Hold time for start condition (4us) */
941 udelay(IXGBE_I2C_T_HD_STA);
942
943 ixgbe_lower_i2c_clk(hw, &i2cctl);
944
945 /* Minimum low period of clock is 4.7 us */
946 udelay(IXGBE_I2C_T_LOW);
947
948}
949
950/**
951 * ixgbe_i2c_stop - Sets I2C stop condition
952 * @hw: pointer to hardware structure
953 *
954 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
955 **/
956static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
957{
958 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
959
960 /* Stop condition must begin with data low and clock high */
961 ixgbe_set_i2c_data(hw, &i2cctl, 0);
962 ixgbe_raise_i2c_clk(hw, &i2cctl);
963
964 /* Setup time for stop condition (4us) */
965 udelay(IXGBE_I2C_T_SU_STO);
966
967 ixgbe_set_i2c_data(hw, &i2cctl, 1);
968
969 /* bus free time between stop and start (4.7us)*/
970 udelay(IXGBE_I2C_T_BUF);
971}
972
973/**
974 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
975 * @hw: pointer to hardware structure
976 * @data: data byte to clock in
977 *
978 * Clocks in one byte data via I2C data/clock
979 **/
980static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
981{
982 s32 status = 0;
983 s32 i;
984 bool bit = 0;
985
986 for (i = 7; i >= 0; i--) {
987 status = ixgbe_clock_in_i2c_bit(hw, &bit);
988 *data |= bit << i;
989
990 if (status != 0)
991 break;
992 }
993
994 return status;
995}
996
997/**
998 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
999 * @hw: pointer to hardware structure
1000 * @data: data byte clocked out
1001 *
1002 * Clocks out one byte data via I2C data/clock
1003 **/
1004static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1005{
1006 s32 status = 0;
1007 s32 i;
1008 u32 i2cctl;
1009 bool bit = 0;
1010
1011 for (i = 7; i >= 0; i--) {
1012 bit = (data >> i) & 0x1;
1013 status = ixgbe_clock_out_i2c_bit(hw, bit);
1014
1015 if (status != 0)
1016 break;
1017 }
1018
1019 /* Release SDA line (set high) */
1020 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1021 i2cctl |= IXGBE_I2C_DATA_OUT;
1022 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1023
1024 return status;
1025}
1026
1027/**
1028 * ixgbe_get_i2c_ack - Polls for I2C ACK
1029 * @hw: pointer to hardware structure
1030 *
1031 * Clocks in/out one bit via I2C data/clock
1032 **/
1033static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1034{
1035 s32 status;
1036 u32 i = 0;
1037 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1038 u32 timeout = 10;
1039 bool ack = 1;
1040
1041 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1042
1043 if (status != 0)
1044 goto out;
1045
1046 /* Minimum high period of clock is 4us */
1047 udelay(IXGBE_I2C_T_HIGH);
1048
1049 /* Poll for ACK. Note that ACK in I2C spec is
1050 * transition from 1 to 0 */
1051 for (i = 0; i < timeout; i++) {
1052 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1053 ack = ixgbe_get_i2c_data(&i2cctl);
1054
1055 udelay(1);
1056 if (ack == 0)
1057 break;
1058 }
1059
1060 if (ack == 1) {
1061 hw_dbg(hw, "I2C ack was not received.\n");
1062 status = IXGBE_ERR_I2C;
1063 }
1064
1065 ixgbe_lower_i2c_clk(hw, &i2cctl);
1066
1067 /* Minimum low period of clock is 4.7 us */
1068 udelay(IXGBE_I2C_T_LOW);
1069
1070out:
1071 return status;
1072}
1073
1074/**
1075 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1076 * @hw: pointer to hardware structure
1077 * @data: read data value
1078 *
1079 * Clocks in one bit via I2C data/clock
1080 **/
1081static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1082{
1083 s32 status;
1084 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1085
1086 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1087
1088 /* Minimum high period of clock is 4us */
1089 udelay(IXGBE_I2C_T_HIGH);
1090
1091 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1092 *data = ixgbe_get_i2c_data(&i2cctl);
1093
1094 ixgbe_lower_i2c_clk(hw, &i2cctl);
1095
1096 /* Minimum low period of clock is 4.7 us */
1097 udelay(IXGBE_I2C_T_LOW);
1098
1099 return status;
1100}
1101
1102/**
1103 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1104 * @hw: pointer to hardware structure
1105 * @data: data value to write
1106 *
1107 * Clocks out one bit via I2C data/clock
1108 **/
1109static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1110{
1111 s32 status;
1112 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1113
1114 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1115 if (status == 0) {
1116 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1117
1118 /* Minimum high period of clock is 4us */
1119 udelay(IXGBE_I2C_T_HIGH);
1120
1121 ixgbe_lower_i2c_clk(hw, &i2cctl);
1122
1123 /* Minimum low period of clock is 4.7 us.
1124 * This also takes care of the data hold time.
1125 */
1126 udelay(IXGBE_I2C_T_LOW);
1127 } else {
1128 status = IXGBE_ERR_I2C;
1129 hw_dbg(hw, "I2C data was not set to %X\n", data);
1130 }
1131
1132 return status;
1133}
1134/**
1135 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1136 * @hw: pointer to hardware structure
1137 * @i2cctl: Current value of I2CCTL register
1138 *
1139 * Raises the I2C clock line '0'->'1'
1140 **/
1141static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1142{
1143 s32 status = 0;
1144
1145 *i2cctl |= IXGBE_I2C_CLK_OUT;
1146
1147 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1148
1149 /* SCL rise time (1000ns) */
1150 udelay(IXGBE_I2C_T_RISE);
1151
1152 return status;
1153}
1154
1155/**
1156 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1157 * @hw: pointer to hardware structure
1158 * @i2cctl: Current value of I2CCTL register
1159 *
1160 * Lowers the I2C clock line '1'->'0'
1161 **/
1162static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1163{
1164
1165 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1166
1167 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1168
1169 /* SCL fall time (300ns) */
1170 udelay(IXGBE_I2C_T_FALL);
1171}
1172
1173/**
1174 * ixgbe_set_i2c_data - Sets the I2C data bit
1175 * @hw: pointer to hardware structure
1176 * @i2cctl: Current value of I2CCTL register
1177 * @data: I2C data value (0 or 1) to set
1178 *
1179 * Sets the I2C data bit
1180 **/
1181static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1182{
1183 s32 status = 0;
1184
1185 if (data)
1186 *i2cctl |= IXGBE_I2C_DATA_OUT;
1187 else
1188 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1189
1190 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1191
1192 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1193 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1194
1195 /* Verify data was set correctly */
1196 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1197 if (data != ixgbe_get_i2c_data(i2cctl)) {
1198 status = IXGBE_ERR_I2C;
1199 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1200 }
1201
1202 return status;
1203}
1204
1205/**
1206 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1207 * @hw: pointer to hardware structure
1208 * @i2cctl: Current value of I2CCTL register
1209 *
1210 * Returns the I2C data bit value
1211 **/
1212static bool ixgbe_get_i2c_data(u32 *i2cctl)
1213{
1214 bool data;
1215
1216 if (*i2cctl & IXGBE_I2C_DATA_IN)
1217 data = 1;
1218 else
1219 data = 0;
1220
1221 return data;
1222}
1223
1224/**
1225 * ixgbe_i2c_bus_clear - Clears the I2C bus
1226 * @hw: pointer to hardware structure
1227 *
1228 * Clears the I2C bus by sending nine clock pulses.
1229 * Used when data line is stuck low.
1230 **/
1231static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1232{
1233 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1234 u32 i;
1235
1236 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1237
1238 for (i = 0; i < 9; i++) {
1239 ixgbe_raise_i2c_clk(hw, &i2cctl);
1240
1241 /* Min high period of clock is 4us */
1242 udelay(IXGBE_I2C_T_HIGH);
1243
1244 ixgbe_lower_i2c_clk(hw, &i2cctl);
1245
1246 /* Min low period of clock is 4.7us*/
1247 udelay(IXGBE_I2C_T_LOW);
1248 }
1249
1250 /* Put the i2c bus back to default state */
1251 ixgbe_i2c_stop(hw);
1252}
1253
0befdb3e
JB		 1254/**
1255 * ixgbe_check_phy_link_tnx - Determine link and speed status
1256 * @hw: pointer to hardware structure
1257 *
1258 * Reads the VS1 register to determine if link is up and the current speed for
1259 * the PHY.
1260 **/
1261s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1262 bool *link_up)
1263{
1264 s32 status = 0;
1265 u32 time_out;
1266 u32 max_time_out = 10;
1267 u16 phy_link = 0;
1268 u16 phy_speed = 0;
1269 u16 phy_data = 0;
1270
1271 /* Initialize speed and link to default case */
1272 *link_up = false;
1273 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1274
1275 /*
1276 * Check current speed and link status of the PHY register.
1277 * This is a vendor specific register and may have to
1278 * be changed for other copper PHYs.
1279 */
1280 for (time_out = 0; time_out < max_time_out; time_out++) {
1281 udelay(10);
1282 status = hw->phy.ops.read_reg(hw,
1283 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
6b73e10d 1284 MDIO_MMD_VEND1,
0befdb3e
JB		 1285 &phy_data);
1286 phy_link = phy_data &
1287 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1288 phy_speed = phy_data &
1289 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1290 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1291 *link_up = true;
1292 if (phy_speed ==
1293 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1294 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1295 break;
1296 }
1297 }
1298
1299 return status;
1300}
1301
1302/**
1303 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1304 * @hw: pointer to hardware structure
1305 * @firmware_version: pointer to the PHY Firmware Version
1306 **/
1307s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1308 u16 *firmware_version)
1309{
1310 s32 status = 0;
1311
6b73e10d 1312 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1,
0befdb3e
JB		 1313 firmware_version);
1314
1315 return status;
1316}
1317
Linux kernel - Deliverables
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