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e1000e: implement ethtool set_phys_id
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_phy.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe_common.h"
33#include "ixgbe_phy.h"
34
11afc1b1
PW		 35static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
42static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
43static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45static bool ixgbe_get_i2c_data(u32 *i2cctl);
46static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
9a799d71
AK		 47static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
9a799d71
AK		 49
50/**
c44ade9e 51 * ixgbe_identify_phy_generic - Get physical layer module
9a799d71
AK		 52 * @hw: pointer to hardware structure
53 *
54 * Determines the physical layer module found on the current adapter.
55 **/
c44ade9e 56s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
9a799d71
AK		 57{
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
59 u32 phy_addr;
037c6d0a 60 u16 ext_ability = 0;
9a799d71 61
c44ade9e
JB		 62 if (hw->phy.type == ixgbe_phy_unknown) {
63 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
63d6e1d8 64 hw->phy.mdio.prtad = phy_addr;
6b73e10d 65 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
c44ade9e
JB		 66 ixgbe_get_phy_id(hw);
67 hw->phy.type =
68 ixgbe_get_phy_type_from_id(hw->phy.id);
037c6d0a
ET		 69
70 if (hw->phy.type == ixgbe_phy_unknown) {
71 hw->phy.ops.read_reg(hw,
72 MDIO_PMA_EXTABLE,
73 MDIO_MMD_PMAPMD,
74 &ext_ability);
75 if (ext_ability &
76 (MDIO_PMA_EXTABLE_10GBT |
77 MDIO_PMA_EXTABLE_1000BT))
78 hw->phy.type =
79 ixgbe_phy_cu_unknown;
80 else
81 hw->phy.type =
82 ixgbe_phy_generic;
83 }
84
c44ade9e
JB		 85 status = 0;
86 break;
87 }
9a799d71 88 }
63d6e1d8 89 /* clear value if nothing found */
037c6d0a
ET		 90 if (status != 0)
91 hw->phy.mdio.prtad = 0;
c44ade9e
JB		 92 } else {
93 status = 0;
9a799d71 94 }
c44ade9e 95
9a799d71
AK		 96 return status;
97}
98
9a799d71
AK		 99/**
100 * ixgbe_get_phy_id - Get the phy type
101 * @hw: pointer to hardware structure
102 *
103 **/
104static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
105{
106 u32 status;
107 u16 phy_id_high = 0;
108 u16 phy_id_low = 0;
109
6b73e10d 110 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
c44ade9e 111 &phy_id_high);
9a799d71
AK		 112
113 if (status == 0) {
114 hw->phy.id = (u32)(phy_id_high << 16);
6b73e10d 115 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
c44ade9e 116 &phy_id_low);
9a799d71
AK		 117 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
118 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
119 }
9a799d71
AK		 120 return status;
121}
122
123/**
124 * ixgbe_get_phy_type_from_id - Get the phy type
125 * @hw: pointer to hardware structure
126 *
127 **/
128static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
129{
130 enum ixgbe_phy_type phy_type;
131
132 switch (phy_id) {
0befdb3e
JB		 133 case TN1010_PHY_ID:
134 phy_type = ixgbe_phy_tn;
135 break;
2b264909 136 case X540_PHY_ID:
fe15e8e1
DS		 137 phy_type = ixgbe_phy_aq;
138 break;
9a799d71
AK		 139 case QT2022_PHY_ID:
140 phy_type = ixgbe_phy_qt;
141 break;
c4900be0
DS		 142 case ATH_PHY_ID:
143 phy_type = ixgbe_phy_nl;
144 break;
9a799d71
AK		 145 default:
146 phy_type = ixgbe_phy_unknown;
147 break;
148 }
149
150 return phy_type;
151}
152
153/**
c44ade9e 154 * ixgbe_reset_phy_generic - Performs a PHY reset
9a799d71
AK		 155 * @hw: pointer to hardware structure
156 **/
c44ade9e 157s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
9a799d71 158{
1783575c
ET		 159 u32 i;
160 u16 ctrl = 0;
161 s32 status = 0;
162
163 if (hw->phy.type == ixgbe_phy_unknown)
164 status = ixgbe_identify_phy_generic(hw);
165
166 if (status != 0 || hw->phy.type == ixgbe_phy_none)
167 goto out;
168
119fc60a
MC		 169 /* Don't reset PHY if it's shut down due to overtemp. */
170 if (!hw->phy.reset_if_overtemp &&
171 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
1783575c 172 goto out;
119fc60a 173
9a799d71
AK		 174 /*
175 * Perform soft PHY reset to the PHY_XS.
176 * This will cause a soft reset to the PHY
177 */
1783575c
ET		 178 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
179 MDIO_MMD_PHYXS,
180 MDIO_CTRL1_RESET);
181
182 /*
183 * Poll for reset bit to self-clear indicating reset is complete.
184 * Some PHYs could take up to 3 seconds to complete and need about
185 * 1.7 usec delay after the reset is complete.
186 */
187 for (i = 0; i < 30; i++) {
188 msleep(100);
189 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
190 MDIO_MMD_PHYXS, &ctrl);
191 if (!(ctrl & MDIO_CTRL1_RESET)) {
192 udelay(2);
193 break;
194 }
195 }
196
197 if (ctrl & MDIO_CTRL1_RESET) {
198 status = IXGBE_ERR_RESET_FAILED;
199 hw_dbg(hw, "PHY reset polling failed to complete.\n");
200 }
201
202out:
203 return status;
9a799d71
AK		 204}
205
206/**
c44ade9e 207 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
9a799d71
AK		 208 * @hw: pointer to hardware structure
209 * @reg_addr: 32 bit address of PHY register to read
210 * @phy_data: Pointer to read data from PHY register
211 **/
c44ade9e
JB		 212s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
213 u32 device_type, u16 *phy_data)
9a799d71
AK		 214{
215 u32 command;
216 u32 i;
9a799d71
AK		 217 u32 data;
218 s32 status = 0;
219 u16 gssr;
220
221 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
222 gssr = IXGBE_GSSR_PHY1_SM;
223 else
224 gssr = IXGBE_GSSR_PHY0_SM;
225
5e655105 226 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
9a799d71
AK		 227 status = IXGBE_ERR_SWFW_SYNC;
228
229 if (status == 0) {
230 /* Setup and write the address cycle command */
231 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 232 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d 233 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 234 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 235
236 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
237
238 /*
239 * Check every 10 usec to see if the address cycle completed.
240 * The MDI Command bit will clear when the operation is
241 * complete
242 */
c44ade9e 243 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 244 udelay(10);
245
246 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
247
248 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
249 break;
250 }
251
252 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
253 hw_dbg(hw, "PHY address command did not complete.\n");
254 status = IXGBE_ERR_PHY;
255 }
256
257 if (status == 0) {
258 /*
259 * Address cycle complete, setup and write the read
260 * command
261 */
262 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 263 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d
BH		 264 (hw->phy.mdio.prtad <<
265 IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 266 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 267
268 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
269
270 /*
271 * Check every 10 usec to see if the address cycle
272 * completed. The MDI Command bit will clear when the
273 * operation is complete
274 */
c44ade9e 275 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 276 udelay(10);
277
278 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
279
280 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
281 break;
282 }
283
284 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
c44ade9e 285 hw_dbg(hw, "PHY read command didn't complete\n");
9a799d71
AK		 286 status = IXGBE_ERR_PHY;
287 } else {
288 /*
289 * Read operation is complete. Get the data
290 * from MSRWD
291 */
292 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
293 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
294 *phy_data = (u16)(data);
295 }
296 }
297
5e655105 298 hw->mac.ops.release_swfw_sync(hw, gssr);
9a799d71 299 }
c44ade9e 300
9a799d71
AK		 301 return status;
302}
303
304/**
c44ade9e 305 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
9a799d71
AK		 306 * @hw: pointer to hardware structure
307 * @reg_addr: 32 bit PHY register to write
308 * @device_type: 5 bit device type
309 * @phy_data: Data to write to the PHY register
310 **/
c44ade9e
JB		 311s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
312 u32 device_type, u16 phy_data)
9a799d71
AK		 313{
314 u32 command;
315 u32 i;
9a799d71
AK		 316 s32 status = 0;
317 u16 gssr;
318
319 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
320 gssr = IXGBE_GSSR_PHY1_SM;
321 else
322 gssr = IXGBE_GSSR_PHY0_SM;
323
5e655105 324 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
9a799d71
AK		 325 status = IXGBE_ERR_SWFW_SYNC;
326
327 if (status == 0) {
328 /* Put the data in the MDI single read and write data register*/
329 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
330
331 /* Setup and write the address cycle command */
332 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 333 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d 334 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 335 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 336
337 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
338
339 /*
340 * Check every 10 usec to see if the address cycle completed.
341 * The MDI Command bit will clear when the operation is
342 * complete
343 */
c44ade9e 344 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 345 udelay(10);
346
347 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
348
c44ade9e 349 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71 350 break;
9a799d71
AK		 351 }
352
c44ade9e
JB		 353 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
354 hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71 355 status = IXGBE_ERR_PHY;
c44ade9e 356 }
9a799d71
AK		 357
358 if (status == 0) {
359 /*
360 * Address cycle complete, setup and write the write
361 * command
362 */
363 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 364 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d
BH		 365 (hw->phy.mdio.prtad <<
366 IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 367 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 368
369 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
370
371 /*
372 * Check every 10 usec to see if the address cycle
373 * completed. The MDI Command bit will clear when the
374 * operation is complete
375 */
c44ade9e 376 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 377 udelay(10);
378
379 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
380
c44ade9e 381 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71 382 break;
9a799d71
AK		 383 }
384
c44ade9e
JB		 385 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
386 hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71 387 status = IXGBE_ERR_PHY;
c44ade9e 388 }
9a799d71
AK		 389 }
390
5e655105 391 hw->mac.ops.release_swfw_sync(hw, gssr);
9a799d71
AK		 392 }
393
394 return status;
395}
396
397/**
c44ade9e 398 * ixgbe_setup_phy_link_generic - Set and restart autoneg
9a799d71
AK		 399 * @hw: pointer to hardware structure
400 *
401 * Restart autonegotiation and PHY and waits for completion.
402 **/
c44ade9e 403s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
9a799d71 404{
9dda1736 405 s32 status = 0;
9a799d71
AK		 406 u32 time_out;
407 u32 max_time_out = 10;
9dda1736
ET		 408 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
409 bool autoneg = false;
410 ixgbe_link_speed speed;
9a799d71 411
9dda1736
ET		 412 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
413
414 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
415 /* Set or unset auto-negotiation 10G advertisement */
416 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
417 MDIO_MMD_AN,
418 &autoneg_reg);
9a799d71 419
6b73e10d 420 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
9dda1736
ET		 421 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
422 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
9a799d71 423
9dda1736
ET		 424 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
425 MDIO_MMD_AN,
426 autoneg_reg);
427 }
428
429 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
430 /* Set or unset auto-negotiation 1G advertisement */
431 hw->phy.ops.read_reg(hw,
432 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
433 MDIO_MMD_AN,
434 &autoneg_reg);
435
436 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
437 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
438 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
439
440 hw->phy.ops.write_reg(hw,
441 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
442 MDIO_MMD_AN,
443 autoneg_reg);
444 }
445
446 if (speed & IXGBE_LINK_SPEED_100_FULL) {
447 /* Set or unset auto-negotiation 100M advertisement */
448 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
449 MDIO_MMD_AN,
450 &autoneg_reg);
451
a59e8a1a
ET		 452 autoneg_reg &= ~(ADVERTISE_100FULL |
453 ADVERTISE_100HALF);
9dda1736
ET		 454 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
455 autoneg_reg |= ADVERTISE_100FULL;
456
457 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
458 MDIO_MMD_AN,
459 autoneg_reg);
460 }
9a799d71
AK		 461
462 /* Restart PHY autonegotiation and wait for completion */
9dda1736
ET		 463 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
464 MDIO_MMD_AN, &autoneg_reg);
9a799d71 465
6b73e10d 466 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
9a799d71 467
9dda1736
ET		 468 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
469 MDIO_MMD_AN, autoneg_reg);
9a799d71
AK		 470
471 /* Wait for autonegotiation to finish */
472 for (time_out = 0; time_out < max_time_out; time_out++) {
473 udelay(10);
474 /* Restart PHY autonegotiation and wait for completion */
9dda1736
ET		 475 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
476 MDIO_MMD_AN,
477 &autoneg_reg);
9a799d71 478
6b73e10d
BH		 479 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
480 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
9a799d71
AK		 481 break;
482 }
483 }
484
9dda1736 485 if (time_out == max_time_out) {
9a799d71 486 status = IXGBE_ERR_LINK_SETUP;
9dda1736
ET		 487 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
488 }
9a799d71
AK		 489
490 return status;
491}
492
493/**
c44ade9e 494 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
9a799d71
AK		 495 * @hw: pointer to hardware structure
496 * @speed: new link speed
497 * @autoneg: true if autonegotiation enabled
498 **/
c44ade9e
JB		 499s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
500 ixgbe_link_speed speed,
501 bool autoneg,
502 bool autoneg_wait_to_complete)
9a799d71 503{
c44ade9e 504
9a799d71
AK		 505 /*
506 * Clear autoneg_advertised and set new values based on input link
507 * speed.
508 */
509 hw->phy.autoneg_advertised = 0;
510
511 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
512 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
c44ade9e 513
9a799d71
AK		 514 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
515 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
516
9dda1736
ET		 517 if (speed & IXGBE_LINK_SPEED_100_FULL)
518 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
519
9a799d71 520 /* Setup link based on the new speed settings */
c44ade9e 521 hw->phy.ops.setup_link(hw);
9a799d71
AK		 522
523 return 0;
524}
c44ade9e 525
a391f1d5
DS		 526/**
527 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
528 * @hw: pointer to hardware structure
529 * @speed: pointer to link speed
530 * @autoneg: boolean auto-negotiation value
531 *
532 * Determines the link capabilities by reading the AUTOC register.
533 */
534s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
fe15e8e1
DS		 535 ixgbe_link_speed *speed,
536 bool *autoneg)
a391f1d5
DS		 537{
538 s32 status = IXGBE_ERR_LINK_SETUP;
539 u16 speed_ability;
540
541 *speed = 0;
542 *autoneg = true;
543
544 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
545 &speed_ability);
546
547 if (status == 0) {
548 if (speed_ability & MDIO_SPEED_10G)
549 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
550 if (speed_ability & MDIO_PMA_SPEED_1000)
551 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
552 if (speed_ability & MDIO_PMA_SPEED_100)
553 *speed |= IXGBE_LINK_SPEED_100_FULL;
554 }
555
556 return status;
557}
558
9dda1736
ET		 559/**
560 * ixgbe_check_phy_link_tnx - Determine link and speed status
561 * @hw: pointer to hardware structure
562 *
563 * Reads the VS1 register to determine if link is up and the current speed for
564 * the PHY.
565 **/
566s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
567 bool *link_up)
568{
569 s32 status = 0;
570 u32 time_out;
571 u32 max_time_out = 10;
572 u16 phy_link = 0;
573 u16 phy_speed = 0;
574 u16 phy_data = 0;
575
576 /* Initialize speed and link to default case */
577 *link_up = false;
578 *speed = IXGBE_LINK_SPEED_10GB_FULL;
579
580 /*
581 * Check current speed and link status of the PHY register.
582 * This is a vendor specific register and may have to
583 * be changed for other copper PHYs.
584 */
585 for (time_out = 0; time_out < max_time_out; time_out++) {
586 udelay(10);
587 status = hw->phy.ops.read_reg(hw,
588 MDIO_STAT1,
589 MDIO_MMD_VEND1,
590 &phy_data);
591 phy_link = phy_data &
592 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
593 phy_speed = phy_data &
594 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
595 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
596 *link_up = true;
597 if (phy_speed ==
598 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
599 *speed = IXGBE_LINK_SPEED_1GB_FULL;
600 break;
601 }
602 }
603
604 return status;
605}
606
607/**
608 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
609 * @hw: pointer to hardware structure
610 *
611 * Restart autonegotiation and PHY and waits for completion.
612 **/
613s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
614{
615 s32 status = 0;
616 u32 time_out;
617 u32 max_time_out = 10;
618 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
619 bool autoneg = false;
620 ixgbe_link_speed speed;
621
622 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
623
624 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
625 /* Set or unset auto-negotiation 10G advertisement */
626 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
627 MDIO_MMD_AN,
628 &autoneg_reg);
629
630 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
631 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
632 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
633
634 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
635 MDIO_MMD_AN,
636 autoneg_reg);
637 }
638
639 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
640 /* Set or unset auto-negotiation 1G advertisement */
641 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
642 MDIO_MMD_AN,
643 &autoneg_reg);
644
645 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
646 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
647 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
648
649 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
650 MDIO_MMD_AN,
651 autoneg_reg);
652 }
653
654 if (speed & IXGBE_LINK_SPEED_100_FULL) {
655 /* Set or unset auto-negotiation 100M advertisement */
656 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
657 MDIO_MMD_AN,
658 &autoneg_reg);
659
660 autoneg_reg &= ~ADVERTISE_100FULL;
661 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
662 autoneg_reg |= ADVERTISE_100FULL;
663
664 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
665 MDIO_MMD_AN,
666 autoneg_reg);
667 }
668
669 /* Restart PHY autonegotiation and wait for completion */
670 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
671 MDIO_MMD_AN, &autoneg_reg);
672
673 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
674
675 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
676 MDIO_MMD_AN, autoneg_reg);
677
678 /* Wait for autonegotiation to finish */
679 for (time_out = 0; time_out < max_time_out; time_out++) {
680 udelay(10);
681 /* Restart PHY autonegotiation and wait for completion */
682 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
683 MDIO_MMD_AN,
684 &autoneg_reg);
685
686 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
687 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE)
688 break;
689 }
690
691 if (time_out == max_time_out) {
692 status = IXGBE_ERR_LINK_SETUP;
693 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
694 }
695
696 return status;
697}
698
699/**
700 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
701 * @hw: pointer to hardware structure
702 * @firmware_version: pointer to the PHY Firmware Version
703 **/
704s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
705 u16 *firmware_version)
706{
707 s32 status = 0;
708
709 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
710 MDIO_MMD_VEND1,
711 firmware_version);
712
713 return status;
714}
715
716/**
717 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
718 * @hw: pointer to hardware structure
719 * @firmware_version: pointer to the PHY Firmware Version
720 **/
721s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
722 u16 *firmware_version)
723{
724 s32 status = 0;
725
726 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
727 MDIO_MMD_VEND1,
728 firmware_version);
729
730 return status;
731}
732
c4900be0
DS		 733/**
734 * ixgbe_reset_phy_nl - Performs a PHY reset
735 * @hw: pointer to hardware structure
736 **/
737s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
738{
739 u16 phy_offset, control, eword, edata, block_crc;
740 bool end_data = false;
741 u16 list_offset, data_offset;
742 u16 phy_data = 0;
743 s32 ret_val = 0;
744 u32 i;
745
6b73e10d 746 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
c4900be0
DS		 747
748 /* reset the PHY and poll for completion */
6b73e10d
BH		 749 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
750 (phy_data | MDIO_CTRL1_RESET));
c4900be0
DS		 751
752 for (i = 0; i < 100; i++) {
6b73e10d
BH		 753 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
754 &phy_data);
755 if ((phy_data & MDIO_CTRL1_RESET) == 0)
c4900be0 756 break;
032b4325 757 usleep_range(10000, 20000);
c4900be0
DS		 758 }
759
6b73e10d 760 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
c4900be0
DS		 761 hw_dbg(hw, "PHY reset did not complete.\n");
762 ret_val = IXGBE_ERR_PHY;
763 goto out;
764 }
765
766 /* Get init offsets */
767 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
768 &data_offset);
769 if (ret_val != 0)
770 goto out;
771
772 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
773 data_offset++;
774 while (!end_data) {
775 /*
776 * Read control word from PHY init contents offset
777 */
778 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
779 control = (eword & IXGBE_CONTROL_MASK_NL) >>
780 IXGBE_CONTROL_SHIFT_NL;
781 edata = eword & IXGBE_DATA_MASK_NL;
782 switch (control) {
783 case IXGBE_DELAY_NL:
784 data_offset++;
785 hw_dbg(hw, "DELAY: %d MS\n", edata);
032b4325 786 usleep_range(edata * 1000, edata * 2000);
c4900be0
DS		 787 break;
788 case IXGBE_DATA_NL:
d6dbee86 789 hw_dbg(hw, "DATA:\n");
c4900be0
DS		 790 data_offset++;
791 hw->eeprom.ops.read(hw, data_offset++,
792 &phy_offset);
793 for (i = 0; i < edata; i++) {
794 hw->eeprom.ops.read(hw, data_offset, &eword);
795 hw->phy.ops.write_reg(hw, phy_offset,
6b73e10d 796 MDIO_MMD_PMAPMD, eword);
c4900be0
DS		 797 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
798 phy_offset);
799 data_offset++;
800 phy_offset++;
801 }
802 break;
803 case IXGBE_CONTROL_NL:
804 data_offset++;
d6dbee86 805 hw_dbg(hw, "CONTROL:\n");
c4900be0
DS		 806 if (edata == IXGBE_CONTROL_EOL_NL) {
807 hw_dbg(hw, "EOL\n");
808 end_data = true;
809 } else if (edata == IXGBE_CONTROL_SOL_NL) {
810 hw_dbg(hw, "SOL\n");
811 } else {
812 hw_dbg(hw, "Bad control value\n");
813 ret_val = IXGBE_ERR_PHY;
814 goto out;
815 }
816 break;
817 default:
818 hw_dbg(hw, "Bad control type\n");
819 ret_val = IXGBE_ERR_PHY;
820 goto out;
821 }
822 }
823
824out:
825 return ret_val;
826}
827
828/**
76d97dd4 829 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
c4900be0
DS		 830 * @hw: pointer to hardware structure
831 *
76d97dd4 832 * Searches for and identifies the SFP module and assigns appropriate PHY type.
c4900be0
DS		 833 **/
834s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
835{
836 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
837 u32 vendor_oui = 0;
553b4497 838 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
c4900be0
DS		 839 u8 identifier = 0;
840 u8 comp_codes_1g = 0;
841 u8 comp_codes_10g = 0;
11afc1b1 842 u8 oui_bytes[3] = {0, 0, 0};
537d58a0 843 u8 cable_tech = 0;
ea0a04df 844 u8 cable_spec = 0;
11afc1b1 845 u16 enforce_sfp = 0;
c4900be0 846
8ca783ab
DS		 847 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
848 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
849 status = IXGBE_ERR_SFP_NOT_PRESENT;
850 goto out;
851 }
852
76d97dd4
ET		 853 status = hw->phy.ops.read_i2c_eeprom(hw,
854 IXGBE_SFF_IDENTIFIER,
c4900be0
DS		 855 &identifier);
856
76d97dd4
ET		 857 if (status == IXGBE_ERR_SWFW_SYNC ||
858 status == IXGBE_ERR_I2C ||
859 status == IXGBE_ERR_SFP_NOT_PRESENT)
860 goto err_read_i2c_eeprom;
c4900be0 861
76d97dd4
ET		 862 /* LAN ID is needed for sfp_type determination */
863 hw->mac.ops.set_lan_id(hw);
864
865 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
866 hw->phy.type = ixgbe_phy_sfp_unsupported;
867 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
868 } else {
869 status = hw->phy.ops.read_i2c_eeprom(hw,
870 IXGBE_SFF_1GBE_COMP_CODES,
871 &comp_codes_1g);
872
873 if (status == IXGBE_ERR_SWFW_SYNC ||
874 status == IXGBE_ERR_I2C ||
875 status == IXGBE_ERR_SFP_NOT_PRESENT)
876 goto err_read_i2c_eeprom;
877
878 status = hw->phy.ops.read_i2c_eeprom(hw,
879 IXGBE_SFF_10GBE_COMP_CODES,
880 &comp_codes_10g);
881
882 if (status == IXGBE_ERR_SWFW_SYNC ||
883 status == IXGBE_ERR_I2C ||
884 status == IXGBE_ERR_SFP_NOT_PRESENT)
885 goto err_read_i2c_eeprom;
886 status = hw->phy.ops.read_i2c_eeprom(hw,
887 IXGBE_SFF_CABLE_TECHNOLOGY,
888 &cable_tech);
889
890 if (status == IXGBE_ERR_SWFW_SYNC ||
891 status == IXGBE_ERR_I2C ||
892 status == IXGBE_ERR_SFP_NOT_PRESENT)
893 goto err_read_i2c_eeprom;
894
895 /* ID Module
896 * =========
897 * 0 SFP_DA_CU
898 * 1 SFP_SR
899 * 2 SFP_LR
900 * 3 SFP_DA_CORE0 - 82599-specific
901 * 4 SFP_DA_CORE1 - 82599-specific
902 * 5 SFP_SR/LR_CORE0 - 82599-specific
903 * 6 SFP_SR/LR_CORE1 - 82599-specific
904 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
905 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
906 * 9 SFP_1g_cu_CORE0 - 82599-specific
907 * 10 SFP_1g_cu_CORE1 - 82599-specific
908 */
11afc1b1 909 if (hw->mac.type == ixgbe_mac_82598EB) {
537d58a0 910 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
11afc1b1
PW		 911 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
912 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
913 hw->phy.sfp_type = ixgbe_sfp_type_sr;
914 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
915 hw->phy.sfp_type = ixgbe_sfp_type_lr;
916 else
917 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
918 } else if (hw->mac.type == ixgbe_mac_82599EB) {
ea0a04df 919 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
11afc1b1
PW		 920 if (hw->bus.lan_id == 0)
921 hw->phy.sfp_type =
922 ixgbe_sfp_type_da_cu_core0;
923 else
924 hw->phy.sfp_type =
925 ixgbe_sfp_type_da_cu_core1;
ea0a04df
DS		 926 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
927 hw->phy.ops.read_i2c_eeprom(
928 hw, IXGBE_SFF_CABLE_SPEC_COMP,
929 &cable_spec);
930 if (cable_spec &
931 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
932 if (hw->bus.lan_id == 0)
933 hw->phy.sfp_type =
934 ixgbe_sfp_type_da_act_lmt_core0;
935 else
936 hw->phy.sfp_type =
937 ixgbe_sfp_type_da_act_lmt_core1;
938 } else {
939 hw->phy.sfp_type =
76d97dd4 940 ixgbe_sfp_type_unknown;
ea0a04df 941 }
76d97dd4
ET		 942 } else if (comp_codes_10g &
943 (IXGBE_SFF_10GBASESR_CAPABLE |
944 IXGBE_SFF_10GBASELR_CAPABLE)) {
11afc1b1
PW		 945 if (hw->bus.lan_id == 0)
946 hw->phy.sfp_type =
947 ixgbe_sfp_type_srlr_core0;
948 else
949 hw->phy.sfp_type =
950 ixgbe_sfp_type_srlr_core1;
76d97dd4 951 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
cb836a97
DS		 952 if (hw->bus.lan_id == 0)
953 hw->phy.sfp_type =
954 ixgbe_sfp_type_1g_cu_core0;
955 else
956 hw->phy.sfp_type =
957 ixgbe_sfp_type_1g_cu_core1;
76d97dd4 958 } else {
11afc1b1 959 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
76d97dd4 960 }
11afc1b1 961 }
c4900be0 962
553b4497
PW		 963 if (hw->phy.sfp_type != stored_sfp_type)
964 hw->phy.sfp_setup_needed = true;
965
966 /* Determine if the SFP+ PHY is dual speed or not. */
50ac58ba 967 hw->phy.multispeed_fiber = false;
553b4497
PW		 968 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
969 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
970 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
971 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
972 hw->phy.multispeed_fiber = true;
973
c4900be0 974 /* Determine PHY vendor */
04193058 975 if (hw->phy.type != ixgbe_phy_nl) {
c4900be0 976 hw->phy.id = identifier;
76d97dd4 977 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 978 IXGBE_SFF_VENDOR_OUI_BYTE0,
979 &oui_bytes[0]);
76d97dd4
ET		 980
981 if (status == IXGBE_ERR_SWFW_SYNC ||
982 status == IXGBE_ERR_I2C ||
983 status == IXGBE_ERR_SFP_NOT_PRESENT)
984 goto err_read_i2c_eeprom;
985
986 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 987 IXGBE_SFF_VENDOR_OUI_BYTE1,
988 &oui_bytes[1]);
76d97dd4
ET		 989
990 if (status == IXGBE_ERR_SWFW_SYNC ||
991 status == IXGBE_ERR_I2C ||
992 status == IXGBE_ERR_SFP_NOT_PRESENT)
993 goto err_read_i2c_eeprom;
994
995 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 996 IXGBE_SFF_VENDOR_OUI_BYTE2,
997 &oui_bytes[2]);
998
76d97dd4
ET		 999 if (status == IXGBE_ERR_SWFW_SYNC ||
1000 status == IXGBE_ERR_I2C ||
1001 status == IXGBE_ERR_SFP_NOT_PRESENT)
1002 goto err_read_i2c_eeprom;
1003
c4900be0
DS		 1004 vendor_oui =
1005 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1006 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1007 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1008
1009 switch (vendor_oui) {
1010 case IXGBE_SFF_VENDOR_OUI_TYCO:
537d58a0 1011 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
ea0a04df 1012 hw->phy.type =
76d97dd4 1013 ixgbe_phy_sfp_passive_tyco;
c4900be0
DS		 1014 break;
1015 case IXGBE_SFF_VENDOR_OUI_FTL:
ea0a04df
DS		 1016 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1017 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1018 else
1019 hw->phy.type = ixgbe_phy_sfp_ftl;
c4900be0
DS		 1020 break;
1021 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1022 hw->phy.type = ixgbe_phy_sfp_avago;
1023 break;
11afc1b1
PW		 1024 case IXGBE_SFF_VENDOR_OUI_INTEL:
1025 hw->phy.type = ixgbe_phy_sfp_intel;
1026 break;
c4900be0 1027 default:
537d58a0 1028 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
ea0a04df 1029 hw->phy.type =
76d97dd4 1030 ixgbe_phy_sfp_passive_unknown;
ea0a04df
DS		 1031 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1032 hw->phy.type =
1033 ixgbe_phy_sfp_active_unknown;
c4900be0
DS		 1034 else
1035 hw->phy.type = ixgbe_phy_sfp_unknown;
1036 break;
1037 }
1038 }
fa466e91 1039
76d97dd4 1040 /* Allow any DA cable vendor */
ea0a04df
DS		 1041 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1042 IXGBE_SFF_DA_ACTIVE_CABLE)) {
fa466e91
WJP		 1043 status = 0;
1044 goto out;
1045 }
1046
cb836a97
DS		 1047 /* Verify supported 1G SFP modules */
1048 if (comp_codes_10g == 0 &&
1049 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1050 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
fa466e91
WJP		 1051 hw->phy.type = ixgbe_phy_sfp_unsupported;
1052 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1053 goto out;
1054 }
1055
1056 /* Anything else 82598-based is supported */
1057 if (hw->mac.type == ixgbe_mac_82598EB) {
11afc1b1
PW		 1058 status = 0;
1059 goto out;
1060 }
1061
04193058 1062 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
cb836a97
DS		 1063 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1064 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1065 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
11afc1b1
PW		 1066 /* Make sure we're a supported PHY type */
1067 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1068 status = 0;
1069 } else {
1070 hw_dbg(hw, "SFP+ module not supported\n");
fa466e91 1071 hw->phy.type = ixgbe_phy_sfp_unsupported;
11afc1b1
PW		 1072 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1073 }
1074 } else {
1075 status = 0;
1076 }
c4900be0
DS		 1077 }
1078
1079out:
1080 return status;
76d97dd4
ET		 1081
1082err_read_i2c_eeprom:
1083 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1084 if (hw->phy.type != ixgbe_phy_nl) {
1085 hw->phy.id = 0;
1086 hw->phy.type = ixgbe_phy_unknown;
1087 }
1088 return IXGBE_ERR_SFP_NOT_PRESENT;
c4900be0
DS		 1089}
1090
1091/**
76d97dd4 1092 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
c4900be0
DS		 1093 * @hw: pointer to hardware structure
1094 * @list_offset: offset to the SFP ID list
1095 * @data_offset: offset to the SFP data block
75f19c3c
ET		 1096 *
1097 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1098 * so it returns the offsets to the phy init sequence block.
c4900be0
DS		 1099 **/
1100s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1101 u16 *list_offset,
1102 u16 *data_offset)
1103{
1104 u16 sfp_id;
cb836a97 1105 u16 sfp_type = hw->phy.sfp_type;
c4900be0
DS		 1106
1107 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1108 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1109
1110 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1111 return IXGBE_ERR_SFP_NOT_PRESENT;
1112
1113 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1114 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1115 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1116
cb836a97
DS		 1117 /*
1118 * Limiting active cables and 1G Phys must be initialized as
1119 * SR modules
1120 */
1121 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1122 sfp_type == ixgbe_sfp_type_1g_cu_core0)
1123 sfp_type = ixgbe_sfp_type_srlr_core0;
1124 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1125 sfp_type == ixgbe_sfp_type_1g_cu_core1)
1126 sfp_type = ixgbe_sfp_type_srlr_core1;
1127
c4900be0
DS		 1128 /* Read offset to PHY init contents */
1129 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1130
1131 if ((!*list_offset) || (*list_offset == 0xFFFF))
11afc1b1 1132 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
c4900be0
DS		 1133
1134 /* Shift offset to first ID word */
1135 (*list_offset)++;
1136
1137 /*
1138 * Find the matching SFP ID in the EEPROM
1139 * and program the init sequence
1140 */
1141 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1142
1143 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
cb836a97 1144 if (sfp_id == sfp_type) {
c4900be0
DS		 1145 (*list_offset)++;
1146 hw->eeprom.ops.read(hw, *list_offset, data_offset);
1147 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1148 hw_dbg(hw, "SFP+ module not supported\n");
1149 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1150 } else {
1151 break;
1152 }
1153 } else {
1154 (*list_offset) += 2;
1155 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1156 return IXGBE_ERR_PHY;
1157 }
1158 }
1159
1160 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1161 hw_dbg(hw, "No matching SFP+ module found\n");
1162 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1163 }
1164
1165 return 0;
1166}
1167
11afc1b1
PW		 1168/**
1169 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1170 * @hw: pointer to hardware structure
1171 * @byte_offset: EEPROM byte offset to read
1172 * @eeprom_data: value read
1173 *
1174 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1175 **/
1176s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1177 u8 *eeprom_data)
1178{
1179 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1180 IXGBE_I2C_EEPROM_DEV_ADDR,
1181 eeprom_data);
1182}
1183
1184/**
1185 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1186 * @hw: pointer to hardware structure
1187 * @byte_offset: EEPROM byte offset to write
1188 * @eeprom_data: value to write
1189 *
1190 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1191 **/
1192s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1193 u8 eeprom_data)
1194{
1195 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1196 IXGBE_I2C_EEPROM_DEV_ADDR,
1197 eeprom_data);
1198}
1199
1200/**
1201 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1202 * @hw: pointer to hardware structure
1203 * @byte_offset: byte offset to read
1204 * @data: value read
1205 *
1206 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1207 * a specified deivce address.
1208 **/
1209s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1210 u8 dev_addr, u8 *data)
1211{
1212 s32 status = 0;
75f19c3c 1213 u32 max_retry = 10;
11afc1b1 1214 u32 retry = 0;
75f19c3c 1215 u16 swfw_mask = 0;
11afc1b1
PW		 1216 bool nack = 1;
1217
75f19c3c
ET		 1218 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1219 swfw_mask = IXGBE_GSSR_PHY1_SM;
1220 else
1221 swfw_mask = IXGBE_GSSR_PHY0_SM;
1222
11afc1b1 1223 do {
75f19c3c
ET		 1224 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) {
1225 status = IXGBE_ERR_SWFW_SYNC;
1226 goto read_byte_out;
1227 }
1228
11afc1b1
PW		 1229 ixgbe_i2c_start(hw);
1230
1231 /* Device Address and write indication */
1232 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1233 if (status != 0)
1234 goto fail;
1235
1236 status = ixgbe_get_i2c_ack(hw);
1237 if (status != 0)
1238 goto fail;
1239
1240 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1241 if (status != 0)
1242 goto fail;
1243
1244 status = ixgbe_get_i2c_ack(hw);
1245 if (status != 0)
1246 goto fail;
1247
1248 ixgbe_i2c_start(hw);
1249
1250 /* Device Address and read indication */
1251 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1252 if (status != 0)
1253 goto fail;
1254
1255 status = ixgbe_get_i2c_ack(hw);
1256 if (status != 0)
1257 goto fail;
1258
1259 status = ixgbe_clock_in_i2c_byte(hw, data);
1260 if (status != 0)
1261 goto fail;
1262
1263 status = ixgbe_clock_out_i2c_bit(hw, nack);
1264 if (status != 0)
1265 goto fail;
1266
1267 ixgbe_i2c_stop(hw);
1268 break;
1269
1270fail:
75f19c3c
ET		 1271 ixgbe_release_swfw_sync(hw, swfw_mask);
1272 msleep(100);
11afc1b1
PW		 1273 ixgbe_i2c_bus_clear(hw);
1274 retry++;
1275 if (retry < max_retry)
1276 hw_dbg(hw, "I2C byte read error - Retrying.\n");
1277 else
1278 hw_dbg(hw, "I2C byte read error.\n");
1279
1280 } while (retry < max_retry);
1281
75f19c3c
ET		 1282 ixgbe_release_swfw_sync(hw, swfw_mask);
1283
1284read_byte_out:
11afc1b1
PW		 1285 return status;
1286}
1287
1288/**
1289 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1290 * @hw: pointer to hardware structure
1291 * @byte_offset: byte offset to write
1292 * @data: value to write
1293 *
1294 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1295 * a specified device address.
1296 **/
1297s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1298 u8 dev_addr, u8 data)
1299{
1300 s32 status = 0;
1301 u32 max_retry = 1;
1302 u32 retry = 0;
75f19c3c
ET		 1303 u16 swfw_mask = 0;
1304
1305 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1306 swfw_mask = IXGBE_GSSR_PHY1_SM;
1307 else
1308 swfw_mask = IXGBE_GSSR_PHY0_SM;
1309
1310 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) {
1311 status = IXGBE_ERR_SWFW_SYNC;
1312 goto write_byte_out;
1313 }
11afc1b1
PW		 1314
1315 do {
1316 ixgbe_i2c_start(hw);
1317
1318 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1319 if (status != 0)
1320 goto fail;
1321
1322 status = ixgbe_get_i2c_ack(hw);
1323 if (status != 0)
1324 goto fail;
1325
1326 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1327 if (status != 0)
1328 goto fail;
1329
1330 status = ixgbe_get_i2c_ack(hw);
1331 if (status != 0)
1332 goto fail;
1333
1334 status = ixgbe_clock_out_i2c_byte(hw, data);
1335 if (status != 0)
1336 goto fail;
1337
1338 status = ixgbe_get_i2c_ack(hw);
1339 if (status != 0)
1340 goto fail;
1341
1342 ixgbe_i2c_stop(hw);
1343 break;
1344
1345fail:
1346 ixgbe_i2c_bus_clear(hw);
1347 retry++;
1348 if (retry < max_retry)
1349 hw_dbg(hw, "I2C byte write error - Retrying.\n");
1350 else
1351 hw_dbg(hw, "I2C byte write error.\n");
1352 } while (retry < max_retry);
1353
75f19c3c
ET		 1354 ixgbe_release_swfw_sync(hw, swfw_mask);
1355
1356write_byte_out:
11afc1b1
PW		 1357 return status;
1358}
1359
1360/**
1361 * ixgbe_i2c_start - Sets I2C start condition
1362 * @hw: pointer to hardware structure
1363 *
1364 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1365 **/
1366static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1367{
1368 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1369
1370 /* Start condition must begin with data and clock high */
1371 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1372 ixgbe_raise_i2c_clk(hw, &i2cctl);
1373
1374 /* Setup time for start condition (4.7us) */
1375 udelay(IXGBE_I2C_T_SU_STA);
1376
1377 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1378
1379 /* Hold time for start condition (4us) */
1380 udelay(IXGBE_I2C_T_HD_STA);
1381
1382 ixgbe_lower_i2c_clk(hw, &i2cctl);
1383
1384 /* Minimum low period of clock is 4.7 us */
1385 udelay(IXGBE_I2C_T_LOW);
1386
1387}
1388
1389/**
1390 * ixgbe_i2c_stop - Sets I2C stop condition
1391 * @hw: pointer to hardware structure
1392 *
1393 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1394 **/
1395static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1396{
1397 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1398
1399 /* Stop condition must begin with data low and clock high */
1400 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1401 ixgbe_raise_i2c_clk(hw, &i2cctl);
1402
1403 /* Setup time for stop condition (4us) */
1404 udelay(IXGBE_I2C_T_SU_STO);
1405
1406 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1407
1408 /* bus free time between stop and start (4.7us)*/
1409 udelay(IXGBE_I2C_T_BUF);
1410}
1411
1412/**
1413 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1414 * @hw: pointer to hardware structure
1415 * @data: data byte to clock in
1416 *
1417 * Clocks in one byte data via I2C data/clock
1418 **/
1419static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1420{
1421 s32 status = 0;
1422 s32 i;
1423 bool bit = 0;
1424
1425 for (i = 7; i >= 0; i--) {
1426 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1427 *data |= bit << i;
1428
1429 if (status != 0)
1430 break;
1431 }
1432
1433 return status;
1434}
1435
1436/**
1437 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1438 * @hw: pointer to hardware structure
1439 * @data: data byte clocked out
1440 *
1441 * Clocks out one byte data via I2C data/clock
1442 **/
1443static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1444{
1445 s32 status = 0;
1446 s32 i;
1447 u32 i2cctl;
1448 bool bit = 0;
1449
1450 for (i = 7; i >= 0; i--) {
1451 bit = (data >> i) & 0x1;
1452 status = ixgbe_clock_out_i2c_bit(hw, bit);
1453
1454 if (status != 0)
1455 break;
1456 }
1457
1458 /* Release SDA line (set high) */
1459 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1460 i2cctl |= IXGBE_I2C_DATA_OUT;
1461 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1462
1463 return status;
1464}
1465
1466/**
1467 * ixgbe_get_i2c_ack - Polls for I2C ACK
1468 * @hw: pointer to hardware structure
1469 *
1470 * Clocks in/out one bit via I2C data/clock
1471 **/
1472static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1473{
1474 s32 status;
1475 u32 i = 0;
1476 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1477 u32 timeout = 10;
1478 bool ack = 1;
1479
1480 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1481
1482 if (status != 0)
1483 goto out;
1484
1485 /* Minimum high period of clock is 4us */
1486 udelay(IXGBE_I2C_T_HIGH);
1487
1488 /* Poll for ACK. Note that ACK in I2C spec is
1489 * transition from 1 to 0 */
1490 for (i = 0; i < timeout; i++) {
1491 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1492 ack = ixgbe_get_i2c_data(&i2cctl);
1493
1494 udelay(1);
1495 if (ack == 0)
1496 break;
1497 }
1498
1499 if (ack == 1) {
1500 hw_dbg(hw, "I2C ack was not received.\n");
1501 status = IXGBE_ERR_I2C;
1502 }
1503
1504 ixgbe_lower_i2c_clk(hw, &i2cctl);
1505
1506 /* Minimum low period of clock is 4.7 us */
1507 udelay(IXGBE_I2C_T_LOW);
1508
1509out:
1510 return status;
1511}
1512
1513/**
1514 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1515 * @hw: pointer to hardware structure
1516 * @data: read data value
1517 *
1518 * Clocks in one bit via I2C data/clock
1519 **/
1520static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1521{
1522 s32 status;
1523 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1524
1525 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1526
1527 /* Minimum high period of clock is 4us */
1528 udelay(IXGBE_I2C_T_HIGH);
1529
1530 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1531 *data = ixgbe_get_i2c_data(&i2cctl);
1532
1533 ixgbe_lower_i2c_clk(hw, &i2cctl);
1534
1535 /* Minimum low period of clock is 4.7 us */
1536 udelay(IXGBE_I2C_T_LOW);
1537
1538 return status;
1539}
1540
1541/**
1542 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1543 * @hw: pointer to hardware structure
1544 * @data: data value to write
1545 *
1546 * Clocks out one bit via I2C data/clock
1547 **/
1548static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1549{
1550 s32 status;
1551 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1552
1553 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1554 if (status == 0) {
1555 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1556
1557 /* Minimum high period of clock is 4us */
1558 udelay(IXGBE_I2C_T_HIGH);
1559
1560 ixgbe_lower_i2c_clk(hw, &i2cctl);
1561
1562 /* Minimum low period of clock is 4.7 us.
1563 * This also takes care of the data hold time.
1564 */
1565 udelay(IXGBE_I2C_T_LOW);
1566 } else {
1567 status = IXGBE_ERR_I2C;
1568 hw_dbg(hw, "I2C data was not set to %X\n", data);
1569 }
1570
1571 return status;
1572}
1573/**
1574 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1575 * @hw: pointer to hardware structure
1576 * @i2cctl: Current value of I2CCTL register
1577 *
1578 * Raises the I2C clock line '0'->'1'
1579 **/
1580static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1581{
1582 s32 status = 0;
1583
1584 *i2cctl |= IXGBE_I2C_CLK_OUT;
1585
1586 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1587
1588 /* SCL rise time (1000ns) */
1589 udelay(IXGBE_I2C_T_RISE);
1590
1591 return status;
1592}
1593
1594/**
1595 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1596 * @hw: pointer to hardware structure
1597 * @i2cctl: Current value of I2CCTL register
1598 *
1599 * Lowers the I2C clock line '1'->'0'
1600 **/
1601static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1602{
1603
1604 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1605
1606 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1607
1608 /* SCL fall time (300ns) */
1609 udelay(IXGBE_I2C_T_FALL);
1610}
1611
1612/**
1613 * ixgbe_set_i2c_data - Sets the I2C data bit
1614 * @hw: pointer to hardware structure
1615 * @i2cctl: Current value of I2CCTL register
1616 * @data: I2C data value (0 or 1) to set
1617 *
1618 * Sets the I2C data bit
1619 **/
1620static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1621{
1622 s32 status = 0;
1623
1624 if (data)
1625 *i2cctl |= IXGBE_I2C_DATA_OUT;
1626 else
1627 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1628
1629 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1630
1631 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1632 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1633
1634 /* Verify data was set correctly */
1635 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1636 if (data != ixgbe_get_i2c_data(i2cctl)) {
1637 status = IXGBE_ERR_I2C;
1638 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1639 }
1640
1641 return status;
1642}
1643
1644/**
1645 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1646 * @hw: pointer to hardware structure
1647 * @i2cctl: Current value of I2CCTL register
1648 *
1649 * Returns the I2C data bit value
1650 **/
1651static bool ixgbe_get_i2c_data(u32 *i2cctl)
1652{
1653 bool data;
1654
1655 if (*i2cctl & IXGBE_I2C_DATA_IN)
1656 data = 1;
1657 else
1658 data = 0;
1659
1660 return data;
1661}
1662
1663/**
1664 * ixgbe_i2c_bus_clear - Clears the I2C bus
1665 * @hw: pointer to hardware structure
1666 *
1667 * Clears the I2C bus by sending nine clock pulses.
1668 * Used when data line is stuck low.
1669 **/
1670static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1671{
1672 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1673 u32 i;
1674
75f19c3c
ET		 1675 ixgbe_i2c_start(hw);
1676
11afc1b1
PW		 1677 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1678
1679 for (i = 0; i < 9; i++) {
1680 ixgbe_raise_i2c_clk(hw, &i2cctl);
1681
1682 /* Min high period of clock is 4us */
1683 udelay(IXGBE_I2C_T_HIGH);
1684
1685 ixgbe_lower_i2c_clk(hw, &i2cctl);
1686
1687 /* Min low period of clock is 4.7us*/
1688 udelay(IXGBE_I2C_T_LOW);
1689 }
1690
75f19c3c
ET		 1691 ixgbe_i2c_start(hw);
1692
11afc1b1
PW		 1693 /* Put the i2c bus back to default state */
1694 ixgbe_i2c_stop(hw);
1695}
1696
119fc60a 1697/**
25985edc 1698 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
119fc60a
MC		 1699 * @hw: pointer to hardware structure
1700 *
1701 * Checks if the LASI temp alarm status was triggered due to overtemp
1702 **/
1703s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1704{
1705 s32 status = 0;
1706 u16 phy_data = 0;
1707
1708 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1709 goto out;
1710
1711 /* Check that the LASI temp alarm status was triggered */
1712 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1713 MDIO_MMD_PMAPMD, &phy_data);
1714
1715 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1716 goto out;
1717
1718 status = IXGBE_ERR_OVERTEMP;
1719out:
1720 return status;
1721}
Linux kernel - Deliverables
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