[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_phy.c

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2008 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/sched.h>

#include "ixgbe_common.h"
#include "ixgbe_phy.h"

static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);

/**
 *  ixgbe_identify_phy_generic - Get physical layer module
 *  @hw: pointer to hardware structure
 *
 *  Determines the physical layer module found on the current adapter.
 **/
s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
{
	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
	u32 phy_addr;

	if (hw->phy.type == ixgbe_phy_unknown) {
		for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
			if (ixgbe_validate_phy_addr(hw, phy_addr)) {
				hw->phy.addr = phy_addr;
				ixgbe_get_phy_id(hw);
				hw->phy.type =
				        ixgbe_get_phy_type_from_id(hw->phy.id);
				status = 0;
				break;
			}
		}
	} else {
		status = 0;
	}

	return status;
}

/**
 *  ixgbe_validate_phy_addr - Determines phy address is valid
 *  @hw: pointer to hardware structure
 *
 **/
static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
{
	u16 phy_id = 0;
	bool valid = false;

	hw->phy.addr = phy_addr;
	hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
	                     IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);

	if (phy_id != 0xFFFF && phy_id != 0x0)
		valid = true;

	return valid;
}

/**
 *  ixgbe_get_phy_id - Get the phy type
 *  @hw: pointer to hardware structure
 *
 **/
static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
{
	u32 status;
	u16 phy_id_high = 0;
	u16 phy_id_low = 0;

	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
	                              IXGBE_MDIO_PMA_PMD_DEV_TYPE,
	                              &phy_id_high);

	if (status == 0) {
		hw->phy.id = (u32)(phy_id_high << 16);
		status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
		                              IXGBE_MDIO_PMA_PMD_DEV_TYPE,
		                              &phy_id_low);
		hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
		hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
	}
	return status;
}

/**
 *  ixgbe_get_phy_type_from_id - Get the phy type
 *  @hw: pointer to hardware structure
 *
 **/
static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
{
	enum ixgbe_phy_type phy_type;

	switch (phy_id) {
	case QT2022_PHY_ID:
		phy_type = ixgbe_phy_qt;
		break;
	default:
		phy_type = ixgbe_phy_unknown;
		break;
	}

	return phy_type;
}

/**
 *  ixgbe_reset_phy_generic - Performs a PHY reset
 *  @hw: pointer to hardware structure
 **/
s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
{
	/*
	 * Perform soft PHY reset to the PHY_XS.
	 * This will cause a soft reset to the PHY
	 */
	return hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
	                             IXGBE_MDIO_PHY_XS_DEV_TYPE,
	                             IXGBE_MDIO_PHY_XS_RESET);
}

/**
 *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 *  @hw: pointer to hardware structure
 *  @reg_addr: 32 bit address of PHY register to read
 *  @phy_data: Pointer to read data from PHY register
 **/
s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
                               u32 device_type, u16 *phy_data)
{
	u32 command;
	u32 i;
	u32 data;
	s32 status = 0;
	u16 gssr;

	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
		gssr = IXGBE_GSSR_PHY1_SM;
	else
		gssr = IXGBE_GSSR_PHY0_SM;

	if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
		status = IXGBE_ERR_SWFW_SYNC;

	if (status == 0) {
		/* Setup and write the address cycle command */
		command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
		           (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
		           (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
		           (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));

		IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);

		/*
		 * Check every 10 usec to see if the address cycle completed.
		 * The MDI Command bit will clear when the operation is
		 * complete
		 */
		for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
			udelay(10);

			command = IXGBE_READ_REG(hw, IXGBE_MSCA);

			if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
				break;
		}

		if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
			hw_dbg(hw, "PHY address command did not complete.\n");
			status = IXGBE_ERR_PHY;
		}

		if (status == 0) {
			/*
			 * Address cycle complete, setup and write the read
			 * command
			 */
			command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
			           (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
			           (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
			           (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));

			IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);

			/*
			 * Check every 10 usec to see if the address cycle
			 * completed. The MDI Command bit will clear when the
			 * operation is complete
			 */
			for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
				udelay(10);

				command = IXGBE_READ_REG(hw, IXGBE_MSCA);

				if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
					break;
			}

			if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
				hw_dbg(hw, "PHY read command didn't complete\n");
				status = IXGBE_ERR_PHY;
			} else {
				/*
				 * Read operation is complete.  Get the data
				 * from MSRWD
				 */
				data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
				data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
				*phy_data = (u16)(data);
			}
		}

		ixgbe_release_swfw_sync(hw, gssr);
	}

	return status;
}

/**
 *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 *  @hw: pointer to hardware structure
 *  @reg_addr: 32 bit PHY register to write
 *  @device_type: 5 bit device type
 *  @phy_data: Data to write to the PHY register
 **/
s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
                                u32 device_type, u16 phy_data)
{
	u32 command;
	u32 i;
	s32 status = 0;
	u16 gssr;

	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
		gssr = IXGBE_GSSR_PHY1_SM;
	else
		gssr = IXGBE_GSSR_PHY0_SM;

	if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
		status = IXGBE_ERR_SWFW_SYNC;

	if (status == 0) {
		/* Put the data in the MDI single read and write data register*/
		IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);

		/* Setup and write the address cycle command */
		command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
		           (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
		           (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
		           (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));

		IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);

		/*
		 * Check every 10 usec to see if the address cycle completed.
		 * The MDI Command bit will clear when the operation is
		 * complete
		 */
		for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
			udelay(10);

			command = IXGBE_READ_REG(hw, IXGBE_MSCA);

			if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
				break;
		}

		if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
			hw_dbg(hw, "PHY address cmd didn't complete\n");
			status = IXGBE_ERR_PHY;
		}

		if (status == 0) {
			/*
			 * Address cycle complete, setup and write the write
			 * command
			 */
			command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
			           (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
			           (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
			           (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));

			IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);

			/*
			 * Check every 10 usec to see if the address cycle
			 * completed. The MDI Command bit will clear when the
			 * operation is complete
			 */
			for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
				udelay(10);

				command = IXGBE_READ_REG(hw, IXGBE_MSCA);

				if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
					break;
			}

			if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
				hw_dbg(hw, "PHY address cmd didn't complete\n");
				status = IXGBE_ERR_PHY;
			}
		}

		ixgbe_release_swfw_sync(hw, gssr);
	}

	return status;
}

/**
 *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 *  @hw: pointer to hardware structure
 *
 *  Restart autonegotiation and PHY and waits for completion.
 **/
s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
{
	s32 status = IXGBE_NOT_IMPLEMENTED;
	u32 time_out;
	u32 max_time_out = 10;
	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;

	/*
	 * Set advertisement settings in PHY based on autoneg_advertised
	 * settings. If autoneg_advertised = 0, then advertise default values
	 * tnx devices cannot be "forced" to a autoneg 10G and fail.  But can
	 * for a 1G.
	 */
	hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
	                     IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);

	if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
		autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */
	else
		autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */

	hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
	                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);

	/* Restart PHY autonegotiation and wait for completion */
	hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
	                     IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);

	autoneg_reg |= IXGBE_MII_RESTART;

	hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
	                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);

	/* Wait for autonegotiation to finish */
	for (time_out = 0; time_out < max_time_out; time_out++) {
		udelay(10);
		/* Restart PHY autonegotiation and wait for completion */
		status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
		                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
		                              &autoneg_reg);

		autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
		if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
			status = 0;
			break;
		}
	}

	if (time_out == max_time_out)
		status = IXGBE_ERR_LINK_SETUP;

	return status;
}

/**
 *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 *  @hw: pointer to hardware structure
 *  @speed: new link speed
 *  @autoneg: true if autonegotiation enabled
 **/
s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
                                       ixgbe_link_speed speed,
                                       bool autoneg,
                                       bool autoneg_wait_to_complete)
{

	/*
	 * Clear autoneg_advertised and set new values based on input link
	 * speed.
	 */
	hw->phy.autoneg_advertised = 0;

	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;

	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;

	/* Setup link based on the new speed settings */
	hw->phy.ops.setup_link(hw);

	return 0;
}
Commit	Line	Data
9a799d71 AK	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
b4617240	4	Copyright(c) 1999 - 2008 Intel Corporation.
9a799d71 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
9a799d71 AK	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#include <linux/pci.h>
	29	#include <linux/delay.h>
	30	#include <linux/sched.h>
	31
	32	#include "ixgbe_common.h"
	33	#include "ixgbe_phy.h"
	34
c44ade9e	35	static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
9a799d71 AK	36	static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
9a799d71 AK	37	static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
9a799d71 AK	38
9a799d71 AK	39	/**
c44ade9e	40	* ixgbe_identify_phy_generic - Get physical layer module
9a799d71 AK	41	* @hw: pointer to hardware structure
	42	*
	43	* Determines the physical layer module found on the current adapter.
	44	**/
c44ade9e	45	s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
9a799d71 AK	46	{
	47	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
	48	u32 phy_addr;
	49
c44ade9e JB	50	if (hw->phy.type == ixgbe_phy_unknown) {
	51	for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
	52	if (ixgbe_validate_phy_addr(hw, phy_addr)) {
	53	hw->phy.addr = phy_addr;
	54	ixgbe_get_phy_id(hw);
	55	hw->phy.type =
	56	ixgbe_get_phy_type_from_id(hw->phy.id);
	57	status = 0;
	58	break;
	59	}
9a799d71	60	}
c44ade9e JB	61	} else {
c44ade9e JB	62	status = 0;
9a799d71	63	}
c44ade9e	64
9a799d71 AK	65	return status;
	66	}
	67
	68	/**
	69	* ixgbe_validate_phy_addr - Determines phy address is valid
	70	* @hw: pointer to hardware structure
	71	*
	72	**/
	73	static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
	74	{
	75	u16 phy_id = 0;
	76	bool valid = false;
	77
	78	hw->phy.addr = phy_addr;
c44ade9e JB	79	hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
c44ade9e JB	80	IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
9a799d71 AK	81
	82	if (phy_id != 0xFFFF && phy_id != 0x0)
	83	valid = true;
	84
	85	return valid;
	86	}
	87
	88	/**
	89	* ixgbe_get_phy_id - Get the phy type
	90	* @hw: pointer to hardware structure
	91	*
	92	**/
	93	static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
	94	{
	95	u32 status;
	96	u16 phy_id_high = 0;
	97	u16 phy_id_low = 0;
	98
c44ade9e JB	99	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
	100	IXGBE_MDIO_PMA_PMD_DEV_TYPE,
	101	&phy_id_high);
9a799d71 AK	102
	103	if (status == 0) {
	104	hw->phy.id = (u32)(phy_id_high << 16);
c44ade9e JB	105	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
	106	IXGBE_MDIO_PMA_PMD_DEV_TYPE,
	107	&phy_id_low);
9a799d71 AK	108	hw->phy.id \|= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
	109	hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
	110	}
9a799d71 AK	111	return status;
	112	}
	113
	114	/**
	115	* ixgbe_get_phy_type_from_id - Get the phy type
	116	* @hw: pointer to hardware structure
	117	*
	118	**/
	119	static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
	120	{
	121	enum ixgbe_phy_type phy_type;
	122
	123	switch (phy_id) {
9a799d71 AK	124	case QT2022_PHY_ID:
	125	phy_type = ixgbe_phy_qt;
	126	break;
	127	default:
	128	phy_type = ixgbe_phy_unknown;
	129	break;
	130	}
	131
	132	return phy_type;
	133	}
	134
	135	/**
c44ade9e	136	* ixgbe_reset_phy_generic - Performs a PHY reset
9a799d71 AK	137	* @hw: pointer to hardware structure
9a799d71 AK	138	**/
c44ade9e	139	s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
9a799d71 AK	140	{
	141	/*
	142	* Perform soft PHY reset to the PHY_XS.
	143	* This will cause a soft reset to the PHY
	144	*/
c44ade9e JB	145	return hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
	146	IXGBE_MDIO_PHY_XS_DEV_TYPE,
	147	IXGBE_MDIO_PHY_XS_RESET);
9a799d71 AK	148	}
	149
	150	/**
c44ade9e	151	* ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
9a799d71 AK	152	* @hw: pointer to hardware structure
	153	* @reg_addr: 32 bit address of PHY register to read
	154	* @phy_data: Pointer to read data from PHY register
	155	**/
c44ade9e JB	156	s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
c44ade9e JB	157	u32 device_type, u16 *phy_data)
9a799d71 AK	158	{
	159	u32 command;
	160	u32 i;
9a799d71 AK	161	u32 data;
	162	s32 status = 0;
	163	u16 gssr;
	164
	165	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
	166	gssr = IXGBE_GSSR_PHY1_SM;
	167	else
	168	gssr = IXGBE_GSSR_PHY0_SM;
	169
	170	if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
	171	status = IXGBE_ERR_SWFW_SYNC;
	172
	173	if (status == 0) {
	174	/* Setup and write the address cycle command */
	175	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) \|
c44ade9e JB	176	(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
	177	(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) \|
	178	(IXGBE_MSCA_ADDR_CYCLE \| IXGBE_MSCA_MDI_COMMAND));
9a799d71 AK	179
	180	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
	181
	182	/*
	183	* Check every 10 usec to see if the address cycle completed.
	184	* The MDI Command bit will clear when the operation is
	185	* complete
	186	*/
c44ade9e	187	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71 AK	188	udelay(10);
	189
	190	command = IXGBE_READ_REG(hw, IXGBE_MSCA);
	191
	192	if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
	193	break;
	194	}
	195
	196	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
	197	hw_dbg(hw, "PHY address command did not complete.\n");
	198	status = IXGBE_ERR_PHY;
	199	}
	200
	201	if (status == 0) {
	202	/*
	203	* Address cycle complete, setup and write the read
	204	* command
	205	*/
	206	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) \|
c44ade9e JB	207	(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
	208	(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) \|
	209	(IXGBE_MSCA_READ \| IXGBE_MSCA_MDI_COMMAND));
9a799d71 AK	210
	211	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
	212
	213	/*
	214	* Check every 10 usec to see if the address cycle
	215	* completed. The MDI Command bit will clear when the
	216	* operation is complete
	217	*/
c44ade9e	218	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71 AK	219	udelay(10);
	220
	221	command = IXGBE_READ_REG(hw, IXGBE_MSCA);
	222
	223	if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
	224	break;
	225	}
	226
	227	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
c44ade9e	228	hw_dbg(hw, "PHY read command didn't complete\n");
9a799d71 AK	229	status = IXGBE_ERR_PHY;
	230	} else {
	231	/*
	232	* Read operation is complete. Get the data
	233	* from MSRWD
	234	*/
	235	data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
	236	data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
	237	*phy_data = (u16)(data);
	238	}
	239	}
	240
	241	ixgbe_release_swfw_sync(hw, gssr);
	242	}
c44ade9e	243
9a799d71 AK	244	return status;
	245	}
	246
	247	/**
c44ade9e	248	* ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
9a799d71 AK	249	* @hw: pointer to hardware structure
	250	* @reg_addr: 32 bit PHY register to write
	251	* @device_type: 5 bit device type
	252	* @phy_data: Data to write to the PHY register
	253	**/
c44ade9e JB	254	s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
c44ade9e JB	255	u32 device_type, u16 phy_data)
9a799d71 AK	256	{
	257	u32 command;
	258	u32 i;
9a799d71 AK	259	s32 status = 0;
	260	u16 gssr;
	261
	262	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
	263	gssr = IXGBE_GSSR_PHY1_SM;
	264	else
	265	gssr = IXGBE_GSSR_PHY0_SM;
	266
	267	if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
	268	status = IXGBE_ERR_SWFW_SYNC;
	269
	270	if (status == 0) {
	271	/* Put the data in the MDI single read and write data register*/
	272	IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
	273
	274	/* Setup and write the address cycle command */
	275	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) \|
c44ade9e JB	276	(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
	277	(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) \|
	278	(IXGBE_MSCA_ADDR_CYCLE \| IXGBE_MSCA_MDI_COMMAND));
9a799d71 AK	279
	280	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
	281
	282	/*
	283	* Check every 10 usec to see if the address cycle completed.
	284	* The MDI Command bit will clear when the operation is
	285	* complete
	286	*/
c44ade9e	287	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71 AK	288	udelay(10);
	289
	290	command = IXGBE_READ_REG(hw, IXGBE_MSCA);
	291
c44ade9e	292	if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71	293	break;
9a799d71 AK	294	}
9a799d71 AK	295
c44ade9e JB	296	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
c44ade9e JB	297	hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71	298	status = IXGBE_ERR_PHY;
c44ade9e	299	}
9a799d71 AK	300
	301	if (status == 0) {
	302	/*
	303	* Address cycle complete, setup and write the write
	304	* command
	305	*/
	306	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) \|
c44ade9e JB	307	(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
	308	(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) \|
	309	(IXGBE_MSCA_WRITE \| IXGBE_MSCA_MDI_COMMAND));
9a799d71 AK	310
	311	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
	312
	313	/*
	314	* Check every 10 usec to see if the address cycle
	315	* completed. The MDI Command bit will clear when the
	316	* operation is complete
	317	*/
c44ade9e	318	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71 AK	319	udelay(10);
	320
	321	command = IXGBE_READ_REG(hw, IXGBE_MSCA);
	322
c44ade9e	323	if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71	324	break;
9a799d71 AK	325	}
9a799d71 AK	326
c44ade9e JB	327	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
c44ade9e JB	328	hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71	329	status = IXGBE_ERR_PHY;
c44ade9e	330	}
9a799d71 AK	331	}
	332
	333	ixgbe_release_swfw_sync(hw, gssr);
	334	}
	335
	336	return status;
	337	}
	338
	339	/**
c44ade9e	340	* ixgbe_setup_phy_link_generic - Set and restart autoneg
9a799d71 AK	341	* @hw: pointer to hardware structure
	342	*
	343	* Restart autonegotiation and PHY and waits for completion.
	344	**/
c44ade9e	345	s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
9a799d71 AK	346	{
	347	s32 status = IXGBE_NOT_IMPLEMENTED;
	348	u32 time_out;
	349	u32 max_time_out = 10;
c44ade9e	350	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
9a799d71 AK	351
	352	/*
	353	* Set advertisement settings in PHY based on autoneg_advertised
	354	* settings. If autoneg_advertised = 0, then advertise default values
c44ade9e	355	* tnx devices cannot be "forced" to a autoneg 10G and fail. But can
9a799d71 AK	356	* for a 1G.
9a799d71 AK	357	*/
c44ade9e JB	358	hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
c44ade9e JB	359	IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
9a799d71 AK	360
	361	if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
	362	autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */
	363	else
	364	autoneg_reg \|= 0x1000; /* 1 in bit 12 is 10G/1G operation */
	365
c44ade9e JB	366	hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
c44ade9e JB	367	IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
9a799d71 AK	368
9a799d71 AK	369	/* Restart PHY autonegotiation and wait for completion */
c44ade9e JB	370	hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
c44ade9e JB	371	IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
9a799d71	372
c44ade9e	373	autoneg_reg \|= IXGBE_MII_RESTART;
9a799d71	374
c44ade9e JB	375	hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
c44ade9e JB	376	IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
9a799d71 AK	377
	378	/* Wait for autonegotiation to finish */
	379	for (time_out = 0; time_out < max_time_out; time_out++) {
	380	udelay(10);
	381	/* Restart PHY autonegotiation and wait for completion */
c44ade9e JB	382	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
	383	IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
	384	&autoneg_reg);
9a799d71	385
c44ade9e JB	386	autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
c44ade9e JB	387	if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
9a799d71 AK	388	status = 0;
	389	break;
	390	}
	391	}
	392
	393	if (time_out == max_time_out)
	394	status = IXGBE_ERR_LINK_SETUP;
	395
	396	return status;
	397	}
	398
	399	/**
c44ade9e	400	* ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
9a799d71 AK	401	* @hw: pointer to hardware structure
	402	* @speed: new link speed
	403	* @autoneg: true if autonegotiation enabled
	404	**/
c44ade9e JB	405	s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
	406	ixgbe_link_speed speed,
	407	bool autoneg,
	408	bool autoneg_wait_to_complete)
9a799d71	409	{
c44ade9e	410
9a799d71 AK	411	/*
	412	* Clear autoneg_advertised and set new values based on input link
	413	* speed.
	414	*/
	415	hw->phy.autoneg_advertised = 0;
	416
	417	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
	418	hw->phy.autoneg_advertised \|= IXGBE_LINK_SPEED_10GB_FULL;
c44ade9e	419
9a799d71 AK	420	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
	421	hw->phy.autoneg_advertised \|= IXGBE_LINK_SPEED_1GB_FULL;
	422
	423	/* Setup link based on the new speed settings */
c44ade9e	424	hw->phy.ops.setup_link(hw);
9a799d71 AK	425
	426	return 0;
	427	}
c44ade9e	428