Commit | Line | Data |
---|---|---|
fe15e8e1 DS |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
a52055e0 | 4 | Copyright(c) 1999 - 2011 Intel Corporation. |
fe15e8e1 DS |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/pci.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/sched.h> | |
31 | ||
32 | #include "ixgbe.h" | |
33 | #include "ixgbe_phy.h" | |
fe15e8e1 DS |
34 | |
35 | #define IXGBE_X540_MAX_TX_QUEUES 128 | |
36 | #define IXGBE_X540_MAX_RX_QUEUES 128 | |
37 | #define IXGBE_X540_RAR_ENTRIES 128 | |
38 | #define IXGBE_X540_MC_TBL_SIZE 128 | |
39 | #define IXGBE_X540_VFT_TBL_SIZE 128 | |
e09ad236 | 40 | #define IXGBE_X540_RX_PB_SIZE 384 |
fe15e8e1 DS |
41 | |
42 | static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); | |
43 | static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); | |
44 | static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask); | |
45 | static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask); | |
46 | static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); | |
47 | static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); | |
48 | ||
b93a2226 | 49 | static enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) |
fe15e8e1 DS |
50 | { |
51 | return ixgbe_media_type_copper; | |
52 | } | |
53 | ||
54 | static s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw) | |
55 | { | |
56 | struct ixgbe_mac_info *mac = &hw->mac; | |
57 | ||
58 | /* Call PHY identify routine to get the phy type */ | |
59 | ixgbe_identify_phy_generic(hw); | |
60 | ||
61 | mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; | |
62 | mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; | |
63 | mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; | |
64 | mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; | |
65 | mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; | |
66 | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); | |
67 | ||
68 | return 0; | |
69 | } | |
70 | ||
71 | /** | |
72 | * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires | |
73 | * @hw: pointer to hardware structure | |
74 | * @speed: new link speed | |
75 | * @autoneg: true if autonegotiation enabled | |
76 | * @autoneg_wait_to_complete: true when waiting for completion is needed | |
77 | **/ | |
b93a2226 DS |
78 | static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, |
79 | ixgbe_link_speed speed, bool autoneg, | |
80 | bool autoneg_wait_to_complete) | |
fe15e8e1 DS |
81 | { |
82 | return hw->phy.ops.setup_link_speed(hw, speed, autoneg, | |
83 | autoneg_wait_to_complete); | |
84 | } | |
85 | ||
86 | /** | |
87 | * ixgbe_reset_hw_X540 - Perform hardware reset | |
88 | * @hw: pointer to hardware structure | |
89 | * | |
90 | * Resets the hardware by resetting the transmit and receive units, masks | |
91 | * and clears all interrupts, perform a PHY reset, and perform a link (MAC) | |
92 | * reset. | |
93 | **/ | |
b93a2226 | 94 | static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) |
fe15e8e1 DS |
95 | { |
96 | ixgbe_link_speed link_speed; | |
97 | s32 status = 0; | |
98 | u32 ctrl; | |
99 | u32 ctrl_ext; | |
100 | u32 reset_bit; | |
101 | u32 i; | |
102 | u32 autoc; | |
103 | u32 autoc2; | |
104 | bool link_up = false; | |
105 | ||
106 | /* Call adapter stop to disable tx/rx and clear interrupts */ | |
107 | hw->mac.ops.stop_adapter(hw); | |
108 | ||
109 | /* | |
110 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master | |
111 | * access and verify no pending requests before reset | |
112 | */ | |
a4297dc2 | 113 | ixgbe_disable_pcie_master(hw); |
fe15e8e1 | 114 | |
a4297dc2 | 115 | mac_reset_top: |
fe15e8e1 DS |
116 | /* |
117 | * Issue global reset to the MAC. Needs to be SW reset if link is up. | |
118 | * If link reset is used when link is up, it might reset the PHY when | |
119 | * mng is using it. If link is down or the flag to force full link | |
120 | * reset is set, then perform link reset. | |
121 | */ | |
122 | if (hw->force_full_reset) { | |
123 | reset_bit = IXGBE_CTRL_LNK_RST; | |
124 | } else { | |
125 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
126 | if (!link_up) | |
127 | reset_bit = IXGBE_CTRL_LNK_RST; | |
128 | else | |
129 | reset_bit = IXGBE_CTRL_RST; | |
130 | } | |
131 | ||
132 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
2c4db944 | 133 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | reset_bit)); |
fe15e8e1 DS |
134 | IXGBE_WRITE_FLUSH(hw); |
135 | ||
136 | /* Poll for reset bit to self-clear indicating reset is complete */ | |
137 | for (i = 0; i < 10; i++) { | |
138 | udelay(1); | |
139 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
2c4db944 | 140 | if (!(ctrl & reset_bit)) |
fe15e8e1 DS |
141 | break; |
142 | } | |
2c4db944 | 143 | if (ctrl & reset_bit) { |
fe15e8e1 DS |
144 | status = IXGBE_ERR_RESET_FAILED; |
145 | hw_dbg(hw, "Reset polling failed to complete.\n"); | |
146 | } | |
147 | ||
a4297dc2 ET |
148 | /* |
149 | * Double resets are required for recovery from certain error | |
150 | * conditions. Between resets, it is necessary to stall to allow time | |
151 | * for any pending HW events to complete. We use 1usec since that is | |
152 | * what is needed for ixgbe_disable_pcie_master(). The second reset | |
153 | * then clears out any effects of those events. | |
154 | */ | |
155 | if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { | |
156 | hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; | |
157 | udelay(1); | |
158 | goto mac_reset_top; | |
159 | } | |
160 | ||
fe15e8e1 DS |
161 | /* Clear PF Reset Done bit so PF/VF Mail Ops can work */ |
162 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
163 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
164 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
165 | ||
166 | msleep(50); | |
167 | ||
168 | /* Set the Rx packet buffer size. */ | |
169 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); | |
170 | ||
171 | /* Store the permanent mac address */ | |
172 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); | |
173 | ||
174 | /* | |
175 | * Store the original AUTOC/AUTOC2 values if they have not been | |
176 | * stored off yet. Otherwise restore the stored original | |
177 | * values since the reset operation sets back to defaults. | |
178 | */ | |
179 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
180 | autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); | |
181 | if (hw->mac.orig_link_settings_stored == false) { | |
182 | hw->mac.orig_autoc = autoc; | |
183 | hw->mac.orig_autoc2 = autoc2; | |
184 | hw->mac.orig_link_settings_stored = true; | |
185 | } else { | |
186 | if (autoc != hw->mac.orig_autoc) | |
187 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | | |
188 | IXGBE_AUTOC_AN_RESTART)); | |
189 | ||
190 | if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != | |
191 | (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { | |
192 | autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; | |
193 | autoc2 |= (hw->mac.orig_autoc2 & | |
194 | IXGBE_AUTOC2_UPPER_MASK); | |
195 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); | |
196 | } | |
197 | } | |
198 | ||
199 | /* | |
200 | * Store MAC address from RAR0, clear receive address registers, and | |
201 | * clear the multicast table. Also reset num_rar_entries to 128, | |
202 | * since we modify this value when programming the SAN MAC address. | |
203 | */ | |
93cb38dc | 204 | hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES; |
fe15e8e1 DS |
205 | hw->mac.ops.init_rx_addrs(hw); |
206 | ||
207 | /* Store the permanent mac address */ | |
208 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); | |
209 | ||
210 | /* Store the permanent SAN mac address */ | |
211 | hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); | |
212 | ||
213 | /* Add the SAN MAC address to the RAR only if it's a valid address */ | |
214 | if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { | |
215 | hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, | |
216 | hw->mac.san_addr, 0, IXGBE_RAH_AV); | |
217 | ||
218 | /* Reserve the last RAR for the SAN MAC address */ | |
219 | hw->mac.num_rar_entries--; | |
220 | } | |
221 | ||
222 | /* Store the alternative WWNN/WWPN prefix */ | |
223 | hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, | |
224 | &hw->mac.wwpn_prefix); | |
225 | ||
226 | return status; | |
227 | } | |
228 | ||
7184b7cf ET |
229 | /** |
230 | * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx | |
231 | * @hw: pointer to hardware structure | |
232 | * | |
233 | * Starts the hardware using the generic start_hw function | |
234 | * and the generation start_hw function. | |
235 | * Then performs revision-specific operations, if any. | |
236 | **/ | |
237 | static s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) | |
238 | { | |
239 | s32 ret_val = 0; | |
240 | ||
241 | ret_val = ixgbe_start_hw_generic(hw); | |
242 | if (ret_val != 0) | |
243 | goto out; | |
244 | ||
245 | ret_val = ixgbe_start_hw_gen2(hw); | |
e09ad236 | 246 | hw->mac.rx_pb_size = IXGBE_X540_RX_PB_SIZE; |
7184b7cf ET |
247 | out: |
248 | return ret_val; | |
249 | } | |
250 | ||
fe15e8e1 DS |
251 | /** |
252 | * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type | |
253 | * @hw: pointer to hardware structure | |
254 | * | |
255 | * Determines physical layer capabilities of the current configuration. | |
256 | **/ | |
b93a2226 | 257 | static u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) |
fe15e8e1 DS |
258 | { |
259 | u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | |
260 | u16 ext_ability = 0; | |
261 | ||
262 | hw->phy.ops.identify(hw); | |
263 | ||
264 | hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, | |
265 | &ext_ability); | |
266 | if (ext_ability & MDIO_PMA_EXTABLE_10GBT) | |
267 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; | |
268 | if (ext_ability & MDIO_PMA_EXTABLE_1000BT) | |
269 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; | |
270 | if (ext_ability & MDIO_PMA_EXTABLE_100BTX) | |
271 | physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; | |
272 | ||
273 | return physical_layer; | |
274 | } | |
275 | ||
276 | /** | |
77ed18f3 ET |
277 | * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params |
278 | * @hw: pointer to hardware structure | |
279 | * | |
280 | * Initializes the EEPROM parameters ixgbe_eeprom_info within the | |
281 | * ixgbe_hw struct in order to set up EEPROM access. | |
fe15e8e1 | 282 | **/ |
b93a2226 | 283 | static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) |
fe15e8e1 DS |
284 | { |
285 | struct ixgbe_eeprom_info *eeprom = &hw->eeprom; | |
286 | u32 eec; | |
287 | u16 eeprom_size; | |
288 | ||
289 | if (eeprom->type == ixgbe_eeprom_uninitialized) { | |
290 | eeprom->semaphore_delay = 10; | |
291 | eeprom->type = ixgbe_flash; | |
292 | ||
293 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
294 | eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> | |
295 | IXGBE_EEC_SIZE_SHIFT); | |
296 | eeprom->word_size = 1 << (eeprom_size + | |
297 | IXGBE_EEPROM_WORD_SIZE_SHIFT); | |
298 | ||
299 | hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", | |
77ed18f3 | 300 | eeprom->type, eeprom->word_size); |
fe15e8e1 DS |
301 | } |
302 | ||
303 | return 0; | |
304 | } | |
305 | ||
306 | /** | |
307 | * ixgbe_read_eerd_X540 - Read EEPROM word using EERD | |
308 | * @hw: pointer to hardware structure | |
309 | * @offset: offset of word in the EEPROM to read | |
310 | * @data: word read from the EERPOM | |
311 | **/ | |
b93a2226 | 312 | static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) |
fe15e8e1 DS |
313 | { |
314 | s32 status; | |
315 | ||
5e655105 | 316 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) |
fe15e8e1 DS |
317 | status = ixgbe_read_eerd_generic(hw, offset, data); |
318 | else | |
319 | status = IXGBE_ERR_SWFW_SYNC; | |
320 | ||
321 | ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM); | |
322 | return status; | |
323 | } | |
324 | ||
325 | /** | |
eb9c3e3e ET |
326 | * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR |
327 | * @hw: pointer to hardware structure | |
328 | * @offset: offset of word in the EEPROM to write | |
329 | * @data: word write to the EEPROM | |
fe15e8e1 | 330 | * |
eb9c3e3e | 331 | * Write a 16 bit word to the EEPROM using the EEWR register. |
fe15e8e1 | 332 | **/ |
b93a2226 | 333 | static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) |
fe15e8e1 | 334 | { |
eb9c3e3e | 335 | s32 status = 0; |
fe15e8e1 | 336 | |
eb9c3e3e ET |
337 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) |
338 | status = ixgbe_write_eewr_generic(hw, offset, data); | |
339 | else | |
fe15e8e1 | 340 | status = IXGBE_ERR_SWFW_SYNC; |
fe15e8e1 | 341 | |
eb9c3e3e | 342 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); |
fe15e8e1 DS |
343 | return status; |
344 | } | |
345 | ||
346 | /** | |
eb9c3e3e ET |
347 | * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum |
348 | * | |
349 | * This function does not use synchronization for EERD and EEWR. It can | |
350 | * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. | |
351 | * | |
352 | * @hw: pointer to hardware structure | |
fe15e8e1 DS |
353 | **/ |
354 | static u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) | |
355 | { | |
356 | u16 i; | |
357 | u16 j; | |
358 | u16 checksum = 0; | |
359 | u16 length = 0; | |
360 | u16 pointer = 0; | |
361 | u16 word = 0; | |
362 | ||
eb9c3e3e ET |
363 | /* |
364 | * Do not use hw->eeprom.ops.read because we do not want to take | |
365 | * the synchronization semaphores here. Instead use | |
366 | * ixgbe_read_eerd_generic | |
367 | */ | |
368 | ||
fe15e8e1 DS |
369 | /* Include 0x0-0x3F in the checksum */ |
370 | for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { | |
eb9c3e3e | 371 | if (ixgbe_read_eerd_generic(hw, i, &word) != 0) { |
fe15e8e1 DS |
372 | hw_dbg(hw, "EEPROM read failed\n"); |
373 | break; | |
374 | } | |
375 | checksum += word; | |
376 | } | |
377 | ||
378 | /* | |
379 | * Include all data from pointers 0x3, 0x6-0xE. This excludes the | |
380 | * FW, PHY module, and PCIe Expansion/Option ROM pointers. | |
381 | */ | |
382 | for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { | |
383 | if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) | |
384 | continue; | |
385 | ||
eb9c3e3e | 386 | if (ixgbe_read_eerd_generic(hw, i, &pointer) != 0) { |
fe15e8e1 DS |
387 | hw_dbg(hw, "EEPROM read failed\n"); |
388 | break; | |
389 | } | |
390 | ||
391 | /* Skip pointer section if the pointer is invalid. */ | |
392 | if (pointer == 0xFFFF || pointer == 0 || | |
393 | pointer >= hw->eeprom.word_size) | |
394 | continue; | |
395 | ||
eb9c3e3e | 396 | if (ixgbe_read_eerd_generic(hw, pointer, &length) != 0) { |
fe15e8e1 DS |
397 | hw_dbg(hw, "EEPROM read failed\n"); |
398 | break; | |
399 | } | |
400 | ||
401 | /* Skip pointer section if length is invalid. */ | |
402 | if (length == 0xFFFF || length == 0 || | |
403 | (pointer + length) >= hw->eeprom.word_size) | |
404 | continue; | |
405 | ||
406 | for (j = pointer+1; j <= pointer+length; j++) { | |
eb9c3e3e | 407 | if (ixgbe_read_eerd_generic(hw, j, &word) != 0) { |
fe15e8e1 DS |
408 | hw_dbg(hw, "EEPROM read failed\n"); |
409 | break; | |
410 | } | |
411 | checksum += word; | |
412 | } | |
413 | } | |
414 | ||
415 | checksum = (u16)IXGBE_EEPROM_SUM - checksum; | |
416 | ||
417 | return checksum; | |
418 | } | |
419 | ||
eb9c3e3e ET |
420 | /** |
421 | * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum | |
422 | * @hw: pointer to hardware structure | |
423 | * @checksum_val: calculated checksum | |
424 | * | |
425 | * Performs checksum calculation and validates the EEPROM checksum. If the | |
426 | * caller does not need checksum_val, the value can be NULL. | |
427 | **/ | |
428 | static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, | |
429 | u16 *checksum_val) | |
430 | { | |
431 | s32 status; | |
432 | u16 checksum; | |
433 | u16 read_checksum = 0; | |
434 | ||
435 | /* | |
436 | * Read the first word from the EEPROM. If this times out or fails, do | |
437 | * not continue or we could be in for a very long wait while every | |
438 | * EEPROM read fails | |
439 | */ | |
440 | status = hw->eeprom.ops.read(hw, 0, &checksum); | |
441 | ||
442 | if (status != 0) { | |
443 | hw_dbg(hw, "EEPROM read failed\n"); | |
444 | goto out; | |
445 | } | |
446 | ||
447 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { | |
448 | checksum = hw->eeprom.ops.calc_checksum(hw); | |
449 | ||
450 | /* | |
451 | * Do not use hw->eeprom.ops.read because we do not want to take | |
452 | * the synchronization semaphores twice here. | |
453 | */ | |
454 | ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, | |
455 | &read_checksum); | |
456 | ||
457 | /* | |
458 | * Verify read checksum from EEPROM is the same as | |
459 | * calculated checksum | |
460 | */ | |
461 | if (read_checksum != checksum) | |
462 | status = IXGBE_ERR_EEPROM_CHECKSUM; | |
463 | ||
464 | /* If the user cares, return the calculated checksum */ | |
465 | if (checksum_val) | |
466 | *checksum_val = checksum; | |
467 | } else { | |
468 | status = IXGBE_ERR_SWFW_SYNC; | |
469 | } | |
470 | ||
471 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
472 | out: | |
473 | return status; | |
474 | } | |
475 | ||
fe15e8e1 DS |
476 | /** |
477 | * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash | |
478 | * @hw: pointer to hardware structure | |
479 | * | |
480 | * After writing EEPROM to shadow RAM using EEWR register, software calculates | |
481 | * checksum and updates the EEPROM and instructs the hardware to update | |
482 | * the flash. | |
483 | **/ | |
b93a2226 | 484 | static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) |
fe15e8e1 DS |
485 | { |
486 | s32 status; | |
eb9c3e3e | 487 | u16 checksum; |
fe15e8e1 | 488 | |
eb9c3e3e ET |
489 | /* |
490 | * Read the first word from the EEPROM. If this times out or fails, do | |
491 | * not continue or we could be in for a very long wait while every | |
492 | * EEPROM read fails | |
493 | */ | |
494 | status = hw->eeprom.ops.read(hw, 0, &checksum); | |
495 | ||
496 | if (status != 0) | |
497 | hw_dbg(hw, "EEPROM read failed\n"); | |
498 | ||
499 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { | |
500 | checksum = hw->eeprom.ops.calc_checksum(hw); | |
fe15e8e1 | 501 | |
eb9c3e3e ET |
502 | /* |
503 | * Do not use hw->eeprom.ops.write because we do not want to | |
504 | * take the synchronization semaphores twice here. | |
505 | */ | |
506 | status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, | |
507 | checksum); | |
508 | ||
509 | if (status == 0) | |
fe15e8e1 | 510 | status = ixgbe_update_flash_X540(hw); |
eb9c3e3e ET |
511 | else |
512 | status = IXGBE_ERR_SWFW_SYNC; | |
513 | } | |
514 | ||
515 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
fe15e8e1 DS |
516 | |
517 | return status; | |
518 | } | |
519 | ||
520 | /** | |
521 | * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device | |
522 | * @hw: pointer to hardware structure | |
523 | * | |
524 | * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy | |
525 | * EEPROM from shadow RAM to the flash device. | |
526 | **/ | |
527 | static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) | |
528 | { | |
529 | u32 flup; | |
530 | s32 status = IXGBE_ERR_EEPROM; | |
531 | ||
532 | status = ixgbe_poll_flash_update_done_X540(hw); | |
533 | if (status == IXGBE_ERR_EEPROM) { | |
534 | hw_dbg(hw, "Flash update time out\n"); | |
535 | goto out; | |
536 | } | |
537 | ||
538 | flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP; | |
539 | IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); | |
540 | ||
541 | status = ixgbe_poll_flash_update_done_X540(hw); | |
2ea5ea5f | 542 | if (status == 0) |
fe15e8e1 DS |
543 | hw_dbg(hw, "Flash update complete\n"); |
544 | else | |
545 | hw_dbg(hw, "Flash update time out\n"); | |
546 | ||
547 | if (hw->revision_id == 0) { | |
548 | flup = IXGBE_READ_REG(hw, IXGBE_EEC); | |
549 | ||
550 | if (flup & IXGBE_EEC_SEC1VAL) { | |
551 | flup |= IXGBE_EEC_FLUP; | |
552 | IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); | |
553 | } | |
554 | ||
555 | status = ixgbe_poll_flash_update_done_X540(hw); | |
2ea5ea5f | 556 | if (status == 0) |
fe15e8e1 DS |
557 | hw_dbg(hw, "Flash update complete\n"); |
558 | else | |
559 | hw_dbg(hw, "Flash update time out\n"); | |
fe15e8e1 DS |
560 | } |
561 | out: | |
562 | return status; | |
563 | } | |
564 | ||
565 | /** | |
566 | * ixgbe_poll_flash_update_done_X540 - Poll flash update status | |
567 | * @hw: pointer to hardware structure | |
568 | * | |
569 | * Polls the FLUDONE (bit 26) of the EEC Register to determine when the | |
570 | * flash update is done. | |
571 | **/ | |
572 | static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) | |
573 | { | |
574 | u32 i; | |
575 | u32 reg; | |
576 | s32 status = IXGBE_ERR_EEPROM; | |
577 | ||
578 | for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { | |
579 | reg = IXGBE_READ_REG(hw, IXGBE_EEC); | |
580 | if (reg & IXGBE_EEC_FLUDONE) { | |
581 | status = 0; | |
582 | break; | |
583 | } | |
584 | udelay(5); | |
585 | } | |
586 | return status; | |
587 | } | |
588 | ||
589 | /** | |
590 | * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore | |
591 | * @hw: pointer to hardware structure | |
592 | * @mask: Mask to specify which semaphore to acquire | |
593 | * | |
594 | * Acquires the SWFW semaphore thought the SW_FW_SYNC register for | |
595 | * the specified function (CSR, PHY0, PHY1, NVM, Flash) | |
596 | **/ | |
597 | static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) | |
598 | { | |
599 | u32 swfw_sync; | |
600 | u32 swmask = mask; | |
601 | u32 fwmask = mask << 5; | |
602 | u32 hwmask = 0; | |
603 | u32 timeout = 200; | |
604 | u32 i; | |
605 | ||
606 | if (swmask == IXGBE_GSSR_EEP_SM) | |
607 | hwmask = IXGBE_GSSR_FLASH_SM; | |
608 | ||
609 | for (i = 0; i < timeout; i++) { | |
610 | /* | |
611 | * SW NVM semaphore bit is used for access to all | |
612 | * SW_FW_SYNC bits (not just NVM) | |
613 | */ | |
614 | if (ixgbe_get_swfw_sync_semaphore(hw)) | |
615 | return IXGBE_ERR_SWFW_SYNC; | |
616 | ||
617 | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); | |
618 | if (!(swfw_sync & (fwmask | swmask | hwmask))) { | |
619 | swfw_sync |= swmask; | |
620 | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); | |
621 | ixgbe_release_swfw_sync_semaphore(hw); | |
622 | break; | |
623 | } else { | |
624 | /* | |
625 | * Firmware currently using resource (fwmask), | |
626 | * hardware currently using resource (hwmask), | |
627 | * or other software thread currently using | |
628 | * resource (swmask) | |
629 | */ | |
630 | ixgbe_release_swfw_sync_semaphore(hw); | |
032b4325 | 631 | usleep_range(5000, 10000); |
fe15e8e1 DS |
632 | } |
633 | } | |
634 | ||
635 | /* | |
636 | * If the resource is not released by the FW/HW the SW can assume that | |
637 | * the FW/HW malfunctions. In that case the SW should sets the | |
638 | * SW bit(s) of the requested resource(s) while ignoring the | |
639 | * corresponding FW/HW bits in the SW_FW_SYNC register. | |
640 | */ | |
641 | if (i >= timeout) { | |
642 | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); | |
643 | if (swfw_sync & (fwmask | hwmask)) { | |
644 | if (ixgbe_get_swfw_sync_semaphore(hw)) | |
645 | return IXGBE_ERR_SWFW_SYNC; | |
646 | ||
647 | swfw_sync |= swmask; | |
648 | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); | |
649 | ixgbe_release_swfw_sync_semaphore(hw); | |
650 | } | |
651 | } | |
652 | ||
032b4325 | 653 | usleep_range(5000, 10000); |
fe15e8e1 DS |
654 | return 0; |
655 | } | |
656 | ||
657 | /** | |
658 | * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore | |
659 | * @hw: pointer to hardware structure | |
660 | * @mask: Mask to specify which semaphore to release | |
661 | * | |
25985edc | 662 | * Releases the SWFW semaphore through the SW_FW_SYNC register |
fe15e8e1 DS |
663 | * for the specified function (CSR, PHY0, PHY1, EVM, Flash) |
664 | **/ | |
665 | static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) | |
666 | { | |
667 | u32 swfw_sync; | |
668 | u32 swmask = mask; | |
669 | ||
670 | ixgbe_get_swfw_sync_semaphore(hw); | |
671 | ||
672 | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); | |
673 | swfw_sync &= ~swmask; | |
674 | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); | |
675 | ||
676 | ixgbe_release_swfw_sync_semaphore(hw); | |
032b4325 | 677 | usleep_range(5000, 10000); |
fe15e8e1 DS |
678 | } |
679 | ||
680 | /** | |
681 | * ixgbe_get_nvm_semaphore - Get hardware semaphore | |
682 | * @hw: pointer to hardware structure | |
683 | * | |
684 | * Sets the hardware semaphores so SW/FW can gain control of shared resources | |
685 | **/ | |
686 | static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) | |
687 | { | |
688 | s32 status = IXGBE_ERR_EEPROM; | |
689 | u32 timeout = 2000; | |
690 | u32 i; | |
691 | u32 swsm; | |
692 | ||
693 | /* Get SMBI software semaphore between device drivers first */ | |
694 | for (i = 0; i < timeout; i++) { | |
695 | /* | |
696 | * If the SMBI bit is 0 when we read it, then the bit will be | |
697 | * set and we have the semaphore | |
698 | */ | |
699 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | |
700 | if (!(swsm & IXGBE_SWSM_SMBI)) { | |
701 | status = 0; | |
702 | break; | |
703 | } | |
704 | udelay(50); | |
705 | } | |
706 | ||
707 | /* Now get the semaphore between SW/FW through the REGSMP bit */ | |
708 | if (status) { | |
709 | for (i = 0; i < timeout; i++) { | |
710 | swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); | |
711 | if (!(swsm & IXGBE_SWFW_REGSMP)) | |
712 | break; | |
713 | ||
714 | udelay(50); | |
715 | } | |
716 | } else { | |
717 | hw_dbg(hw, "Software semaphore SMBI between device drivers " | |
718 | "not granted.\n"); | |
719 | } | |
720 | ||
721 | return status; | |
722 | } | |
723 | ||
724 | /** | |
725 | * ixgbe_release_nvm_semaphore - Release hardware semaphore | |
726 | * @hw: pointer to hardware structure | |
727 | * | |
728 | * This function clears hardware semaphore bits. | |
729 | **/ | |
730 | static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) | |
731 | { | |
732 | u32 swsm; | |
733 | ||
734 | /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ | |
735 | ||
736 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | |
737 | swsm &= ~IXGBE_SWSM_SMBI; | |
738 | IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); | |
739 | ||
740 | swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); | |
741 | swsm &= ~IXGBE_SWFW_REGSMP; | |
742 | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm); | |
743 | ||
744 | IXGBE_WRITE_FLUSH(hw); | |
745 | } | |
746 | ||
747 | static struct ixgbe_mac_operations mac_ops_X540 = { | |
748 | .init_hw = &ixgbe_init_hw_generic, | |
749 | .reset_hw = &ixgbe_reset_hw_X540, | |
7184b7cf | 750 | .start_hw = &ixgbe_start_hw_X540, |
fe15e8e1 DS |
751 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, |
752 | .get_media_type = &ixgbe_get_media_type_X540, | |
753 | .get_supported_physical_layer = | |
754 | &ixgbe_get_supported_physical_layer_X540, | |
755 | .enable_rx_dma = &ixgbe_enable_rx_dma_generic, | |
756 | .get_mac_addr = &ixgbe_get_mac_addr_generic, | |
757 | .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, | |
b776d104 | 758 | .get_device_caps = &ixgbe_get_device_caps_generic, |
fe15e8e1 DS |
759 | .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, |
760 | .stop_adapter = &ixgbe_stop_adapter_generic, | |
761 | .get_bus_info = &ixgbe_get_bus_info_generic, | |
762 | .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, | |
763 | .read_analog_reg8 = NULL, | |
764 | .write_analog_reg8 = NULL, | |
765 | .setup_link = &ixgbe_setup_mac_link_X540, | |
766 | .check_link = &ixgbe_check_mac_link_generic, | |
767 | .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, | |
768 | .led_on = &ixgbe_led_on_generic, | |
769 | .led_off = &ixgbe_led_off_generic, | |
770 | .blink_led_start = &ixgbe_blink_led_start_generic, | |
771 | .blink_led_stop = &ixgbe_blink_led_stop_generic, | |
772 | .set_rar = &ixgbe_set_rar_generic, | |
773 | .clear_rar = &ixgbe_clear_rar_generic, | |
774 | .set_vmdq = &ixgbe_set_vmdq_generic, | |
775 | .clear_vmdq = &ixgbe_clear_vmdq_generic, | |
776 | .init_rx_addrs = &ixgbe_init_rx_addrs_generic, | |
fe15e8e1 DS |
777 | .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, |
778 | .enable_mc = &ixgbe_enable_mc_generic, | |
779 | .disable_mc = &ixgbe_disable_mc_generic, | |
780 | .clear_vfta = &ixgbe_clear_vfta_generic, | |
781 | .set_vfta = &ixgbe_set_vfta_generic, | |
782 | .fc_enable = &ixgbe_fc_enable_generic, | |
783 | .init_uta_tables = &ixgbe_init_uta_tables_generic, | |
784 | .setup_sfp = NULL, | |
3377eba7 GR |
785 | .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, |
786 | .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, | |
5e655105 DS |
787 | .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, |
788 | .release_swfw_sync = &ixgbe_release_swfw_sync_X540, | |
fe15e8e1 DS |
789 | }; |
790 | ||
791 | static struct ixgbe_eeprom_operations eeprom_ops_X540 = { | |
792 | .init_params = &ixgbe_init_eeprom_params_X540, | |
793 | .read = &ixgbe_read_eerd_X540, | |
794 | .write = &ixgbe_write_eewr_X540, | |
795 | .calc_checksum = &ixgbe_calc_eeprom_checksum_X540, | |
eb9c3e3e | 796 | .validate_checksum = &ixgbe_validate_eeprom_checksum_X540, |
fe15e8e1 DS |
797 | .update_checksum = &ixgbe_update_eeprom_checksum_X540, |
798 | }; | |
799 | ||
800 | static struct ixgbe_phy_operations phy_ops_X540 = { | |
801 | .identify = &ixgbe_identify_phy_generic, | |
802 | .identify_sfp = &ixgbe_identify_sfp_module_generic, | |
803 | .init = NULL, | |
b60c5dd3 | 804 | .reset = NULL, |
fe15e8e1 DS |
805 | .read_reg = &ixgbe_read_phy_reg_generic, |
806 | .write_reg = &ixgbe_write_phy_reg_generic, | |
807 | .setup_link = &ixgbe_setup_phy_link_generic, | |
808 | .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, | |
809 | .read_i2c_byte = &ixgbe_read_i2c_byte_generic, | |
810 | .write_i2c_byte = &ixgbe_write_i2c_byte_generic, | |
811 | .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, | |
812 | .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, | |
813 | .check_overtemp = &ixgbe_tn_check_overtemp, | |
814 | }; | |
815 | ||
816 | struct ixgbe_info ixgbe_X540_info = { | |
817 | .mac = ixgbe_mac_X540, | |
818 | .get_invariants = &ixgbe_get_invariants_X540, | |
819 | .mac_ops = &mac_ops_X540, | |
820 | .eeprom_ops = &eeprom_ops_X540, | |
821 | .phy_ops = &phy_ops_X540, | |
822 | .mbx_ops = &mbx_ops_generic, | |
823 | }; |