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jme: Fix VLAN memory leak
[deliverable/linux.git] / drivers / net / jme.c
CommitLineData
95252236
GFT		 1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
95252236
GFT		 24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/pci.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/ethtool.h>
30#include <linux/mii.h>
31#include <linux/crc32.h>
32#include <linux/delay.h>
33#include <linux/spinlock.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/ipv6.h>
37#include <linux/tcp.h>
38#include <linux/udp.h>
39#include <linux/if_vlan.h>
b7c6bfb7 40#include <net/ip6_checksum.h>
95252236
GFT		 41#include "jme.h"
42
43static int force_pseudohp = -1;
44static int no_pseudohp = -1;
45static int no_extplug = -1;
46module_param(force_pseudohp, int, 0);
47MODULE_PARM_DESC(force_pseudohp,
48 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49module_param(no_pseudohp, int, 0);
50MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51module_param(no_extplug, int, 0);
52MODULE_PARM_DESC(no_extplug,
53 "Do not use external plug signal for pseudo hot-plug.");
54
55static int
56jme_mdio_read(struct net_device *netdev, int phy, int reg)
57{
58 struct jme_adapter *jme = netdev_priv(netdev);
59 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
60
61read_again:
62 jwrite32(jme, JME_SMI, SMI_OP_REQ |
63 smi_phy_addr(phy) |
64 smi_reg_addr(reg));
65
66 wmb();
67 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
68 udelay(20);
69 val = jread32(jme, JME_SMI);
70 if ((val & SMI_OP_REQ) == 0)
71 break;
72 }
73
74 if (i == 0) {
75 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
76 return 0;
77 }
78
79 if (again--)
80 goto read_again;
81
82 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
83}
84
85static void
86jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
88{
89 struct jme_adapter *jme = netdev_priv(netdev);
90 int i;
91
92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
95
96 wmb();
97 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
98 udelay(20);
99 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
100 break;
101 }
102
103 if (i == 0)
104 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
105
106 return;
107}
108
109static inline void
110jme_reset_phy_processor(struct jme_adapter *jme)
111{
112 u32 val;
113
114 jme_mdio_write(jme->dev,
115 jme->mii_if.phy_id,
116 MII_ADVERTISE, ADVERTISE_ALL |
117 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
118
119 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
120 jme_mdio_write(jme->dev,
121 jme->mii_if.phy_id,
122 MII_CTRL1000,
123 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
124
125 val = jme_mdio_read(jme->dev,
126 jme->mii_if.phy_id,
127 MII_BMCR);
128
129 jme_mdio_write(jme->dev,
130 jme->mii_if.phy_id,
131 MII_BMCR, val | BMCR_RESET);
132
133 return;
134}
135
136static void
137jme_setup_wakeup_frame(struct jme_adapter *jme,
138 u32 *mask, u32 crc, int fnr)
139{
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161}
162
163static inline void
164jme_reset_mac_processor(struct jme_adapter *jme)
165{
166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
168 u32 gpreg0;
169 int i;
170
171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
172 udelay(2);
173 jwrite32(jme, JME_GHC, jme->reg_ghc);
174
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
183
184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
187 jme_setup_wakeup_frame(jme, mask, crc, i);
188 if (jme->fpgaver)
189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190 else
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
a821ebe5 193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
95252236
GFT		 194}
195
196static inline void
197jme_reset_ghc_speed(struct jme_adapter *jme)
198{
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
201}
202
203static inline void
204jme_clear_pm(struct jme_adapter *jme)
205{
206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207 pci_set_power_state(jme->pdev, PCI_D0);
208 pci_enable_wake(jme->pdev, PCI_D0, false);
209}
210
211static int
212jme_reload_eeprom(struct jme_adapter *jme)
213{
214 u32 val;
215 int i;
216
217 val = jread32(jme, JME_SMBCSR);
218
219 if (val & SMBCSR_EEPROMD) {
220 val |= SMBCSR_CNACK;
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
224 mdelay(12);
225
226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
227 mdelay(1);
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
229 break;
230 }
231
232 if (i == 0) {
233 jeprintk(jme->pdev, "eeprom reload timeout\n");
234 return -EIO;
235 }
236 }
237
238 return 0;
239}
240
241static void
242jme_load_macaddr(struct net_device *netdev)
243{
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
246 u32 val;
247
248 spin_lock_bh(&jme->macaddr_lock);
249 val = jread32(jme, JME_RXUMA_LO);
250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
254 val = jread32(jme, JME_RXUMA_HI);
255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
259}
260
261static inline void
262jme_set_rx_pcc(struct jme_adapter *jme, int p)
263{
264 switch (p) {
265 case PCC_OFF:
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
269 break;
270 case PCC_P1:
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
274 break;
275 case PCC_P2:
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
279 break;
280 case PCC_P3:
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
284 break;
285 default:
286 break;
287 }
288 wmb();
289
290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
f8502ce4 291 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
95252236
GFT		 292}
293
294static void
295jme_start_irq(struct jme_adapter *jme)
296{
297 register struct dynpcc_info *dpi = &(jme->dpi);
298
299 jme_set_rx_pcc(jme, PCC_P1);
300 dpi->cur = PCC_P1;
301 dpi->attempt = PCC_P1;
302 dpi->cnt = 0;
303
304 jwrite32(jme, JME_PCCTX,
305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
307 PCCTXQ0_EN
308 );
309
310 /*
311 * Enable Interrupts
312 */
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
314}
315
316static inline void
317jme_stop_irq(struct jme_adapter *jme)
318{
319 /*
320 * Disable Interrupts
321 */
322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
323}
324
95252236
GFT		 325static u32
326jme_linkstat_from_phy(struct jme_adapter *jme)
327{
328 u32 phylink, bmsr;
329
330 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
331 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
332 if (bmsr & BMSR_ANCOMP)
333 phylink |= PHY_LINK_AUTONEG_COMPLETE;
334
335 return phylink;
336}
337
338static inline void
339jme_set_phyfifoa(struct jme_adapter *jme)
340{
341 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
342}
343
344static inline void
345jme_set_phyfifob(struct jme_adapter *jme)
346{
347 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
348}
349
350static int
351jme_check_link(struct net_device *netdev, int testonly)
352{
353 struct jme_adapter *jme = netdev_priv(netdev);
a821ebe5 354 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
95252236
GFT		 355 char linkmsg[64];
356 int rc = 0;
357
358 linkmsg[0] = '\0';
359
360 if (jme->fpgaver)
361 phylink = jme_linkstat_from_phy(jme);
362 else
363 phylink = jread32(jme, JME_PHY_LINK);
364
365 if (phylink & PHY_LINK_UP) {
366 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
367 /*
368 * If we did not enable AN
369 * Speed/Duplex Info should be obtained from SMI
370 */
371 phylink = PHY_LINK_UP;
372
373 bmcr = jme_mdio_read(jme->dev,
374 jme->mii_if.phy_id,
375 MII_BMCR);
376
377 phylink |= ((bmcr & BMCR_SPEED1000) &&
378 (bmcr & BMCR_SPEED100) == 0) ?
379 PHY_LINK_SPEED_1000M :
380 (bmcr & BMCR_SPEED100) ?
381 PHY_LINK_SPEED_100M :
382 PHY_LINK_SPEED_10M;
383
384 phylink |= (bmcr & BMCR_FULLDPLX) ?
385 PHY_LINK_DUPLEX : 0;
386
387 strcat(linkmsg, "Forced: ");
388 } else {
389 /*
390 * Keep polling for speed/duplex resolve complete
391 */
392 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
393 --cnt) {
394
395 udelay(1);
396
397 if (jme->fpgaver)
398 phylink = jme_linkstat_from_phy(jme);
399 else
400 phylink = jread32(jme, JME_PHY_LINK);
401 }
402 if (!cnt)
403 jeprintk(jme->pdev,
404 "Waiting speed resolve timeout.\n");
405
406 strcat(linkmsg, "ANed: ");
407 }
408
409 if (jme->phylink == phylink) {
410 rc = 1;
411 goto out;
412 }
413 if (testonly)
414 goto out;
415
416 jme->phylink = phylink;
417
eb352b83
GFT		 418 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
419 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
420 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
95252236
GFT		 421 switch (phylink & PHY_LINK_SPEED_MASK) {
422 case PHY_LINK_SPEED_10M:
4f40bf46 423 ghc |= GHC_SPEED_10M |
424 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
95252236 425 strcat(linkmsg, "10 Mbps, ");
95252236
GFT		 426 break;
427 case PHY_LINK_SPEED_100M:
4f40bf46 428 ghc |= GHC_SPEED_100M |
429 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
95252236 430 strcat(linkmsg, "100 Mbps, ");
95252236
GFT		 431 break;
432 case PHY_LINK_SPEED_1000M:
4f40bf46 433 ghc |= GHC_SPEED_1000M |
434 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
95252236 435 strcat(linkmsg, "1000 Mbps, ");
95252236
GFT		 436 break;
437 default:
438 break;
439 }
95252236
GFT		 440
441 if (phylink & PHY_LINK_DUPLEX) {
442 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
a821ebe5 443 ghc |= GHC_DPX;
95252236
GFT		 444 } else {
445 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
446 TXMCS_BACKOFF |
447 TXMCS_CARRIERSENSE |
448 TXMCS_COLLISION);
449 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
450 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
451 TXTRHD_TXREN |
452 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
453 }
a821ebe5
GFT		 454
455 gpreg1 = GPREG1_DEFAULT;
456 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
457 if (!(phylink & PHY_LINK_DUPLEX))
458 gpreg1 |= GPREG1_HALFMODEPATCH;
459 switch (phylink & PHY_LINK_SPEED_MASK) {
460 case PHY_LINK_SPEED_10M:
461 jme_set_phyfifoa(jme);
462 gpreg1 |= GPREG1_RSSPATCH;
463 break;
464 case PHY_LINK_SPEED_100M:
465 jme_set_phyfifob(jme);
466 gpreg1 |= GPREG1_RSSPATCH;
467 break;
468 case PHY_LINK_SPEED_1000M:
469 jme_set_phyfifoa(jme);
470 break;
471 default:
472 break;
473 }
474 }
95252236 475
4f40bf46 476 jwrite32(jme, JME_GPREG1, gpreg1);
95252236 477 jwrite32(jme, JME_GHC, ghc);
4f40bf46 478 jme->reg_ghc = ghc;
95252236 479
4f40bf46 480 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
481 "Full-Duplex, " :
482 "Half-Duplex, ");
483 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
484 "MDI-X" :
485 "MDI");
f8502ce4 486 netif_info(jme, link, jme->dev, "Link is up at %s.\n", linkmsg);
95252236
GFT		 487 netif_carrier_on(netdev);
488 } else {
489 if (testonly)
490 goto out;
491
f8502ce4 492 netif_info(jme, link, jme->dev, "Link is down.\n");
95252236
GFT		 493 jme->phylink = 0;
494 netif_carrier_off(netdev);
495 }
496
497out:
498 return rc;
499}
500
501static int
502jme_setup_tx_resources(struct jme_adapter *jme)
503{
504 struct jme_ring *txring = &(jme->txring[0]);
505
506 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
507 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
508 &(txring->dmaalloc),
509 GFP_ATOMIC);
510
47bd10d1
GFT		 511 if (!txring->alloc)
512 goto err_set_null;
95252236
GFT		 513
514 /*
515 * 16 Bytes align
516 */
517 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
518 RING_DESC_ALIGN);
519 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
520 txring->next_to_use = 0;
521 atomic_set(&txring->next_to_clean, 0);
522 atomic_set(&txring->nr_free, jme->tx_ring_size);
523
47bd10d1
GFT		 524 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
525 jme->tx_ring_size, GFP_ATOMIC);
526 if (unlikely(!(txring->bufinf)))
527 goto err_free_txring;
528
95252236
GFT		 529 /*
530 * Initialize Transmit Descriptors
531 */
532 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
533 memset(txring->bufinf, 0,
534 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
535
536 return 0;
47bd10d1
GFT		 537
538err_free_txring:
539 dma_free_coherent(&(jme->pdev->dev),
540 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
541 txring->alloc,
542 txring->dmaalloc);
543
544err_set_null:
545 txring->desc = NULL;
546 txring->dmaalloc = 0;
547 txring->dma = 0;
548 txring->bufinf = NULL;
549
550 return -ENOMEM;
95252236
GFT		 551}
552
553static void
554jme_free_tx_resources(struct jme_adapter *jme)
555{
556 int i;
557 struct jme_ring *txring = &(jme->txring[0]);
eacf69a1 558 struct jme_buffer_info *txbi;
95252236
GFT		 559
560 if (txring->alloc) {
47bd10d1
GFT		 561 if (txring->bufinf) {
562 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
563 txbi = txring->bufinf + i;
564 if (txbi->skb) {
565 dev_kfree_skb(txbi->skb);
566 txbi->skb = NULL;
567 }
568 txbi->mapping = 0;
569 txbi->len = 0;
570 txbi->nr_desc = 0;
571 txbi->start_xmit = 0;
95252236 572 }
47bd10d1 573 kfree(txring->bufinf);
95252236
GFT		 574 }
575
576 dma_free_coherent(&(jme->pdev->dev),
577 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
578 txring->alloc,
579 txring->dmaalloc);
580
581 txring->alloc = NULL;
582 txring->desc = NULL;
583 txring->dmaalloc = 0;
584 txring->dma = 0;
47bd10d1 585 txring->bufinf = NULL;
95252236
GFT		 586 }
587 txring->next_to_use = 0;
588 atomic_set(&txring->next_to_clean, 0);
589 atomic_set(&txring->nr_free, 0);
95252236
GFT		 590}
591
592static inline void
593jme_enable_tx_engine(struct jme_adapter *jme)
594{
595 /*
596 * Select Queue 0
597 */
598 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
599 wmb();
600
601 /*
602 * Setup TX Queue 0 DMA Bass Address
603 */
604 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
605 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
606 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
607
608 /*
609 * Setup TX Descptor Count
610 */
611 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
612
613 /*
614 * Enable TX Engine
615 */
616 wmb();
617 jwrite32(jme, JME_TXCS, jme->reg_txcs |
618 TXCS_SELECT_QUEUE0 |
619 TXCS_ENABLE);
620
621}
622
623static inline void
624jme_restart_tx_engine(struct jme_adapter *jme)
625{
626 /*
627 * Restart TX Engine
628 */
629 jwrite32(jme, JME_TXCS, jme->reg_txcs |
630 TXCS_SELECT_QUEUE0 |
631 TXCS_ENABLE);
632}
633
634static inline void
635jme_disable_tx_engine(struct jme_adapter *jme)
636{
637 int i;
638 u32 val;
639
640 /*
641 * Disable TX Engine
642 */
643 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
644 wmb();
645
646 val = jread32(jme, JME_TXCS);
647 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
648 mdelay(1);
649 val = jread32(jme, JME_TXCS);
650 rmb();
651 }
652
653 if (!i)
654 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
655}
656
657static void
658jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
659{
eacf69a1 660 struct jme_ring *rxring = &(jme->rxring[0]);
95252236
GFT		 661 register struct rxdesc *rxdesc = rxring->desc;
662 struct jme_buffer_info *rxbi = rxring->bufinf;
663 rxdesc += i;
664 rxbi += i;
665
666 rxdesc->dw[0] = 0;
667 rxdesc->dw[1] = 0;
668 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
669 rxdesc->desc1.bufaddrl = cpu_to_le32(
670 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
671 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
672 if (jme->dev->features & NETIF_F_HIGHDMA)
673 rxdesc->desc1.flags = RXFLAG_64BIT;
674 wmb();
675 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
676}
677
678static int
679jme_make_new_rx_buf(struct jme_adapter *jme, int i)
680{
681 struct jme_ring *rxring = &(jme->rxring[0]);
682 struct jme_buffer_info *rxbi = rxring->bufinf + i;
683 struct sk_buff *skb;
684
685 skb = netdev_alloc_skb(jme->dev,
686 jme->dev->mtu + RX_EXTRA_LEN);
687 if (unlikely(!skb))
688 return -ENOMEM;
689
690 rxbi->skb = skb;
691 rxbi->len = skb_tailroom(skb);
692 rxbi->mapping = pci_map_page(jme->pdev,
693 virt_to_page(skb->data),
694 offset_in_page(skb->data),
695 rxbi->len,
696 PCI_DMA_FROMDEVICE);
697
698 return 0;
699}
700
701static void
702jme_free_rx_buf(struct jme_adapter *jme, int i)
703{
704 struct jme_ring *rxring = &(jme->rxring[0]);
705 struct jme_buffer_info *rxbi = rxring->bufinf;
706 rxbi += i;
707
708 if (rxbi->skb) {
709 pci_unmap_page(jme->pdev,
710 rxbi->mapping,
711 rxbi->len,
712 PCI_DMA_FROMDEVICE);
713 dev_kfree_skb(rxbi->skb);
714 rxbi->skb = NULL;
715 rxbi->mapping = 0;
716 rxbi->len = 0;
717 }
718}
719
720static void
721jme_free_rx_resources(struct jme_adapter *jme)
722{
723 int i;
724 struct jme_ring *rxring = &(jme->rxring[0]);
725
726 if (rxring->alloc) {
47bd10d1
GFT		 727 if (rxring->bufinf) {
728 for (i = 0 ; i < jme->rx_ring_size ; ++i)
729 jme_free_rx_buf(jme, i);
730 kfree(rxring->bufinf);
731 }
95252236
GFT		 732
733 dma_free_coherent(&(jme->pdev->dev),
734 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
735 rxring->alloc,
736 rxring->dmaalloc);
737 rxring->alloc = NULL;
738 rxring->desc = NULL;
739 rxring->dmaalloc = 0;
740 rxring->dma = 0;
47bd10d1 741 rxring->bufinf = NULL;
95252236
GFT		 742 }
743 rxring->next_to_use = 0;
744 atomic_set(&rxring->next_to_clean, 0);
745}
746
747static int
748jme_setup_rx_resources(struct jme_adapter *jme)
749{
750 int i;
751 struct jme_ring *rxring = &(jme->rxring[0]);
752
753 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
754 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
755 &(rxring->dmaalloc),
756 GFP_ATOMIC);
47bd10d1
GFT		 757 if (!rxring->alloc)
758 goto err_set_null;
95252236
GFT		 759
760 /*
761 * 16 Bytes align
762 */
763 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
764 RING_DESC_ALIGN);
765 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
766 rxring->next_to_use = 0;
767 atomic_set(&rxring->next_to_clean, 0);
768
47bd10d1
GFT		 769 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
770 jme->rx_ring_size, GFP_ATOMIC);
771 if (unlikely(!(rxring->bufinf)))
772 goto err_free_rxring;
773
95252236
GFT		 774 /*
775 * Initiallize Receive Descriptors
776 */
47bd10d1
GFT		 777 memset(rxring->bufinf, 0,
778 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
95252236
GFT		 779 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
780 if (unlikely(jme_make_new_rx_buf(jme, i))) {
781 jme_free_rx_resources(jme);
782 return -ENOMEM;
783 }
784
785 jme_set_clean_rxdesc(jme, i);
786 }
787
788 return 0;
47bd10d1
GFT		 789
790err_free_rxring:
791 dma_free_coherent(&(jme->pdev->dev),
792 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
793 rxring->alloc,
794 rxring->dmaalloc);
795err_set_null:
796 rxring->desc = NULL;
797 rxring->dmaalloc = 0;
798 rxring->dma = 0;
799 rxring->bufinf = NULL;
800
801 return -ENOMEM;
95252236
GFT		 802}
803
804static inline void
805jme_enable_rx_engine(struct jme_adapter *jme)
806{
807 /*
808 * Select Queue 0
809 */
810 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
811 RXCS_QUEUESEL_Q0);
812 wmb();
813
814 /*
815 * Setup RX DMA Bass Address
816 */
eacf69a1 817 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
95252236 818 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
eacf69a1 819 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
95252236
GFT		 820
821 /*
822 * Setup RX Descriptor Count
823 */
824 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
825
826 /*
827 * Setup Unicast Filter
828 */
829 jme_set_multi(jme->dev);
830
831 /*
832 * Enable RX Engine
833 */
834 wmb();
835 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
836 RXCS_QUEUESEL_Q0 |
837 RXCS_ENABLE |
838 RXCS_QST);
839}
840
841static inline void
842jme_restart_rx_engine(struct jme_adapter *jme)
843{
844 /*
845 * Start RX Engine
846 */
847 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
848 RXCS_QUEUESEL_Q0 |
849 RXCS_ENABLE |
850 RXCS_QST);
851}
852
853static inline void
854jme_disable_rx_engine(struct jme_adapter *jme)
855{
856 int i;
857 u32 val;
858
859 /*
860 * Disable RX Engine
861 */
862 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
863 wmb();
864
865 val = jread32(jme, JME_RXCS);
866 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
867 mdelay(1);
868 val = jread32(jme, JME_RXCS);
869 rmb();
870 }
871
872 if (!i)
873 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
874
875}
876
877static int
878jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
879{
880 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
881 return false;
882
ce7d70af
GFT		 883 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
884 == RXWBFLAG_TCPON)) {
885 if (flags & RXWBFLAG_IPV4)
f8502ce4 886 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
ce7d70af 887 return false;
95252236
GFT		 888 }
889
ce7d70af
GFT		 890 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
891 == RXWBFLAG_UDPON)) {
892 if (flags & RXWBFLAG_IPV4)
f8502ce4 893 netif_err(jme, rx_err, jme->dev, "UDP Checksum error.\n");
ce7d70af 894 return false;
95252236
GFT		 895 }
896
ce7d70af
GFT		 897 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
898 == RXWBFLAG_IPV4)) {
f8502ce4 899 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error.\n");
ce7d70af 900 return false;
95252236
GFT		 901 }
902
903 return true;
95252236
GFT		 904}
905
906static void
907jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
908{
909 struct jme_ring *rxring = &(jme->rxring[0]);
910 struct rxdesc *rxdesc = rxring->desc;
911 struct jme_buffer_info *rxbi = rxring->bufinf;
912 struct sk_buff *skb;
913 int framesize;
914
915 rxdesc += idx;
916 rxbi += idx;
917
918 skb = rxbi->skb;
919 pci_dma_sync_single_for_cpu(jme->pdev,
920 rxbi->mapping,
921 rxbi->len,
922 PCI_DMA_FROMDEVICE);
923
924 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
925 pci_dma_sync_single_for_device(jme->pdev,
926 rxbi->mapping,
927 rxbi->len,
928 PCI_DMA_FROMDEVICE);
929
930 ++(NET_STAT(jme).rx_dropped);
931 } else {
932 framesize = le16_to_cpu(rxdesc->descwb.framesize)
933 - RX_PREPAD_SIZE;
934
935 skb_reserve(skb, RX_PREPAD_SIZE);
936 skb_put(skb, framesize);
937 skb->protocol = eth_type_trans(skb, jme->dev);
938
31c221c4 939 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
95252236
GFT		 940 skb->ip_summed = CHECKSUM_UNNECESSARY;
941 else
942 skb->ip_summed = CHECKSUM_NONE;
943
31c221c4 944 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
95252236
GFT		 945 if (jme->vlgrp) {
946 jme->jme_vlan_rx(skb, jme->vlgrp,
31c221c4 947 le16_to_cpu(rxdesc->descwb.vlan));
95252236 948 NET_STAT(jme).rx_bytes += 4;
17da69b8
GFT		 949 } else {
950 dev_kfree_skb(skb);
95252236
GFT		 951 }
952 } else {
953 jme->jme_rx(skb);
954 }
955
31c221c4
HH		 956 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
957 cpu_to_le16(RXWBFLAG_DEST_MUL))
95252236
GFT		 958 ++(NET_STAT(jme).multicast);
959
95252236
GFT		 960 NET_STAT(jme).rx_bytes += framesize;
961 ++(NET_STAT(jme).rx_packets);
962 }
963
964 jme_set_clean_rxdesc(jme, idx);
965
966}
967
968static int
969jme_process_receive(struct jme_adapter *jme, int limit)
970{
971 struct jme_ring *rxring = &(jme->rxring[0]);
972 struct rxdesc *rxdesc = rxring->desc;
973 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
974
975 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
976 goto out_inc;
977
978 if (unlikely(atomic_read(&jme->link_changing) != 1))
979 goto out_inc;
980
981 if (unlikely(!netif_carrier_ok(jme->dev)))
982 goto out_inc;
983
984 i = atomic_read(&rxring->next_to_clean);
858b9ced 985 while (limit > 0) {
95252236
GFT		 986 rxdesc = rxring->desc;
987 rxdesc += i;
988
31c221c4 989 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
95252236
GFT		 990 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
991 goto out;
858b9ced 992 --limit;
95252236
GFT		 993
994 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
995
996 if (unlikely(desccnt > 1 ||
997 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
998
999 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1000 ++(NET_STAT(jme).rx_crc_errors);
1001 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1002 ++(NET_STAT(jme).rx_fifo_errors);
1003 else
1004 ++(NET_STAT(jme).rx_errors);
1005
1006 if (desccnt > 1)
1007 limit -= desccnt - 1;
1008
1009 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1010 jme_set_clean_rxdesc(jme, j);
1011 j = (j + 1) & (mask);
1012 }
1013
1014 } else {
1015 jme_alloc_and_feed_skb(jme, i);
1016 }
1017
1018 i = (i + desccnt) & (mask);
1019 }
1020
1021out:
1022 atomic_set(&rxring->next_to_clean, i);
1023
1024out_inc:
1025 atomic_inc(&jme->rx_cleaning);
1026
1027 return limit > 0 ? limit : 0;
1028
1029}
1030
1031static void
1032jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1033{
1034 if (likely(atmp == dpi->cur)) {
1035 dpi->cnt = 0;
1036 return;
1037 }
1038
1039 if (dpi->attempt == atmp) {
1040 ++(dpi->cnt);
1041 } else {
1042 dpi->attempt = atmp;
1043 dpi->cnt = 0;
1044 }
1045
1046}
1047
1048static void
1049jme_dynamic_pcc(struct jme_adapter *jme)
1050{
1051 register struct dynpcc_info *dpi = &(jme->dpi);
1052
1053 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1054 jme_attempt_pcc(dpi, PCC_P3);
8e95a202
JP		 1055 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1056 dpi->intr_cnt > PCC_INTR_THRESHOLD)
95252236
GFT		 1057 jme_attempt_pcc(dpi, PCC_P2);
1058 else
1059 jme_attempt_pcc(dpi, PCC_P1);
1060
1061 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1062 if (dpi->attempt < dpi->cur)
1063 tasklet_schedule(&jme->rxclean_task);
1064 jme_set_rx_pcc(jme, dpi->attempt);
1065 dpi->cur = dpi->attempt;
1066 dpi->cnt = 0;
1067 }
1068}
1069
1070static void
1071jme_start_pcc_timer(struct jme_adapter *jme)
1072{
1073 struct dynpcc_info *dpi = &(jme->dpi);
1074 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1075 dpi->last_pkts = NET_STAT(jme).rx_packets;
1076 dpi->intr_cnt = 0;
1077 jwrite32(jme, JME_TMCSR,
1078 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1079}
1080
1081static inline void
1082jme_stop_pcc_timer(struct jme_adapter *jme)
1083{
1084 jwrite32(jme, JME_TMCSR, 0);
1085}
1086
1087static void
1088jme_shutdown_nic(struct jme_adapter *jme)
1089{
1090 u32 phylink;
1091
1092 phylink = jme_linkstat_from_phy(jme);
1093
1094 if (!(phylink & PHY_LINK_UP)) {
1095 /*
1096 * Disable all interrupt before issue timer
1097 */
1098 jme_stop_irq(jme);
1099 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1100 }
1101}
1102
1103static void
1104jme_pcc_tasklet(unsigned long arg)
1105{
1106 struct jme_adapter *jme = (struct jme_adapter *)arg;
1107 struct net_device *netdev = jme->dev;
1108
1109 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1110 jme_shutdown_nic(jme);
1111 return;
1112 }
1113
1114 if (unlikely(!netif_carrier_ok(netdev) ||
1115 (atomic_read(&jme->link_changing) != 1)
1116 )) {
1117 jme_stop_pcc_timer(jme);
1118 return;
1119 }
1120
1121 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1122 jme_dynamic_pcc(jme);
1123
1124 jme_start_pcc_timer(jme);
1125}
1126
1127static inline void
1128jme_polling_mode(struct jme_adapter *jme)
1129{
1130 jme_set_rx_pcc(jme, PCC_OFF);
1131}
1132
1133static inline void
1134jme_interrupt_mode(struct jme_adapter *jme)
1135{
1136 jme_set_rx_pcc(jme, PCC_P1);
1137}
1138
1139static inline int
1140jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1141{
1142 u32 apmc;
1143 apmc = jread32(jme, JME_APMC);
1144 return apmc & JME_APMC_PSEUDO_HP_EN;
1145}
1146
1147static void
1148jme_start_shutdown_timer(struct jme_adapter *jme)
1149{
1150 u32 apmc;
1151
1152 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1153 apmc &= ~JME_APMC_EPIEN_CTRL;
1154 if (!no_extplug) {
1155 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1156 wmb();
1157 }
1158 jwrite32f(jme, JME_APMC, apmc);
1159
1160 jwrite32f(jme, JME_TIMER2, 0);
1161 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1162 jwrite32(jme, JME_TMCSR,
1163 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1164}
1165
1166static void
1167jme_stop_shutdown_timer(struct jme_adapter *jme)
1168{
1169 u32 apmc;
1170
1171 jwrite32f(jme, JME_TMCSR, 0);
1172 jwrite32f(jme, JME_TIMER2, 0);
1173 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1174
1175 apmc = jread32(jme, JME_APMC);
1176 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1177 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1178 wmb();
1179 jwrite32f(jme, JME_APMC, apmc);
1180}
1181
1182static void
1183jme_link_change_tasklet(unsigned long arg)
1184{
1185 struct jme_adapter *jme = (struct jme_adapter *)arg;
1186 struct net_device *netdev = jme->dev;
1187 int rc;
1188
1189 while (!atomic_dec_and_test(&jme->link_changing)) {
1190 atomic_inc(&jme->link_changing);
f8502ce4 1191 netif_info(jme, intr, jme->dev, "Get link change lock failed.\n");
95252236 1192 while (atomic_read(&jme->link_changing) != 1)
f8502ce4 1193 netif_info(jme, intr, jme->dev, "Waiting link change lock.\n");
95252236
GFT		 1194 }
1195
1196 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1197 goto out;
1198
1199 jme->old_mtu = netdev->mtu;
1200 netif_stop_queue(netdev);
1201 if (jme_pseudo_hotplug_enabled(jme))
1202 jme_stop_shutdown_timer(jme);
1203
1204 jme_stop_pcc_timer(jme);
1205 tasklet_disable(&jme->txclean_task);
1206 tasklet_disable(&jme->rxclean_task);
1207 tasklet_disable(&jme->rxempty_task);
1208
1209 if (netif_carrier_ok(netdev)) {
1210 jme_reset_ghc_speed(jme);
1211 jme_disable_rx_engine(jme);
1212 jme_disable_tx_engine(jme);
1213 jme_reset_mac_processor(jme);
1214 jme_free_rx_resources(jme);
1215 jme_free_tx_resources(jme);
1216
1217 if (test_bit(JME_FLAG_POLL, &jme->flags))
1218 jme_polling_mode(jme);
1219
1220 netif_carrier_off(netdev);
1221 }
1222
1223 jme_check_link(netdev, 0);
1224 if (netif_carrier_ok(netdev)) {
1225 rc = jme_setup_rx_resources(jme);
1226 if (rc) {
1227 jeprintk(jme->pdev, "Allocating resources for RX error"
1228 ", Device STOPPED!\n");
1229 goto out_enable_tasklet;
1230 }
1231
1232 rc = jme_setup_tx_resources(jme);
1233 if (rc) {
1234 jeprintk(jme->pdev, "Allocating resources for TX error"
1235 ", Device STOPPED!\n");
1236 goto err_out_free_rx_resources;
1237 }
1238
1239 jme_enable_rx_engine(jme);
1240 jme_enable_tx_engine(jme);
1241
1242 netif_start_queue(netdev);
1243
1244 if (test_bit(JME_FLAG_POLL, &jme->flags))
1245 jme_interrupt_mode(jme);
1246
1247 jme_start_pcc_timer(jme);
1248 } else if (jme_pseudo_hotplug_enabled(jme)) {
1249 jme_start_shutdown_timer(jme);
1250 }
1251
1252 goto out_enable_tasklet;
1253
1254err_out_free_rx_resources:
1255 jme_free_rx_resources(jme);
1256out_enable_tasklet:
1257 tasklet_enable(&jme->txclean_task);
1258 tasklet_hi_enable(&jme->rxclean_task);
1259 tasklet_hi_enable(&jme->rxempty_task);
1260out:
1261 atomic_inc(&jme->link_changing);
1262}
1263
1264static void
1265jme_rx_clean_tasklet(unsigned long arg)
1266{
1267 struct jme_adapter *jme = (struct jme_adapter *)arg;
1268 struct dynpcc_info *dpi = &(jme->dpi);
1269
1270 jme_process_receive(jme, jme->rx_ring_size);
1271 ++(dpi->intr_cnt);
1272
1273}
1274
1275static int
1276jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1277{
1278 struct jme_adapter *jme = jme_napi_priv(holder);
95252236
GFT		 1279 int rest;
1280
1281 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1282
1283 while (atomic_read(&jme->rx_empty) > 0) {
1284 atomic_dec(&jme->rx_empty);
1285 ++(NET_STAT(jme).rx_dropped);
1286 jme_restart_rx_engine(jme);
1287 }
1288 atomic_inc(&jme->rx_empty);
1289
1290 if (rest) {
1291 JME_RX_COMPLETE(netdev, holder);
1292 jme_interrupt_mode(jme);
1293 }
1294
1295 JME_NAPI_WEIGHT_SET(budget, rest);
1296 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1297}
1298
1299static void
1300jme_rx_empty_tasklet(unsigned long arg)
1301{
1302 struct jme_adapter *jme = (struct jme_adapter *)arg;
1303
1304 if (unlikely(atomic_read(&jme->link_changing) != 1))
1305 return;
1306
1307 if (unlikely(!netif_carrier_ok(jme->dev)))
1308 return;
1309
f8502ce4 1310 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
95252236
GFT		 1311
1312 jme_rx_clean_tasklet(arg);
1313
1314 while (atomic_read(&jme->rx_empty) > 0) {
1315 atomic_dec(&jme->rx_empty);
1316 ++(NET_STAT(jme).rx_dropped);
1317 jme_restart_rx_engine(jme);
1318 }
1319 atomic_inc(&jme->rx_empty);
1320}
1321
1322static void
1323jme_wake_queue_if_stopped(struct jme_adapter *jme)
1324{
eacf69a1 1325 struct jme_ring *txring = &(jme->txring[0]);
95252236
GFT		 1326
1327 smp_wmb();
1328 if (unlikely(netif_queue_stopped(jme->dev) &&
1329 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
f8502ce4 1330 netif_info(jme, tx_done, jme->dev, "TX Queue Waked.\n");
95252236
GFT		 1331 netif_wake_queue(jme->dev);
1332 }
1333
1334}
1335
1336static void
1337jme_tx_clean_tasklet(unsigned long arg)
1338{
1339 struct jme_adapter *jme = (struct jme_adapter *)arg;
1340 struct jme_ring *txring = &(jme->txring[0]);
1341 struct txdesc *txdesc = txring->desc;
1342 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1343 int i, j, cnt = 0, max, err, mask;
1344
1345 tx_dbg(jme, "Into txclean.\n");
1346
1347 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1348 goto out;
1349
1350 if (unlikely(atomic_read(&jme->link_changing) != 1))
1351 goto out;
1352
1353 if (unlikely(!netif_carrier_ok(jme->dev)))
1354 goto out;
1355
1356 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1357 mask = jme->tx_ring_mask;
1358
1359 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1360
1361 ctxbi = txbi + i;
1362
1363 if (likely(ctxbi->skb &&
1364 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1365
1366 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1367 i, ctxbi->nr_desc, jiffies);
1368
1369 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1370
1371 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1372 ttxbi = txbi + ((i + j) & (mask));
1373 txdesc[(i + j) & (mask)].dw[0] = 0;
1374
1375 pci_unmap_page(jme->pdev,
1376 ttxbi->mapping,
1377 ttxbi->len,
1378 PCI_DMA_TODEVICE);
1379
1380 ttxbi->mapping = 0;
1381 ttxbi->len = 0;
1382 }
1383
1384 dev_kfree_skb(ctxbi->skb);
1385
1386 cnt += ctxbi->nr_desc;
1387
1388 if (unlikely(err)) {
1389 ++(NET_STAT(jme).tx_carrier_errors);
1390 } else {
1391 ++(NET_STAT(jme).tx_packets);
1392 NET_STAT(jme).tx_bytes += ctxbi->len;
1393 }
1394
1395 ctxbi->skb = NULL;
1396 ctxbi->len = 0;
1397 ctxbi->start_xmit = 0;
1398
1399 } else {
1400 break;
1401 }
1402
1403 i = (i + ctxbi->nr_desc) & mask;
1404
1405 ctxbi->nr_desc = 0;
1406 }
1407
1408 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1409 atomic_set(&txring->next_to_clean, i);
1410 atomic_add(cnt, &txring->nr_free);
1411
1412 jme_wake_queue_if_stopped(jme);
1413
1414out:
1415 atomic_inc(&jme->tx_cleaning);
1416}
1417
1418static void
1419jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1420{
1421 /*
1422 * Disable interrupt
1423 */
1424 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1425
1426 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1427 /*
1428 * Link change event is critical
1429 * all other events are ignored
1430 */
1431 jwrite32(jme, JME_IEVE, intrstat);
1432 tasklet_schedule(&jme->linkch_task);
1433 goto out_reenable;
1434 }
1435
1436 if (intrstat & INTR_TMINTR) {
1437 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1438 tasklet_schedule(&jme->pcc_task);
1439 }
1440
1441 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1442 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1443 tasklet_schedule(&jme->txclean_task);
1444 }
1445
1446 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1447 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1448 INTR_PCCRX0 |
1449 INTR_RX0EMP)) |
1450 INTR_RX0);
1451 }
1452
1453 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1454 if (intrstat & INTR_RX0EMP)
1455 atomic_inc(&jme->rx_empty);
1456
1457 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1458 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1459 jme_polling_mode(jme);
1460 JME_RX_SCHEDULE(jme);
1461 }
1462 }
1463 } else {
1464 if (intrstat & INTR_RX0EMP) {
1465 atomic_inc(&jme->rx_empty);
1466 tasklet_hi_schedule(&jme->rxempty_task);
1467 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1468 tasklet_hi_schedule(&jme->rxclean_task);
1469 }
1470 }
1471
1472out_reenable:
1473 /*
1474 * Re-enable interrupt
1475 */
1476 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1477}
1478
1479static irqreturn_t
1480jme_intr(int irq, void *dev_id)
1481{
1482 struct net_device *netdev = dev_id;
1483 struct jme_adapter *jme = netdev_priv(netdev);
1484 u32 intrstat;
1485
1486 intrstat = jread32(jme, JME_IEVE);
1487
1488 /*
1489 * Check if it's really an interrupt for us
1490 */
576b5223 1491 if (unlikely((intrstat & INTR_ENABLE) == 0))
95252236
GFT		 1492 return IRQ_NONE;
1493
1494 /*
1495 * Check if the device still exist
1496 */
1497 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1498 return IRQ_NONE;
1499
1500 jme_intr_msi(jme, intrstat);
1501
1502 return IRQ_HANDLED;
1503}
1504
1505static irqreturn_t
1506jme_msi(int irq, void *dev_id)
1507{
1508 struct net_device *netdev = dev_id;
1509 struct jme_adapter *jme = netdev_priv(netdev);
1510 u32 intrstat;
1511
d1dfa1d1 1512 intrstat = jread32(jme, JME_IEVE);
95252236
GFT		 1513
1514 jme_intr_msi(jme, intrstat);
1515
1516 return IRQ_HANDLED;
1517}
1518
1519static void
1520jme_reset_link(struct jme_adapter *jme)
1521{
1522 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1523}
1524
1525static void
1526jme_restart_an(struct jme_adapter *jme)
1527{
1528 u32 bmcr;
1529
1530 spin_lock_bh(&jme->phy_lock);
1531 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1532 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1533 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1534 spin_unlock_bh(&jme->phy_lock);
1535}
1536
1537static int
1538jme_request_irq(struct jme_adapter *jme)
1539{
1540 int rc;
1541 struct net_device *netdev = jme->dev;
1542 irq_handler_t handler = jme_intr;
1543 int irq_flags = IRQF_SHARED;
1544
1545 if (!pci_enable_msi(jme->pdev)) {
1546 set_bit(JME_FLAG_MSI, &jme->flags);
1547 handler = jme_msi;
1548 irq_flags = 0;
1549 }
1550
1551 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1552 netdev);
1553 if (rc) {
1554 jeprintk(jme->pdev,
1555 "Unable to request %s interrupt (return: %d)\n",
1556 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1557 rc);
1558
1559 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1560 pci_disable_msi(jme->pdev);
1561 clear_bit(JME_FLAG_MSI, &jme->flags);
1562 }
1563 } else {
1564 netdev->irq = jme->pdev->irq;
1565 }
1566
1567 return rc;
1568}
1569
1570static void
1571jme_free_irq(struct jme_adapter *jme)
1572{
1573 free_irq(jme->pdev->irq, jme->dev);
1574 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1575 pci_disable_msi(jme->pdev);
1576 clear_bit(JME_FLAG_MSI, &jme->flags);
1577 jme->dev->irq = jme->pdev->irq;
1578 }
1579}
1580
1581static int
1582jme_open(struct net_device *netdev)
1583{
1584 struct jme_adapter *jme = netdev_priv(netdev);
1585 int rc;
1586
1587 jme_clear_pm(jme);
1588 JME_NAPI_ENABLE(jme);
1589
38ed0c21 1590 tasklet_enable(&jme->linkch_task);
95252236
GFT		 1591 tasklet_enable(&jme->txclean_task);
1592 tasklet_hi_enable(&jme->rxclean_task);
1593 tasklet_hi_enable(&jme->rxempty_task);
1594
1595 rc = jme_request_irq(jme);
1596 if (rc)
1597 goto err_out;
1598
95252236
GFT		 1599 jme_start_irq(jme);
1600
1601 if (test_bit(JME_FLAG_SSET, &jme->flags))
1602 jme_set_settings(netdev, &jme->old_ecmd);
1603 else
1604 jme_reset_phy_processor(jme);
1605
1606 jme_reset_link(jme);
1607
1608 return 0;
1609
1610err_out:
1611 netif_stop_queue(netdev);
1612 netif_carrier_off(netdev);
1613 return rc;
1614}
1615
724f8805 1616#ifdef CONFIG_PM
95252236
GFT		 1617static void
1618jme_set_100m_half(struct jme_adapter *jme)
1619{
1620 u32 bmcr, tmp;
1621
1622 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1623 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1624 BMCR_SPEED1000 | BMCR_FULLDPLX);
1625 tmp |= BMCR_SPEED100;
1626
1627 if (bmcr != tmp)
1628 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1629
1630 if (jme->fpgaver)
1631 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1632 else
1633 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1634}
1635
1636#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1637static void
1638jme_wait_link(struct jme_adapter *jme)
1639{
1640 u32 phylink, to = JME_WAIT_LINK_TIME;
1641
1642 mdelay(1000);
1643 phylink = jme_linkstat_from_phy(jme);
1644 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1645 mdelay(10);
1646 phylink = jme_linkstat_from_phy(jme);
1647 }
1648}
724f8805 1649#endif
95252236
GFT		 1650
1651static inline void
1652jme_phy_off(struct jme_adapter *jme)
1653{
1654 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1655}
1656
1657static int
1658jme_close(struct net_device *netdev)
1659{
1660 struct jme_adapter *jme = netdev_priv(netdev);
1661
1662 netif_stop_queue(netdev);
1663 netif_carrier_off(netdev);
1664
1665 jme_stop_irq(jme);
95252236
GFT		 1666 jme_free_irq(jme);
1667
1668 JME_NAPI_DISABLE(jme);
1669
38ed0c21
GFT		 1670 tasklet_disable(&jme->linkch_task);
1671 tasklet_disable(&jme->txclean_task);
1672 tasklet_disable(&jme->rxclean_task);
1673 tasklet_disable(&jme->rxempty_task);
95252236
GFT		 1674
1675 jme_reset_ghc_speed(jme);
1676 jme_disable_rx_engine(jme);
1677 jme_disable_tx_engine(jme);
1678 jme_reset_mac_processor(jme);
1679 jme_free_rx_resources(jme);
1680 jme_free_tx_resources(jme);
1681 jme->phylink = 0;
1682 jme_phy_off(jme);
1683
1684 return 0;
1685}
1686
1687static int
1688jme_alloc_txdesc(struct jme_adapter *jme,
1689 struct sk_buff *skb)
1690{
eacf69a1 1691 struct jme_ring *txring = &(jme->txring[0]);
95252236
GFT		 1692 int idx, nr_alloc, mask = jme->tx_ring_mask;
1693
1694 idx = txring->next_to_use;
1695 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1696
1697 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1698 return -1;
1699
1700 atomic_sub(nr_alloc, &txring->nr_free);
1701
1702 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1703
1704 return idx;
1705}
1706
1707static void
1708jme_fill_tx_map(struct pci_dev *pdev,
1709 struct txdesc *txdesc,
1710 struct jme_buffer_info *txbi,
1711 struct page *page,
1712 u32 page_offset,
1713 u32 len,
1714 u8 hidma)
1715{
1716 dma_addr_t dmaaddr;
1717
1718 dmaaddr = pci_map_page(pdev,
1719 page,
1720 page_offset,
1721 len,
1722 PCI_DMA_TODEVICE);
1723
1724 pci_dma_sync_single_for_device(pdev,
1725 dmaaddr,
1726 len,
1727 PCI_DMA_TODEVICE);
1728
1729 txdesc->dw[0] = 0;
1730 txdesc->dw[1] = 0;
1731 txdesc->desc2.flags = TXFLAG_OWN;
1732 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1733 txdesc->desc2.datalen = cpu_to_le16(len);
1734 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1735 txdesc->desc2.bufaddrl = cpu_to_le32(
1736 (__u64)dmaaddr & 0xFFFFFFFFUL);
1737
1738 txbi->mapping = dmaaddr;
1739 txbi->len = len;
1740}
1741
1742static void
1743jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1744{
eacf69a1 1745 struct jme_ring *txring = &(jme->txring[0]);
95252236
GFT		 1746 struct txdesc *txdesc = txring->desc, *ctxdesc;
1747 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1748 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1749 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1750 int mask = jme->tx_ring_mask;
1751 struct skb_frag_struct *frag;
1752 u32 len;
1753
1754 for (i = 0 ; i < nr_frags ; ++i) {
1755 frag = &skb_shinfo(skb)->frags[i];
1756 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1757 ctxbi = txbi + ((idx + i + 2) & (mask));
1758
1759 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1760 frag->page_offset, frag->size, hidma);
1761 }
1762
1763 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1764 ctxdesc = txdesc + ((idx + 1) & (mask));
1765 ctxbi = txbi + ((idx + 1) & (mask));
1766 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1767 offset_in_page(skb->data), len, hidma);
1768
1769}
1770
1771static int
1772jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1773{
1774 if (unlikely(skb_shinfo(skb)->gso_size &&
1775 skb_header_cloned(skb) &&
1776 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1777 dev_kfree_skb(skb);
1778 return -1;
1779 }
1780
1781 return 0;
1782}
1783
1784static int
31c221c4 1785jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
95252236 1786{
31c221c4 1787 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
95252236
GFT		 1788 if (*mss) {
1789 *flags |= TXFLAG_LSEN;
1790
1791 if (skb->protocol == htons(ETH_P_IP)) {
1792 struct iphdr *iph = ip_hdr(skb);
1793
1794 iph->check = 0;
1795 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1796 iph->daddr, 0,
1797 IPPROTO_TCP,
1798 0);
1799 } else {
1800 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1801
1802 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1803 &ip6h->daddr, 0,
1804 IPPROTO_TCP,
1805 0);
1806 }
1807
1808 return 0;
1809 }
1810
1811 return 1;
1812}
1813
1814static void
1815jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1816{
1817 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1818 u8 ip_proto;
1819
1820 switch (skb->protocol) {
1821 case htons(ETH_P_IP):
1822 ip_proto = ip_hdr(skb)->protocol;
1823 break;
1824 case htons(ETH_P_IPV6):
1825 ip_proto = ipv6_hdr(skb)->nexthdr;
1826 break;
1827 default:
1828 ip_proto = 0;
1829 break;
1830 }
1831
1832 switch (ip_proto) {
1833 case IPPROTO_TCP:
1834 *flags |= TXFLAG_TCPCS;
1835 break;
1836 case IPPROTO_UDP:
1837 *flags |= TXFLAG_UDPCS;
1838 break;
1839 default:
f8502ce4 1840 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol.\n");
95252236
GFT		 1841 break;
1842 }
1843 }
1844}
1845
1846static inline void
31c221c4 1847jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
95252236
GFT		 1848{
1849 if (vlan_tx_tag_present(skb)) {
1850 *flags |= TXFLAG_TAGON;
31c221c4 1851 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
95252236
GFT		 1852 }
1853}
1854
1855static int
7f7fd2da 1856jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
95252236 1857{
eacf69a1 1858 struct jme_ring *txring = &(jme->txring[0]);
95252236
GFT		 1859 struct txdesc *txdesc;
1860 struct jme_buffer_info *txbi;
1861 u8 flags;
1862
1863 txdesc = (struct txdesc *)txring->desc + idx;
1864 txbi = txring->bufinf + idx;
1865
1866 txdesc->dw[0] = 0;
1867 txdesc->dw[1] = 0;
1868 txdesc->dw[2] = 0;
1869 txdesc->dw[3] = 0;
1870 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1871 /*
1872 * Set OWN bit at final.
1873 * When kernel transmit faster than NIC.
1874 * And NIC trying to send this descriptor before we tell
1875 * it to start sending this TX queue.
1876 * Other fields are already filled correctly.
1877 */
1878 wmb();
1879 flags = TXFLAG_OWN | TXFLAG_INT;
1880 /*
1881 * Set checksum flags while not tso
1882 */
1883 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1884 jme_tx_csum(jme, skb, &flags);
1885 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
7f7fd2da 1886 jme_map_tx_skb(jme, skb, idx);
95252236
GFT		 1887 txdesc->desc1.flags = flags;
1888 /*
1889 * Set tx buffer info after telling NIC to send
1890 * For better tx_clean timing
1891 */
1892 wmb();
1893 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1894 txbi->skb = skb;
1895 txbi->len = skb->len;
1896 txbi->start_xmit = jiffies;
1897 if (!txbi->start_xmit)
1898 txbi->start_xmit = (0UL-1);
1899
1900 return 0;
1901}
1902
1903static void
1904jme_stop_queue_if_full(struct jme_adapter *jme)
1905{
eacf69a1 1906 struct jme_ring *txring = &(jme->txring[0]);
95252236
GFT		 1907 struct jme_buffer_info *txbi = txring->bufinf;
1908 int idx = atomic_read(&txring->next_to_clean);
1909
1910 txbi += idx;
1911
1912 smp_wmb();
1913 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1914 netif_stop_queue(jme->dev);
f8502ce4 1915 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused.\n");
95252236
GFT		 1916 smp_wmb();
1917 if (atomic_read(&txring->nr_free)
1918 >= (jme->tx_wake_threshold)) {
1919 netif_wake_queue(jme->dev);
f8502ce4 1920 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked.\n");
95252236
GFT		 1921 }
1922 }
1923
1924 if (unlikely(txbi->start_xmit &&
1925 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1926 txbi->skb)) {
1927 netif_stop_queue(jme->dev);
f8502ce4 1928 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
95252236
GFT		 1929 }
1930}
1931
1932/*
1933 * This function is already protected by netif_tx_lock()
1934 */
1935
61357325 1936static netdev_tx_t
95252236
GFT		 1937jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1938{
1939 struct jme_adapter *jme = netdev_priv(netdev);
1940 int idx;
1941
1942 if (unlikely(jme_expand_header(jme, skb))) {
1943 ++(NET_STAT(jme).tx_dropped);
1944 return NETDEV_TX_OK;
1945 }
1946
1947 idx = jme_alloc_txdesc(jme, skb);
1948
1949 if (unlikely(idx < 0)) {
1950 netif_stop_queue(netdev);
f8502ce4 1951 netif_err(jme, tx_err, jme->dev, "BUG! Tx ring full when queue awake!\n");
95252236
GFT		 1952
1953 return NETDEV_TX_BUSY;
1954 }
1955
7f7fd2da 1956 jme_fill_tx_desc(jme, skb, idx);
95252236
GFT		 1957
1958 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1959 TXCS_SELECT_QUEUE0 |
1960 TXCS_QUEUE0S |
1961 TXCS_ENABLE);
95252236
GFT		 1962
1963 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1964 skb_shinfo(skb)->nr_frags + 2,
1965 jiffies);
1966 jme_stop_queue_if_full(jme);
1967
1968 return NETDEV_TX_OK;
1969}
1970
1971static int
1972jme_set_macaddr(struct net_device *netdev, void *p)
1973{
1974 struct jme_adapter *jme = netdev_priv(netdev);
1975 struct sockaddr *addr = p;
1976 u32 val;
1977
1978 if (netif_running(netdev))
1979 return -EBUSY;
1980
1981 spin_lock_bh(&jme->macaddr_lock);
1982 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1983
1984 val = (addr->sa_data[3] & 0xff) << 24 |
1985 (addr->sa_data[2] & 0xff) << 16 |
1986 (addr->sa_data[1] & 0xff) << 8 |
1987 (addr->sa_data[0] & 0xff);
1988 jwrite32(jme, JME_RXUMA_LO, val);
1989 val = (addr->sa_data[5] & 0xff) << 8 |
1990 (addr->sa_data[4] & 0xff);
1991 jwrite32(jme, JME_RXUMA_HI, val);
1992 spin_unlock_bh(&jme->macaddr_lock);
1993
1994 return 0;
1995}
1996
1997static void
1998jme_set_multi(struct net_device *netdev)
1999{
2000 struct jme_adapter *jme = netdev_priv(netdev);
2001 u32 mc_hash[2] = {};
95252236
GFT		 2002
2003 spin_lock_bh(&jme->rxmcs_lock);
2004
2005 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2006
2007 if (netdev->flags & IFF_PROMISC) {
2008 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2009 } else if (netdev->flags & IFF_ALLMULTI) {
2010 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2011 } else if (netdev->flags & IFF_MULTICAST) {
2012 struct dev_mc_list *mclist;
2013 int bit_nr;
2014
2015 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
f9dcbcc9 2016 netdev_for_each_mc_addr(mclist, netdev) {
95252236
GFT		 2017 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2018 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2019 }
2020
2021 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2022 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2023 }
2024
2025 wmb();
2026 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2027
2028 spin_unlock_bh(&jme->rxmcs_lock);
2029}
2030
2031static int
2032jme_change_mtu(struct net_device *netdev, int new_mtu)
2033{
2034 struct jme_adapter *jme = netdev_priv(netdev);
2035
2036 if (new_mtu == jme->old_mtu)
2037 return 0;
2038
2039 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2040 ((new_mtu) < IPV6_MIN_MTU))
2041 return -EINVAL;
2042
2043 if (new_mtu > 4000) {
2044 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2045 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2046 jme_restart_rx_engine(jme);
2047 } else {
2048 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2049 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2050 jme_restart_rx_engine(jme);
2051 }
2052
2053 if (new_mtu > 1900) {
2054 netdev->features &= ~(NETIF_F_HW_CSUM |
2055 NETIF_F_TSO |
2056 NETIF_F_TSO6);
2057 } else {
2058 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2059 netdev->features |= NETIF_F_HW_CSUM;
2060 if (test_bit(JME_FLAG_TSO, &jme->flags))
2061 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2062 }
2063
2064 netdev->mtu = new_mtu;
2065 jme_reset_link(jme);
2066
2067 return 0;
2068}
2069
2070static void
2071jme_tx_timeout(struct net_device *netdev)
2072{
2073 struct jme_adapter *jme = netdev_priv(netdev);
2074
2075 jme->phylink = 0;
2076 jme_reset_phy_processor(jme);
2077 if (test_bit(JME_FLAG_SSET, &jme->flags))
2078 jme_set_settings(netdev, &jme->old_ecmd);
2079
2080 /*
2081 * Force to Reset the link again
2082 */
2083 jme_reset_link(jme);
2084}
2085
2086static void
2087jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2088{
2089 struct jme_adapter *jme = netdev_priv(netdev);
2090
2091 jme->vlgrp = grp;
2092}
2093
2094static void
2095jme_get_drvinfo(struct net_device *netdev,
2096 struct ethtool_drvinfo *info)
2097{
2098 struct jme_adapter *jme = netdev_priv(netdev);
2099
2100 strcpy(info->driver, DRV_NAME);
2101 strcpy(info->version, DRV_VERSION);
2102 strcpy(info->bus_info, pci_name(jme->pdev));
2103}
2104
2105static int
2106jme_get_regs_len(struct net_device *netdev)
2107{
2108 return JME_REG_LEN;
2109}
2110
2111static void
2112mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2113{
2114 int i;
2115
2116 for (i = 0 ; i < len ; i += 4)
2117 p[i >> 2] = jread32(jme, reg + i);
2118}
2119
2120static void
2121mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2122{
2123 int i;
2124 u16 *p16 = (u16 *)p;
2125
2126 for (i = 0 ; i < reg_nr ; ++i)
2127 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2128}
2129
2130static void
2131jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2132{
2133 struct jme_adapter *jme = netdev_priv(netdev);
2134 u32 *p32 = (u32 *)p;
2135
2136 memset(p, 0xFF, JME_REG_LEN);
2137
2138 regs->version = 1;
2139 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2140
2141 p32 += 0x100 >> 2;
2142 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2143
2144 p32 += 0x100 >> 2;
2145 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2146
2147 p32 += 0x100 >> 2;
2148 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2149
2150 p32 += 0x100 >> 2;
2151 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2152}
2153
2154static int
2155jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2156{
2157 struct jme_adapter *jme = netdev_priv(netdev);
2158
2159 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2160 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2161
2162 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2163 ecmd->use_adaptive_rx_coalesce = false;
2164 ecmd->rx_coalesce_usecs = 0;
2165 ecmd->rx_max_coalesced_frames = 0;
2166 return 0;
2167 }
2168
2169 ecmd->use_adaptive_rx_coalesce = true;
2170
2171 switch (jme->dpi.cur) {
2172 case PCC_P1:
2173 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2174 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2175 break;
2176 case PCC_P2:
2177 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2178 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2179 break;
2180 case PCC_P3:
2181 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2182 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2183 break;
2184 default:
2185 break;
2186 }
2187
2188 return 0;
2189}
2190
2191static int
2192jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2193{
2194 struct jme_adapter *jme = netdev_priv(netdev);
2195 struct dynpcc_info *dpi = &(jme->dpi);
2196
2197 if (netif_running(netdev))
2198 return -EBUSY;
2199
8e95a202
JP		 2200 if (ecmd->use_adaptive_rx_coalesce &&
2201 test_bit(JME_FLAG_POLL, &jme->flags)) {
95252236
GFT		 2202 clear_bit(JME_FLAG_POLL, &jme->flags);
2203 jme->jme_rx = netif_rx;
2204 jme->jme_vlan_rx = vlan_hwaccel_rx;
2205 dpi->cur = PCC_P1;
2206 dpi->attempt = PCC_P1;
2207 dpi->cnt = 0;
2208 jme_set_rx_pcc(jme, PCC_P1);
2209 jme_interrupt_mode(jme);
8e95a202
JP		 2210 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2211 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
95252236
GFT		 2212 set_bit(JME_FLAG_POLL, &jme->flags);
2213 jme->jme_rx = netif_receive_skb;
2214 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2215 jme_interrupt_mode(jme);
2216 }
2217
2218 return 0;
2219}
2220
2221static void
2222jme_get_pauseparam(struct net_device *netdev,
2223 struct ethtool_pauseparam *ecmd)
2224{
2225 struct jme_adapter *jme = netdev_priv(netdev);
2226 u32 val;
2227
2228 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2229 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2230
2231 spin_lock_bh(&jme->phy_lock);
2232 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2233 spin_unlock_bh(&jme->phy_lock);
2234
2235 ecmd->autoneg =
2236 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2237}
2238
2239static int
2240jme_set_pauseparam(struct net_device *netdev,
2241 struct ethtool_pauseparam *ecmd)
2242{
2243 struct jme_adapter *jme = netdev_priv(netdev);
2244 u32 val;
2245
2246 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2247 (ecmd->tx_pause != 0)) {
2248
2249 if (ecmd->tx_pause)
2250 jme->reg_txpfc |= TXPFC_PF_EN;
2251 else
2252 jme->reg_txpfc &= ~TXPFC_PF_EN;
2253
2254 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2255 }
2256
2257 spin_lock_bh(&jme->rxmcs_lock);
2258 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2259 (ecmd->rx_pause != 0)) {
2260
2261 if (ecmd->rx_pause)
2262 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2263 else
2264 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2265
2266 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2267 }
2268 spin_unlock_bh(&jme->rxmcs_lock);
2269
2270 spin_lock_bh(&jme->phy_lock);
2271 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2272 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2273 (ecmd->autoneg != 0)) {
2274
2275 if (ecmd->autoneg)
2276 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2277 else
2278 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2279
2280 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2281 MII_ADVERTISE, val);
2282 }
2283 spin_unlock_bh(&jme->phy_lock);
2284
2285 return 0;
2286}
2287
2288static void
2289jme_get_wol(struct net_device *netdev,
2290 struct ethtool_wolinfo *wol)
2291{
2292 struct jme_adapter *jme = netdev_priv(netdev);
2293
2294 wol->supported = WAKE_MAGIC | WAKE_PHY;
2295
2296 wol->wolopts = 0;
2297
2298 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2299 wol->wolopts |= WAKE_PHY;
2300
2301 if (jme->reg_pmcs & PMCS_MFEN)
2302 wol->wolopts |= WAKE_MAGIC;
2303
2304}
2305
2306static int
2307jme_set_wol(struct net_device *netdev,
2308 struct ethtool_wolinfo *wol)
2309{
2310 struct jme_adapter *jme = netdev_priv(netdev);
2311
2312 if (wol->wolopts & (WAKE_MAGICSECURE |
2313 WAKE_UCAST |
2314 WAKE_MCAST |
2315 WAKE_BCAST |
2316 WAKE_ARP))
2317 return -EOPNOTSUPP;
2318
2319 jme->reg_pmcs = 0;
2320
2321 if (wol->wolopts & WAKE_PHY)
2322 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2323
2324 if (wol->wolopts & WAKE_MAGIC)
2325 jme->reg_pmcs |= PMCS_MFEN;
2326
2327 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2328
2329 return 0;
2330}
2331
2332static int
2333jme_get_settings(struct net_device *netdev,
2334 struct ethtool_cmd *ecmd)
2335{
2336 struct jme_adapter *jme = netdev_priv(netdev);
2337 int rc;
2338
2339 spin_lock_bh(&jme->phy_lock);
2340 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2341 spin_unlock_bh(&jme->phy_lock);
2342 return rc;
2343}
2344
2345static int
2346jme_set_settings(struct net_device *netdev,
2347 struct ethtool_cmd *ecmd)
2348{
2349 struct jme_adapter *jme = netdev_priv(netdev);
2350 int rc, fdc = 0;
2351
2352 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2353 return -EINVAL;
2354
2355 if (jme->mii_if.force_media &&
2356 ecmd->autoneg != AUTONEG_ENABLE &&
2357 (jme->mii_if.full_duplex != ecmd->duplex))
2358 fdc = 1;
2359
2360 spin_lock_bh(&jme->phy_lock);
2361 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2362 spin_unlock_bh(&jme->phy_lock);
2363
2364 if (!rc && fdc)
2365 jme_reset_link(jme);
2366
2367 if (!rc) {
2368 set_bit(JME_FLAG_SSET, &jme->flags);
2369 jme->old_ecmd = *ecmd;
2370 }
2371
2372 return rc;
2373}
2374
2375static u32
2376jme_get_link(struct net_device *netdev)
2377{
2378 struct jme_adapter *jme = netdev_priv(netdev);
2379 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2380}
2381
2382static u32
2383jme_get_msglevel(struct net_device *netdev)
2384{
2385 struct jme_adapter *jme = netdev_priv(netdev);
2386 return jme->msg_enable;
2387}
2388
2389static void
2390jme_set_msglevel(struct net_device *netdev, u32 value)
2391{
2392 struct jme_adapter *jme = netdev_priv(netdev);
2393 jme->msg_enable = value;
2394}
2395
2396static u32
2397jme_get_rx_csum(struct net_device *netdev)
2398{
2399 struct jme_adapter *jme = netdev_priv(netdev);
2400 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2401}
2402
2403static int
2404jme_set_rx_csum(struct net_device *netdev, u32 on)
2405{
2406 struct jme_adapter *jme = netdev_priv(netdev);
2407
2408 spin_lock_bh(&jme->rxmcs_lock);
2409 if (on)
2410 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2411 else
2412 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2413 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2414 spin_unlock_bh(&jme->rxmcs_lock);
2415
2416 return 0;
2417}
2418
2419static int
2420jme_set_tx_csum(struct net_device *netdev, u32 on)
2421{
2422 struct jme_adapter *jme = netdev_priv(netdev);
2423
2424 if (on) {
2425 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2426 if (netdev->mtu <= 1900)
2427 netdev->features |= NETIF_F_HW_CSUM;
2428 } else {
2429 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2430 netdev->features &= ~NETIF_F_HW_CSUM;
2431 }
2432
2433 return 0;
2434}
2435
2436static int
2437jme_set_tso(struct net_device *netdev, u32 on)
2438{
2439 struct jme_adapter *jme = netdev_priv(netdev);
2440
2441 if (on) {
2442 set_bit(JME_FLAG_TSO, &jme->flags);
2443 if (netdev->mtu <= 1900)
2444 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2445 } else {
2446 clear_bit(JME_FLAG_TSO, &jme->flags);
2447 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2448 }
2449
2450 return 0;
2451}
2452
2453static int
2454jme_nway_reset(struct net_device *netdev)
2455{
2456 struct jme_adapter *jme = netdev_priv(netdev);
2457 jme_restart_an(jme);
2458 return 0;
2459}
2460
2461static u8
2462jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2463{
2464 u32 val;
2465 int to;
2466
2467 val = jread32(jme, JME_SMBCSR);
2468 to = JME_SMB_BUSY_TIMEOUT;
2469 while ((val & SMBCSR_BUSY) && --to) {
2470 msleep(1);
2471 val = jread32(jme, JME_SMBCSR);
2472 }
2473 if (!to) {
f8502ce4 2474 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
95252236
GFT		 2475 return 0xFF;
2476 }
2477
2478 jwrite32(jme, JME_SMBINTF,
2479 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2480 SMBINTF_HWRWN_READ |
2481 SMBINTF_HWCMD);
2482
2483 val = jread32(jme, JME_SMBINTF);
2484 to = JME_SMB_BUSY_TIMEOUT;
2485 while ((val & SMBINTF_HWCMD) && --to) {
2486 msleep(1);
2487 val = jread32(jme, JME_SMBINTF);
2488 }
2489 if (!to) {
f8502ce4 2490 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
95252236
GFT		 2491 return 0xFF;
2492 }
2493
2494 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2495}
2496
2497static void
2498jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2499{
2500 u32 val;
2501 int to;
2502
2503 val = jread32(jme, JME_SMBCSR);
2504 to = JME_SMB_BUSY_TIMEOUT;
2505 while ((val & SMBCSR_BUSY) && --to) {
2506 msleep(1);
2507 val = jread32(jme, JME_SMBCSR);
2508 }
2509 if (!to) {
f8502ce4 2510 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
95252236
GFT		 2511 return;
2512 }
2513
2514 jwrite32(jme, JME_SMBINTF,
2515 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2516 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2517 SMBINTF_HWRWN_WRITE |
2518 SMBINTF_HWCMD);
2519
2520 val = jread32(jme, JME_SMBINTF);
2521 to = JME_SMB_BUSY_TIMEOUT;
2522 while ((val & SMBINTF_HWCMD) && --to) {
2523 msleep(1);
2524 val = jread32(jme, JME_SMBINTF);
2525 }
2526 if (!to) {
f8502ce4 2527 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
95252236
GFT		 2528 return;
2529 }
2530
2531 mdelay(2);
2532}
2533
2534static int
2535jme_get_eeprom_len(struct net_device *netdev)
2536{
2537 struct jme_adapter *jme = netdev_priv(netdev);
2538 u32 val;
2539 val = jread32(jme, JME_SMBCSR);
2540 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2541}
2542
2543static int
2544jme_get_eeprom(struct net_device *netdev,
2545 struct ethtool_eeprom *eeprom, u8 *data)
2546{
2547 struct jme_adapter *jme = netdev_priv(netdev);
2548 int i, offset = eeprom->offset, len = eeprom->len;
2549
2550 /*
2551 * ethtool will check the boundary for us
2552 */
2553 eeprom->magic = JME_EEPROM_MAGIC;
2554 for (i = 0 ; i < len ; ++i)
2555 data[i] = jme_smb_read(jme, i + offset);
2556
2557 return 0;
2558}
2559
2560static int
2561jme_set_eeprom(struct net_device *netdev,
2562 struct ethtool_eeprom *eeprom, u8 *data)
2563{
2564 struct jme_adapter *jme = netdev_priv(netdev);
2565 int i, offset = eeprom->offset, len = eeprom->len;
2566
2567 if (eeprom->magic != JME_EEPROM_MAGIC)
2568 return -EINVAL;
2569
2570 /*
2571 * ethtool will check the boundary for us
2572 */
2573 for (i = 0 ; i < len ; ++i)
2574 jme_smb_write(jme, i + offset, data[i]);
2575
2576 return 0;
2577}
2578
2579static const struct ethtool_ops jme_ethtool_ops = {
2580 .get_drvinfo = jme_get_drvinfo,
2581 .get_regs_len = jme_get_regs_len,
2582 .get_regs = jme_get_regs,
2583 .get_coalesce = jme_get_coalesce,
2584 .set_coalesce = jme_set_coalesce,
2585 .get_pauseparam = jme_get_pauseparam,
2586 .set_pauseparam = jme_set_pauseparam,
2587 .get_wol = jme_get_wol,
2588 .set_wol = jme_set_wol,
2589 .get_settings = jme_get_settings,
2590 .set_settings = jme_set_settings,
2591 .get_link = jme_get_link,
2592 .get_msglevel = jme_get_msglevel,
2593 .set_msglevel = jme_set_msglevel,
2594 .get_rx_csum = jme_get_rx_csum,
2595 .set_rx_csum = jme_set_rx_csum,
2596 .set_tx_csum = jme_set_tx_csum,
2597 .set_tso = jme_set_tso,
2598 .set_sg = ethtool_op_set_sg,
2599 .nway_reset = jme_nway_reset,
2600 .get_eeprom_len = jme_get_eeprom_len,
2601 .get_eeprom = jme_get_eeprom,
2602 .set_eeprom = jme_set_eeprom,
2603};
2604
2605static int
2606jme_pci_dma64(struct pci_dev *pdev)
2607{
814c01dc 2608 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
e930438c
YH		 2609 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2610 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
814c01dc
GFT		 2611 return 1;
2612
2613 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
e930438c
YH		 2614 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2615 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
814c01dc
GFT		 2616 return 1;
2617
284901a9
YH		 2618 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2619 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
95252236
GFT		 2620 return 0;
2621
2622 return -1;
2623}
2624
2625static inline void
2626jme_phy_init(struct jme_adapter *jme)
2627{
2628 u16 reg26;
2629
2630 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2631 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2632}
2633
2634static inline void
2635jme_check_hw_ver(struct jme_adapter *jme)
2636{
2637 u32 chipmode;
2638
2639 chipmode = jread32(jme, JME_CHIPMODE);
2640
2641 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2642 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2643}
2644
e48714ba
SH		 2645static const struct net_device_ops jme_netdev_ops = {
2646 .ndo_open = jme_open,
2647 .ndo_stop = jme_close,
2648 .ndo_validate_addr = eth_validate_addr,
2649 .ndo_start_xmit = jme_start_xmit,
2650 .ndo_set_mac_address = jme_set_macaddr,
2651 .ndo_set_multicast_list = jme_set_multi,
2652 .ndo_change_mtu = jme_change_mtu,
2653 .ndo_tx_timeout = jme_tx_timeout,
2654 .ndo_vlan_rx_register = jme_vlan_rx_register,
2655};
2656
95252236
GFT		 2657static int __devinit
2658jme_init_one(struct pci_dev *pdev,
2659 const struct pci_device_id *ent)
2660{
2661 int rc = 0, using_dac, i;
2662 struct net_device *netdev;
2663 struct jme_adapter *jme;
2664 u16 bmcr, bmsr;
2665 u32 apmc;
2666
2667 /*
2668 * set up PCI device basics
2669 */
2670 rc = pci_enable_device(pdev);
2671 if (rc) {
2672 jeprintk(pdev, "Cannot enable PCI device.\n");
2673 goto err_out;
2674 }
2675
2676 using_dac = jme_pci_dma64(pdev);
2677 if (using_dac < 0) {
2678 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2679 rc = -EIO;
2680 goto err_out_disable_pdev;
2681 }
2682
2683 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2684 jeprintk(pdev, "No PCI resource region found.\n");
2685 rc = -ENOMEM;
2686 goto err_out_disable_pdev;
2687 }
2688
2689 rc = pci_request_regions(pdev, DRV_NAME);
2690 if (rc) {
2691 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2692 goto err_out_disable_pdev;
2693 }
2694
2695 pci_set_master(pdev);
2696
2697 /*
2698 * alloc and init net device
2699 */
2700 netdev = alloc_etherdev(sizeof(*jme));
2701 if (!netdev) {
2702 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2703 rc = -ENOMEM;
2704 goto err_out_release_regions;
2705 }
e48714ba 2706 netdev->netdev_ops = &jme_netdev_ops;
95252236 2707 netdev->ethtool_ops = &jme_ethtool_ops;
95252236 2708 netdev->watchdog_timeo = TX_TIMEOUT;
95252236
GFT		 2709 netdev->features = NETIF_F_HW_CSUM |
2710 NETIF_F_SG |
2711 NETIF_F_TSO |
2712 NETIF_F_TSO6 |
2713 NETIF_F_HW_VLAN_TX |
2714 NETIF_F_HW_VLAN_RX;
2715 if (using_dac)
2716 netdev->features |= NETIF_F_HIGHDMA;
2717
2718 SET_NETDEV_DEV(netdev, &pdev->dev);
2719 pci_set_drvdata(pdev, netdev);
2720
2721 /*
2722 * init adapter info
2723 */
2724 jme = netdev_priv(netdev);
2725 jme->pdev = pdev;
2726 jme->dev = netdev;
2727 jme->jme_rx = netif_rx;
2728 jme->jme_vlan_rx = vlan_hwaccel_rx;
2729 jme->old_mtu = netdev->mtu = 1500;
2730 jme->phylink = 0;
2731 jme->tx_ring_size = 1 << 10;
2732 jme->tx_ring_mask = jme->tx_ring_size - 1;
2733 jme->tx_wake_threshold = 1 << 9;
2734 jme->rx_ring_size = 1 << 9;
2735 jme->rx_ring_mask = jme->rx_ring_size - 1;
2736 jme->msg_enable = JME_DEF_MSG_ENABLE;
2737 jme->regs = ioremap(pci_resource_start(pdev, 0),
2738 pci_resource_len(pdev, 0));
2739 if (!(jme->regs)) {
2740 jeprintk(pdev, "Mapping PCI resource region error.\n");
2741 rc = -ENOMEM;
2742 goto err_out_free_netdev;
2743 }
95252236
GFT		 2744
2745 if (no_pseudohp) {
2746 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2747 jwrite32(jme, JME_APMC, apmc);
2748 } else if (force_pseudohp) {
2749 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2750 jwrite32(jme, JME_APMC, apmc);
2751 }
2752
2753 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2754
2755 spin_lock_init(&jme->phy_lock);
2756 spin_lock_init(&jme->macaddr_lock);
2757 spin_lock_init(&jme->rxmcs_lock);
2758
2759 atomic_set(&jme->link_changing, 1);
2760 atomic_set(&jme->rx_cleaning, 1);
2761 atomic_set(&jme->tx_cleaning, 1);
2762 atomic_set(&jme->rx_empty, 1);
2763
2764 tasklet_init(&jme->pcc_task,
164165da 2765 jme_pcc_tasklet,
95252236
GFT		 2766 (unsigned long) jme);
2767 tasklet_init(&jme->linkch_task,
164165da 2768 jme_link_change_tasklet,
95252236
GFT		 2769 (unsigned long) jme);
2770 tasklet_init(&jme->txclean_task,
164165da 2771 jme_tx_clean_tasklet,
95252236
GFT		 2772 (unsigned long) jme);
2773 tasklet_init(&jme->rxclean_task,
164165da 2774 jme_rx_clean_tasklet,
95252236
GFT		 2775 (unsigned long) jme);
2776 tasklet_init(&jme->rxempty_task,
164165da 2777 jme_rx_empty_tasklet,
95252236 2778 (unsigned long) jme);
38ed0c21 2779 tasklet_disable_nosync(&jme->linkch_task);
95252236
GFT		 2780 tasklet_disable_nosync(&jme->txclean_task);
2781 tasklet_disable_nosync(&jme->rxclean_task);
2782 tasklet_disable_nosync(&jme->rxempty_task);
2783 jme->dpi.cur = PCC_P1;
2784
2785 jme->reg_ghc = 0;
2786 jme->reg_rxcs = RXCS_DEFAULT;
2787 jme->reg_rxmcs = RXMCS_DEFAULT;
2788 jme->reg_txpfc = 0;
2789 jme->reg_pmcs = PMCS_MFEN;
2790 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2791 set_bit(JME_FLAG_TSO, &jme->flags);
2792
2793 /*
2794 * Get Max Read Req Size from PCI Config Space
2795 */
2796 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2797 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2798 switch (jme->mrrs) {
2799 case MRRS_128B:
2800 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2801 break;
2802 case MRRS_256B:
2803 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2804 break;
2805 default:
2806 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2807 break;
2808 };
2809
2810 /*
2811 * Must check before reset_mac_processor
2812 */
2813 jme_check_hw_ver(jme);
2814 jme->mii_if.dev = netdev;
2815 if (jme->fpgaver) {
2816 jme->mii_if.phy_id = 0;
2817 for (i = 1 ; i < 32 ; ++i) {
2818 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2819 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2820 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2821 jme->mii_if.phy_id = i;
2822 break;
2823 }
2824 }
2825
2826 if (!jme->mii_if.phy_id) {
2827 rc = -EIO;
2828 jeprintk(pdev, "Can not find phy_id.\n");
d1dfa1d1 2829 goto err_out_unmap;
95252236
GFT		 2830 }
2831
2832 jme->reg_ghc |= GHC_LINK_POLL;
2833 } else {
2834 jme->mii_if.phy_id = 1;
2835 }
2836 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2837 jme->mii_if.supports_gmii = true;
2838 else
2839 jme->mii_if.supports_gmii = false;
2840 jme->mii_if.mdio_read = jme_mdio_read;
2841 jme->mii_if.mdio_write = jme_mdio_write;
2842
2843 jme_clear_pm(jme);
2844 jme_set_phyfifoa(jme);
2845 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2846 if (!jme->fpgaver)
2847 jme_phy_init(jme);
2848 jme_phy_off(jme);
2849
2850 /*
2851 * Reset MAC processor and reload EEPROM for MAC Address
2852 */
2853 jme_reset_mac_processor(jme);
2854 rc = jme_reload_eeprom(jme);
2855 if (rc) {
2856 jeprintk(pdev,
2857 "Reload eeprom for reading MAC Address error.\n");
d1dfa1d1 2858 goto err_out_unmap;
95252236
GFT		 2859 }
2860 jme_load_macaddr(netdev);
2861
2862 /*
2863 * Tell stack that we are not ready to work until open()
2864 */
2865 netif_carrier_off(netdev);
2866 netif_stop_queue(netdev);
2867
2868 /*
2869 * Register netdev
2870 */
2871 rc = register_netdev(netdev);
2872 if (rc) {
2873 jeprintk(pdev, "Cannot register net device.\n");
d1dfa1d1 2874 goto err_out_unmap;
95252236
GFT		 2875 }
2876
f8502ce4
JP		 2877 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2878 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2879 "JMC250 Gigabit Ethernet" :
2880 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2881 "JMC260 Fast Ethernet" : "Unknown",
2882 (jme->fpgaver != 0) ? " (FPGA)" : "",
2883 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2884 jme->rev, netdev->dev_addr);
95252236
GFT		 2885
2886 return 0;
2887
95252236
GFT		 2888err_out_unmap:
2889 iounmap(jme->regs);
2890err_out_free_netdev:
2891 pci_set_drvdata(pdev, NULL);
2892 free_netdev(netdev);
2893err_out_release_regions:
2894 pci_release_regions(pdev);
2895err_out_disable_pdev:
2896 pci_disable_device(pdev);
2897err_out:
2898 return rc;
2899}
2900
2901static void __devexit
2902jme_remove_one(struct pci_dev *pdev)
2903{
2904 struct net_device *netdev = pci_get_drvdata(pdev);
2905 struct jme_adapter *jme = netdev_priv(netdev);
2906
2907 unregister_netdev(netdev);
95252236
GFT		 2908 iounmap(jme->regs);
2909 pci_set_drvdata(pdev, NULL);
2910 free_netdev(netdev);
2911 pci_release_regions(pdev);
2912 pci_disable_device(pdev);
2913
2914}
2915
724f8805 2916#ifdef CONFIG_PM
95252236
GFT		 2917static int
2918jme_suspend(struct pci_dev *pdev, pm_message_t state)
2919{
2920 struct net_device *netdev = pci_get_drvdata(pdev);
2921 struct jme_adapter *jme = netdev_priv(netdev);
2922
2923 atomic_dec(&jme->link_changing);
2924
2925 netif_device_detach(netdev);
2926 netif_stop_queue(netdev);
2927 jme_stop_irq(jme);
2928
2929 tasklet_disable(&jme->txclean_task);
2930 tasklet_disable(&jme->rxclean_task);
2931 tasklet_disable(&jme->rxempty_task);
2932
95252236
GFT		 2933 if (netif_carrier_ok(netdev)) {
2934 if (test_bit(JME_FLAG_POLL, &jme->flags))
2935 jme_polling_mode(jme);
2936
2937 jme_stop_pcc_timer(jme);
2938 jme_reset_ghc_speed(jme);
2939 jme_disable_rx_engine(jme);
2940 jme_disable_tx_engine(jme);
2941 jme_reset_mac_processor(jme);
2942 jme_free_rx_resources(jme);
2943 jme_free_tx_resources(jme);
2944 netif_carrier_off(netdev);
2945 jme->phylink = 0;
2946 }
2947
2948 tasklet_enable(&jme->txclean_task);
2949 tasklet_hi_enable(&jme->rxclean_task);
2950 tasklet_hi_enable(&jme->rxempty_task);
2951
2952 pci_save_state(pdev);
2953 if (jme->reg_pmcs) {
2954 jme_set_100m_half(jme);
2955
2956 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2957 jme_wait_link(jme);
2958
2959 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2960
2961 pci_enable_wake(pdev, PCI_D3cold, true);
2962 } else {
2963 jme_phy_off(jme);
2964 }
2965 pci_set_power_state(pdev, PCI_D3cold);
2966
2967 return 0;
2968}
2969
2970static int
2971jme_resume(struct pci_dev *pdev)
2972{
2973 struct net_device *netdev = pci_get_drvdata(pdev);
2974 struct jme_adapter *jme = netdev_priv(netdev);
2975
2976 jme_clear_pm(jme);
2977 pci_restore_state(pdev);
2978
2979 if (test_bit(JME_FLAG_SSET, &jme->flags))
2980 jme_set_settings(netdev, &jme->old_ecmd);
2981 else
2982 jme_reset_phy_processor(jme);
2983
95252236
GFT		 2984 jme_start_irq(jme);
2985 netif_device_attach(netdev);
2986
2987 atomic_inc(&jme->link_changing);
2988
2989 jme_reset_link(jme);
2990
2991 return 0;
2992}
724f8805 2993#endif
95252236 2994
a3aa1884 2995static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
95252236
GFT		 2996 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
2997 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
2998 { }
2999};
3000
3001static struct pci_driver jme_driver = {
3002 .name = DRV_NAME,
3003 .id_table = jme_pci_tbl,
3004 .probe = jme_init_one,
3005 .remove = __devexit_p(jme_remove_one),
3006#ifdef CONFIG_PM
3007 .suspend = jme_suspend,
3008 .resume = jme_resume,
3009#endif /* CONFIG_PM */
3010};
3011
3012static int __init
3013jme_init_module(void)
3014{
07c8d2aa 3015 printk(KERN_INFO PFX "JMicron JMC2XX ethernet "
95252236
GFT		 3016 "driver version %s\n", DRV_VERSION);
3017 return pci_register_driver(&jme_driver);
3018}
3019
3020static void __exit
3021jme_cleanup_module(void)
3022{
3023 pci_unregister_driver(&jme_driver);
3024}
3025
3026module_init(jme_init_module);
3027module_exit(jme_cleanup_module);
3028
3029MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3030MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3031MODULE_LICENSE("GPL");
3032MODULE_VERSION(DRV_VERSION);
3033MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3034
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