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ef11291b FF |
1 | /* |
2 | * Driver for the IDT RC32434 (Korina) on-chip ethernet controller. | |
3 | * | |
4 | * Copyright 2004 IDT Inc. (rischelp@idt.com) | |
5 | * Copyright 2006 Felix Fietkau <nbd@openwrt.org> | |
6 | * Copyright 2008 Florian Fainelli <florian@openwrt.org> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
27 | * | |
28 | * Writing to a DMA status register: | |
29 | * | |
30 | * When writing to the status register, you should mask the bit you have | |
31 | * been testing the status register with. Both Tx and Rx DMA registers | |
32 | * should stick to this procedure. | |
33 | */ | |
34 | ||
35 | #include <linux/module.h> | |
36 | #include <linux/kernel.h> | |
37 | #include <linux/moduleparam.h> | |
38 | #include <linux/sched.h> | |
39 | #include <linux/ctype.h> | |
40 | #include <linux/types.h> | |
41 | #include <linux/interrupt.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/ioport.h> | |
44 | #include <linux/in.h> | |
45 | #include <linux/slab.h> | |
46 | #include <linux/string.h> | |
47 | #include <linux/delay.h> | |
48 | #include <linux/netdevice.h> | |
49 | #include <linux/etherdevice.h> | |
50 | #include <linux/skbuff.h> | |
51 | #include <linux/errno.h> | |
52 | #include <linux/platform_device.h> | |
53 | #include <linux/mii.h> | |
54 | #include <linux/ethtool.h> | |
55 | #include <linux/crc32.h> | |
56 | ||
57 | #include <asm/bootinfo.h> | |
58 | #include <asm/system.h> | |
59 | #include <asm/bitops.h> | |
60 | #include <asm/pgtable.h> | |
61 | #include <asm/segment.h> | |
62 | #include <asm/io.h> | |
63 | #include <asm/dma.h> | |
64 | ||
65 | #include <asm/mach-rc32434/rb.h> | |
66 | #include <asm/mach-rc32434/rc32434.h> | |
67 | #include <asm/mach-rc32434/eth.h> | |
68 | #include <asm/mach-rc32434/dma_v.h> | |
69 | ||
70 | #define DRV_NAME "korina" | |
71 | #define DRV_VERSION "0.10" | |
72 | #define DRV_RELDATE "04Mar2008" | |
73 | ||
74 | #define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \ | |
75 | ((dev)->dev_addr[1])) | |
76 | #define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \ | |
77 | ((dev)->dev_addr[3] << 16) | \ | |
78 | ((dev)->dev_addr[4] << 8) | \ | |
79 | ((dev)->dev_addr[5])) | |
80 | ||
81 | #define MII_CLOCK 1250000 /* no more than 2.5MHz */ | |
82 | ||
83 | /* the following must be powers of two */ | |
84 | #define KORINA_NUM_RDS 64 /* number of receive descriptors */ | |
85 | #define KORINA_NUM_TDS 64 /* number of transmit descriptors */ | |
86 | ||
a13b2782 PS |
87 | /* KORINA_RBSIZE is the hardware's default maximum receive |
88 | * frame size in bytes. Having this hardcoded means that there | |
89 | * is no support for MTU sizes greater than 1500. */ | |
90 | #define KORINA_RBSIZE 1536 /* size of one resource buffer = Ether MTU */ | |
ef11291b FF |
91 | #define KORINA_RDS_MASK (KORINA_NUM_RDS - 1) |
92 | #define KORINA_TDS_MASK (KORINA_NUM_TDS - 1) | |
93 | #define RD_RING_SIZE (KORINA_NUM_RDS * sizeof(struct dma_desc)) | |
94 | #define TD_RING_SIZE (KORINA_NUM_TDS * sizeof(struct dma_desc)) | |
95 | ||
96 | #define TX_TIMEOUT (6000 * HZ / 1000) | |
97 | ||
98 | enum chain_status { desc_filled, desc_empty }; | |
99 | #define IS_DMA_FINISHED(X) (((X) & (DMA_DESC_FINI)) != 0) | |
100 | #define IS_DMA_DONE(X) (((X) & (DMA_DESC_DONE)) != 0) | |
101 | #define RCVPKT_LENGTH(X) (((X) & ETH_RX_LEN) >> ETH_RX_LEN_BIT) | |
102 | ||
103 | /* Information that need to be kept for each board. */ | |
104 | struct korina_private { | |
105 | struct eth_regs *eth_regs; | |
106 | struct dma_reg *rx_dma_regs; | |
107 | struct dma_reg *tx_dma_regs; | |
108 | struct dma_desc *td_ring; /* transmit descriptor ring */ | |
109 | struct dma_desc *rd_ring; /* receive descriptor ring */ | |
110 | ||
111 | struct sk_buff *tx_skb[KORINA_NUM_TDS]; | |
112 | struct sk_buff *rx_skb[KORINA_NUM_RDS]; | |
113 | ||
114 | int rx_next_done; | |
115 | int rx_chain_head; | |
116 | int rx_chain_tail; | |
117 | enum chain_status rx_chain_status; | |
118 | ||
119 | int tx_next_done; | |
120 | int tx_chain_head; | |
121 | int tx_chain_tail; | |
122 | enum chain_status tx_chain_status; | |
123 | int tx_count; | |
124 | int tx_full; | |
125 | ||
126 | int rx_irq; | |
127 | int tx_irq; | |
128 | int ovr_irq; | |
129 | int und_irq; | |
130 | ||
131 | spinlock_t lock; /* NIC xmit lock */ | |
132 | ||
133 | int dma_halt_cnt; | |
134 | int dma_run_cnt; | |
135 | struct napi_struct napi; | |
4d5ef9f0 | 136 | struct timer_list media_check_timer; |
ef11291b FF |
137 | struct mii_if_info mii_if; |
138 | struct net_device *dev; | |
139 | int phy_addr; | |
140 | }; | |
141 | ||
142 | extern unsigned int idt_cpu_freq; | |
143 | ||
144 | static inline void korina_start_dma(struct dma_reg *ch, u32 dma_addr) | |
145 | { | |
146 | writel(0, &ch->dmandptr); | |
147 | writel(dma_addr, &ch->dmadptr); | |
148 | } | |
149 | ||
150 | static inline void korina_abort_dma(struct net_device *dev, | |
151 | struct dma_reg *ch) | |
152 | { | |
153 | if (readl(&ch->dmac) & DMA_CHAN_RUN_BIT) { | |
154 | writel(0x10, &ch->dmac); | |
155 | ||
156 | while (!(readl(&ch->dmas) & DMA_STAT_HALT)) | |
157 | dev->trans_start = jiffies; | |
158 | ||
159 | writel(0, &ch->dmas); | |
160 | } | |
161 | ||
162 | writel(0, &ch->dmadptr); | |
163 | writel(0, &ch->dmandptr); | |
164 | } | |
165 | ||
166 | static inline void korina_chain_dma(struct dma_reg *ch, u32 dma_addr) | |
167 | { | |
168 | writel(dma_addr, &ch->dmandptr); | |
169 | } | |
170 | ||
171 | static void korina_abort_tx(struct net_device *dev) | |
172 | { | |
173 | struct korina_private *lp = netdev_priv(dev); | |
174 | ||
175 | korina_abort_dma(dev, lp->tx_dma_regs); | |
176 | } | |
177 | ||
178 | static void korina_abort_rx(struct net_device *dev) | |
179 | { | |
180 | struct korina_private *lp = netdev_priv(dev); | |
181 | ||
182 | korina_abort_dma(dev, lp->rx_dma_regs); | |
183 | } | |
184 | ||
185 | static void korina_start_rx(struct korina_private *lp, | |
186 | struct dma_desc *rd) | |
187 | { | |
188 | korina_start_dma(lp->rx_dma_regs, CPHYSADDR(rd)); | |
189 | } | |
190 | ||
191 | static void korina_chain_rx(struct korina_private *lp, | |
192 | struct dma_desc *rd) | |
193 | { | |
194 | korina_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd)); | |
195 | } | |
196 | ||
197 | /* transmit packet */ | |
198 | static int korina_send_packet(struct sk_buff *skb, struct net_device *dev) | |
199 | { | |
200 | struct korina_private *lp = netdev_priv(dev); | |
201 | unsigned long flags; | |
202 | u32 length; | |
97bc477c | 203 | u32 chain_prev, chain_next; |
ef11291b FF |
204 | struct dma_desc *td; |
205 | ||
206 | spin_lock_irqsave(&lp->lock, flags); | |
207 | ||
208 | td = &lp->td_ring[lp->tx_chain_tail]; | |
209 | ||
210 | /* stop queue when full, drop pkts if queue already full */ | |
211 | if (lp->tx_count >= (KORINA_NUM_TDS - 2)) { | |
212 | lp->tx_full = 1; | |
213 | ||
214 | if (lp->tx_count == (KORINA_NUM_TDS - 2)) | |
215 | netif_stop_queue(dev); | |
216 | else { | |
217 | dev->stats.tx_dropped++; | |
218 | dev_kfree_skb_any(skb); | |
219 | spin_unlock_irqrestore(&lp->lock, flags); | |
220 | ||
221 | return NETDEV_TX_BUSY; | |
222 | } | |
223 | } | |
224 | ||
225 | lp->tx_count++; | |
226 | ||
227 | lp->tx_skb[lp->tx_chain_tail] = skb; | |
228 | ||
229 | length = skb->len; | |
230 | dma_cache_wback((u32)skb->data, skb->len); | |
231 | ||
232 | /* Setup the transmit descriptor. */ | |
233 | dma_cache_inv((u32) td, sizeof(*td)); | |
234 | td->ca = CPHYSADDR(skb->data); | |
97bc477c PS |
235 | chain_prev = (lp->tx_chain_tail - 1) & KORINA_TDS_MASK; |
236 | chain_next = (lp->tx_chain_tail + 1) & KORINA_TDS_MASK; | |
ef11291b FF |
237 | |
238 | if (readl(&(lp->tx_dma_regs->dmandptr)) == 0) { | |
239 | if (lp->tx_chain_status == desc_empty) { | |
240 | /* Update tail */ | |
241 | td->control = DMA_COUNT(length) | | |
242 | DMA_DESC_COF | DMA_DESC_IOF; | |
243 | /* Move tail */ | |
97bc477c | 244 | lp->tx_chain_tail = chain_next; |
ef11291b FF |
245 | /* Write to NDPTR */ |
246 | writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), | |
247 | &lp->tx_dma_regs->dmandptr); | |
248 | /* Move head to tail */ | |
249 | lp->tx_chain_head = lp->tx_chain_tail; | |
250 | } else { | |
251 | /* Update tail */ | |
252 | td->control = DMA_COUNT(length) | | |
253 | DMA_DESC_COF | DMA_DESC_IOF; | |
254 | /* Link to prev */ | |
97bc477c | 255 | lp->td_ring[chain_prev].control &= |
ef11291b FF |
256 | ~DMA_DESC_COF; |
257 | /* Link to prev */ | |
97bc477c | 258 | lp->td_ring[chain_prev].link = CPHYSADDR(td); |
ef11291b | 259 | /* Move tail */ |
97bc477c | 260 | lp->tx_chain_tail = chain_next; |
ef11291b FF |
261 | /* Write to NDPTR */ |
262 | writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), | |
263 | &(lp->tx_dma_regs->dmandptr)); | |
264 | /* Move head to tail */ | |
265 | lp->tx_chain_head = lp->tx_chain_tail; | |
266 | lp->tx_chain_status = desc_empty; | |
267 | } | |
268 | } else { | |
269 | if (lp->tx_chain_status == desc_empty) { | |
270 | /* Update tail */ | |
271 | td->control = DMA_COUNT(length) | | |
272 | DMA_DESC_COF | DMA_DESC_IOF; | |
273 | /* Move tail */ | |
97bc477c | 274 | lp->tx_chain_tail = chain_next; |
ef11291b | 275 | lp->tx_chain_status = desc_filled; |
ef11291b FF |
276 | } else { |
277 | /* Update tail */ | |
278 | td->control = DMA_COUNT(length) | | |
279 | DMA_DESC_COF | DMA_DESC_IOF; | |
97bc477c | 280 | lp->td_ring[chain_prev].control &= |
ef11291b | 281 | ~DMA_DESC_COF; |
97bc477c PS |
282 | lp->td_ring[chain_prev].link = CPHYSADDR(td); |
283 | lp->tx_chain_tail = chain_next; | |
ef11291b FF |
284 | } |
285 | } | |
286 | dma_cache_wback((u32) td, sizeof(*td)); | |
287 | ||
288 | dev->trans_start = jiffies; | |
289 | spin_unlock_irqrestore(&lp->lock, flags); | |
290 | ||
291 | return NETDEV_TX_OK; | |
292 | } | |
293 | ||
294 | static int mdio_read(struct net_device *dev, int mii_id, int reg) | |
295 | { | |
296 | struct korina_private *lp = netdev_priv(dev); | |
297 | int ret; | |
298 | ||
299 | mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8); | |
300 | ||
301 | writel(0, &lp->eth_regs->miimcfg); | |
302 | writel(0, &lp->eth_regs->miimcmd); | |
303 | writel(mii_id | reg, &lp->eth_regs->miimaddr); | |
304 | writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd); | |
305 | ||
306 | ret = (int)(readl(&lp->eth_regs->miimrdd)); | |
307 | return ret; | |
308 | } | |
309 | ||
310 | static void mdio_write(struct net_device *dev, int mii_id, int reg, int val) | |
311 | { | |
312 | struct korina_private *lp = netdev_priv(dev); | |
313 | ||
314 | mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8); | |
315 | ||
316 | writel(0, &lp->eth_regs->miimcfg); | |
317 | writel(1, &lp->eth_regs->miimcmd); | |
318 | writel(mii_id | reg, &lp->eth_regs->miimaddr); | |
319 | writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd); | |
320 | writel(val, &lp->eth_regs->miimwtd); | |
321 | } | |
322 | ||
323 | /* Ethernet Rx DMA interrupt */ | |
324 | static irqreturn_t korina_rx_dma_interrupt(int irq, void *dev_id) | |
325 | { | |
326 | struct net_device *dev = dev_id; | |
327 | struct korina_private *lp = netdev_priv(dev); | |
328 | u32 dmas, dmasm; | |
329 | irqreturn_t retval; | |
330 | ||
331 | dmas = readl(&lp->rx_dma_regs->dmas); | |
332 | if (dmas & (DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR)) { | |
ef11291b FF |
333 | dmasm = readl(&lp->rx_dma_regs->dmasm); |
334 | writel(dmasm | (DMA_STAT_DONE | | |
335 | DMA_STAT_HALT | DMA_STAT_ERR), | |
336 | &lp->rx_dma_regs->dmasm); | |
337 | ||
288379f0 | 338 | napi_schedule(&lp->napi); |
60d3f982 | 339 | |
ef11291b | 340 | if (dmas & DMA_STAT_ERR) |
f16aea4d | 341 | printk(KERN_ERR "%s: DMA error\n", dev->name); |
ef11291b FF |
342 | |
343 | retval = IRQ_HANDLED; | |
344 | } else | |
345 | retval = IRQ_NONE; | |
346 | ||
347 | return retval; | |
348 | } | |
349 | ||
350 | static int korina_rx(struct net_device *dev, int limit) | |
351 | { | |
352 | struct korina_private *lp = netdev_priv(dev); | |
353 | struct dma_desc *rd = &lp->rd_ring[lp->rx_next_done]; | |
354 | struct sk_buff *skb, *skb_new; | |
355 | u8 *pkt_buf; | |
4cf83b66 | 356 | u32 devcs, pkt_len, dmas; |
ef11291b FF |
357 | int count; |
358 | ||
359 | dma_cache_inv((u32)rd, sizeof(*rd)); | |
360 | ||
361 | for (count = 0; count < limit; count++) { | |
4cf83b66 PS |
362 | skb = lp->rx_skb[lp->rx_next_done]; |
363 | skb_new = NULL; | |
ef11291b FF |
364 | |
365 | devcs = rd->devcs; | |
366 | ||
4cf83b66 PS |
367 | if ((KORINA_RBSIZE - (u32)DMA_COUNT(rd->control)) == 0) |
368 | break; | |
369 | ||
ef11291b FF |
370 | /* Update statistics counters */ |
371 | if (devcs & ETH_RX_CRC) | |
372 | dev->stats.rx_crc_errors++; | |
373 | if (devcs & ETH_RX_LOR) | |
374 | dev->stats.rx_length_errors++; | |
375 | if (devcs & ETH_RX_LE) | |
376 | dev->stats.rx_length_errors++; | |
377 | if (devcs & ETH_RX_OVR) | |
378 | dev->stats.rx_over_errors++; | |
379 | if (devcs & ETH_RX_CV) | |
380 | dev->stats.rx_frame_errors++; | |
381 | if (devcs & ETH_RX_CES) | |
382 | dev->stats.rx_length_errors++; | |
383 | if (devcs & ETH_RX_MP) | |
384 | dev->stats.multicast++; | |
385 | ||
386 | if ((devcs & ETH_RX_LD) != ETH_RX_LD) { | |
387 | /* check that this is a whole packet | |
388 | * WARNING: DMA_FD bit incorrectly set | |
389 | * in Rc32434 (errata ref #077) */ | |
390 | dev->stats.rx_errors++; | |
391 | dev->stats.rx_dropped++; | |
4cf83b66 | 392 | } else if ((devcs & ETH_RX_ROK)) { |
ef11291b | 393 | pkt_len = RCVPKT_LENGTH(devcs); |
4cf83b66 PS |
394 | |
395 | /* must be the (first and) last | |
396 | * descriptor then */ | |
397 | pkt_buf = (u8 *)lp->rx_skb[lp->rx_next_done]->data; | |
398 | ||
399 | /* invalidate the cache */ | |
400 | dma_cache_inv((unsigned long)pkt_buf, pkt_len - 4); | |
401 | ||
402 | /* Malloc up new buffer. */ | |
89d71a66 | 403 | skb_new = netdev_alloc_skb_ip_align(dev, KORINA_RBSIZE); |
4cf83b66 PS |
404 | |
405 | if (!skb_new) | |
406 | break; | |
407 | /* Do not count the CRC */ | |
408 | skb_put(skb, pkt_len - 4); | |
409 | skb->protocol = eth_type_trans(skb, dev); | |
410 | ||
411 | /* Pass the packet to upper layers */ | |
412 | netif_receive_skb(skb); | |
413 | dev->stats.rx_packets++; | |
414 | dev->stats.rx_bytes += pkt_len; | |
415 | ||
416 | /* Update the mcast stats */ | |
417 | if (devcs & ETH_RX_MP) | |
418 | dev->stats.multicast++; | |
419 | ||
420 | lp->rx_skb[lp->rx_next_done] = skb_new; | |
ef11291b | 421 | } |
4cf83b66 PS |
422 | |
423 | rd->devcs = 0; | |
424 | ||
425 | /* Restore descriptor's curr_addr */ | |
426 | if (skb_new) | |
427 | rd->ca = CPHYSADDR(skb_new->data); | |
428 | else | |
429 | rd->ca = CPHYSADDR(skb->data); | |
430 | ||
431 | rd->control = DMA_COUNT(KORINA_RBSIZE) | | |
432 | DMA_DESC_COD | DMA_DESC_IOD; | |
433 | lp->rd_ring[(lp->rx_next_done - 1) & | |
434 | KORINA_RDS_MASK].control &= | |
435 | ~DMA_DESC_COD; | |
436 | ||
437 | lp->rx_next_done = (lp->rx_next_done + 1) & KORINA_RDS_MASK; | |
438 | dma_cache_wback((u32)rd, sizeof(*rd)); | |
439 | rd = &lp->rd_ring[lp->rx_next_done]; | |
440 | writel(~DMA_STAT_DONE, &lp->rx_dma_regs->dmas); | |
ef11291b FF |
441 | } |
442 | ||
443 | dmas = readl(&lp->rx_dma_regs->dmas); | |
444 | ||
445 | if (dmas & DMA_STAT_HALT) { | |
446 | writel(~(DMA_STAT_HALT | DMA_STAT_ERR), | |
447 | &lp->rx_dma_regs->dmas); | |
448 | ||
449 | lp->dma_halt_cnt++; | |
450 | rd->devcs = 0; | |
451 | skb = lp->rx_skb[lp->rx_next_done]; | |
452 | rd->ca = CPHYSADDR(skb->data); | |
453 | dma_cache_wback((u32)rd, sizeof(*rd)); | |
454 | korina_chain_rx(lp, rd); | |
455 | } | |
456 | ||
457 | return count; | |
458 | } | |
459 | ||
460 | static int korina_poll(struct napi_struct *napi, int budget) | |
461 | { | |
462 | struct korina_private *lp = | |
463 | container_of(napi, struct korina_private, napi); | |
464 | struct net_device *dev = lp->dev; | |
465 | int work_done; | |
466 | ||
467 | work_done = korina_rx(dev, budget); | |
468 | if (work_done < budget) { | |
288379f0 | 469 | napi_complete(napi); |
ef11291b FF |
470 | |
471 | writel(readl(&lp->rx_dma_regs->dmasm) & | |
472 | ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR), | |
473 | &lp->rx_dma_regs->dmasm); | |
474 | } | |
475 | return work_done; | |
476 | } | |
477 | ||
478 | /* | |
479 | * Set or clear the multicast filter for this adaptor. | |
480 | */ | |
481 | static void korina_multicast_list(struct net_device *dev) | |
482 | { | |
483 | struct korina_private *lp = netdev_priv(dev); | |
484 | unsigned long flags; | |
f9dcbcc9 | 485 | struct dev_mc_list *dmi; |
ef11291b FF |
486 | u32 recognise = ETH_ARC_AB; /* always accept broadcasts */ |
487 | int i; | |
488 | ||
489 | /* Set promiscuous mode */ | |
490 | if (dev->flags & IFF_PROMISC) | |
491 | recognise |= ETH_ARC_PRO; | |
492 | ||
4cd24eaf | 493 | else if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 4)) |
ef11291b FF |
494 | /* All multicast and broadcast */ |
495 | recognise |= ETH_ARC_AM; | |
496 | ||
497 | /* Build the hash table */ | |
4cd24eaf | 498 | if (netdev_mc_count(dev) > 4) { |
ef11291b FF |
499 | u16 hash_table[4]; |
500 | u32 crc; | |
501 | ||
502 | for (i = 0; i < 4; i++) | |
503 | hash_table[i] = 0; | |
504 | ||
f9dcbcc9 | 505 | netdev_for_each_mc_addr(dmi, dev) { |
ef11291b FF |
506 | char *addrs = dmi->dmi_addr; |
507 | ||
ef11291b FF |
508 | if (!(*addrs & 1)) |
509 | continue; | |
510 | ||
511 | crc = ether_crc_le(6, addrs); | |
512 | crc >>= 26; | |
513 | hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf)); | |
514 | } | |
515 | /* Accept filtered multicast */ | |
516 | recognise |= ETH_ARC_AFM; | |
517 | ||
518 | /* Fill the MAC hash tables with their values */ | |
519 | writel((u32)(hash_table[1] << 16 | hash_table[0]), | |
520 | &lp->eth_regs->ethhash0); | |
521 | writel((u32)(hash_table[3] << 16 | hash_table[2]), | |
522 | &lp->eth_regs->ethhash1); | |
523 | } | |
524 | ||
525 | spin_lock_irqsave(&lp->lock, flags); | |
526 | writel(recognise, &lp->eth_regs->etharc); | |
527 | spin_unlock_irqrestore(&lp->lock, flags); | |
528 | } | |
529 | ||
530 | static void korina_tx(struct net_device *dev) | |
531 | { | |
532 | struct korina_private *lp = netdev_priv(dev); | |
533 | struct dma_desc *td = &lp->td_ring[lp->tx_next_done]; | |
534 | u32 devcs; | |
535 | u32 dmas; | |
536 | ||
537 | spin_lock(&lp->lock); | |
538 | ||
539 | /* Process all desc that are done */ | |
540 | while (IS_DMA_FINISHED(td->control)) { | |
541 | if (lp->tx_full == 1) { | |
542 | netif_wake_queue(dev); | |
543 | lp->tx_full = 0; | |
544 | } | |
545 | ||
546 | devcs = lp->td_ring[lp->tx_next_done].devcs; | |
547 | if ((devcs & (ETH_TX_FD | ETH_TX_LD)) != | |
548 | (ETH_TX_FD | ETH_TX_LD)) { | |
549 | dev->stats.tx_errors++; | |
550 | dev->stats.tx_dropped++; | |
551 | ||
552 | /* Should never happen */ | |
f16aea4d | 553 | printk(KERN_ERR "%s: split tx ignored\n", |
ef11291b FF |
554 | dev->name); |
555 | } else if (devcs & ETH_TX_TOK) { | |
556 | dev->stats.tx_packets++; | |
557 | dev->stats.tx_bytes += | |
558 | lp->tx_skb[lp->tx_next_done]->len; | |
559 | } else { | |
560 | dev->stats.tx_errors++; | |
561 | dev->stats.tx_dropped++; | |
562 | ||
563 | /* Underflow */ | |
564 | if (devcs & ETH_TX_UND) | |
565 | dev->stats.tx_fifo_errors++; | |
566 | ||
567 | /* Oversized frame */ | |
568 | if (devcs & ETH_TX_OF) | |
569 | dev->stats.tx_aborted_errors++; | |
570 | ||
571 | /* Excessive deferrals */ | |
572 | if (devcs & ETH_TX_ED) | |
573 | dev->stats.tx_carrier_errors++; | |
574 | ||
575 | /* Collisions: medium busy */ | |
576 | if (devcs & ETH_TX_EC) | |
577 | dev->stats.collisions++; | |
578 | ||
579 | /* Late collision */ | |
580 | if (devcs & ETH_TX_LC) | |
581 | dev->stats.tx_window_errors++; | |
582 | } | |
583 | ||
584 | /* We must always free the original skb */ | |
585 | if (lp->tx_skb[lp->tx_next_done]) { | |
586 | dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]); | |
587 | lp->tx_skb[lp->tx_next_done] = NULL; | |
588 | } | |
589 | ||
590 | lp->td_ring[lp->tx_next_done].control = DMA_DESC_IOF; | |
591 | lp->td_ring[lp->tx_next_done].devcs = ETH_TX_FD | ETH_TX_LD; | |
592 | lp->td_ring[lp->tx_next_done].link = 0; | |
593 | lp->td_ring[lp->tx_next_done].ca = 0; | |
594 | lp->tx_count--; | |
595 | ||
596 | /* Go on to next transmission */ | |
597 | lp->tx_next_done = (lp->tx_next_done + 1) & KORINA_TDS_MASK; | |
598 | td = &lp->td_ring[lp->tx_next_done]; | |
599 | ||
600 | } | |
601 | ||
602 | /* Clear the DMA status register */ | |
603 | dmas = readl(&lp->tx_dma_regs->dmas); | |
604 | writel(~dmas, &lp->tx_dma_regs->dmas); | |
605 | ||
606 | writel(readl(&lp->tx_dma_regs->dmasm) & | |
607 | ~(DMA_STAT_FINI | DMA_STAT_ERR), | |
608 | &lp->tx_dma_regs->dmasm); | |
609 | ||
610 | spin_unlock(&lp->lock); | |
611 | } | |
612 | ||
613 | static irqreturn_t | |
614 | korina_tx_dma_interrupt(int irq, void *dev_id) | |
615 | { | |
616 | struct net_device *dev = dev_id; | |
617 | struct korina_private *lp = netdev_priv(dev); | |
618 | u32 dmas, dmasm; | |
619 | irqreturn_t retval; | |
620 | ||
621 | dmas = readl(&lp->tx_dma_regs->dmas); | |
622 | ||
623 | if (dmas & (DMA_STAT_FINI | DMA_STAT_ERR)) { | |
ef11291b FF |
624 | dmasm = readl(&lp->tx_dma_regs->dmasm); |
625 | writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR), | |
626 | &lp->tx_dma_regs->dmasm); | |
627 | ||
60d3f982 PS |
628 | korina_tx(dev); |
629 | ||
ef11291b FF |
630 | if (lp->tx_chain_status == desc_filled && |
631 | (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) { | |
632 | writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), | |
633 | &(lp->tx_dma_regs->dmandptr)); | |
634 | lp->tx_chain_status = desc_empty; | |
635 | lp->tx_chain_head = lp->tx_chain_tail; | |
636 | dev->trans_start = jiffies; | |
637 | } | |
638 | if (dmas & DMA_STAT_ERR) | |
f16aea4d | 639 | printk(KERN_ERR "%s: DMA error\n", dev->name); |
ef11291b FF |
640 | |
641 | retval = IRQ_HANDLED; | |
642 | } else | |
643 | retval = IRQ_NONE; | |
644 | ||
645 | return retval; | |
646 | } | |
647 | ||
648 | ||
649 | static void korina_check_media(struct net_device *dev, unsigned int init_media) | |
650 | { | |
651 | struct korina_private *lp = netdev_priv(dev); | |
652 | ||
653 | mii_check_media(&lp->mii_if, 0, init_media); | |
654 | ||
655 | if (lp->mii_if.full_duplex) | |
656 | writel(readl(&lp->eth_regs->ethmac2) | ETH_MAC2_FD, | |
657 | &lp->eth_regs->ethmac2); | |
658 | else | |
659 | writel(readl(&lp->eth_regs->ethmac2) & ~ETH_MAC2_FD, | |
660 | &lp->eth_regs->ethmac2); | |
661 | } | |
662 | ||
4d5ef9f0 FF |
663 | static void korina_poll_media(unsigned long data) |
664 | { | |
665 | struct net_device *dev = (struct net_device *) data; | |
666 | struct korina_private *lp = netdev_priv(dev); | |
667 | ||
668 | korina_check_media(dev, 0); | |
669 | mod_timer(&lp->media_check_timer, jiffies + HZ); | |
670 | } | |
671 | ||
ef11291b FF |
672 | static void korina_set_carrier(struct mii_if_info *mii) |
673 | { | |
674 | if (mii->force_media) { | |
675 | /* autoneg is off: Link is always assumed to be up */ | |
676 | if (!netif_carrier_ok(mii->dev)) | |
677 | netif_carrier_on(mii->dev); | |
678 | } else /* Let MMI library update carrier status */ | |
679 | korina_check_media(mii->dev, 0); | |
680 | } | |
681 | ||
682 | static int korina_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
683 | { | |
684 | struct korina_private *lp = netdev_priv(dev); | |
685 | struct mii_ioctl_data *data = if_mii(rq); | |
686 | int rc; | |
687 | ||
688 | if (!netif_running(dev)) | |
689 | return -EINVAL; | |
690 | spin_lock_irq(&lp->lock); | |
691 | rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL); | |
692 | spin_unlock_irq(&lp->lock); | |
693 | korina_set_carrier(&lp->mii_if); | |
694 | ||
695 | return rc; | |
696 | } | |
697 | ||
698 | /* ethtool helpers */ | |
699 | static void netdev_get_drvinfo(struct net_device *dev, | |
700 | struct ethtool_drvinfo *info) | |
701 | { | |
702 | struct korina_private *lp = netdev_priv(dev); | |
703 | ||
704 | strcpy(info->driver, DRV_NAME); | |
705 | strcpy(info->version, DRV_VERSION); | |
706 | strcpy(info->bus_info, lp->dev->name); | |
707 | } | |
708 | ||
709 | static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
710 | { | |
711 | struct korina_private *lp = netdev_priv(dev); | |
712 | int rc; | |
713 | ||
714 | spin_lock_irq(&lp->lock); | |
715 | rc = mii_ethtool_gset(&lp->mii_if, cmd); | |
716 | spin_unlock_irq(&lp->lock); | |
717 | ||
718 | return rc; | |
719 | } | |
720 | ||
721 | static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
722 | { | |
723 | struct korina_private *lp = netdev_priv(dev); | |
724 | int rc; | |
725 | ||
726 | spin_lock_irq(&lp->lock); | |
727 | rc = mii_ethtool_sset(&lp->mii_if, cmd); | |
728 | spin_unlock_irq(&lp->lock); | |
729 | korina_set_carrier(&lp->mii_if); | |
730 | ||
731 | return rc; | |
732 | } | |
733 | ||
734 | static u32 netdev_get_link(struct net_device *dev) | |
735 | { | |
736 | struct korina_private *lp = netdev_priv(dev); | |
737 | ||
738 | return mii_link_ok(&lp->mii_if); | |
739 | } | |
740 | ||
0fc0b732 | 741 | static const struct ethtool_ops netdev_ethtool_ops = { |
ef11291b FF |
742 | .get_drvinfo = netdev_get_drvinfo, |
743 | .get_settings = netdev_get_settings, | |
744 | .set_settings = netdev_set_settings, | |
745 | .get_link = netdev_get_link, | |
746 | }; | |
747 | ||
7010837a | 748 | static int korina_alloc_ring(struct net_device *dev) |
ef11291b FF |
749 | { |
750 | struct korina_private *lp = netdev_priv(dev); | |
e85bf47e | 751 | struct sk_buff *skb; |
ef11291b FF |
752 | int i; |
753 | ||
754 | /* Initialize the transmit descriptors */ | |
755 | for (i = 0; i < KORINA_NUM_TDS; i++) { | |
756 | lp->td_ring[i].control = DMA_DESC_IOF; | |
757 | lp->td_ring[i].devcs = ETH_TX_FD | ETH_TX_LD; | |
758 | lp->td_ring[i].ca = 0; | |
759 | lp->td_ring[i].link = 0; | |
760 | } | |
761 | lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = | |
762 | lp->tx_full = lp->tx_count = 0; | |
763 | lp->tx_chain_status = desc_empty; | |
764 | ||
765 | /* Initialize the receive descriptors */ | |
766 | for (i = 0; i < KORINA_NUM_RDS; i++) { | |
ef11291b FF |
767 | skb = dev_alloc_skb(KORINA_RBSIZE + 2); |
768 | if (!skb) | |
7010837a | 769 | return -ENOMEM; |
ef11291b FF |
770 | skb_reserve(skb, 2); |
771 | lp->rx_skb[i] = skb; | |
772 | lp->rd_ring[i].control = DMA_DESC_IOD | | |
773 | DMA_COUNT(KORINA_RBSIZE); | |
774 | lp->rd_ring[i].devcs = 0; | |
775 | lp->rd_ring[i].ca = CPHYSADDR(skb->data); | |
776 | lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]); | |
777 | } | |
778 | ||
6a2fe983 PS |
779 | /* loop back receive descriptors, so the last |
780 | * descriptor points to the first one */ | |
781 | lp->rd_ring[i - 1].link = CPHYSADDR(&lp->rd_ring[0]); | |
782 | lp->rd_ring[i - 1].control |= DMA_DESC_COD; | |
ef11291b | 783 | |
6a2fe983 | 784 | lp->rx_next_done = 0; |
ef11291b FF |
785 | lp->rx_chain_head = 0; |
786 | lp->rx_chain_tail = 0; | |
787 | lp->rx_chain_status = desc_empty; | |
7010837a PS |
788 | |
789 | return 0; | |
ef11291b FF |
790 | } |
791 | ||
792 | static void korina_free_ring(struct net_device *dev) | |
793 | { | |
794 | struct korina_private *lp = netdev_priv(dev); | |
795 | int i; | |
796 | ||
797 | for (i = 0; i < KORINA_NUM_RDS; i++) { | |
798 | lp->rd_ring[i].control = 0; | |
799 | if (lp->rx_skb[i]) | |
800 | dev_kfree_skb_any(lp->rx_skb[i]); | |
801 | lp->rx_skb[i] = NULL; | |
802 | } | |
803 | ||
804 | for (i = 0; i < KORINA_NUM_TDS; i++) { | |
805 | lp->td_ring[i].control = 0; | |
806 | if (lp->tx_skb[i]) | |
807 | dev_kfree_skb_any(lp->tx_skb[i]); | |
808 | lp->tx_skb[i] = NULL; | |
809 | } | |
810 | } | |
811 | ||
812 | /* | |
813 | * Initialize the RC32434 ethernet controller. | |
814 | */ | |
815 | static int korina_init(struct net_device *dev) | |
816 | { | |
817 | struct korina_private *lp = netdev_priv(dev); | |
818 | ||
819 | /* Disable DMA */ | |
820 | korina_abort_tx(dev); | |
821 | korina_abort_rx(dev); | |
822 | ||
823 | /* reset ethernet logic */ | |
824 | writel(0, &lp->eth_regs->ethintfc); | |
825 | while ((readl(&lp->eth_regs->ethintfc) & ETH_INT_FC_RIP)) | |
826 | dev->trans_start = jiffies; | |
827 | ||
828 | /* Enable Ethernet Interface */ | |
829 | writel(ETH_INT_FC_EN, &lp->eth_regs->ethintfc); | |
830 | ||
831 | /* Allocate rings */ | |
7010837a PS |
832 | if (korina_alloc_ring(dev)) { |
833 | printk(KERN_ERR "%s: descriptor allocation failed\n", dev->name); | |
834 | korina_free_ring(dev); | |
835 | return -ENOMEM; | |
836 | } | |
ef11291b FF |
837 | |
838 | writel(0, &lp->rx_dma_regs->dmas); | |
839 | /* Start Rx DMA */ | |
840 | korina_start_rx(lp, &lp->rd_ring[0]); | |
841 | ||
842 | writel(readl(&lp->tx_dma_regs->dmasm) & | |
843 | ~(DMA_STAT_FINI | DMA_STAT_ERR), | |
844 | &lp->tx_dma_regs->dmasm); | |
845 | writel(readl(&lp->rx_dma_regs->dmasm) & | |
846 | ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR), | |
847 | &lp->rx_dma_regs->dmasm); | |
848 | ||
849 | /* Accept only packets destined for this Ethernet device address */ | |
850 | writel(ETH_ARC_AB, &lp->eth_regs->etharc); | |
851 | ||
852 | /* Set all Ether station address registers to their initial values */ | |
853 | writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0); | |
854 | writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0); | |
855 | ||
856 | writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1); | |
857 | writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1); | |
858 | ||
859 | writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2); | |
860 | writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2); | |
861 | ||
862 | writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3); | |
863 | writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3); | |
864 | ||
865 | ||
866 | /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */ | |
867 | writel(ETH_MAC2_PE | ETH_MAC2_CEN | ETH_MAC2_FD, | |
868 | &lp->eth_regs->ethmac2); | |
869 | ||
870 | /* Back to back inter-packet-gap */ | |
871 | writel(0x15, &lp->eth_regs->ethipgt); | |
872 | /* Non - Back to back inter-packet-gap */ | |
873 | writel(0x12, &lp->eth_regs->ethipgr); | |
874 | ||
875 | /* Management Clock Prescaler Divisor | |
876 | * Clock independent setting */ | |
877 | writel(((idt_cpu_freq) / MII_CLOCK + 1) & ~1, | |
878 | &lp->eth_regs->ethmcp); | |
879 | ||
880 | /* don't transmit until fifo contains 48b */ | |
881 | writel(48, &lp->eth_regs->ethfifott); | |
882 | ||
883 | writel(ETH_MAC1_RE, &lp->eth_regs->ethmac1); | |
884 | ||
885 | napi_enable(&lp->napi); | |
886 | netif_start_queue(dev); | |
887 | ||
888 | return 0; | |
889 | } | |
890 | ||
891 | /* | |
892 | * Restart the RC32434 ethernet controller. | |
893 | * FIXME: check the return status where we call it | |
894 | */ | |
895 | static int korina_restart(struct net_device *dev) | |
896 | { | |
897 | struct korina_private *lp = netdev_priv(dev); | |
e3152ab9 | 898 | int ret; |
ef11291b FF |
899 | |
900 | /* | |
901 | * Disable interrupts | |
902 | */ | |
903 | disable_irq(lp->rx_irq); | |
904 | disable_irq(lp->tx_irq); | |
905 | disable_irq(lp->ovr_irq); | |
906 | disable_irq(lp->und_irq); | |
907 | ||
908 | writel(readl(&lp->tx_dma_regs->dmasm) | | |
909 | DMA_STAT_FINI | DMA_STAT_ERR, | |
910 | &lp->tx_dma_regs->dmasm); | |
911 | writel(readl(&lp->rx_dma_regs->dmasm) | | |
912 | DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR, | |
913 | &lp->rx_dma_regs->dmasm); | |
914 | ||
915 | korina_free_ring(dev); | |
916 | ||
beb0babf PS |
917 | napi_disable(&lp->napi); |
918 | ||
ef11291b FF |
919 | ret = korina_init(dev); |
920 | if (ret < 0) { | |
f16aea4d | 921 | printk(KERN_ERR "%s: cannot restart device\n", dev->name); |
ef11291b FF |
922 | return ret; |
923 | } | |
924 | korina_multicast_list(dev); | |
925 | ||
926 | enable_irq(lp->und_irq); | |
927 | enable_irq(lp->ovr_irq); | |
928 | enable_irq(lp->tx_irq); | |
929 | enable_irq(lp->rx_irq); | |
930 | ||
931 | return ret; | |
932 | } | |
933 | ||
934 | static void korina_clear_and_restart(struct net_device *dev, u32 value) | |
935 | { | |
936 | struct korina_private *lp = netdev_priv(dev); | |
937 | ||
938 | netif_stop_queue(dev); | |
939 | writel(value, &lp->eth_regs->ethintfc); | |
940 | korina_restart(dev); | |
941 | } | |
942 | ||
943 | /* Ethernet Tx Underflow interrupt */ | |
944 | static irqreturn_t korina_und_interrupt(int irq, void *dev_id) | |
945 | { | |
946 | struct net_device *dev = dev_id; | |
947 | struct korina_private *lp = netdev_priv(dev); | |
948 | unsigned int und; | |
949 | ||
950 | spin_lock(&lp->lock); | |
951 | ||
952 | und = readl(&lp->eth_regs->ethintfc); | |
953 | ||
954 | if (und & ETH_INT_FC_UND) | |
955 | korina_clear_and_restart(dev, und & ~ETH_INT_FC_UND); | |
956 | ||
957 | spin_unlock(&lp->lock); | |
958 | ||
959 | return IRQ_HANDLED; | |
960 | } | |
961 | ||
962 | static void korina_tx_timeout(struct net_device *dev) | |
963 | { | |
964 | struct korina_private *lp = netdev_priv(dev); | |
965 | unsigned long flags; | |
966 | ||
967 | spin_lock_irqsave(&lp->lock, flags); | |
968 | korina_restart(dev); | |
969 | spin_unlock_irqrestore(&lp->lock, flags); | |
970 | } | |
971 | ||
972 | /* Ethernet Rx Overflow interrupt */ | |
973 | static irqreturn_t | |
974 | korina_ovr_interrupt(int irq, void *dev_id) | |
975 | { | |
976 | struct net_device *dev = dev_id; | |
977 | struct korina_private *lp = netdev_priv(dev); | |
978 | unsigned int ovr; | |
979 | ||
980 | spin_lock(&lp->lock); | |
981 | ovr = readl(&lp->eth_regs->ethintfc); | |
982 | ||
983 | if (ovr & ETH_INT_FC_OVR) | |
984 | korina_clear_and_restart(dev, ovr & ~ETH_INT_FC_OVR); | |
985 | ||
986 | spin_unlock(&lp->lock); | |
987 | ||
988 | return IRQ_HANDLED; | |
989 | } | |
990 | ||
991 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
992 | static void korina_poll_controller(struct net_device *dev) | |
993 | { | |
994 | disable_irq(dev->irq); | |
995 | korina_tx_dma_interrupt(dev->irq, dev); | |
996 | enable_irq(dev->irq); | |
997 | } | |
998 | #endif | |
999 | ||
1000 | static int korina_open(struct net_device *dev) | |
1001 | { | |
1002 | struct korina_private *lp = netdev_priv(dev); | |
e3152ab9 | 1003 | int ret; |
ef11291b FF |
1004 | |
1005 | /* Initialize */ | |
1006 | ret = korina_init(dev); | |
1007 | if (ret < 0) { | |
f16aea4d | 1008 | printk(KERN_ERR "%s: cannot open device\n", dev->name); |
ef11291b FF |
1009 | goto out; |
1010 | } | |
1011 | ||
1012 | /* Install the interrupt handler | |
1013 | * that handles the Done Finished | |
1014 | * Ovr and Und Events */ | |
a0607fd3 | 1015 | ret = request_irq(lp->rx_irq, korina_rx_dma_interrupt, |
1c5625cf | 1016 | IRQF_DISABLED, "Korina ethernet Rx", dev); |
ef11291b | 1017 | if (ret < 0) { |
f16aea4d | 1018 | printk(KERN_ERR "%s: unable to get Rx DMA IRQ %d\n", |
ef11291b FF |
1019 | dev->name, lp->rx_irq); |
1020 | goto err_release; | |
1021 | } | |
a0607fd3 | 1022 | ret = request_irq(lp->tx_irq, korina_tx_dma_interrupt, |
1c5625cf | 1023 | IRQF_DISABLED, "Korina ethernet Tx", dev); |
ef11291b | 1024 | if (ret < 0) { |
f16aea4d | 1025 | printk(KERN_ERR "%s: unable to get Tx DMA IRQ %d\n", |
ef11291b FF |
1026 | dev->name, lp->tx_irq); |
1027 | goto err_free_rx_irq; | |
1028 | } | |
1029 | ||
1030 | /* Install handler for overrun error. */ | |
a0607fd3 | 1031 | ret = request_irq(lp->ovr_irq, korina_ovr_interrupt, |
1c5625cf | 1032 | IRQF_DISABLED, "Ethernet Overflow", dev); |
ef11291b | 1033 | if (ret < 0) { |
f16aea4d | 1034 | printk(KERN_ERR "%s: unable to get OVR IRQ %d\n", |
ef11291b FF |
1035 | dev->name, lp->ovr_irq); |
1036 | goto err_free_tx_irq; | |
1037 | } | |
1038 | ||
1039 | /* Install handler for underflow error. */ | |
a0607fd3 | 1040 | ret = request_irq(lp->und_irq, korina_und_interrupt, |
1c5625cf | 1041 | IRQF_DISABLED, "Ethernet Underflow", dev); |
ef11291b | 1042 | if (ret < 0) { |
f16aea4d | 1043 | printk(KERN_ERR "%s: unable to get UND IRQ %d\n", |
ef11291b FF |
1044 | dev->name, lp->und_irq); |
1045 | goto err_free_ovr_irq; | |
1046 | } | |
4d5ef9f0 | 1047 | mod_timer(&lp->media_check_timer, jiffies + 1); |
751c2e47 FR |
1048 | out: |
1049 | return ret; | |
ef11291b FF |
1050 | |
1051 | err_free_ovr_irq: | |
1052 | free_irq(lp->ovr_irq, dev); | |
1053 | err_free_tx_irq: | |
1054 | free_irq(lp->tx_irq, dev); | |
1055 | err_free_rx_irq: | |
1056 | free_irq(lp->rx_irq, dev); | |
1057 | err_release: | |
1058 | korina_free_ring(dev); | |
1059 | goto out; | |
ef11291b FF |
1060 | } |
1061 | ||
1062 | static int korina_close(struct net_device *dev) | |
1063 | { | |
1064 | struct korina_private *lp = netdev_priv(dev); | |
1065 | u32 tmp; | |
1066 | ||
4d5ef9f0 FF |
1067 | del_timer(&lp->media_check_timer); |
1068 | ||
ef11291b FF |
1069 | /* Disable interrupts */ |
1070 | disable_irq(lp->rx_irq); | |
1071 | disable_irq(lp->tx_irq); | |
1072 | disable_irq(lp->ovr_irq); | |
1073 | disable_irq(lp->und_irq); | |
1074 | ||
1075 | korina_abort_tx(dev); | |
1076 | tmp = readl(&lp->tx_dma_regs->dmasm); | |
1077 | tmp = tmp | DMA_STAT_FINI | DMA_STAT_ERR; | |
1078 | writel(tmp, &lp->tx_dma_regs->dmasm); | |
1079 | ||
1080 | korina_abort_rx(dev); | |
1081 | tmp = readl(&lp->rx_dma_regs->dmasm); | |
1082 | tmp = tmp | DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR; | |
1083 | writel(tmp, &lp->rx_dma_regs->dmasm); | |
1084 | ||
1085 | korina_free_ring(dev); | |
1086 | ||
beb0babf PS |
1087 | napi_disable(&lp->napi); |
1088 | ||
ef11291b FF |
1089 | free_irq(lp->rx_irq, dev); |
1090 | free_irq(lp->tx_irq, dev); | |
1091 | free_irq(lp->ovr_irq, dev); | |
1092 | free_irq(lp->und_irq, dev); | |
1093 | ||
1094 | return 0; | |
1095 | } | |
1096 | ||
52b031ff AB |
1097 | static const struct net_device_ops korina_netdev_ops = { |
1098 | .ndo_open = korina_open, | |
1099 | .ndo_stop = korina_close, | |
1100 | .ndo_start_xmit = korina_send_packet, | |
1101 | .ndo_set_multicast_list = korina_multicast_list, | |
1102 | .ndo_tx_timeout = korina_tx_timeout, | |
1103 | .ndo_do_ioctl = korina_ioctl, | |
1104 | .ndo_change_mtu = eth_change_mtu, | |
1105 | .ndo_validate_addr = eth_validate_addr, | |
1106 | .ndo_set_mac_address = eth_mac_addr, | |
1107 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1108 | .ndo_poll_controller = korina_poll_controller, | |
1109 | #endif | |
1110 | }; | |
1111 | ||
ef11291b FF |
1112 | static int korina_probe(struct platform_device *pdev) |
1113 | { | |
1114 | struct korina_device *bif = platform_get_drvdata(pdev); | |
1115 | struct korina_private *lp; | |
1116 | struct net_device *dev; | |
1117 | struct resource *r; | |
e3152ab9 | 1118 | int rc; |
ef11291b FF |
1119 | |
1120 | dev = alloc_etherdev(sizeof(struct korina_private)); | |
1121 | if (!dev) { | |
1122 | printk(KERN_ERR DRV_NAME ": alloc_etherdev failed\n"); | |
1123 | return -ENOMEM; | |
1124 | } | |
1125 | SET_NETDEV_DEV(dev, &pdev->dev); | |
ef11291b FF |
1126 | lp = netdev_priv(dev); |
1127 | ||
1128 | bif->dev = dev; | |
1129 | memcpy(dev->dev_addr, bif->mac, 6); | |
1130 | ||
1131 | lp->rx_irq = platform_get_irq_byname(pdev, "korina_rx"); | |
1132 | lp->tx_irq = platform_get_irq_byname(pdev, "korina_tx"); | |
1133 | lp->ovr_irq = platform_get_irq_byname(pdev, "korina_ovr"); | |
1134 | lp->und_irq = platform_get_irq_byname(pdev, "korina_und"); | |
1135 | ||
1136 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_regs"); | |
1137 | dev->base_addr = r->start; | |
1138 | lp->eth_regs = ioremap_nocache(r->start, r->end - r->start); | |
1139 | if (!lp->eth_regs) { | |
f16aea4d | 1140 | printk(KERN_ERR DRV_NAME ": cannot remap registers\n"); |
e3152ab9 | 1141 | rc = -ENXIO; |
ef11291b FF |
1142 | goto probe_err_out; |
1143 | } | |
1144 | ||
1145 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_rx"); | |
1146 | lp->rx_dma_regs = ioremap_nocache(r->start, r->end - r->start); | |
1147 | if (!lp->rx_dma_regs) { | |
f16aea4d | 1148 | printk(KERN_ERR DRV_NAME ": cannot remap Rx DMA registers\n"); |
e3152ab9 | 1149 | rc = -ENXIO; |
ef11291b FF |
1150 | goto probe_err_dma_rx; |
1151 | } | |
1152 | ||
1153 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_tx"); | |
1154 | lp->tx_dma_regs = ioremap_nocache(r->start, r->end - r->start); | |
1155 | if (!lp->tx_dma_regs) { | |
f16aea4d | 1156 | printk(KERN_ERR DRV_NAME ": cannot remap Tx DMA registers\n"); |
e3152ab9 | 1157 | rc = -ENXIO; |
ef11291b FF |
1158 | goto probe_err_dma_tx; |
1159 | } | |
1160 | ||
1161 | lp->td_ring = kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL); | |
1162 | if (!lp->td_ring) { | |
f16aea4d | 1163 | printk(KERN_ERR DRV_NAME ": cannot allocate descriptors\n"); |
e3152ab9 | 1164 | rc = -ENXIO; |
ef11291b FF |
1165 | goto probe_err_td_ring; |
1166 | } | |
1167 | ||
1168 | dma_cache_inv((unsigned long)(lp->td_ring), | |
1169 | TD_RING_SIZE + RD_RING_SIZE); | |
1170 | ||
1171 | /* now convert TD_RING pointer to KSEG1 */ | |
1172 | lp->td_ring = (struct dma_desc *)KSEG1ADDR(lp->td_ring); | |
1173 | lp->rd_ring = &lp->td_ring[KORINA_NUM_TDS]; | |
1174 | ||
1175 | spin_lock_init(&lp->lock); | |
1176 | /* just use the rx dma irq */ | |
1177 | dev->irq = lp->rx_irq; | |
1178 | lp->dev = dev; | |
1179 | ||
52b031ff | 1180 | dev->netdev_ops = &korina_netdev_ops; |
ef11291b | 1181 | dev->ethtool_ops = &netdev_ethtool_ops; |
ef11291b | 1182 | dev->watchdog_timeo = TX_TIMEOUT; |
ef11291b FF |
1183 | netif_napi_add(dev, &lp->napi, korina_poll, 64); |
1184 | ||
1185 | lp->phy_addr = (((lp->rx_irq == 0x2c? 1:0) << 8) | 0x05); | |
1186 | lp->mii_if.dev = dev; | |
1187 | lp->mii_if.mdio_read = mdio_read; | |
1188 | lp->mii_if.mdio_write = mdio_write; | |
1189 | lp->mii_if.phy_id = lp->phy_addr; | |
1190 | lp->mii_if.phy_id_mask = 0x1f; | |
1191 | lp->mii_if.reg_num_mask = 0x1f; | |
1192 | ||
e3152ab9 FR |
1193 | rc = register_netdev(dev); |
1194 | if (rc < 0) { | |
ef11291b | 1195 | printk(KERN_ERR DRV_NAME |
f16aea4d | 1196 | ": cannot register net device: %d\n", rc); |
ef11291b FF |
1197 | goto probe_err_register; |
1198 | } | |
4d5ef9f0 | 1199 | setup_timer(&lp->media_check_timer, korina_poll_media, (unsigned long) dev); |
f16aea4d PS |
1200 | |
1201 | printk(KERN_INFO "%s: " DRV_NAME "-" DRV_VERSION " " DRV_RELDATE "\n", | |
1202 | dev->name); | |
e3152ab9 FR |
1203 | out: |
1204 | return rc; | |
ef11291b FF |
1205 | |
1206 | probe_err_register: | |
1207 | kfree(lp->td_ring); | |
1208 | probe_err_td_ring: | |
1209 | iounmap(lp->tx_dma_regs); | |
1210 | probe_err_dma_tx: | |
1211 | iounmap(lp->rx_dma_regs); | |
1212 | probe_err_dma_rx: | |
1213 | iounmap(lp->eth_regs); | |
1214 | probe_err_out: | |
1215 | free_netdev(dev); | |
e3152ab9 | 1216 | goto out; |
ef11291b FF |
1217 | } |
1218 | ||
1219 | static int korina_remove(struct platform_device *pdev) | |
1220 | { | |
1221 | struct korina_device *bif = platform_get_drvdata(pdev); | |
1222 | struct korina_private *lp = netdev_priv(bif->dev); | |
1223 | ||
e3152ab9 FR |
1224 | iounmap(lp->eth_regs); |
1225 | iounmap(lp->rx_dma_regs); | |
1226 | iounmap(lp->tx_dma_regs); | |
ef11291b FF |
1227 | |
1228 | platform_set_drvdata(pdev, NULL); | |
1229 | unregister_netdev(bif->dev); | |
1230 | free_netdev(bif->dev); | |
1231 | ||
1232 | return 0; | |
1233 | } | |
1234 | ||
1235 | static struct platform_driver korina_driver = { | |
1236 | .driver.name = "korina", | |
1237 | .probe = korina_probe, | |
1238 | .remove = korina_remove, | |
1239 | }; | |
1240 | ||
1241 | static int __init korina_init_module(void) | |
1242 | { | |
1243 | return platform_driver_register(&korina_driver); | |
1244 | } | |
1245 | ||
1246 | static void korina_cleanup_module(void) | |
1247 | { | |
1248 | return platform_driver_unregister(&korina_driver); | |
1249 | } | |
1250 | ||
1251 | module_init(korina_init_module); | |
1252 | module_exit(korina_cleanup_module); | |
1253 | ||
1254 | MODULE_AUTHOR("Philip Rischel <rischelp@idt.com>"); | |
1255 | MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>"); | |
1256 | MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); | |
1257 | MODULE_DESCRIPTION("IDT RC32434 (Korina) Ethernet driver"); | |
1258 | MODULE_LICENSE("GPL"); |