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8ca86fd8 TH |
1 | /** |
2 | * drivers/net/ksx884x.c - Micrel KSZ8841/2 PCI Ethernet driver | |
3 | * | |
4 | * Copyright (c) 2009-2010 Micrel, Inc. | |
5 | * Tristram Ha <Tristram.Ha@micrel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
0dc7d2b3 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
8ca86fd8 TH |
19 | #include <linux/init.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
8ca86fd8 TH |
22 | #include <linux/ioport.h> |
23 | #include <linux/pci.h> | |
24 | #include <linux/proc_fs.h> | |
25 | #include <linux/mii.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/ethtool.h> | |
28 | #include <linux/etherdevice.h> | |
29 | #include <linux/in.h> | |
30 | #include <linux/ip.h> | |
31 | #include <linux/if_vlan.h> | |
32 | #include <linux/crc32.h> | |
33 | #include <linux/sched.h> | |
5a0e3ad6 | 34 | #include <linux/slab.h> |
8ca86fd8 TH |
35 | |
36 | ||
37 | /* DMA Registers */ | |
38 | ||
39 | #define KS_DMA_TX_CTRL 0x0000 | |
40 | #define DMA_TX_ENABLE 0x00000001 | |
41 | #define DMA_TX_CRC_ENABLE 0x00000002 | |
42 | #define DMA_TX_PAD_ENABLE 0x00000004 | |
43 | #define DMA_TX_LOOPBACK 0x00000100 | |
44 | #define DMA_TX_FLOW_ENABLE 0x00000200 | |
45 | #define DMA_TX_CSUM_IP 0x00010000 | |
46 | #define DMA_TX_CSUM_TCP 0x00020000 | |
47 | #define DMA_TX_CSUM_UDP 0x00040000 | |
48 | #define DMA_TX_BURST_SIZE 0x3F000000 | |
49 | ||
50 | #define KS_DMA_RX_CTRL 0x0004 | |
51 | #define DMA_RX_ENABLE 0x00000001 | |
52 | #define KS884X_DMA_RX_MULTICAST 0x00000002 | |
53 | #define DMA_RX_PROMISCUOUS 0x00000004 | |
54 | #define DMA_RX_ERROR 0x00000008 | |
55 | #define DMA_RX_UNICAST 0x00000010 | |
56 | #define DMA_RX_ALL_MULTICAST 0x00000020 | |
57 | #define DMA_RX_BROADCAST 0x00000040 | |
58 | #define DMA_RX_FLOW_ENABLE 0x00000200 | |
59 | #define DMA_RX_CSUM_IP 0x00010000 | |
60 | #define DMA_RX_CSUM_TCP 0x00020000 | |
61 | #define DMA_RX_CSUM_UDP 0x00040000 | |
62 | #define DMA_RX_BURST_SIZE 0x3F000000 | |
63 | ||
64 | #define DMA_BURST_SHIFT 24 | |
65 | #define DMA_BURST_DEFAULT 8 | |
66 | ||
67 | #define KS_DMA_TX_START 0x0008 | |
68 | #define KS_DMA_RX_START 0x000C | |
69 | #define DMA_START 0x00000001 | |
70 | ||
71 | #define KS_DMA_TX_ADDR 0x0010 | |
72 | #define KS_DMA_RX_ADDR 0x0014 | |
73 | ||
74 | #define DMA_ADDR_LIST_MASK 0xFFFFFFFC | |
75 | #define DMA_ADDR_LIST_SHIFT 2 | |
76 | ||
77 | /* MTR0 */ | |
78 | #define KS884X_MULTICAST_0_OFFSET 0x0020 | |
79 | #define KS884X_MULTICAST_1_OFFSET 0x0021 | |
80 | #define KS884X_MULTICAST_2_OFFSET 0x0022 | |
81 | #define KS884x_MULTICAST_3_OFFSET 0x0023 | |
82 | /* MTR1 */ | |
83 | #define KS884X_MULTICAST_4_OFFSET 0x0024 | |
84 | #define KS884X_MULTICAST_5_OFFSET 0x0025 | |
85 | #define KS884X_MULTICAST_6_OFFSET 0x0026 | |
86 | #define KS884X_MULTICAST_7_OFFSET 0x0027 | |
87 | ||
88 | /* Interrupt Registers */ | |
89 | ||
90 | /* INTEN */ | |
91 | #define KS884X_INTERRUPTS_ENABLE 0x0028 | |
92 | /* INTST */ | |
93 | #define KS884X_INTERRUPTS_STATUS 0x002C | |
94 | ||
95 | #define KS884X_INT_RX_STOPPED 0x02000000 | |
96 | #define KS884X_INT_TX_STOPPED 0x04000000 | |
97 | #define KS884X_INT_RX_OVERRUN 0x08000000 | |
98 | #define KS884X_INT_TX_EMPTY 0x10000000 | |
99 | #define KS884X_INT_RX 0x20000000 | |
100 | #define KS884X_INT_TX 0x40000000 | |
101 | #define KS884X_INT_PHY 0x80000000 | |
102 | ||
103 | #define KS884X_INT_RX_MASK \ | |
104 | (KS884X_INT_RX | KS884X_INT_RX_OVERRUN) | |
105 | #define KS884X_INT_TX_MASK \ | |
106 | (KS884X_INT_TX | KS884X_INT_TX_EMPTY) | |
107 | #define KS884X_INT_MASK (KS884X_INT_RX | KS884X_INT_TX | KS884X_INT_PHY) | |
108 | ||
109 | /* MAC Additional Station Address */ | |
110 | ||
111 | /* MAAL0 */ | |
112 | #define KS_ADD_ADDR_0_LO 0x0080 | |
113 | /* MAAH0 */ | |
114 | #define KS_ADD_ADDR_0_HI 0x0084 | |
115 | /* MAAL1 */ | |
116 | #define KS_ADD_ADDR_1_LO 0x0088 | |
117 | /* MAAH1 */ | |
118 | #define KS_ADD_ADDR_1_HI 0x008C | |
119 | /* MAAL2 */ | |
120 | #define KS_ADD_ADDR_2_LO 0x0090 | |
121 | /* MAAH2 */ | |
122 | #define KS_ADD_ADDR_2_HI 0x0094 | |
123 | /* MAAL3 */ | |
124 | #define KS_ADD_ADDR_3_LO 0x0098 | |
125 | /* MAAH3 */ | |
126 | #define KS_ADD_ADDR_3_HI 0x009C | |
127 | /* MAAL4 */ | |
128 | #define KS_ADD_ADDR_4_LO 0x00A0 | |
129 | /* MAAH4 */ | |
130 | #define KS_ADD_ADDR_4_HI 0x00A4 | |
131 | /* MAAL5 */ | |
132 | #define KS_ADD_ADDR_5_LO 0x00A8 | |
133 | /* MAAH5 */ | |
134 | #define KS_ADD_ADDR_5_HI 0x00AC | |
135 | /* MAAL6 */ | |
136 | #define KS_ADD_ADDR_6_LO 0x00B0 | |
137 | /* MAAH6 */ | |
138 | #define KS_ADD_ADDR_6_HI 0x00B4 | |
139 | /* MAAL7 */ | |
140 | #define KS_ADD_ADDR_7_LO 0x00B8 | |
141 | /* MAAH7 */ | |
142 | #define KS_ADD_ADDR_7_HI 0x00BC | |
143 | /* MAAL8 */ | |
144 | #define KS_ADD_ADDR_8_LO 0x00C0 | |
145 | /* MAAH8 */ | |
146 | #define KS_ADD_ADDR_8_HI 0x00C4 | |
147 | /* MAAL9 */ | |
148 | #define KS_ADD_ADDR_9_LO 0x00C8 | |
149 | /* MAAH9 */ | |
150 | #define KS_ADD_ADDR_9_HI 0x00CC | |
151 | /* MAAL10 */ | |
152 | #define KS_ADD_ADDR_A_LO 0x00D0 | |
153 | /* MAAH10 */ | |
154 | #define KS_ADD_ADDR_A_HI 0x00D4 | |
155 | /* MAAL11 */ | |
156 | #define KS_ADD_ADDR_B_LO 0x00D8 | |
157 | /* MAAH11 */ | |
158 | #define KS_ADD_ADDR_B_HI 0x00DC | |
159 | /* MAAL12 */ | |
160 | #define KS_ADD_ADDR_C_LO 0x00E0 | |
161 | /* MAAH12 */ | |
162 | #define KS_ADD_ADDR_C_HI 0x00E4 | |
163 | /* MAAL13 */ | |
164 | #define KS_ADD_ADDR_D_LO 0x00E8 | |
165 | /* MAAH13 */ | |
166 | #define KS_ADD_ADDR_D_HI 0x00EC | |
167 | /* MAAL14 */ | |
168 | #define KS_ADD_ADDR_E_LO 0x00F0 | |
169 | /* MAAH14 */ | |
170 | #define KS_ADD_ADDR_E_HI 0x00F4 | |
171 | /* MAAL15 */ | |
172 | #define KS_ADD_ADDR_F_LO 0x00F8 | |
173 | /* MAAH15 */ | |
174 | #define KS_ADD_ADDR_F_HI 0x00FC | |
175 | ||
176 | #define ADD_ADDR_HI_MASK 0x0000FFFF | |
177 | #define ADD_ADDR_ENABLE 0x80000000 | |
178 | #define ADD_ADDR_INCR 8 | |
179 | ||
180 | /* Miscellaneous Registers */ | |
181 | ||
182 | /* MARL */ | |
183 | #define KS884X_ADDR_0_OFFSET 0x0200 | |
184 | #define KS884X_ADDR_1_OFFSET 0x0201 | |
185 | /* MARM */ | |
186 | #define KS884X_ADDR_2_OFFSET 0x0202 | |
187 | #define KS884X_ADDR_3_OFFSET 0x0203 | |
188 | /* MARH */ | |
189 | #define KS884X_ADDR_4_OFFSET 0x0204 | |
190 | #define KS884X_ADDR_5_OFFSET 0x0205 | |
191 | ||
192 | /* OBCR */ | |
193 | #define KS884X_BUS_CTRL_OFFSET 0x0210 | |
194 | ||
195 | #define BUS_SPEED_125_MHZ 0x0000 | |
196 | #define BUS_SPEED_62_5_MHZ 0x0001 | |
197 | #define BUS_SPEED_41_66_MHZ 0x0002 | |
198 | #define BUS_SPEED_25_MHZ 0x0003 | |
199 | ||
200 | /* EEPCR */ | |
201 | #define KS884X_EEPROM_CTRL_OFFSET 0x0212 | |
202 | ||
203 | #define EEPROM_CHIP_SELECT 0x0001 | |
204 | #define EEPROM_SERIAL_CLOCK 0x0002 | |
205 | #define EEPROM_DATA_OUT 0x0004 | |
206 | #define EEPROM_DATA_IN 0x0008 | |
207 | #define EEPROM_ACCESS_ENABLE 0x0010 | |
208 | ||
209 | /* MBIR */ | |
210 | #define KS884X_MEM_INFO_OFFSET 0x0214 | |
211 | ||
212 | #define RX_MEM_TEST_FAILED 0x0008 | |
213 | #define RX_MEM_TEST_FINISHED 0x0010 | |
214 | #define TX_MEM_TEST_FAILED 0x0800 | |
215 | #define TX_MEM_TEST_FINISHED 0x1000 | |
216 | ||
217 | /* GCR */ | |
218 | #define KS884X_GLOBAL_CTRL_OFFSET 0x0216 | |
219 | #define GLOBAL_SOFTWARE_RESET 0x0001 | |
220 | ||
221 | #define KS8841_POWER_MANAGE_OFFSET 0x0218 | |
222 | ||
223 | /* WFCR */ | |
224 | #define KS8841_WOL_CTRL_OFFSET 0x021A | |
225 | #define KS8841_WOL_MAGIC_ENABLE 0x0080 | |
226 | #define KS8841_WOL_FRAME3_ENABLE 0x0008 | |
227 | #define KS8841_WOL_FRAME2_ENABLE 0x0004 | |
228 | #define KS8841_WOL_FRAME1_ENABLE 0x0002 | |
229 | #define KS8841_WOL_FRAME0_ENABLE 0x0001 | |
230 | ||
231 | /* WF0 */ | |
232 | #define KS8841_WOL_FRAME_CRC_OFFSET 0x0220 | |
233 | #define KS8841_WOL_FRAME_BYTE0_OFFSET 0x0224 | |
234 | #define KS8841_WOL_FRAME_BYTE2_OFFSET 0x0228 | |
235 | ||
236 | /* IACR */ | |
237 | #define KS884X_IACR_P 0x04A0 | |
238 | #define KS884X_IACR_OFFSET KS884X_IACR_P | |
239 | ||
240 | /* IADR1 */ | |
241 | #define KS884X_IADR1_P 0x04A2 | |
242 | #define KS884X_IADR2_P 0x04A4 | |
243 | #define KS884X_IADR3_P 0x04A6 | |
244 | #define KS884X_IADR4_P 0x04A8 | |
245 | #define KS884X_IADR5_P 0x04AA | |
246 | ||
247 | #define KS884X_ACC_CTRL_SEL_OFFSET KS884X_IACR_P | |
248 | #define KS884X_ACC_CTRL_INDEX_OFFSET (KS884X_ACC_CTRL_SEL_OFFSET + 1) | |
249 | ||
250 | #define KS884X_ACC_DATA_0_OFFSET KS884X_IADR4_P | |
251 | #define KS884X_ACC_DATA_1_OFFSET (KS884X_ACC_DATA_0_OFFSET + 1) | |
252 | #define KS884X_ACC_DATA_2_OFFSET KS884X_IADR5_P | |
253 | #define KS884X_ACC_DATA_3_OFFSET (KS884X_ACC_DATA_2_OFFSET + 1) | |
254 | #define KS884X_ACC_DATA_4_OFFSET KS884X_IADR2_P | |
255 | #define KS884X_ACC_DATA_5_OFFSET (KS884X_ACC_DATA_4_OFFSET + 1) | |
256 | #define KS884X_ACC_DATA_6_OFFSET KS884X_IADR3_P | |
257 | #define KS884X_ACC_DATA_7_OFFSET (KS884X_ACC_DATA_6_OFFSET + 1) | |
258 | #define KS884X_ACC_DATA_8_OFFSET KS884X_IADR1_P | |
259 | ||
260 | /* P1MBCR */ | |
261 | #define KS884X_P1MBCR_P 0x04D0 | |
262 | #define KS884X_P1MBSR_P 0x04D2 | |
263 | #define KS884X_PHY1ILR_P 0x04D4 | |
264 | #define KS884X_PHY1IHR_P 0x04D6 | |
265 | #define KS884X_P1ANAR_P 0x04D8 | |
266 | #define KS884X_P1ANLPR_P 0x04DA | |
267 | ||
268 | /* P2MBCR */ | |
269 | #define KS884X_P2MBCR_P 0x04E0 | |
270 | #define KS884X_P2MBSR_P 0x04E2 | |
271 | #define KS884X_PHY2ILR_P 0x04E4 | |
272 | #define KS884X_PHY2IHR_P 0x04E6 | |
273 | #define KS884X_P2ANAR_P 0x04E8 | |
274 | #define KS884X_P2ANLPR_P 0x04EA | |
275 | ||
276 | #define KS884X_PHY_1_CTRL_OFFSET KS884X_P1MBCR_P | |
277 | #define PHY_CTRL_INTERVAL (KS884X_P2MBCR_P - KS884X_P1MBCR_P) | |
278 | ||
279 | #define KS884X_PHY_CTRL_OFFSET 0x00 | |
280 | ||
281 | /* Mode Control Register */ | |
282 | #define PHY_REG_CTRL 0 | |
283 | ||
284 | #define PHY_RESET 0x8000 | |
285 | #define PHY_LOOPBACK 0x4000 | |
286 | #define PHY_SPEED_100MBIT 0x2000 | |
287 | #define PHY_AUTO_NEG_ENABLE 0x1000 | |
288 | #define PHY_POWER_DOWN 0x0800 | |
289 | #define PHY_MII_DISABLE 0x0400 | |
290 | #define PHY_AUTO_NEG_RESTART 0x0200 | |
291 | #define PHY_FULL_DUPLEX 0x0100 | |
292 | #define PHY_COLLISION_TEST 0x0080 | |
293 | #define PHY_HP_MDIX 0x0020 | |
294 | #define PHY_FORCE_MDIX 0x0010 | |
295 | #define PHY_AUTO_MDIX_DISABLE 0x0008 | |
296 | #define PHY_REMOTE_FAULT_DISABLE 0x0004 | |
297 | #define PHY_TRANSMIT_DISABLE 0x0002 | |
298 | #define PHY_LED_DISABLE 0x0001 | |
299 | ||
300 | #define KS884X_PHY_STATUS_OFFSET 0x02 | |
301 | ||
302 | /* Mode Status Register */ | |
303 | #define PHY_REG_STATUS 1 | |
304 | ||
305 | #define PHY_100BT4_CAPABLE 0x8000 | |
306 | #define PHY_100BTX_FD_CAPABLE 0x4000 | |
307 | #define PHY_100BTX_CAPABLE 0x2000 | |
308 | #define PHY_10BT_FD_CAPABLE 0x1000 | |
309 | #define PHY_10BT_CAPABLE 0x0800 | |
310 | #define PHY_MII_SUPPRESS_CAPABLE 0x0040 | |
311 | #define PHY_AUTO_NEG_ACKNOWLEDGE 0x0020 | |
312 | #define PHY_REMOTE_FAULT 0x0010 | |
313 | #define PHY_AUTO_NEG_CAPABLE 0x0008 | |
314 | #define PHY_LINK_STATUS 0x0004 | |
315 | #define PHY_JABBER_DETECT 0x0002 | |
316 | #define PHY_EXTENDED_CAPABILITY 0x0001 | |
317 | ||
318 | #define KS884X_PHY_ID_1_OFFSET 0x04 | |
319 | #define KS884X_PHY_ID_2_OFFSET 0x06 | |
320 | ||
321 | /* PHY Identifier Registers */ | |
322 | #define PHY_REG_ID_1 2 | |
323 | #define PHY_REG_ID_2 3 | |
324 | ||
325 | #define KS884X_PHY_AUTO_NEG_OFFSET 0x08 | |
326 | ||
327 | /* Auto-Negotiation Advertisement Register */ | |
328 | #define PHY_REG_AUTO_NEGOTIATION 4 | |
329 | ||
330 | #define PHY_AUTO_NEG_NEXT_PAGE 0x8000 | |
331 | #define PHY_AUTO_NEG_REMOTE_FAULT 0x2000 | |
332 | /* Not supported. */ | |
333 | #define PHY_AUTO_NEG_ASYM_PAUSE 0x0800 | |
334 | #define PHY_AUTO_NEG_SYM_PAUSE 0x0400 | |
335 | #define PHY_AUTO_NEG_100BT4 0x0200 | |
336 | #define PHY_AUTO_NEG_100BTX_FD 0x0100 | |
337 | #define PHY_AUTO_NEG_100BTX 0x0080 | |
338 | #define PHY_AUTO_NEG_10BT_FD 0x0040 | |
339 | #define PHY_AUTO_NEG_10BT 0x0020 | |
340 | #define PHY_AUTO_NEG_SELECTOR 0x001F | |
341 | #define PHY_AUTO_NEG_802_3 0x0001 | |
342 | ||
343 | #define PHY_AUTO_NEG_PAUSE (PHY_AUTO_NEG_SYM_PAUSE | PHY_AUTO_NEG_ASYM_PAUSE) | |
344 | ||
345 | #define KS884X_PHY_REMOTE_CAP_OFFSET 0x0A | |
346 | ||
347 | /* Auto-Negotiation Link Partner Ability Register */ | |
348 | #define PHY_REG_REMOTE_CAPABILITY 5 | |
349 | ||
350 | #define PHY_REMOTE_NEXT_PAGE 0x8000 | |
351 | #define PHY_REMOTE_ACKNOWLEDGE 0x4000 | |
352 | #define PHY_REMOTE_REMOTE_FAULT 0x2000 | |
353 | #define PHY_REMOTE_SYM_PAUSE 0x0400 | |
354 | #define PHY_REMOTE_100BTX_FD 0x0100 | |
355 | #define PHY_REMOTE_100BTX 0x0080 | |
356 | #define PHY_REMOTE_10BT_FD 0x0040 | |
357 | #define PHY_REMOTE_10BT 0x0020 | |
358 | ||
359 | /* P1VCT */ | |
360 | #define KS884X_P1VCT_P 0x04F0 | |
361 | #define KS884X_P1PHYCTRL_P 0x04F2 | |
362 | ||
363 | /* P2VCT */ | |
364 | #define KS884X_P2VCT_P 0x04F4 | |
365 | #define KS884X_P2PHYCTRL_P 0x04F6 | |
366 | ||
367 | #define KS884X_PHY_SPECIAL_OFFSET KS884X_P1VCT_P | |
368 | #define PHY_SPECIAL_INTERVAL (KS884X_P2VCT_P - KS884X_P1VCT_P) | |
369 | ||
370 | #define KS884X_PHY_LINK_MD_OFFSET 0x00 | |
371 | ||
372 | #define PHY_START_CABLE_DIAG 0x8000 | |
373 | #define PHY_CABLE_DIAG_RESULT 0x6000 | |
374 | #define PHY_CABLE_STAT_NORMAL 0x0000 | |
375 | #define PHY_CABLE_STAT_OPEN 0x2000 | |
376 | #define PHY_CABLE_STAT_SHORT 0x4000 | |
377 | #define PHY_CABLE_STAT_FAILED 0x6000 | |
378 | #define PHY_CABLE_10M_SHORT 0x1000 | |
379 | #define PHY_CABLE_FAULT_COUNTER 0x01FF | |
380 | ||
381 | #define KS884X_PHY_PHY_CTRL_OFFSET 0x02 | |
382 | ||
383 | #define PHY_STAT_REVERSED_POLARITY 0x0020 | |
384 | #define PHY_STAT_MDIX 0x0010 | |
385 | #define PHY_FORCE_LINK 0x0008 | |
386 | #define PHY_POWER_SAVING_DISABLE 0x0004 | |
387 | #define PHY_REMOTE_LOOPBACK 0x0002 | |
388 | ||
389 | /* SIDER */ | |
390 | #define KS884X_SIDER_P 0x0400 | |
391 | #define KS884X_CHIP_ID_OFFSET KS884X_SIDER_P | |
392 | #define KS884X_FAMILY_ID_OFFSET (KS884X_CHIP_ID_OFFSET + 1) | |
393 | ||
394 | #define REG_FAMILY_ID 0x88 | |
395 | ||
396 | #define REG_CHIP_ID_41 0x8810 | |
397 | #define REG_CHIP_ID_42 0x8800 | |
398 | ||
399 | #define KS884X_CHIP_ID_MASK_41 0xFF10 | |
400 | #define KS884X_CHIP_ID_MASK 0xFFF0 | |
401 | #define KS884X_CHIP_ID_SHIFT 4 | |
402 | #define KS884X_REVISION_MASK 0x000E | |
403 | #define KS884X_REVISION_SHIFT 1 | |
404 | #define KS8842_START 0x0001 | |
405 | ||
406 | #define CHIP_IP_41_M 0x8810 | |
407 | #define CHIP_IP_42_M 0x8800 | |
408 | #define CHIP_IP_61_M 0x8890 | |
409 | #define CHIP_IP_62_M 0x8880 | |
410 | ||
411 | #define CHIP_IP_41_P 0x8850 | |
412 | #define CHIP_IP_42_P 0x8840 | |
413 | #define CHIP_IP_61_P 0x88D0 | |
414 | #define CHIP_IP_62_P 0x88C0 | |
415 | ||
416 | /* SGCR1 */ | |
417 | #define KS8842_SGCR1_P 0x0402 | |
418 | #define KS8842_SWITCH_CTRL_1_OFFSET KS8842_SGCR1_P | |
419 | ||
420 | #define SWITCH_PASS_ALL 0x8000 | |
421 | #define SWITCH_TX_FLOW_CTRL 0x2000 | |
422 | #define SWITCH_RX_FLOW_CTRL 0x1000 | |
423 | #define SWITCH_CHECK_LENGTH 0x0800 | |
424 | #define SWITCH_AGING_ENABLE 0x0400 | |
425 | #define SWITCH_FAST_AGING 0x0200 | |
426 | #define SWITCH_AGGR_BACKOFF 0x0100 | |
427 | #define SWITCH_PASS_PAUSE 0x0008 | |
428 | #define SWITCH_LINK_AUTO_AGING 0x0001 | |
429 | ||
430 | /* SGCR2 */ | |
431 | #define KS8842_SGCR2_P 0x0404 | |
432 | #define KS8842_SWITCH_CTRL_2_OFFSET KS8842_SGCR2_P | |
433 | ||
434 | #define SWITCH_VLAN_ENABLE 0x8000 | |
435 | #define SWITCH_IGMP_SNOOP 0x4000 | |
436 | #define IPV6_MLD_SNOOP_ENABLE 0x2000 | |
437 | #define IPV6_MLD_SNOOP_OPTION 0x1000 | |
438 | #define PRIORITY_SCHEME_SELECT 0x0800 | |
439 | #define SWITCH_MIRROR_RX_TX 0x0100 | |
440 | #define UNICAST_VLAN_BOUNDARY 0x0080 | |
441 | #define MULTICAST_STORM_DISABLE 0x0040 | |
442 | #define SWITCH_BACK_PRESSURE 0x0020 | |
443 | #define FAIR_FLOW_CTRL 0x0010 | |
444 | #define NO_EXC_COLLISION_DROP 0x0008 | |
445 | #define SWITCH_HUGE_PACKET 0x0004 | |
446 | #define SWITCH_LEGAL_PACKET 0x0002 | |
447 | #define SWITCH_BUF_RESERVE 0x0001 | |
448 | ||
449 | /* SGCR3 */ | |
450 | #define KS8842_SGCR3_P 0x0406 | |
451 | #define KS8842_SWITCH_CTRL_3_OFFSET KS8842_SGCR3_P | |
452 | ||
453 | #define BROADCAST_STORM_RATE_LO 0xFF00 | |
454 | #define SWITCH_REPEATER 0x0080 | |
455 | #define SWITCH_HALF_DUPLEX 0x0040 | |
456 | #define SWITCH_FLOW_CTRL 0x0020 | |
457 | #define SWITCH_10_MBIT 0x0010 | |
458 | #define SWITCH_REPLACE_NULL_VID 0x0008 | |
459 | #define BROADCAST_STORM_RATE_HI 0x0007 | |
460 | ||
461 | #define BROADCAST_STORM_RATE 0x07FF | |
462 | ||
463 | /* SGCR4 */ | |
464 | #define KS8842_SGCR4_P 0x0408 | |
465 | ||
466 | /* SGCR5 */ | |
467 | #define KS8842_SGCR5_P 0x040A | |
468 | #define KS8842_SWITCH_CTRL_5_OFFSET KS8842_SGCR5_P | |
469 | ||
470 | #define LED_MODE 0x8200 | |
471 | #define LED_SPEED_DUPLEX_ACT 0x0000 | |
472 | #define LED_SPEED_DUPLEX_LINK_ACT 0x8000 | |
473 | #define LED_DUPLEX_10_100 0x0200 | |
474 | ||
475 | /* SGCR6 */ | |
476 | #define KS8842_SGCR6_P 0x0410 | |
477 | #define KS8842_SWITCH_CTRL_6_OFFSET KS8842_SGCR6_P | |
478 | ||
479 | #define KS8842_PRIORITY_MASK 3 | |
480 | #define KS8842_PRIORITY_SHIFT 2 | |
481 | ||
482 | /* SGCR7 */ | |
483 | #define KS8842_SGCR7_P 0x0412 | |
484 | #define KS8842_SWITCH_CTRL_7_OFFSET KS8842_SGCR7_P | |
485 | ||
486 | #define SWITCH_UNK_DEF_PORT_ENABLE 0x0008 | |
487 | #define SWITCH_UNK_DEF_PORT_3 0x0004 | |
488 | #define SWITCH_UNK_DEF_PORT_2 0x0002 | |
489 | #define SWITCH_UNK_DEF_PORT_1 0x0001 | |
490 | ||
491 | /* MACAR1 */ | |
492 | #define KS8842_MACAR1_P 0x0470 | |
493 | #define KS8842_MACAR2_P 0x0472 | |
494 | #define KS8842_MACAR3_P 0x0474 | |
495 | #define KS8842_MAC_ADDR_1_OFFSET KS8842_MACAR1_P | |
496 | #define KS8842_MAC_ADDR_0_OFFSET (KS8842_MAC_ADDR_1_OFFSET + 1) | |
497 | #define KS8842_MAC_ADDR_3_OFFSET KS8842_MACAR2_P | |
498 | #define KS8842_MAC_ADDR_2_OFFSET (KS8842_MAC_ADDR_3_OFFSET + 1) | |
499 | #define KS8842_MAC_ADDR_5_OFFSET KS8842_MACAR3_P | |
500 | #define KS8842_MAC_ADDR_4_OFFSET (KS8842_MAC_ADDR_5_OFFSET + 1) | |
501 | ||
502 | /* TOSR1 */ | |
503 | #define KS8842_TOSR1_P 0x0480 | |
504 | #define KS8842_TOSR2_P 0x0482 | |
505 | #define KS8842_TOSR3_P 0x0484 | |
506 | #define KS8842_TOSR4_P 0x0486 | |
507 | #define KS8842_TOSR5_P 0x0488 | |
508 | #define KS8842_TOSR6_P 0x048A | |
509 | #define KS8842_TOSR7_P 0x0490 | |
510 | #define KS8842_TOSR8_P 0x0492 | |
511 | #define KS8842_TOS_1_OFFSET KS8842_TOSR1_P | |
512 | #define KS8842_TOS_2_OFFSET KS8842_TOSR2_P | |
513 | #define KS8842_TOS_3_OFFSET KS8842_TOSR3_P | |
514 | #define KS8842_TOS_4_OFFSET KS8842_TOSR4_P | |
515 | #define KS8842_TOS_5_OFFSET KS8842_TOSR5_P | |
516 | #define KS8842_TOS_6_OFFSET KS8842_TOSR6_P | |
517 | ||
518 | #define KS8842_TOS_7_OFFSET KS8842_TOSR7_P | |
519 | #define KS8842_TOS_8_OFFSET KS8842_TOSR8_P | |
520 | ||
521 | /* P1CR1 */ | |
522 | #define KS8842_P1CR1_P 0x0500 | |
523 | #define KS8842_P1CR2_P 0x0502 | |
524 | #define KS8842_P1VIDR_P 0x0504 | |
525 | #define KS8842_P1CR3_P 0x0506 | |
526 | #define KS8842_P1IRCR_P 0x0508 | |
527 | #define KS8842_P1ERCR_P 0x050A | |
528 | #define KS884X_P1SCSLMD_P 0x0510 | |
529 | #define KS884X_P1CR4_P 0x0512 | |
530 | #define KS884X_P1SR_P 0x0514 | |
531 | ||
532 | /* P2CR1 */ | |
533 | #define KS8842_P2CR1_P 0x0520 | |
534 | #define KS8842_P2CR2_P 0x0522 | |
535 | #define KS8842_P2VIDR_P 0x0524 | |
536 | #define KS8842_P2CR3_P 0x0526 | |
537 | #define KS8842_P2IRCR_P 0x0528 | |
538 | #define KS8842_P2ERCR_P 0x052A | |
539 | #define KS884X_P2SCSLMD_P 0x0530 | |
540 | #define KS884X_P2CR4_P 0x0532 | |
541 | #define KS884X_P2SR_P 0x0534 | |
542 | ||
543 | /* P3CR1 */ | |
544 | #define KS8842_P3CR1_P 0x0540 | |
545 | #define KS8842_P3CR2_P 0x0542 | |
546 | #define KS8842_P3VIDR_P 0x0544 | |
547 | #define KS8842_P3CR3_P 0x0546 | |
548 | #define KS8842_P3IRCR_P 0x0548 | |
549 | #define KS8842_P3ERCR_P 0x054A | |
550 | ||
551 | #define KS8842_PORT_1_CTRL_1 KS8842_P1CR1_P | |
552 | #define KS8842_PORT_2_CTRL_1 KS8842_P2CR1_P | |
553 | #define KS8842_PORT_3_CTRL_1 KS8842_P3CR1_P | |
554 | ||
555 | #define PORT_CTRL_ADDR(port, addr) \ | |
556 | (addr = KS8842_PORT_1_CTRL_1 + (port) * \ | |
557 | (KS8842_PORT_2_CTRL_1 - KS8842_PORT_1_CTRL_1)) | |
558 | ||
559 | #define KS8842_PORT_CTRL_1_OFFSET 0x00 | |
560 | ||
561 | #define PORT_BROADCAST_STORM 0x0080 | |
562 | #define PORT_DIFFSERV_ENABLE 0x0040 | |
563 | #define PORT_802_1P_ENABLE 0x0020 | |
564 | #define PORT_BASED_PRIORITY_MASK 0x0018 | |
565 | #define PORT_BASED_PRIORITY_BASE 0x0003 | |
566 | #define PORT_BASED_PRIORITY_SHIFT 3 | |
567 | #define PORT_BASED_PRIORITY_0 0x0000 | |
568 | #define PORT_BASED_PRIORITY_1 0x0008 | |
569 | #define PORT_BASED_PRIORITY_2 0x0010 | |
570 | #define PORT_BASED_PRIORITY_3 0x0018 | |
571 | #define PORT_INSERT_TAG 0x0004 | |
572 | #define PORT_REMOVE_TAG 0x0002 | |
573 | #define PORT_PRIO_QUEUE_ENABLE 0x0001 | |
574 | ||
575 | #define KS8842_PORT_CTRL_2_OFFSET 0x02 | |
576 | ||
577 | #define PORT_INGRESS_VLAN_FILTER 0x4000 | |
578 | #define PORT_DISCARD_NON_VID 0x2000 | |
579 | #define PORT_FORCE_FLOW_CTRL 0x1000 | |
580 | #define PORT_BACK_PRESSURE 0x0800 | |
581 | #define PORT_TX_ENABLE 0x0400 | |
582 | #define PORT_RX_ENABLE 0x0200 | |
583 | #define PORT_LEARN_DISABLE 0x0100 | |
584 | #define PORT_MIRROR_SNIFFER 0x0080 | |
585 | #define PORT_MIRROR_RX 0x0040 | |
586 | #define PORT_MIRROR_TX 0x0020 | |
587 | #define PORT_USER_PRIORITY_CEILING 0x0008 | |
588 | #define PORT_VLAN_MEMBERSHIP 0x0007 | |
589 | ||
590 | #define KS8842_PORT_CTRL_VID_OFFSET 0x04 | |
591 | ||
592 | #define PORT_DEFAULT_VID 0x0001 | |
593 | ||
594 | #define KS8842_PORT_CTRL_3_OFFSET 0x06 | |
595 | ||
596 | #define PORT_INGRESS_LIMIT_MODE 0x000C | |
597 | #define PORT_INGRESS_ALL 0x0000 | |
598 | #define PORT_INGRESS_UNICAST 0x0004 | |
599 | #define PORT_INGRESS_MULTICAST 0x0008 | |
600 | #define PORT_INGRESS_BROADCAST 0x000C | |
601 | #define PORT_COUNT_IFG 0x0002 | |
602 | #define PORT_COUNT_PREAMBLE 0x0001 | |
603 | ||
604 | #define KS8842_PORT_IN_RATE_OFFSET 0x08 | |
605 | #define KS8842_PORT_OUT_RATE_OFFSET 0x0A | |
606 | ||
607 | #define PORT_PRIORITY_RATE 0x0F | |
608 | #define PORT_PRIORITY_RATE_SHIFT 4 | |
609 | ||
610 | #define KS884X_PORT_LINK_MD 0x10 | |
611 | ||
612 | #define PORT_CABLE_10M_SHORT 0x8000 | |
613 | #define PORT_CABLE_DIAG_RESULT 0x6000 | |
614 | #define PORT_CABLE_STAT_NORMAL 0x0000 | |
615 | #define PORT_CABLE_STAT_OPEN 0x2000 | |
616 | #define PORT_CABLE_STAT_SHORT 0x4000 | |
617 | #define PORT_CABLE_STAT_FAILED 0x6000 | |
618 | #define PORT_START_CABLE_DIAG 0x1000 | |
619 | #define PORT_FORCE_LINK 0x0800 | |
620 | #define PORT_POWER_SAVING_DISABLE 0x0400 | |
621 | #define PORT_PHY_REMOTE_LOOPBACK 0x0200 | |
622 | #define PORT_CABLE_FAULT_COUNTER 0x01FF | |
623 | ||
624 | #define KS884X_PORT_CTRL_4_OFFSET 0x12 | |
625 | ||
626 | #define PORT_LED_OFF 0x8000 | |
627 | #define PORT_TX_DISABLE 0x4000 | |
628 | #define PORT_AUTO_NEG_RESTART 0x2000 | |
629 | #define PORT_REMOTE_FAULT_DISABLE 0x1000 | |
630 | #define PORT_POWER_DOWN 0x0800 | |
631 | #define PORT_AUTO_MDIX_DISABLE 0x0400 | |
632 | #define PORT_FORCE_MDIX 0x0200 | |
633 | #define PORT_LOOPBACK 0x0100 | |
634 | #define PORT_AUTO_NEG_ENABLE 0x0080 | |
635 | #define PORT_FORCE_100_MBIT 0x0040 | |
636 | #define PORT_FORCE_FULL_DUPLEX 0x0020 | |
637 | #define PORT_AUTO_NEG_SYM_PAUSE 0x0010 | |
638 | #define PORT_AUTO_NEG_100BTX_FD 0x0008 | |
639 | #define PORT_AUTO_NEG_100BTX 0x0004 | |
640 | #define PORT_AUTO_NEG_10BT_FD 0x0002 | |
641 | #define PORT_AUTO_NEG_10BT 0x0001 | |
642 | ||
643 | #define KS884X_PORT_STATUS_OFFSET 0x14 | |
644 | ||
645 | #define PORT_HP_MDIX 0x8000 | |
646 | #define PORT_REVERSED_POLARITY 0x2000 | |
647 | #define PORT_RX_FLOW_CTRL 0x0800 | |
648 | #define PORT_TX_FLOW_CTRL 0x1000 | |
649 | #define PORT_STATUS_SPEED_100MBIT 0x0400 | |
650 | #define PORT_STATUS_FULL_DUPLEX 0x0200 | |
651 | #define PORT_REMOTE_FAULT 0x0100 | |
652 | #define PORT_MDIX_STATUS 0x0080 | |
653 | #define PORT_AUTO_NEG_COMPLETE 0x0040 | |
654 | #define PORT_STATUS_LINK_GOOD 0x0020 | |
655 | #define PORT_REMOTE_SYM_PAUSE 0x0010 | |
656 | #define PORT_REMOTE_100BTX_FD 0x0008 | |
657 | #define PORT_REMOTE_100BTX 0x0004 | |
658 | #define PORT_REMOTE_10BT_FD 0x0002 | |
659 | #define PORT_REMOTE_10BT 0x0001 | |
660 | ||
661 | /* | |
662 | #define STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF | |
663 | #define STATIC_MAC_TABLE_FWD_PORTS 00-00070000-00000000 | |
664 | #define STATIC_MAC_TABLE_VALID 00-00080000-00000000 | |
665 | #define STATIC_MAC_TABLE_OVERRIDE 00-00100000-00000000 | |
666 | #define STATIC_MAC_TABLE_USE_FID 00-00200000-00000000 | |
667 | #define STATIC_MAC_TABLE_FID 00-03C00000-00000000 | |
668 | */ | |
669 | ||
670 | #define STATIC_MAC_TABLE_ADDR 0x0000FFFF | |
671 | #define STATIC_MAC_TABLE_FWD_PORTS 0x00070000 | |
672 | #define STATIC_MAC_TABLE_VALID 0x00080000 | |
673 | #define STATIC_MAC_TABLE_OVERRIDE 0x00100000 | |
674 | #define STATIC_MAC_TABLE_USE_FID 0x00200000 | |
675 | #define STATIC_MAC_TABLE_FID 0x03C00000 | |
676 | ||
677 | #define STATIC_MAC_FWD_PORTS_SHIFT 16 | |
678 | #define STATIC_MAC_FID_SHIFT 22 | |
679 | ||
680 | /* | |
681 | #define VLAN_TABLE_VID 00-00000000-00000FFF | |
682 | #define VLAN_TABLE_FID 00-00000000-0000F000 | |
683 | #define VLAN_TABLE_MEMBERSHIP 00-00000000-00070000 | |
684 | #define VLAN_TABLE_VALID 00-00000000-00080000 | |
685 | */ | |
686 | ||
687 | #define VLAN_TABLE_VID 0x00000FFF | |
688 | #define VLAN_TABLE_FID 0x0000F000 | |
689 | #define VLAN_TABLE_MEMBERSHIP 0x00070000 | |
690 | #define VLAN_TABLE_VALID 0x00080000 | |
691 | ||
692 | #define VLAN_TABLE_FID_SHIFT 12 | |
693 | #define VLAN_TABLE_MEMBERSHIP_SHIFT 16 | |
694 | ||
695 | /* | |
696 | #define DYNAMIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF | |
697 | #define DYNAMIC_MAC_TABLE_FID 00-000F0000-00000000 | |
698 | #define DYNAMIC_MAC_TABLE_SRC_PORT 00-00300000-00000000 | |
699 | #define DYNAMIC_MAC_TABLE_TIMESTAMP 00-00C00000-00000000 | |
700 | #define DYNAMIC_MAC_TABLE_ENTRIES 03-FF000000-00000000 | |
701 | #define DYNAMIC_MAC_TABLE_MAC_EMPTY 04-00000000-00000000 | |
702 | #define DYNAMIC_MAC_TABLE_RESERVED 78-00000000-00000000 | |
703 | #define DYNAMIC_MAC_TABLE_NOT_READY 80-00000000-00000000 | |
704 | */ | |
705 | ||
706 | #define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF | |
707 | #define DYNAMIC_MAC_TABLE_FID 0x000F0000 | |
708 | #define DYNAMIC_MAC_TABLE_SRC_PORT 0x00300000 | |
709 | #define DYNAMIC_MAC_TABLE_TIMESTAMP 0x00C00000 | |
710 | #define DYNAMIC_MAC_TABLE_ENTRIES 0xFF000000 | |
711 | ||
712 | #define DYNAMIC_MAC_TABLE_ENTRIES_H 0x03 | |
713 | #define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x04 | |
714 | #define DYNAMIC_MAC_TABLE_RESERVED 0x78 | |
715 | #define DYNAMIC_MAC_TABLE_NOT_READY 0x80 | |
716 | ||
717 | #define DYNAMIC_MAC_FID_SHIFT 16 | |
718 | #define DYNAMIC_MAC_SRC_PORT_SHIFT 20 | |
719 | #define DYNAMIC_MAC_TIMESTAMP_SHIFT 22 | |
720 | #define DYNAMIC_MAC_ENTRIES_SHIFT 24 | |
721 | #define DYNAMIC_MAC_ENTRIES_H_SHIFT 8 | |
722 | ||
723 | /* | |
724 | #define MIB_COUNTER_VALUE 00-00000000-3FFFFFFF | |
725 | #define MIB_COUNTER_VALID 00-00000000-40000000 | |
726 | #define MIB_COUNTER_OVERFLOW 00-00000000-80000000 | |
727 | */ | |
728 | ||
729 | #define MIB_COUNTER_VALUE 0x3FFFFFFF | |
730 | #define MIB_COUNTER_VALID 0x40000000 | |
731 | #define MIB_COUNTER_OVERFLOW 0x80000000 | |
732 | ||
733 | #define MIB_PACKET_DROPPED 0x0000FFFF | |
734 | ||
735 | #define KS_MIB_PACKET_DROPPED_TX_0 0x100 | |
736 | #define KS_MIB_PACKET_DROPPED_TX_1 0x101 | |
737 | #define KS_MIB_PACKET_DROPPED_TX 0x102 | |
738 | #define KS_MIB_PACKET_DROPPED_RX_0 0x103 | |
739 | #define KS_MIB_PACKET_DROPPED_RX_1 0x104 | |
740 | #define KS_MIB_PACKET_DROPPED_RX 0x105 | |
741 | ||
742 | /* Change default LED mode. */ | |
743 | #define SET_DEFAULT_LED LED_SPEED_DUPLEX_ACT | |
744 | ||
745 | #define MAC_ADDR_LEN 6 | |
746 | #define MAC_ADDR_ORDER(i) (MAC_ADDR_LEN - 1 - (i)) | |
747 | ||
748 | #define MAX_ETHERNET_BODY_SIZE 1500 | |
749 | #define ETHERNET_HEADER_SIZE 14 | |
750 | ||
751 | #define MAX_ETHERNET_PACKET_SIZE \ | |
752 | (MAX_ETHERNET_BODY_SIZE + ETHERNET_HEADER_SIZE) | |
753 | ||
754 | #define REGULAR_RX_BUF_SIZE (MAX_ETHERNET_PACKET_SIZE + 4) | |
755 | #define MAX_RX_BUF_SIZE (1912 + 4) | |
756 | ||
757 | #define ADDITIONAL_ENTRIES 16 | |
758 | #define MAX_MULTICAST_LIST 32 | |
759 | ||
760 | #define HW_MULTICAST_SIZE 8 | |
761 | ||
762 | #define HW_TO_DEV_PORT(port) (port - 1) | |
763 | ||
764 | enum { | |
765 | media_connected, | |
766 | media_disconnected | |
767 | }; | |
768 | ||
769 | enum { | |
770 | OID_COUNTER_UNKOWN, | |
771 | ||
772 | OID_COUNTER_FIRST, | |
773 | ||
774 | /* total transmit errors */ | |
775 | OID_COUNTER_XMIT_ERROR, | |
776 | ||
777 | /* total receive errors */ | |
778 | OID_COUNTER_RCV_ERROR, | |
779 | ||
780 | OID_COUNTER_LAST | |
781 | }; | |
782 | ||
783 | /* | |
784 | * Hardware descriptor definitions | |
785 | */ | |
786 | ||
787 | #define DESC_ALIGNMENT 16 | |
788 | #define BUFFER_ALIGNMENT 8 | |
789 | ||
790 | #define NUM_OF_RX_DESC 64 | |
791 | #define NUM_OF_TX_DESC 64 | |
792 | ||
793 | #define KS_DESC_RX_FRAME_LEN 0x000007FF | |
794 | #define KS_DESC_RX_FRAME_TYPE 0x00008000 | |
795 | #define KS_DESC_RX_ERROR_CRC 0x00010000 | |
796 | #define KS_DESC_RX_ERROR_RUNT 0x00020000 | |
797 | #define KS_DESC_RX_ERROR_TOO_LONG 0x00040000 | |
798 | #define KS_DESC_RX_ERROR_PHY 0x00080000 | |
799 | #define KS884X_DESC_RX_PORT_MASK 0x00300000 | |
800 | #define KS_DESC_RX_MULTICAST 0x01000000 | |
801 | #define KS_DESC_RX_ERROR 0x02000000 | |
802 | #define KS_DESC_RX_ERROR_CSUM_UDP 0x04000000 | |
803 | #define KS_DESC_RX_ERROR_CSUM_TCP 0x08000000 | |
804 | #define KS_DESC_RX_ERROR_CSUM_IP 0x10000000 | |
805 | #define KS_DESC_RX_LAST 0x20000000 | |
806 | #define KS_DESC_RX_FIRST 0x40000000 | |
807 | #define KS_DESC_RX_ERROR_COND \ | |
808 | (KS_DESC_RX_ERROR_CRC | \ | |
809 | KS_DESC_RX_ERROR_RUNT | \ | |
810 | KS_DESC_RX_ERROR_PHY | \ | |
811 | KS_DESC_RX_ERROR_TOO_LONG) | |
812 | ||
813 | #define KS_DESC_HW_OWNED 0x80000000 | |
814 | ||
815 | #define KS_DESC_BUF_SIZE 0x000007FF | |
816 | #define KS884X_DESC_TX_PORT_MASK 0x00300000 | |
817 | #define KS_DESC_END_OF_RING 0x02000000 | |
818 | #define KS_DESC_TX_CSUM_GEN_UDP 0x04000000 | |
819 | #define KS_DESC_TX_CSUM_GEN_TCP 0x08000000 | |
820 | #define KS_DESC_TX_CSUM_GEN_IP 0x10000000 | |
821 | #define KS_DESC_TX_LAST 0x20000000 | |
822 | #define KS_DESC_TX_FIRST 0x40000000 | |
823 | #define KS_DESC_TX_INTERRUPT 0x80000000 | |
824 | ||
825 | #define KS_DESC_PORT_SHIFT 20 | |
826 | ||
827 | #define KS_DESC_RX_MASK (KS_DESC_BUF_SIZE) | |
828 | ||
829 | #define KS_DESC_TX_MASK \ | |
830 | (KS_DESC_TX_INTERRUPT | \ | |
831 | KS_DESC_TX_FIRST | \ | |
832 | KS_DESC_TX_LAST | \ | |
833 | KS_DESC_TX_CSUM_GEN_IP | \ | |
834 | KS_DESC_TX_CSUM_GEN_TCP | \ | |
835 | KS_DESC_TX_CSUM_GEN_UDP | \ | |
836 | KS_DESC_BUF_SIZE) | |
837 | ||
838 | struct ksz_desc_rx_stat { | |
839 | #ifdef __BIG_ENDIAN_BITFIELD | |
840 | u32 hw_owned:1; | |
841 | u32 first_desc:1; | |
842 | u32 last_desc:1; | |
843 | u32 csum_err_ip:1; | |
844 | u32 csum_err_tcp:1; | |
845 | u32 csum_err_udp:1; | |
846 | u32 error:1; | |
847 | u32 multicast:1; | |
848 | u32 src_port:4; | |
849 | u32 err_phy:1; | |
850 | u32 err_too_long:1; | |
851 | u32 err_runt:1; | |
852 | u32 err_crc:1; | |
853 | u32 frame_type:1; | |
854 | u32 reserved1:4; | |
855 | u32 frame_len:11; | |
856 | #else | |
857 | u32 frame_len:11; | |
858 | u32 reserved1:4; | |
859 | u32 frame_type:1; | |
860 | u32 err_crc:1; | |
861 | u32 err_runt:1; | |
862 | u32 err_too_long:1; | |
863 | u32 err_phy:1; | |
864 | u32 src_port:4; | |
865 | u32 multicast:1; | |
866 | u32 error:1; | |
867 | u32 csum_err_udp:1; | |
868 | u32 csum_err_tcp:1; | |
869 | u32 csum_err_ip:1; | |
870 | u32 last_desc:1; | |
871 | u32 first_desc:1; | |
872 | u32 hw_owned:1; | |
873 | #endif | |
874 | }; | |
875 | ||
876 | struct ksz_desc_tx_stat { | |
877 | #ifdef __BIG_ENDIAN_BITFIELD | |
878 | u32 hw_owned:1; | |
879 | u32 reserved1:31; | |
880 | #else | |
881 | u32 reserved1:31; | |
882 | u32 hw_owned:1; | |
883 | #endif | |
884 | }; | |
885 | ||
886 | struct ksz_desc_rx_buf { | |
887 | #ifdef __BIG_ENDIAN_BITFIELD | |
888 | u32 reserved4:6; | |
889 | u32 end_of_ring:1; | |
890 | u32 reserved3:14; | |
891 | u32 buf_size:11; | |
892 | #else | |
893 | u32 buf_size:11; | |
894 | u32 reserved3:14; | |
895 | u32 end_of_ring:1; | |
896 | u32 reserved4:6; | |
897 | #endif | |
898 | }; | |
899 | ||
900 | struct ksz_desc_tx_buf { | |
901 | #ifdef __BIG_ENDIAN_BITFIELD | |
902 | u32 intr:1; | |
903 | u32 first_seg:1; | |
904 | u32 last_seg:1; | |
905 | u32 csum_gen_ip:1; | |
906 | u32 csum_gen_tcp:1; | |
907 | u32 csum_gen_udp:1; | |
908 | u32 end_of_ring:1; | |
909 | u32 reserved4:1; | |
910 | u32 dest_port:4; | |
911 | u32 reserved3:9; | |
912 | u32 buf_size:11; | |
913 | #else | |
914 | u32 buf_size:11; | |
915 | u32 reserved3:9; | |
916 | u32 dest_port:4; | |
917 | u32 reserved4:1; | |
918 | u32 end_of_ring:1; | |
919 | u32 csum_gen_udp:1; | |
920 | u32 csum_gen_tcp:1; | |
921 | u32 csum_gen_ip:1; | |
922 | u32 last_seg:1; | |
923 | u32 first_seg:1; | |
924 | u32 intr:1; | |
925 | #endif | |
926 | }; | |
927 | ||
928 | union desc_stat { | |
929 | struct ksz_desc_rx_stat rx; | |
930 | struct ksz_desc_tx_stat tx; | |
931 | u32 data; | |
932 | }; | |
933 | ||
934 | union desc_buf { | |
935 | struct ksz_desc_rx_buf rx; | |
936 | struct ksz_desc_tx_buf tx; | |
937 | u32 data; | |
938 | }; | |
939 | ||
940 | /** | |
941 | * struct ksz_hw_desc - Hardware descriptor data structure | |
942 | * @ctrl: Descriptor control value. | |
943 | * @buf: Descriptor buffer value. | |
944 | * @addr: Physical address of memory buffer. | |
945 | * @next: Pointer to next hardware descriptor. | |
946 | */ | |
947 | struct ksz_hw_desc { | |
948 | union desc_stat ctrl; | |
949 | union desc_buf buf; | |
950 | u32 addr; | |
951 | u32 next; | |
952 | }; | |
953 | ||
954 | /** | |
955 | * struct ksz_sw_desc - Software descriptor data structure | |
956 | * @ctrl: Descriptor control value. | |
957 | * @buf: Descriptor buffer value. | |
958 | * @buf_size: Current buffers size value in hardware descriptor. | |
959 | */ | |
960 | struct ksz_sw_desc { | |
961 | union desc_stat ctrl; | |
962 | union desc_buf buf; | |
963 | u32 buf_size; | |
964 | }; | |
965 | ||
966 | /** | |
967 | * struct ksz_dma_buf - OS dependent DMA buffer data structure | |
968 | * @skb: Associated socket buffer. | |
969 | * @dma: Associated physical DMA address. | |
970 | * len: Actual len used. | |
971 | */ | |
972 | struct ksz_dma_buf { | |
973 | struct sk_buff *skb; | |
974 | dma_addr_t dma; | |
975 | int len; | |
976 | }; | |
977 | ||
978 | /** | |
979 | * struct ksz_desc - Descriptor structure | |
980 | * @phw: Hardware descriptor pointer to uncached physical memory. | |
981 | * @sw: Cached memory to hold hardware descriptor values for | |
982 | * manipulation. | |
983 | * @dma_buf: Operating system dependent data structure to hold physical | |
984 | * memory buffer allocation information. | |
985 | */ | |
986 | struct ksz_desc { | |
987 | struct ksz_hw_desc *phw; | |
988 | struct ksz_sw_desc sw; | |
989 | struct ksz_dma_buf dma_buf; | |
990 | }; | |
991 | ||
992 | #define DMA_BUFFER(desc) ((struct ksz_dma_buf *)(&(desc)->dma_buf)) | |
993 | ||
994 | /** | |
995 | * struct ksz_desc_info - Descriptor information data structure | |
996 | * @ring: First descriptor in the ring. | |
997 | * @cur: Current descriptor being manipulated. | |
998 | * @ring_virt: First hardware descriptor in the ring. | |
999 | * @ring_phys: The physical address of the first descriptor of the ring. | |
1000 | * @size: Size of hardware descriptor. | |
1001 | * @alloc: Number of descriptors allocated. | |
1002 | * @avail: Number of descriptors available for use. | |
1003 | * @last: Index for last descriptor released to hardware. | |
1004 | * @next: Index for next descriptor available for use. | |
1005 | * @mask: Mask for index wrapping. | |
1006 | */ | |
1007 | struct ksz_desc_info { | |
1008 | struct ksz_desc *ring; | |
1009 | struct ksz_desc *cur; | |
1010 | struct ksz_hw_desc *ring_virt; | |
1011 | u32 ring_phys; | |
1012 | int size; | |
1013 | int alloc; | |
1014 | int avail; | |
1015 | int last; | |
1016 | int next; | |
1017 | int mask; | |
1018 | }; | |
1019 | ||
1020 | /* | |
1021 | * KSZ8842 switch definitions | |
1022 | */ | |
1023 | ||
1024 | enum { | |
1025 | TABLE_STATIC_MAC = 0, | |
1026 | TABLE_VLAN, | |
1027 | TABLE_DYNAMIC_MAC, | |
1028 | TABLE_MIB | |
1029 | }; | |
1030 | ||
1031 | #define LEARNED_MAC_TABLE_ENTRIES 1024 | |
1032 | #define STATIC_MAC_TABLE_ENTRIES 8 | |
1033 | ||
1034 | /** | |
1035 | * struct ksz_mac_table - Static MAC table data structure | |
1036 | * @mac_addr: MAC address to filter. | |
1037 | * @vid: VID value. | |
1038 | * @fid: FID value. | |
1039 | * @ports: Port membership. | |
1040 | * @override: Override setting. | |
1041 | * @use_fid: FID use setting. | |
1042 | * @valid: Valid setting indicating the entry is being used. | |
1043 | */ | |
1044 | struct ksz_mac_table { | |
1045 | u8 mac_addr[MAC_ADDR_LEN]; | |
1046 | u16 vid; | |
1047 | u8 fid; | |
1048 | u8 ports; | |
1049 | u8 override:1; | |
1050 | u8 use_fid:1; | |
1051 | u8 valid:1; | |
1052 | }; | |
1053 | ||
1054 | #define VLAN_TABLE_ENTRIES 16 | |
1055 | ||
1056 | /** | |
1057 | * struct ksz_vlan_table - VLAN table data structure | |
1058 | * @vid: VID value. | |
1059 | * @fid: FID value. | |
1060 | * @member: Port membership. | |
1061 | */ | |
1062 | struct ksz_vlan_table { | |
1063 | u16 vid; | |
1064 | u8 fid; | |
1065 | u8 member; | |
1066 | }; | |
1067 | ||
1068 | #define DIFFSERV_ENTRIES 64 | |
1069 | #define PRIO_802_1P_ENTRIES 8 | |
1070 | #define PRIO_QUEUES 4 | |
1071 | ||
1072 | #define SWITCH_PORT_NUM 2 | |
1073 | #define TOTAL_PORT_NUM (SWITCH_PORT_NUM + 1) | |
1074 | #define HOST_MASK (1 << SWITCH_PORT_NUM) | |
1075 | #define PORT_MASK 7 | |
1076 | ||
1077 | #define MAIN_PORT 0 | |
1078 | #define OTHER_PORT 1 | |
1079 | #define HOST_PORT SWITCH_PORT_NUM | |
1080 | ||
1081 | #define PORT_COUNTER_NUM 0x20 | |
1082 | #define TOTAL_PORT_COUNTER_NUM (PORT_COUNTER_NUM + 2) | |
1083 | ||
1084 | #define MIB_COUNTER_RX_LO_PRIORITY 0x00 | |
1085 | #define MIB_COUNTER_RX_HI_PRIORITY 0x01 | |
1086 | #define MIB_COUNTER_RX_UNDERSIZE 0x02 | |
1087 | #define MIB_COUNTER_RX_FRAGMENT 0x03 | |
1088 | #define MIB_COUNTER_RX_OVERSIZE 0x04 | |
1089 | #define MIB_COUNTER_RX_JABBER 0x05 | |
1090 | #define MIB_COUNTER_RX_SYMBOL_ERR 0x06 | |
1091 | #define MIB_COUNTER_RX_CRC_ERR 0x07 | |
1092 | #define MIB_COUNTER_RX_ALIGNMENT_ERR 0x08 | |
1093 | #define MIB_COUNTER_RX_CTRL_8808 0x09 | |
1094 | #define MIB_COUNTER_RX_PAUSE 0x0A | |
1095 | #define MIB_COUNTER_RX_BROADCAST 0x0B | |
1096 | #define MIB_COUNTER_RX_MULTICAST 0x0C | |
1097 | #define MIB_COUNTER_RX_UNICAST 0x0D | |
1098 | #define MIB_COUNTER_RX_OCTET_64 0x0E | |
1099 | #define MIB_COUNTER_RX_OCTET_65_127 0x0F | |
1100 | #define MIB_COUNTER_RX_OCTET_128_255 0x10 | |
1101 | #define MIB_COUNTER_RX_OCTET_256_511 0x11 | |
1102 | #define MIB_COUNTER_RX_OCTET_512_1023 0x12 | |
1103 | #define MIB_COUNTER_RX_OCTET_1024_1522 0x13 | |
1104 | #define MIB_COUNTER_TX_LO_PRIORITY 0x14 | |
1105 | #define MIB_COUNTER_TX_HI_PRIORITY 0x15 | |
1106 | #define MIB_COUNTER_TX_LATE_COLLISION 0x16 | |
1107 | #define MIB_COUNTER_TX_PAUSE 0x17 | |
1108 | #define MIB_COUNTER_TX_BROADCAST 0x18 | |
1109 | #define MIB_COUNTER_TX_MULTICAST 0x19 | |
1110 | #define MIB_COUNTER_TX_UNICAST 0x1A | |
1111 | #define MIB_COUNTER_TX_DEFERRED 0x1B | |
1112 | #define MIB_COUNTER_TX_TOTAL_COLLISION 0x1C | |
1113 | #define MIB_COUNTER_TX_EXCESS_COLLISION 0x1D | |
1114 | #define MIB_COUNTER_TX_SINGLE_COLLISION 0x1E | |
1115 | #define MIB_COUNTER_TX_MULTI_COLLISION 0x1F | |
1116 | ||
1117 | #define MIB_COUNTER_RX_DROPPED_PACKET 0x20 | |
1118 | #define MIB_COUNTER_TX_DROPPED_PACKET 0x21 | |
1119 | ||
1120 | /** | |
1121 | * struct ksz_port_mib - Port MIB data structure | |
1122 | * @cnt_ptr: Current pointer to MIB counter index. | |
1123 | * @link_down: Indication the link has just gone down. | |
1124 | * @state: Connection status of the port. | |
1125 | * @mib_start: The starting counter index. Some ports do not start at 0. | |
1126 | * @counter: 64-bit MIB counter value. | |
1127 | * @dropped: Temporary buffer to remember last read packet dropped values. | |
1128 | * | |
1129 | * MIB counters needs to be read periodically so that counters do not get | |
1130 | * overflowed and give incorrect values. A right balance is needed to | |
1131 | * satisfy this condition and not waste too much CPU time. | |
1132 | * | |
1133 | * It is pointless to read MIB counters when the port is disconnected. The | |
1134 | * @state provides the connection status so that MIB counters are read only | |
1135 | * when the port is connected. The @link_down indicates the port is just | |
1136 | * disconnected so that all MIB counters are read one last time to update the | |
1137 | * information. | |
1138 | */ | |
1139 | struct ksz_port_mib { | |
1140 | u8 cnt_ptr; | |
1141 | u8 link_down; | |
1142 | u8 state; | |
1143 | u8 mib_start; | |
1144 | ||
1145 | u64 counter[TOTAL_PORT_COUNTER_NUM]; | |
1146 | u32 dropped[2]; | |
1147 | }; | |
1148 | ||
1149 | /** | |
1150 | * struct ksz_port_cfg - Port configuration data structure | |
1151 | * @vid: VID value. | |
1152 | * @member: Port membership. | |
1153 | * @port_prio: Port priority. | |
1154 | * @rx_rate: Receive priority rate. | |
1155 | * @tx_rate: Transmit priority rate. | |
1156 | * @stp_state: Current Spanning Tree Protocol state. | |
1157 | */ | |
1158 | struct ksz_port_cfg { | |
1159 | u16 vid; | |
1160 | u8 member; | |
1161 | u8 port_prio; | |
1162 | u32 rx_rate[PRIO_QUEUES]; | |
1163 | u32 tx_rate[PRIO_QUEUES]; | |
1164 | int stp_state; | |
1165 | }; | |
1166 | ||
1167 | /** | |
1168 | * struct ksz_switch - KSZ8842 switch data structure | |
1169 | * @mac_table: MAC table entries information. | |
1170 | * @vlan_table: VLAN table entries information. | |
1171 | * @port_cfg: Port configuration information. | |
1172 | * @diffserv: DiffServ priority settings. Possible values from 6-bit of ToS | |
1173 | * (bit7 ~ bit2) field. | |
1174 | * @p_802_1p: 802.1P priority settings. Possible values from 3-bit of 802.1p | |
1175 | * Tag priority field. | |
1176 | * @br_addr: Bridge address. Used for STP. | |
1177 | * @other_addr: Other MAC address. Used for multiple network device mode. | |
1178 | * @broad_per: Broadcast storm percentage. | |
1179 | * @member: Current port membership. Used for STP. | |
1180 | */ | |
1181 | struct ksz_switch { | |
1182 | struct ksz_mac_table mac_table[STATIC_MAC_TABLE_ENTRIES]; | |
1183 | struct ksz_vlan_table vlan_table[VLAN_TABLE_ENTRIES]; | |
1184 | struct ksz_port_cfg port_cfg[TOTAL_PORT_NUM]; | |
1185 | ||
1186 | u8 diffserv[DIFFSERV_ENTRIES]; | |
1187 | u8 p_802_1p[PRIO_802_1P_ENTRIES]; | |
1188 | ||
1189 | u8 br_addr[MAC_ADDR_LEN]; | |
1190 | u8 other_addr[MAC_ADDR_LEN]; | |
1191 | ||
1192 | u8 broad_per; | |
1193 | u8 member; | |
1194 | }; | |
1195 | ||
1196 | #define TX_RATE_UNIT 10000 | |
1197 | ||
1198 | /** | |
1199 | * struct ksz_port_info - Port information data structure | |
1200 | * @state: Connection status of the port. | |
1201 | * @tx_rate: Transmit rate divided by 10000 to get Mbit. | |
1202 | * @duplex: Duplex mode. | |
1203 | * @advertised: Advertised auto-negotiation setting. Used to determine link. | |
1204 | * @partner: Auto-negotiation partner setting. Used to determine link. | |
1205 | * @port_id: Port index to access actual hardware register. | |
1206 | * @pdev: Pointer to OS dependent network device. | |
1207 | */ | |
1208 | struct ksz_port_info { | |
1209 | uint state; | |
1210 | uint tx_rate; | |
1211 | u8 duplex; | |
1212 | u8 advertised; | |
1213 | u8 partner; | |
1214 | u8 port_id; | |
1215 | void *pdev; | |
1216 | }; | |
1217 | ||
1218 | #define MAX_TX_HELD_SIZE 52000 | |
1219 | ||
1220 | /* Hardware features and bug fixes. */ | |
1221 | #define LINK_INT_WORKING (1 << 0) | |
1222 | #define SMALL_PACKET_TX_BUG (1 << 1) | |
1223 | #define HALF_DUPLEX_SIGNAL_BUG (1 << 2) | |
1224 | #define IPV6_CSUM_GEN_HACK (1 << 3) | |
1225 | #define RX_HUGE_FRAME (1 << 4) | |
1226 | #define STP_SUPPORT (1 << 8) | |
1227 | ||
1228 | /* Software overrides. */ | |
1229 | #define PAUSE_FLOW_CTRL (1 << 0) | |
1230 | #define FAST_AGING (1 << 1) | |
1231 | ||
1232 | /** | |
1233 | * struct ksz_hw - KSZ884X hardware data structure | |
1234 | * @io: Virtual address assigned. | |
1235 | * @ksz_switch: Pointer to KSZ8842 switch. | |
1236 | * @port_info: Port information. | |
1237 | * @port_mib: Port MIB information. | |
1238 | * @dev_count: Number of network devices this hardware supports. | |
1239 | * @dst_ports: Destination ports in switch for transmission. | |
1240 | * @id: Hardware ID. Used for display only. | |
1241 | * @mib_cnt: Number of MIB counters this hardware has. | |
1242 | * @mib_port_cnt: Number of ports with MIB counters. | |
1243 | * @tx_cfg: Cached transmit control settings. | |
1244 | * @rx_cfg: Cached receive control settings. | |
1245 | * @intr_mask: Current interrupt mask. | |
1246 | * @intr_set: Current interrup set. | |
1247 | * @intr_blocked: Interrupt blocked. | |
1248 | * @rx_desc_info: Receive descriptor information. | |
1249 | * @tx_desc_info: Transmit descriptor information. | |
1250 | * @tx_int_cnt: Transmit interrupt count. Used for TX optimization. | |
1251 | * @tx_int_mask: Transmit interrupt mask. Used for TX optimization. | |
1252 | * @tx_size: Transmit data size. Used for TX optimization. | |
1253 | * The maximum is defined by MAX_TX_HELD_SIZE. | |
1254 | * @perm_addr: Permanent MAC address. | |
1255 | * @override_addr: Overrided MAC address. | |
1256 | * @address: Additional MAC address entries. | |
1257 | * @addr_list_size: Additional MAC address list size. | |
1258 | * @mac_override: Indication of MAC address overrided. | |
1259 | * @promiscuous: Counter to keep track of promiscuous mode set. | |
1260 | * @all_multi: Counter to keep track of all multicast mode set. | |
1261 | * @multi_list: Multicast address entries. | |
1262 | * @multi_bits: Cached multicast hash table settings. | |
1263 | * @multi_list_size: Multicast address list size. | |
1264 | * @enabled: Indication of hardware enabled. | |
1265 | * @rx_stop: Indication of receive process stop. | |
1266 | * @features: Hardware features to enable. | |
1267 | * @overrides: Hardware features to override. | |
1268 | * @parent: Pointer to parent, network device private structure. | |
1269 | */ | |
1270 | struct ksz_hw { | |
1271 | void __iomem *io; | |
1272 | ||
1273 | struct ksz_switch *ksz_switch; | |
1274 | struct ksz_port_info port_info[SWITCH_PORT_NUM]; | |
1275 | struct ksz_port_mib port_mib[TOTAL_PORT_NUM]; | |
1276 | int dev_count; | |
1277 | int dst_ports; | |
1278 | int id; | |
1279 | int mib_cnt; | |
1280 | int mib_port_cnt; | |
1281 | ||
1282 | u32 tx_cfg; | |
1283 | u32 rx_cfg; | |
1284 | u32 intr_mask; | |
1285 | u32 intr_set; | |
1286 | uint intr_blocked; | |
1287 | ||
1288 | struct ksz_desc_info rx_desc_info; | |
1289 | struct ksz_desc_info tx_desc_info; | |
1290 | ||
1291 | int tx_int_cnt; | |
1292 | int tx_int_mask; | |
1293 | int tx_size; | |
1294 | ||
1295 | u8 perm_addr[MAC_ADDR_LEN]; | |
1296 | u8 override_addr[MAC_ADDR_LEN]; | |
1297 | u8 address[ADDITIONAL_ENTRIES][MAC_ADDR_LEN]; | |
1298 | u8 addr_list_size; | |
1299 | u8 mac_override; | |
1300 | u8 promiscuous; | |
1301 | u8 all_multi; | |
1302 | u8 multi_list[MAX_MULTICAST_LIST][MAC_ADDR_LEN]; | |
1303 | u8 multi_bits[HW_MULTICAST_SIZE]; | |
1304 | u8 multi_list_size; | |
1305 | ||
1306 | u8 enabled; | |
1307 | u8 rx_stop; | |
1308 | u8 reserved2[1]; | |
1309 | ||
1310 | uint features; | |
1311 | uint overrides; | |
1312 | ||
1313 | void *parent; | |
1314 | }; | |
1315 | ||
1316 | enum { | |
1317 | PHY_NO_FLOW_CTRL, | |
1318 | PHY_FLOW_CTRL, | |
1319 | PHY_TX_ONLY, | |
1320 | PHY_RX_ONLY | |
1321 | }; | |
1322 | ||
1323 | /** | |
1324 | * struct ksz_port - Virtual port data structure | |
1325 | * @duplex: Duplex mode setting. 1 for half duplex, 2 for full | |
1326 | * duplex, and 0 for auto, which normally results in full | |
1327 | * duplex. | |
1328 | * @speed: Speed setting. 10 for 10 Mbit, 100 for 100 Mbit, and | |
1329 | * 0 for auto, which normally results in 100 Mbit. | |
1330 | * @force_link: Force link setting. 0 for auto-negotiation, and 1 for | |
1331 | * force. | |
1332 | * @flow_ctrl: Flow control setting. PHY_NO_FLOW_CTRL for no flow | |
1333 | * control, and PHY_FLOW_CTRL for flow control. | |
1334 | * PHY_TX_ONLY and PHY_RX_ONLY are not supported for 100 | |
1335 | * Mbit PHY. | |
1336 | * @first_port: Index of first port this port supports. | |
1337 | * @mib_port_cnt: Number of ports with MIB counters. | |
1338 | * @port_cnt: Number of ports this port supports. | |
1339 | * @counter: Port statistics counter. | |
1340 | * @hw: Pointer to hardware structure. | |
1341 | * @linked: Pointer to port information linked to this port. | |
1342 | */ | |
1343 | struct ksz_port { | |
1344 | u8 duplex; | |
1345 | u8 speed; | |
1346 | u8 force_link; | |
1347 | u8 flow_ctrl; | |
1348 | ||
1349 | int first_port; | |
1350 | int mib_port_cnt; | |
1351 | int port_cnt; | |
1352 | u64 counter[OID_COUNTER_LAST]; | |
1353 | ||
1354 | struct ksz_hw *hw; | |
1355 | struct ksz_port_info *linked; | |
1356 | }; | |
1357 | ||
1358 | /** | |
1359 | * struct ksz_timer_info - Timer information data structure | |
1360 | * @timer: Kernel timer. | |
1361 | * @cnt: Running timer counter. | |
1362 | * @max: Number of times to run timer; -1 for infinity. | |
1363 | * @period: Timer period in jiffies. | |
1364 | */ | |
1365 | struct ksz_timer_info { | |
1366 | struct timer_list timer; | |
1367 | int cnt; | |
1368 | int max; | |
1369 | int period; | |
1370 | }; | |
1371 | ||
1372 | /** | |
1373 | * struct ksz_shared_mem - OS dependent shared memory data structure | |
1374 | * @dma_addr: Physical DMA address allocated. | |
1375 | * @alloc_size: Allocation size. | |
1376 | * @phys: Actual physical address used. | |
1377 | * @alloc_virt: Virtual address allocated. | |
1378 | * @virt: Actual virtual address used. | |
1379 | */ | |
1380 | struct ksz_shared_mem { | |
1381 | dma_addr_t dma_addr; | |
1382 | uint alloc_size; | |
1383 | uint phys; | |
1384 | u8 *alloc_virt; | |
1385 | u8 *virt; | |
1386 | }; | |
1387 | ||
1388 | /** | |
1389 | * struct ksz_counter_info - OS dependent counter information data structure | |
1390 | * @counter: Wait queue to wakeup after counters are read. | |
1391 | * @time: Next time in jiffies to read counter. | |
1392 | * @read: Indication of counters read in full or not. | |
1393 | */ | |
1394 | struct ksz_counter_info { | |
1395 | wait_queue_head_t counter; | |
1396 | unsigned long time; | |
1397 | int read; | |
1398 | }; | |
1399 | ||
1400 | /** | |
1401 | * struct dev_info - Network device information data structure | |
1402 | * @dev: Pointer to network device. | |
1403 | * @pdev: Pointer to PCI device. | |
1404 | * @hw: Hardware structure. | |
1405 | * @desc_pool: Physical memory used for descriptor pool. | |
1406 | * @hwlock: Spinlock to prevent hardware from accessing. | |
1407 | * @lock: Mutex lock to prevent device from accessing. | |
1408 | * @dev_rcv: Receive process function used. | |
1409 | * @last_skb: Socket buffer allocated for descriptor rx fragments. | |
1410 | * @skb_index: Buffer index for receiving fragments. | |
1411 | * @skb_len: Buffer length for receiving fragments. | |
1412 | * @mib_read: Workqueue to read MIB counters. | |
1413 | * @mib_timer_info: Timer to read MIB counters. | |
1414 | * @counter: Used for MIB reading. | |
1415 | * @mtu: Current MTU used. The default is REGULAR_RX_BUF_SIZE; | |
1416 | * the maximum is MAX_RX_BUF_SIZE. | |
1417 | * @opened: Counter to keep track of device open. | |
1418 | * @rx_tasklet: Receive processing tasklet. | |
1419 | * @tx_tasklet: Transmit processing tasklet. | |
1420 | * @wol_enable: Wake-on-LAN enable set by ethtool. | |
1421 | * @wol_support: Wake-on-LAN support used by ethtool. | |
1422 | * @pme_wait: Used for KSZ8841 power management. | |
1423 | */ | |
1424 | struct dev_info { | |
1425 | struct net_device *dev; | |
1426 | struct pci_dev *pdev; | |
1427 | ||
1428 | struct ksz_hw hw; | |
1429 | struct ksz_shared_mem desc_pool; | |
1430 | ||
1431 | spinlock_t hwlock; | |
1432 | struct mutex lock; | |
1433 | ||
1434 | int (*dev_rcv)(struct dev_info *); | |
1435 | ||
1436 | struct sk_buff *last_skb; | |
1437 | int skb_index; | |
1438 | int skb_len; | |
1439 | ||
1440 | struct work_struct mib_read; | |
1441 | struct ksz_timer_info mib_timer_info; | |
1442 | struct ksz_counter_info counter[TOTAL_PORT_NUM]; | |
1443 | ||
1444 | int mtu; | |
1445 | int opened; | |
1446 | ||
1447 | struct tasklet_struct rx_tasklet; | |
1448 | struct tasklet_struct tx_tasklet; | |
1449 | ||
1450 | int wol_enable; | |
1451 | int wol_support; | |
1452 | unsigned long pme_wait; | |
1453 | }; | |
1454 | ||
1455 | /** | |
1456 | * struct dev_priv - Network device private data structure | |
1457 | * @adapter: Adapter device information. | |
1458 | * @port: Port information. | |
1459 | * @monitor_time_info: Timer to monitor ports. | |
8ca86fd8 TH |
1460 | * @proc_sem: Semaphore for proc accessing. |
1461 | * @id: Device ID. | |
1462 | * @mii_if: MII interface information. | |
1463 | * @advertising: Temporary variable to store advertised settings. | |
1464 | * @msg_enable: The message flags controlling driver output. | |
1465 | * @media_state: The connection status of the device. | |
1466 | * @multicast: The all multicast state of the device. | |
1467 | * @promiscuous: The promiscuous state of the device. | |
1468 | */ | |
1469 | struct dev_priv { | |
1470 | struct dev_info *adapter; | |
1471 | struct ksz_port port; | |
1472 | struct ksz_timer_info monitor_timer_info; | |
8ca86fd8 TH |
1473 | |
1474 | struct semaphore proc_sem; | |
1475 | int id; | |
1476 | ||
1477 | struct mii_if_info mii_if; | |
1478 | u32 advertising; | |
1479 | ||
1480 | u32 msg_enable; | |
1481 | int media_state; | |
1482 | int multicast; | |
1483 | int promiscuous; | |
1484 | }; | |
1485 | ||
8ca86fd8 TH |
1486 | #define DRV_NAME "KSZ884X PCI" |
1487 | #define DEVICE_NAME "KSZ884x PCI" | |
1488 | #define DRV_VERSION "1.0.0" | |
1489 | #define DRV_RELDATE "Feb 8, 2010" | |
1490 | ||
1491 | static char version[] __devinitdata = | |
1492 | "Micrel " DEVICE_NAME " " DRV_VERSION " (" DRV_RELDATE ")"; | |
1493 | ||
1494 | static u8 DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 }; | |
1495 | ||
1496 | /* | |
1497 | * Interrupt processing primary routines | |
1498 | */ | |
1499 | ||
1500 | static inline void hw_ack_intr(struct ksz_hw *hw, uint interrupt) | |
1501 | { | |
1502 | writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS); | |
1503 | } | |
1504 | ||
1505 | static inline void hw_dis_intr(struct ksz_hw *hw) | |
1506 | { | |
1507 | hw->intr_blocked = hw->intr_mask; | |
1508 | writel(0, hw->io + KS884X_INTERRUPTS_ENABLE); | |
1509 | hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE); | |
1510 | } | |
1511 | ||
1512 | static inline void hw_set_intr(struct ksz_hw *hw, uint interrupt) | |
1513 | { | |
1514 | hw->intr_set = interrupt; | |
1515 | writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE); | |
1516 | } | |
1517 | ||
1518 | static inline void hw_ena_intr(struct ksz_hw *hw) | |
1519 | { | |
1520 | hw->intr_blocked = 0; | |
1521 | hw_set_intr(hw, hw->intr_mask); | |
1522 | } | |
1523 | ||
1524 | static inline void hw_dis_intr_bit(struct ksz_hw *hw, uint bit) | |
1525 | { | |
1526 | hw->intr_mask &= ~(bit); | |
1527 | } | |
1528 | ||
1529 | static inline void hw_turn_off_intr(struct ksz_hw *hw, uint interrupt) | |
1530 | { | |
1531 | u32 read_intr; | |
1532 | ||
1533 | read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE); | |
1534 | hw->intr_set = read_intr & ~interrupt; | |
1535 | writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE); | |
1536 | hw_dis_intr_bit(hw, interrupt); | |
1537 | } | |
1538 | ||
1539 | /** | |
1540 | * hw_turn_on_intr - turn on specified interrupts | |
1541 | * @hw: The hardware instance. | |
1542 | * @bit: The interrupt bits to be on. | |
1543 | * | |
1544 | * This routine turns on the specified interrupts in the interrupt mask so that | |
1545 | * those interrupts will be enabled. | |
1546 | */ | |
1547 | static void hw_turn_on_intr(struct ksz_hw *hw, u32 bit) | |
1548 | { | |
1549 | hw->intr_mask |= bit; | |
1550 | ||
1551 | if (!hw->intr_blocked) | |
1552 | hw_set_intr(hw, hw->intr_mask); | |
1553 | } | |
1554 | ||
1555 | static inline void hw_ena_intr_bit(struct ksz_hw *hw, uint interrupt) | |
1556 | { | |
1557 | u32 read_intr; | |
1558 | ||
1559 | read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE); | |
1560 | hw->intr_set = read_intr | interrupt; | |
1561 | writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE); | |
1562 | } | |
1563 | ||
1564 | static inline void hw_read_intr(struct ksz_hw *hw, uint *status) | |
1565 | { | |
1566 | *status = readl(hw->io + KS884X_INTERRUPTS_STATUS); | |
1567 | *status = *status & hw->intr_set; | |
1568 | } | |
1569 | ||
1570 | static inline void hw_restore_intr(struct ksz_hw *hw, uint interrupt) | |
1571 | { | |
1572 | if (interrupt) | |
1573 | hw_ena_intr(hw); | |
1574 | } | |
1575 | ||
1576 | /** | |
1577 | * hw_block_intr - block hardware interrupts | |
1578 | * | |
1579 | * This function blocks all interrupts of the hardware and returns the current | |
1580 | * interrupt enable mask so that interrupts can be restored later. | |
1581 | * | |
1582 | * Return the current interrupt enable mask. | |
1583 | */ | |
1584 | static uint hw_block_intr(struct ksz_hw *hw) | |
1585 | { | |
1586 | uint interrupt = 0; | |
1587 | ||
1588 | if (!hw->intr_blocked) { | |
1589 | hw_dis_intr(hw); | |
1590 | interrupt = hw->intr_blocked; | |
1591 | } | |
1592 | return interrupt; | |
1593 | } | |
1594 | ||
1595 | /* | |
1596 | * Hardware descriptor routines | |
1597 | */ | |
1598 | ||
1599 | static inline void reset_desc(struct ksz_desc *desc, union desc_stat status) | |
1600 | { | |
1601 | status.rx.hw_owned = 0; | |
1602 | desc->phw->ctrl.data = cpu_to_le32(status.data); | |
1603 | } | |
1604 | ||
1605 | static inline void release_desc(struct ksz_desc *desc) | |
1606 | { | |
1607 | desc->sw.ctrl.tx.hw_owned = 1; | |
1608 | if (desc->sw.buf_size != desc->sw.buf.data) { | |
1609 | desc->sw.buf_size = desc->sw.buf.data; | |
1610 | desc->phw->buf.data = cpu_to_le32(desc->sw.buf.data); | |
1611 | } | |
1612 | desc->phw->ctrl.data = cpu_to_le32(desc->sw.ctrl.data); | |
1613 | } | |
1614 | ||
1615 | static void get_rx_pkt(struct ksz_desc_info *info, struct ksz_desc **desc) | |
1616 | { | |
1617 | *desc = &info->ring[info->last]; | |
1618 | info->last++; | |
1619 | info->last &= info->mask; | |
1620 | info->avail--; | |
1621 | (*desc)->sw.buf.data &= ~KS_DESC_RX_MASK; | |
1622 | } | |
1623 | ||
1624 | static inline void set_rx_buf(struct ksz_desc *desc, u32 addr) | |
1625 | { | |
1626 | desc->phw->addr = cpu_to_le32(addr); | |
1627 | } | |
1628 | ||
1629 | static inline void set_rx_len(struct ksz_desc *desc, u32 len) | |
1630 | { | |
1631 | desc->sw.buf.rx.buf_size = len; | |
1632 | } | |
1633 | ||
1634 | static inline void get_tx_pkt(struct ksz_desc_info *info, | |
1635 | struct ksz_desc **desc) | |
1636 | { | |
1637 | *desc = &info->ring[info->next]; | |
1638 | info->next++; | |
1639 | info->next &= info->mask; | |
1640 | info->avail--; | |
1641 | (*desc)->sw.buf.data &= ~KS_DESC_TX_MASK; | |
1642 | } | |
1643 | ||
1644 | static inline void set_tx_buf(struct ksz_desc *desc, u32 addr) | |
1645 | { | |
1646 | desc->phw->addr = cpu_to_le32(addr); | |
1647 | } | |
1648 | ||
1649 | static inline void set_tx_len(struct ksz_desc *desc, u32 len) | |
1650 | { | |
1651 | desc->sw.buf.tx.buf_size = len; | |
1652 | } | |
1653 | ||
1654 | /* Switch functions */ | |
1655 | ||
1656 | #define TABLE_READ 0x10 | |
1657 | #define TABLE_SEL_SHIFT 2 | |
1658 | ||
1659 | #define HW_DELAY(hw, reg) \ | |
1660 | do { \ | |
1661 | u16 dummy; \ | |
1662 | dummy = readw(hw->io + reg); \ | |
1663 | } while (0) | |
1664 | ||
1665 | /** | |
1666 | * sw_r_table - read 4 bytes of data from switch table | |
1667 | * @hw: The hardware instance. | |
1668 | * @table: The table selector. | |
1669 | * @addr: The address of the table entry. | |
1670 | * @data: Buffer to store the read data. | |
1671 | * | |
1672 | * This routine reads 4 bytes of data from the table of the switch. | |
1673 | * Hardware interrupts are disabled to minimize corruption of read data. | |
1674 | */ | |
1675 | static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data) | |
1676 | { | |
1677 | u16 ctrl_addr; | |
1678 | uint interrupt; | |
1679 | ||
1680 | ctrl_addr = (((table << TABLE_SEL_SHIFT) | TABLE_READ) << 8) | addr; | |
1681 | ||
1682 | interrupt = hw_block_intr(hw); | |
1683 | ||
1684 | writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); | |
1685 | HW_DELAY(hw, KS884X_IACR_OFFSET); | |
1686 | *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET); | |
1687 | ||
1688 | hw_restore_intr(hw, interrupt); | |
1689 | } | |
1690 | ||
1691 | /** | |
1692 | * sw_w_table_64 - write 8 bytes of data to the switch table | |
1693 | * @hw: The hardware instance. | |
1694 | * @table: The table selector. | |
1695 | * @addr: The address of the table entry. | |
1696 | * @data_hi: The high part of data to be written (bit63 ~ bit32). | |
1697 | * @data_lo: The low part of data to be written (bit31 ~ bit0). | |
1698 | * | |
1699 | * This routine writes 8 bytes of data to the table of the switch. | |
1700 | * Hardware interrupts are disabled to minimize corruption of written data. | |
1701 | */ | |
1702 | static void sw_w_table_64(struct ksz_hw *hw, int table, u16 addr, u32 data_hi, | |
1703 | u32 data_lo) | |
1704 | { | |
1705 | u16 ctrl_addr; | |
1706 | uint interrupt; | |
1707 | ||
1708 | ctrl_addr = ((table << TABLE_SEL_SHIFT) << 8) | addr; | |
1709 | ||
1710 | interrupt = hw_block_intr(hw); | |
1711 | ||
1712 | writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET); | |
1713 | writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET); | |
1714 | ||
1715 | writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); | |
1716 | HW_DELAY(hw, KS884X_IACR_OFFSET); | |
1717 | ||
1718 | hw_restore_intr(hw, interrupt); | |
1719 | } | |
1720 | ||
1721 | /** | |
1722 | * sw_w_sta_mac_table - write to the static MAC table | |
1723 | * @hw: The hardware instance. | |
1724 | * @addr: The address of the table entry. | |
1725 | * @mac_addr: The MAC address. | |
1726 | * @ports: The port members. | |
1727 | * @override: The flag to override the port receive/transmit settings. | |
1728 | * @valid: The flag to indicate entry is valid. | |
1729 | * @use_fid: The flag to indicate the FID is valid. | |
1730 | * @fid: The FID value. | |
1731 | * | |
1732 | * This routine writes an entry of the static MAC table of the switch. It | |
1733 | * calls sw_w_table_64() to write the data. | |
1734 | */ | |
1735 | static void sw_w_sta_mac_table(struct ksz_hw *hw, u16 addr, u8 *mac_addr, | |
1736 | u8 ports, int override, int valid, int use_fid, u8 fid) | |
1737 | { | |
1738 | u32 data_hi; | |
1739 | u32 data_lo; | |
1740 | ||
1741 | data_lo = ((u32) mac_addr[2] << 24) | | |
1742 | ((u32) mac_addr[3] << 16) | | |
1743 | ((u32) mac_addr[4] << 8) | mac_addr[5]; | |
1744 | data_hi = ((u32) mac_addr[0] << 8) | mac_addr[1]; | |
1745 | data_hi |= (u32) ports << STATIC_MAC_FWD_PORTS_SHIFT; | |
1746 | ||
1747 | if (override) | |
1748 | data_hi |= STATIC_MAC_TABLE_OVERRIDE; | |
1749 | if (use_fid) { | |
1750 | data_hi |= STATIC_MAC_TABLE_USE_FID; | |
1751 | data_hi |= (u32) fid << STATIC_MAC_FID_SHIFT; | |
1752 | } | |
1753 | if (valid) | |
1754 | data_hi |= STATIC_MAC_TABLE_VALID; | |
1755 | ||
1756 | sw_w_table_64(hw, TABLE_STATIC_MAC, addr, data_hi, data_lo); | |
1757 | } | |
1758 | ||
1759 | /** | |
1760 | * sw_r_vlan_table - read from the VLAN table | |
1761 | * @hw: The hardware instance. | |
1762 | * @addr: The address of the table entry. | |
1763 | * @vid: Buffer to store the VID. | |
1764 | * @fid: Buffer to store the VID. | |
1765 | * @member: Buffer to store the port membership. | |
1766 | * | |
1767 | * This function reads an entry of the VLAN table of the switch. It calls | |
1768 | * sw_r_table() to get the data. | |
1769 | * | |
1770 | * Return 0 if the entry is valid; otherwise -1. | |
1771 | */ | |
1772 | static int sw_r_vlan_table(struct ksz_hw *hw, u16 addr, u16 *vid, u8 *fid, | |
1773 | u8 *member) | |
1774 | { | |
1775 | u32 data; | |
1776 | ||
1777 | sw_r_table(hw, TABLE_VLAN, addr, &data); | |
1778 | if (data & VLAN_TABLE_VALID) { | |
1779 | *vid = (u16)(data & VLAN_TABLE_VID); | |
1780 | *fid = (u8)((data & VLAN_TABLE_FID) >> VLAN_TABLE_FID_SHIFT); | |
1781 | *member = (u8)((data & VLAN_TABLE_MEMBERSHIP) >> | |
1782 | VLAN_TABLE_MEMBERSHIP_SHIFT); | |
1783 | return 0; | |
1784 | } | |
1785 | return -1; | |
1786 | } | |
1787 | ||
1788 | /** | |
1789 | * port_r_mib_cnt - read MIB counter | |
1790 | * @hw: The hardware instance. | |
1791 | * @port: The port index. | |
1792 | * @addr: The address of the counter. | |
1793 | * @cnt: Buffer to store the counter. | |
1794 | * | |
1795 | * This routine reads a MIB counter of the port. | |
1796 | * Hardware interrupts are disabled to minimize corruption of read data. | |
1797 | */ | |
1798 | static void port_r_mib_cnt(struct ksz_hw *hw, int port, u16 addr, u64 *cnt) | |
1799 | { | |
1800 | u32 data; | |
1801 | u16 ctrl_addr; | |
1802 | uint interrupt; | |
1803 | int timeout; | |
1804 | ||
1805 | ctrl_addr = addr + PORT_COUNTER_NUM * port; | |
1806 | ||
1807 | interrupt = hw_block_intr(hw); | |
1808 | ||
1809 | ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) << 8); | |
1810 | writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); | |
1811 | HW_DELAY(hw, KS884X_IACR_OFFSET); | |
1812 | ||
1813 | for (timeout = 100; timeout > 0; timeout--) { | |
1814 | data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET); | |
1815 | ||
1816 | if (data & MIB_COUNTER_VALID) { | |
1817 | if (data & MIB_COUNTER_OVERFLOW) | |
1818 | *cnt += MIB_COUNTER_VALUE + 1; | |
1819 | *cnt += data & MIB_COUNTER_VALUE; | |
1820 | break; | |
1821 | } | |
1822 | } | |
1823 | ||
1824 | hw_restore_intr(hw, interrupt); | |
1825 | } | |
1826 | ||
1827 | /** | |
1828 | * port_r_mib_pkt - read dropped packet counts | |
1829 | * @hw: The hardware instance. | |
1830 | * @port: The port index. | |
1831 | * @cnt: Buffer to store the receive and transmit dropped packet counts. | |
1832 | * | |
1833 | * This routine reads the dropped packet counts of the port. | |
1834 | * Hardware interrupts are disabled to minimize corruption of read data. | |
1835 | */ | |
1836 | static void port_r_mib_pkt(struct ksz_hw *hw, int port, u32 *last, u64 *cnt) | |
1837 | { | |
1838 | u32 cur; | |
1839 | u32 data; | |
1840 | u16 ctrl_addr; | |
1841 | uint interrupt; | |
1842 | int index; | |
1843 | ||
1844 | index = KS_MIB_PACKET_DROPPED_RX_0 + port; | |
1845 | do { | |
1846 | interrupt = hw_block_intr(hw); | |
1847 | ||
1848 | ctrl_addr = (u16) index; | |
1849 | ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) | |
1850 | << 8); | |
1851 | writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET); | |
1852 | HW_DELAY(hw, KS884X_IACR_OFFSET); | |
1853 | data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET); | |
1854 | ||
1855 | hw_restore_intr(hw, interrupt); | |
1856 | ||
1857 | data &= MIB_PACKET_DROPPED; | |
1858 | cur = *last; | |
1859 | if (data != cur) { | |
1860 | *last = data; | |
1861 | if (data < cur) | |
1862 | data += MIB_PACKET_DROPPED + 1; | |
1863 | data -= cur; | |
1864 | *cnt += data; | |
1865 | } | |
1866 | ++last; | |
1867 | ++cnt; | |
1868 | index -= KS_MIB_PACKET_DROPPED_TX - | |
1869 | KS_MIB_PACKET_DROPPED_TX_0 + 1; | |
1870 | } while (index >= KS_MIB_PACKET_DROPPED_TX_0 + port); | |
1871 | } | |
1872 | ||
1873 | /** | |
1874 | * port_r_cnt - read MIB counters periodically | |
1875 | * @hw: The hardware instance. | |
1876 | * @port: The port index. | |
1877 | * | |
1878 | * This routine is used to read the counters of the port periodically to avoid | |
1879 | * counter overflow. The hardware should be acquired first before calling this | |
1880 | * routine. | |
1881 | * | |
1882 | * Return non-zero when not all counters not read. | |
1883 | */ | |
1884 | static int port_r_cnt(struct ksz_hw *hw, int port) | |
1885 | { | |
1886 | struct ksz_port_mib *mib = &hw->port_mib[port]; | |
1887 | ||
1888 | if (mib->mib_start < PORT_COUNTER_NUM) | |
1889 | while (mib->cnt_ptr < PORT_COUNTER_NUM) { | |
1890 | port_r_mib_cnt(hw, port, mib->cnt_ptr, | |
1891 | &mib->counter[mib->cnt_ptr]); | |
1892 | ++mib->cnt_ptr; | |
1893 | } | |
1894 | if (hw->mib_cnt > PORT_COUNTER_NUM) | |
1895 | port_r_mib_pkt(hw, port, mib->dropped, | |
1896 | &mib->counter[PORT_COUNTER_NUM]); | |
1897 | mib->cnt_ptr = 0; | |
1898 | return 0; | |
1899 | } | |
1900 | ||
1901 | /** | |
1902 | * port_init_cnt - initialize MIB counter values | |
1903 | * @hw: The hardware instance. | |
1904 | * @port: The port index. | |
1905 | * | |
1906 | * This routine is used to initialize all counters to zero if the hardware | |
1907 | * cannot do it after reset. | |
1908 | */ | |
1909 | static void port_init_cnt(struct ksz_hw *hw, int port) | |
1910 | { | |
1911 | struct ksz_port_mib *mib = &hw->port_mib[port]; | |
1912 | ||
1913 | mib->cnt_ptr = 0; | |
1914 | if (mib->mib_start < PORT_COUNTER_NUM) | |
1915 | do { | |
1916 | port_r_mib_cnt(hw, port, mib->cnt_ptr, | |
1917 | &mib->counter[mib->cnt_ptr]); | |
1918 | ++mib->cnt_ptr; | |
1919 | } while (mib->cnt_ptr < PORT_COUNTER_NUM); | |
1920 | if (hw->mib_cnt > PORT_COUNTER_NUM) | |
1921 | port_r_mib_pkt(hw, port, mib->dropped, | |
1922 | &mib->counter[PORT_COUNTER_NUM]); | |
1923 | memset((void *) mib->counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM); | |
1924 | mib->cnt_ptr = 0; | |
1925 | } | |
1926 | ||
1927 | /* | |
1928 | * Port functions | |
1929 | */ | |
1930 | ||
1931 | /** | |
1932 | * port_chk - check port register bits | |
1933 | * @hw: The hardware instance. | |
1934 | * @port: The port index. | |
1935 | * @offset: The offset of the port register. | |
1936 | * @bits: The data bits to check. | |
1937 | * | |
1938 | * This function checks whether the specified bits of the port register are set | |
1939 | * or not. | |
1940 | * | |
1941 | * Return 0 if the bits are not set. | |
1942 | */ | |
1943 | static int port_chk(struct ksz_hw *hw, int port, int offset, u16 bits) | |
1944 | { | |
1945 | u32 addr; | |
1946 | u16 data; | |
1947 | ||
1948 | PORT_CTRL_ADDR(port, addr); | |
1949 | addr += offset; | |
1950 | data = readw(hw->io + addr); | |
1951 | return (data & bits) == bits; | |
1952 | } | |
1953 | ||
1954 | /** | |
1955 | * port_cfg - set port register bits | |
1956 | * @hw: The hardware instance. | |
1957 | * @port: The port index. | |
1958 | * @offset: The offset of the port register. | |
1959 | * @bits: The data bits to set. | |
1960 | * @set: The flag indicating whether the bits are to be set or not. | |
1961 | * | |
1962 | * This routine sets or resets the specified bits of the port register. | |
1963 | */ | |
1964 | static void port_cfg(struct ksz_hw *hw, int port, int offset, u16 bits, | |
1965 | int set) | |
1966 | { | |
1967 | u32 addr; | |
1968 | u16 data; | |
1969 | ||
1970 | PORT_CTRL_ADDR(port, addr); | |
1971 | addr += offset; | |
1972 | data = readw(hw->io + addr); | |
1973 | if (set) | |
1974 | data |= bits; | |
1975 | else | |
1976 | data &= ~bits; | |
1977 | writew(data, hw->io + addr); | |
1978 | } | |
1979 | ||
1980 | /** | |
1981 | * port_chk_shift - check port bit | |
1982 | * @hw: The hardware instance. | |
1983 | * @port: The port index. | |
1984 | * @offset: The offset of the register. | |
1985 | * @shift: Number of bits to shift. | |
1986 | * | |
1987 | * This function checks whether the specified port is set in the register or | |
1988 | * not. | |
1989 | * | |
1990 | * Return 0 if the port is not set. | |
1991 | */ | |
1992 | static int port_chk_shift(struct ksz_hw *hw, int port, u32 addr, int shift) | |
1993 | { | |
1994 | u16 data; | |
1995 | u16 bit = 1 << port; | |
1996 | ||
1997 | data = readw(hw->io + addr); | |
1998 | data >>= shift; | |
1999 | return (data & bit) == bit; | |
2000 | } | |
2001 | ||
2002 | /** | |
2003 | * port_cfg_shift - set port bit | |
2004 | * @hw: The hardware instance. | |
2005 | * @port: The port index. | |
2006 | * @offset: The offset of the register. | |
2007 | * @shift: Number of bits to shift. | |
2008 | * @set: The flag indicating whether the port is to be set or not. | |
2009 | * | |
2010 | * This routine sets or resets the specified port in the register. | |
2011 | */ | |
2012 | static void port_cfg_shift(struct ksz_hw *hw, int port, u32 addr, int shift, | |
2013 | int set) | |
2014 | { | |
2015 | u16 data; | |
2016 | u16 bits = 1 << port; | |
2017 | ||
2018 | data = readw(hw->io + addr); | |
2019 | bits <<= shift; | |
2020 | if (set) | |
2021 | data |= bits; | |
2022 | else | |
2023 | data &= ~bits; | |
2024 | writew(data, hw->io + addr); | |
2025 | } | |
2026 | ||
2027 | /** | |
2028 | * port_r8 - read byte from port register | |
2029 | * @hw: The hardware instance. | |
2030 | * @port: The port index. | |
2031 | * @offset: The offset of the port register. | |
2032 | * @data: Buffer to store the data. | |
2033 | * | |
2034 | * This routine reads a byte from the port register. | |
2035 | */ | |
2036 | static void port_r8(struct ksz_hw *hw, int port, int offset, u8 *data) | |
2037 | { | |
2038 | u32 addr; | |
2039 | ||
2040 | PORT_CTRL_ADDR(port, addr); | |
2041 | addr += offset; | |
2042 | *data = readb(hw->io + addr); | |
2043 | } | |
2044 | ||
2045 | /** | |
2046 | * port_r16 - read word from port register. | |
2047 | * @hw: The hardware instance. | |
2048 | * @port: The port index. | |
2049 | * @offset: The offset of the port register. | |
2050 | * @data: Buffer to store the data. | |
2051 | * | |
2052 | * This routine reads a word from the port register. | |
2053 | */ | |
2054 | static void port_r16(struct ksz_hw *hw, int port, int offset, u16 *data) | |
2055 | { | |
2056 | u32 addr; | |
2057 | ||
2058 | PORT_CTRL_ADDR(port, addr); | |
2059 | addr += offset; | |
2060 | *data = readw(hw->io + addr); | |
2061 | } | |
2062 | ||
2063 | /** | |
2064 | * port_w16 - write word to port register. | |
2065 | * @hw: The hardware instance. | |
2066 | * @port: The port index. | |
2067 | * @offset: The offset of the port register. | |
2068 | * @data: Data to write. | |
2069 | * | |
2070 | * This routine writes a word to the port register. | |
2071 | */ | |
2072 | static void port_w16(struct ksz_hw *hw, int port, int offset, u16 data) | |
2073 | { | |
2074 | u32 addr; | |
2075 | ||
2076 | PORT_CTRL_ADDR(port, addr); | |
2077 | addr += offset; | |
2078 | writew(data, hw->io + addr); | |
2079 | } | |
2080 | ||
2081 | /** | |
2082 | * sw_chk - check switch register bits | |
2083 | * @hw: The hardware instance. | |
2084 | * @addr: The address of the switch register. | |
2085 | * @bits: The data bits to check. | |
2086 | * | |
2087 | * This function checks whether the specified bits of the switch register are | |
2088 | * set or not. | |
2089 | * | |
2090 | * Return 0 if the bits are not set. | |
2091 | */ | |
2092 | static int sw_chk(struct ksz_hw *hw, u32 addr, u16 bits) | |
2093 | { | |
2094 | u16 data; | |
2095 | ||
2096 | data = readw(hw->io + addr); | |
2097 | return (data & bits) == bits; | |
2098 | } | |
2099 | ||
2100 | /** | |
2101 | * sw_cfg - set switch register bits | |
2102 | * @hw: The hardware instance. | |
2103 | * @addr: The address of the switch register. | |
2104 | * @bits: The data bits to set. | |
2105 | * @set: The flag indicating whether the bits are to be set or not. | |
2106 | * | |
2107 | * This function sets or resets the specified bits of the switch register. | |
2108 | */ | |
2109 | static void sw_cfg(struct ksz_hw *hw, u32 addr, u16 bits, int set) | |
2110 | { | |
2111 | u16 data; | |
2112 | ||
2113 | data = readw(hw->io + addr); | |
2114 | if (set) | |
2115 | data |= bits; | |
2116 | else | |
2117 | data &= ~bits; | |
2118 | writew(data, hw->io + addr); | |
2119 | } | |
2120 | ||
2121 | /* Bandwidth */ | |
2122 | ||
2123 | static inline void port_cfg_broad_storm(struct ksz_hw *hw, int p, int set) | |
2124 | { | |
2125 | port_cfg(hw, p, | |
2126 | KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM, set); | |
2127 | } | |
2128 | ||
2129 | static inline int port_chk_broad_storm(struct ksz_hw *hw, int p) | |
2130 | { | |
2131 | return port_chk(hw, p, | |
2132 | KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM); | |
2133 | } | |
2134 | ||
2135 | /* Driver set switch broadcast storm protection at 10% rate. */ | |
2136 | #define BROADCAST_STORM_PROTECTION_RATE 10 | |
2137 | ||
2138 | /* 148,800 frames * 67 ms / 100 */ | |
2139 | #define BROADCAST_STORM_VALUE 9969 | |
2140 | ||
2141 | /** | |
2142 | * sw_cfg_broad_storm - configure broadcast storm threshold | |
2143 | * @hw: The hardware instance. | |
2144 | * @percent: Broadcast storm threshold in percent of transmit rate. | |
2145 | * | |
2146 | * This routine configures the broadcast storm threshold of the switch. | |
2147 | */ | |
2148 | static void sw_cfg_broad_storm(struct ksz_hw *hw, u8 percent) | |
2149 | { | |
2150 | u16 data; | |
2151 | u32 value = ((u32) BROADCAST_STORM_VALUE * (u32) percent / 100); | |
2152 | ||
2153 | if (value > BROADCAST_STORM_RATE) | |
2154 | value = BROADCAST_STORM_RATE; | |
2155 | ||
2156 | data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET); | |
2157 | data &= ~(BROADCAST_STORM_RATE_LO | BROADCAST_STORM_RATE_HI); | |
2158 | data |= ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8); | |
2159 | writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET); | |
2160 | } | |
2161 | ||
2162 | /** | |
2163 | * sw_get_board_storm - get broadcast storm threshold | |
2164 | * @hw: The hardware instance. | |
2165 | * @percent: Buffer to store the broadcast storm threshold percentage. | |
2166 | * | |
2167 | * This routine retrieves the broadcast storm threshold of the switch. | |
2168 | */ | |
2169 | static void sw_get_broad_storm(struct ksz_hw *hw, u8 *percent) | |
2170 | { | |
2171 | int num; | |
2172 | u16 data; | |
2173 | ||
2174 | data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET); | |
2175 | num = (data & BROADCAST_STORM_RATE_HI); | |
2176 | num <<= 8; | |
2177 | num |= (data & BROADCAST_STORM_RATE_LO) >> 8; | |
2178 | num = (num * 100 + BROADCAST_STORM_VALUE / 2) / BROADCAST_STORM_VALUE; | |
2179 | *percent = (u8) num; | |
2180 | } | |
2181 | ||
2182 | /** | |
2183 | * sw_dis_broad_storm - disable broadstorm | |
2184 | * @hw: The hardware instance. | |
2185 | * @port: The port index. | |
2186 | * | |
2187 | * This routine disables the broadcast storm limit function of the switch. | |
2188 | */ | |
2189 | static void sw_dis_broad_storm(struct ksz_hw *hw, int port) | |
2190 | { | |
2191 | port_cfg_broad_storm(hw, port, 0); | |
2192 | } | |
2193 | ||
2194 | /** | |
2195 | * sw_ena_broad_storm - enable broadcast storm | |
2196 | * @hw: The hardware instance. | |
2197 | * @port: The port index. | |
2198 | * | |
2199 | * This routine enables the broadcast storm limit function of the switch. | |
2200 | */ | |
2201 | static void sw_ena_broad_storm(struct ksz_hw *hw, int port) | |
2202 | { | |
2203 | sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per); | |
2204 | port_cfg_broad_storm(hw, port, 1); | |
2205 | } | |
2206 | ||
2207 | /** | |
2208 | * sw_init_broad_storm - initialize broadcast storm | |
2209 | * @hw: The hardware instance. | |
2210 | * | |
2211 | * This routine initializes the broadcast storm limit function of the switch. | |
2212 | */ | |
2213 | static void sw_init_broad_storm(struct ksz_hw *hw) | |
2214 | { | |
2215 | int port; | |
2216 | ||
2217 | hw->ksz_switch->broad_per = 1; | |
2218 | sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per); | |
2219 | for (port = 0; port < TOTAL_PORT_NUM; port++) | |
2220 | sw_dis_broad_storm(hw, port); | |
2221 | sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, MULTICAST_STORM_DISABLE, 1); | |
2222 | } | |
2223 | ||
2224 | /** | |
2225 | * hw_cfg_broad_storm - configure broadcast storm | |
2226 | * @hw: The hardware instance. | |
2227 | * @percent: Broadcast storm threshold in percent of transmit rate. | |
2228 | * | |
2229 | * This routine configures the broadcast storm threshold of the switch. | |
2230 | * It is called by user functions. The hardware should be acquired first. | |
2231 | */ | |
2232 | static void hw_cfg_broad_storm(struct ksz_hw *hw, u8 percent) | |
2233 | { | |
2234 | if (percent > 100) | |
2235 | percent = 100; | |
2236 | ||
2237 | sw_cfg_broad_storm(hw, percent); | |
2238 | sw_get_broad_storm(hw, &percent); | |
2239 | hw->ksz_switch->broad_per = percent; | |
2240 | } | |
2241 | ||
2242 | /** | |
2243 | * sw_dis_prio_rate - disable switch priority rate | |
2244 | * @hw: The hardware instance. | |
2245 | * @port: The port index. | |
2246 | * | |
2247 | * This routine disables the priority rate function of the switch. | |
2248 | */ | |
2249 | static void sw_dis_prio_rate(struct ksz_hw *hw, int port) | |
2250 | { | |
2251 | u32 addr; | |
2252 | ||
2253 | PORT_CTRL_ADDR(port, addr); | |
2254 | addr += KS8842_PORT_IN_RATE_OFFSET; | |
2255 | writel(0, hw->io + addr); | |
2256 | } | |
2257 | ||
2258 | /** | |
2259 | * sw_init_prio_rate - initialize switch prioirty rate | |
2260 | * @hw: The hardware instance. | |
2261 | * | |
2262 | * This routine initializes the priority rate function of the switch. | |
2263 | */ | |
2264 | static void sw_init_prio_rate(struct ksz_hw *hw) | |
2265 | { | |
2266 | int port; | |
2267 | int prio; | |
2268 | struct ksz_switch *sw = hw->ksz_switch; | |
2269 | ||
2270 | for (port = 0; port < TOTAL_PORT_NUM; port++) { | |
2271 | for (prio = 0; prio < PRIO_QUEUES; prio++) { | |
2272 | sw->port_cfg[port].rx_rate[prio] = | |
2273 | sw->port_cfg[port].tx_rate[prio] = 0; | |
2274 | } | |
2275 | sw_dis_prio_rate(hw, port); | |
2276 | } | |
2277 | } | |
2278 | ||
2279 | /* Communication */ | |
2280 | ||
2281 | static inline void port_cfg_back_pressure(struct ksz_hw *hw, int p, int set) | |
2282 | { | |
2283 | port_cfg(hw, p, | |
2284 | KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE, set); | |
2285 | } | |
2286 | ||
2287 | static inline void port_cfg_force_flow_ctrl(struct ksz_hw *hw, int p, int set) | |
2288 | { | |
2289 | port_cfg(hw, p, | |
2290 | KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL, set); | |
2291 | } | |
2292 | ||
2293 | static inline int port_chk_back_pressure(struct ksz_hw *hw, int p) | |
2294 | { | |
2295 | return port_chk(hw, p, | |
2296 | KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE); | |
2297 | } | |
2298 | ||
2299 | static inline int port_chk_force_flow_ctrl(struct ksz_hw *hw, int p) | |
2300 | { | |
2301 | return port_chk(hw, p, | |
2302 | KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL); | |
2303 | } | |
2304 | ||
2305 | /* Spanning Tree */ | |
2306 | ||
2307 | static inline void port_cfg_dis_learn(struct ksz_hw *hw, int p, int set) | |
2308 | { | |
2309 | port_cfg(hw, p, | |
2310 | KS8842_PORT_CTRL_2_OFFSET, PORT_LEARN_DISABLE, set); | |
2311 | } | |
2312 | ||
2313 | static inline void port_cfg_rx(struct ksz_hw *hw, int p, int set) | |
2314 | { | |
2315 | port_cfg(hw, p, | |
2316 | KS8842_PORT_CTRL_2_OFFSET, PORT_RX_ENABLE, set); | |
2317 | } | |
2318 | ||
2319 | static inline void port_cfg_tx(struct ksz_hw *hw, int p, int set) | |
2320 | { | |
2321 | port_cfg(hw, p, | |
2322 | KS8842_PORT_CTRL_2_OFFSET, PORT_TX_ENABLE, set); | |
2323 | } | |
2324 | ||
2325 | static inline void sw_cfg_fast_aging(struct ksz_hw *hw, int set) | |
2326 | { | |
2327 | sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, SWITCH_FAST_AGING, set); | |
2328 | } | |
2329 | ||
2330 | static inline void sw_flush_dyn_mac_table(struct ksz_hw *hw) | |
2331 | { | |
2332 | if (!(hw->overrides & FAST_AGING)) { | |
2333 | sw_cfg_fast_aging(hw, 1); | |
2334 | mdelay(1); | |
2335 | sw_cfg_fast_aging(hw, 0); | |
2336 | } | |
2337 | } | |
2338 | ||
2339 | /* VLAN */ | |
2340 | ||
2341 | static inline void port_cfg_ins_tag(struct ksz_hw *hw, int p, int insert) | |
2342 | { | |
2343 | port_cfg(hw, p, | |
2344 | KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG, insert); | |
2345 | } | |
2346 | ||
2347 | static inline void port_cfg_rmv_tag(struct ksz_hw *hw, int p, int remove) | |
2348 | { | |
2349 | port_cfg(hw, p, | |
2350 | KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG, remove); | |
2351 | } | |
2352 | ||
2353 | static inline int port_chk_ins_tag(struct ksz_hw *hw, int p) | |
2354 | { | |
2355 | return port_chk(hw, p, | |
2356 | KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG); | |
2357 | } | |
2358 | ||
2359 | static inline int port_chk_rmv_tag(struct ksz_hw *hw, int p) | |
2360 | { | |
2361 | return port_chk(hw, p, | |
2362 | KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG); | |
2363 | } | |
2364 | ||
2365 | static inline void port_cfg_dis_non_vid(struct ksz_hw *hw, int p, int set) | |
2366 | { | |
2367 | port_cfg(hw, p, | |
2368 | KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID, set); | |
2369 | } | |
2370 | ||
2371 | static inline void port_cfg_in_filter(struct ksz_hw *hw, int p, int set) | |
2372 | { | |
2373 | port_cfg(hw, p, | |
2374 | KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER, set); | |
2375 | } | |
2376 | ||
2377 | static inline int port_chk_dis_non_vid(struct ksz_hw *hw, int p) | |
2378 | { | |
2379 | return port_chk(hw, p, | |
2380 | KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID); | |
2381 | } | |
2382 | ||
2383 | static inline int port_chk_in_filter(struct ksz_hw *hw, int p) | |
2384 | { | |
2385 | return port_chk(hw, p, | |
2386 | KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER); | |
2387 | } | |
2388 | ||
2389 | /* Mirroring */ | |
2390 | ||
2391 | static inline void port_cfg_mirror_sniffer(struct ksz_hw *hw, int p, int set) | |
2392 | { | |
2393 | port_cfg(hw, p, | |
2394 | KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_SNIFFER, set); | |
2395 | } | |
2396 | ||
2397 | static inline void port_cfg_mirror_rx(struct ksz_hw *hw, int p, int set) | |
2398 | { | |
2399 | port_cfg(hw, p, | |
2400 | KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_RX, set); | |
2401 | } | |
2402 | ||
2403 | static inline void port_cfg_mirror_tx(struct ksz_hw *hw, int p, int set) | |
2404 | { | |
2405 | port_cfg(hw, p, | |
2406 | KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_TX, set); | |
2407 | } | |
2408 | ||
2409 | static inline void sw_cfg_mirror_rx_tx(struct ksz_hw *hw, int set) | |
2410 | { | |
2411 | sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, SWITCH_MIRROR_RX_TX, set); | |
2412 | } | |
2413 | ||
2414 | static void sw_init_mirror(struct ksz_hw *hw) | |
2415 | { | |
2416 | int port; | |
2417 | ||
2418 | for (port = 0; port < TOTAL_PORT_NUM; port++) { | |
2419 | port_cfg_mirror_sniffer(hw, port, 0); | |
2420 | port_cfg_mirror_rx(hw, port, 0); | |
2421 | port_cfg_mirror_tx(hw, port, 0); | |
2422 | } | |
2423 | sw_cfg_mirror_rx_tx(hw, 0); | |
2424 | } | |
2425 | ||
2426 | static inline void sw_cfg_unk_def_deliver(struct ksz_hw *hw, int set) | |
2427 | { | |
2428 | sw_cfg(hw, KS8842_SWITCH_CTRL_7_OFFSET, | |
2429 | SWITCH_UNK_DEF_PORT_ENABLE, set); | |
2430 | } | |
2431 | ||
2432 | static inline int sw_cfg_chk_unk_def_deliver(struct ksz_hw *hw) | |
2433 | { | |
2434 | return sw_chk(hw, KS8842_SWITCH_CTRL_7_OFFSET, | |
2435 | SWITCH_UNK_DEF_PORT_ENABLE); | |
2436 | } | |
2437 | ||
2438 | static inline void sw_cfg_unk_def_port(struct ksz_hw *hw, int port, int set) | |
2439 | { | |
2440 | port_cfg_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0, set); | |
2441 | } | |
2442 | ||
2443 | static inline int sw_chk_unk_def_port(struct ksz_hw *hw, int port) | |
2444 | { | |
2445 | return port_chk_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0); | |
2446 | } | |
2447 | ||
2448 | /* Priority */ | |
2449 | ||
2450 | static inline void port_cfg_diffserv(struct ksz_hw *hw, int p, int set) | |
2451 | { | |
2452 | port_cfg(hw, p, | |
2453 | KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE, set); | |
2454 | } | |
2455 | ||
2456 | static inline void port_cfg_802_1p(struct ksz_hw *hw, int p, int set) | |
2457 | { | |
2458 | port_cfg(hw, p, | |
2459 | KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE, set); | |
2460 | } | |
2461 | ||
2462 | static inline void port_cfg_replace_vid(struct ksz_hw *hw, int p, int set) | |
2463 | { | |
2464 | port_cfg(hw, p, | |
2465 | KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING, set); | |
2466 | } | |
2467 | ||
2468 | static inline void port_cfg_prio(struct ksz_hw *hw, int p, int set) | |
2469 | { | |
2470 | port_cfg(hw, p, | |
2471 | KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE, set); | |
2472 | } | |
2473 | ||
2474 | static inline int port_chk_diffserv(struct ksz_hw *hw, int p) | |
2475 | { | |
2476 | return port_chk(hw, p, | |
2477 | KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE); | |
2478 | } | |
2479 | ||
2480 | static inline int port_chk_802_1p(struct ksz_hw *hw, int p) | |
2481 | { | |
2482 | return port_chk(hw, p, | |
2483 | KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE); | |
2484 | } | |
2485 | ||
2486 | static inline int port_chk_replace_vid(struct ksz_hw *hw, int p) | |
2487 | { | |
2488 | return port_chk(hw, p, | |
2489 | KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING); | |
2490 | } | |
2491 | ||
2492 | static inline int port_chk_prio(struct ksz_hw *hw, int p) | |
2493 | { | |
2494 | return port_chk(hw, p, | |
2495 | KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE); | |
2496 | } | |
2497 | ||
2498 | /** | |
2499 | * sw_dis_diffserv - disable switch DiffServ priority | |
2500 | * @hw: The hardware instance. | |
2501 | * @port: The port index. | |
2502 | * | |
2503 | * This routine disables the DiffServ priority function of the switch. | |
2504 | */ | |
2505 | static void sw_dis_diffserv(struct ksz_hw *hw, int port) | |
2506 | { | |
2507 | port_cfg_diffserv(hw, port, 0); | |
2508 | } | |
2509 | ||
2510 | /** | |
2511 | * sw_dis_802_1p - disable switch 802.1p priority | |
2512 | * @hw: The hardware instance. | |
2513 | * @port: The port index. | |
2514 | * | |
2515 | * This routine disables the 802.1p priority function of the switch. | |
2516 | */ | |
2517 | static void sw_dis_802_1p(struct ksz_hw *hw, int port) | |
2518 | { | |
2519 | port_cfg_802_1p(hw, port, 0); | |
2520 | } | |
2521 | ||
2522 | /** | |
2523 | * sw_cfg_replace_null_vid - | |
2524 | * @hw: The hardware instance. | |
2525 | * @set: The flag to disable or enable. | |
2526 | * | |
2527 | */ | |
2528 | static void sw_cfg_replace_null_vid(struct ksz_hw *hw, int set) | |
2529 | { | |
2530 | sw_cfg(hw, KS8842_SWITCH_CTRL_3_OFFSET, SWITCH_REPLACE_NULL_VID, set); | |
2531 | } | |
2532 | ||
2533 | /** | |
2534 | * sw_cfg_replace_vid - enable switch 802.10 priority re-mapping | |
2535 | * @hw: The hardware instance. | |
2536 | * @port: The port index. | |
2537 | * @set: The flag to disable or enable. | |
2538 | * | |
2539 | * This routine enables the 802.1p priority re-mapping function of the switch. | |
2540 | * That allows 802.1p priority field to be replaced with the port's default | |
2541 | * tag's priority value if the ingress packet's 802.1p priority has a higher | |
2542 | * priority than port's default tag's priority. | |
2543 | */ | |
2544 | static void sw_cfg_replace_vid(struct ksz_hw *hw, int port, int set) | |
2545 | { | |
2546 | port_cfg_replace_vid(hw, port, set); | |
2547 | } | |
2548 | ||
2549 | /** | |
2550 | * sw_cfg_port_based - configure switch port based priority | |
2551 | * @hw: The hardware instance. | |
2552 | * @port: The port index. | |
2553 | * @prio: The priority to set. | |
2554 | * | |
2555 | * This routine configures the port based priority of the switch. | |
2556 | */ | |
2557 | static void sw_cfg_port_based(struct ksz_hw *hw, int port, u8 prio) | |
2558 | { | |
2559 | u16 data; | |
2560 | ||
2561 | if (prio > PORT_BASED_PRIORITY_BASE) | |
2562 | prio = PORT_BASED_PRIORITY_BASE; | |
2563 | ||
2564 | hw->ksz_switch->port_cfg[port].port_prio = prio; | |
2565 | ||
2566 | port_r16(hw, port, KS8842_PORT_CTRL_1_OFFSET, &data); | |
2567 | data &= ~PORT_BASED_PRIORITY_MASK; | |
2568 | data |= prio << PORT_BASED_PRIORITY_SHIFT; | |
2569 | port_w16(hw, port, KS8842_PORT_CTRL_1_OFFSET, data); | |
2570 | } | |
2571 | ||
2572 | /** | |
2573 | * sw_dis_multi_queue - disable transmit multiple queues | |
2574 | * @hw: The hardware instance. | |
2575 | * @port: The port index. | |
2576 | * | |
2577 | * This routine disables the transmit multiple queues selection of the switch | |
2578 | * port. Only single transmit queue on the port. | |
2579 | */ | |
2580 | static void sw_dis_multi_queue(struct ksz_hw *hw, int port) | |
2581 | { | |
2582 | port_cfg_prio(hw, port, 0); | |
2583 | } | |
2584 | ||
2585 | /** | |
2586 | * sw_init_prio - initialize switch priority | |
2587 | * @hw: The hardware instance. | |
2588 | * | |
2589 | * This routine initializes the switch QoS priority functions. | |
2590 | */ | |
2591 | static void sw_init_prio(struct ksz_hw *hw) | |
2592 | { | |
2593 | int port; | |
2594 | int tos; | |
2595 | struct ksz_switch *sw = hw->ksz_switch; | |
2596 | ||
2597 | /* | |
2598 | * Init all the 802.1p tag priority value to be assigned to different | |
2599 | * priority queue. | |
2600 | */ | |
2601 | sw->p_802_1p[0] = 0; | |
2602 | sw->p_802_1p[1] = 0; | |
2603 | sw->p_802_1p[2] = 1; | |
2604 | sw->p_802_1p[3] = 1; | |
2605 | sw->p_802_1p[4] = 2; | |
2606 | sw->p_802_1p[5] = 2; | |
2607 | sw->p_802_1p[6] = 3; | |
2608 | sw->p_802_1p[7] = 3; | |
2609 | ||
2610 | /* | |
2611 | * Init all the DiffServ priority value to be assigned to priority | |
2612 | * queue 0. | |
2613 | */ | |
2614 | for (tos = 0; tos < DIFFSERV_ENTRIES; tos++) | |
2615 | sw->diffserv[tos] = 0; | |
2616 | ||
2617 | /* All QoS functions disabled. */ | |
2618 | for (port = 0; port < TOTAL_PORT_NUM; port++) { | |
2619 | sw_dis_multi_queue(hw, port); | |
2620 | sw_dis_diffserv(hw, port); | |
2621 | sw_dis_802_1p(hw, port); | |
2622 | sw_cfg_replace_vid(hw, port, 0); | |
2623 | ||
2624 | sw->port_cfg[port].port_prio = 0; | |
2625 | sw_cfg_port_based(hw, port, sw->port_cfg[port].port_prio); | |
2626 | } | |
2627 | sw_cfg_replace_null_vid(hw, 0); | |
2628 | } | |
2629 | ||
2630 | /** | |
2631 | * port_get_def_vid - get port default VID. | |
2632 | * @hw: The hardware instance. | |
2633 | * @port: The port index. | |
2634 | * @vid: Buffer to store the VID. | |
2635 | * | |
2636 | * This routine retrieves the default VID of the port. | |
2637 | */ | |
2638 | static void port_get_def_vid(struct ksz_hw *hw, int port, u16 *vid) | |
2639 | { | |
2640 | u32 addr; | |
2641 | ||
2642 | PORT_CTRL_ADDR(port, addr); | |
2643 | addr += KS8842_PORT_CTRL_VID_OFFSET; | |
2644 | *vid = readw(hw->io + addr); | |
2645 | } | |
2646 | ||
2647 | /** | |
2648 | * sw_init_vlan - initialize switch VLAN | |
2649 | * @hw: The hardware instance. | |
2650 | * | |
2651 | * This routine initializes the VLAN function of the switch. | |
2652 | */ | |
2653 | static void sw_init_vlan(struct ksz_hw *hw) | |
2654 | { | |
2655 | int port; | |
2656 | int entry; | |
2657 | struct ksz_switch *sw = hw->ksz_switch; | |
2658 | ||
2659 | /* Read 16 VLAN entries from device's VLAN table. */ | |
2660 | for (entry = 0; entry < VLAN_TABLE_ENTRIES; entry++) { | |
2661 | sw_r_vlan_table(hw, entry, | |
2662 | &sw->vlan_table[entry].vid, | |
2663 | &sw->vlan_table[entry].fid, | |
2664 | &sw->vlan_table[entry].member); | |
2665 | } | |
2666 | ||
2667 | for (port = 0; port < TOTAL_PORT_NUM; port++) { | |
2668 | port_get_def_vid(hw, port, &sw->port_cfg[port].vid); | |
2669 | sw->port_cfg[port].member = PORT_MASK; | |
2670 | } | |
2671 | } | |
2672 | ||
2673 | /** | |
2674 | * sw_cfg_port_base_vlan - configure port-based VLAN membership | |
2675 | * @hw: The hardware instance. | |
2676 | * @port: The port index. | |
2677 | * @member: The port-based VLAN membership. | |
2678 | * | |
2679 | * This routine configures the port-based VLAN membership of the port. | |
2680 | */ | |
2681 | static void sw_cfg_port_base_vlan(struct ksz_hw *hw, int port, u8 member) | |
2682 | { | |
2683 | u32 addr; | |
2684 | u8 data; | |
2685 | ||
2686 | PORT_CTRL_ADDR(port, addr); | |
2687 | addr += KS8842_PORT_CTRL_2_OFFSET; | |
2688 | ||
2689 | data = readb(hw->io + addr); | |
2690 | data &= ~PORT_VLAN_MEMBERSHIP; | |
2691 | data |= (member & PORT_MASK); | |
2692 | writeb(data, hw->io + addr); | |
2693 | ||
2694 | hw->ksz_switch->port_cfg[port].member = member; | |
2695 | } | |
2696 | ||
2697 | /** | |
2698 | * sw_get_addr - get the switch MAC address. | |
2699 | * @hw: The hardware instance. | |
2700 | * @mac_addr: Buffer to store the MAC address. | |
2701 | * | |
2702 | * This function retrieves the MAC address of the switch. | |
2703 | */ | |
2704 | static inline void sw_get_addr(struct ksz_hw *hw, u8 *mac_addr) | |
2705 | { | |
2706 | int i; | |
2707 | ||
2708 | for (i = 0; i < 6; i += 2) { | |
2709 | mac_addr[i] = readb(hw->io + KS8842_MAC_ADDR_0_OFFSET + i); | |
2710 | mac_addr[1 + i] = readb(hw->io + KS8842_MAC_ADDR_1_OFFSET + i); | |
2711 | } | |
2712 | } | |
2713 | ||
2714 | /** | |
2715 | * sw_set_addr - configure switch MAC address | |
2716 | * @hw: The hardware instance. | |
2717 | * @mac_addr: The MAC address. | |
2718 | * | |
2719 | * This function configures the MAC address of the switch. | |
2720 | */ | |
2721 | static void sw_set_addr(struct ksz_hw *hw, u8 *mac_addr) | |
2722 | { | |
2723 | int i; | |
2724 | ||
2725 | for (i = 0; i < 6; i += 2) { | |
2726 | writeb(mac_addr[i], hw->io + KS8842_MAC_ADDR_0_OFFSET + i); | |
2727 | writeb(mac_addr[1 + i], hw->io + KS8842_MAC_ADDR_1_OFFSET + i); | |
2728 | } | |
2729 | } | |
2730 | ||
2731 | /** | |
2732 | * sw_set_global_ctrl - set switch global control | |
2733 | * @hw: The hardware instance. | |
2734 | * | |
2735 | * This routine sets the global control of the switch function. | |
2736 | */ | |
2737 | static void sw_set_global_ctrl(struct ksz_hw *hw) | |
2738 | { | |
2739 | u16 data; | |
2740 | ||
2741 | /* Enable switch MII flow control. */ | |
2742 | data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET); | |
2743 | data |= SWITCH_FLOW_CTRL; | |
2744 | writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET); | |
2745 | ||
2746 | data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET); | |
2747 | ||
2748 | /* Enable aggressive back off algorithm in half duplex mode. */ | |
2749 | data |= SWITCH_AGGR_BACKOFF; | |
2750 | ||
2751 | /* Enable automatic fast aging when link changed detected. */ | |
2752 | data |= SWITCH_AGING_ENABLE; | |
2753 | data |= SWITCH_LINK_AUTO_AGING; | |
2754 | ||
2755 | if (hw->overrides & FAST_AGING) | |
2756 | data |= SWITCH_FAST_AGING; | |
2757 | else | |
2758 | data &= ~SWITCH_FAST_AGING; | |
2759 | writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET); | |
2760 | ||
2761 | data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET); | |
2762 | ||
2763 | /* Enable no excessive collision drop. */ | |
2764 | data |= NO_EXC_COLLISION_DROP; | |
2765 | writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET); | |
2766 | } | |
2767 | ||
2768 | enum { | |
2769 | STP_STATE_DISABLED = 0, | |
2770 | STP_STATE_LISTENING, | |
2771 | STP_STATE_LEARNING, | |
2772 | STP_STATE_FORWARDING, | |
2773 | STP_STATE_BLOCKED, | |
2774 | STP_STATE_SIMPLE | |
2775 | }; | |
2776 | ||
2777 | /** | |
2778 | * port_set_stp_state - configure port spanning tree state | |
2779 | * @hw: The hardware instance. | |
2780 | * @port: The port index. | |
2781 | * @state: The spanning tree state. | |
2782 | * | |
2783 | * This routine configures the spanning tree state of the port. | |
2784 | */ | |
2785 | static void port_set_stp_state(struct ksz_hw *hw, int port, int state) | |
2786 | { | |
2787 | u16 data; | |
2788 | ||
2789 | port_r16(hw, port, KS8842_PORT_CTRL_2_OFFSET, &data); | |
2790 | switch (state) { | |
2791 | case STP_STATE_DISABLED: | |
2792 | data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE); | |
2793 | data |= PORT_LEARN_DISABLE; | |
2794 | break; | |
2795 | case STP_STATE_LISTENING: | |
2796 | /* | |
2797 | * No need to turn on transmit because of port direct mode. | |
2798 | * Turning on receive is required if static MAC table is not setup. | |
2799 | */ | |
2800 | data &= ~PORT_TX_ENABLE; | |
2801 | data |= PORT_RX_ENABLE; | |
2802 | data |= PORT_LEARN_DISABLE; | |
2803 | break; | |
2804 | case STP_STATE_LEARNING: | |
2805 | data &= ~PORT_TX_ENABLE; | |
2806 | data |= PORT_RX_ENABLE; | |
2807 | data &= ~PORT_LEARN_DISABLE; | |
2808 | break; | |
2809 | case STP_STATE_FORWARDING: | |
2810 | data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); | |
2811 | data &= ~PORT_LEARN_DISABLE; | |
2812 | break; | |
2813 | case STP_STATE_BLOCKED: | |
2814 | /* | |
2815 | * Need to setup static MAC table with override to keep receiving BPDU | |
2816 | * messages. See sw_init_stp routine. | |
2817 | */ | |
2818 | data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE); | |
2819 | data |= PORT_LEARN_DISABLE; | |
2820 | break; | |
2821 | case STP_STATE_SIMPLE: | |
2822 | data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); | |
2823 | data |= PORT_LEARN_DISABLE; | |
2824 | break; | |
2825 | } | |
2826 | port_w16(hw, port, KS8842_PORT_CTRL_2_OFFSET, data); | |
2827 | hw->ksz_switch->port_cfg[port].stp_state = state; | |
2828 | } | |
2829 | ||
2830 | #define STP_ENTRY 0 | |
2831 | #define BROADCAST_ENTRY 1 | |
2832 | #define BRIDGE_ADDR_ENTRY 2 | |
2833 | #define IPV6_ADDR_ENTRY 3 | |
2834 | ||
2835 | /** | |
2836 | * sw_clr_sta_mac_table - clear static MAC table | |
2837 | * @hw: The hardware instance. | |
2838 | * | |
2839 | * This routine clears the static MAC table. | |
2840 | */ | |
2841 | static void sw_clr_sta_mac_table(struct ksz_hw *hw) | |
2842 | { | |
2843 | struct ksz_mac_table *entry; | |
2844 | int i; | |
2845 | ||
2846 | for (i = 0; i < STATIC_MAC_TABLE_ENTRIES; i++) { | |
2847 | entry = &hw->ksz_switch->mac_table[i]; | |
2848 | sw_w_sta_mac_table(hw, i, | |
2849 | entry->mac_addr, entry->ports, | |
2850 | entry->override, 0, | |
2851 | entry->use_fid, entry->fid); | |
2852 | } | |
2853 | } | |
2854 | ||
2855 | /** | |
2856 | * sw_init_stp - initialize switch spanning tree support | |
2857 | * @hw: The hardware instance. | |
2858 | * | |
2859 | * This routine initializes the spanning tree support of the switch. | |
2860 | */ | |
2861 | static void sw_init_stp(struct ksz_hw *hw) | |
2862 | { | |
2863 | struct ksz_mac_table *entry; | |
2864 | ||
2865 | entry = &hw->ksz_switch->mac_table[STP_ENTRY]; | |
2866 | entry->mac_addr[0] = 0x01; | |
2867 | entry->mac_addr[1] = 0x80; | |
2868 | entry->mac_addr[2] = 0xC2; | |
2869 | entry->mac_addr[3] = 0x00; | |
2870 | entry->mac_addr[4] = 0x00; | |
2871 | entry->mac_addr[5] = 0x00; | |
2872 | entry->ports = HOST_MASK; | |
2873 | entry->override = 1; | |
2874 | entry->valid = 1; | |
2875 | sw_w_sta_mac_table(hw, STP_ENTRY, | |
2876 | entry->mac_addr, entry->ports, | |
2877 | entry->override, entry->valid, | |
2878 | entry->use_fid, entry->fid); | |
2879 | } | |
2880 | ||
2881 | /** | |
2882 | * sw_block_addr - block certain packets from the host port | |
2883 | * @hw: The hardware instance. | |
2884 | * | |
2885 | * This routine blocks certain packets from reaching to the host port. | |
2886 | */ | |
2887 | static void sw_block_addr(struct ksz_hw *hw) | |
2888 | { | |
2889 | struct ksz_mac_table *entry; | |
2890 | int i; | |
2891 | ||
2892 | for (i = BROADCAST_ENTRY; i <= IPV6_ADDR_ENTRY; i++) { | |
2893 | entry = &hw->ksz_switch->mac_table[i]; | |
2894 | entry->valid = 0; | |
2895 | sw_w_sta_mac_table(hw, i, | |
2896 | entry->mac_addr, entry->ports, | |
2897 | entry->override, entry->valid, | |
2898 | entry->use_fid, entry->fid); | |
2899 | } | |
2900 | } | |
2901 | ||
2902 | #define PHY_LINK_SUPPORT \ | |
2903 | (PHY_AUTO_NEG_ASYM_PAUSE | \ | |
2904 | PHY_AUTO_NEG_SYM_PAUSE | \ | |
2905 | PHY_AUTO_NEG_100BT4 | \ | |
2906 | PHY_AUTO_NEG_100BTX_FD | \ | |
2907 | PHY_AUTO_NEG_100BTX | \ | |
2908 | PHY_AUTO_NEG_10BT_FD | \ | |
2909 | PHY_AUTO_NEG_10BT) | |
2910 | ||
2911 | static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data) | |
2912 | { | |
2913 | *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET); | |
2914 | } | |
2915 | ||
2916 | static inline void hw_w_phy_ctrl(struct ksz_hw *hw, int phy, u16 data) | |
2917 | { | |
2918 | writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET); | |
2919 | } | |
2920 | ||
2921 | static inline void hw_r_phy_link_stat(struct ksz_hw *hw, int phy, u16 *data) | |
2922 | { | |
2923 | *data = readw(hw->io + phy + KS884X_PHY_STATUS_OFFSET); | |
2924 | } | |
2925 | ||
2926 | static inline void hw_r_phy_auto_neg(struct ksz_hw *hw, int phy, u16 *data) | |
2927 | { | |
2928 | *data = readw(hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET); | |
2929 | } | |
2930 | ||
2931 | static inline void hw_w_phy_auto_neg(struct ksz_hw *hw, int phy, u16 data) | |
2932 | { | |
2933 | writew(data, hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET); | |
2934 | } | |
2935 | ||
2936 | static inline void hw_r_phy_rem_cap(struct ksz_hw *hw, int phy, u16 *data) | |
2937 | { | |
2938 | *data = readw(hw->io + phy + KS884X_PHY_REMOTE_CAP_OFFSET); | |
2939 | } | |
2940 | ||
2941 | static inline void hw_r_phy_crossover(struct ksz_hw *hw, int phy, u16 *data) | |
2942 | { | |
2943 | *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET); | |
2944 | } | |
2945 | ||
2946 | static inline void hw_w_phy_crossover(struct ksz_hw *hw, int phy, u16 data) | |
2947 | { | |
2948 | writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET); | |
2949 | } | |
2950 | ||
2951 | static inline void hw_r_phy_polarity(struct ksz_hw *hw, int phy, u16 *data) | |
2952 | { | |
2953 | *data = readw(hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET); | |
2954 | } | |
2955 | ||
2956 | static inline void hw_w_phy_polarity(struct ksz_hw *hw, int phy, u16 data) | |
2957 | { | |
2958 | writew(data, hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET); | |
2959 | } | |
2960 | ||
2961 | static inline void hw_r_phy_link_md(struct ksz_hw *hw, int phy, u16 *data) | |
2962 | { | |
2963 | *data = readw(hw->io + phy + KS884X_PHY_LINK_MD_OFFSET); | |
2964 | } | |
2965 | ||
2966 | static inline void hw_w_phy_link_md(struct ksz_hw *hw, int phy, u16 data) | |
2967 | { | |
2968 | writew(data, hw->io + phy + KS884X_PHY_LINK_MD_OFFSET); | |
2969 | } | |
2970 | ||
2971 | /** | |
2972 | * hw_r_phy - read data from PHY register | |
2973 | * @hw: The hardware instance. | |
2974 | * @port: Port to read. | |
2975 | * @reg: PHY register to read. | |
2976 | * @val: Buffer to store the read data. | |
2977 | * | |
2978 | * This routine reads data from the PHY register. | |
2979 | */ | |
2980 | static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val) | |
2981 | { | |
2982 | int phy; | |
2983 | ||
2984 | phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg; | |
2985 | *val = readw(hw->io + phy); | |
2986 | } | |
2987 | ||
2988 | /** | |
2989 | * port_w_phy - write data to PHY register | |
2990 | * @hw: The hardware instance. | |
2991 | * @port: Port to write. | |
2992 | * @reg: PHY register to write. | |
2993 | * @val: Word data to write. | |
2994 | * | |
2995 | * This routine writes data to the PHY register. | |
2996 | */ | |
2997 | static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val) | |
2998 | { | |
2999 | int phy; | |
3000 | ||
3001 | phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg; | |
3002 | writew(val, hw->io + phy); | |
3003 | } | |
3004 | ||
3005 | /* | |
3006 | * EEPROM access functions | |
3007 | */ | |
3008 | ||
3009 | #define AT93C_CODE 0 | |
3010 | #define AT93C_WR_OFF 0x00 | |
3011 | #define AT93C_WR_ALL 0x10 | |
3012 | #define AT93C_ER_ALL 0x20 | |
3013 | #define AT93C_WR_ON 0x30 | |
3014 | ||
3015 | #define AT93C_WRITE 1 | |
3016 | #define AT93C_READ 2 | |
3017 | #define AT93C_ERASE 3 | |
3018 | ||
3019 | #define EEPROM_DELAY 4 | |
3020 | ||
3021 | static inline void drop_gpio(struct ksz_hw *hw, u8 gpio) | |
3022 | { | |
3023 | u16 data; | |
3024 | ||
3025 | data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET); | |
3026 | data &= ~gpio; | |
3027 | writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET); | |
3028 | } | |
3029 | ||
3030 | static inline void raise_gpio(struct ksz_hw *hw, u8 gpio) | |
3031 | { | |
3032 | u16 data; | |
3033 | ||
3034 | data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET); | |
3035 | data |= gpio; | |
3036 | writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET); | |
3037 | } | |
3038 | ||
3039 | static inline u8 state_gpio(struct ksz_hw *hw, u8 gpio) | |
3040 | { | |
3041 | u16 data; | |
3042 | ||
3043 | data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET); | |
3044 | return (u8)(data & gpio); | |
3045 | } | |
3046 | ||
3047 | static void eeprom_clk(struct ksz_hw *hw) | |
3048 | { | |
3049 | raise_gpio(hw, EEPROM_SERIAL_CLOCK); | |
3050 | udelay(EEPROM_DELAY); | |
3051 | drop_gpio(hw, EEPROM_SERIAL_CLOCK); | |
3052 | udelay(EEPROM_DELAY); | |
3053 | } | |
3054 | ||
3055 | static u16 spi_r(struct ksz_hw *hw) | |
3056 | { | |
3057 | int i; | |
3058 | u16 temp = 0; | |
3059 | ||
3060 | for (i = 15; i >= 0; i--) { | |
3061 | raise_gpio(hw, EEPROM_SERIAL_CLOCK); | |
3062 | udelay(EEPROM_DELAY); | |
3063 | ||
3064 | temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0; | |
3065 | ||
3066 | drop_gpio(hw, EEPROM_SERIAL_CLOCK); | |
3067 | udelay(EEPROM_DELAY); | |
3068 | } | |
3069 | return temp; | |
3070 | } | |
3071 | ||
3072 | static void spi_w(struct ksz_hw *hw, u16 data) | |
3073 | { | |
3074 | int i; | |
3075 | ||
3076 | for (i = 15; i >= 0; i--) { | |
3077 | (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : | |
3078 | drop_gpio(hw, EEPROM_DATA_OUT); | |
3079 | eeprom_clk(hw); | |
3080 | } | |
3081 | } | |
3082 | ||
3083 | static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg) | |
3084 | { | |
3085 | int i; | |
3086 | ||
3087 | /* Initial start bit */ | |
3088 | raise_gpio(hw, EEPROM_DATA_OUT); | |
3089 | eeprom_clk(hw); | |
3090 | ||
3091 | /* AT93C operation */ | |
3092 | for (i = 1; i >= 0; i--) { | |
3093 | (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : | |
3094 | drop_gpio(hw, EEPROM_DATA_OUT); | |
3095 | eeprom_clk(hw); | |
3096 | } | |
3097 | ||
3098 | /* Address location */ | |
3099 | for (i = 5; i >= 0; i--) { | |
3100 | (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : | |
3101 | drop_gpio(hw, EEPROM_DATA_OUT); | |
3102 | eeprom_clk(hw); | |
3103 | } | |
3104 | } | |
3105 | ||
3106 | #define EEPROM_DATA_RESERVED 0 | |
3107 | #define EEPROM_DATA_MAC_ADDR_0 1 | |
3108 | #define EEPROM_DATA_MAC_ADDR_1 2 | |
3109 | #define EEPROM_DATA_MAC_ADDR_2 3 | |
3110 | #define EEPROM_DATA_SUBSYS_ID 4 | |
3111 | #define EEPROM_DATA_SUBSYS_VEN_ID 5 | |
3112 | #define EEPROM_DATA_PM_CAP 6 | |
3113 | ||
3114 | /* User defined EEPROM data */ | |
3115 | #define EEPROM_DATA_OTHER_MAC_ADDR 9 | |
3116 | ||
3117 | /** | |
3118 | * eeprom_read - read from AT93C46 EEPROM | |
3119 | * @hw: The hardware instance. | |
3120 | * @reg: The register offset. | |
3121 | * | |
3122 | * This function reads a word from the AT93C46 EEPROM. | |
3123 | * | |
3124 | * Return the data value. | |
3125 | */ | |
3126 | static u16 eeprom_read(struct ksz_hw *hw, u8 reg) | |
3127 | { | |
3128 | u16 data; | |
3129 | ||
3130 | raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT); | |
3131 | ||
3132 | spi_reg(hw, AT93C_READ, reg); | |
3133 | data = spi_r(hw); | |
3134 | ||
3135 | drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT); | |
3136 | ||
3137 | return data; | |
3138 | } | |
3139 | ||
3140 | /** | |
3141 | * eeprom_write - write to AT93C46 EEPROM | |
3142 | * @hw: The hardware instance. | |
3143 | * @reg: The register offset. | |
3144 | * @data: The data value. | |
3145 | * | |
3146 | * This procedure writes a word to the AT93C46 EEPROM. | |
3147 | */ | |
3148 | static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data) | |
3149 | { | |
3150 | int timeout; | |
3151 | ||
3152 | raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT); | |
3153 | ||
3154 | /* Enable write. */ | |
3155 | spi_reg(hw, AT93C_CODE, AT93C_WR_ON); | |
3156 | drop_gpio(hw, EEPROM_CHIP_SELECT); | |
3157 | udelay(1); | |
3158 | ||
3159 | /* Erase the register. */ | |
3160 | raise_gpio(hw, EEPROM_CHIP_SELECT); | |
3161 | spi_reg(hw, AT93C_ERASE, reg); | |
3162 | drop_gpio(hw, EEPROM_CHIP_SELECT); | |
3163 | udelay(1); | |
3164 | ||
3165 | /* Check operation complete. */ | |
3166 | raise_gpio(hw, EEPROM_CHIP_SELECT); | |
3167 | timeout = 8; | |
3168 | mdelay(2); | |
3169 | do { | |
3170 | mdelay(1); | |
3171 | } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout); | |
3172 | drop_gpio(hw, EEPROM_CHIP_SELECT); | |
3173 | udelay(1); | |
3174 | ||
3175 | /* Write the register. */ | |
3176 | raise_gpio(hw, EEPROM_CHIP_SELECT); | |
3177 | spi_reg(hw, AT93C_WRITE, reg); | |
3178 | spi_w(hw, data); | |
3179 | drop_gpio(hw, EEPROM_CHIP_SELECT); | |
3180 | udelay(1); | |
3181 | ||
3182 | /* Check operation complete. */ | |
3183 | raise_gpio(hw, EEPROM_CHIP_SELECT); | |
3184 | timeout = 8; | |
3185 | mdelay(2); | |
3186 | do { | |
3187 | mdelay(1); | |
3188 | } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout); | |
3189 | drop_gpio(hw, EEPROM_CHIP_SELECT); | |
3190 | udelay(1); | |
3191 | ||
3192 | /* Disable write. */ | |
3193 | raise_gpio(hw, EEPROM_CHIP_SELECT); | |
3194 | spi_reg(hw, AT93C_CODE, AT93C_WR_OFF); | |
3195 | ||
3196 | drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT); | |
3197 | } | |
3198 | ||
3199 | /* | |
3200 | * Link detection routines | |
3201 | */ | |
3202 | ||
3203 | static u16 advertised_flow_ctrl(struct ksz_port *port, u16 ctrl) | |
3204 | { | |
3205 | ctrl &= ~PORT_AUTO_NEG_SYM_PAUSE; | |
3206 | switch (port->flow_ctrl) { | |
3207 | case PHY_FLOW_CTRL: | |
3208 | ctrl |= PORT_AUTO_NEG_SYM_PAUSE; | |
3209 | break; | |
3210 | /* Not supported. */ | |
3211 | case PHY_TX_ONLY: | |
3212 | case PHY_RX_ONLY: | |
3213 | default: | |
3214 | break; | |
3215 | } | |
3216 | return ctrl; | |
3217 | } | |
3218 | ||
3219 | static void set_flow_ctrl(struct ksz_hw *hw, int rx, int tx) | |
3220 | { | |
3221 | u32 rx_cfg; | |
3222 | u32 tx_cfg; | |
3223 | ||
3224 | rx_cfg = hw->rx_cfg; | |
3225 | tx_cfg = hw->tx_cfg; | |
3226 | if (rx) | |
3227 | hw->rx_cfg |= DMA_RX_FLOW_ENABLE; | |
3228 | else | |
3229 | hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE; | |
3230 | if (tx) | |
3231 | hw->tx_cfg |= DMA_TX_FLOW_ENABLE; | |
3232 | else | |
3233 | hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE; | |
3234 | if (hw->enabled) { | |
3235 | if (rx_cfg != hw->rx_cfg) | |
3236 | writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL); | |
3237 | if (tx_cfg != hw->tx_cfg) | |
3238 | writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL); | |
3239 | } | |
3240 | } | |
3241 | ||
3242 | static void determine_flow_ctrl(struct ksz_hw *hw, struct ksz_port *port, | |
3243 | u16 local, u16 remote) | |
3244 | { | |
3245 | int rx; | |
3246 | int tx; | |
3247 | ||
3248 | if (hw->overrides & PAUSE_FLOW_CTRL) | |
3249 | return; | |
3250 | ||
3251 | rx = tx = 0; | |
3252 | if (port->force_link) | |
3253 | rx = tx = 1; | |
3254 | if (remote & PHY_AUTO_NEG_SYM_PAUSE) { | |
3255 | if (local & PHY_AUTO_NEG_SYM_PAUSE) { | |
3256 | rx = tx = 1; | |
3257 | } else if ((remote & PHY_AUTO_NEG_ASYM_PAUSE) && | |
3258 | (local & PHY_AUTO_NEG_PAUSE) == | |
3259 | PHY_AUTO_NEG_ASYM_PAUSE) { | |
3260 | tx = 1; | |
3261 | } | |
3262 | } else if (remote & PHY_AUTO_NEG_ASYM_PAUSE) { | |
3263 | if ((local & PHY_AUTO_NEG_PAUSE) == PHY_AUTO_NEG_PAUSE) | |
3264 | rx = 1; | |
3265 | } | |
3266 | if (!hw->ksz_switch) | |
3267 | set_flow_ctrl(hw, rx, tx); | |
3268 | } | |
3269 | ||
3270 | static inline void port_cfg_change(struct ksz_hw *hw, struct ksz_port *port, | |
3271 | struct ksz_port_info *info, u16 link_status) | |
3272 | { | |
3273 | if ((hw->features & HALF_DUPLEX_SIGNAL_BUG) && | |
3274 | !(hw->overrides & PAUSE_FLOW_CTRL)) { | |
3275 | u32 cfg = hw->tx_cfg; | |
3276 | ||
3277 | /* Disable flow control in the half duplex mode. */ | |
3278 | if (1 == info->duplex) | |
3279 | hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE; | |
3280 | if (hw->enabled && cfg != hw->tx_cfg) | |
3281 | writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL); | |
3282 | } | |
3283 | } | |
3284 | ||
3285 | /** | |
3286 | * port_get_link_speed - get current link status | |
3287 | * @port: The port instance. | |
3288 | * | |
3289 | * This routine reads PHY registers to determine the current link status of the | |
3290 | * switch ports. | |
3291 | */ | |
3292 | static void port_get_link_speed(struct ksz_port *port) | |
3293 | { | |
3294 | uint interrupt; | |
3295 | struct ksz_port_info *info; | |
3296 | struct ksz_port_info *linked = NULL; | |
3297 | struct ksz_hw *hw = port->hw; | |
3298 | u16 data; | |
3299 | u16 status; | |
3300 | u8 local; | |
3301 | u8 remote; | |
3302 | int i; | |
3303 | int p; | |
3304 | int change = 0; | |
3305 | ||
3306 | interrupt = hw_block_intr(hw); | |
3307 | ||
3308 | for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { | |
3309 | info = &hw->port_info[p]; | |
3310 | port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data); | |
3311 | port_r16(hw, p, KS884X_PORT_STATUS_OFFSET, &status); | |
3312 | ||
3313 | /* | |
3314 | * Link status is changing all the time even when there is no | |
3315 | * cable connection! | |
3316 | */ | |
3317 | remote = status & (PORT_AUTO_NEG_COMPLETE | | |
3318 | PORT_STATUS_LINK_GOOD); | |
3319 | local = (u8) data; | |
3320 | ||
3321 | /* No change to status. */ | |
3322 | if (local == info->advertised && remote == info->partner) | |
3323 | continue; | |
3324 | ||
3325 | info->advertised = local; | |
3326 | info->partner = remote; | |
3327 | if (status & PORT_STATUS_LINK_GOOD) { | |
3328 | ||
3329 | /* Remember the first linked port. */ | |
3330 | if (!linked) | |
3331 | linked = info; | |
3332 | ||
3333 | info->tx_rate = 10 * TX_RATE_UNIT; | |
3334 | if (status & PORT_STATUS_SPEED_100MBIT) | |
3335 | info->tx_rate = 100 * TX_RATE_UNIT; | |
3336 | ||
3337 | info->duplex = 1; | |
3338 | if (status & PORT_STATUS_FULL_DUPLEX) | |
3339 | info->duplex = 2; | |
3340 | ||
3341 | if (media_connected != info->state) { | |
3342 | hw_r_phy(hw, p, KS884X_PHY_AUTO_NEG_OFFSET, | |
3343 | &data); | |
3344 | hw_r_phy(hw, p, KS884X_PHY_REMOTE_CAP_OFFSET, | |
3345 | &status); | |
3346 | determine_flow_ctrl(hw, port, data, status); | |
3347 | if (hw->ksz_switch) { | |
3348 | port_cfg_back_pressure(hw, p, | |
3349 | (1 == info->duplex)); | |
3350 | } | |
3351 | change |= 1 << i; | |
3352 | port_cfg_change(hw, port, info, status); | |
3353 | } | |
3354 | info->state = media_connected; | |
3355 | } else { | |
3356 | if (media_disconnected != info->state) { | |
3357 | change |= 1 << i; | |
3358 | ||
3359 | /* Indicate the link just goes down. */ | |
3360 | hw->port_mib[p].link_down = 1; | |
3361 | } | |
3362 | info->state = media_disconnected; | |
3363 | } | |
3364 | hw->port_mib[p].state = (u8) info->state; | |
3365 | } | |
3366 | ||
3367 | if (linked && media_disconnected == port->linked->state) | |
3368 | port->linked = linked; | |
3369 | ||
3370 | hw_restore_intr(hw, interrupt); | |
3371 | } | |
3372 | ||
3373 | #define PHY_RESET_TIMEOUT 10 | |
3374 | ||
3375 | /** | |
3376 | * port_set_link_speed - set port speed | |
3377 | * @port: The port instance. | |
3378 | * | |
3379 | * This routine sets the link speed of the switch ports. | |
3380 | */ | |
3381 | static void port_set_link_speed(struct ksz_port *port) | |
3382 | { | |
3383 | struct ksz_port_info *info; | |
3384 | struct ksz_hw *hw = port->hw; | |
3385 | u16 data; | |
3386 | u16 cfg; | |
3387 | u8 status; | |
3388 | int i; | |
3389 | int p; | |
3390 | ||
3391 | for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { | |
3392 | info = &hw->port_info[p]; | |
3393 | ||
3394 | port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data); | |
3395 | port_r8(hw, p, KS884X_PORT_STATUS_OFFSET, &status); | |
3396 | ||
3397 | cfg = 0; | |
3398 | if (status & PORT_STATUS_LINK_GOOD) | |
3399 | cfg = data; | |
3400 | ||
3401 | data |= PORT_AUTO_NEG_ENABLE; | |
3402 | data = advertised_flow_ctrl(port, data); | |
3403 | ||
3404 | data |= PORT_AUTO_NEG_100BTX_FD | PORT_AUTO_NEG_100BTX | | |
3405 | PORT_AUTO_NEG_10BT_FD | PORT_AUTO_NEG_10BT; | |
3406 | ||
3407 | /* Check if manual configuration is specified by the user. */ | |
3408 | if (port->speed || port->duplex) { | |
3409 | if (10 == port->speed) | |
3410 | data &= ~(PORT_AUTO_NEG_100BTX_FD | | |
3411 | PORT_AUTO_NEG_100BTX); | |
3412 | else if (100 == port->speed) | |
3413 | data &= ~(PORT_AUTO_NEG_10BT_FD | | |
3414 | PORT_AUTO_NEG_10BT); | |
3415 | if (1 == port->duplex) | |
3416 | data &= ~(PORT_AUTO_NEG_100BTX_FD | | |
3417 | PORT_AUTO_NEG_10BT_FD); | |
3418 | else if (2 == port->duplex) | |
3419 | data &= ~(PORT_AUTO_NEG_100BTX | | |
3420 | PORT_AUTO_NEG_10BT); | |
3421 | } | |
3422 | if (data != cfg) { | |
3423 | data |= PORT_AUTO_NEG_RESTART; | |
3424 | port_w16(hw, p, KS884X_PORT_CTRL_4_OFFSET, data); | |
3425 | } | |
3426 | } | |
3427 | } | |
3428 | ||
3429 | /** | |
3430 | * port_force_link_speed - force port speed | |
3431 | * @port: The port instance. | |
3432 | * | |
3433 | * This routine forces the link speed of the switch ports. | |
3434 | */ | |
3435 | static void port_force_link_speed(struct ksz_port *port) | |
3436 | { | |
3437 | struct ksz_hw *hw = port->hw; | |
3438 | u16 data; | |
3439 | int i; | |
3440 | int phy; | |
3441 | int p; | |
3442 | ||
3443 | for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { | |
3444 | phy = KS884X_PHY_1_CTRL_OFFSET + p * PHY_CTRL_INTERVAL; | |
3445 | hw_r_phy_ctrl(hw, phy, &data); | |
3446 | ||
3447 | data &= ~PHY_AUTO_NEG_ENABLE; | |
3448 | ||
3449 | if (10 == port->speed) | |
3450 | data &= ~PHY_SPEED_100MBIT; | |
3451 | else if (100 == port->speed) | |
3452 | data |= PHY_SPEED_100MBIT; | |
3453 | if (1 == port->duplex) | |
3454 | data &= ~PHY_FULL_DUPLEX; | |
3455 | else if (2 == port->duplex) | |
3456 | data |= PHY_FULL_DUPLEX; | |
3457 | hw_w_phy_ctrl(hw, phy, data); | |
3458 | } | |
3459 | } | |
3460 | ||
3461 | static void port_set_power_saving(struct ksz_port *port, int enable) | |
3462 | { | |
3463 | struct ksz_hw *hw = port->hw; | |
3464 | int i; | |
3465 | int p; | |
3466 | ||
3467 | for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) | |
3468 | port_cfg(hw, p, | |
3469 | KS884X_PORT_CTRL_4_OFFSET, PORT_POWER_DOWN, enable); | |
3470 | } | |
3471 | ||
3472 | /* | |
3473 | * KSZ8841 power management functions | |
3474 | */ | |
3475 | ||
3476 | /** | |
3477 | * hw_chk_wol_pme_status - check PMEN pin | |
3478 | * @hw: The hardware instance. | |
3479 | * | |
3480 | * This function is used to check PMEN pin is asserted. | |
3481 | * | |
3482 | * Return 1 if PMEN pin is asserted; otherwise, 0. | |
3483 | */ | |
3484 | static int hw_chk_wol_pme_status(struct ksz_hw *hw) | |
3485 | { | |
3486 | struct dev_info *hw_priv = container_of(hw, struct dev_info, hw); | |
3487 | struct pci_dev *pdev = hw_priv->pdev; | |
3488 | u16 data; | |
3489 | ||
3490 | if (!pdev->pm_cap) | |
3491 | return 0; | |
3492 | pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data); | |
3493 | return (data & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS; | |
3494 | } | |
3495 | ||
3496 | /** | |
3497 | * hw_clr_wol_pme_status - clear PMEN pin | |
3498 | * @hw: The hardware instance. | |
3499 | * | |
3500 | * This routine is used to clear PME_Status to deassert PMEN pin. | |
3501 | */ | |
3502 | static void hw_clr_wol_pme_status(struct ksz_hw *hw) | |
3503 | { | |
3504 | struct dev_info *hw_priv = container_of(hw, struct dev_info, hw); | |
3505 | struct pci_dev *pdev = hw_priv->pdev; | |
3506 | u16 data; | |
3507 | ||
3508 | if (!pdev->pm_cap) | |
3509 | return; | |
3510 | ||
3511 | /* Clear PME_Status to deassert PMEN pin. */ | |
3512 | pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data); | |
3513 | data |= PCI_PM_CTRL_PME_STATUS; | |
3514 | pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data); | |
3515 | } | |
3516 | ||
3517 | /** | |
3518 | * hw_cfg_wol_pme - enable or disable Wake-on-LAN | |
3519 | * @hw: The hardware instance. | |
3520 | * @set: The flag indicating whether to enable or disable. | |
3521 | * | |
3522 | * This routine is used to enable or disable Wake-on-LAN. | |
3523 | */ | |
3524 | static void hw_cfg_wol_pme(struct ksz_hw *hw, int set) | |
3525 | { | |
3526 | struct dev_info *hw_priv = container_of(hw, struct dev_info, hw); | |
3527 | struct pci_dev *pdev = hw_priv->pdev; | |
3528 | u16 data; | |
3529 | ||
3530 | if (!pdev->pm_cap) | |
3531 | return; | |
3532 | pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data); | |
3533 | data &= ~PCI_PM_CTRL_STATE_MASK; | |
3534 | if (set) | |
3535 | data |= PCI_PM_CTRL_PME_ENABLE | PCI_D3hot; | |
3536 | else | |
3537 | data &= ~PCI_PM_CTRL_PME_ENABLE; | |
3538 | pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data); | |
3539 | } | |
3540 | ||
3541 | /** | |
3542 | * hw_cfg_wol - configure Wake-on-LAN features | |
3543 | * @hw: The hardware instance. | |
3544 | * @frame: The pattern frame bit. | |
3545 | * @set: The flag indicating whether to enable or disable. | |
3546 | * | |
3547 | * This routine is used to enable or disable certain Wake-on-LAN features. | |
3548 | */ | |
3549 | static void hw_cfg_wol(struct ksz_hw *hw, u16 frame, int set) | |
3550 | { | |
3551 | u16 data; | |
3552 | ||
3553 | data = readw(hw->io + KS8841_WOL_CTRL_OFFSET); | |
3554 | if (set) | |
3555 | data |= frame; | |
3556 | else | |
3557 | data &= ~frame; | |
3558 | writew(data, hw->io + KS8841_WOL_CTRL_OFFSET); | |
3559 | } | |
3560 | ||
3561 | /** | |
3562 | * hw_set_wol_frame - program Wake-on-LAN pattern | |
3563 | * @hw: The hardware instance. | |
3564 | * @i: The frame index. | |
3565 | * @mask_size: The size of the mask. | |
3566 | * @mask: Mask to ignore certain bytes in the pattern. | |
3567 | * @frame_size: The size of the frame. | |
3568 | * @pattern: The frame data. | |
3569 | * | |
3570 | * This routine is used to program Wake-on-LAN pattern. | |
3571 | */ | |
3572 | static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size, | |
3573 | u8 *mask, uint frame_size, u8 *pattern) | |
3574 | { | |
3575 | int bits; | |
3576 | int from; | |
3577 | int len; | |
3578 | int to; | |
3579 | u32 crc; | |
3580 | u8 data[64]; | |
3581 | u8 val = 0; | |
3582 | ||
3583 | if (frame_size > mask_size * 8) | |
3584 | frame_size = mask_size * 8; | |
3585 | if (frame_size > 64) | |
3586 | frame_size = 64; | |
3587 | ||
3588 | i *= 0x10; | |
3589 | writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i); | |
3590 | writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i); | |
3591 | ||
3592 | bits = len = from = to = 0; | |
3593 | do { | |
3594 | if (bits) { | |
3595 | if ((val & 1)) | |
3596 | data[to++] = pattern[from]; | |
3597 | val >>= 1; | |
3598 | ++from; | |
3599 | --bits; | |
3600 | } else { | |
3601 | val = mask[len]; | |
3602 | writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i | |
3603 | + len); | |
3604 | ++len; | |
3605 | if (val) | |
3606 | bits = 8; | |
3607 | else | |
3608 | from += 8; | |
3609 | } | |
3610 | } while (from < (int) frame_size); | |
3611 | if (val) { | |
3612 | bits = mask[len - 1]; | |
3613 | val <<= (from % 8); | |
3614 | bits &= ~val; | |
3615 | writeb(bits, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i + len - | |
3616 | 1); | |
3617 | } | |
3618 | crc = ether_crc(to, data); | |
3619 | writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i); | |
3620 | } | |
3621 | ||
3622 | /** | |
3623 | * hw_add_wol_arp - add ARP pattern | |
3624 | * @hw: The hardware instance. | |
3625 | * @ip_addr: The IPv4 address assigned to the device. | |
3626 | * | |
3627 | * This routine is used to add ARP pattern for waking up the host. | |
3628 | */ | |
3629 | static void hw_add_wol_arp(struct ksz_hw *hw, u8 *ip_addr) | |
3630 | { | |
3631 | u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 }; | |
3632 | u8 pattern[42] = { | |
3633 | 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, | |
3634 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
3635 | 0x08, 0x06, | |
3636 | 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01, | |
3637 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
3638 | 0x00, 0x00, 0x00, 0x00, | |
3639 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
3640 | 0x00, 0x00, 0x00, 0x00 }; | |
3641 | ||
3642 | memcpy(&pattern[38], ip_addr, 4); | |
3643 | hw_set_wol_frame(hw, 3, 6, mask, 42, pattern); | |
3644 | } | |
3645 | ||
3646 | /** | |
3647 | * hw_add_wol_bcast - add broadcast pattern | |
3648 | * @hw: The hardware instance. | |
3649 | * | |
3650 | * This routine is used to add broadcast pattern for waking up the host. | |
3651 | */ | |
3652 | static void hw_add_wol_bcast(struct ksz_hw *hw) | |
3653 | { | |
3654 | u8 mask[] = { 0x3F }; | |
3655 | u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; | |
3656 | ||
3657 | hw_set_wol_frame(hw, 2, 1, mask, MAC_ADDR_LEN, pattern); | |
3658 | } | |
3659 | ||
3660 | /** | |
3661 | * hw_add_wol_mcast - add multicast pattern | |
3662 | * @hw: The hardware instance. | |
3663 | * | |
3664 | * This routine is used to add multicast pattern for waking up the host. | |
3665 | * | |
3666 | * It is assumed the multicast packet is the ICMPv6 neighbor solicitation used | |
3667 | * by IPv6 ping command. Note that multicast packets are filtred through the | |
3668 | * multicast hash table, so not all multicast packets can wake up the host. | |
3669 | */ | |
3670 | static void hw_add_wol_mcast(struct ksz_hw *hw) | |
3671 | { | |
3672 | u8 mask[] = { 0x3F }; | |
3673 | u8 pattern[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 }; | |
3674 | ||
3675 | memcpy(&pattern[3], &hw->override_addr[3], 3); | |
3676 | hw_set_wol_frame(hw, 1, 1, mask, 6, pattern); | |
3677 | } | |
3678 | ||
3679 | /** | |
3680 | * hw_add_wol_ucast - add unicast pattern | |
3681 | * @hw: The hardware instance. | |
3682 | * | |
3683 | * This routine is used to add unicast pattern to wakeup the host. | |
3684 | * | |
3685 | * It is assumed the unicast packet is directed to the device, as the hardware | |
3686 | * can only receive them in normal case. | |
3687 | */ | |
3688 | static void hw_add_wol_ucast(struct ksz_hw *hw) | |
3689 | { | |
3690 | u8 mask[] = { 0x3F }; | |
3691 | ||
3692 | hw_set_wol_frame(hw, 0, 1, mask, MAC_ADDR_LEN, hw->override_addr); | |
3693 | } | |
3694 | ||
3695 | /** | |
3696 | * hw_enable_wol - enable Wake-on-LAN | |
3697 | * @hw: The hardware instance. | |
3698 | * @wol_enable: The Wake-on-LAN settings. | |
3699 | * @net_addr: The IPv4 address assigned to the device. | |
3700 | * | |
3701 | * This routine is used to enable Wake-on-LAN depending on driver settings. | |
3702 | */ | |
3703 | static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, u8 *net_addr) | |
3704 | { | |
3705 | hw_cfg_wol(hw, KS8841_WOL_MAGIC_ENABLE, (wol_enable & WAKE_MAGIC)); | |
3706 | hw_cfg_wol(hw, KS8841_WOL_FRAME0_ENABLE, (wol_enable & WAKE_UCAST)); | |
3707 | hw_add_wol_ucast(hw); | |
3708 | hw_cfg_wol(hw, KS8841_WOL_FRAME1_ENABLE, (wol_enable & WAKE_MCAST)); | |
3709 | hw_add_wol_mcast(hw); | |
3710 | hw_cfg_wol(hw, KS8841_WOL_FRAME2_ENABLE, (wol_enable & WAKE_BCAST)); | |
3711 | hw_cfg_wol(hw, KS8841_WOL_FRAME3_ENABLE, (wol_enable & WAKE_ARP)); | |
3712 | hw_add_wol_arp(hw, net_addr); | |
3713 | } | |
3714 | ||
3715 | /** | |
3716 | * hw_init - check driver is correct for the hardware | |
3717 | * @hw: The hardware instance. | |
3718 | * | |
3719 | * This function checks the hardware is correct for this driver and sets the | |
3720 | * hardware up for proper initialization. | |
3721 | * | |
3722 | * Return number of ports or 0 if not right. | |
3723 | */ | |
3724 | static int hw_init(struct ksz_hw *hw) | |
3725 | { | |
3726 | int rc = 0; | |
3727 | u16 data; | |
3728 | u16 revision; | |
3729 | ||
3730 | /* Set bus speed to 125MHz. */ | |
3731 | writew(BUS_SPEED_125_MHZ, hw->io + KS884X_BUS_CTRL_OFFSET); | |
3732 | ||
3733 | /* Check KSZ884x chip ID. */ | |
3734 | data = readw(hw->io + KS884X_CHIP_ID_OFFSET); | |
3735 | ||
3736 | revision = (data & KS884X_REVISION_MASK) >> KS884X_REVISION_SHIFT; | |
3737 | data &= KS884X_CHIP_ID_MASK_41; | |
3738 | if (REG_CHIP_ID_41 == data) | |
3739 | rc = 1; | |
3740 | else if (REG_CHIP_ID_42 == data) | |
3741 | rc = 2; | |
3742 | else | |
3743 | return 0; | |
3744 | ||
3745 | /* Setup hardware features or bug workarounds. */ | |
3746 | if (revision <= 1) { | |
3747 | hw->features |= SMALL_PACKET_TX_BUG; | |
3748 | if (1 == rc) | |
3749 | hw->features |= HALF_DUPLEX_SIGNAL_BUG; | |
3750 | } | |
3751 | hw->features |= IPV6_CSUM_GEN_HACK; | |
3752 | return rc; | |
3753 | } | |
3754 | ||
3755 | /** | |
3756 | * hw_reset - reset the hardware | |
3757 | * @hw: The hardware instance. | |
3758 | * | |
3759 | * This routine resets the hardware. | |
3760 | */ | |
3761 | static void hw_reset(struct ksz_hw *hw) | |
3762 | { | |
3763 | writew(GLOBAL_SOFTWARE_RESET, hw->io + KS884X_GLOBAL_CTRL_OFFSET); | |
3764 | ||
3765 | /* Wait for device to reset. */ | |
3766 | mdelay(10); | |
3767 | ||
3768 | /* Write 0 to clear device reset. */ | |
3769 | writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET); | |
3770 | } | |
3771 | ||
3772 | /** | |
3773 | * hw_setup - setup the hardware | |
3774 | * @hw: The hardware instance. | |
3775 | * | |
3776 | * This routine setup the hardware for proper operation. | |
3777 | */ | |
3778 | static void hw_setup(struct ksz_hw *hw) | |
3779 | { | |
3780 | #if SET_DEFAULT_LED | |
3781 | u16 data; | |
3782 | ||
3783 | /* Change default LED mode. */ | |
3784 | data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET); | |
3785 | data &= ~LED_MODE; | |
3786 | data |= SET_DEFAULT_LED; | |
3787 | writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET); | |
3788 | #endif | |
3789 | ||
3790 | /* Setup transmit control. */ | |
3791 | hw->tx_cfg = (DMA_TX_PAD_ENABLE | DMA_TX_CRC_ENABLE | | |
3792 | (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_TX_ENABLE); | |
3793 | ||
3794 | /* Setup receive control. */ | |
3795 | hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST | | |
3796 | (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_RX_ENABLE); | |
3797 | hw->rx_cfg |= KS884X_DMA_RX_MULTICAST; | |
3798 | ||
3799 | /* Hardware cannot handle UDP packet in IP fragments. */ | |
3800 | hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP); | |
3801 | ||
3802 | if (hw->all_multi) | |
3803 | hw->rx_cfg |= DMA_RX_ALL_MULTICAST; | |
3804 | if (hw->promiscuous) | |
3805 | hw->rx_cfg |= DMA_RX_PROMISCUOUS; | |
3806 | } | |
3807 | ||
3808 | /** | |
3809 | * hw_setup_intr - setup interrupt mask | |
3810 | * @hw: The hardware instance. | |
3811 | * | |
3812 | * This routine setup the interrupt mask for proper operation. | |
3813 | */ | |
3814 | static void hw_setup_intr(struct ksz_hw *hw) | |
3815 | { | |
3816 | hw->intr_mask = KS884X_INT_MASK | KS884X_INT_RX_OVERRUN; | |
3817 | } | |
3818 | ||
3819 | static void ksz_check_desc_num(struct ksz_desc_info *info) | |
3820 | { | |
3821 | #define MIN_DESC_SHIFT 2 | |
3822 | ||
3823 | int alloc = info->alloc; | |
3824 | int shift; | |
3825 | ||
3826 | shift = 0; | |
3827 | while (!(alloc & 1)) { | |
3828 | shift++; | |
3829 | alloc >>= 1; | |
3830 | } | |
3831 | if (alloc != 1 || shift < MIN_DESC_SHIFT) { | |
0dc7d2b3 | 3832 | pr_alert("Hardware descriptor numbers not right!\n"); |
8ca86fd8 TH |
3833 | while (alloc) { |
3834 | shift++; | |
3835 | alloc >>= 1; | |
3836 | } | |
3837 | if (shift < MIN_DESC_SHIFT) | |
3838 | shift = MIN_DESC_SHIFT; | |
3839 | alloc = 1 << shift; | |
3840 | info->alloc = alloc; | |
3841 | } | |
3842 | info->mask = info->alloc - 1; | |
3843 | } | |
3844 | ||
3845 | static void hw_init_desc(struct ksz_desc_info *desc_info, int transmit) | |
3846 | { | |
3847 | int i; | |
3848 | u32 phys = desc_info->ring_phys; | |
3849 | struct ksz_hw_desc *desc = desc_info->ring_virt; | |
3850 | struct ksz_desc *cur = desc_info->ring; | |
3851 | struct ksz_desc *previous = NULL; | |
3852 | ||
3853 | for (i = 0; i < desc_info->alloc; i++) { | |
3854 | cur->phw = desc++; | |
3855 | phys += desc_info->size; | |
3856 | previous = cur++; | |
3857 | previous->phw->next = cpu_to_le32(phys); | |
3858 | } | |
3859 | previous->phw->next = cpu_to_le32(desc_info->ring_phys); | |
3860 | previous->sw.buf.rx.end_of_ring = 1; | |
3861 | previous->phw->buf.data = cpu_to_le32(previous->sw.buf.data); | |
3862 | ||
3863 | desc_info->avail = desc_info->alloc; | |
3864 | desc_info->last = desc_info->next = 0; | |
3865 | ||
3866 | desc_info->cur = desc_info->ring; | |
3867 | } | |
3868 | ||
3869 | /** | |
3870 | * hw_set_desc_base - set descriptor base addresses | |
3871 | * @hw: The hardware instance. | |
3872 | * @tx_addr: The transmit descriptor base. | |
3873 | * @rx_addr: The receive descriptor base. | |
3874 | * | |
3875 | * This routine programs the descriptor base addresses after reset. | |
3876 | */ | |
3877 | static void hw_set_desc_base(struct ksz_hw *hw, u32 tx_addr, u32 rx_addr) | |
3878 | { | |
3879 | /* Set base address of Tx/Rx descriptors. */ | |
3880 | writel(tx_addr, hw->io + KS_DMA_TX_ADDR); | |
3881 | writel(rx_addr, hw->io + KS_DMA_RX_ADDR); | |
3882 | } | |
3883 | ||
3884 | static void hw_reset_pkts(struct ksz_desc_info *info) | |
3885 | { | |
3886 | info->cur = info->ring; | |
3887 | info->avail = info->alloc; | |
3888 | info->last = info->next = 0; | |
3889 | } | |
3890 | ||
3891 | static inline void hw_resume_rx(struct ksz_hw *hw) | |
3892 | { | |
3893 | writel(DMA_START, hw->io + KS_DMA_RX_START); | |
3894 | } | |
3895 | ||
3896 | /** | |
3897 | * hw_start_rx - start receiving | |
3898 | * @hw: The hardware instance. | |
3899 | * | |
3900 | * This routine starts the receive function of the hardware. | |
3901 | */ | |
3902 | static void hw_start_rx(struct ksz_hw *hw) | |
3903 | { | |
3904 | writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL); | |
3905 | ||
3906 | /* Notify when the receive stops. */ | |
3907 | hw->intr_mask |= KS884X_INT_RX_STOPPED; | |
3908 | ||
3909 | writel(DMA_START, hw->io + KS_DMA_RX_START); | |
3910 | hw_ack_intr(hw, KS884X_INT_RX_STOPPED); | |
3911 | hw->rx_stop++; | |
3912 | ||
3913 | /* Variable overflows. */ | |
3914 | if (0 == hw->rx_stop) | |
3915 | hw->rx_stop = 2; | |
3916 | } | |
3917 | ||
3918 | /* | |
3919 | * hw_stop_rx - stop receiving | |
3920 | * @hw: The hardware instance. | |
3921 | * | |
3922 | * This routine stops the receive function of the hardware. | |
3923 | */ | |
3924 | static void hw_stop_rx(struct ksz_hw *hw) | |
3925 | { | |
3926 | hw->rx_stop = 0; | |
3927 | hw_turn_off_intr(hw, KS884X_INT_RX_STOPPED); | |
3928 | writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL); | |
3929 | } | |
3930 | ||
3931 | /** | |
3932 | * hw_start_tx - start transmitting | |
3933 | * @hw: The hardware instance. | |
3934 | * | |
3935 | * This routine starts the transmit function of the hardware. | |
3936 | */ | |
3937 | static void hw_start_tx(struct ksz_hw *hw) | |
3938 | { | |
3939 | writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL); | |
3940 | } | |
3941 | ||
3942 | /** | |
3943 | * hw_stop_tx - stop transmitting | |
3944 | * @hw: The hardware instance. | |
3945 | * | |
3946 | * This routine stops the transmit function of the hardware. | |
3947 | */ | |
3948 | static void hw_stop_tx(struct ksz_hw *hw) | |
3949 | { | |
3950 | writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL); | |
3951 | } | |
3952 | ||
3953 | /** | |
3954 | * hw_disable - disable hardware | |
3955 | * @hw: The hardware instance. | |
3956 | * | |
3957 | * This routine disables the hardware. | |
3958 | */ | |
3959 | static void hw_disable(struct ksz_hw *hw) | |
3960 | { | |
3961 | hw_stop_rx(hw); | |
3962 | hw_stop_tx(hw); | |
3963 | hw->enabled = 0; | |
3964 | } | |
3965 | ||
3966 | /** | |
3967 | * hw_enable - enable hardware | |
3968 | * @hw: The hardware instance. | |
3969 | * | |
3970 | * This routine enables the hardware. | |
3971 | */ | |
3972 | static void hw_enable(struct ksz_hw *hw) | |
3973 | { | |
3974 | hw_start_tx(hw); | |
3975 | hw_start_rx(hw); | |
3976 | hw->enabled = 1; | |
3977 | } | |
3978 | ||
3979 | /** | |
3980 | * hw_alloc_pkt - allocate enough descriptors for transmission | |
3981 | * @hw: The hardware instance. | |
3982 | * @length: The length of the packet. | |
3983 | * @physical: Number of descriptors required. | |
3984 | * | |
3985 | * This function allocates descriptors for transmission. | |
3986 | * | |
3987 | * Return 0 if not successful; 1 for buffer copy; or number of descriptors. | |
3988 | */ | |
3989 | static int hw_alloc_pkt(struct ksz_hw *hw, int length, int physical) | |
3990 | { | |
3991 | /* Always leave one descriptor free. */ | |
3992 | if (hw->tx_desc_info.avail <= 1) | |
3993 | return 0; | |
3994 | ||
3995 | /* Allocate a descriptor for transmission and mark it current. */ | |
3996 | get_tx_pkt(&hw->tx_desc_info, &hw->tx_desc_info.cur); | |
3997 | hw->tx_desc_info.cur->sw.buf.tx.first_seg = 1; | |
3998 | ||
3999 | /* Keep track of number of transmit descriptors used so far. */ | |
4000 | ++hw->tx_int_cnt; | |
4001 | hw->tx_size += length; | |
4002 | ||
4003 | /* Cannot hold on too much data. */ | |
4004 | if (hw->tx_size >= MAX_TX_HELD_SIZE) | |
4005 | hw->tx_int_cnt = hw->tx_int_mask + 1; | |
4006 | ||
4007 | if (physical > hw->tx_desc_info.avail) | |
4008 | return 1; | |
4009 | ||
4010 | return hw->tx_desc_info.avail; | |
4011 | } | |
4012 | ||
4013 | /** | |
4014 | * hw_send_pkt - mark packet for transmission | |
4015 | * @hw: The hardware instance. | |
4016 | * | |
4017 | * This routine marks the packet for transmission in PCI version. | |
4018 | */ | |
4019 | static void hw_send_pkt(struct ksz_hw *hw) | |
4020 | { | |
4021 | struct ksz_desc *cur = hw->tx_desc_info.cur; | |
4022 | ||
4023 | cur->sw.buf.tx.last_seg = 1; | |
4024 | ||
4025 | /* Interrupt only after specified number of descriptors used. */ | |
4026 | if (hw->tx_int_cnt > hw->tx_int_mask) { | |
4027 | cur->sw.buf.tx.intr = 1; | |
4028 | hw->tx_int_cnt = 0; | |
4029 | hw->tx_size = 0; | |
4030 | } | |
4031 | ||
4032 | /* KSZ8842 supports port directed transmission. */ | |
4033 | cur->sw.buf.tx.dest_port = hw->dst_ports; | |
4034 | ||
4035 | release_desc(cur); | |
4036 | ||
4037 | writel(0, hw->io + KS_DMA_TX_START); | |
4038 | } | |
4039 | ||
4040 | static int empty_addr(u8 *addr) | |
4041 | { | |
4042 | u32 *addr1 = (u32 *) addr; | |
4043 | u16 *addr2 = (u16 *) &addr[4]; | |
4044 | ||
4045 | return 0 == *addr1 && 0 == *addr2; | |
4046 | } | |
4047 | ||
4048 | /** | |
4049 | * hw_set_addr - set MAC address | |
4050 | * @hw: The hardware instance. | |
4051 | * | |
4052 | * This routine programs the MAC address of the hardware when the address is | |
4053 | * overrided. | |
4054 | */ | |
4055 | static void hw_set_addr(struct ksz_hw *hw) | |
4056 | { | |
4057 | int i; | |
4058 | ||
4059 | for (i = 0; i < MAC_ADDR_LEN; i++) | |
4060 | writeb(hw->override_addr[MAC_ADDR_ORDER(i)], | |
4061 | hw->io + KS884X_ADDR_0_OFFSET + i); | |
4062 | ||
4063 | sw_set_addr(hw, hw->override_addr); | |
4064 | } | |
4065 | ||
4066 | /** | |
4067 | * hw_read_addr - read MAC address | |
4068 | * @hw: The hardware instance. | |
4069 | * | |
4070 | * This routine retrieves the MAC address of the hardware. | |
4071 | */ | |
4072 | static void hw_read_addr(struct ksz_hw *hw) | |
4073 | { | |
4074 | int i; | |
4075 | ||
4076 | for (i = 0; i < MAC_ADDR_LEN; i++) | |
4077 | hw->perm_addr[MAC_ADDR_ORDER(i)] = readb(hw->io + | |
4078 | KS884X_ADDR_0_OFFSET + i); | |
4079 | ||
4080 | if (!hw->mac_override) { | |
4081 | memcpy(hw->override_addr, hw->perm_addr, MAC_ADDR_LEN); | |
4082 | if (empty_addr(hw->override_addr)) { | |
4083 | memcpy(hw->perm_addr, DEFAULT_MAC_ADDRESS, | |
4084 | MAC_ADDR_LEN); | |
4085 | memcpy(hw->override_addr, DEFAULT_MAC_ADDRESS, | |
4086 | MAC_ADDR_LEN); | |
4087 | hw->override_addr[5] += hw->id; | |
4088 | hw_set_addr(hw); | |
4089 | } | |
4090 | } | |
4091 | } | |
4092 | ||
4093 | static void hw_ena_add_addr(struct ksz_hw *hw, int index, u8 *mac_addr) | |
4094 | { | |
4095 | int i; | |
4096 | u32 mac_addr_lo; | |
4097 | u32 mac_addr_hi; | |
4098 | ||
4099 | mac_addr_hi = 0; | |
4100 | for (i = 0; i < 2; i++) { | |
4101 | mac_addr_hi <<= 8; | |
4102 | mac_addr_hi |= mac_addr[i]; | |
4103 | } | |
4104 | mac_addr_hi |= ADD_ADDR_ENABLE; | |
4105 | mac_addr_lo = 0; | |
4106 | for (i = 2; i < 6; i++) { | |
4107 | mac_addr_lo <<= 8; | |
4108 | mac_addr_lo |= mac_addr[i]; | |
4109 | } | |
4110 | index *= ADD_ADDR_INCR; | |
4111 | ||
4112 | writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO); | |
4113 | writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI); | |
4114 | } | |
4115 | ||
4116 | static void hw_set_add_addr(struct ksz_hw *hw) | |
4117 | { | |
4118 | int i; | |
4119 | ||
4120 | for (i = 0; i < ADDITIONAL_ENTRIES; i++) { | |
4121 | if (empty_addr(hw->address[i])) | |
4122 | writel(0, hw->io + ADD_ADDR_INCR * i + | |
4123 | KS_ADD_ADDR_0_HI); | |
4124 | else | |
4125 | hw_ena_add_addr(hw, i, hw->address[i]); | |
4126 | } | |
4127 | } | |
4128 | ||
4129 | static int hw_add_addr(struct ksz_hw *hw, u8 *mac_addr) | |
4130 | { | |
4131 | int i; | |
4132 | int j = ADDITIONAL_ENTRIES; | |
4133 | ||
4134 | if (!memcmp(hw->override_addr, mac_addr, MAC_ADDR_LEN)) | |
4135 | return 0; | |
4136 | for (i = 0; i < hw->addr_list_size; i++) { | |
4137 | if (!memcmp(hw->address[i], mac_addr, MAC_ADDR_LEN)) | |
4138 | return 0; | |
4139 | if (ADDITIONAL_ENTRIES == j && empty_addr(hw->address[i])) | |
4140 | j = i; | |
4141 | } | |
4142 | if (j < ADDITIONAL_ENTRIES) { | |
4143 | memcpy(hw->address[j], mac_addr, MAC_ADDR_LEN); | |
4144 | hw_ena_add_addr(hw, j, hw->address[j]); | |
4145 | return 0; | |
4146 | } | |
4147 | return -1; | |
4148 | } | |
4149 | ||
4150 | static int hw_del_addr(struct ksz_hw *hw, u8 *mac_addr) | |
4151 | { | |
4152 | int i; | |
4153 | ||
4154 | for (i = 0; i < hw->addr_list_size; i++) { | |
4155 | if (!memcmp(hw->address[i], mac_addr, MAC_ADDR_LEN)) { | |
4156 | memset(hw->address[i], 0, MAC_ADDR_LEN); | |
4157 | writel(0, hw->io + ADD_ADDR_INCR * i + | |
4158 | KS_ADD_ADDR_0_HI); | |
4159 | return 0; | |
4160 | } | |
4161 | } | |
4162 | return -1; | |
4163 | } | |
4164 | ||
4165 | /** | |
4166 | * hw_clr_multicast - clear multicast addresses | |
4167 | * @hw: The hardware instance. | |
4168 | * | |
4169 | * This routine removes all multicast addresses set in the hardware. | |
4170 | */ | |
4171 | static void hw_clr_multicast(struct ksz_hw *hw) | |
4172 | { | |
4173 | int i; | |
4174 | ||
4175 | for (i = 0; i < HW_MULTICAST_SIZE; i++) { | |
4176 | hw->multi_bits[i] = 0; | |
4177 | ||
4178 | writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i); | |
4179 | } | |
4180 | } | |
4181 | ||
4182 | /** | |
4183 | * hw_set_grp_addr - set multicast addresses | |
4184 | * @hw: The hardware instance. | |
4185 | * | |
4186 | * This routine programs multicast addresses for the hardware to accept those | |
4187 | * addresses. | |
4188 | */ | |
4189 | static void hw_set_grp_addr(struct ksz_hw *hw) | |
4190 | { | |
4191 | int i; | |
4192 | int index; | |
4193 | int position; | |
4194 | int value; | |
4195 | ||
4196 | memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE); | |
4197 | ||
4198 | for (i = 0; i < hw->multi_list_size; i++) { | |
4199 | position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f; | |
4200 | index = position >> 3; | |
4201 | value = 1 << (position & 7); | |
4202 | hw->multi_bits[index] |= (u8) value; | |
4203 | } | |
4204 | ||
4205 | for (i = 0; i < HW_MULTICAST_SIZE; i++) | |
4206 | writeb(hw->multi_bits[i], hw->io + KS884X_MULTICAST_0_OFFSET + | |
4207 | i); | |
4208 | } | |
4209 | ||
4210 | /** | |
4211 | * hw_set_multicast - enable or disable all multicast receiving | |
4212 | * @hw: The hardware instance. | |
4213 | * @multicast: To turn on or off the all multicast feature. | |
4214 | * | |
4215 | * This routine enables/disables the hardware to accept all multicast packets. | |
4216 | */ | |
4217 | static void hw_set_multicast(struct ksz_hw *hw, u8 multicast) | |
4218 | { | |
4219 | /* Stop receiving for reconfiguration. */ | |
4220 | hw_stop_rx(hw); | |
4221 | ||
4222 | if (multicast) | |
4223 | hw->rx_cfg |= DMA_RX_ALL_MULTICAST; | |
4224 | else | |
4225 | hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST; | |
4226 | ||
4227 | if (hw->enabled) | |
4228 | hw_start_rx(hw); | |
4229 | } | |
4230 | ||
4231 | /** | |
4232 | * hw_set_promiscuous - enable or disable promiscuous receiving | |
4233 | * @hw: The hardware instance. | |
4234 | * @prom: To turn on or off the promiscuous feature. | |
4235 | * | |
4236 | * This routine enables/disables the hardware to accept all packets. | |
4237 | */ | |
4238 | static void hw_set_promiscuous(struct ksz_hw *hw, u8 prom) | |
4239 | { | |
4240 | /* Stop receiving for reconfiguration. */ | |
4241 | hw_stop_rx(hw); | |
4242 | ||
4243 | if (prom) | |
4244 | hw->rx_cfg |= DMA_RX_PROMISCUOUS; | |
4245 | else | |
4246 | hw->rx_cfg &= ~DMA_RX_PROMISCUOUS; | |
4247 | ||
4248 | if (hw->enabled) | |
4249 | hw_start_rx(hw); | |
4250 | } | |
4251 | ||
4252 | /** | |
4253 | * sw_enable - enable the switch | |
4254 | * @hw: The hardware instance. | |
4255 | * @enable: The flag to enable or disable the switch | |
4256 | * | |
4257 | * This routine is used to enable/disable the switch in KSZ8842. | |
4258 | */ | |
4259 | static void sw_enable(struct ksz_hw *hw, int enable) | |
4260 | { | |
4261 | int port; | |
4262 | ||
4263 | for (port = 0; port < SWITCH_PORT_NUM; port++) { | |
4264 | if (hw->dev_count > 1) { | |
4265 | /* Set port-base vlan membership with host port. */ | |
4266 | sw_cfg_port_base_vlan(hw, port, | |
4267 | HOST_MASK | (1 << port)); | |
4268 | port_set_stp_state(hw, port, STP_STATE_DISABLED); | |
4269 | } else { | |
4270 | sw_cfg_port_base_vlan(hw, port, PORT_MASK); | |
4271 | port_set_stp_state(hw, port, STP_STATE_FORWARDING); | |
4272 | } | |
4273 | } | |
4274 | if (hw->dev_count > 1) | |
4275 | port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE); | |
4276 | else | |
4277 | port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_FORWARDING); | |
4278 | ||
4279 | if (enable) | |
4280 | enable = KS8842_START; | |
4281 | writew(enable, hw->io + KS884X_CHIP_ID_OFFSET); | |
4282 | } | |
4283 | ||
4284 | /** | |
4285 | * sw_setup - setup the switch | |
4286 | * @hw: The hardware instance. | |
4287 | * | |
4288 | * This routine setup the hardware switch engine for default operation. | |
4289 | */ | |
4290 | static void sw_setup(struct ksz_hw *hw) | |
4291 | { | |
4292 | int port; | |
4293 | ||
4294 | sw_set_global_ctrl(hw); | |
4295 | ||
4296 | /* Enable switch broadcast storm protection at 10% percent rate. */ | |
4297 | sw_init_broad_storm(hw); | |
4298 | hw_cfg_broad_storm(hw, BROADCAST_STORM_PROTECTION_RATE); | |
4299 | for (port = 0; port < SWITCH_PORT_NUM; port++) | |
4300 | sw_ena_broad_storm(hw, port); | |
4301 | ||
4302 | sw_init_prio(hw); | |
4303 | ||
4304 | sw_init_mirror(hw); | |
4305 | ||
4306 | sw_init_prio_rate(hw); | |
4307 | ||
4308 | sw_init_vlan(hw); | |
4309 | ||
4310 | if (hw->features & STP_SUPPORT) | |
4311 | sw_init_stp(hw); | |
4312 | if (!sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET, | |
4313 | SWITCH_TX_FLOW_CTRL | SWITCH_RX_FLOW_CTRL)) | |
4314 | hw->overrides |= PAUSE_FLOW_CTRL; | |
4315 | sw_enable(hw, 1); | |
4316 | } | |
4317 | ||
4318 | /** | |
4319 | * ksz_start_timer - start kernel timer | |
4320 | * @info: Kernel timer information. | |
4321 | * @time: The time tick. | |
4322 | * | |
4323 | * This routine starts the kernel timer after the specified time tick. | |
4324 | */ | |
4325 | static void ksz_start_timer(struct ksz_timer_info *info, int time) | |
4326 | { | |
4327 | info->cnt = 0; | |
4328 | info->timer.expires = jiffies + time; | |
4329 | add_timer(&info->timer); | |
4330 | ||
4331 | /* infinity */ | |
4332 | info->max = -1; | |
4333 | } | |
4334 | ||
4335 | /** | |
4336 | * ksz_stop_timer - stop kernel timer | |
4337 | * @info: Kernel timer information. | |
4338 | * | |
4339 | * This routine stops the kernel timer. | |
4340 | */ | |
4341 | static void ksz_stop_timer(struct ksz_timer_info *info) | |
4342 | { | |
4343 | if (info->max) { | |
4344 | info->max = 0; | |
4345 | del_timer_sync(&info->timer); | |
4346 | } | |
4347 | } | |
4348 | ||
4349 | static void ksz_init_timer(struct ksz_timer_info *info, int period, | |
4350 | void (*function)(unsigned long), void *data) | |
4351 | { | |
4352 | info->max = 0; | |
4353 | info->period = period; | |
4354 | init_timer(&info->timer); | |
4355 | info->timer.function = function; | |
4356 | info->timer.data = (unsigned long) data; | |
4357 | } | |
4358 | ||
4359 | static void ksz_update_timer(struct ksz_timer_info *info) | |
4360 | { | |
4361 | ++info->cnt; | |
4362 | if (info->max > 0) { | |
4363 | if (info->cnt < info->max) { | |
4364 | info->timer.expires = jiffies + info->period; | |
4365 | add_timer(&info->timer); | |
4366 | } else | |
4367 | info->max = 0; | |
4368 | } else if (info->max < 0) { | |
4369 | info->timer.expires = jiffies + info->period; | |
4370 | add_timer(&info->timer); | |
4371 | } | |
4372 | } | |
4373 | ||
4374 | /** | |
4375 | * ksz_alloc_soft_desc - allocate software descriptors | |
4376 | * @desc_info: Descriptor information structure. | |
4377 | * @transmit: Indication that descriptors are for transmit. | |
4378 | * | |
4379 | * This local function allocates software descriptors for manipulation in | |
4380 | * memory. | |
4381 | * | |
4382 | * Return 0 if successful. | |
4383 | */ | |
4384 | static int ksz_alloc_soft_desc(struct ksz_desc_info *desc_info, int transmit) | |
4385 | { | |
4386 | desc_info->ring = kmalloc(sizeof(struct ksz_desc) * desc_info->alloc, | |
4387 | GFP_KERNEL); | |
4388 | if (!desc_info->ring) | |
4389 | return 1; | |
4390 | memset((void *) desc_info->ring, 0, | |
4391 | sizeof(struct ksz_desc) * desc_info->alloc); | |
4392 | hw_init_desc(desc_info, transmit); | |
4393 | return 0; | |
4394 | } | |
4395 | ||
4396 | /** | |
4397 | * ksz_alloc_desc - allocate hardware descriptors | |
4398 | * @adapter: Adapter information structure. | |
4399 | * | |
4400 | * This local function allocates hardware descriptors for receiving and | |
4401 | * transmitting. | |
4402 | * | |
4403 | * Return 0 if successful. | |
4404 | */ | |
4405 | static int ksz_alloc_desc(struct dev_info *adapter) | |
4406 | { | |
4407 | struct ksz_hw *hw = &adapter->hw; | |
4408 | int offset; | |
4409 | ||
4410 | /* Allocate memory for RX & TX descriptors. */ | |
4411 | adapter->desc_pool.alloc_size = | |
4412 | hw->rx_desc_info.size * hw->rx_desc_info.alloc + | |
4413 | hw->tx_desc_info.size * hw->tx_desc_info.alloc + | |
4414 | DESC_ALIGNMENT; | |
4415 | ||
4416 | adapter->desc_pool.alloc_virt = | |
4417 | pci_alloc_consistent( | |
4418 | adapter->pdev, adapter->desc_pool.alloc_size, | |
4419 | &adapter->desc_pool.dma_addr); | |
4420 | if (adapter->desc_pool.alloc_virt == NULL) { | |
4421 | adapter->desc_pool.alloc_size = 0; | |
4422 | return 1; | |
4423 | } | |
4424 | memset(adapter->desc_pool.alloc_virt, 0, adapter->desc_pool.alloc_size); | |
4425 | ||
4426 | /* Align to the next cache line boundary. */ | |
4427 | offset = (((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT) ? | |
4428 | (DESC_ALIGNMENT - | |
4429 | ((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT)) : 0); | |
4430 | adapter->desc_pool.virt = adapter->desc_pool.alloc_virt + offset; | |
4431 | adapter->desc_pool.phys = adapter->desc_pool.dma_addr + offset; | |
4432 | ||
4433 | /* Allocate receive/transmit descriptors. */ | |
4434 | hw->rx_desc_info.ring_virt = (struct ksz_hw_desc *) | |
4435 | adapter->desc_pool.virt; | |
4436 | hw->rx_desc_info.ring_phys = adapter->desc_pool.phys; | |
4437 | offset = hw->rx_desc_info.alloc * hw->rx_desc_info.size; | |
4438 | hw->tx_desc_info.ring_virt = (struct ksz_hw_desc *) | |
4439 | (adapter->desc_pool.virt + offset); | |
4440 | hw->tx_desc_info.ring_phys = adapter->desc_pool.phys + offset; | |
4441 | ||
4442 | if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0)) | |
4443 | return 1; | |
4444 | if (ksz_alloc_soft_desc(&hw->tx_desc_info, 1)) | |
4445 | return 1; | |
4446 | ||
4447 | return 0; | |
4448 | } | |
4449 | ||
4450 | /** | |
4451 | * free_dma_buf - release DMA buffer resources | |
4452 | * @adapter: Adapter information structure. | |
4453 | * | |
4454 | * This routine is just a helper function to release the DMA buffer resources. | |
4455 | */ | |
4456 | static void free_dma_buf(struct dev_info *adapter, struct ksz_dma_buf *dma_buf, | |
4457 | int direction) | |
4458 | { | |
4459 | pci_unmap_single(adapter->pdev, dma_buf->dma, dma_buf->len, direction); | |
4460 | dev_kfree_skb(dma_buf->skb); | |
4461 | dma_buf->skb = NULL; | |
4462 | dma_buf->dma = 0; | |
4463 | } | |
4464 | ||
4465 | /** | |
4466 | * ksz_init_rx_buffers - initialize receive descriptors | |
4467 | * @adapter: Adapter information structure. | |
4468 | * | |
4469 | * This routine initializes DMA buffers for receiving. | |
4470 | */ | |
4471 | static void ksz_init_rx_buffers(struct dev_info *adapter) | |
4472 | { | |
4473 | int i; | |
4474 | struct ksz_desc *desc; | |
4475 | struct ksz_dma_buf *dma_buf; | |
4476 | struct ksz_hw *hw = &adapter->hw; | |
4477 | struct ksz_desc_info *info = &hw->rx_desc_info; | |
4478 | ||
4479 | for (i = 0; i < hw->rx_desc_info.alloc; i++) { | |
4480 | get_rx_pkt(info, &desc); | |
4481 | ||
4482 | dma_buf = DMA_BUFFER(desc); | |
4483 | if (dma_buf->skb && dma_buf->len != adapter->mtu) | |
4484 | free_dma_buf(adapter, dma_buf, PCI_DMA_FROMDEVICE); | |
4485 | dma_buf->len = adapter->mtu; | |
4486 | if (!dma_buf->skb) | |
4487 | dma_buf->skb = alloc_skb(dma_buf->len, GFP_ATOMIC); | |
4488 | if (dma_buf->skb && !dma_buf->dma) { | |
4489 | dma_buf->skb->dev = adapter->dev; | |
4490 | dma_buf->dma = pci_map_single( | |
4491 | adapter->pdev, | |
4492 | skb_tail_pointer(dma_buf->skb), | |
4493 | dma_buf->len, | |
4494 | PCI_DMA_FROMDEVICE); | |
4495 | } | |
4496 | ||
4497 | /* Set descriptor. */ | |
4498 | set_rx_buf(desc, dma_buf->dma); | |
4499 | set_rx_len(desc, dma_buf->len); | |
4500 | release_desc(desc); | |
4501 | } | |
4502 | } | |
4503 | ||
4504 | /** | |
4505 | * ksz_alloc_mem - allocate memory for hardware descriptors | |
4506 | * @adapter: Adapter information structure. | |
4507 | * | |
4508 | * This function allocates memory for use by hardware descriptors for receiving | |
4509 | * and transmitting. | |
4510 | * | |
4511 | * Return 0 if successful. | |
4512 | */ | |
4513 | static int ksz_alloc_mem(struct dev_info *adapter) | |
4514 | { | |
4515 | struct ksz_hw *hw = &adapter->hw; | |
4516 | ||
4517 | /* Determine the number of receive and transmit descriptors. */ | |
4518 | hw->rx_desc_info.alloc = NUM_OF_RX_DESC; | |
4519 | hw->tx_desc_info.alloc = NUM_OF_TX_DESC; | |
4520 | ||
4521 | /* Determine how many descriptors to skip transmit interrupt. */ | |
4522 | hw->tx_int_cnt = 0; | |
4523 | hw->tx_int_mask = NUM_OF_TX_DESC / 4; | |
4524 | if (hw->tx_int_mask > 8) | |
4525 | hw->tx_int_mask = 8; | |
4526 | while (hw->tx_int_mask) { | |
4527 | hw->tx_int_cnt++; | |
4528 | hw->tx_int_mask >>= 1; | |
4529 | } | |
4530 | if (hw->tx_int_cnt) { | |
4531 | hw->tx_int_mask = (1 << (hw->tx_int_cnt - 1)) - 1; | |
4532 | hw->tx_int_cnt = 0; | |
4533 | } | |
4534 | ||
4535 | /* Determine the descriptor size. */ | |
4536 | hw->rx_desc_info.size = | |
4537 | (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) / | |
4538 | DESC_ALIGNMENT) * DESC_ALIGNMENT); | |
4539 | hw->tx_desc_info.size = | |
4540 | (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) / | |
4541 | DESC_ALIGNMENT) * DESC_ALIGNMENT); | |
4542 | if (hw->rx_desc_info.size != sizeof(struct ksz_hw_desc)) | |
0dc7d2b3 | 4543 | pr_alert("Hardware descriptor size not right!\n"); |
8ca86fd8 TH |
4544 | ksz_check_desc_num(&hw->rx_desc_info); |
4545 | ksz_check_desc_num(&hw->tx_desc_info); | |
4546 | ||
4547 | /* Allocate descriptors. */ | |
4548 | if (ksz_alloc_desc(adapter)) | |
4549 | return 1; | |
4550 | ||
4551 | return 0; | |
4552 | } | |
4553 | ||
4554 | /** | |
4555 | * ksz_free_desc - free software and hardware descriptors | |
4556 | * @adapter: Adapter information structure. | |
4557 | * | |
4558 | * This local routine frees the software and hardware descriptors allocated by | |
4559 | * ksz_alloc_desc(). | |
4560 | */ | |
4561 | static void ksz_free_desc(struct dev_info *adapter) | |
4562 | { | |
4563 | struct ksz_hw *hw = &adapter->hw; | |
4564 | ||
4565 | /* Reset descriptor. */ | |
4566 | hw->rx_desc_info.ring_virt = NULL; | |
4567 | hw->tx_desc_info.ring_virt = NULL; | |
4568 | hw->rx_desc_info.ring_phys = 0; | |
4569 | hw->tx_desc_info.ring_phys = 0; | |
4570 | ||
4571 | /* Free memory. */ | |
4572 | if (adapter->desc_pool.alloc_virt) | |
4573 | pci_free_consistent( | |
4574 | adapter->pdev, | |
4575 | adapter->desc_pool.alloc_size, | |
4576 | adapter->desc_pool.alloc_virt, | |
4577 | adapter->desc_pool.dma_addr); | |
4578 | ||
4579 | /* Reset resource pool. */ | |
4580 | adapter->desc_pool.alloc_size = 0; | |
4581 | adapter->desc_pool.alloc_virt = NULL; | |
4582 | ||
4583 | kfree(hw->rx_desc_info.ring); | |
4584 | hw->rx_desc_info.ring = NULL; | |
4585 | kfree(hw->tx_desc_info.ring); | |
4586 | hw->tx_desc_info.ring = NULL; | |
4587 | } | |
4588 | ||
4589 | /** | |
4590 | * ksz_free_buffers - free buffers used in the descriptors | |
4591 | * @adapter: Adapter information structure. | |
4592 | * @desc_info: Descriptor information structure. | |
4593 | * | |
4594 | * This local routine frees buffers used in the DMA buffers. | |
4595 | */ | |
4596 | static void ksz_free_buffers(struct dev_info *adapter, | |
4597 | struct ksz_desc_info *desc_info, int direction) | |
4598 | { | |
4599 | int i; | |
4600 | struct ksz_dma_buf *dma_buf; | |
4601 | struct ksz_desc *desc = desc_info->ring; | |
4602 | ||
4603 | for (i = 0; i < desc_info->alloc; i++) { | |
4604 | dma_buf = DMA_BUFFER(desc); | |
4605 | if (dma_buf->skb) | |
4606 | free_dma_buf(adapter, dma_buf, direction); | |
4607 | desc++; | |
4608 | } | |
4609 | } | |
4610 | ||
4611 | /** | |
4612 | * ksz_free_mem - free all resources used by descriptors | |
4613 | * @adapter: Adapter information structure. | |
4614 | * | |
4615 | * This local routine frees all the resources allocated by ksz_alloc_mem(). | |
4616 | */ | |
4617 | static void ksz_free_mem(struct dev_info *adapter) | |
4618 | { | |
4619 | /* Free transmit buffers. */ | |
4620 | ksz_free_buffers(adapter, &adapter->hw.tx_desc_info, | |
4621 | PCI_DMA_TODEVICE); | |
4622 | ||
4623 | /* Free receive buffers. */ | |
4624 | ksz_free_buffers(adapter, &adapter->hw.rx_desc_info, | |
4625 | PCI_DMA_FROMDEVICE); | |
4626 | ||
4627 | /* Free descriptors. */ | |
4628 | ksz_free_desc(adapter); | |
4629 | } | |
4630 | ||
4631 | static void get_mib_counters(struct ksz_hw *hw, int first, int cnt, | |
4632 | u64 *counter) | |
4633 | { | |
4634 | int i; | |
4635 | int mib; | |
4636 | int port; | |
4637 | struct ksz_port_mib *port_mib; | |
4638 | ||
4639 | memset(counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM); | |
4640 | for (i = 0, port = first; i < cnt; i++, port++) { | |
4641 | port_mib = &hw->port_mib[port]; | |
4642 | for (mib = port_mib->mib_start; mib < hw->mib_cnt; mib++) | |
4643 | counter[mib] += port_mib->counter[mib]; | |
4644 | } | |
4645 | } | |
4646 | ||
4647 | /** | |
4648 | * send_packet - send packet | |
4649 | * @skb: Socket buffer. | |
4650 | * @dev: Network device. | |
4651 | * | |
4652 | * This routine is used to send a packet out to the network. | |
4653 | */ | |
4654 | static void send_packet(struct sk_buff *skb, struct net_device *dev) | |
4655 | { | |
4656 | struct ksz_desc *desc; | |
4657 | struct ksz_desc *first; | |
4658 | struct dev_priv *priv = netdev_priv(dev); | |
4659 | struct dev_info *hw_priv = priv->adapter; | |
4660 | struct ksz_hw *hw = &hw_priv->hw; | |
4661 | struct ksz_desc_info *info = &hw->tx_desc_info; | |
4662 | struct ksz_dma_buf *dma_buf; | |
4663 | int len; | |
4664 | int last_frag = skb_shinfo(skb)->nr_frags; | |
4665 | ||
4666 | /* | |
4667 | * KSZ8842 with multiple device interfaces needs to be told which port | |
4668 | * to send. | |
4669 | */ | |
4670 | if (hw->dev_count > 1) | |
4671 | hw->dst_ports = 1 << priv->port.first_port; | |
4672 | ||
4673 | /* Hardware will pad the length to 60. */ | |
4674 | len = skb->len; | |
4675 | ||
4676 | /* Remember the very first descriptor. */ | |
4677 | first = info->cur; | |
4678 | desc = first; | |
4679 | ||
4680 | dma_buf = DMA_BUFFER(desc); | |
4681 | if (last_frag) { | |
4682 | int frag; | |
4683 | skb_frag_t *this_frag; | |
4684 | ||
e743d313 | 4685 | dma_buf->len = skb_headlen(skb); |
8ca86fd8 TH |
4686 | |
4687 | dma_buf->dma = pci_map_single( | |
4688 | hw_priv->pdev, skb->data, dma_buf->len, | |
4689 | PCI_DMA_TODEVICE); | |
4690 | set_tx_buf(desc, dma_buf->dma); | |
4691 | set_tx_len(desc, dma_buf->len); | |
4692 | ||
4693 | frag = 0; | |
4694 | do { | |
4695 | this_frag = &skb_shinfo(skb)->frags[frag]; | |
4696 | ||
4697 | /* Get a new descriptor. */ | |
4698 | get_tx_pkt(info, &desc); | |
4699 | ||
4700 | /* Keep track of descriptors used so far. */ | |
4701 | ++hw->tx_int_cnt; | |
4702 | ||
4703 | dma_buf = DMA_BUFFER(desc); | |
4704 | dma_buf->len = this_frag->size; | |
4705 | ||
4706 | dma_buf->dma = pci_map_single( | |
4707 | hw_priv->pdev, | |
4708 | page_address(this_frag->page) + | |
4709 | this_frag->page_offset, | |
4710 | dma_buf->len, | |
4711 | PCI_DMA_TODEVICE); | |
4712 | set_tx_buf(desc, dma_buf->dma); | |
4713 | set_tx_len(desc, dma_buf->len); | |
4714 | ||
4715 | frag++; | |
4716 | if (frag == last_frag) | |
4717 | break; | |
4718 | ||
4719 | /* Do not release the last descriptor here. */ | |
4720 | release_desc(desc); | |
4721 | } while (1); | |
4722 | ||
4723 | /* current points to the last descriptor. */ | |
4724 | info->cur = desc; | |
4725 | ||
4726 | /* Release the first descriptor. */ | |
4727 | release_desc(first); | |
4728 | } else { | |
4729 | dma_buf->len = len; | |
4730 | ||
4731 | dma_buf->dma = pci_map_single( | |
4732 | hw_priv->pdev, skb->data, dma_buf->len, | |
4733 | PCI_DMA_TODEVICE); | |
4734 | set_tx_buf(desc, dma_buf->dma); | |
4735 | set_tx_len(desc, dma_buf->len); | |
4736 | } | |
4737 | ||
4738 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
4739 | (desc)->sw.buf.tx.csum_gen_tcp = 1; | |
4740 | (desc)->sw.buf.tx.csum_gen_udp = 1; | |
4741 | } | |
4742 | ||
4743 | /* | |
4744 | * The last descriptor holds the packet so that it can be returned to | |
4745 | * network subsystem after all descriptors are transmitted. | |
4746 | */ | |
4747 | dma_buf->skb = skb; | |
4748 | ||
4749 | hw_send_pkt(hw); | |
4750 | ||
4751 | /* Update transmit statistics. */ | |
897dd41d KV |
4752 | dev->stats.tx_packets++; |
4753 | dev->stats.tx_bytes += len; | |
8ca86fd8 TH |
4754 | } |
4755 | ||
4756 | /** | |
4757 | * transmit_cleanup - clean up transmit descriptors | |
4758 | * @dev: Network device. | |
4759 | * | |
4760 | * This routine is called to clean up the transmitted buffers. | |
4761 | */ | |
4762 | static void transmit_cleanup(struct dev_info *hw_priv, int normal) | |
4763 | { | |
4764 | int last; | |
4765 | union desc_stat status; | |
4766 | struct ksz_hw *hw = &hw_priv->hw; | |
4767 | struct ksz_desc_info *info = &hw->tx_desc_info; | |
4768 | struct ksz_desc *desc; | |
4769 | struct ksz_dma_buf *dma_buf; | |
4770 | struct net_device *dev = NULL; | |
4771 | ||
4772 | spin_lock(&hw_priv->hwlock); | |
4773 | last = info->last; | |
4774 | ||
4775 | while (info->avail < info->alloc) { | |
4776 | /* Get next descriptor which is not hardware owned. */ | |
4777 | desc = &info->ring[last]; | |
4778 | status.data = le32_to_cpu(desc->phw->ctrl.data); | |
4779 | if (status.tx.hw_owned) { | |
4780 | if (normal) | |
4781 | break; | |
4782 | else | |
4783 | reset_desc(desc, status); | |
4784 | } | |
4785 | ||
4786 | dma_buf = DMA_BUFFER(desc); | |
4787 | pci_unmap_single( | |
4788 | hw_priv->pdev, dma_buf->dma, dma_buf->len, | |
4789 | PCI_DMA_TODEVICE); | |
4790 | ||
4791 | /* This descriptor contains the last buffer in the packet. */ | |
4792 | if (dma_buf->skb) { | |
4793 | dev = dma_buf->skb->dev; | |
4794 | ||
4795 | /* Release the packet back to network subsystem. */ | |
4796 | dev_kfree_skb_irq(dma_buf->skb); | |
4797 | dma_buf->skb = NULL; | |
4798 | } | |
4799 | ||
4800 | /* Free the transmitted descriptor. */ | |
4801 | last++; | |
4802 | last &= info->mask; | |
4803 | info->avail++; | |
4804 | } | |
4805 | info->last = last; | |
4806 | spin_unlock(&hw_priv->hwlock); | |
4807 | ||
4808 | /* Notify the network subsystem that the packet has been sent. */ | |
4809 | if (dev) | |
4810 | dev->trans_start = jiffies; | |
4811 | } | |
4812 | ||
4813 | /** | |
4814 | * transmit_done - transmit done processing | |
4815 | * @dev: Network device. | |
4816 | * | |
4817 | * This routine is called when the transmit interrupt is triggered, indicating | |
4818 | * either a packet is sent successfully or there are transmit errors. | |
4819 | */ | |
4820 | static void tx_done(struct dev_info *hw_priv) | |
4821 | { | |
4822 | struct ksz_hw *hw = &hw_priv->hw; | |
4823 | int port; | |
4824 | ||
4825 | transmit_cleanup(hw_priv, 1); | |
4826 | ||
4827 | for (port = 0; port < hw->dev_count; port++) { | |
4828 | struct net_device *dev = hw->port_info[port].pdev; | |
4829 | ||
4830 | if (netif_running(dev) && netif_queue_stopped(dev)) | |
4831 | netif_wake_queue(dev); | |
4832 | } | |
4833 | } | |
4834 | ||
4835 | static inline void copy_old_skb(struct sk_buff *old, struct sk_buff *skb) | |
4836 | { | |
4837 | skb->dev = old->dev; | |
4838 | skb->protocol = old->protocol; | |
4839 | skb->ip_summed = old->ip_summed; | |
4840 | skb->csum = old->csum; | |
4841 | skb_set_network_header(skb, ETH_HLEN); | |
4842 | ||
4843 | dev_kfree_skb(old); | |
4844 | } | |
4845 | ||
4846 | /** | |
4847 | * netdev_tx - send out packet | |
4848 | * @skb: Socket buffer. | |
4849 | * @dev: Network device. | |
4850 | * | |
4851 | * This function is used by the upper network layer to send out a packet. | |
4852 | * | |
4853 | * Return 0 if successful; otherwise an error code indicating failure. | |
4854 | */ | |
5ed83663 | 4855 | static netdev_tx_t netdev_tx(struct sk_buff *skb, struct net_device *dev) |
8ca86fd8 TH |
4856 | { |
4857 | struct dev_priv *priv = netdev_priv(dev); | |
4858 | struct dev_info *hw_priv = priv->adapter; | |
4859 | struct ksz_hw *hw = &hw_priv->hw; | |
4860 | int left; | |
4861 | int num = 1; | |
4862 | int rc = 0; | |
4863 | ||
4864 | if (hw->features & SMALL_PACKET_TX_BUG) { | |
4865 | struct sk_buff *org_skb = skb; | |
4866 | ||
4867 | if (skb->len <= 48) { | |
4868 | if (skb_end_pointer(skb) - skb->data >= 50) { | |
4869 | memset(&skb->data[skb->len], 0, 50 - skb->len); | |
4870 | skb->len = 50; | |
4871 | } else { | |
4872 | skb = dev_alloc_skb(50); | |
4873 | if (!skb) | |
4874 | return NETDEV_TX_BUSY; | |
4875 | memcpy(skb->data, org_skb->data, org_skb->len); | |
4876 | memset(&skb->data[org_skb->len], 0, | |
4877 | 50 - org_skb->len); | |
4878 | skb->len = 50; | |
4879 | copy_old_skb(org_skb, skb); | |
4880 | } | |
4881 | } | |
4882 | } | |
4883 | ||
4884 | spin_lock_irq(&hw_priv->hwlock); | |
4885 | ||
4886 | num = skb_shinfo(skb)->nr_frags + 1; | |
4887 | left = hw_alloc_pkt(hw, skb->len, num); | |
4888 | if (left) { | |
4889 | if (left < num || | |
4890 | ((hw->features & IPV6_CSUM_GEN_HACK) && | |
4891 | (CHECKSUM_PARTIAL == skb->ip_summed) && | |
4892 | (ETH_P_IPV6 == htons(skb->protocol)))) { | |
4893 | struct sk_buff *org_skb = skb; | |
4894 | ||
4895 | skb = dev_alloc_skb(org_skb->len); | |
edee3932 JS |
4896 | if (!skb) { |
4897 | rc = NETDEV_TX_BUSY; | |
4898 | goto unlock; | |
4899 | } | |
8ca86fd8 TH |
4900 | skb_copy_and_csum_dev(org_skb, skb->data); |
4901 | org_skb->ip_summed = 0; | |
4902 | skb->len = org_skb->len; | |
4903 | copy_old_skb(org_skb, skb); | |
4904 | } | |
4905 | send_packet(skb, dev); | |
4906 | if (left <= num) | |
4907 | netif_stop_queue(dev); | |
4908 | } else { | |
4909 | /* Stop the transmit queue until packet is allocated. */ | |
4910 | netif_stop_queue(dev); | |
4911 | rc = NETDEV_TX_BUSY; | |
4912 | } | |
edee3932 | 4913 | unlock: |
8ca86fd8 TH |
4914 | spin_unlock_irq(&hw_priv->hwlock); |
4915 | ||
4916 | return rc; | |
4917 | } | |
4918 | ||
4919 | /** | |
4920 | * netdev_tx_timeout - transmit timeout processing | |
4921 | * @dev: Network device. | |
4922 | * | |
4923 | * This routine is called when the transmit timer expires. That indicates the | |
4924 | * hardware is not running correctly because transmit interrupts are not | |
4925 | * triggered to free up resources so that the transmit routine can continue | |
4926 | * sending out packets. The hardware is reset to correct the problem. | |
4927 | */ | |
4928 | static void netdev_tx_timeout(struct net_device *dev) | |
4929 | { | |
4930 | static unsigned long last_reset; | |
4931 | ||
4932 | struct dev_priv *priv = netdev_priv(dev); | |
4933 | struct dev_info *hw_priv = priv->adapter; | |
4934 | struct ksz_hw *hw = &hw_priv->hw; | |
4935 | int port; | |
4936 | ||
4937 | if (hw->dev_count > 1) { | |
4938 | /* | |
4939 | * Only reset the hardware if time between calls is long | |
4940 | * enough. | |
4941 | */ | |
4942 | if (jiffies - last_reset <= dev->watchdog_timeo) | |
4943 | hw_priv = NULL; | |
4944 | } | |
4945 | ||
4946 | last_reset = jiffies; | |
4947 | if (hw_priv) { | |
4948 | hw_dis_intr(hw); | |
4949 | hw_disable(hw); | |
4950 | ||
4951 | transmit_cleanup(hw_priv, 0); | |
4952 | hw_reset_pkts(&hw->rx_desc_info); | |
4953 | hw_reset_pkts(&hw->tx_desc_info); | |
4954 | ksz_init_rx_buffers(hw_priv); | |
4955 | ||
4956 | hw_reset(hw); | |
4957 | ||
4958 | hw_set_desc_base(hw, | |
4959 | hw->tx_desc_info.ring_phys, | |
4960 | hw->rx_desc_info.ring_phys); | |
4961 | hw_set_addr(hw); | |
4962 | if (hw->all_multi) | |
4963 | hw_set_multicast(hw, hw->all_multi); | |
4964 | else if (hw->multi_list_size) | |
4965 | hw_set_grp_addr(hw); | |
4966 | ||
4967 | if (hw->dev_count > 1) { | |
4968 | hw_set_add_addr(hw); | |
4969 | for (port = 0; port < SWITCH_PORT_NUM; port++) { | |
4970 | struct net_device *port_dev; | |
4971 | ||
4972 | port_set_stp_state(hw, port, | |
4973 | STP_STATE_DISABLED); | |
4974 | ||
4975 | port_dev = hw->port_info[port].pdev; | |
4976 | if (netif_running(port_dev)) | |
4977 | port_set_stp_state(hw, port, | |
4978 | STP_STATE_SIMPLE); | |
4979 | } | |
4980 | } | |
4981 | ||
4982 | hw_enable(hw); | |
4983 | hw_ena_intr(hw); | |
4984 | } | |
4985 | ||
4986 | dev->trans_start = jiffies; | |
4987 | netif_wake_queue(dev); | |
4988 | } | |
4989 | ||
4990 | static inline void csum_verified(struct sk_buff *skb) | |
4991 | { | |
4992 | unsigned short protocol; | |
4993 | struct iphdr *iph; | |
4994 | ||
4995 | protocol = skb->protocol; | |
4996 | skb_reset_network_header(skb); | |
4997 | iph = (struct iphdr *) skb_network_header(skb); | |
4998 | if (protocol == htons(ETH_P_8021Q)) { | |
4999 | protocol = iph->tot_len; | |
5000 | skb_set_network_header(skb, VLAN_HLEN); | |
5001 | iph = (struct iphdr *) skb_network_header(skb); | |
5002 | } | |
5003 | if (protocol == htons(ETH_P_IP)) { | |
5004 | if (iph->protocol == IPPROTO_TCP) | |
5005 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
5006 | } | |
5007 | } | |
5008 | ||
5009 | static inline int rx_proc(struct net_device *dev, struct ksz_hw* hw, | |
5010 | struct ksz_desc *desc, union desc_stat status) | |
5011 | { | |
5012 | int packet_len; | |
5013 | struct dev_priv *priv = netdev_priv(dev); | |
5014 | struct dev_info *hw_priv = priv->adapter; | |
5015 | struct ksz_dma_buf *dma_buf; | |
5016 | struct sk_buff *skb; | |
5017 | int rx_status; | |
5018 | ||
5019 | /* Received length includes 4-byte CRC. */ | |
5020 | packet_len = status.rx.frame_len - 4; | |
5021 | ||
5022 | dma_buf = DMA_BUFFER(desc); | |
5023 | pci_dma_sync_single_for_cpu( | |
5024 | hw_priv->pdev, dma_buf->dma, packet_len + 4, | |
5025 | PCI_DMA_FROMDEVICE); | |
5026 | ||
5027 | do { | |
5028 | /* skb->data != skb->head */ | |
5029 | skb = dev_alloc_skb(packet_len + 2); | |
5030 | if (!skb) { | |
897dd41d | 5031 | dev->stats.rx_dropped++; |
8ca86fd8 TH |
5032 | return -ENOMEM; |
5033 | } | |
5034 | ||
5035 | /* | |
5036 | * Align socket buffer in 4-byte boundary for better | |
5037 | * performance. | |
5038 | */ | |
5039 | skb_reserve(skb, 2); | |
5040 | ||
5041 | memcpy(skb_put(skb, packet_len), | |
5042 | dma_buf->skb->data, packet_len); | |
5043 | } while (0); | |
5044 | ||
8ca86fd8 TH |
5045 | skb->protocol = eth_type_trans(skb, dev); |
5046 | ||
5047 | if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP)) | |
5048 | csum_verified(skb); | |
5049 | ||
5050 | /* Update receive statistics. */ | |
897dd41d KV |
5051 | dev->stats.rx_packets++; |
5052 | dev->stats.rx_bytes += packet_len; | |
8ca86fd8 TH |
5053 | |
5054 | /* Notify upper layer for received packet. */ | |
8ca86fd8 TH |
5055 | rx_status = netif_rx(skb); |
5056 | ||
5057 | return 0; | |
5058 | } | |
5059 | ||
5060 | static int dev_rcv_packets(struct dev_info *hw_priv) | |
5061 | { | |
5062 | int next; | |
5063 | union desc_stat status; | |
5064 | struct ksz_hw *hw = &hw_priv->hw; | |
5065 | struct net_device *dev = hw->port_info[0].pdev; | |
5066 | struct ksz_desc_info *info = &hw->rx_desc_info; | |
5067 | int left = info->alloc; | |
5068 | struct ksz_desc *desc; | |
5069 | int received = 0; | |
5070 | ||
5071 | next = info->next; | |
5072 | while (left--) { | |
5073 | /* Get next descriptor which is not hardware owned. */ | |
5074 | desc = &info->ring[next]; | |
5075 | status.data = le32_to_cpu(desc->phw->ctrl.data); | |
5076 | if (status.rx.hw_owned) | |
5077 | break; | |
5078 | ||
5079 | /* Status valid only when last descriptor bit is set. */ | |
5080 | if (status.rx.last_desc && status.rx.first_desc) { | |
5081 | if (rx_proc(dev, hw, desc, status)) | |
5082 | goto release_packet; | |
5083 | received++; | |
5084 | } | |
5085 | ||
5086 | release_packet: | |
5087 | release_desc(desc); | |
5088 | next++; | |
5089 | next &= info->mask; | |
5090 | } | |
5091 | info->next = next; | |
5092 | ||
5093 | return received; | |
5094 | } | |
5095 | ||
5096 | static int port_rcv_packets(struct dev_info *hw_priv) | |
5097 | { | |
5098 | int next; | |
5099 | union desc_stat status; | |
5100 | struct ksz_hw *hw = &hw_priv->hw; | |
5101 | struct net_device *dev = hw->port_info[0].pdev; | |
5102 | struct ksz_desc_info *info = &hw->rx_desc_info; | |
5103 | int left = info->alloc; | |
5104 | struct ksz_desc *desc; | |
5105 | int received = 0; | |
5106 | ||
5107 | next = info->next; | |
5108 | while (left--) { | |
5109 | /* Get next descriptor which is not hardware owned. */ | |
5110 | desc = &info->ring[next]; | |
5111 | status.data = le32_to_cpu(desc->phw->ctrl.data); | |
5112 | if (status.rx.hw_owned) | |
5113 | break; | |
5114 | ||
5115 | if (hw->dev_count > 1) { | |
5116 | /* Get received port number. */ | |
5117 | int p = HW_TO_DEV_PORT(status.rx.src_port); | |
5118 | ||
5119 | dev = hw->port_info[p].pdev; | |
5120 | if (!netif_running(dev)) | |
5121 | goto release_packet; | |
5122 | } | |
5123 | ||
5124 | /* Status valid only when last descriptor bit is set. */ | |
5125 | if (status.rx.last_desc && status.rx.first_desc) { | |
5126 | if (rx_proc(dev, hw, desc, status)) | |
5127 | goto release_packet; | |
5128 | received++; | |
5129 | } | |
5130 | ||
5131 | release_packet: | |
5132 | release_desc(desc); | |
5133 | next++; | |
5134 | next &= info->mask; | |
5135 | } | |
5136 | info->next = next; | |
5137 | ||
5138 | return received; | |
5139 | } | |
5140 | ||
5141 | static int dev_rcv_special(struct dev_info *hw_priv) | |
5142 | { | |
5143 | int next; | |
5144 | union desc_stat status; | |
5145 | struct ksz_hw *hw = &hw_priv->hw; | |
5146 | struct net_device *dev = hw->port_info[0].pdev; | |
5147 | struct ksz_desc_info *info = &hw->rx_desc_info; | |
5148 | int left = info->alloc; | |
5149 | struct ksz_desc *desc; | |
5150 | int received = 0; | |
5151 | ||
5152 | next = info->next; | |
5153 | while (left--) { | |
5154 | /* Get next descriptor which is not hardware owned. */ | |
5155 | desc = &info->ring[next]; | |
5156 | status.data = le32_to_cpu(desc->phw->ctrl.data); | |
5157 | if (status.rx.hw_owned) | |
5158 | break; | |
5159 | ||
5160 | if (hw->dev_count > 1) { | |
5161 | /* Get received port number. */ | |
5162 | int p = HW_TO_DEV_PORT(status.rx.src_port); | |
5163 | ||
5164 | dev = hw->port_info[p].pdev; | |
5165 | if (!netif_running(dev)) | |
5166 | goto release_packet; | |
5167 | } | |
5168 | ||
5169 | /* Status valid only when last descriptor bit is set. */ | |
5170 | if (status.rx.last_desc && status.rx.first_desc) { | |
5171 | /* | |
5172 | * Receive without error. With receive errors | |
5173 | * disabled, packets with receive errors will be | |
5174 | * dropped, so no need to check the error bit. | |
5175 | */ | |
5176 | if (!status.rx.error || (status.data & | |
5177 | KS_DESC_RX_ERROR_COND) == | |
5178 | KS_DESC_RX_ERROR_TOO_LONG) { | |
5179 | if (rx_proc(dev, hw, desc, status)) | |
5180 | goto release_packet; | |
5181 | received++; | |
5182 | } else { | |
5183 | struct dev_priv *priv = netdev_priv(dev); | |
5184 | ||
5185 | /* Update receive error statistics. */ | |
5186 | priv->port.counter[OID_COUNTER_RCV_ERROR]++; | |
5187 | } | |
5188 | } | |
5189 | ||
5190 | release_packet: | |
5191 | release_desc(desc); | |
5192 | next++; | |
5193 | next &= info->mask; | |
5194 | } | |
5195 | info->next = next; | |
5196 | ||
5197 | return received; | |
5198 | } | |
5199 | ||
5200 | static void rx_proc_task(unsigned long data) | |
5201 | { | |
5202 | struct dev_info *hw_priv = (struct dev_info *) data; | |
5203 | struct ksz_hw *hw = &hw_priv->hw; | |
5204 | ||
5205 | if (!hw->enabled) | |
5206 | return; | |
5207 | if (unlikely(!hw_priv->dev_rcv(hw_priv))) { | |
5208 | ||
5209 | /* In case receive process is suspended because of overrun. */ | |
5210 | hw_resume_rx(hw); | |
5211 | ||
5212 | /* tasklets are interruptible. */ | |
5213 | spin_lock_irq(&hw_priv->hwlock); | |
5214 | hw_turn_on_intr(hw, KS884X_INT_RX_MASK); | |
5215 | spin_unlock_irq(&hw_priv->hwlock); | |
5216 | } else { | |
5217 | hw_ack_intr(hw, KS884X_INT_RX); | |
5218 | tasklet_schedule(&hw_priv->rx_tasklet); | |
5219 | } | |
5220 | } | |
5221 | ||
5222 | static void tx_proc_task(unsigned long data) | |
5223 | { | |
5224 | struct dev_info *hw_priv = (struct dev_info *) data; | |
5225 | struct ksz_hw *hw = &hw_priv->hw; | |
5226 | ||
5227 | hw_ack_intr(hw, KS884X_INT_TX_MASK); | |
5228 | ||
5229 | tx_done(hw_priv); | |
5230 | ||
5231 | /* tasklets are interruptible. */ | |
5232 | spin_lock_irq(&hw_priv->hwlock); | |
5233 | hw_turn_on_intr(hw, KS884X_INT_TX); | |
5234 | spin_unlock_irq(&hw_priv->hwlock); | |
5235 | } | |
5236 | ||
5237 | static inline void handle_rx_stop(struct ksz_hw *hw) | |
5238 | { | |
5239 | /* Receive just has been stopped. */ | |
5240 | if (0 == hw->rx_stop) | |
5241 | hw->intr_mask &= ~KS884X_INT_RX_STOPPED; | |
5242 | else if (hw->rx_stop > 1) { | |
5243 | if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) { | |
5244 | hw_start_rx(hw); | |
5245 | } else { | |
5246 | hw->intr_mask &= ~KS884X_INT_RX_STOPPED; | |
5247 | hw->rx_stop = 0; | |
5248 | } | |
5249 | } else | |
5250 | /* Receive just has been started. */ | |
5251 | hw->rx_stop++; | |
5252 | } | |
5253 | ||
5254 | /** | |
5255 | * netdev_intr - interrupt handling | |
5256 | * @irq: Interrupt number. | |
5257 | * @dev_id: Network device. | |
5258 | * | |
5259 | * This function is called by upper network layer to signal interrupt. | |
5260 | * | |
5261 | * Return IRQ_HANDLED if interrupt is handled. | |
5262 | */ | |
5263 | static irqreturn_t netdev_intr(int irq, void *dev_id) | |
5264 | { | |
5265 | uint int_enable = 0; | |
5266 | struct net_device *dev = (struct net_device *) dev_id; | |
5267 | struct dev_priv *priv = netdev_priv(dev); | |
5268 | struct dev_info *hw_priv = priv->adapter; | |
5269 | struct ksz_hw *hw = &hw_priv->hw; | |
5270 | ||
5271 | hw_read_intr(hw, &int_enable); | |
5272 | ||
5273 | /* Not our interrupt! */ | |
5274 | if (!int_enable) | |
5275 | return IRQ_NONE; | |
5276 | ||
5277 | do { | |
5278 | hw_ack_intr(hw, int_enable); | |
5279 | int_enable &= hw->intr_mask; | |
5280 | ||
5281 | if (unlikely(int_enable & KS884X_INT_TX_MASK)) { | |
5282 | hw_dis_intr_bit(hw, KS884X_INT_TX_MASK); | |
5283 | tasklet_schedule(&hw_priv->tx_tasklet); | |
5284 | } | |
5285 | ||
5286 | if (likely(int_enable & KS884X_INT_RX)) { | |
5287 | hw_dis_intr_bit(hw, KS884X_INT_RX); | |
5288 | tasklet_schedule(&hw_priv->rx_tasklet); | |
5289 | } | |
5290 | ||
5291 | if (unlikely(int_enable & KS884X_INT_RX_OVERRUN)) { | |
897dd41d | 5292 | dev->stats.rx_fifo_errors++; |
8ca86fd8 TH |
5293 | hw_resume_rx(hw); |
5294 | } | |
5295 | ||
5296 | if (unlikely(int_enable & KS884X_INT_PHY)) { | |
5297 | struct ksz_port *port = &priv->port; | |
5298 | ||
5299 | hw->features |= LINK_INT_WORKING; | |
5300 | port_get_link_speed(port); | |
5301 | } | |
5302 | ||
5303 | if (unlikely(int_enable & KS884X_INT_RX_STOPPED)) { | |
5304 | handle_rx_stop(hw); | |
5305 | break; | |
5306 | } | |
5307 | ||
5308 | if (unlikely(int_enable & KS884X_INT_TX_STOPPED)) { | |
5309 | u32 data; | |
5310 | ||
5311 | hw->intr_mask &= ~KS884X_INT_TX_STOPPED; | |
0dc7d2b3 | 5312 | pr_info("Tx stopped\n"); |
8ca86fd8 TH |
5313 | data = readl(hw->io + KS_DMA_TX_CTRL); |
5314 | if (!(data & DMA_TX_ENABLE)) | |
0dc7d2b3 | 5315 | pr_info("Tx disabled\n"); |
8ca86fd8 TH |
5316 | break; |
5317 | } | |
5318 | } while (0); | |
5319 | ||
5320 | hw_ena_intr(hw); | |
5321 | ||
5322 | return IRQ_HANDLED; | |
5323 | } | |
5324 | ||
5325 | /* | |
5326 | * Linux network device functions | |
5327 | */ | |
5328 | ||
5329 | static unsigned long next_jiffies; | |
5330 | ||
5331 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
5332 | static void netdev_netpoll(struct net_device *dev) | |
5333 | { | |
5334 | struct dev_priv *priv = netdev_priv(dev); | |
5335 | struct dev_info *hw_priv = priv->adapter; | |
5336 | ||
5337 | hw_dis_intr(&hw_priv->hw); | |
5338 | netdev_intr(dev->irq, dev); | |
5339 | } | |
5340 | #endif | |
5341 | ||
5342 | static void bridge_change(struct ksz_hw *hw) | |
5343 | { | |
5344 | int port; | |
5345 | u8 member; | |
5346 | struct ksz_switch *sw = hw->ksz_switch; | |
5347 | ||
5348 | /* No ports in forwarding state. */ | |
5349 | if (!sw->member) { | |
5350 | port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE); | |
5351 | sw_block_addr(hw); | |
5352 | } | |
5353 | for (port = 0; port < SWITCH_PORT_NUM; port++) { | |
5354 | if (STP_STATE_FORWARDING == sw->port_cfg[port].stp_state) | |
5355 | member = HOST_MASK | sw->member; | |
5356 | else | |
5357 | member = HOST_MASK | (1 << port); | |
5358 | if (member != sw->port_cfg[port].member) | |
5359 | sw_cfg_port_base_vlan(hw, port, member); | |
5360 | } | |
5361 | } | |
5362 | ||
5363 | /** | |
5364 | * netdev_close - close network device | |
5365 | * @dev: Network device. | |
5366 | * | |
5367 | * This function process the close operation of network device. This is caused | |
5368 | * by the user command "ifconfig ethX down." | |
5369 | * | |
5370 | * Return 0 if successful; otherwise an error code indicating failure. | |
5371 | */ | |
5372 | static int netdev_close(struct net_device *dev) | |
5373 | { | |
5374 | struct dev_priv *priv = netdev_priv(dev); | |
5375 | struct dev_info *hw_priv = priv->adapter; | |
5376 | struct ksz_port *port = &priv->port; | |
5377 | struct ksz_hw *hw = &hw_priv->hw; | |
5378 | int pi; | |
5379 | ||
5380 | netif_stop_queue(dev); | |
5381 | ||
5382 | ksz_stop_timer(&priv->monitor_timer_info); | |
5383 | ||
5384 | /* Need to shut the port manually in multiple device interfaces mode. */ | |
5385 | if (hw->dev_count > 1) { | |
5386 | port_set_stp_state(hw, port->first_port, STP_STATE_DISABLED); | |
5387 | ||
5388 | /* Port is closed. Need to change bridge setting. */ | |
5389 | if (hw->features & STP_SUPPORT) { | |
5390 | pi = 1 << port->first_port; | |
5391 | if (hw->ksz_switch->member & pi) { | |
5392 | hw->ksz_switch->member &= ~pi; | |
5393 | bridge_change(hw); | |
5394 | } | |
5395 | } | |
5396 | } | |
5397 | if (port->first_port > 0) | |
5398 | hw_del_addr(hw, dev->dev_addr); | |
5399 | if (!hw_priv->wol_enable) | |
5400 | port_set_power_saving(port, true); | |
5401 | ||
5402 | if (priv->multicast) | |
5403 | --hw->all_multi; | |
5404 | if (priv->promiscuous) | |
5405 | --hw->promiscuous; | |
5406 | ||
5407 | hw_priv->opened--; | |
5408 | if (!(hw_priv->opened)) { | |
5409 | ksz_stop_timer(&hw_priv->mib_timer_info); | |
5410 | flush_work(&hw_priv->mib_read); | |
5411 | ||
5412 | hw_dis_intr(hw); | |
5413 | hw_disable(hw); | |
5414 | hw_clr_multicast(hw); | |
5415 | ||
5416 | /* Delay for receive task to stop scheduling itself. */ | |
5417 | msleep(2000 / HZ); | |
5418 | ||
5419 | tasklet_disable(&hw_priv->rx_tasklet); | |
5420 | tasklet_disable(&hw_priv->tx_tasklet); | |
5421 | free_irq(dev->irq, hw_priv->dev); | |
5422 | ||
5423 | transmit_cleanup(hw_priv, 0); | |
5424 | hw_reset_pkts(&hw->rx_desc_info); | |
5425 | hw_reset_pkts(&hw->tx_desc_info); | |
5426 | ||
5427 | /* Clean out static MAC table when the switch is shutdown. */ | |
5428 | if (hw->features & STP_SUPPORT) | |
5429 | sw_clr_sta_mac_table(hw); | |
5430 | } | |
5431 | ||
5432 | return 0; | |
5433 | } | |
5434 | ||
5435 | static void hw_cfg_huge_frame(struct dev_info *hw_priv, struct ksz_hw *hw) | |
5436 | { | |
5437 | if (hw->ksz_switch) { | |
5438 | u32 data; | |
5439 | ||
5440 | data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET); | |
5441 | if (hw->features & RX_HUGE_FRAME) | |
5442 | data |= SWITCH_HUGE_PACKET; | |
5443 | else | |
5444 | data &= ~SWITCH_HUGE_PACKET; | |
5445 | writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET); | |
5446 | } | |
5447 | if (hw->features & RX_HUGE_FRAME) { | |
5448 | hw->rx_cfg |= DMA_RX_ERROR; | |
5449 | hw_priv->dev_rcv = dev_rcv_special; | |
5450 | } else { | |
5451 | hw->rx_cfg &= ~DMA_RX_ERROR; | |
5452 | if (hw->dev_count > 1) | |
5453 | hw_priv->dev_rcv = port_rcv_packets; | |
5454 | else | |
5455 | hw_priv->dev_rcv = dev_rcv_packets; | |
5456 | } | |
5457 | } | |
5458 | ||
5459 | static int prepare_hardware(struct net_device *dev) | |
5460 | { | |
5461 | struct dev_priv *priv = netdev_priv(dev); | |
5462 | struct dev_info *hw_priv = priv->adapter; | |
5463 | struct ksz_hw *hw = &hw_priv->hw; | |
5464 | int rc = 0; | |
5465 | ||
5466 | /* Remember the network device that requests interrupts. */ | |
5467 | hw_priv->dev = dev; | |
5468 | rc = request_irq(dev->irq, netdev_intr, IRQF_SHARED, dev->name, dev); | |
5469 | if (rc) | |
5470 | return rc; | |
5471 | tasklet_enable(&hw_priv->rx_tasklet); | |
5472 | tasklet_enable(&hw_priv->tx_tasklet); | |
5473 | ||
5474 | hw->promiscuous = 0; | |
5475 | hw->all_multi = 0; | |
5476 | hw->multi_list_size = 0; | |
5477 | ||
5478 | hw_reset(hw); | |
5479 | ||
5480 | hw_set_desc_base(hw, | |
5481 | hw->tx_desc_info.ring_phys, hw->rx_desc_info.ring_phys); | |
5482 | hw_set_addr(hw); | |
5483 | hw_cfg_huge_frame(hw_priv, hw); | |
5484 | ksz_init_rx_buffers(hw_priv); | |
5485 | return 0; | |
5486 | } | |
5487 | ||
0dc7d2b3 JP |
5488 | static void set_media_state(struct net_device *dev, int media_state) |
5489 | { | |
5490 | struct dev_priv *priv = netdev_priv(dev); | |
5491 | ||
5492 | if (media_state == priv->media_state) | |
5493 | netif_carrier_on(dev); | |
5494 | else | |
5495 | netif_carrier_off(dev); | |
5496 | netif_info(priv, link, dev, "link %s\n", | |
5497 | media_state == priv->media_state ? "on" : "off"); | |
5498 | } | |
5499 | ||
8ca86fd8 TH |
5500 | /** |
5501 | * netdev_open - open network device | |
5502 | * @dev: Network device. | |
5503 | * | |
5504 | * This function process the open operation of network device. This is caused | |
5505 | * by the user command "ifconfig ethX up." | |
5506 | * | |
5507 | * Return 0 if successful; otherwise an error code indicating failure. | |
5508 | */ | |
5509 | static int netdev_open(struct net_device *dev) | |
5510 | { | |
5511 | struct dev_priv *priv = netdev_priv(dev); | |
5512 | struct dev_info *hw_priv = priv->adapter; | |
5513 | struct ksz_hw *hw = &hw_priv->hw; | |
5514 | struct ksz_port *port = &priv->port; | |
5515 | int i; | |
5516 | int p; | |
5517 | int rc = 0; | |
5518 | ||
5519 | priv->multicast = 0; | |
5520 | priv->promiscuous = 0; | |
5521 | ||
5522 | /* Reset device statistics. */ | |
897dd41d | 5523 | memset(&dev->stats, 0, sizeof(struct net_device_stats)); |
8ca86fd8 TH |
5524 | memset((void *) port->counter, 0, |
5525 | (sizeof(u64) * OID_COUNTER_LAST)); | |
5526 | ||
5527 | if (!(hw_priv->opened)) { | |
5528 | rc = prepare_hardware(dev); | |
5529 | if (rc) | |
5530 | return rc; | |
5531 | for (i = 0; i < hw->mib_port_cnt; i++) { | |
5532 | if (next_jiffies < jiffies) | |
5533 | next_jiffies = jiffies + HZ * 2; | |
5534 | else | |
5535 | next_jiffies += HZ * 1; | |
5536 | hw_priv->counter[i].time = next_jiffies; | |
5537 | hw->port_mib[i].state = media_disconnected; | |
5538 | port_init_cnt(hw, i); | |
5539 | } | |
5540 | if (hw->ksz_switch) | |
5541 | hw->port_mib[HOST_PORT].state = media_connected; | |
5542 | else { | |
5543 | hw_add_wol_bcast(hw); | |
5544 | hw_cfg_wol_pme(hw, 0); | |
5545 | hw_clr_wol_pme_status(&hw_priv->hw); | |
5546 | } | |
5547 | } | |
5548 | port_set_power_saving(port, false); | |
5549 | ||
5550 | for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { | |
5551 | /* | |
5552 | * Initialize to invalid value so that link detection | |
5553 | * is done. | |
5554 | */ | |
5555 | hw->port_info[p].partner = 0xFF; | |
5556 | hw->port_info[p].state = media_disconnected; | |
5557 | } | |
5558 | ||
5559 | /* Need to open the port in multiple device interfaces mode. */ | |
5560 | if (hw->dev_count > 1) { | |
5561 | port_set_stp_state(hw, port->first_port, STP_STATE_SIMPLE); | |
5562 | if (port->first_port > 0) | |
5563 | hw_add_addr(hw, dev->dev_addr); | |
5564 | } | |
5565 | ||
5566 | port_get_link_speed(port); | |
5567 | if (port->force_link) | |
5568 | port_force_link_speed(port); | |
5569 | else | |
5570 | port_set_link_speed(port); | |
5571 | ||
5572 | if (!(hw_priv->opened)) { | |
5573 | hw_setup_intr(hw); | |
5574 | hw_enable(hw); | |
5575 | hw_ena_intr(hw); | |
5576 | ||
5577 | if (hw->mib_port_cnt) | |
5578 | ksz_start_timer(&hw_priv->mib_timer_info, | |
5579 | hw_priv->mib_timer_info.period); | |
5580 | } | |
5581 | ||
5582 | hw_priv->opened++; | |
5583 | ||
5584 | ksz_start_timer(&priv->monitor_timer_info, | |
5585 | priv->monitor_timer_info.period); | |
5586 | ||
5587 | priv->media_state = port->linked->state; | |
5588 | ||
0dc7d2b3 | 5589 | set_media_state(dev, media_connected); |
8ca86fd8 TH |
5590 | netif_start_queue(dev); |
5591 | ||
5592 | return 0; | |
5593 | } | |
5594 | ||
5595 | /* RX errors = rx_errors */ | |
5596 | /* RX dropped = rx_dropped */ | |
5597 | /* RX overruns = rx_fifo_errors */ | |
5598 | /* RX frame = rx_crc_errors + rx_frame_errors + rx_length_errors */ | |
5599 | /* TX errors = tx_errors */ | |
5600 | /* TX dropped = tx_dropped */ | |
5601 | /* TX overruns = tx_fifo_errors */ | |
5602 | /* TX carrier = tx_aborted_errors + tx_carrier_errors + tx_window_errors */ | |
5603 | /* collisions = collisions */ | |
5604 | ||
5605 | /** | |
5606 | * netdev_query_statistics - query network device statistics | |
5607 | * @dev: Network device. | |
5608 | * | |
5609 | * This function returns the statistics of the network device. The device | |
5610 | * needs not be opened. | |
5611 | * | |
5612 | * Return network device statistics. | |
5613 | */ | |
5614 | static struct net_device_stats *netdev_query_statistics(struct net_device *dev) | |
5615 | { | |
5616 | struct dev_priv *priv = netdev_priv(dev); | |
5617 | struct ksz_port *port = &priv->port; | |
5618 | struct ksz_hw *hw = &priv->adapter->hw; | |
5619 | struct ksz_port_mib *mib; | |
5620 | int i; | |
5621 | int p; | |
5622 | ||
897dd41d KV |
5623 | dev->stats.rx_errors = port->counter[OID_COUNTER_RCV_ERROR]; |
5624 | dev->stats.tx_errors = port->counter[OID_COUNTER_XMIT_ERROR]; | |
8ca86fd8 TH |
5625 | |
5626 | /* Reset to zero to add count later. */ | |
897dd41d KV |
5627 | dev->stats.multicast = 0; |
5628 | dev->stats.collisions = 0; | |
5629 | dev->stats.rx_length_errors = 0; | |
5630 | dev->stats.rx_crc_errors = 0; | |
5631 | dev->stats.rx_frame_errors = 0; | |
5632 | dev->stats.tx_window_errors = 0; | |
8ca86fd8 TH |
5633 | |
5634 | for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) { | |
5635 | mib = &hw->port_mib[p]; | |
5636 | ||
897dd41d | 5637 | dev->stats.multicast += (unsigned long) |
8ca86fd8 TH |
5638 | mib->counter[MIB_COUNTER_RX_MULTICAST]; |
5639 | ||
897dd41d | 5640 | dev->stats.collisions += (unsigned long) |
8ca86fd8 TH |
5641 | mib->counter[MIB_COUNTER_TX_TOTAL_COLLISION]; |
5642 | ||
897dd41d | 5643 | dev->stats.rx_length_errors += (unsigned long)( |
8ca86fd8 TH |
5644 | mib->counter[MIB_COUNTER_RX_UNDERSIZE] + |
5645 | mib->counter[MIB_COUNTER_RX_FRAGMENT] + | |
5646 | mib->counter[MIB_COUNTER_RX_OVERSIZE] + | |
5647 | mib->counter[MIB_COUNTER_RX_JABBER]); | |
897dd41d | 5648 | dev->stats.rx_crc_errors += (unsigned long) |
8ca86fd8 | 5649 | mib->counter[MIB_COUNTER_RX_CRC_ERR]; |
897dd41d | 5650 | dev->stats.rx_frame_errors += (unsigned long)( |
8ca86fd8 TH |
5651 | mib->counter[MIB_COUNTER_RX_ALIGNMENT_ERR] + |
5652 | mib->counter[MIB_COUNTER_RX_SYMBOL_ERR]); | |
5653 | ||
897dd41d | 5654 | dev->stats.tx_window_errors += (unsigned long) |
8ca86fd8 TH |
5655 | mib->counter[MIB_COUNTER_TX_LATE_COLLISION]; |
5656 | } | |
5657 | ||
897dd41d | 5658 | return &dev->stats; |
8ca86fd8 TH |
5659 | } |
5660 | ||
5661 | /** | |
5662 | * netdev_set_mac_address - set network device MAC address | |
5663 | * @dev: Network device. | |
5664 | * @addr: Buffer of MAC address. | |
5665 | * | |
5666 | * This function is used to set the MAC address of the network device. | |
5667 | * | |
5668 | * Return 0 to indicate success. | |
5669 | */ | |
5670 | static int netdev_set_mac_address(struct net_device *dev, void *addr) | |
5671 | { | |
5672 | struct dev_priv *priv = netdev_priv(dev); | |
5673 | struct dev_info *hw_priv = priv->adapter; | |
5674 | struct ksz_hw *hw = &hw_priv->hw; | |
5675 | struct sockaddr *mac = addr; | |
5676 | uint interrupt; | |
5677 | ||
5678 | if (priv->port.first_port > 0) | |
5679 | hw_del_addr(hw, dev->dev_addr); | |
5680 | else { | |
5681 | hw->mac_override = 1; | |
5682 | memcpy(hw->override_addr, mac->sa_data, MAC_ADDR_LEN); | |
5683 | } | |
5684 | ||
5685 | memcpy(dev->dev_addr, mac->sa_data, MAX_ADDR_LEN); | |
5686 | ||
5687 | interrupt = hw_block_intr(hw); | |
5688 | ||
5689 | if (priv->port.first_port > 0) | |
5690 | hw_add_addr(hw, dev->dev_addr); | |
5691 | else | |
5692 | hw_set_addr(hw); | |
5693 | hw_restore_intr(hw, interrupt); | |
5694 | ||
5695 | return 0; | |
5696 | } | |
5697 | ||
5698 | static void dev_set_promiscuous(struct net_device *dev, struct dev_priv *priv, | |
5699 | struct ksz_hw *hw, int promiscuous) | |
5700 | { | |
5701 | if (promiscuous != priv->promiscuous) { | |
5702 | u8 prev_state = hw->promiscuous; | |
5703 | ||
5704 | if (promiscuous) | |
5705 | ++hw->promiscuous; | |
5706 | else | |
5707 | --hw->promiscuous; | |
5708 | priv->promiscuous = promiscuous; | |
5709 | ||
5710 | /* Turn on/off promiscuous mode. */ | |
5711 | if (hw->promiscuous <= 1 && prev_state <= 1) | |
5712 | hw_set_promiscuous(hw, hw->promiscuous); | |
5713 | ||
5714 | /* | |
5715 | * Port is not in promiscuous mode, meaning it is released | |
5716 | * from the bridge. | |
5717 | */ | |
5718 | if ((hw->features & STP_SUPPORT) && !promiscuous && | |
f350a0a8 | 5719 | (dev->priv_flags & IFF_BRIDGE_PORT)) { |
8ca86fd8 TH |
5720 | struct ksz_switch *sw = hw->ksz_switch; |
5721 | int port = priv->port.first_port; | |
5722 | ||
5723 | port_set_stp_state(hw, port, STP_STATE_DISABLED); | |
5724 | port = 1 << port; | |
5725 | if (sw->member & port) { | |
5726 | sw->member &= ~port; | |
5727 | bridge_change(hw); | |
5728 | } | |
5729 | } | |
5730 | } | |
5731 | } | |
5732 | ||
5733 | static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw, | |
5734 | int multicast) | |
5735 | { | |
5736 | if (multicast != priv->multicast) { | |
5737 | u8 all_multi = hw->all_multi; | |
5738 | ||
5739 | if (multicast) | |
5740 | ++hw->all_multi; | |
5741 | else | |
5742 | --hw->all_multi; | |
5743 | priv->multicast = multicast; | |
5744 | ||
5745 | /* Turn on/off all multicast mode. */ | |
5746 | if (hw->all_multi <= 1 && all_multi <= 1) | |
5747 | hw_set_multicast(hw, hw->all_multi); | |
5748 | } | |
5749 | } | |
5750 | ||
5751 | /** | |
5752 | * netdev_set_rx_mode | |
5753 | * @dev: Network device. | |
5754 | * | |
5755 | * This routine is used to set multicast addresses or put the network device | |
5756 | * into promiscuous mode. | |
5757 | */ | |
5758 | static void netdev_set_rx_mode(struct net_device *dev) | |
5759 | { | |
5760 | struct dev_priv *priv = netdev_priv(dev); | |
5761 | struct dev_info *hw_priv = priv->adapter; | |
5762 | struct ksz_hw *hw = &hw_priv->hw; | |
22bedad3 | 5763 | struct netdev_hw_addr *ha; |
8ca86fd8 TH |
5764 | int multicast = (dev->flags & IFF_ALLMULTI); |
5765 | ||
5766 | dev_set_promiscuous(dev, priv, hw, (dev->flags & IFF_PROMISC)); | |
5767 | ||
5768 | if (hw_priv->hw.dev_count > 1) | |
5769 | multicast |= (dev->flags & IFF_MULTICAST); | |
5770 | dev_set_multicast(priv, hw, multicast); | |
5771 | ||
5772 | /* Cannot use different hashes in multiple device interfaces mode. */ | |
5773 | if (hw_priv->hw.dev_count > 1) | |
5774 | return; | |
5775 | ||
f9dcbcc9 | 5776 | if ((dev->flags & IFF_MULTICAST) && !netdev_mc_empty(dev)) { |
8ca86fd8 TH |
5777 | int i = 0; |
5778 | ||
5779 | /* List too big to support so turn on all multicast mode. */ | |
22bedad3 | 5780 | if (netdev_mc_count(dev) > MAX_MULTICAST_LIST) { |
8ca86fd8 TH |
5781 | if (MAX_MULTICAST_LIST != hw->multi_list_size) { |
5782 | hw->multi_list_size = MAX_MULTICAST_LIST; | |
5783 | ++hw->all_multi; | |
5784 | hw_set_multicast(hw, hw->all_multi); | |
5785 | } | |
5786 | return; | |
5787 | } | |
5788 | ||
22bedad3 JP |
5789 | netdev_for_each_mc_addr(ha, dev) { |
5790 | if (!(*ha->addr & 1)) | |
8ca86fd8 TH |
5791 | continue; |
5792 | if (i >= MAX_MULTICAST_LIST) | |
5793 | break; | |
22bedad3 | 5794 | memcpy(hw->multi_list[i++], ha->addr, MAC_ADDR_LEN); |
8ca86fd8 TH |
5795 | } |
5796 | hw->multi_list_size = (u8) i; | |
5797 | hw_set_grp_addr(hw); | |
5798 | } else { | |
5799 | if (MAX_MULTICAST_LIST == hw->multi_list_size) { | |
5800 | --hw->all_multi; | |
5801 | hw_set_multicast(hw, hw->all_multi); | |
5802 | } | |
5803 | hw->multi_list_size = 0; | |
5804 | hw_clr_multicast(hw); | |
5805 | } | |
5806 | } | |
5807 | ||
5808 | static int netdev_change_mtu(struct net_device *dev, int new_mtu) | |
5809 | { | |
5810 | struct dev_priv *priv = netdev_priv(dev); | |
5811 | struct dev_info *hw_priv = priv->adapter; | |
5812 | struct ksz_hw *hw = &hw_priv->hw; | |
5813 | int hw_mtu; | |
5814 | ||
5815 | if (netif_running(dev)) | |
5816 | return -EBUSY; | |
5817 | ||
5818 | /* Cannot use different MTU in multiple device interfaces mode. */ | |
5819 | if (hw->dev_count > 1) | |
5820 | if (dev != hw_priv->dev) | |
5821 | return 0; | |
5822 | if (new_mtu < 60) | |
5823 | return -EINVAL; | |
5824 | ||
5825 | if (dev->mtu != new_mtu) { | |
5826 | hw_mtu = new_mtu + ETHERNET_HEADER_SIZE + 4; | |
5827 | if (hw_mtu > MAX_RX_BUF_SIZE) | |
5828 | return -EINVAL; | |
5829 | if (hw_mtu > REGULAR_RX_BUF_SIZE) { | |
5830 | hw->features |= RX_HUGE_FRAME; | |
5831 | hw_mtu = MAX_RX_BUF_SIZE; | |
5832 | } else { | |
5833 | hw->features &= ~RX_HUGE_FRAME; | |
5834 | hw_mtu = REGULAR_RX_BUF_SIZE; | |
5835 | } | |
5836 | hw_mtu = (hw_mtu + 3) & ~3; | |
5837 | hw_priv->mtu = hw_mtu; | |
5838 | dev->mtu = new_mtu; | |
5839 | } | |
5840 | return 0; | |
5841 | } | |
5842 | ||
5843 | /** | |
5844 | * netdev_ioctl - I/O control processing | |
5845 | * @dev: Network device. | |
5846 | * @ifr: Interface request structure. | |
5847 | * @cmd: I/O control code. | |
5848 | * | |
5849 | * This function is used to process I/O control calls. | |
5850 | * | |
5851 | * Return 0 to indicate success. | |
5852 | */ | |
5853 | static int netdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
5854 | { | |
5855 | struct dev_priv *priv = netdev_priv(dev); | |
5856 | struct dev_info *hw_priv = priv->adapter; | |
5857 | struct ksz_hw *hw = &hw_priv->hw; | |
5858 | struct ksz_port *port = &priv->port; | |
5859 | int rc; | |
5860 | int result = 0; | |
5861 | struct mii_ioctl_data *data = if_mii(ifr); | |
5862 | ||
5863 | if (down_interruptible(&priv->proc_sem)) | |
5864 | return -ERESTARTSYS; | |
5865 | ||
5866 | /* assume success */ | |
5867 | rc = 0; | |
5868 | switch (cmd) { | |
5869 | /* Get address of MII PHY in use. */ | |
5870 | case SIOCGMIIPHY: | |
5871 | data->phy_id = priv->id; | |
5872 | ||
5873 | /* Fallthrough... */ | |
5874 | ||
5875 | /* Read MII PHY register. */ | |
5876 | case SIOCGMIIREG: | |
5877 | if (data->phy_id != priv->id || data->reg_num >= 6) | |
5878 | result = -EIO; | |
5879 | else | |
5880 | hw_r_phy(hw, port->linked->port_id, data->reg_num, | |
5881 | &data->val_out); | |
5882 | break; | |
5883 | ||
5884 | /* Write MII PHY register. */ | |
5885 | case SIOCSMIIREG: | |
5886 | if (!capable(CAP_NET_ADMIN)) | |
5887 | result = -EPERM; | |
5888 | else if (data->phy_id != priv->id || data->reg_num >= 6) | |
5889 | result = -EIO; | |
5890 | else | |
5891 | hw_w_phy(hw, port->linked->port_id, data->reg_num, | |
5892 | data->val_in); | |
5893 | break; | |
5894 | ||
5895 | default: | |
5896 | result = -EOPNOTSUPP; | |
5897 | } | |
5898 | ||
5899 | up(&priv->proc_sem); | |
5900 | ||
5901 | return result; | |
5902 | } | |
5903 | ||
5904 | /* | |
5905 | * MII support | |
5906 | */ | |
5907 | ||
5908 | /** | |
5909 | * mdio_read - read PHY register | |
5910 | * @dev: Network device. | |
5911 | * @phy_id: The PHY id. | |
5912 | * @reg_num: The register number. | |
5913 | * | |
5914 | * This function returns the PHY register value. | |
5915 | * | |
5916 | * Return the register value. | |
5917 | */ | |
5918 | static int mdio_read(struct net_device *dev, int phy_id, int reg_num) | |
5919 | { | |
5920 | struct dev_priv *priv = netdev_priv(dev); | |
5921 | struct ksz_port *port = &priv->port; | |
5922 | struct ksz_hw *hw = port->hw; | |
5923 | u16 val_out; | |
5924 | ||
5925 | hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out); | |
5926 | return val_out; | |
5927 | } | |
5928 | ||
5929 | /** | |
5930 | * mdio_write - set PHY register | |
5931 | * @dev: Network device. | |
5932 | * @phy_id: The PHY id. | |
5933 | * @reg_num: The register number. | |
5934 | * @val: The register value. | |
5935 | * | |
5936 | * This procedure sets the PHY register value. | |
5937 | */ | |
5938 | static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) | |
5939 | { | |
5940 | struct dev_priv *priv = netdev_priv(dev); | |
5941 | struct ksz_port *port = &priv->port; | |
5942 | struct ksz_hw *hw = port->hw; | |
5943 | int i; | |
5944 | int pi; | |
5945 | ||
5946 | for (i = 0, pi = port->first_port; i < port->port_cnt; i++, pi++) | |
5947 | hw_w_phy(hw, pi, reg_num << 1, val); | |
5948 | } | |
5949 | ||
5950 | /* | |
5951 | * ethtool support | |
5952 | */ | |
5953 | ||
5954 | #define EEPROM_SIZE 0x40 | |
5955 | ||
5956 | static u16 eeprom_data[EEPROM_SIZE] = { 0 }; | |
5957 | ||
5958 | #define ADVERTISED_ALL \ | |
5959 | (ADVERTISED_10baseT_Half | \ | |
5960 | ADVERTISED_10baseT_Full | \ | |
5961 | ADVERTISED_100baseT_Half | \ | |
5962 | ADVERTISED_100baseT_Full) | |
5963 | ||
5964 | /* These functions use the MII functions in mii.c. */ | |
5965 | ||
5966 | /** | |
5967 | * netdev_get_settings - get network device settings | |
5968 | * @dev: Network device. | |
5969 | * @cmd: Ethtool command. | |
5970 | * | |
5971 | * This function queries the PHY and returns its state in the ethtool command. | |
5972 | * | |
5973 | * Return 0 if successful; otherwise an error code. | |
5974 | */ | |
5975 | static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
5976 | { | |
5977 | struct dev_priv *priv = netdev_priv(dev); | |
5978 | struct dev_info *hw_priv = priv->adapter; | |
5979 | ||
5980 | mutex_lock(&hw_priv->lock); | |
5981 | mii_ethtool_gset(&priv->mii_if, cmd); | |
5982 | cmd->advertising |= SUPPORTED_TP; | |
5983 | mutex_unlock(&hw_priv->lock); | |
5984 | ||
5985 | /* Save advertised settings for workaround in next function. */ | |
5986 | priv->advertising = cmd->advertising; | |
5987 | return 0; | |
5988 | } | |
5989 | ||
5990 | /** | |
5991 | * netdev_set_settings - set network device settings | |
5992 | * @dev: Network device. | |
5993 | * @cmd: Ethtool command. | |
5994 | * | |
5995 | * This function sets the PHY according to the ethtool command. | |
5996 | * | |
5997 | * Return 0 if successful; otherwise an error code. | |
5998 | */ | |
5999 | static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
6000 | { | |
6001 | struct dev_priv *priv = netdev_priv(dev); | |
6002 | struct dev_info *hw_priv = priv->adapter; | |
6003 | struct ksz_port *port = &priv->port; | |
6004 | int rc; | |
6005 | ||
6006 | /* | |
6007 | * ethtool utility does not change advertised setting if auto | |
6008 | * negotiation is not specified explicitly. | |
6009 | */ | |
6010 | if (cmd->autoneg && priv->advertising == cmd->advertising) { | |
6011 | cmd->advertising |= ADVERTISED_ALL; | |
6012 | if (10 == cmd->speed) | |
6013 | cmd->advertising &= | |
6014 | ~(ADVERTISED_100baseT_Full | | |
6015 | ADVERTISED_100baseT_Half); | |
6016 | else if (100 == cmd->speed) | |
6017 | cmd->advertising &= | |
6018 | ~(ADVERTISED_10baseT_Full | | |
6019 | ADVERTISED_10baseT_Half); | |
6020 | if (0 == cmd->duplex) | |
6021 | cmd->advertising &= | |
6022 | ~(ADVERTISED_100baseT_Full | | |
6023 | ADVERTISED_10baseT_Full); | |
6024 | else if (1 == cmd->duplex) | |
6025 | cmd->advertising &= | |
6026 | ~(ADVERTISED_100baseT_Half | | |
6027 | ADVERTISED_10baseT_Half); | |
6028 | } | |
6029 | mutex_lock(&hw_priv->lock); | |
6030 | if (cmd->autoneg && | |
6031 | (cmd->advertising & ADVERTISED_ALL) == | |
6032 | ADVERTISED_ALL) { | |
6033 | port->duplex = 0; | |
6034 | port->speed = 0; | |
6035 | port->force_link = 0; | |
6036 | } else { | |
6037 | port->duplex = cmd->duplex + 1; | |
6038 | if (cmd->speed != 1000) | |
6039 | port->speed = cmd->speed; | |
6040 | if (cmd->autoneg) | |
6041 | port->force_link = 0; | |
6042 | else | |
6043 | port->force_link = 1; | |
6044 | } | |
6045 | rc = mii_ethtool_sset(&priv->mii_if, cmd); | |
6046 | mutex_unlock(&hw_priv->lock); | |
6047 | return rc; | |
6048 | } | |
6049 | ||
6050 | /** | |
6051 | * netdev_nway_reset - restart auto-negotiation | |
6052 | * @dev: Network device. | |
6053 | * | |
6054 | * This function restarts the PHY for auto-negotiation. | |
6055 | * | |
6056 | * Return 0 if successful; otherwise an error code. | |
6057 | */ | |
6058 | static int netdev_nway_reset(struct net_device *dev) | |
6059 | { | |
6060 | struct dev_priv *priv = netdev_priv(dev); | |
6061 | struct dev_info *hw_priv = priv->adapter; | |
6062 | int rc; | |
6063 | ||
6064 | mutex_lock(&hw_priv->lock); | |
6065 | rc = mii_nway_restart(&priv->mii_if); | |
6066 | mutex_unlock(&hw_priv->lock); | |
6067 | return rc; | |
6068 | } | |
6069 | ||
6070 | /** | |
6071 | * netdev_get_link - get network device link status | |
6072 | * @dev: Network device. | |
6073 | * | |
6074 | * This function gets the link status from the PHY. | |
6075 | * | |
6076 | * Return true if PHY is linked and false otherwise. | |
6077 | */ | |
6078 | static u32 netdev_get_link(struct net_device *dev) | |
6079 | { | |
6080 | struct dev_priv *priv = netdev_priv(dev); | |
6081 | int rc; | |
6082 | ||
6083 | rc = mii_link_ok(&priv->mii_if); | |
6084 | return rc; | |
6085 | } | |
6086 | ||
6087 | /** | |
6088 | * netdev_get_drvinfo - get network driver information | |
6089 | * @dev: Network device. | |
6090 | * @info: Ethtool driver info data structure. | |
6091 | * | |
6092 | * This procedure returns the driver information. | |
6093 | */ | |
6094 | static void netdev_get_drvinfo(struct net_device *dev, | |
6095 | struct ethtool_drvinfo *info) | |
6096 | { | |
6097 | struct dev_priv *priv = netdev_priv(dev); | |
6098 | struct dev_info *hw_priv = priv->adapter; | |
6099 | ||
6100 | strcpy(info->driver, DRV_NAME); | |
6101 | strcpy(info->version, DRV_VERSION); | |
6102 | strcpy(info->bus_info, pci_name(hw_priv->pdev)); | |
6103 | } | |
6104 | ||
6105 | /** | |
6106 | * netdev_get_regs_len - get length of register dump | |
6107 | * @dev: Network device. | |
6108 | * | |
6109 | * This function returns the length of the register dump. | |
6110 | * | |
6111 | * Return length of the register dump. | |
6112 | */ | |
6113 | static struct hw_regs { | |
6114 | int start; | |
6115 | int end; | |
6116 | } hw_regs_range[] = { | |
6117 | { KS_DMA_TX_CTRL, KS884X_INTERRUPTS_STATUS }, | |
6118 | { KS_ADD_ADDR_0_LO, KS_ADD_ADDR_F_HI }, | |
6119 | { KS884X_ADDR_0_OFFSET, KS8841_WOL_FRAME_BYTE2_OFFSET }, | |
6120 | { KS884X_SIDER_P, KS8842_SGCR7_P }, | |
6121 | { KS8842_MACAR1_P, KS8842_TOSR8_P }, | |
6122 | { KS884X_P1MBCR_P, KS8842_P3ERCR_P }, | |
6123 | { 0, 0 } | |
6124 | }; | |
6125 | ||
6126 | static int netdev_get_regs_len(struct net_device *dev) | |
6127 | { | |
6128 | struct hw_regs *range = hw_regs_range; | |
6129 | int regs_len = 0x10 * sizeof(u32); | |
6130 | ||
6131 | while (range->end > range->start) { | |
6132 | regs_len += (range->end - range->start + 3) / 4 * 4; | |
6133 | range++; | |
6134 | } | |
6135 | return regs_len; | |
6136 | } | |
6137 | ||
6138 | /** | |
6139 | * netdev_get_regs - get register dump | |
6140 | * @dev: Network device. | |
6141 | * @regs: Ethtool registers data structure. | |
6142 | * @ptr: Buffer to store the register values. | |
6143 | * | |
6144 | * This procedure dumps the register values in the provided buffer. | |
6145 | */ | |
6146 | static void netdev_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
6147 | void *ptr) | |
6148 | { | |
6149 | struct dev_priv *priv = netdev_priv(dev); | |
6150 | struct dev_info *hw_priv = priv->adapter; | |
6151 | struct ksz_hw *hw = &hw_priv->hw; | |
6152 | int *buf = (int *) ptr; | |
6153 | struct hw_regs *range = hw_regs_range; | |
6154 | int len; | |
6155 | ||
6156 | mutex_lock(&hw_priv->lock); | |
6157 | regs->version = 0; | |
6158 | for (len = 0; len < 0x40; len += 4) { | |
6159 | pci_read_config_dword(hw_priv->pdev, len, buf); | |
6160 | buf++; | |
6161 | } | |
6162 | while (range->end > range->start) { | |
6163 | for (len = range->start; len < range->end; len += 4) { | |
6164 | *buf = readl(hw->io + len); | |
6165 | buf++; | |
6166 | } | |
6167 | range++; | |
6168 | } | |
6169 | mutex_unlock(&hw_priv->lock); | |
6170 | } | |
6171 | ||
6172 | #define WOL_SUPPORT \ | |
6173 | (WAKE_PHY | WAKE_MAGIC | \ | |
6174 | WAKE_UCAST | WAKE_MCAST | \ | |
6175 | WAKE_BCAST | WAKE_ARP) | |
6176 | ||
6177 | /** | |
6178 | * netdev_get_wol - get Wake-on-LAN support | |
6179 | * @dev: Network device. | |
6180 | * @wol: Ethtool Wake-on-LAN data structure. | |
6181 | * | |
6182 | * This procedure returns Wake-on-LAN support. | |
6183 | */ | |
6184 | static void netdev_get_wol(struct net_device *dev, | |
6185 | struct ethtool_wolinfo *wol) | |
6186 | { | |
6187 | struct dev_priv *priv = netdev_priv(dev); | |
6188 | struct dev_info *hw_priv = priv->adapter; | |
6189 | ||
6190 | wol->supported = hw_priv->wol_support; | |
6191 | wol->wolopts = hw_priv->wol_enable; | |
6192 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
6193 | } | |
6194 | ||
6195 | /** | |
6196 | * netdev_set_wol - set Wake-on-LAN support | |
6197 | * @dev: Network device. | |
6198 | * @wol: Ethtool Wake-on-LAN data structure. | |
6199 | * | |
6200 | * This function sets Wake-on-LAN support. | |
6201 | * | |
6202 | * Return 0 if successful; otherwise an error code. | |
6203 | */ | |
6204 | static int netdev_set_wol(struct net_device *dev, | |
6205 | struct ethtool_wolinfo *wol) | |
6206 | { | |
6207 | struct dev_priv *priv = netdev_priv(dev); | |
6208 | struct dev_info *hw_priv = priv->adapter; | |
6209 | ||
6210 | /* Need to find a way to retrieve the device IP address. */ | |
6211 | u8 net_addr[] = { 192, 168, 1, 1 }; | |
6212 | ||
6213 | if (wol->wolopts & ~hw_priv->wol_support) | |
6214 | return -EINVAL; | |
6215 | ||
6216 | hw_priv->wol_enable = wol->wolopts; | |
6217 | ||
6218 | /* Link wakeup cannot really be disabled. */ | |
6219 | if (wol->wolopts) | |
6220 | hw_priv->wol_enable |= WAKE_PHY; | |
6221 | hw_enable_wol(&hw_priv->hw, hw_priv->wol_enable, net_addr); | |
6222 | return 0; | |
6223 | } | |
6224 | ||
6225 | /** | |
6226 | * netdev_get_msglevel - get debug message level | |
6227 | * @dev: Network device. | |
6228 | * | |
6229 | * This function returns current debug message level. | |
6230 | * | |
6231 | * Return current debug message flags. | |
6232 | */ | |
6233 | static u32 netdev_get_msglevel(struct net_device *dev) | |
6234 | { | |
6235 | struct dev_priv *priv = netdev_priv(dev); | |
6236 | ||
6237 | return priv->msg_enable; | |
6238 | } | |
6239 | ||
6240 | /** | |
6241 | * netdev_set_msglevel - set debug message level | |
6242 | * @dev: Network device. | |
6243 | * @value: Debug message flags. | |
6244 | * | |
6245 | * This procedure sets debug message level. | |
6246 | */ | |
6247 | static void netdev_set_msglevel(struct net_device *dev, u32 value) | |
6248 | { | |
6249 | struct dev_priv *priv = netdev_priv(dev); | |
6250 | ||
6251 | priv->msg_enable = value; | |
6252 | } | |
6253 | ||
6254 | /** | |
6255 | * netdev_get_eeprom_len - get EEPROM length | |
6256 | * @dev: Network device. | |
6257 | * | |
6258 | * This function returns the length of the EEPROM. | |
6259 | * | |
6260 | * Return length of the EEPROM. | |
6261 | */ | |
6262 | static int netdev_get_eeprom_len(struct net_device *dev) | |
6263 | { | |
6264 | return EEPROM_SIZE * 2; | |
6265 | } | |
6266 | ||
6267 | /** | |
6268 | * netdev_get_eeprom - get EEPROM data | |
6269 | * @dev: Network device. | |
6270 | * @eeprom: Ethtool EEPROM data structure. | |
6271 | * @data: Buffer to store the EEPROM data. | |
6272 | * | |
6273 | * This function dumps the EEPROM data in the provided buffer. | |
6274 | * | |
6275 | * Return 0 if successful; otherwise an error code. | |
6276 | */ | |
6277 | #define EEPROM_MAGIC 0x10A18842 | |
6278 | ||
6279 | static int netdev_get_eeprom(struct net_device *dev, | |
6280 | struct ethtool_eeprom *eeprom, u8 *data) | |
6281 | { | |
6282 | struct dev_priv *priv = netdev_priv(dev); | |
6283 | struct dev_info *hw_priv = priv->adapter; | |
6284 | u8 *eeprom_byte = (u8 *) eeprom_data; | |
6285 | int i; | |
6286 | int len; | |
6287 | ||
6288 | len = (eeprom->offset + eeprom->len + 1) / 2; | |
6289 | for (i = eeprom->offset / 2; i < len; i++) | |
6290 | eeprom_data[i] = eeprom_read(&hw_priv->hw, i); | |
6291 | eeprom->magic = EEPROM_MAGIC; | |
6292 | memcpy(data, &eeprom_byte[eeprom->offset], eeprom->len); | |
6293 | ||
6294 | return 0; | |
6295 | } | |
6296 | ||
6297 | /** | |
6298 | * netdev_set_eeprom - write EEPROM data | |
6299 | * @dev: Network device. | |
6300 | * @eeprom: Ethtool EEPROM data structure. | |
6301 | * @data: Data buffer. | |
6302 | * | |
6303 | * This function modifies the EEPROM data one byte at a time. | |
6304 | * | |
6305 | * Return 0 if successful; otherwise an error code. | |
6306 | */ | |
6307 | static int netdev_set_eeprom(struct net_device *dev, | |
6308 | struct ethtool_eeprom *eeprom, u8 *data) | |
6309 | { | |
6310 | struct dev_priv *priv = netdev_priv(dev); | |
6311 | struct dev_info *hw_priv = priv->adapter; | |
6312 | u16 eeprom_word[EEPROM_SIZE]; | |
6313 | u8 *eeprom_byte = (u8 *) eeprom_word; | |
6314 | int i; | |
6315 | int len; | |
6316 | ||
6317 | if (eeprom->magic != EEPROM_MAGIC) | |
4881a4f8 | 6318 | return -EINVAL; |
8ca86fd8 TH |
6319 | |
6320 | len = (eeprom->offset + eeprom->len + 1) / 2; | |
6321 | for (i = eeprom->offset / 2; i < len; i++) | |
6322 | eeprom_data[i] = eeprom_read(&hw_priv->hw, i); | |
6323 | memcpy(eeprom_word, eeprom_data, EEPROM_SIZE * 2); | |
6324 | memcpy(&eeprom_byte[eeprom->offset], data, eeprom->len); | |
6325 | for (i = 0; i < EEPROM_SIZE; i++) | |
6326 | if (eeprom_word[i] != eeprom_data[i]) { | |
6327 | eeprom_data[i] = eeprom_word[i]; | |
6328 | eeprom_write(&hw_priv->hw, i, eeprom_data[i]); | |
6329 | } | |
6330 | ||
6331 | return 0; | |
6332 | } | |
6333 | ||
6334 | /** | |
6335 | * netdev_get_pauseparam - get flow control parameters | |
6336 | * @dev: Network device. | |
6337 | * @pause: Ethtool PAUSE settings data structure. | |
6338 | * | |
6339 | * This procedure returns the PAUSE control flow settings. | |
6340 | */ | |
6341 | static void netdev_get_pauseparam(struct net_device *dev, | |
6342 | struct ethtool_pauseparam *pause) | |
6343 | { | |
6344 | struct dev_priv *priv = netdev_priv(dev); | |
6345 | struct dev_info *hw_priv = priv->adapter; | |
6346 | struct ksz_hw *hw = &hw_priv->hw; | |
6347 | ||
6348 | pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1; | |
6349 | if (!hw->ksz_switch) { | |
6350 | pause->rx_pause = | |
6351 | (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0; | |
6352 | pause->tx_pause = | |
6353 | (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0; | |
6354 | } else { | |
6355 | pause->rx_pause = | |
6356 | (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET, | |
6357 | SWITCH_RX_FLOW_CTRL)) ? 1 : 0; | |
6358 | pause->tx_pause = | |
6359 | (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET, | |
6360 | SWITCH_TX_FLOW_CTRL)) ? 1 : 0; | |
6361 | } | |
6362 | } | |
6363 | ||
6364 | /** | |
6365 | * netdev_set_pauseparam - set flow control parameters | |
6366 | * @dev: Network device. | |
6367 | * @pause: Ethtool PAUSE settings data structure. | |
6368 | * | |
6369 | * This function sets the PAUSE control flow settings. | |
6370 | * Not implemented yet. | |
6371 | * | |
6372 | * Return 0 if successful; otherwise an error code. | |
6373 | */ | |
6374 | static int netdev_set_pauseparam(struct net_device *dev, | |
6375 | struct ethtool_pauseparam *pause) | |
6376 | { | |
6377 | struct dev_priv *priv = netdev_priv(dev); | |
6378 | struct dev_info *hw_priv = priv->adapter; | |
6379 | struct ksz_hw *hw = &hw_priv->hw; | |
6380 | struct ksz_port *port = &priv->port; | |
6381 | ||
6382 | mutex_lock(&hw_priv->lock); | |
6383 | if (pause->autoneg) { | |
6384 | if (!pause->rx_pause && !pause->tx_pause) | |
6385 | port->flow_ctrl = PHY_NO_FLOW_CTRL; | |
6386 | else | |
6387 | port->flow_ctrl = PHY_FLOW_CTRL; | |
6388 | hw->overrides &= ~PAUSE_FLOW_CTRL; | |
6389 | port->force_link = 0; | |
6390 | if (hw->ksz_switch) { | |
6391 | sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, | |
6392 | SWITCH_RX_FLOW_CTRL, 1); | |
6393 | sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, | |
6394 | SWITCH_TX_FLOW_CTRL, 1); | |
6395 | } | |
6396 | port_set_link_speed(port); | |
6397 | } else { | |
6398 | hw->overrides |= PAUSE_FLOW_CTRL; | |
6399 | if (hw->ksz_switch) { | |
6400 | sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, | |
6401 | SWITCH_RX_FLOW_CTRL, pause->rx_pause); | |
6402 | sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, | |
6403 | SWITCH_TX_FLOW_CTRL, pause->tx_pause); | |
6404 | } else | |
6405 | set_flow_ctrl(hw, pause->rx_pause, pause->tx_pause); | |
6406 | } | |
6407 | mutex_unlock(&hw_priv->lock); | |
6408 | ||
6409 | return 0; | |
6410 | } | |
6411 | ||
6412 | /** | |
6413 | * netdev_get_ringparam - get tx/rx ring parameters | |
6414 | * @dev: Network device. | |
6415 | * @pause: Ethtool RING settings data structure. | |
6416 | * | |
6417 | * This procedure returns the TX/RX ring settings. | |
6418 | */ | |
6419 | static void netdev_get_ringparam(struct net_device *dev, | |
6420 | struct ethtool_ringparam *ring) | |
6421 | { | |
6422 | struct dev_priv *priv = netdev_priv(dev); | |
6423 | struct dev_info *hw_priv = priv->adapter; | |
6424 | struct ksz_hw *hw = &hw_priv->hw; | |
6425 | ||
6426 | ring->tx_max_pending = (1 << 9); | |
6427 | ring->tx_pending = hw->tx_desc_info.alloc; | |
6428 | ring->rx_max_pending = (1 << 9); | |
6429 | ring->rx_pending = hw->rx_desc_info.alloc; | |
6430 | } | |
6431 | ||
6432 | #define STATS_LEN (TOTAL_PORT_COUNTER_NUM) | |
6433 | ||
6434 | static struct { | |
6435 | char string[ETH_GSTRING_LEN]; | |
6436 | } ethtool_stats_keys[STATS_LEN] = { | |
6437 | { "rx_lo_priority_octets" }, | |
6438 | { "rx_hi_priority_octets" }, | |
6439 | { "rx_undersize_packets" }, | |
6440 | { "rx_fragments" }, | |
6441 | { "rx_oversize_packets" }, | |
6442 | { "rx_jabbers" }, | |
6443 | { "rx_symbol_errors" }, | |
6444 | { "rx_crc_errors" }, | |
6445 | { "rx_align_errors" }, | |
6446 | { "rx_mac_ctrl_packets" }, | |
6447 | { "rx_pause_packets" }, | |
6448 | { "rx_bcast_packets" }, | |
6449 | { "rx_mcast_packets" }, | |
6450 | { "rx_ucast_packets" }, | |
6451 | { "rx_64_or_less_octet_packets" }, | |
6452 | { "rx_65_to_127_octet_packets" }, | |
6453 | { "rx_128_to_255_octet_packets" }, | |
6454 | { "rx_256_to_511_octet_packets" }, | |
6455 | { "rx_512_to_1023_octet_packets" }, | |
6456 | { "rx_1024_to_1522_octet_packets" }, | |
6457 | ||
6458 | { "tx_lo_priority_octets" }, | |
6459 | { "tx_hi_priority_octets" }, | |
6460 | { "tx_late_collisions" }, | |
6461 | { "tx_pause_packets" }, | |
6462 | { "tx_bcast_packets" }, | |
6463 | { "tx_mcast_packets" }, | |
6464 | { "tx_ucast_packets" }, | |
6465 | { "tx_deferred" }, | |
6466 | { "tx_total_collisions" }, | |
6467 | { "tx_excessive_collisions" }, | |
6468 | { "tx_single_collisions" }, | |
6469 | { "tx_mult_collisions" }, | |
6470 | ||
6471 | { "rx_discards" }, | |
6472 | { "tx_discards" }, | |
6473 | }; | |
6474 | ||
6475 | /** | |
6476 | * netdev_get_strings - get statistics identity strings | |
6477 | * @dev: Network device. | |
6478 | * @stringset: String set identifier. | |
6479 | * @buf: Buffer to store the strings. | |
6480 | * | |
6481 | * This procedure returns the strings used to identify the statistics. | |
6482 | */ | |
6483 | static void netdev_get_strings(struct net_device *dev, u32 stringset, u8 *buf) | |
6484 | { | |
6485 | struct dev_priv *priv = netdev_priv(dev); | |
6486 | struct dev_info *hw_priv = priv->adapter; | |
6487 | struct ksz_hw *hw = &hw_priv->hw; | |
6488 | ||
6489 | if (ETH_SS_STATS == stringset) | |
6490 | memcpy(buf, ðtool_stats_keys, | |
6491 | ETH_GSTRING_LEN * hw->mib_cnt); | |
6492 | } | |
6493 | ||
6494 | /** | |
6495 | * netdev_get_sset_count - get statistics size | |
6496 | * @dev: Network device. | |
6497 | * @sset: The statistics set number. | |
6498 | * | |
6499 | * This function returns the size of the statistics to be reported. | |
6500 | * | |
6501 | * Return size of the statistics to be reported. | |
6502 | */ | |
6503 | static int netdev_get_sset_count(struct net_device *dev, int sset) | |
6504 | { | |
6505 | struct dev_priv *priv = netdev_priv(dev); | |
6506 | struct dev_info *hw_priv = priv->adapter; | |
6507 | struct ksz_hw *hw = &hw_priv->hw; | |
6508 | ||
6509 | switch (sset) { | |
6510 | case ETH_SS_STATS: | |
6511 | return hw->mib_cnt; | |
6512 | default: | |
6513 | return -EOPNOTSUPP; | |
6514 | } | |
6515 | } | |
6516 | ||
6517 | /** | |
6518 | * netdev_get_ethtool_stats - get network device statistics | |
6519 | * @dev: Network device. | |
6520 | * @stats: Ethtool statistics data structure. | |
6521 | * @data: Buffer to store the statistics. | |
6522 | * | |
6523 | * This procedure returns the statistics. | |
6524 | */ | |
6525 | static void netdev_get_ethtool_stats(struct net_device *dev, | |
6526 | struct ethtool_stats *stats, u64 *data) | |
6527 | { | |
6528 | struct dev_priv *priv = netdev_priv(dev); | |
6529 | struct dev_info *hw_priv = priv->adapter; | |
6530 | struct ksz_hw *hw = &hw_priv->hw; | |
6531 | struct ksz_port *port = &priv->port; | |
6532 | int n_stats = stats->n_stats; | |
6533 | int i; | |
6534 | int n; | |
6535 | int p; | |
6536 | int rc; | |
6537 | u64 counter[TOTAL_PORT_COUNTER_NUM]; | |
6538 | ||
6539 | mutex_lock(&hw_priv->lock); | |
6540 | n = SWITCH_PORT_NUM; | |
6541 | for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) { | |
6542 | if (media_connected == hw->port_mib[p].state) { | |
6543 | hw_priv->counter[p].read = 1; | |
6544 | ||
6545 | /* Remember first port that requests read. */ | |
6546 | if (n == SWITCH_PORT_NUM) | |
6547 | n = p; | |
6548 | } | |
6549 | } | |
6550 | mutex_unlock(&hw_priv->lock); | |
6551 | ||
6552 | if (n < SWITCH_PORT_NUM) | |
6553 | schedule_work(&hw_priv->mib_read); | |
6554 | ||
6555 | if (1 == port->mib_port_cnt && n < SWITCH_PORT_NUM) { | |
6556 | p = n; | |
6557 | rc = wait_event_interruptible_timeout( | |
6558 | hw_priv->counter[p].counter, | |
6559 | 2 == hw_priv->counter[p].read, | |
6560 | HZ * 1); | |
6561 | } else | |
6562 | for (i = 0, p = n; i < port->mib_port_cnt - n; i++, p++) { | |
6563 | if (0 == i) { | |
6564 | rc = wait_event_interruptible_timeout( | |
6565 | hw_priv->counter[p].counter, | |
6566 | 2 == hw_priv->counter[p].read, | |
6567 | HZ * 2); | |
6568 | } else if (hw->port_mib[p].cnt_ptr) { | |
6569 | rc = wait_event_interruptible_timeout( | |
6570 | hw_priv->counter[p].counter, | |
6571 | 2 == hw_priv->counter[p].read, | |
6572 | HZ * 1); | |
6573 | } | |
6574 | } | |
6575 | ||
6576 | get_mib_counters(hw, port->first_port, port->mib_port_cnt, counter); | |
6577 | n = hw->mib_cnt; | |
6578 | if (n > n_stats) | |
6579 | n = n_stats; | |
6580 | n_stats -= n; | |
6581 | for (i = 0; i < n; i++) | |
6582 | *data++ = counter[i]; | |
6583 | } | |
6584 | ||
6585 | /** | |
6586 | * netdev_get_rx_csum - get receive checksum support | |
6587 | * @dev: Network device. | |
6588 | * | |
6589 | * This function gets receive checksum support setting. | |
6590 | * | |
6591 | * Return true if receive checksum is enabled; false otherwise. | |
6592 | */ | |
6593 | static u32 netdev_get_rx_csum(struct net_device *dev) | |
6594 | { | |
6595 | struct dev_priv *priv = netdev_priv(dev); | |
6596 | struct dev_info *hw_priv = priv->adapter; | |
6597 | struct ksz_hw *hw = &hw_priv->hw; | |
6598 | ||
6599 | return hw->rx_cfg & | |
6600 | (DMA_RX_CSUM_UDP | | |
6601 | DMA_RX_CSUM_TCP | | |
6602 | DMA_RX_CSUM_IP); | |
6603 | } | |
6604 | ||
6605 | /** | |
6606 | * netdev_set_rx_csum - set receive checksum support | |
6607 | * @dev: Network device. | |
6608 | * @data: Zero to disable receive checksum support. | |
6609 | * | |
6610 | * This function sets receive checksum support setting. | |
6611 | * | |
6612 | * Return 0 if successful; otherwise an error code. | |
6613 | */ | |
6614 | static int netdev_set_rx_csum(struct net_device *dev, u32 data) | |
6615 | { | |
6616 | struct dev_priv *priv = netdev_priv(dev); | |
6617 | struct dev_info *hw_priv = priv->adapter; | |
6618 | struct ksz_hw *hw = &hw_priv->hw; | |
6619 | u32 new_setting = hw->rx_cfg; | |
6620 | ||
6621 | if (data) | |
6622 | new_setting |= | |
6623 | (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP | | |
6624 | DMA_RX_CSUM_IP); | |
6625 | else | |
6626 | new_setting &= | |
6627 | ~(DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP | | |
6628 | DMA_RX_CSUM_IP); | |
6629 | new_setting &= ~DMA_RX_CSUM_UDP; | |
6630 | mutex_lock(&hw_priv->lock); | |
6631 | if (new_setting != hw->rx_cfg) { | |
6632 | hw->rx_cfg = new_setting; | |
6633 | if (hw->enabled) | |
6634 | writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL); | |
6635 | } | |
6636 | mutex_unlock(&hw_priv->lock); | |
6637 | return 0; | |
6638 | } | |
6639 | ||
6640 | static struct ethtool_ops netdev_ethtool_ops = { | |
6641 | .get_settings = netdev_get_settings, | |
6642 | .set_settings = netdev_set_settings, | |
6643 | .nway_reset = netdev_nway_reset, | |
6644 | .get_link = netdev_get_link, | |
6645 | .get_drvinfo = netdev_get_drvinfo, | |
6646 | .get_regs_len = netdev_get_regs_len, | |
6647 | .get_regs = netdev_get_regs, | |
6648 | .get_wol = netdev_get_wol, | |
6649 | .set_wol = netdev_set_wol, | |
6650 | .get_msglevel = netdev_get_msglevel, | |
6651 | .set_msglevel = netdev_set_msglevel, | |
6652 | .get_eeprom_len = netdev_get_eeprom_len, | |
6653 | .get_eeprom = netdev_get_eeprom, | |
6654 | .set_eeprom = netdev_set_eeprom, | |
6655 | .get_pauseparam = netdev_get_pauseparam, | |
6656 | .set_pauseparam = netdev_set_pauseparam, | |
6657 | .get_ringparam = netdev_get_ringparam, | |
6658 | .get_strings = netdev_get_strings, | |
6659 | .get_sset_count = netdev_get_sset_count, | |
6660 | .get_ethtool_stats = netdev_get_ethtool_stats, | |
6661 | .get_rx_csum = netdev_get_rx_csum, | |
6662 | .set_rx_csum = netdev_set_rx_csum, | |
6663 | .get_tx_csum = ethtool_op_get_tx_csum, | |
6664 | .set_tx_csum = ethtool_op_set_tx_csum, | |
6665 | .get_sg = ethtool_op_get_sg, | |
6666 | .set_sg = ethtool_op_set_sg, | |
6667 | }; | |
6668 | ||
6669 | /* | |
6670 | * Hardware monitoring | |
6671 | */ | |
6672 | ||
6673 | static void update_link(struct net_device *dev, struct dev_priv *priv, | |
6674 | struct ksz_port *port) | |
6675 | { | |
6676 | if (priv->media_state != port->linked->state) { | |
6677 | priv->media_state = port->linked->state; | |
0dc7d2b3 JP |
6678 | if (netif_running(dev)) |
6679 | set_media_state(dev, media_connected); | |
8ca86fd8 TH |
6680 | } |
6681 | } | |
6682 | ||
6683 | static void mib_read_work(struct work_struct *work) | |
6684 | { | |
6685 | struct dev_info *hw_priv = | |
6686 | container_of(work, struct dev_info, mib_read); | |
6687 | struct ksz_hw *hw = &hw_priv->hw; | |
6688 | struct ksz_port_mib *mib; | |
6689 | int i; | |
6690 | ||
6691 | next_jiffies = jiffies; | |
6692 | for (i = 0; i < hw->mib_port_cnt; i++) { | |
6693 | mib = &hw->port_mib[i]; | |
6694 | ||
6695 | /* Reading MIB counters or requested to read. */ | |
6696 | if (mib->cnt_ptr || 1 == hw_priv->counter[i].read) { | |
6697 | ||
6698 | /* Need to process receive interrupt. */ | |
6699 | if (port_r_cnt(hw, i)) | |
6700 | break; | |
6701 | hw_priv->counter[i].read = 0; | |
6702 | ||
6703 | /* Finish reading counters. */ | |
6704 | if (0 == mib->cnt_ptr) { | |
6705 | hw_priv->counter[i].read = 2; | |
6706 | wake_up_interruptible( | |
6707 | &hw_priv->counter[i].counter); | |
6708 | } | |
6709 | } else if (jiffies >= hw_priv->counter[i].time) { | |
6710 | /* Only read MIB counters when the port is connected. */ | |
6711 | if (media_connected == mib->state) | |
6712 | hw_priv->counter[i].read = 1; | |
6713 | next_jiffies += HZ * 1 * hw->mib_port_cnt; | |
6714 | hw_priv->counter[i].time = next_jiffies; | |
6715 | ||
6716 | /* Port is just disconnected. */ | |
6717 | } else if (mib->link_down) { | |
6718 | mib->link_down = 0; | |
6719 | ||
6720 | /* Read counters one last time after link is lost. */ | |
6721 | hw_priv->counter[i].read = 1; | |
6722 | } | |
6723 | } | |
6724 | } | |
6725 | ||
6726 | static void mib_monitor(unsigned long ptr) | |
6727 | { | |
6728 | struct dev_info *hw_priv = (struct dev_info *) ptr; | |
6729 | ||
6730 | mib_read_work(&hw_priv->mib_read); | |
6731 | ||
6732 | /* This is used to verify Wake-on-LAN is working. */ | |
6733 | if (hw_priv->pme_wait) { | |
6734 | if (hw_priv->pme_wait <= jiffies) { | |
6735 | hw_clr_wol_pme_status(&hw_priv->hw); | |
6736 | hw_priv->pme_wait = 0; | |
6737 | } | |
6738 | } else if (hw_chk_wol_pme_status(&hw_priv->hw)) { | |
6739 | ||
6740 | /* PME is asserted. Wait 2 seconds to clear it. */ | |
6741 | hw_priv->pme_wait = jiffies + HZ * 2; | |
6742 | } | |
6743 | ||
6744 | ksz_update_timer(&hw_priv->mib_timer_info); | |
6745 | } | |
6746 | ||
6747 | /** | |
6748 | * dev_monitor - periodic monitoring | |
6749 | * @ptr: Network device pointer. | |
6750 | * | |
6751 | * This routine is run in a kernel timer to monitor the network device. | |
6752 | */ | |
6753 | static void dev_monitor(unsigned long ptr) | |
6754 | { | |
6755 | struct net_device *dev = (struct net_device *) ptr; | |
6756 | struct dev_priv *priv = netdev_priv(dev); | |
6757 | struct dev_info *hw_priv = priv->adapter; | |
6758 | struct ksz_hw *hw = &hw_priv->hw; | |
6759 | struct ksz_port *port = &priv->port; | |
6760 | ||
6761 | if (!(hw->features & LINK_INT_WORKING)) | |
6762 | port_get_link_speed(port); | |
6763 | update_link(dev, priv, port); | |
6764 | ||
6765 | ksz_update_timer(&priv->monitor_timer_info); | |
6766 | } | |
6767 | ||
6768 | /* | |
6769 | * Linux network device interface functions | |
6770 | */ | |
6771 | ||
6772 | /* Driver exported variables */ | |
6773 | ||
6774 | static int msg_enable; | |
6775 | ||
6776 | static char *macaddr = ":"; | |
6777 | static char *mac1addr = ":"; | |
6778 | ||
6779 | /* | |
6780 | * This enables multiple network device mode for KSZ8842, which contains a | |
6781 | * switch with two physical ports. Some users like to take control of the | |
6782 | * ports for running Spanning Tree Protocol. The driver will create an | |
6783 | * additional eth? device for the other port. | |
6784 | * | |
6785 | * Some limitations are the network devices cannot have different MTU and | |
6786 | * multicast hash tables. | |
6787 | */ | |
6788 | static int multi_dev; | |
6789 | ||
6790 | /* | |
6791 | * As most users select multiple network device mode to use Spanning Tree | |
6792 | * Protocol, this enables a feature in which most unicast and multicast packets | |
6793 | * are forwarded inside the switch and not passed to the host. Only packets | |
6794 | * that need the host's attention are passed to it. This prevents the host | |
6795 | * wasting CPU time to examine each and every incoming packets and do the | |
6796 | * forwarding itself. | |
6797 | * | |
6798 | * As the hack requires the private bridge header, the driver cannot compile | |
6799 | * with just the kernel headers. | |
6800 | * | |
6801 | * Enabling STP support also turns on multiple network device mode. | |
6802 | */ | |
6803 | static int stp; | |
6804 | ||
6805 | /* | |
6806 | * This enables fast aging in the KSZ8842 switch. Not sure what situation | |
6807 | * needs that. However, fast aging is used to flush the dynamic MAC table when | |
6808 | * STP suport is enabled. | |
6809 | */ | |
6810 | static int fast_aging; | |
6811 | ||
6812 | /** | |
421f91d2 | 6813 | * netdev_init - initialize network device. |
8ca86fd8 TH |
6814 | * @dev: Network device. |
6815 | * | |
6816 | * This function initializes the network device. | |
6817 | * | |
6818 | * Return 0 if successful; otherwise an error code indicating failure. | |
6819 | */ | |
6820 | static int __init netdev_init(struct net_device *dev) | |
6821 | { | |
6822 | struct dev_priv *priv = netdev_priv(dev); | |
6823 | ||
6824 | /* 500 ms timeout */ | |
6825 | ksz_init_timer(&priv->monitor_timer_info, 500 * HZ / 1000, | |
6826 | dev_monitor, dev); | |
6827 | ||
6828 | /* 500 ms timeout */ | |
6829 | dev->watchdog_timeo = HZ / 2; | |
6830 | ||
6831 | dev->features |= NETIF_F_IP_CSUM; | |
6832 | ||
6833 | /* | |
6834 | * Hardware does not really support IPv6 checksum generation, but | |
6835 | * driver actually runs faster with this on. Refer IPV6_CSUM_GEN_HACK. | |
6836 | */ | |
6837 | dev->features |= NETIF_F_IPV6_CSUM; | |
6838 | dev->features |= NETIF_F_SG; | |
6839 | ||
6840 | sema_init(&priv->proc_sem, 1); | |
6841 | ||
6842 | priv->mii_if.phy_id_mask = 0x1; | |
6843 | priv->mii_if.reg_num_mask = 0x7; | |
6844 | priv->mii_if.dev = dev; | |
6845 | priv->mii_if.mdio_read = mdio_read; | |
6846 | priv->mii_if.mdio_write = mdio_write; | |
6847 | priv->mii_if.phy_id = priv->port.first_port + 1; | |
6848 | ||
6849 | priv->msg_enable = netif_msg_init(msg_enable, | |
6850 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)); | |
6851 | ||
6852 | return 0; | |
6853 | } | |
6854 | ||
6855 | static const struct net_device_ops netdev_ops = { | |
6856 | .ndo_init = netdev_init, | |
6857 | .ndo_open = netdev_open, | |
6858 | .ndo_stop = netdev_close, | |
6859 | .ndo_get_stats = netdev_query_statistics, | |
6860 | .ndo_start_xmit = netdev_tx, | |
6861 | .ndo_tx_timeout = netdev_tx_timeout, | |
6862 | .ndo_change_mtu = netdev_change_mtu, | |
6863 | .ndo_set_mac_address = netdev_set_mac_address, | |
96ed741e | 6864 | .ndo_validate_addr = eth_validate_addr, |
8ca86fd8 TH |
6865 | .ndo_do_ioctl = netdev_ioctl, |
6866 | .ndo_set_rx_mode = netdev_set_rx_mode, | |
6867 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
6868 | .ndo_poll_controller = netdev_netpoll, | |
6869 | #endif | |
6870 | }; | |
6871 | ||
6872 | static void netdev_free(struct net_device *dev) | |
6873 | { | |
6874 | if (dev->watchdog_timeo) | |
6875 | unregister_netdev(dev); | |
6876 | ||
6877 | free_netdev(dev); | |
6878 | } | |
6879 | ||
6880 | struct platform_info { | |
6881 | struct dev_info dev_info; | |
6882 | struct net_device *netdev[SWITCH_PORT_NUM]; | |
6883 | }; | |
6884 | ||
6885 | static int net_device_present; | |
6886 | ||
6887 | static void get_mac_addr(struct dev_info *hw_priv, u8 *macaddr, int port) | |
6888 | { | |
6889 | int i; | |
6890 | int j; | |
6891 | int got_num; | |
6892 | int num; | |
6893 | ||
6894 | i = j = num = got_num = 0; | |
6895 | while (j < MAC_ADDR_LEN) { | |
6896 | if (macaddr[i]) { | |
5c4ac8c6 AS |
6897 | int digit; |
6898 | ||
8ca86fd8 | 6899 | got_num = 1; |
5c4ac8c6 AS |
6900 | digit = hex_to_bin(macaddr[i]); |
6901 | if (digit >= 0) | |
6902 | num = num * 16 + digit; | |
8ca86fd8 TH |
6903 | else if (':' == macaddr[i]) |
6904 | got_num = 2; | |
6905 | else | |
6906 | break; | |
6907 | } else if (got_num) | |
6908 | got_num = 2; | |
6909 | else | |
6910 | break; | |
6911 | if (2 == got_num) { | |
6912 | if (MAIN_PORT == port) { | |
6913 | hw_priv->hw.override_addr[j++] = (u8) num; | |
6914 | hw_priv->hw.override_addr[5] += | |
6915 | hw_priv->hw.id; | |
6916 | } else { | |
6917 | hw_priv->hw.ksz_switch->other_addr[j++] = | |
6918 | (u8) num; | |
6919 | hw_priv->hw.ksz_switch->other_addr[5] += | |
6920 | hw_priv->hw.id; | |
6921 | } | |
6922 | num = got_num = 0; | |
6923 | } | |
6924 | i++; | |
6925 | } | |
6926 | if (MAC_ADDR_LEN == j) { | |
6927 | if (MAIN_PORT == port) | |
6928 | hw_priv->hw.mac_override = 1; | |
6929 | } | |
6930 | } | |
6931 | ||
6932 | #define KS884X_DMA_MASK (~0x0UL) | |
6933 | ||
6934 | static void read_other_addr(struct ksz_hw *hw) | |
6935 | { | |
6936 | int i; | |
6937 | u16 data[3]; | |
6938 | struct ksz_switch *sw = hw->ksz_switch; | |
6939 | ||
6940 | for (i = 0; i < 3; i++) | |
6941 | data[i] = eeprom_read(hw, i + EEPROM_DATA_OTHER_MAC_ADDR); | |
6942 | if ((data[0] || data[1] || data[2]) && data[0] != 0xffff) { | |
6943 | sw->other_addr[5] = (u8) data[0]; | |
6944 | sw->other_addr[4] = (u8)(data[0] >> 8); | |
6945 | sw->other_addr[3] = (u8) data[1]; | |
6946 | sw->other_addr[2] = (u8)(data[1] >> 8); | |
6947 | sw->other_addr[1] = (u8) data[2]; | |
6948 | sw->other_addr[0] = (u8)(data[2] >> 8); | |
6949 | } | |
6950 | } | |
6951 | ||
6952 | #ifndef PCI_VENDOR_ID_MICREL_KS | |
6953 | #define PCI_VENDOR_ID_MICREL_KS 0x16c6 | |
6954 | #endif | |
6955 | ||
6956 | static int __init pcidev_init(struct pci_dev *pdev, | |
6957 | const struct pci_device_id *id) | |
6958 | { | |
6959 | struct net_device *dev; | |
6960 | struct dev_priv *priv; | |
6961 | struct dev_info *hw_priv; | |
6962 | struct ksz_hw *hw; | |
6963 | struct platform_info *info; | |
6964 | struct ksz_port *port; | |
6965 | unsigned long reg_base; | |
6966 | unsigned long reg_len; | |
6967 | int cnt; | |
6968 | int i; | |
6969 | int mib_port_count; | |
6970 | int pi; | |
6971 | int port_count; | |
6972 | int result; | |
0dc7d2b3 | 6973 | char banner[sizeof(version)]; |
8ca86fd8 TH |
6974 | struct ksz_switch *sw = NULL; |
6975 | ||
6976 | result = pci_enable_device(pdev); | |
6977 | if (result) | |
6978 | return result; | |
6979 | ||
6980 | result = -ENODEV; | |
6981 | ||
6982 | if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) || | |
6983 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) | |
6984 | return result; | |
6985 | ||
6986 | reg_base = pci_resource_start(pdev, 0); | |
6987 | reg_len = pci_resource_len(pdev, 0); | |
6988 | if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) | |
6989 | return result; | |
6990 | ||
6991 | if (!request_mem_region(reg_base, reg_len, DRV_NAME)) | |
6992 | return result; | |
6993 | pci_set_master(pdev); | |
6994 | ||
6995 | result = -ENOMEM; | |
6996 | ||
0dc7d2b3 | 6997 | info = kzalloc(sizeof(struct platform_info), GFP_KERNEL); |
8ca86fd8 TH |
6998 | if (!info) |
6999 | goto pcidev_init_dev_err; | |
8ca86fd8 TH |
7000 | |
7001 | hw_priv = &info->dev_info; | |
7002 | hw_priv->pdev = pdev; | |
7003 | ||
7004 | hw = &hw_priv->hw; | |
7005 | ||
7006 | hw->io = ioremap(reg_base, reg_len); | |
7007 | if (!hw->io) | |
7008 | goto pcidev_init_io_err; | |
7009 | ||
7010 | cnt = hw_init(hw); | |
7011 | if (!cnt) { | |
7012 | if (msg_enable & NETIF_MSG_PROBE) | |
0dc7d2b3 | 7013 | pr_alert("chip not detected\n"); |
8ca86fd8 TH |
7014 | result = -ENODEV; |
7015 | goto pcidev_init_alloc_err; | |
7016 | } | |
7017 | ||
0dc7d2b3 JP |
7018 | snprintf(banner, sizeof(banner), "%s", version); |
7019 | banner[13] = cnt + '0'; /* Replace x in "Micrel KSZ884x" */ | |
7020 | dev_info(&hw_priv->pdev->dev, "%s\n", banner); | |
7021 | dev_dbg(&hw_priv->pdev->dev, "Mem = %p; IRQ = %d\n", hw->io, pdev->irq); | |
8ca86fd8 TH |
7022 | |
7023 | /* Assume device is KSZ8841. */ | |
7024 | hw->dev_count = 1; | |
7025 | port_count = 1; | |
7026 | mib_port_count = 1; | |
7027 | hw->addr_list_size = 0; | |
7028 | hw->mib_cnt = PORT_COUNTER_NUM; | |
7029 | hw->mib_port_cnt = 1; | |
7030 | ||
7031 | /* KSZ8842 has a switch with multiple ports. */ | |
7032 | if (2 == cnt) { | |
7033 | if (fast_aging) | |
7034 | hw->overrides |= FAST_AGING; | |
7035 | ||
7036 | hw->mib_cnt = TOTAL_PORT_COUNTER_NUM; | |
7037 | ||
7038 | /* Multiple network device interfaces are required. */ | |
7039 | if (multi_dev) { | |
7040 | hw->dev_count = SWITCH_PORT_NUM; | |
7041 | hw->addr_list_size = SWITCH_PORT_NUM - 1; | |
7042 | } | |
7043 | ||
7044 | /* Single network device has multiple ports. */ | |
7045 | if (1 == hw->dev_count) { | |
7046 | port_count = SWITCH_PORT_NUM; | |
7047 | mib_port_count = SWITCH_PORT_NUM; | |
7048 | } | |
7049 | hw->mib_port_cnt = TOTAL_PORT_NUM; | |
a05abcb5 | 7050 | hw->ksz_switch = kzalloc(sizeof(struct ksz_switch), GFP_KERNEL); |
8ca86fd8 TH |
7051 | if (!hw->ksz_switch) |
7052 | goto pcidev_init_alloc_err; | |
8ca86fd8 TH |
7053 | |
7054 | sw = hw->ksz_switch; | |
7055 | } | |
7056 | for (i = 0; i < hw->mib_port_cnt; i++) | |
7057 | hw->port_mib[i].mib_start = 0; | |
7058 | ||
7059 | hw->parent = hw_priv; | |
7060 | ||
7061 | /* Default MTU is 1500. */ | |
7062 | hw_priv->mtu = (REGULAR_RX_BUF_SIZE + 3) & ~3; | |
7063 | ||
7064 | if (ksz_alloc_mem(hw_priv)) | |
7065 | goto pcidev_init_mem_err; | |
7066 | ||
7067 | hw_priv->hw.id = net_device_present; | |
7068 | ||
7069 | spin_lock_init(&hw_priv->hwlock); | |
7070 | mutex_init(&hw_priv->lock); | |
7071 | ||
7072 | /* tasklet is enabled. */ | |
7073 | tasklet_init(&hw_priv->rx_tasklet, rx_proc_task, | |
7074 | (unsigned long) hw_priv); | |
7075 | tasklet_init(&hw_priv->tx_tasklet, tx_proc_task, | |
7076 | (unsigned long) hw_priv); | |
7077 | ||
7078 | /* tasklet_enable will decrement the atomic counter. */ | |
7079 | tasklet_disable(&hw_priv->rx_tasklet); | |
7080 | tasklet_disable(&hw_priv->tx_tasklet); | |
7081 | ||
7082 | for (i = 0; i < TOTAL_PORT_NUM; i++) | |
7083 | init_waitqueue_head(&hw_priv->counter[i].counter); | |
7084 | ||
7085 | if (macaddr[0] != ':') | |
7086 | get_mac_addr(hw_priv, macaddr, MAIN_PORT); | |
7087 | ||
7088 | /* Read MAC address and initialize override address if not overrided. */ | |
7089 | hw_read_addr(hw); | |
7090 | ||
7091 | /* Multiple device interfaces mode requires a second MAC address. */ | |
7092 | if (hw->dev_count > 1) { | |
7093 | memcpy(sw->other_addr, hw->override_addr, MAC_ADDR_LEN); | |
7094 | read_other_addr(hw); | |
7095 | if (mac1addr[0] != ':') | |
7096 | get_mac_addr(hw_priv, mac1addr, OTHER_PORT); | |
7097 | } | |
7098 | ||
7099 | hw_setup(hw); | |
7100 | if (hw->ksz_switch) | |
7101 | sw_setup(hw); | |
7102 | else { | |
7103 | hw_priv->wol_support = WOL_SUPPORT; | |
7104 | hw_priv->wol_enable = 0; | |
7105 | } | |
7106 | ||
7107 | INIT_WORK(&hw_priv->mib_read, mib_read_work); | |
7108 | ||
7109 | /* 500 ms timeout */ | |
7110 | ksz_init_timer(&hw_priv->mib_timer_info, 500 * HZ / 1000, | |
7111 | mib_monitor, hw_priv); | |
7112 | ||
7113 | for (i = 0; i < hw->dev_count; i++) { | |
7114 | dev = alloc_etherdev(sizeof(struct dev_priv)); | |
7115 | if (!dev) | |
7116 | goto pcidev_init_reg_err; | |
7117 | info->netdev[i] = dev; | |
7118 | ||
7119 | priv = netdev_priv(dev); | |
7120 | priv->adapter = hw_priv; | |
7121 | priv->id = net_device_present++; | |
7122 | ||
7123 | port = &priv->port; | |
7124 | port->port_cnt = port_count; | |
7125 | port->mib_port_cnt = mib_port_count; | |
7126 | port->first_port = i; | |
7127 | port->flow_ctrl = PHY_FLOW_CTRL; | |
7128 | ||
7129 | port->hw = hw; | |
7130 | port->linked = &hw->port_info[port->first_port]; | |
7131 | ||
7132 | for (cnt = 0, pi = i; cnt < port_count; cnt++, pi++) { | |
7133 | hw->port_info[pi].port_id = pi; | |
7134 | hw->port_info[pi].pdev = dev; | |
7135 | hw->port_info[pi].state = media_disconnected; | |
7136 | } | |
7137 | ||
7138 | dev->mem_start = (unsigned long) hw->io; | |
7139 | dev->mem_end = dev->mem_start + reg_len - 1; | |
7140 | dev->irq = pdev->irq; | |
7141 | if (MAIN_PORT == i) | |
7142 | memcpy(dev->dev_addr, hw_priv->hw.override_addr, | |
7143 | MAC_ADDR_LEN); | |
7144 | else { | |
7145 | memcpy(dev->dev_addr, sw->other_addr, | |
7146 | MAC_ADDR_LEN); | |
7147 | if (!memcmp(sw->other_addr, hw->override_addr, | |
7148 | MAC_ADDR_LEN)) | |
7149 | dev->dev_addr[5] += port->first_port; | |
7150 | } | |
7151 | ||
7152 | dev->netdev_ops = &netdev_ops; | |
7153 | SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops); | |
7154 | if (register_netdev(dev)) | |
7155 | goto pcidev_init_reg_err; | |
7156 | port_set_power_saving(port, true); | |
7157 | } | |
7158 | ||
7159 | pci_dev_get(hw_priv->pdev); | |
7160 | pci_set_drvdata(pdev, info); | |
7161 | return 0; | |
7162 | ||
7163 | pcidev_init_reg_err: | |
7164 | for (i = 0; i < hw->dev_count; i++) { | |
7165 | if (info->netdev[i]) { | |
7166 | netdev_free(info->netdev[i]); | |
7167 | info->netdev[i] = NULL; | |
7168 | } | |
7169 | } | |
7170 | ||
7171 | pcidev_init_mem_err: | |
7172 | ksz_free_mem(hw_priv); | |
7173 | kfree(hw->ksz_switch); | |
7174 | ||
7175 | pcidev_init_alloc_err: | |
7176 | iounmap(hw->io); | |
7177 | ||
7178 | pcidev_init_io_err: | |
7179 | kfree(info); | |
7180 | ||
7181 | pcidev_init_dev_err: | |
7182 | release_mem_region(reg_base, reg_len); | |
7183 | ||
7184 | return result; | |
7185 | } | |
7186 | ||
7187 | static void pcidev_exit(struct pci_dev *pdev) | |
7188 | { | |
7189 | int i; | |
7190 | struct platform_info *info = pci_get_drvdata(pdev); | |
7191 | struct dev_info *hw_priv = &info->dev_info; | |
7192 | ||
7193 | pci_set_drvdata(pdev, NULL); | |
7194 | ||
7195 | release_mem_region(pci_resource_start(pdev, 0), | |
7196 | pci_resource_len(pdev, 0)); | |
7197 | for (i = 0; i < hw_priv->hw.dev_count; i++) { | |
7198 | if (info->netdev[i]) | |
7199 | netdev_free(info->netdev[i]); | |
7200 | } | |
7201 | if (hw_priv->hw.io) | |
7202 | iounmap(hw_priv->hw.io); | |
7203 | ksz_free_mem(hw_priv); | |
7204 | kfree(hw_priv->hw.ksz_switch); | |
7205 | pci_dev_put(hw_priv->pdev); | |
7206 | kfree(info); | |
7207 | } | |
7208 | ||
7209 | #ifdef CONFIG_PM | |
7210 | static int pcidev_resume(struct pci_dev *pdev) | |
7211 | { | |
7212 | int i; | |
7213 | struct platform_info *info = pci_get_drvdata(pdev); | |
7214 | struct dev_info *hw_priv = &info->dev_info; | |
7215 | struct ksz_hw *hw = &hw_priv->hw; | |
7216 | ||
7217 | pci_set_power_state(pdev, PCI_D0); | |
7218 | pci_restore_state(pdev); | |
7219 | pci_enable_wake(pdev, PCI_D0, 0); | |
7220 | ||
7221 | if (hw_priv->wol_enable) | |
7222 | hw_cfg_wol_pme(hw, 0); | |
7223 | for (i = 0; i < hw->dev_count; i++) { | |
7224 | if (info->netdev[i]) { | |
7225 | struct net_device *dev = info->netdev[i]; | |
7226 | ||
7227 | if (netif_running(dev)) { | |
7228 | netdev_open(dev); | |
7229 | netif_device_attach(dev); | |
7230 | } | |
7231 | } | |
7232 | } | |
7233 | return 0; | |
7234 | } | |
7235 | ||
7236 | static int pcidev_suspend(struct pci_dev *pdev, pm_message_t state) | |
7237 | { | |
7238 | int i; | |
7239 | struct platform_info *info = pci_get_drvdata(pdev); | |
7240 | struct dev_info *hw_priv = &info->dev_info; | |
7241 | struct ksz_hw *hw = &hw_priv->hw; | |
7242 | ||
7243 | /* Need to find a way to retrieve the device IP address. */ | |
7244 | u8 net_addr[] = { 192, 168, 1, 1 }; | |
7245 | ||
7246 | for (i = 0; i < hw->dev_count; i++) { | |
7247 | if (info->netdev[i]) { | |
7248 | struct net_device *dev = info->netdev[i]; | |
7249 | ||
7250 | if (netif_running(dev)) { | |
7251 | netif_device_detach(dev); | |
7252 | netdev_close(dev); | |
7253 | } | |
7254 | } | |
7255 | } | |
7256 | if (hw_priv->wol_enable) { | |
7257 | hw_enable_wol(hw, hw_priv->wol_enable, net_addr); | |
7258 | hw_cfg_wol_pme(hw, 1); | |
7259 | } | |
7260 | ||
7261 | pci_save_state(pdev); | |
7262 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); | |
7263 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
7264 | return 0; | |
7265 | } | |
7266 | #endif | |
7267 | ||
7268 | static char pcidev_name[] = "ksz884xp"; | |
7269 | ||
7270 | static struct pci_device_id pcidev_table[] = { | |
7271 | { PCI_VENDOR_ID_MICREL_KS, 0x8841, | |
7272 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
7273 | { PCI_VENDOR_ID_MICREL_KS, 0x8842, | |
7274 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
7275 | { 0 } | |
7276 | }; | |
7277 | ||
7278 | MODULE_DEVICE_TABLE(pci, pcidev_table); | |
7279 | ||
7280 | static struct pci_driver pci_device_driver = { | |
7281 | #ifdef CONFIG_PM | |
7282 | .suspend = pcidev_suspend, | |
7283 | .resume = pcidev_resume, | |
7284 | #endif | |
7285 | .name = pcidev_name, | |
7286 | .id_table = pcidev_table, | |
7287 | .probe = pcidev_init, | |
7288 | .remove = pcidev_exit | |
7289 | }; | |
7290 | ||
7291 | static int __init ksz884x_init_module(void) | |
7292 | { | |
7293 | return pci_register_driver(&pci_device_driver); | |
7294 | } | |
7295 | ||
7296 | static void __exit ksz884x_cleanup_module(void) | |
7297 | { | |
7298 | pci_unregister_driver(&pci_device_driver); | |
7299 | } | |
7300 | ||
7301 | module_init(ksz884x_init_module); | |
7302 | module_exit(ksz884x_cleanup_module); | |
7303 | ||
7304 | MODULE_DESCRIPTION("KSZ8841/2 PCI network driver"); | |
7305 | MODULE_AUTHOR("Tristram Ha <Tristram.Ha@micrel.com>"); | |
7306 | MODULE_LICENSE("GPL"); | |
7307 | ||
7308 | module_param_named(message, msg_enable, int, 0); | |
7309 | MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)"); | |
7310 | ||
7311 | module_param(macaddr, charp, 0); | |
7312 | module_param(mac1addr, charp, 0); | |
7313 | module_param(fast_aging, int, 0); | |
7314 | module_param(multi_dev, int, 0); | |
7315 | module_param(stp, int, 0); | |
7316 | MODULE_PARM_DESC(macaddr, "MAC address"); | |
7317 | MODULE_PARM_DESC(mac1addr, "Second MAC address"); | |
7318 | MODULE_PARM_DESC(fast_aging, "Fast aging"); | |
7319 | MODULE_PARM_DESC(multi_dev, "Multiple device interfaces"); | |
7320 | MODULE_PARM_DESC(stp, "STP support"); |