Commit | Line | Data |
---|---|---|
89e5785f HS |
1 | /* |
2 | * Atmel MACB Ethernet Controller driver | |
3 | * | |
4 | * Copyright (C) 2004-2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/clk.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/moduleparam.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/netdevice.h> | |
19 | #include <linux/etherdevice.h> | |
89e5785f | 20 | #include <linux/dma-mapping.h> |
89e5785f | 21 | #include <linux/platform_device.h> |
6c36a707 | 22 | #include <linux/phy.h> |
89e5785f | 23 | |
a09e64fb RK |
24 | #include <mach/board.h> |
25 | #include <mach/cpu.h> | |
89e5785f HS |
26 | |
27 | #include "macb.h" | |
28 | ||
89e5785f HS |
29 | #define RX_BUFFER_SIZE 128 |
30 | #define RX_RING_SIZE 512 | |
31 | #define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE) | |
32 | ||
33 | /* Make the IP header word-aligned (the ethernet header is 14 bytes) */ | |
34 | #define RX_OFFSET 2 | |
35 | ||
36 | #define TX_RING_SIZE 128 | |
37 | #define DEF_TX_RING_PENDING (TX_RING_SIZE - 1) | |
38 | #define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE) | |
39 | ||
40 | #define TX_RING_GAP(bp) \ | |
41 | (TX_RING_SIZE - (bp)->tx_pending) | |
42 | #define TX_BUFFS_AVAIL(bp) \ | |
43 | (((bp)->tx_tail <= (bp)->tx_head) ? \ | |
44 | (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \ | |
45 | (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp)) | |
46 | #define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1)) | |
47 | ||
48 | #define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1)) | |
49 | ||
50 | /* minimum number of free TX descriptors before waking up TX process */ | |
51 | #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4) | |
52 | ||
53 | #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ | |
54 | | MACB_BIT(ISR_ROVR)) | |
55 | ||
56 | static void __macb_set_hwaddr(struct macb *bp) | |
57 | { | |
58 | u32 bottom; | |
59 | u16 top; | |
60 | ||
61 | bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr)); | |
62 | macb_writel(bp, SA1B, bottom); | |
63 | top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); | |
64 | macb_writel(bp, SA1T, top); | |
65 | } | |
66 | ||
67 | static void __init macb_get_hwaddr(struct macb *bp) | |
68 | { | |
69 | u32 bottom; | |
70 | u16 top; | |
71 | u8 addr[6]; | |
72 | ||
73 | bottom = macb_readl(bp, SA1B); | |
74 | top = macb_readl(bp, SA1T); | |
75 | ||
76 | addr[0] = bottom & 0xff; | |
77 | addr[1] = (bottom >> 8) & 0xff; | |
78 | addr[2] = (bottom >> 16) & 0xff; | |
79 | addr[3] = (bottom >> 24) & 0xff; | |
80 | addr[4] = top & 0xff; | |
81 | addr[5] = (top >> 8) & 0xff; | |
82 | ||
d1d5741d | 83 | if (is_valid_ether_addr(addr)) { |
89e5785f | 84 | memcpy(bp->dev->dev_addr, addr, sizeof(addr)); |
d1d5741d SS |
85 | } else { |
86 | dev_info(&bp->pdev->dev, "invalid hw address, using random\n"); | |
87 | random_ether_addr(bp->dev->dev_addr); | |
88 | } | |
89e5785f HS |
89 | } |
90 | ||
6c36a707 | 91 | static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
89e5785f | 92 | { |
6c36a707 | 93 | struct macb *bp = bus->priv; |
89e5785f HS |
94 | int value; |
95 | ||
89e5785f HS |
96 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) |
97 | | MACB_BF(RW, MACB_MAN_READ) | |
6c36a707 R |
98 | | MACB_BF(PHYA, mii_id) |
99 | | MACB_BF(REGA, regnum) | |
89e5785f HS |
100 | | MACB_BF(CODE, MACB_MAN_CODE))); |
101 | ||
6c36a707 R |
102 | /* wait for end of transfer */ |
103 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
104 | cpu_relax(); | |
89e5785f HS |
105 | |
106 | value = MACB_BFEXT(DATA, macb_readl(bp, MAN)); | |
89e5785f HS |
107 | |
108 | return value; | |
109 | } | |
110 | ||
6c36a707 R |
111 | static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
112 | u16 value) | |
89e5785f | 113 | { |
6c36a707 | 114 | struct macb *bp = bus->priv; |
89e5785f HS |
115 | |
116 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) | |
117 | | MACB_BF(RW, MACB_MAN_WRITE) | |
6c36a707 R |
118 | | MACB_BF(PHYA, mii_id) |
119 | | MACB_BF(REGA, regnum) | |
89e5785f | 120 | | MACB_BF(CODE, MACB_MAN_CODE) |
6c36a707 | 121 | | MACB_BF(DATA, value))); |
89e5785f | 122 | |
6c36a707 R |
123 | /* wait for end of transfer */ |
124 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
125 | cpu_relax(); | |
126 | ||
127 | return 0; | |
128 | } | |
89e5785f | 129 | |
6c36a707 R |
130 | static int macb_mdio_reset(struct mii_bus *bus) |
131 | { | |
132 | return 0; | |
89e5785f HS |
133 | } |
134 | ||
6c36a707 | 135 | static void macb_handle_link_change(struct net_device *dev) |
89e5785f | 136 | { |
6c36a707 R |
137 | struct macb *bp = netdev_priv(dev); |
138 | struct phy_device *phydev = bp->phy_dev; | |
139 | unsigned long flags; | |
89e5785f | 140 | |
6c36a707 | 141 | int status_change = 0; |
89e5785f | 142 | |
6c36a707 R |
143 | spin_lock_irqsave(&bp->lock, flags); |
144 | ||
145 | if (phydev->link) { | |
146 | if ((bp->speed != phydev->speed) || | |
147 | (bp->duplex != phydev->duplex)) { | |
148 | u32 reg; | |
149 | ||
150 | reg = macb_readl(bp, NCFGR); | |
151 | reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); | |
152 | ||
153 | if (phydev->duplex) | |
154 | reg |= MACB_BIT(FD); | |
179956f4 | 155 | if (phydev->speed == SPEED_100) |
6c36a707 R |
156 | reg |= MACB_BIT(SPD); |
157 | ||
158 | macb_writel(bp, NCFGR, reg); | |
159 | ||
160 | bp->speed = phydev->speed; | |
161 | bp->duplex = phydev->duplex; | |
162 | status_change = 1; | |
163 | } | |
89e5785f HS |
164 | } |
165 | ||
6c36a707 | 166 | if (phydev->link != bp->link) { |
c8f15686 | 167 | if (!phydev->link) { |
6c36a707 R |
168 | bp->speed = 0; |
169 | bp->duplex = -1; | |
170 | } | |
171 | bp->link = phydev->link; | |
89e5785f | 172 | |
6c36a707 R |
173 | status_change = 1; |
174 | } | |
89e5785f | 175 | |
6c36a707 R |
176 | spin_unlock_irqrestore(&bp->lock, flags); |
177 | ||
178 | if (status_change) { | |
179 | if (phydev->link) | |
180 | printk(KERN_INFO "%s: link up (%d/%s)\n", | |
181 | dev->name, phydev->speed, | |
182 | DUPLEX_FULL == phydev->duplex ? "Full":"Half"); | |
183 | else | |
184 | printk(KERN_INFO "%s: link down\n", dev->name); | |
185 | } | |
89e5785f HS |
186 | } |
187 | ||
6c36a707 R |
188 | /* based on au1000_eth. c*/ |
189 | static int macb_mii_probe(struct net_device *dev) | |
89e5785f | 190 | { |
6c36a707 R |
191 | struct macb *bp = netdev_priv(dev); |
192 | struct phy_device *phydev = NULL; | |
193 | struct eth_platform_data *pdata; | |
194 | int phy_addr; | |
89e5785f | 195 | |
6c36a707 R |
196 | /* find the first phy */ |
197 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | |
298cf9be LB |
198 | if (bp->mii_bus->phy_map[phy_addr]) { |
199 | phydev = bp->mii_bus->phy_map[phy_addr]; | |
6c36a707 R |
200 | break; |
201 | } | |
202 | } | |
203 | ||
204 | if (!phydev) { | |
205 | printk (KERN_ERR "%s: no PHY found\n", dev->name); | |
206 | return -1; | |
207 | } | |
208 | ||
209 | pdata = bp->pdev->dev.platform_data; | |
210 | /* TODO : add pin_irq */ | |
211 | ||
212 | /* attach the mac to the phy */ | |
213 | if (pdata && pdata->is_rmii) { | |
214 | phydev = phy_connect(dev, phydev->dev.bus_id, | |
215 | &macb_handle_link_change, 0, PHY_INTERFACE_MODE_RMII); | |
216 | } else { | |
217 | phydev = phy_connect(dev, phydev->dev.bus_id, | |
218 | &macb_handle_link_change, 0, PHY_INTERFACE_MODE_MII); | |
219 | } | |
220 | ||
221 | if (IS_ERR(phydev)) { | |
222 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
223 | return PTR_ERR(phydev); | |
224 | } | |
225 | ||
226 | /* mask with MAC supported features */ | |
227 | phydev->supported &= PHY_BASIC_FEATURES; | |
228 | ||
229 | phydev->advertising = phydev->supported; | |
230 | ||
231 | bp->link = 0; | |
232 | bp->speed = 0; | |
233 | bp->duplex = -1; | |
234 | bp->phy_dev = phydev; | |
235 | ||
236 | return 0; | |
89e5785f HS |
237 | } |
238 | ||
6c36a707 | 239 | static int macb_mii_init(struct macb *bp) |
89e5785f | 240 | { |
6c36a707 R |
241 | struct eth_platform_data *pdata; |
242 | int err = -ENXIO, i; | |
89e5785f | 243 | |
6c36a707 R |
244 | /* Enable managment port */ |
245 | macb_writel(bp, NCR, MACB_BIT(MPE)); | |
89e5785f | 246 | |
298cf9be LB |
247 | bp->mii_bus = mdiobus_alloc(); |
248 | if (bp->mii_bus == NULL) { | |
249 | err = -ENOMEM; | |
250 | goto err_out; | |
251 | } | |
252 | ||
253 | bp->mii_bus->name = "MACB_mii_bus"; | |
254 | bp->mii_bus->read = &macb_mdio_read; | |
255 | bp->mii_bus->write = &macb_mdio_write; | |
256 | bp->mii_bus->reset = &macb_mdio_reset; | |
257 | snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", bp->pdev->id); | |
258 | bp->mii_bus->priv = bp; | |
259 | bp->mii_bus->parent = &bp->dev->dev; | |
6c36a707 | 260 | pdata = bp->pdev->dev.platform_data; |
89e5785f | 261 | |
6c36a707 | 262 | if (pdata) |
298cf9be | 263 | bp->mii_bus->phy_mask = pdata->phy_mask; |
89e5785f | 264 | |
298cf9be LB |
265 | bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); |
266 | if (!bp->mii_bus->irq) { | |
6c36a707 | 267 | err = -ENOMEM; |
298cf9be | 268 | goto err_out_free_mdiobus; |
89e5785f HS |
269 | } |
270 | ||
6c36a707 | 271 | for (i = 0; i < PHY_MAX_ADDR; i++) |
298cf9be | 272 | bp->mii_bus->irq[i] = PHY_POLL; |
89e5785f | 273 | |
298cf9be | 274 | platform_set_drvdata(bp->dev, bp->mii_bus); |
89e5785f | 275 | |
298cf9be | 276 | if (mdiobus_register(bp->mii_bus)) |
6c36a707 | 277 | goto err_out_free_mdio_irq; |
89e5785f | 278 | |
6c36a707 R |
279 | if (macb_mii_probe(bp->dev) != 0) { |
280 | goto err_out_unregister_bus; | |
281 | } | |
89e5785f | 282 | |
6c36a707 | 283 | return 0; |
89e5785f | 284 | |
6c36a707 | 285 | err_out_unregister_bus: |
298cf9be | 286 | mdiobus_unregister(bp->mii_bus); |
6c36a707 | 287 | err_out_free_mdio_irq: |
298cf9be LB |
288 | kfree(bp->mii_bus->irq); |
289 | err_out_free_mdiobus: | |
290 | mdiobus_free(bp->mii_bus); | |
6c36a707 R |
291 | err_out: |
292 | return err; | |
89e5785f HS |
293 | } |
294 | ||
295 | static void macb_update_stats(struct macb *bp) | |
296 | { | |
297 | u32 __iomem *reg = bp->regs + MACB_PFR; | |
298 | u32 *p = &bp->hw_stats.rx_pause_frames; | |
299 | u32 *end = &bp->hw_stats.tx_pause_frames + 1; | |
300 | ||
301 | WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); | |
302 | ||
303 | for(; p < end; p++, reg++) | |
0f0d84e5 | 304 | *p += __raw_readl(reg); |
89e5785f HS |
305 | } |
306 | ||
89e5785f HS |
307 | static void macb_tx(struct macb *bp) |
308 | { | |
309 | unsigned int tail; | |
310 | unsigned int head; | |
311 | u32 status; | |
312 | ||
313 | status = macb_readl(bp, TSR); | |
314 | macb_writel(bp, TSR, status); | |
315 | ||
316 | dev_dbg(&bp->pdev->dev, "macb_tx status = %02lx\n", | |
317 | (unsigned long)status); | |
318 | ||
319 | if (status & MACB_BIT(UND)) { | |
bdcba151 | 320 | int i; |
89e5785f | 321 | printk(KERN_ERR "%s: TX underrun, resetting buffers\n", |
bdcba151 GC |
322 | bp->dev->name); |
323 | ||
324 | head = bp->tx_head; | |
325 | ||
326 | /*Mark all the buffer as used to avoid sending a lost buffer*/ | |
327 | for (i = 0; i < TX_RING_SIZE; i++) | |
328 | bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); | |
329 | ||
330 | /* free transmit buffer in upper layer*/ | |
331 | for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) { | |
332 | struct ring_info *rp = &bp->tx_skb[tail]; | |
333 | struct sk_buff *skb = rp->skb; | |
334 | ||
335 | BUG_ON(skb == NULL); | |
336 | ||
337 | rmb(); | |
338 | ||
339 | dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len, | |
340 | DMA_TO_DEVICE); | |
341 | rp->skb = NULL; | |
342 | dev_kfree_skb_irq(skb); | |
343 | } | |
344 | ||
89e5785f HS |
345 | bp->tx_head = bp->tx_tail = 0; |
346 | } | |
347 | ||
348 | if (!(status & MACB_BIT(COMP))) | |
349 | /* | |
350 | * This may happen when a buffer becomes complete | |
351 | * between reading the ISR and scanning the | |
352 | * descriptors. Nothing to worry about. | |
353 | */ | |
354 | return; | |
355 | ||
356 | head = bp->tx_head; | |
357 | for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) { | |
358 | struct ring_info *rp = &bp->tx_skb[tail]; | |
359 | struct sk_buff *skb = rp->skb; | |
360 | u32 bufstat; | |
361 | ||
362 | BUG_ON(skb == NULL); | |
363 | ||
364 | rmb(); | |
365 | bufstat = bp->tx_ring[tail].ctrl; | |
366 | ||
367 | if (!(bufstat & MACB_BIT(TX_USED))) | |
368 | break; | |
369 | ||
370 | dev_dbg(&bp->pdev->dev, "skb %u (data %p) TX complete\n", | |
371 | tail, skb->data); | |
372 | dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len, | |
373 | DMA_TO_DEVICE); | |
374 | bp->stats.tx_packets++; | |
375 | bp->stats.tx_bytes += skb->len; | |
376 | rp->skb = NULL; | |
377 | dev_kfree_skb_irq(skb); | |
378 | } | |
379 | ||
380 | bp->tx_tail = tail; | |
381 | if (netif_queue_stopped(bp->dev) && | |
382 | TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH) | |
383 | netif_wake_queue(bp->dev); | |
384 | } | |
385 | ||
386 | static int macb_rx_frame(struct macb *bp, unsigned int first_frag, | |
387 | unsigned int last_frag) | |
388 | { | |
389 | unsigned int len; | |
390 | unsigned int frag; | |
391 | unsigned int offset = 0; | |
392 | struct sk_buff *skb; | |
393 | ||
394 | len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl); | |
395 | ||
396 | dev_dbg(&bp->pdev->dev, "macb_rx_frame frags %u - %u (len %u)\n", | |
397 | first_frag, last_frag, len); | |
398 | ||
399 | skb = dev_alloc_skb(len + RX_OFFSET); | |
400 | if (!skb) { | |
401 | bp->stats.rx_dropped++; | |
402 | for (frag = first_frag; ; frag = NEXT_RX(frag)) { | |
403 | bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); | |
404 | if (frag == last_frag) | |
405 | break; | |
406 | } | |
407 | wmb(); | |
408 | return 1; | |
409 | } | |
410 | ||
411 | skb_reserve(skb, RX_OFFSET); | |
89e5785f HS |
412 | skb->ip_summed = CHECKSUM_NONE; |
413 | skb_put(skb, len); | |
414 | ||
415 | for (frag = first_frag; ; frag = NEXT_RX(frag)) { | |
416 | unsigned int frag_len = RX_BUFFER_SIZE; | |
417 | ||
418 | if (offset + frag_len > len) { | |
419 | BUG_ON(frag != last_frag); | |
420 | frag_len = len - offset; | |
421 | } | |
27d7ff46 ACM |
422 | skb_copy_to_linear_data_offset(skb, offset, |
423 | (bp->rx_buffers + | |
424 | (RX_BUFFER_SIZE * frag)), | |
425 | frag_len); | |
89e5785f HS |
426 | offset += RX_BUFFER_SIZE; |
427 | bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); | |
428 | wmb(); | |
429 | ||
430 | if (frag == last_frag) | |
431 | break; | |
432 | } | |
433 | ||
434 | skb->protocol = eth_type_trans(skb, bp->dev); | |
435 | ||
436 | bp->stats.rx_packets++; | |
437 | bp->stats.rx_bytes += len; | |
438 | bp->dev->last_rx = jiffies; | |
439 | dev_dbg(&bp->pdev->dev, "received skb of length %u, csum: %08x\n", | |
440 | skb->len, skb->csum); | |
441 | netif_receive_skb(skb); | |
442 | ||
443 | return 0; | |
444 | } | |
445 | ||
446 | /* Mark DMA descriptors from begin up to and not including end as unused */ | |
447 | static void discard_partial_frame(struct macb *bp, unsigned int begin, | |
448 | unsigned int end) | |
449 | { | |
450 | unsigned int frag; | |
451 | ||
452 | for (frag = begin; frag != end; frag = NEXT_RX(frag)) | |
453 | bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); | |
454 | wmb(); | |
455 | ||
456 | /* | |
457 | * When this happens, the hardware stats registers for | |
458 | * whatever caused this is updated, so we don't have to record | |
459 | * anything. | |
460 | */ | |
461 | } | |
462 | ||
463 | static int macb_rx(struct macb *bp, int budget) | |
464 | { | |
465 | int received = 0; | |
466 | unsigned int tail = bp->rx_tail; | |
467 | int first_frag = -1; | |
468 | ||
469 | for (; budget > 0; tail = NEXT_RX(tail)) { | |
470 | u32 addr, ctrl; | |
471 | ||
472 | rmb(); | |
473 | addr = bp->rx_ring[tail].addr; | |
474 | ctrl = bp->rx_ring[tail].ctrl; | |
475 | ||
476 | if (!(addr & MACB_BIT(RX_USED))) | |
477 | break; | |
478 | ||
479 | if (ctrl & MACB_BIT(RX_SOF)) { | |
480 | if (first_frag != -1) | |
481 | discard_partial_frame(bp, first_frag, tail); | |
482 | first_frag = tail; | |
483 | } | |
484 | ||
485 | if (ctrl & MACB_BIT(RX_EOF)) { | |
486 | int dropped; | |
487 | BUG_ON(first_frag == -1); | |
488 | ||
489 | dropped = macb_rx_frame(bp, first_frag, tail); | |
490 | first_frag = -1; | |
491 | if (!dropped) { | |
492 | received++; | |
493 | budget--; | |
494 | } | |
495 | } | |
496 | } | |
497 | ||
498 | if (first_frag != -1) | |
499 | bp->rx_tail = first_frag; | |
500 | else | |
501 | bp->rx_tail = tail; | |
502 | ||
503 | return received; | |
504 | } | |
505 | ||
bea3348e | 506 | static int macb_poll(struct napi_struct *napi, int budget) |
89e5785f | 507 | { |
bea3348e SH |
508 | struct macb *bp = container_of(napi, struct macb, napi); |
509 | struct net_device *dev = bp->dev; | |
510 | int work_done; | |
89e5785f HS |
511 | u32 status; |
512 | ||
513 | status = macb_readl(bp, RSR); | |
514 | macb_writel(bp, RSR, status); | |
515 | ||
bea3348e | 516 | work_done = 0; |
89e5785f HS |
517 | if (!status) { |
518 | /* | |
519 | * This may happen if an interrupt was pending before | |
520 | * this function was called last time, and no packets | |
521 | * have been received since. | |
522 | */ | |
bea3348e | 523 | netif_rx_complete(dev, napi); |
89e5785f HS |
524 | goto out; |
525 | } | |
526 | ||
527 | dev_dbg(&bp->pdev->dev, "poll: status = %08lx, budget = %d\n", | |
bea3348e | 528 | (unsigned long)status, budget); |
89e5785f HS |
529 | |
530 | if (!(status & MACB_BIT(REC))) { | |
531 | dev_warn(&bp->pdev->dev, | |
532 | "No RX buffers complete, status = %02lx\n", | |
533 | (unsigned long)status); | |
bea3348e | 534 | netif_rx_complete(dev, napi); |
89e5785f HS |
535 | goto out; |
536 | } | |
537 | ||
bea3348e SH |
538 | work_done = macb_rx(bp, budget); |
539 | if (work_done < budget) | |
540 | netif_rx_complete(dev, napi); | |
89e5785f HS |
541 | |
542 | /* | |
543 | * We've done what we can to clean the buffers. Make sure we | |
544 | * get notified when new packets arrive. | |
545 | */ | |
546 | out: | |
547 | macb_writel(bp, IER, MACB_RX_INT_FLAGS); | |
548 | ||
549 | /* TODO: Handle errors */ | |
550 | ||
bea3348e | 551 | return work_done; |
89e5785f HS |
552 | } |
553 | ||
554 | static irqreturn_t macb_interrupt(int irq, void *dev_id) | |
555 | { | |
556 | struct net_device *dev = dev_id; | |
557 | struct macb *bp = netdev_priv(dev); | |
558 | u32 status; | |
559 | ||
560 | status = macb_readl(bp, ISR); | |
561 | ||
562 | if (unlikely(!status)) | |
563 | return IRQ_NONE; | |
564 | ||
565 | spin_lock(&bp->lock); | |
566 | ||
567 | while (status) { | |
89e5785f HS |
568 | /* close possible race with dev_close */ |
569 | if (unlikely(!netif_running(dev))) { | |
570 | macb_writel(bp, IDR, ~0UL); | |
571 | break; | |
572 | } | |
573 | ||
574 | if (status & MACB_RX_INT_FLAGS) { | |
bea3348e | 575 | if (netif_rx_schedule_prep(dev, &bp->napi)) { |
89e5785f HS |
576 | /* |
577 | * There's no point taking any more interrupts | |
578 | * until we have processed the buffers | |
579 | */ | |
580 | macb_writel(bp, IDR, MACB_RX_INT_FLAGS); | |
6c36a707 R |
581 | dev_dbg(&bp->pdev->dev, |
582 | "scheduling RX softirq\n"); | |
bea3348e | 583 | __netif_rx_schedule(dev, &bp->napi); |
89e5785f HS |
584 | } |
585 | } | |
586 | ||
587 | if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND))) | |
588 | macb_tx(bp); | |
589 | ||
590 | /* | |
591 | * Link change detection isn't possible with RMII, so we'll | |
592 | * add that if/when we get our hands on a full-blown MII PHY. | |
593 | */ | |
594 | ||
595 | if (status & MACB_BIT(HRESP)) { | |
596 | /* | |
597 | * TODO: Reset the hardware, and maybe move the printk | |
598 | * to a lower-priority context as well (work queue?) | |
599 | */ | |
600 | printk(KERN_ERR "%s: DMA bus error: HRESP not OK\n", | |
601 | dev->name); | |
602 | } | |
603 | ||
604 | status = macb_readl(bp, ISR); | |
605 | } | |
606 | ||
607 | spin_unlock(&bp->lock); | |
608 | ||
609 | return IRQ_HANDLED; | |
610 | } | |
611 | ||
612 | static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
613 | { | |
614 | struct macb *bp = netdev_priv(dev); | |
615 | dma_addr_t mapping; | |
616 | unsigned int len, entry; | |
617 | u32 ctrl; | |
618 | ||
619 | #ifdef DEBUG | |
620 | int i; | |
621 | dev_dbg(&bp->pdev->dev, | |
622 | "start_xmit: len %u head %p data %p tail %p end %p\n", | |
27a884dc | 623 | skb->len, skb->head, skb->data, |
4305b541 | 624 | skb_tail_pointer(skb), skb_end_pointer(skb)); |
89e5785f HS |
625 | dev_dbg(&bp->pdev->dev, |
626 | "data:"); | |
627 | for (i = 0; i < 16; i++) | |
628 | printk(" %02x", (unsigned int)skb->data[i]); | |
629 | printk("\n"); | |
630 | #endif | |
631 | ||
632 | len = skb->len; | |
633 | spin_lock_irq(&bp->lock); | |
634 | ||
635 | /* This is a hard error, log it. */ | |
636 | if (TX_BUFFS_AVAIL(bp) < 1) { | |
637 | netif_stop_queue(dev); | |
638 | spin_unlock_irq(&bp->lock); | |
639 | dev_err(&bp->pdev->dev, | |
640 | "BUG! Tx Ring full when queue awake!\n"); | |
641 | dev_dbg(&bp->pdev->dev, "tx_head = %u, tx_tail = %u\n", | |
642 | bp->tx_head, bp->tx_tail); | |
643 | return 1; | |
644 | } | |
645 | ||
646 | entry = bp->tx_head; | |
647 | dev_dbg(&bp->pdev->dev, "Allocated ring entry %u\n", entry); | |
648 | mapping = dma_map_single(&bp->pdev->dev, skb->data, | |
649 | len, DMA_TO_DEVICE); | |
650 | bp->tx_skb[entry].skb = skb; | |
651 | bp->tx_skb[entry].mapping = mapping; | |
652 | dev_dbg(&bp->pdev->dev, "Mapped skb data %p to DMA addr %08lx\n", | |
653 | skb->data, (unsigned long)mapping); | |
654 | ||
655 | ctrl = MACB_BF(TX_FRMLEN, len); | |
656 | ctrl |= MACB_BIT(TX_LAST); | |
657 | if (entry == (TX_RING_SIZE - 1)) | |
658 | ctrl |= MACB_BIT(TX_WRAP); | |
659 | ||
660 | bp->tx_ring[entry].addr = mapping; | |
661 | bp->tx_ring[entry].ctrl = ctrl; | |
662 | wmb(); | |
663 | ||
664 | entry = NEXT_TX(entry); | |
665 | bp->tx_head = entry; | |
666 | ||
667 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); | |
668 | ||
669 | if (TX_BUFFS_AVAIL(bp) < 1) | |
670 | netif_stop_queue(dev); | |
671 | ||
672 | spin_unlock_irq(&bp->lock); | |
673 | ||
674 | dev->trans_start = jiffies; | |
675 | ||
676 | return 0; | |
677 | } | |
678 | ||
679 | static void macb_free_consistent(struct macb *bp) | |
680 | { | |
681 | if (bp->tx_skb) { | |
682 | kfree(bp->tx_skb); | |
683 | bp->tx_skb = NULL; | |
684 | } | |
685 | if (bp->rx_ring) { | |
686 | dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES, | |
687 | bp->rx_ring, bp->rx_ring_dma); | |
688 | bp->rx_ring = NULL; | |
689 | } | |
690 | if (bp->tx_ring) { | |
691 | dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES, | |
692 | bp->tx_ring, bp->tx_ring_dma); | |
693 | bp->tx_ring = NULL; | |
694 | } | |
695 | if (bp->rx_buffers) { | |
696 | dma_free_coherent(&bp->pdev->dev, | |
697 | RX_RING_SIZE * RX_BUFFER_SIZE, | |
698 | bp->rx_buffers, bp->rx_buffers_dma); | |
699 | bp->rx_buffers = NULL; | |
700 | } | |
701 | } | |
702 | ||
703 | static int macb_alloc_consistent(struct macb *bp) | |
704 | { | |
705 | int size; | |
706 | ||
707 | size = TX_RING_SIZE * sizeof(struct ring_info); | |
708 | bp->tx_skb = kmalloc(size, GFP_KERNEL); | |
709 | if (!bp->tx_skb) | |
710 | goto out_err; | |
711 | ||
712 | size = RX_RING_BYTES; | |
713 | bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
714 | &bp->rx_ring_dma, GFP_KERNEL); | |
715 | if (!bp->rx_ring) | |
716 | goto out_err; | |
717 | dev_dbg(&bp->pdev->dev, | |
718 | "Allocated RX ring of %d bytes at %08lx (mapped %p)\n", | |
719 | size, (unsigned long)bp->rx_ring_dma, bp->rx_ring); | |
720 | ||
721 | size = TX_RING_BYTES; | |
722 | bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
723 | &bp->tx_ring_dma, GFP_KERNEL); | |
724 | if (!bp->tx_ring) | |
725 | goto out_err; | |
726 | dev_dbg(&bp->pdev->dev, | |
727 | "Allocated TX ring of %d bytes at %08lx (mapped %p)\n", | |
728 | size, (unsigned long)bp->tx_ring_dma, bp->tx_ring); | |
729 | ||
730 | size = RX_RING_SIZE * RX_BUFFER_SIZE; | |
731 | bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, | |
732 | &bp->rx_buffers_dma, GFP_KERNEL); | |
733 | if (!bp->rx_buffers) | |
734 | goto out_err; | |
735 | dev_dbg(&bp->pdev->dev, | |
736 | "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n", | |
737 | size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers); | |
738 | ||
739 | return 0; | |
740 | ||
741 | out_err: | |
742 | macb_free_consistent(bp); | |
743 | return -ENOMEM; | |
744 | } | |
745 | ||
746 | static void macb_init_rings(struct macb *bp) | |
747 | { | |
748 | int i; | |
749 | dma_addr_t addr; | |
750 | ||
751 | addr = bp->rx_buffers_dma; | |
752 | for (i = 0; i < RX_RING_SIZE; i++) { | |
753 | bp->rx_ring[i].addr = addr; | |
754 | bp->rx_ring[i].ctrl = 0; | |
755 | addr += RX_BUFFER_SIZE; | |
756 | } | |
757 | bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP); | |
758 | ||
759 | for (i = 0; i < TX_RING_SIZE; i++) { | |
760 | bp->tx_ring[i].addr = 0; | |
761 | bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); | |
762 | } | |
763 | bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); | |
764 | ||
765 | bp->rx_tail = bp->tx_head = bp->tx_tail = 0; | |
766 | } | |
767 | ||
768 | static void macb_reset_hw(struct macb *bp) | |
769 | { | |
770 | /* Make sure we have the write buffer for ourselves */ | |
771 | wmb(); | |
772 | ||
773 | /* | |
774 | * Disable RX and TX (XXX: Should we halt the transmission | |
775 | * more gracefully?) | |
776 | */ | |
777 | macb_writel(bp, NCR, 0); | |
778 | ||
779 | /* Clear the stats registers (XXX: Update stats first?) */ | |
780 | macb_writel(bp, NCR, MACB_BIT(CLRSTAT)); | |
781 | ||
782 | /* Clear all status flags */ | |
783 | macb_writel(bp, TSR, ~0UL); | |
784 | macb_writel(bp, RSR, ~0UL); | |
785 | ||
786 | /* Disable all interrupts */ | |
787 | macb_writel(bp, IDR, ~0UL); | |
788 | macb_readl(bp, ISR); | |
789 | } | |
790 | ||
791 | static void macb_init_hw(struct macb *bp) | |
792 | { | |
793 | u32 config; | |
794 | ||
795 | macb_reset_hw(bp); | |
796 | __macb_set_hwaddr(bp); | |
797 | ||
798 | config = macb_readl(bp, NCFGR) & MACB_BF(CLK, -1L); | |
799 | config |= MACB_BIT(PAE); /* PAuse Enable */ | |
800 | config |= MACB_BIT(DRFCS); /* Discard Rx FCS */ | |
801 | if (bp->dev->flags & IFF_PROMISC) | |
802 | config |= MACB_BIT(CAF); /* Copy All Frames */ | |
803 | if (!(bp->dev->flags & IFF_BROADCAST)) | |
804 | config |= MACB_BIT(NBC); /* No BroadCast */ | |
805 | macb_writel(bp, NCFGR, config); | |
806 | ||
807 | /* Initialize TX and RX buffers */ | |
808 | macb_writel(bp, RBQP, bp->rx_ring_dma); | |
809 | macb_writel(bp, TBQP, bp->tx_ring_dma); | |
810 | ||
811 | /* Enable TX and RX */ | |
6c36a707 | 812 | macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE)); |
89e5785f HS |
813 | |
814 | /* Enable interrupts */ | |
815 | macb_writel(bp, IER, (MACB_BIT(RCOMP) | |
816 | | MACB_BIT(RXUBR) | |
817 | | MACB_BIT(ISR_TUND) | |
818 | | MACB_BIT(ISR_RLE) | |
819 | | MACB_BIT(TXERR) | |
820 | | MACB_BIT(TCOMP) | |
821 | | MACB_BIT(ISR_ROVR) | |
822 | | MACB_BIT(HRESP))); | |
89e5785f | 823 | |
89e5785f HS |
824 | } |
825 | ||
446ebd01 PV |
826 | /* |
827 | * The hash address register is 64 bits long and takes up two | |
828 | * locations in the memory map. The least significant bits are stored | |
829 | * in EMAC_HSL and the most significant bits in EMAC_HSH. | |
830 | * | |
831 | * The unicast hash enable and the multicast hash enable bits in the | |
832 | * network configuration register enable the reception of hash matched | |
833 | * frames. The destination address is reduced to a 6 bit index into | |
834 | * the 64 bit hash register using the following hash function. The | |
835 | * hash function is an exclusive or of every sixth bit of the | |
836 | * destination address. | |
837 | * | |
838 | * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] | |
839 | * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] | |
840 | * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] | |
841 | * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] | |
842 | * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] | |
843 | * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] | |
844 | * | |
845 | * da[0] represents the least significant bit of the first byte | |
846 | * received, that is, the multicast/unicast indicator, and da[47] | |
847 | * represents the most significant bit of the last byte received. If | |
848 | * the hash index, hi[n], points to a bit that is set in the hash | |
849 | * register then the frame will be matched according to whether the | |
850 | * frame is multicast or unicast. A multicast match will be signalled | |
851 | * if the multicast hash enable bit is set, da[0] is 1 and the hash | |
852 | * index points to a bit set in the hash register. A unicast match | |
853 | * will be signalled if the unicast hash enable bit is set, da[0] is 0 | |
854 | * and the hash index points to a bit set in the hash register. To | |
855 | * receive all multicast frames, the hash register should be set with | |
856 | * all ones and the multicast hash enable bit should be set in the | |
857 | * network configuration register. | |
858 | */ | |
859 | ||
860 | static inline int hash_bit_value(int bitnr, __u8 *addr) | |
861 | { | |
862 | if (addr[bitnr / 8] & (1 << (bitnr % 8))) | |
863 | return 1; | |
864 | return 0; | |
865 | } | |
866 | ||
867 | /* | |
868 | * Return the hash index value for the specified address. | |
869 | */ | |
870 | static int hash_get_index(__u8 *addr) | |
871 | { | |
872 | int i, j, bitval; | |
873 | int hash_index = 0; | |
874 | ||
875 | for (j = 0; j < 6; j++) { | |
876 | for (i = 0, bitval = 0; i < 8; i++) | |
877 | bitval ^= hash_bit_value(i*6 + j, addr); | |
878 | ||
879 | hash_index |= (bitval << j); | |
880 | } | |
881 | ||
882 | return hash_index; | |
883 | } | |
884 | ||
885 | /* | |
886 | * Add multicast addresses to the internal multicast-hash table. | |
887 | */ | |
888 | static void macb_sethashtable(struct net_device *dev) | |
889 | { | |
890 | struct dev_mc_list *curr; | |
891 | unsigned long mc_filter[2]; | |
892 | unsigned int i, bitnr; | |
893 | struct macb *bp = netdev_priv(dev); | |
894 | ||
895 | mc_filter[0] = mc_filter[1] = 0; | |
896 | ||
897 | curr = dev->mc_list; | |
898 | for (i = 0; i < dev->mc_count; i++, curr = curr->next) { | |
899 | if (!curr) break; /* unexpected end of list */ | |
900 | ||
901 | bitnr = hash_get_index(curr->dmi_addr); | |
902 | mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); | |
903 | } | |
904 | ||
905 | macb_writel(bp, HRB, mc_filter[0]); | |
906 | macb_writel(bp, HRT, mc_filter[1]); | |
907 | } | |
908 | ||
909 | /* | |
910 | * Enable/Disable promiscuous and multicast modes. | |
911 | */ | |
912 | static void macb_set_rx_mode(struct net_device *dev) | |
913 | { | |
914 | unsigned long cfg; | |
915 | struct macb *bp = netdev_priv(dev); | |
916 | ||
917 | cfg = macb_readl(bp, NCFGR); | |
918 | ||
919 | if (dev->flags & IFF_PROMISC) | |
920 | /* Enable promiscuous mode */ | |
921 | cfg |= MACB_BIT(CAF); | |
922 | else if (dev->flags & (~IFF_PROMISC)) | |
923 | /* Disable promiscuous mode */ | |
924 | cfg &= ~MACB_BIT(CAF); | |
925 | ||
926 | if (dev->flags & IFF_ALLMULTI) { | |
927 | /* Enable all multicast mode */ | |
928 | macb_writel(bp, HRB, -1); | |
929 | macb_writel(bp, HRT, -1); | |
930 | cfg |= MACB_BIT(NCFGR_MTI); | |
931 | } else if (dev->mc_count > 0) { | |
932 | /* Enable specific multicasts */ | |
933 | macb_sethashtable(dev); | |
934 | cfg |= MACB_BIT(NCFGR_MTI); | |
935 | } else if (dev->flags & (~IFF_ALLMULTI)) { | |
936 | /* Disable all multicast mode */ | |
937 | macb_writel(bp, HRB, 0); | |
938 | macb_writel(bp, HRT, 0); | |
939 | cfg &= ~MACB_BIT(NCFGR_MTI); | |
940 | } | |
941 | ||
942 | macb_writel(bp, NCFGR, cfg); | |
943 | } | |
944 | ||
89e5785f HS |
945 | static int macb_open(struct net_device *dev) |
946 | { | |
947 | struct macb *bp = netdev_priv(dev); | |
948 | int err; | |
949 | ||
950 | dev_dbg(&bp->pdev->dev, "open\n"); | |
951 | ||
6c36a707 R |
952 | /* if the phy is not yet register, retry later*/ |
953 | if (!bp->phy_dev) | |
954 | return -EAGAIN; | |
955 | ||
89e5785f HS |
956 | if (!is_valid_ether_addr(dev->dev_addr)) |
957 | return -EADDRNOTAVAIL; | |
958 | ||
959 | err = macb_alloc_consistent(bp); | |
960 | if (err) { | |
961 | printk(KERN_ERR | |
962 | "%s: Unable to allocate DMA memory (error %d)\n", | |
963 | dev->name, err); | |
964 | return err; | |
965 | } | |
966 | ||
bea3348e SH |
967 | napi_enable(&bp->napi); |
968 | ||
89e5785f HS |
969 | macb_init_rings(bp); |
970 | macb_init_hw(bp); | |
89e5785f | 971 | |
6c36a707 R |
972 | /* schedule a link state check */ |
973 | phy_start(bp->phy_dev); | |
89e5785f | 974 | |
6c36a707 | 975 | netif_start_queue(dev); |
89e5785f HS |
976 | |
977 | return 0; | |
978 | } | |
979 | ||
980 | static int macb_close(struct net_device *dev) | |
981 | { | |
982 | struct macb *bp = netdev_priv(dev); | |
983 | unsigned long flags; | |
984 | ||
89e5785f | 985 | netif_stop_queue(dev); |
bea3348e | 986 | napi_disable(&bp->napi); |
89e5785f | 987 | |
6c36a707 R |
988 | if (bp->phy_dev) |
989 | phy_stop(bp->phy_dev); | |
990 | ||
89e5785f HS |
991 | spin_lock_irqsave(&bp->lock, flags); |
992 | macb_reset_hw(bp); | |
993 | netif_carrier_off(dev); | |
994 | spin_unlock_irqrestore(&bp->lock, flags); | |
995 | ||
996 | macb_free_consistent(bp); | |
997 | ||
998 | return 0; | |
999 | } | |
1000 | ||
1001 | static struct net_device_stats *macb_get_stats(struct net_device *dev) | |
1002 | { | |
1003 | struct macb *bp = netdev_priv(dev); | |
1004 | struct net_device_stats *nstat = &bp->stats; | |
1005 | struct macb_stats *hwstat = &bp->hw_stats; | |
1006 | ||
6c36a707 R |
1007 | /* read stats from hardware */ |
1008 | macb_update_stats(bp); | |
1009 | ||
89e5785f HS |
1010 | /* Convert HW stats into netdevice stats */ |
1011 | nstat->rx_errors = (hwstat->rx_fcs_errors + | |
1012 | hwstat->rx_align_errors + | |
1013 | hwstat->rx_resource_errors + | |
1014 | hwstat->rx_overruns + | |
1015 | hwstat->rx_oversize_pkts + | |
1016 | hwstat->rx_jabbers + | |
1017 | hwstat->rx_undersize_pkts + | |
1018 | hwstat->sqe_test_errors + | |
1019 | hwstat->rx_length_mismatch); | |
1020 | nstat->tx_errors = (hwstat->tx_late_cols + | |
1021 | hwstat->tx_excessive_cols + | |
1022 | hwstat->tx_underruns + | |
1023 | hwstat->tx_carrier_errors); | |
1024 | nstat->collisions = (hwstat->tx_single_cols + | |
1025 | hwstat->tx_multiple_cols + | |
1026 | hwstat->tx_excessive_cols); | |
1027 | nstat->rx_length_errors = (hwstat->rx_oversize_pkts + | |
1028 | hwstat->rx_jabbers + | |
1029 | hwstat->rx_undersize_pkts + | |
1030 | hwstat->rx_length_mismatch); | |
1031 | nstat->rx_over_errors = hwstat->rx_resource_errors; | |
1032 | nstat->rx_crc_errors = hwstat->rx_fcs_errors; | |
1033 | nstat->rx_frame_errors = hwstat->rx_align_errors; | |
1034 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
1035 | /* XXX: What does "missed" mean? */ | |
1036 | nstat->tx_aborted_errors = hwstat->tx_excessive_cols; | |
1037 | nstat->tx_carrier_errors = hwstat->tx_carrier_errors; | |
1038 | nstat->tx_fifo_errors = hwstat->tx_underruns; | |
1039 | /* Don't know about heartbeat or window errors... */ | |
1040 | ||
1041 | return nstat; | |
1042 | } | |
1043 | ||
1044 | static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1045 | { | |
1046 | struct macb *bp = netdev_priv(dev); | |
6c36a707 R |
1047 | struct phy_device *phydev = bp->phy_dev; |
1048 | ||
1049 | if (!phydev) | |
1050 | return -ENODEV; | |
89e5785f | 1051 | |
6c36a707 | 1052 | return phy_ethtool_gset(phydev, cmd); |
89e5785f HS |
1053 | } |
1054 | ||
1055 | static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1056 | { | |
1057 | struct macb *bp = netdev_priv(dev); | |
6c36a707 | 1058 | struct phy_device *phydev = bp->phy_dev; |
89e5785f | 1059 | |
6c36a707 R |
1060 | if (!phydev) |
1061 | return -ENODEV; | |
1062 | ||
1063 | return phy_ethtool_sset(phydev, cmd); | |
89e5785f HS |
1064 | } |
1065 | ||
6c36a707 R |
1066 | static void macb_get_drvinfo(struct net_device *dev, |
1067 | struct ethtool_drvinfo *info) | |
89e5785f HS |
1068 | { |
1069 | struct macb *bp = netdev_priv(dev); | |
1070 | ||
1071 | strcpy(info->driver, bp->pdev->dev.driver->name); | |
1072 | strcpy(info->version, "$Revision: 1.14 $"); | |
1073 | strcpy(info->bus_info, bp->pdev->dev.bus_id); | |
1074 | } | |
1075 | ||
89e5785f HS |
1076 | static struct ethtool_ops macb_ethtool_ops = { |
1077 | .get_settings = macb_get_settings, | |
1078 | .set_settings = macb_set_settings, | |
1079 | .get_drvinfo = macb_get_drvinfo, | |
89e5785f HS |
1080 | .get_link = ethtool_op_get_link, |
1081 | }; | |
1082 | ||
1083 | static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1084 | { | |
1085 | struct macb *bp = netdev_priv(dev); | |
6c36a707 | 1086 | struct phy_device *phydev = bp->phy_dev; |
89e5785f HS |
1087 | |
1088 | if (!netif_running(dev)) | |
1089 | return -EINVAL; | |
1090 | ||
6c36a707 R |
1091 | if (!phydev) |
1092 | return -ENODEV; | |
89e5785f | 1093 | |
6c36a707 | 1094 | return phy_mii_ioctl(phydev, if_mii(rq), cmd); |
89e5785f HS |
1095 | } |
1096 | ||
06c3fd6a | 1097 | static int __init macb_probe(struct platform_device *pdev) |
89e5785f HS |
1098 | { |
1099 | struct eth_platform_data *pdata; | |
1100 | struct resource *regs; | |
1101 | struct net_device *dev; | |
1102 | struct macb *bp; | |
6c36a707 | 1103 | struct phy_device *phydev; |
89e5785f HS |
1104 | unsigned long pclk_hz; |
1105 | u32 config; | |
1106 | int err = -ENXIO; | |
0795af57 | 1107 | DECLARE_MAC_BUF(mac); |
89e5785f HS |
1108 | |
1109 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1110 | if (!regs) { | |
1111 | dev_err(&pdev->dev, "no mmio resource defined\n"); | |
1112 | goto err_out; | |
1113 | } | |
1114 | ||
1115 | err = -ENOMEM; | |
1116 | dev = alloc_etherdev(sizeof(*bp)); | |
1117 | if (!dev) { | |
1118 | dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n"); | |
1119 | goto err_out; | |
1120 | } | |
1121 | ||
89e5785f HS |
1122 | SET_NETDEV_DEV(dev, &pdev->dev); |
1123 | ||
1124 | /* TODO: Actually, we have some interesting features... */ | |
1125 | dev->features |= 0; | |
1126 | ||
1127 | bp = netdev_priv(dev); | |
1128 | bp->pdev = pdev; | |
1129 | bp->dev = dev; | |
1130 | ||
1131 | spin_lock_init(&bp->lock); | |
1132 | ||
0cc8674f AV |
1133 | #if defined(CONFIG_ARCH_AT91) |
1134 | bp->pclk = clk_get(&pdev->dev, "macb_clk"); | |
1135 | if (IS_ERR(bp->pclk)) { | |
1136 | dev_err(&pdev->dev, "failed to get macb_clk\n"); | |
1137 | goto err_out_free_dev; | |
1138 | } | |
1139 | clk_enable(bp->pclk); | |
1140 | #else | |
89e5785f HS |
1141 | bp->pclk = clk_get(&pdev->dev, "pclk"); |
1142 | if (IS_ERR(bp->pclk)) { | |
1143 | dev_err(&pdev->dev, "failed to get pclk\n"); | |
1144 | goto err_out_free_dev; | |
1145 | } | |
1146 | bp->hclk = clk_get(&pdev->dev, "hclk"); | |
1147 | if (IS_ERR(bp->hclk)) { | |
1148 | dev_err(&pdev->dev, "failed to get hclk\n"); | |
1149 | goto err_out_put_pclk; | |
1150 | } | |
1151 | ||
1152 | clk_enable(bp->pclk); | |
1153 | clk_enable(bp->hclk); | |
0cc8674f | 1154 | #endif |
89e5785f HS |
1155 | |
1156 | bp->regs = ioremap(regs->start, regs->end - regs->start + 1); | |
1157 | if (!bp->regs) { | |
1158 | dev_err(&pdev->dev, "failed to map registers, aborting.\n"); | |
1159 | err = -ENOMEM; | |
1160 | goto err_out_disable_clocks; | |
1161 | } | |
1162 | ||
1163 | dev->irq = platform_get_irq(pdev, 0); | |
38515e90 | 1164 | err = request_irq(dev->irq, macb_interrupt, IRQF_SAMPLE_RANDOM, |
89e5785f HS |
1165 | dev->name, dev); |
1166 | if (err) { | |
1167 | printk(KERN_ERR | |
1168 | "%s: Unable to request IRQ %d (error %d)\n", | |
1169 | dev->name, dev->irq, err); | |
1170 | goto err_out_iounmap; | |
1171 | } | |
1172 | ||
1173 | dev->open = macb_open; | |
1174 | dev->stop = macb_close; | |
1175 | dev->hard_start_xmit = macb_start_xmit; | |
1176 | dev->get_stats = macb_get_stats; | |
446ebd01 | 1177 | dev->set_multicast_list = macb_set_rx_mode; |
89e5785f | 1178 | dev->do_ioctl = macb_ioctl; |
bea3348e | 1179 | netif_napi_add(dev, &bp->napi, macb_poll, 64); |
89e5785f HS |
1180 | dev->ethtool_ops = &macb_ethtool_ops; |
1181 | ||
1182 | dev->base_addr = regs->start; | |
1183 | ||
89e5785f HS |
1184 | /* Set MII management clock divider */ |
1185 | pclk_hz = clk_get_rate(bp->pclk); | |
1186 | if (pclk_hz <= 20000000) | |
1187 | config = MACB_BF(CLK, MACB_CLK_DIV8); | |
1188 | else if (pclk_hz <= 40000000) | |
1189 | config = MACB_BF(CLK, MACB_CLK_DIV16); | |
1190 | else if (pclk_hz <= 80000000) | |
1191 | config = MACB_BF(CLK, MACB_CLK_DIV32); | |
1192 | else | |
1193 | config = MACB_BF(CLK, MACB_CLK_DIV64); | |
1194 | macb_writel(bp, NCFGR, config); | |
1195 | ||
89e5785f | 1196 | macb_get_hwaddr(bp); |
89e5785f | 1197 | pdata = pdev->dev.platform_data; |
6c36a707 | 1198 | |
89e5785f | 1199 | if (pdata && pdata->is_rmii) |
0cc8674f AV |
1200 | #if defined(CONFIG_ARCH_AT91) |
1201 | macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) ); | |
1202 | #else | |
89e5785f | 1203 | macb_writel(bp, USRIO, 0); |
0cc8674f | 1204 | #endif |
89e5785f | 1205 | else |
0cc8674f AV |
1206 | #if defined(CONFIG_ARCH_AT91) |
1207 | macb_writel(bp, USRIO, MACB_BIT(CLKEN)); | |
1208 | #else | |
89e5785f | 1209 | macb_writel(bp, USRIO, MACB_BIT(MII)); |
0cc8674f | 1210 | #endif |
89e5785f HS |
1211 | |
1212 | bp->tx_pending = DEF_TX_RING_PENDING; | |
1213 | ||
1214 | err = register_netdev(dev); | |
1215 | if (err) { | |
1216 | dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); | |
1217 | goto err_out_free_irq; | |
1218 | } | |
1219 | ||
6c36a707 R |
1220 | if (macb_mii_init(bp) != 0) { |
1221 | goto err_out_unregister_netdev; | |
1222 | } | |
89e5785f | 1223 | |
6c36a707 | 1224 | platform_set_drvdata(pdev, dev); |
89e5785f HS |
1225 | |
1226 | printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d " | |
0795af57 | 1227 | "(%s)\n", |
89e5785f | 1228 | dev->name, dev->base_addr, dev->irq, |
0795af57 | 1229 | print_mac(mac, dev->dev_addr)); |
89e5785f | 1230 | |
6c36a707 R |
1231 | phydev = bp->phy_dev; |
1232 | printk(KERN_INFO "%s: attached PHY driver [%s] " | |
1233 | "(mii_bus:phy_addr=%s, irq=%d)\n", | |
1234 | dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq); | |
1235 | ||
89e5785f HS |
1236 | return 0; |
1237 | ||
6c36a707 R |
1238 | err_out_unregister_netdev: |
1239 | unregister_netdev(dev); | |
89e5785f HS |
1240 | err_out_free_irq: |
1241 | free_irq(dev->irq, dev); | |
1242 | err_out_iounmap: | |
1243 | iounmap(bp->regs); | |
1244 | err_out_disable_clocks: | |
0cc8674f | 1245 | #ifndef CONFIG_ARCH_AT91 |
89e5785f | 1246 | clk_disable(bp->hclk); |
89e5785f | 1247 | clk_put(bp->hclk); |
0cc8674f AV |
1248 | #endif |
1249 | clk_disable(bp->pclk); | |
6c36a707 | 1250 | #ifndef CONFIG_ARCH_AT91 |
89e5785f | 1251 | err_out_put_pclk: |
6c36a707 | 1252 | #endif |
89e5785f HS |
1253 | clk_put(bp->pclk); |
1254 | err_out_free_dev: | |
1255 | free_netdev(dev); | |
1256 | err_out: | |
1257 | platform_set_drvdata(pdev, NULL); | |
1258 | return err; | |
1259 | } | |
1260 | ||
06c3fd6a | 1261 | static int __exit macb_remove(struct platform_device *pdev) |
89e5785f HS |
1262 | { |
1263 | struct net_device *dev; | |
1264 | struct macb *bp; | |
1265 | ||
1266 | dev = platform_get_drvdata(pdev); | |
1267 | ||
1268 | if (dev) { | |
1269 | bp = netdev_priv(dev); | |
84b7901f AN |
1270 | if (bp->phy_dev) |
1271 | phy_disconnect(bp->phy_dev); | |
298cf9be LB |
1272 | mdiobus_unregister(bp->mii_bus); |
1273 | kfree(bp->mii_bus->irq); | |
1274 | mdiobus_free(bp->mii_bus); | |
89e5785f HS |
1275 | unregister_netdev(dev); |
1276 | free_irq(dev->irq, dev); | |
1277 | iounmap(bp->regs); | |
0cc8674f | 1278 | #ifndef CONFIG_ARCH_AT91 |
89e5785f | 1279 | clk_disable(bp->hclk); |
89e5785f | 1280 | clk_put(bp->hclk); |
0cc8674f AV |
1281 | #endif |
1282 | clk_disable(bp->pclk); | |
89e5785f HS |
1283 | clk_put(bp->pclk); |
1284 | free_netdev(dev); | |
1285 | platform_set_drvdata(pdev, NULL); | |
1286 | } | |
1287 | ||
1288 | return 0; | |
1289 | } | |
1290 | ||
c1f598fd HS |
1291 | #ifdef CONFIG_PM |
1292 | static int macb_suspend(struct platform_device *pdev, pm_message_t state) | |
1293 | { | |
1294 | struct net_device *netdev = platform_get_drvdata(pdev); | |
1295 | struct macb *bp = netdev_priv(netdev); | |
1296 | ||
1297 | netif_device_detach(netdev); | |
1298 | ||
1299 | #ifndef CONFIG_ARCH_AT91 | |
1300 | clk_disable(bp->hclk); | |
1301 | #endif | |
1302 | clk_disable(bp->pclk); | |
1303 | ||
1304 | return 0; | |
1305 | } | |
1306 | ||
1307 | static int macb_resume(struct platform_device *pdev) | |
1308 | { | |
1309 | struct net_device *netdev = platform_get_drvdata(pdev); | |
1310 | struct macb *bp = netdev_priv(netdev); | |
1311 | ||
1312 | clk_enable(bp->pclk); | |
1313 | #ifndef CONFIG_ARCH_AT91 | |
1314 | clk_enable(bp->hclk); | |
1315 | #endif | |
1316 | ||
1317 | netif_device_attach(netdev); | |
1318 | ||
1319 | return 0; | |
1320 | } | |
1321 | #else | |
1322 | #define macb_suspend NULL | |
1323 | #define macb_resume NULL | |
1324 | #endif | |
1325 | ||
89e5785f | 1326 | static struct platform_driver macb_driver = { |
06c3fd6a | 1327 | .remove = __exit_p(macb_remove), |
c1f598fd HS |
1328 | .suspend = macb_suspend, |
1329 | .resume = macb_resume, | |
89e5785f HS |
1330 | .driver = { |
1331 | .name = "macb", | |
72abb461 | 1332 | .owner = THIS_MODULE, |
89e5785f HS |
1333 | }, |
1334 | }; | |
1335 | ||
1336 | static int __init macb_init(void) | |
1337 | { | |
06c3fd6a | 1338 | return platform_driver_probe(&macb_driver, macb_probe); |
89e5785f HS |
1339 | } |
1340 | ||
1341 | static void __exit macb_exit(void) | |
1342 | { | |
1343 | platform_driver_unregister(&macb_driver); | |
1344 | } | |
1345 | ||
1346 | module_init(macb_init); | |
1347 | module_exit(macb_exit); | |
1348 | ||
1349 | MODULE_LICENSE("GPL"); | |
1350 | MODULE_DESCRIPTION("Atmel MACB Ethernet driver"); | |
1351 | MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>"); | |
72abb461 | 1352 | MODULE_ALIAS("platform:macb"); |